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fix: fix chiplets bus
1 parent 766292d commit 0cbcaee

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2 files changed

+18
-3
lines changed

2 files changed

+18
-3
lines changed

processor/src/chiplets/aux_trace/mod.rs

+1-2
Original file line numberDiff line numberDiff line change
@@ -63,8 +63,7 @@ impl AuxTraceBuilder {
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let b_chip = bus_col_builder.build_aux_column(main_trace, rand_elements);
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debug_assert_eq!(*t_chip.last().unwrap(), E::ONE);
66-
// TODO: Fix and re-enable after testing with miden-base
67-
// debug_assert_eq!(*b_chip.last().unwrap(), E::ONE);
66+
debug_assert_eq!(*b_chip.last().unwrap(), E::ONE);
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vec![t_chip, b_chip]
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}
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}

test-utils/src/lib.rs

+17-1
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@ pub use vm_core::{
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Felt, FieldElement, StackInputs, StackOutputs, StarkField, Word, EMPTY_WORD, ONE, WORD_SIZE,
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ZERO,
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};
37+
use winter_prover::Trace;
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pub mod math {
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pub use winter_prover::math::{
@@ -343,7 +344,22 @@ impl Test {
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for library in &self.libraries {
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host.load_mast_forest(library.mast_forest().clone());
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}
346-
processor::execute(&program, self.stack_inputs.clone(), host, ExecutionOptions::default())
347+
let main_trace = processor::execute(
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&program,
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self.stack_inputs.clone(),
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host,
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ExecutionOptions::default(),
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)?;
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354+
// Build the auxiliary trace too to run the debug assertions
355+
let rand_elements: Vec<_> = {
356+
let num_rand_elements = main_trace.info().get_num_aux_segment_rand_elements();
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358+
(0..num_rand_elements).map(|i| Felt::from((i + 1) as u32)).collect()
359+
};
360+
let _aux_trace = main_trace.build_aux_trace(&rand_elements);
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362+
Ok(main_trace)
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}
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/// Compiles the test's source to a Program and executes it with the tests inputs. Returns the

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