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Add intrinsics for the new FP conversions introduced by the 2024 dpISA
FEAT_FPRCVT adds 4 new variants for each FCVTAS, FCVTAU, FCVTMS, FCVTMU,
FCVTNS, FCVTNU, FCVTPS, FCVTPU, FCVTZS, and FCVTZU instruction.
1) Half Precision to 32-bit
2) Half Precision to 64-bit
3) Single Precision to 64-bit
4) Double Precision to 32-bit
For the Single Precision to 64-bit and Double Precision to 32-bit variants,
this patch adds two new intrinsics, that reduce to
- Single Precision to 64-bit : <INST> Dd,Sn
- Double Precision to 32-bit : <INST> Sd,Dn
The intrinsics for conversions from Half Precision are already defined.
However they are documented as reducing to the incorrect instruction format;
<INST> Hd,Hn, so this patch fixes them to be
- Half Precision to 32-bit : <INST> Sd,Hn
- Half Precision to 64-bit : <INST> Dd,Hn
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