All notable changes to this project will be documented in this file.
The format is based on Keep a Changelog and this project adheres to Semantic Versioning.
- Add support for virtually-indexed addressing
- Fix forwarding logic of uncacheable Icache response in the cva6 cache subsystem.
- Fix wrong mask signal when implementing the MSHR in registers
- Add additional configuration to implement MSHR in registers (when the number of entries is low)
- Fix cache data SRAM chip-select generation when word width is different than 64 bits (e.g. 32 bits)
- Add parameters in the HPDcache module to define the types of interfaces to the memory
- Add helper verilog header file with macros to ease the type definition of interfaces to the memory
- Add new event signals in the HPDCache top module
- Add generic single-port RAM macros with byte-enable signals
- Add parameters in the package to choose between RAM macros implementing byte-enable or bitmask for the different RAMs instances
- Add additional assertions to verify parameters
- Add additional configuration signal to inhibit write coalescing in the write buffer
- Remove base_id ports in the HPDCache top module
- Remove nettype (wire,var) in ports as it looks like is badly supported in some cases by some simulation tools
- Split the hpdcache_pkg into: (1) the hpdcache_pkg contains internally defined parameters; (2) a new hpdcache_params_pkg that defines user parameters
- New selection policy of ready requests in the replay table. It gives priority to requests in the same linked list.
- The write buffer now accepts writes from requesters in a pending slot when it is waiting for the internal arbiter to forward the data to the NoC.
- Correctly support HPDCACHE_ACCESS_WORDS=1
- Correctly support HPDCACHE_ACCESS_WORDS=HPDCACHE_CL_WORDS
- Fix width of the nlines count register in the HW memory prefetcher.
- Initial release to the OpenHW Group