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vivado_2416.backup.log
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vivado_2416.backup.log
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#-----------------------------------------------------------
# Vivado v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Mon Jun 12 00:12:38 2023
# Process ID: 2416
# Current directory: E:/Xilinx/Projects/Nano Processor Final
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent8308 E:\Xilinx\Projects\Nano Processor Final\Nano Processor Final.xpr
# Log file: E:/Xilinx/Projects/Nano Processor Final/vivado.log
# Journal file: E:/Xilinx/Projects/Nano Processor Final\vivado.jou
#-----------------------------------------------------------
start_gui
open_project {E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.xpr}
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2018.2/data/ip'.
open_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:20 . Memory (MB): peak = 812.996 ; gain = 91.195
update_compile_order -fileset sources_1
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'System_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj System_TB_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '5' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: E:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 67a5dd7157414ed9814149af3173682b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot System_TB_behav xil_defaultlib.System_TB -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.LUT_16_7 [lut_16_7_default]
Compiling architecture behavioral of entity xil_defaultlib.Slow_Clock [slow_clock_default]
Compiling architecture behavioral of entity xil_defaultlib.Reg_3bit [reg_3bit_default]
Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default]
Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default]
Compiling architecture behavioral of entity xil_defaultlib.Adder_3bit [adder_3bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Mux_2_to_1_3bit [mux_2_to_1_3bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Program_ROM [program_rom_default]
Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default]
Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default]
Compiling architecture behavioral of entity xil_defaultlib.Mux_2_to_1_4bit [mux_2_to_1_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Reg_4bit [reg_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Decoder_3_to_8 [decoder_3_to_8_default]
Compiling architecture behavioral of entity xil_defaultlib.Register_Bank [register_bank_default]
Compiling architecture behavioral of entity xil_defaultlib.Mux_8_to_1_4bit [mux_8_to_1_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.ASU_4bit [asu_4bit_default]
Compiling architecture behavioral of entity xil_defaultlib.Nano_Processor [nano_processor_default]
Compiling architecture behavioral of entity xil_defaultlib.System [system_default]
Compiling architecture behavioral of entity xil_defaultlib.system_tb
Built simulation snapshot System_TB_behav
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 820.969 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '8' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'E:/Xilinx/Projects/Nano Processor Final/Nano Processor Final.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "System_TB_behav -key {Behavioral:sim_1:Functional:System_TB} -tclbatch {System_TB.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2018.2
Time resolution is 1 ps
source System_TB.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
xsim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 835.758 ; gain = 7.188
INFO: [USF-XSim-96] XSim completed. Design snapshot 'System_TB_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:25 . Memory (MB): peak = 835.758 ; gain = 14.789
close_sim
INFO: [Simtcl 6-16] Simulation closed
close_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 847.969 ; gain = 0.000
exit
INFO: [Common 17-206] Exiting Vivado at Mon Jun 12 01:07:52 2023...