From b5b06caa8fab008e4041fda99e0339b843d5065e Mon Sep 17 00:00:00 2001 From: Hormoz Zarnani Date: Tue, 25 Jun 2024 22:58:45 -0700 Subject: [PATCH] Atmosic ATM33 Platform f8c606ae20452ba6df087224da81ee226eea78b1 Change-Id: Ib140fe5bdd1444c0813a1c4b853fcc05a56d860f --- ATM33xx-5/CMakeLists.txt | 22 + ATM33xx-5/config/atm33-mbedtls-config.h | 45 + ATM33xx-5/drivers/CMakeLists.txt | 120 + ATM33xx-5/drivers/Kconfig | 28 + ATM33xx-5/drivers/at_tz_mpc/at_tz_mpc.c | 250 + ATM33xx-5/drivers/at_tz_mpc/at_tz_mpc.h | 215 + ATM33xx-5/drivers/atm_aes/aes_alt.c | 138 + ATM33xx-5/drivers/atm_aes/atm_aes.c | 170 + ATM33xx-5/drivers/atm_aes/atm_aes.h | 118 + ATM33xx-5/drivers/atm_bp_clock/atm_bp_clock.c | 83 + ATM33xx-5/drivers/atm_bp_clock/atm_bp_clock.h | 105 + ATM33xx-5/drivers/atm_sha2/atm_sha2.c | 669 + ATM33xx-5/drivers/atm_sha2/atm_sha2.h | 286 + ATM33xx-5/drivers/atm_sha2/sha256_alt.c | 100 + ATM33xx-5/drivers/atm_sha2/sha256_alt.h | 25 + ATM33xx-5/drivers/atmwstk/atmwstk.c | 96 + ATM33xx-5/drivers/atmwstk/atmwstk.h | 68 + .../drivers/atmwstk/atmwstk_CPD200_sha.h | 16 + ATM33xx-5/drivers/atmwstk/atmwstk_PD100_sha.h | 16 + ATM33xx-5/drivers/atmwstk/atmwstk_PD150_sha.h | 16 + ATM33xx-5/drivers/dma/dma.h | 109 + ATM33xx-5/drivers/micro-ecc/ecdsa_alt.c | 263 + ATM33xx-5/drivers/rep_vec/rep_vec.h | 517 + ATM33xx-5/drivers/reset/reset.c | 228 + ATM33xx-5/drivers/reset/reset.h | 226 + .../drivers/rram_rom_prot/rram_rom_prot.c | 212 + .../drivers/rram_rom_prot/rram_rom_prot.h | 162 + ATM33xx-5/drivers/sec_cache/sec_cache.c | 68 + ATM33xx-5/drivers/sec_cache/sec_cache.h | 73 + .../drivers/sec_dev_lockout/sec_dev_lockout.c | 56 + .../drivers/sec_dev_lockout/sec_dev_lockout.h | 140 + ATM33xx-5/drivers/sec_jrnl/sec_jrnl.c | 364 + ATM33xx-5/drivers/sec_jrnl/sec_jrnl.h | 180 + ATM33xx-5/drivers/sec_reset/sec_reset.c | 99 + ATM33xx-5/drivers/sec_reset/sec_reset.h | 66 + ATM33xx-5/drivers/spi/qspi.h | 220 + ATM33xx-5/drivers/spi/spi.c | 211 + ATM33xx-5/drivers/spi/spi.h | 271 + ATM33xx-5/drivers/spi/spi_flash.c | 214 + ATM33xx-5/drivers/spi/spi_flash.h | 182 + ATM33xx-5/drivers/spi/spi_multi.c | 122 + ATM33xx-5/drivers/spi/spi_multi.h | 49 + ATM33xx-5/drivers/timer/timer.h | 305 + ATM33xx-5/drivers/trng/trng_internal.h | 199 + ATM33xx-5/drivers/user_debug.c | 174 + ATM33xx-5/drivers/workarounds/workarounds.c | 292 + ATM33xx-5/drivers/workarounds/workarounds.h | 41 + ATM33xx-5/examples/spe/CMakeLists.txt | 20 + ATM33xx-5/examples/spe/Kconfig | 13 + ATM33xx-5/examples/spe/prj.conf | 24 + ATM33xx-5/examples/spe/sample.yaml | 7 + .../spe/src/cust_sec_func/cust_sec_func.c | 34 + .../spe/src/cust_sec_func/cust_sec_func.h | 18 + ATM33xx-5/examples/spe/src/main.c | 309 + ATM33xx-5/include/arch.h | 638 + ATM33xx-5/include/arm/ARMv8MBL.h | 4152 ++++ ATM33xx-5/include/arm/system_ARMv8MBL.h | 64 + ATM33xx-5/include/armgcc/compiler.h | 150 + ATM33xx-5/include/at_tz_ppc.h | 446 + ATM33xx-5/include/at_tz_sau.h | 194 + ATM33xx-5/include/calibration.h | 181 + ATM33xx-5/include/iccarm/compiler.h | 122 + ATM33xx-5/include/ll.h | 125 + ATM33xx-5/include/pseq_status.h | 35 + .../include/reg/at_ahb_dma_regs_core_macro.h | 4650 +++++ .../include/reg/at_ahb_prrf_regs_core_macro.h | 3446 ++++ .../include/reg/at_ahb_sha2_regs_core_macro.h | 1684 ++ .../include/reg/at_apb_aes_regs_core_macro.h | 1918 ++ .../reg/at_apb_clkrstgen_regs_core_macro.h | 1382 ++ .../include/reg/at_apb_gadc_regs_core_macro.h | 2285 +++ .../include/reg/at_apb_i2c_regs_core_macro.h | 1079 ++ .../include/reg/at_apb_ksm_regs_core_macro.h | 1112 ++ .../include/reg/at_apb_pdm_regs_core_macro.h | 2159 +++ .../include/reg/at_apb_pseq_regs_core_macro.h | 14423 ++++++++++++++ .../include/reg/at_apb_pwm_regs_core_macro.h | 3570 ++++ .../include/reg/at_apb_qdec_regs_core_macro.h | 1100 ++ .../include/reg/at_apb_qspi_regs_core_macro.h | 1844 ++ .../reg/at_apb_rcos_cal_regs_core_macro.h | 672 + .../include/reg/at_apb_shub_regs_core_macro.h | 13794 +++++++++++++ .../reg/at_apb_slwtimer_regs_core_macro.h | 970 + .../include/reg/at_apb_spi_regs_core_macro.h | 1574 ++ .../include/reg/at_apb_swd_regs_core_macro.h | 1238 ++ .../include/reg/at_apb_trng_regs_core_macro.h | 571 + .../reg/at_apb_tsmc_nvm_regs_core_macro.h | 1162 ++ .../include/reg/at_apb_uart_regs_core_macro.h | 2486 +++ .../reg/at_apb_wrpr_pins_regs_core_macro.h | 5911 ++++++ .../reg/at_apb_wrpr_short_regs_core_macro.h | 1854 ++ ATM33xx-5/include/reg/at_clkrstgen.h | 485 + .../include/reg/at_i2s_regs_core_macro.h | 5591 ++++++ ATM33xx-5/include/reg/at_lc_regs_core_macro.h | 8108 ++++++++ ATM33xx-5/include/reg/at_pinmux.h | 1676 ++ ATM33xx-5/include/reg/at_wrpr.h | 222 + ATM33xx-5/include/reg/base_addr.h | 1280 ++ .../include/reg/base_addr_place_holders.h | 69 + ATM33xx-5/include/reg/base_addr_utils.h | 1499 ++ ATM33xx-5/include/reg/mdm_macro.h | 15938 ++++++++++++++++ ATM33xx-5/include/reg/pll_regs_core_macro.h | 713 + .../include/reg/pmu_gadc_regs_core_macro.h | 482 + .../include/reg/pmu_pmuadc_regs_core_macro.h | 1854 ++ ATM33xx-5/include/reg/pmu_spi.h | 132 + .../include/reg/pmu_swreg_regs_core_macro.h | 2020 ++ .../include/reg/pmu_top_regs_core_macro.h | 13030 +++++++++++++ .../include/reg/pmu_wurx_regs_core_macro.h | 2165 +++ ATM33xx-5/include/reg/pseq_states.h | 205 + .../include/reg/radio_rx_regs_core_macro.h | 2973 +++ ATM33xx-5/include/reg/radio_spi.h | 58 + .../include/reg/radio_synth_regs_core_macro.h | 2185 +++ .../include/reg/radio_top_regs_core_macro.h | 1599 ++ ATM33xx-5/include/reg/rif_regs_core_macro.h | 8632 +++++++++ ATM33xx-5/include/reg/rram.h | 130 + .../include/reg/swreg_aon_regs_core_macro.h | 2175 +++ .../include/reg/swreg_main_regs_core_macro.h | 2912 +++ .../reg/swreg_simple_regs_core_macro.h | 464 + ATM33xx-5/include/test_common.h | 120 + ATM33xx-5/include/vectors.h | 144 + ATM33xx-5/lib/CMakeLists.txt | 49 + ATM33xx-5/lib/Kconfig | 28 + ATM33xx-5/lib/at_cmd/at_cmd.c | 522 + ATM33xx-5/lib/at_cmd/at_cmd.h | 262 + ATM33xx-5/lib/at_cmd/at_cmd_pasr.c | 466 + ATM33xx-5/lib/at_cmd/at_cmd_pasr.h | 255 + ATM33xx-5/lib/atm_asm/CMakeLists.txt | 13 + ATM33xx-5/lib/atm_asm/Kconfig | 7 + ATM33xx-5/lib/atm_asm/atm_asm.c | 184 + ATM33xx-5/lib/atm_asm/atm_asm.h | 163 + ATM33xx-5/lib/atm_utils_c/atm_utils_c.h | 247 + ATM33xx-5/lib/atm_utils_math/atm_utils_math.h | 171 + ATM33xx-5/lib/atm_utils_reg/atm_utils_reg.c | 97 + ATM33xx-5/lib/atm_utils_reg/atm_utils_reg.h | 92 + ATM33xx-5/lib/atm_vendor/CMakeLists.txt | 59 + ATM33xx-5/lib/atm_vendor/Kconfig | 96 + ATM33xx-5/lib/atm_vendor/atm_hci_uart.c | 461 + ATM33xx-5/lib/atm_vendor/atm_hci_uart.h | 61 + ATM33xx-5/lib/atm_vendor/atm_vendor.c | 1727 ++ ATM33xx-5/lib/atm_vendor/atm_vendor.h | 80 + .../lib/atm_vendor/atm_vendor_internal.h | 556 + ATM33xx-5/lib/sec_service/sec_service.c | 134 + ATM33xx-5/lib/sec_service/sec_service.h | 79 + ATM33xx-5/noinit.ld | 7 + ATM33xx-5/ramfunc-section.ld | 7 + CMakeLists.txt | 9 + Kconfig | 21 + tools/Kconfig | 11 + tools/scripts/atm_openocd.py | 177 + tools/scripts/atm_otp/__init__.py | 0 tools/scripts/atm_otp/atm_otp.py | 207 + tools/scripts/atm_otp/test_atm_otp.py | 92 + tools/scripts/gen_atm_partition_info.py | 640 + tools/scripts/sec_jrnl_tlv/__init__.py | 0 tools/scripts/sec_jrnl_tlv/sec_jrnl_tlv.py | 351 + .../scripts/sec_jrnl_tlv/test_sec_jrnl_tlv.py | 152 + west/__init__.py | 0 west/atm_arch_extension.py | 379 + west/atm_otp_west_extension.py | 178 + west/atm_west_utils.py | 37 + west/sec_jrnl_west_extension.py | 290 + west/tests/__init__.py | 0 west/tests/test_atm_arch_west_extension.py | 154 + west/tests/test_atm_otp_west_extension.py | 108 + west/tests/test_sec_jrnl_west_extension.py | 143 + west/west-commands.yml | 16 + zephyr/module.yml | 7 + 162 files changed, 170701 insertions(+) create mode 100644 ATM33xx-5/CMakeLists.txt create mode 100644 ATM33xx-5/config/atm33-mbedtls-config.h create mode 100644 ATM33xx-5/drivers/CMakeLists.txt create mode 100644 ATM33xx-5/drivers/Kconfig create mode 100644 ATM33xx-5/drivers/at_tz_mpc/at_tz_mpc.c create mode 100644 ATM33xx-5/drivers/at_tz_mpc/at_tz_mpc.h create mode 100644 ATM33xx-5/drivers/atm_aes/aes_alt.c create mode 100644 ATM33xx-5/drivers/atm_aes/atm_aes.c create mode 100644 ATM33xx-5/drivers/atm_aes/atm_aes.h create mode 100644 ATM33xx-5/drivers/atm_bp_clock/atm_bp_clock.c create mode 100644 ATM33xx-5/drivers/atm_bp_clock/atm_bp_clock.h create mode 100644 ATM33xx-5/drivers/atm_sha2/atm_sha2.c create mode 100644 ATM33xx-5/drivers/atm_sha2/atm_sha2.h create mode 100644 ATM33xx-5/drivers/atm_sha2/sha256_alt.c create mode 100644 ATM33xx-5/drivers/atm_sha2/sha256_alt.h create mode 100644 ATM33xx-5/drivers/atmwstk/atmwstk.c create mode 100644 ATM33xx-5/drivers/atmwstk/atmwstk.h create mode 100644 ATM33xx-5/drivers/atmwstk/atmwstk_CPD200_sha.h create mode 100644 ATM33xx-5/drivers/atmwstk/atmwstk_PD100_sha.h create mode 100644 ATM33xx-5/drivers/atmwstk/atmwstk_PD150_sha.h create mode 100644 ATM33xx-5/drivers/dma/dma.h create mode 100644 ATM33xx-5/drivers/micro-ecc/ecdsa_alt.c create mode 100644 ATM33xx-5/drivers/rep_vec/rep_vec.h create mode 100644 ATM33xx-5/drivers/reset/reset.c create mode 100644 ATM33xx-5/drivers/reset/reset.h create mode 100644 ATM33xx-5/drivers/rram_rom_prot/rram_rom_prot.c create mode 100644 ATM33xx-5/drivers/rram_rom_prot/rram_rom_prot.h create mode 100644 ATM33xx-5/drivers/sec_cache/sec_cache.c create mode 100644 ATM33xx-5/drivers/sec_cache/sec_cache.h create mode 100644 ATM33xx-5/drivers/sec_dev_lockout/sec_dev_lockout.c create mode 100644 ATM33xx-5/drivers/sec_dev_lockout/sec_dev_lockout.h create mode 100644 ATM33xx-5/drivers/sec_jrnl/sec_jrnl.c create mode 100644 ATM33xx-5/drivers/sec_jrnl/sec_jrnl.h create mode 100644 ATM33xx-5/drivers/sec_reset/sec_reset.c create mode 100644 ATM33xx-5/drivers/sec_reset/sec_reset.h create mode 100644 ATM33xx-5/drivers/spi/qspi.h create mode 100644 ATM33xx-5/drivers/spi/spi.c create mode 100644 ATM33xx-5/drivers/spi/spi.h create mode 100644 ATM33xx-5/drivers/spi/spi_flash.c create mode 100644 ATM33xx-5/drivers/spi/spi_flash.h create mode 100644 ATM33xx-5/drivers/spi/spi_multi.c create mode 100644 ATM33xx-5/drivers/spi/spi_multi.h create mode 100644 ATM33xx-5/drivers/timer/timer.h create mode 100644 ATM33xx-5/drivers/trng/trng_internal.h create mode 100644 ATM33xx-5/drivers/user_debug.c create mode 100644 ATM33xx-5/drivers/workarounds/workarounds.c create mode 100644 ATM33xx-5/drivers/workarounds/workarounds.h create mode 100644 ATM33xx-5/examples/spe/CMakeLists.txt create mode 100644 ATM33xx-5/examples/spe/Kconfig create mode 100644 ATM33xx-5/examples/spe/prj.conf create mode 100644 ATM33xx-5/examples/spe/sample.yaml create mode 100644 ATM33xx-5/examples/spe/src/cust_sec_func/cust_sec_func.c create mode 100644 ATM33xx-5/examples/spe/src/cust_sec_func/cust_sec_func.h create mode 100644 ATM33xx-5/examples/spe/src/main.c create mode 100644 ATM33xx-5/include/arch.h create mode 100755 ATM33xx-5/include/arm/ARMv8MBL.h create mode 100644 ATM33xx-5/include/arm/system_ARMv8MBL.h create mode 100644 ATM33xx-5/include/armgcc/compiler.h create mode 100644 ATM33xx-5/include/at_tz_ppc.h create mode 100644 ATM33xx-5/include/at_tz_sau.h create mode 100644 ATM33xx-5/include/calibration.h create mode 100644 ATM33xx-5/include/iccarm/compiler.h create mode 100644 ATM33xx-5/include/ll.h create mode 100644 ATM33xx-5/include/pseq_status.h create mode 100644 ATM33xx-5/include/reg/at_ahb_dma_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_ahb_prrf_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_ahb_sha2_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_apb_aes_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_apb_clkrstgen_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_apb_gadc_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_apb_i2c_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_apb_ksm_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_apb_pdm_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_apb_pseq_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_apb_pwm_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_apb_qdec_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_apb_qspi_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_apb_rcos_cal_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_apb_shub_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_apb_slwtimer_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_apb_spi_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_apb_swd_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_apb_trng_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_apb_tsmc_nvm_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_apb_uart_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_apb_wrpr_pins_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_apb_wrpr_short_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_clkrstgen.h create mode 100644 ATM33xx-5/include/reg/at_i2s_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_lc_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/at_pinmux.h create mode 100644 ATM33xx-5/include/reg/at_wrpr.h create mode 100644 ATM33xx-5/include/reg/base_addr.h create mode 100644 ATM33xx-5/include/reg/base_addr_place_holders.h create mode 100644 ATM33xx-5/include/reg/base_addr_utils.h create mode 100644 ATM33xx-5/include/reg/mdm_macro.h create mode 100644 ATM33xx-5/include/reg/pll_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/pmu_gadc_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/pmu_pmuadc_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/pmu_spi.h create mode 100644 ATM33xx-5/include/reg/pmu_swreg_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/pmu_top_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/pmu_wurx_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/pseq_states.h create mode 100644 ATM33xx-5/include/reg/radio_rx_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/radio_spi.h create mode 100644 ATM33xx-5/include/reg/radio_synth_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/radio_top_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/rif_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/rram.h create mode 100644 ATM33xx-5/include/reg/swreg_aon_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/swreg_main_regs_core_macro.h create mode 100644 ATM33xx-5/include/reg/swreg_simple_regs_core_macro.h create mode 100644 ATM33xx-5/include/test_common.h create mode 100644 ATM33xx-5/include/vectors.h create mode 100644 ATM33xx-5/lib/CMakeLists.txt create mode 100644 ATM33xx-5/lib/Kconfig create mode 100644 ATM33xx-5/lib/at_cmd/at_cmd.c create mode 100644 ATM33xx-5/lib/at_cmd/at_cmd.h create mode 100644 ATM33xx-5/lib/at_cmd/at_cmd_pasr.c create mode 100644 ATM33xx-5/lib/at_cmd/at_cmd_pasr.h create mode 100644 ATM33xx-5/lib/atm_asm/CMakeLists.txt create mode 100644 ATM33xx-5/lib/atm_asm/Kconfig create mode 100644 ATM33xx-5/lib/atm_asm/atm_asm.c create mode 100644 ATM33xx-5/lib/atm_asm/atm_asm.h create mode 100644 ATM33xx-5/lib/atm_utils_c/atm_utils_c.h create mode 100644 ATM33xx-5/lib/atm_utils_math/atm_utils_math.h create mode 100644 ATM33xx-5/lib/atm_utils_reg/atm_utils_reg.c create mode 100644 ATM33xx-5/lib/atm_utils_reg/atm_utils_reg.h create mode 100644 ATM33xx-5/lib/atm_vendor/CMakeLists.txt create mode 100644 ATM33xx-5/lib/atm_vendor/Kconfig create mode 100644 ATM33xx-5/lib/atm_vendor/atm_hci_uart.c create mode 100644 ATM33xx-5/lib/atm_vendor/atm_hci_uart.h create mode 100644 ATM33xx-5/lib/atm_vendor/atm_vendor.c create mode 100644 ATM33xx-5/lib/atm_vendor/atm_vendor.h create mode 100644 ATM33xx-5/lib/atm_vendor/atm_vendor_internal.h create mode 100644 ATM33xx-5/lib/sec_service/sec_service.c create mode 100644 ATM33xx-5/lib/sec_service/sec_service.h create mode 100644 ATM33xx-5/noinit.ld create mode 100644 ATM33xx-5/ramfunc-section.ld create mode 100644 CMakeLists.txt create mode 100644 Kconfig create mode 100644 tools/Kconfig create mode 100644 tools/scripts/atm_openocd.py create mode 100644 tools/scripts/atm_otp/__init__.py create mode 100644 tools/scripts/atm_otp/atm_otp.py create mode 100644 tools/scripts/atm_otp/test_atm_otp.py create mode 100644 tools/scripts/gen_atm_partition_info.py create mode 100644 tools/scripts/sec_jrnl_tlv/__init__.py create mode 100644 tools/scripts/sec_jrnl_tlv/sec_jrnl_tlv.py create mode 100644 tools/scripts/sec_jrnl_tlv/test_sec_jrnl_tlv.py create mode 100644 west/__init__.py create mode 100644 west/atm_arch_extension.py create mode 100644 west/atm_otp_west_extension.py create mode 100644 west/atm_west_utils.py create mode 100644 west/sec_jrnl_west_extension.py create mode 100644 west/tests/__init__.py create mode 100644 west/tests/test_atm_arch_west_extension.py create mode 100644 west/tests/test_atm_otp_west_extension.py create mode 100644 west/tests/test_sec_jrnl_west_extension.py create mode 100644 west/west-commands.yml create mode 100644 zephyr/module.yml diff --git a/ATM33xx-5/CMakeLists.txt b/ATM33xx-5/CMakeLists.txt new file mode 100644 index 0000000..6fbf019 --- /dev/null +++ b/ATM33xx-5/CMakeLists.txt @@ -0,0 +1,22 @@ +# Copyright (c) 2022-2024 Atmosic +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories( + include + include/arm + include/armgcc + include/reg +) + +if (CONFIG_ATM_ENABLE_NSC_EXAMPLE) + zephyr_include_directories( + examples/spe/src/cust_sec_func + ) +endif() + +add_subdirectory(lib) +add_subdirectory(drivers) + +zephyr_linker_sources(NOINIT noinit.ld) +zephyr_linker_sources(RAMFUNC_SECTION ramfunc-section.ld) diff --git a/ATM33xx-5/config/atm33-mbedtls-config.h b/ATM33xx-5/config/atm33-mbedtls-config.h new file mode 100644 index 0000000..e75a52a --- /dev/null +++ b/ATM33xx-5/config/atm33-mbedtls-config.h @@ -0,0 +1,45 @@ +/** + ******************************************************************************* + * + * @file atm33-mbedtls-config.h + * + * @brief mbedtls glue for Atmosic HW engines + * + * Copyright (C) Atmosic 2023 + * + ******************************************************************************* + */ + +#pragma once + +#ifdef CONFIG_ATM_AES_HW + +#define MBEDTLS_AES_SETKEY_ENC_ALT +#define MBEDTLS_AES_SETKEY_DEC_ALT +#define MBEDTLS_AES_ENCRYPT_ALT +#define MBEDTLS_AES_DECRYPT_ALT + +#endif + +#ifdef CONFIG_ATM_SHA2_HW + +#define MBEDTLS_SHA256_ALT + +#endif + +#ifdef CONFIG_ATM_UECC + +#define MBEDTLS_ECDSA_GENKEY_ALT +#define MBEDTLS_ECDSA_SIGN_ALT +#define MBEDTLS_ECDSA_VERIFY_ALT +#undef MBEDTLS_ECP_DP_SECP384R1_ENABLED +#undef MBEDTLS_ECP_DP_SECP521R1_ENABLED +#undef MBEDTLS_ECP_DP_SECP192K1_ENABLED +#undef MBEDTLS_ECP_DP_SECP224K1_ENABLED +#undef MBEDTLS_ECP_DP_BP256R1_ENABLED +#undef MBEDTLS_ECP_DP_BP384R1_ENABLED +#undef MBEDTLS_ECP_DP_BP512R1_ENABLED +#undef MBEDTLS_ECP_DP_CURVE25519_ENABLED +#undef MBEDTLS_ECP_DP_CURVE448_ENABLED + +#endif diff --git a/ATM33xx-5/drivers/CMakeLists.txt b/ATM33xx-5/drivers/CMakeLists.txt new file mode 100644 index 0000000..23d2738 --- /dev/null +++ b/ATM33xx-5/drivers/CMakeLists.txt @@ -0,0 +1,120 @@ +# Copyright (c) 2023-2024 Atmosic +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories( + atm_bp_clock + dma + flash + rep_vec + sec_cache + sec_jrnl + sec_reset + spi + timer + trng +) + +if (CONFIG_ATM_PLF_DEBUG) + zephyr_compile_definitions( + CFG_PLF_DEBUG + ) + zephyr_sources( + user_debug.c + ) +endif () + +if (CONFIG_ADC OR CONFIG_BT OR CONFIG_ENTROPY_ATM_TRNG OR CONFIG_PM) + zephyr_include_directories( + reset + workarounds + ) + zephyr_sources( + reset/reset.c + workarounds/workarounds.c + ) +endif () + +if ((CONFIG_BT OR CONFIG_ENTROPY_ATM_TRNG) AND CONFIG_USE_ATMWSTK) + zephyr_include_directories( + atmwstk + ) + zephyr_sources( + atmwstk/atmwstk.c + ) +endif () + +if (CONFIG_TRUSTED_EXECUTION_SECURE OR CONFIG_SOC_FLASH_ATM_RRAM) + zephyr_include_directories( + rram_rom_prot + ) + zephyr_sources( + rram_rom_prot/rram_rom_prot.c + ) +endif () + +if (CONFIG_TRUSTED_EXECUTION_SECURE) + zephyr_sources( + sec_cache/sec_cache.c + sec_jrnl/sec_jrnl.c + ) + + if (NOT CONFIG_MCUBOOT) + zephyr_include_directories( + at_tz_mpc + sec_dev_lockout + ) + zephyr_sources( + at_tz_mpc/at_tz_mpc.c + sec_dev_lockout/sec_dev_lockout.c + sec_reset/sec_reset.c + ) + endif () +endif () + +if ((CONFIG_TRUSTED_EXECUTION_NONSECURE AND (CONFIG_SOC_FLASH_ATM OR CONFIG_BT OR CONFIG_ENTROPY_ATM_TRNG OR CONFIG_PM OR CONFIG_ADC)) OR (CONFIG_TRUSTED_EXECUTION_SECURE AND NOT CONFIG_BOOTLOADER_MCUBOOT)) + zephyr_sources( + atm_bp_clock/atm_bp_clock.c + spi/spi.c + ) +endif () + +if (CONFIG_ATM_AES_HW OR CONFIG_ATM_SHA2_HW OR CONFIG_ATM_UECC) + zephyr_include_directories( + ../config + ) + zephyr_link_libraries(mbedTLS) +endif () + +if (CONFIG_ATM_AES_HW) + zephyr_include_directories( + atm_aes + ) + zephyr_sources( + atm_aes/atm_aes.c + atm_aes/aes_alt.c + ) +endif () + +if (CONFIG_ATM_SHA2_HW OR CONFIG_ATM_SHA2_HW_BOOTUTIL) + zephyr_include_directories( + atm_sha2 + ) + zephyr_sources( + atm_sha2/atm_sha2.c + ) +endif () +if (CONFIG_ATM_SHA2_HW) + zephyr_sources( + atm_sha2/sha256_alt.c + ) +endif () + +if (CONFIG_ATM_UECC) + zephyr_include_directories( + micro-ecc + ) + zephyr_sources( + micro-ecc/ecdsa_alt.c + ) +endif () diff --git a/ATM33xx-5/drivers/Kconfig b/ATM33xx-5/drivers/Kconfig new file mode 100644 index 0000000..003dd3c --- /dev/null +++ b/ATM33xx-5/drivers/Kconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2023-2024 Atmosic +# +# SPDX-License-Identifier: Apache-2.0 + + +config ATM_AES_HW + bool "Hardware accelerator for AES" + default y + depends on MBEDTLS_CIPHER_AES_ENABLED && !USERSPACE + select MBEDTLS_USER_CONFIG_ENABLE + +config ATM_SHA2_HW + bool "Hardware accelerator for SHA256 hash" + default n + depends on MBEDTLS_HASH_SHA256_ENABLED && !USERSPACE + select MBEDTLS_USER_CONFIG_ENABLE + +config ATM_SHA2_HW_BOOTUTIL + bool "Hardware accelerator for SHA256 hash supporting bootutil API (only used by MCUBOOT)" + default n + +config ATM_UECC + bool "Optimized ECC library" + default n + depends on MBEDTLS_ECDSA_C + +config MBEDTLS_USER_CONFIG_FILE + default "atm33-mbedtls-config.h" if ATM_AES_HW || ATM_SHA2_HW || ATM_UECC diff --git a/ATM33xx-5/drivers/at_tz_mpc/at_tz_mpc.c b/ATM33xx-5/drivers/at_tz_mpc/at_tz_mpc.c new file mode 100644 index 0000000..0b17a8a --- /dev/null +++ b/ATM33xx-5/drivers/at_tz_mpc/at_tz_mpc.c @@ -0,0 +1,250 @@ +/** + ******************************************************************************* + * + * @file at_tz_mpc.c + * + * @brief Memory Protection Controller (MPC) driver + * + * Copyright (C) Atmosic 2022-2024 + * + ******************************************************************************* + */ + +#include "arch.h" +#include +#include "at_tz_mpc.h" + +// Strip off IDAU bit to get physical address +#define GET_PHYS_ADDR(addr) ((addr) & ~0x10000000) +// Physical flash base address +#define PHYS_FLASH_BASE GET_PHYS_ADDR(CMSDK_FLASH_BASE) +// Physical RAM base address +#define PHYS_SRAM_BASE GET_PHYS_ADDR(CMSDK_SRAM_BASE) +// Base address for external flash +#define PHYS_EXT_FLASH_BASE CMSDK_EXT_FLASH_NONSECURE_BASE +// MPC only covers lower 128K of ext flash +#define AT_TZ_MPC_EXT_FLASH_LIMIT (PHYS_EXT_FLASH_BASE + AT_TZ_MPC_EXT_FLASH_MPC_SIZE) + +// Normalize address to an offset from base (by type) +#define NORMALIZE_ADDR(addr, type) ((addr) - \ + (((type) == AT_TZ_MPC_DEV_FLASH) ? PHYS_FLASH_BASE : PHYS_SRAM_BASE)) + +// MPC_FLS->BLK_MAX is incorrect. correct value is 34 due to size constraints +#define MAX_MPC_FLS_LUT_IDX 34 +#define BLOCKS_PER_MPC(type) (1 + \ + (((type) == AT_TZ_MPC_DEV_RAM) ? MPC_RAM0->BLK_MAX : MAX_MPC_FLS_LUT_IDX)) + +#define LUT_IDX_FROM_BLOCK(block, type) ((block) % BLOCKS_PER_MPC(type)) + +/* + * The flash mpc covers an address range that is a superset of + * valid addresses, only allow MPC control if in following range: + * - ROM+RRAM (0x00000 - 0x90000) + * - RRAM control registers (0x90000 - 0x90800) + * - AT_PRRF registers (0x1FF800 - 0x200000) + * - External flash (0x200000 - 0x220000) + * + * The RAM mpc simply covers the entire RAM range + */ +static at_tz_mpc_id_t at_tz_mpc_dev_from_addr(uint32_t phys_address) +{ + if (((phys_address >= PHYS_FLASH_BASE) && + (phys_address < PHYS_FLASH_BASE + ROM_RRAM_SIZE + + at_tz_mpc_get_block_size(AT_TZ_MPC_DEV_FLASH))) || + ((phys_address >= PHYS_EXT_FLASH_BASE - + at_tz_mpc_get_block_size(AT_TZ_MPC_DEV_FLASH)) && + (phys_address < AT_TZ_MPC_EXT_FLASH_LIMIT))) { + return AT_TZ_MPC_DEV_FLASH; + } else if ((phys_address >= PHYS_SRAM_BASE) && + (phys_address < PHYS_SRAM_BASE + RAM_SIZE)) { + return AT_TZ_MPC_DEV_RAM; + } + return AT_TZ_MPC_DEV_INVALID; +} + +static at_tz_mpc_ret_t at_tz_mpc_from_block_word(uint32_t block_word, + at_tz_mpc_id_t mpc_type, MPC_TypeDef **current_mpc, + uint32_t *mpc_ctrl_restore) +{ + if (mpc_type == AT_TZ_MPC_DEV_FLASH) { + *current_mpc = MPC_FLS; + return AT_TZ_MPC_RET_OK; + } + // Assumes all RAM MPCs have the same number of blocks + uint32_t mpc_idx = block_word / BLOCKS_PER_MPC(mpc_type); + MPC_TypeDef *new_mpc = NULL; + switch (mpc_idx) { + case 0: + new_mpc = MPC_RAM0; + break; + case 1: + new_mpc = MPC_RAM1; + break; + case 2: + new_mpc = MPC_RAM2; + break; + case 3: + new_mpc = MPC_RAM3; + break; + default: + return AT_TZ_MPC_RET_BLK_IDX_TOO_HIGH; + } + // Crossed a boundary to a new mpc. Need to restore ctrl register + // and save a new ctrl register + if (mpc_ctrl_restore && (new_mpc != *current_mpc)) { + (*current_mpc)->CTRL = *mpc_ctrl_restore; + *mpc_ctrl_restore = new_mpc->CTRL; + new_mpc->CTRL &= ~MPC_CTRL_AUTO_INCREMENT_Msk; + } + *current_mpc = new_mpc; + return AT_TZ_MPC_RET_OK; +} + +static at_tz_mpc_ret_t at_tz_mpc_check_bound(uint32_t limit_word, + at_tz_mpc_id_t mpc_start_type) +{ + if (mpc_start_type == AT_TZ_MPC_DEV_FLASH) { + if (limit_word < MAX_MPC_FLS_LUT_IDX) { + return AT_TZ_MPC_RET_OK; + } + return AT_TZ_MPC_RET_BLK_IDX_TOO_HIGH; + } + if (mpc_start_type == AT_TZ_MPC_DEV_RAM) { + // Assumes that all MPC_RAM[0-3] have the same block count and size + if (limit_word < ((MPC_RAM0->BLK_MAX + 1) * 4)) { + return AT_TZ_MPC_RET_OK; + } + return AT_TZ_MPC_RET_BLK_IDX_TOO_HIGH; + } + return AT_TZ_MPC_RET_INVALID_TYPE; +} + +at_tz_mpc_ret_t at_tz_mpc_config_region(uint32_t base, uint32_t limit, + at_tz_mpc_attr_t attr) +{ + uint32_t phys_base = GET_PHYS_ADDR(base); + uint32_t phys_limit = GET_PHYS_ADDR(limit); + + if (phys_limit <= phys_base) { + return AT_TZ_MPC_RET_BAD_BOUNDS; + } + // if address range is in flash, it will only use one MPC to cover range, + // if address range is in RAM, 4 MPCs are used to cover entire range + at_tz_mpc_id_t mpc_start_type = at_tz_mpc_dev_from_addr(phys_base); + + if (mpc_start_type == AT_TZ_MPC_DEV_INVALID) { + // base address not covered by MPC + return AT_TZ_MPC_RET_BAD_BOUNDS; + } + at_tz_mpc_id_t mpc_end_type = at_tz_mpc_dev_from_addr(phys_limit); + if (mpc_start_type != mpc_end_type) { + // limit address not covered by MPC or base and limit exist in + // different MPC types + return AT_TZ_MPC_RET_BAD_BOUNDS; + } + uint32_t block_size = at_tz_mpc_get_block_size(mpc_start_type); + + // this assumes all MPCs for RAM have the same block size + if (phys_base & (block_size - 1)) { + return AT_TZ_MPC_RET_BAD_BOUNDS; + } + // limit is inclusive, so it must be just before block size boundary + if ((phys_limit + 1) & (block_size - 1)) { + return AT_TZ_MPC_RET_BAD_BOUNDS; + } + + // Get a normalized address that is an offset from the beginning + // of the lowest range controlled by the MPC + uint32_t norm_base = NORMALIZE_ADDR(phys_base, mpc_start_type); + uint32_t norm_limit = NORMALIZE_ADDR(phys_limit, mpc_start_type); + uint32_t block_start_idx = norm_base / block_size; + uint32_t block_start_word = block_start_idx / 32; + uint32_t block_end_idx = norm_limit / block_size; + uint32_t block_end_word = block_end_idx / 32; + // Sanity check that word limit fits in bounds covered by MPC + if (at_tz_mpc_check_bound(block_end_word, mpc_start_type)) { + return AT_TZ_MPC_RET_BLK_IDX_TOO_HIGH; + } + + // Get masks for "incomplete" blocks, all remaining LUTs are the same mask + uint32_t block_start_mask = ~((1 << (block_start_idx % 32)) - 1); + uint32_t block_end_mask = (1 << ((block_end_idx + 1) % 32)) - 1; + + // If block_end_mask is 0, it means that the limit touched block index is + // the limit in its word, so the limit word mask has all its bits selected + if (block_end_mask == 0) { + block_end_mask = 0xFFFFFFFF; + } + // If the blocks to configure are all packed in one word, only touch this + // word. Only bits that are the same in both masks are valid + if (block_start_word == block_end_word) { + uint32_t joined_mask = ~(block_start_mask ^ block_end_mask); + block_start_mask = joined_mask; + // this should not be used + block_end_mask = joined_mask; + } + + // Starts changing actual configuration so issue DMB to ensure every + // transaction has completed by now + __DMB(); + + MPC_TypeDef *current_mpc = NULL; + // get current_mpc to check block size before continuing. + at_tz_mpc_ret_t ret = at_tz_mpc_from_block_word(block_start_word, + mpc_start_type, ¤t_mpc, NULL); + if ((ret != AT_TZ_MPC_RET_OK) || (current_mpc == NULL)) { + return ret; + } + // at_tz_mpc_from_block_word() restores previous MPC when necessary. + uint32_t ctrl_bkup = current_mpc->CTRL; + current_mpc->CTRL &= ~MPC_CTRL_AUTO_INCREMENT_Msk; + uint32_t lut_idx = LUT_IDX_FROM_BLOCK(block_start_word, mpc_start_type); + + // Handle first bit mask + current_mpc->BLK_IDX = lut_idx; + if (attr == AT_TZ_MPC_ATTR_NONSECURE) { + current_mpc->BLK_LUT |= block_start_mask; + } else { + current_mpc->BLK_LUT &= ~block_start_mask; + } + + // short circuit if we are only modifying a single block + if (block_start_word == block_end_word) { + goto at_tz_mpc_config_done; + } + + // Handle body + for (uint32_t bword = block_start_word + 1; bword < block_end_word; + bword++) { + // update MPC to next mpc if we overflow into the next one. + at_tz_mpc_from_block_word(bword, mpc_start_type, ¤t_mpc, + &ctrl_bkup); + lut_idx = LUT_IDX_FROM_BLOCK(bword, mpc_start_type); + current_mpc->BLK_IDX = lut_idx; + if (attr == AT_TZ_MPC_ATTR_NONSECURE) { + current_mpc->BLK_LUT = 0xFFFFFFFF; + } else { + current_mpc->BLK_LUT = 0x00000000; + } + } + + // Handle final LUT + at_tz_mpc_from_block_word(block_end_word, mpc_start_type, ¤t_mpc, + &ctrl_bkup); + lut_idx = LUT_IDX_FROM_BLOCK(block_end_word, mpc_start_type); + current_mpc->BLK_IDX = lut_idx; + if (attr == AT_TZ_MPC_ATTR_NONSECURE) { + current_mpc->BLK_LUT |= block_end_mask; + } else { + current_mpc->BLK_LUT &= ~block_end_mask; + } + // Restore previous configuration + current_mpc->CTRL = ctrl_bkup; + +at_tz_mpc_config_done: + /* Changes complete, issue sync barrier to commit config */ + __DSB(); + __ISB(); + + return AT_TZ_MPC_RET_OK; +} diff --git a/ATM33xx-5/drivers/at_tz_mpc/at_tz_mpc.h b/ATM33xx-5/drivers/at_tz_mpc/at_tz_mpc.h new file mode 100644 index 0000000..2d4fc7e --- /dev/null +++ b/ATM33xx-5/drivers/at_tz_mpc/at_tz_mpc.h @@ -0,0 +1,215 @@ +/** + ******************************************************************************* + * + * @file at_tz_mpc.h + * + * @brief Memory Protection Controller (MPC) driver + * + * Copyright (C) Atmosic 2022 + * + ******************************************************************************* + */ + +#pragma once + +#include "arch.h" +#include + +/** + * @defgroup AT_TZ_MPC MPC + * @ingroup DRIVERS + * @brief Trustzone MPC driver + * + * This module contains the necessary functions to manage Memory protection + * controllers + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/// Block size of MPC_FLS +#define AT_TZ_MPC_FLS_BLK_SIZE 2048 +/// Block size of MPC_RAM[0-3] +#define AT_TZ_MPC_RAM_BLK_SIZE 256 + +// only 128K of ext flash is configurable via MPC +#define AT_TZ_MPC_EXT_FLASH_MPC_SIZE 0x20000 + +typedef enum { + /// Success + AT_TZ_MPC_RET_OK, + /// Bounds are invalid for configuration + AT_TZ_MPC_RET_BAD_BOUNDS, + /// address results in invalid block address + AT_TZ_MPC_RET_BLK_IDX_TOO_HIGH, + /// Memory type not supported by MPC + AT_TZ_MPC_RET_INVALID_TYPE, + AT_TZ_MPC_RET_MAX, +} at_tz_mpc_ret_t; + +typedef enum { + /// MPC secure attribute + AT_TZ_MPC_ATTR_SECURE, + /// MPC non-secure attribute + AT_TZ_MPC_ATTR_NONSECURE, + AT_TZ_MPC_ATTR_MAX, +} at_tz_mpc_attr_t; + +typedef enum { + /// FLASH MPC + AT_TZ_MPC_DEV_FLASH, + /// RAM MPC + AT_TZ_MPC_DEV_RAM, + AT_TZ_MPC_DEV_INVALID, + AT_TZ_MPC_DEV_MAX, +} at_tz_mpc_id_t; + +/** + * @brief Get block size for a given MPC + * + * @param[in] mpc_type MPC + * @return block size of MPC + */ +__STATIC_INLINE uint32_t at_tz_mpc_get_block_size(at_tz_mpc_id_t mpc_type) +{ + if (mpc_type == AT_TZ_MPC_DEV_FLASH) { + return AT_TZ_MPC_FLS_BLK_SIZE; + } + ASSERT_INFO(mpc_type == AT_TZ_MPC_DEV_RAM, mpc_type, 0); + // assumes all RAM mpcs have the same block size + return AT_TZ_MPC_RAM_BLK_SIZE; +} + +/** + * @brief Enable interrupt on specific MPC + * @note This API only enables the interrupt at the controller. + * User is required to implement MPC interrupt handler. + * + * @param[in] mpc_type MPC to enable interrupt on + * @return AT_TZ_MPC_RET_OK on success + */ +__STATIC_INLINE at_tz_mpc_ret_t at_tz_mpc_enable_int(at_tz_mpc_id_t mpc_type) +{ + if (mpc_type == AT_TZ_MPC_DEV_FLASH) { + MPC_FLS->INT_EN |= MPC_INT_EN_IRQ_EN_Msk; + return AT_TZ_MPC_RET_OK; + } else if (mpc_type == AT_TZ_MPC_DEV_RAM) { + MPC_RAM0->INT_EN |= MPC_INT_EN_IRQ_EN_Msk; + MPC_RAM1->INT_EN |= MPC_INT_EN_IRQ_EN_Msk; + MPC_RAM2->INT_EN |= MPC_INT_EN_IRQ_EN_Msk; + MPC_RAM3->INT_EN |= MPC_INT_EN_IRQ_EN_Msk; + return AT_TZ_MPC_RET_OK; + } + return AT_TZ_MPC_RET_INVALID_TYPE; +} + +/** + * @brief Disable interupt on specific MPC + * + * @param[in] mpc_type MPC to disable interrupt on + * @return AT_TZ_MPC_RET_OK on success + */ +__STATIC_INLINE at_tz_mpc_ret_t at_tz_mpc_disable_int(at_tz_mpc_id_t mpc_type) +{ + if (mpc_type == AT_TZ_MPC_DEV_FLASH) { + MPC_FLS->INT_EN &= ~MPC_INT_EN_IRQ_EN_Msk; + return AT_TZ_MPC_RET_OK; + } else if (mpc_type == AT_TZ_MPC_DEV_RAM) { + MPC_RAM0->INT_EN &= ~MPC_INT_EN_IRQ_EN_Msk; + MPC_RAM1->INT_EN &= ~MPC_INT_EN_IRQ_EN_Msk; + MPC_RAM2->INT_EN &= ~MPC_INT_EN_IRQ_EN_Msk; + MPC_RAM3->INT_EN &= ~MPC_INT_EN_IRQ_EN_Msk; + return AT_TZ_MPC_RET_OK; + } + return AT_TZ_MPC_RET_INVALID_TYPE; +} + +/** + * @brief Enable triggering bus fault on mpc violation + * + * @param[in] mpc_type MPC to enable interrupt on + * @return AT_TZ_MPC_RET_OK on success + */ +__STATIC_INLINE at_tz_mpc_ret_t at_tz_mpc_enable_bus_fault( + at_tz_mpc_id_t mpc_type) +{ + if (mpc_type == AT_TZ_MPC_DEV_FLASH) { + MPC_FLS->CTRL |= MPC_CTRL_CFG_SEC_RESP_Msk; + return AT_TZ_MPC_RET_OK; + } else if (mpc_type == AT_TZ_MPC_DEV_RAM) { + MPC_RAM0->CTRL |= MPC_CTRL_CFG_SEC_RESP_Msk; + MPC_RAM1->CTRL |= MPC_CTRL_CFG_SEC_RESP_Msk; + MPC_RAM2->CTRL |= MPC_CTRL_CFG_SEC_RESP_Msk; + MPC_RAM3->CTRL |= MPC_CTRL_CFG_SEC_RESP_Msk; + return AT_TZ_MPC_RET_OK; + } + return AT_TZ_MPC_RET_INVALID_TYPE; +} + +/** + * @brief Enable lockdown feature that prevents malicious software from + * changing the security configuration. + * + * @note lockdown can only be disabled with a reset. + * + * @param[in] mpc_type device to lock down + * @return AT_TZ_MPC_RET_OK on success + */ +__STATIC_INLINE at_tz_mpc_ret_t at_tz_mpc_lock_down(at_tz_mpc_id_t mpc_type) +{ + // Arm recommends that you enabled the auto-increment bit before enabling + // the configuration lockdown feature. When the feature is enabled, only + // LUT dumping is available which is simpler when BLK_IDX auto-increments + if (mpc_type == AT_TZ_MPC_DEV_FLASH) { + MPC_FLS->CTRL |= (MPC_CTRL_AUTO_INCREMENT_Msk | MPC_CTRL_SEC_LOCK_Msk); + return AT_TZ_MPC_RET_OK; + } else if (mpc_type == AT_TZ_MPC_DEV_RAM) { + MPC_RAM0->CTRL |= (MPC_CTRL_AUTO_INCREMENT_Msk | MPC_CTRL_SEC_LOCK_Msk); + MPC_RAM1->CTRL |= (MPC_CTRL_AUTO_INCREMENT_Msk | MPC_CTRL_SEC_LOCK_Msk); + MPC_RAM2->CTRL |= (MPC_CTRL_AUTO_INCREMENT_Msk | MPC_CTRL_SEC_LOCK_Msk); + MPC_RAM3->CTRL |= (MPC_CTRL_AUTO_INCREMENT_Msk | MPC_CTRL_SEC_LOCK_Msk); + return AT_TZ_MPC_RET_OK; + } + return AT_TZ_MPC_RET_INVALID_TYPE; +} + +/** + * @brief Configure a given region to a specific security attribute. + * + * @param[in] base base address for lower bound of region + * Must be aligned to at_tz_mpc_get_block_size(type) + * @param[in] limit limit of region, inclusive. + * Must be aligned to (at_tz_mpc_get_block_size(type) - 1) + * @param[in] attr attribute to configure region to + * @return AT_TZ_MPC_RET_OK on success + */ +at_tz_mpc_ret_t at_tz_mpc_config_region(uint32_t base, uint32_t limit, + at_tz_mpc_attr_t attr); + +/** + * @brief Configure remaining external flash (beyond 128k) security + * + * @note Size of flash is highly variable, only 128k is configurable at + * 2k boundary, remaining up to 16M is controlled by a single bit. + * @return AT_TZ_MPC_RET_OK on success + */ +__STATIC_INLINE at_tz_mpc_ret_t at_tz_mpc_config_remaining_ext_flash( + at_tz_mpc_attr_t attr) +{ + MPC_FLS->BLK_IDX = 34; + if (attr == AT_TZ_MPC_ATTR_NONSECURE) { + MPC_FLS->BLK_LUT = 0x1; + return AT_TZ_MPC_RET_OK; + } + MPC_FLS->BLK_LUT = 0x0; + return AT_TZ_MPC_RET_OK; +} + +#ifdef __cplusplus +} +#endif + +/// @} diff --git a/ATM33xx-5/drivers/atm_aes/aes_alt.c b/ATM33xx-5/drivers/atm_aes/aes_alt.c new file mode 100644 index 0000000..35272c8 --- /dev/null +++ b/ATM33xx-5/drivers/atm_aes/aes_alt.c @@ -0,0 +1,138 @@ +/** + ******************************************************************************* + * + * @file aes_alt.c + * + * @brief mbedtls glue for Atmosic AES driver + * + * Copyright (C) Atmosic 2023 + * + ******************************************************************************* + */ + +#ifdef CONFIG_SOC_FAMILY_ATM +#include +#endif + +#include "arch.h" +#include +#include "atm_aes.h" + +#define MBEDTLS_ALLOW_PRIVATE_ACCESS + +#include "mbedtls/aes.h" +#include "mbedtls/error.h" + +#ifdef CONFIG_SOC_FAMILY_ATM +static K_MUTEX_DEFINE(aes_hw_mutex); +#endif + +int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits) +{ + switch (keybits) { + case 128: + ctx->nr = ATM_AES_KEY_LEN_128; + break; + case 192: + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + case 256: + ctx->nr = ATM_AES_KEY_LEN_256; + break; + default: + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + ctx->rk_offset = 0; + memcpy(ctx->buf + ctx->rk_offset, key, keybits >> 3); + return 0; +} + +int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits) +{ + switch (keybits) { + case 128: + ctx->nr = ATM_AES_KEY_LEN_128; + break; + case 192: + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + case 256: + ctx->nr = ATM_AES_KEY_LEN_256; + break; + default: + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + ctx->rk_offset = 0; + memcpy(ctx->buf + ctx->rk_offset, key, keybits >> 3); + return 0; +} + +int mbedtls_internal_aes_encrypt(mbedtls_aes_context *ctx, + const unsigned char input[16], unsigned char output[16]) +{ + atm_aes_params_t params = { + .mode = ATM_AES_MODE_ECB, + .key_len = ctx->nr, + .encrypt = true, + .key = (uint8_t *)(ctx->buf + ctx->rk_offset), + }; + +#ifdef CONFIG_SOC_FAMILY_ATM + if (k_mutex_lock(&aes_hw_mutex, K_MSEC(100))) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } +#endif + + atm_aes_res_t res = atm_aes_init(¶ms); + if (res != ATM_AES_RES_SUCCESS) { +#ifdef CONFIG_SOC_FAMILY_ATM + k_mutex_unlock(&aes_hw_mutex); +#endif + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + res = atm_aes_update(output, input, 16); +#ifdef CONFIG_SOC_FAMILY_ATM + k_mutex_unlock(&aes_hw_mutex); +#endif + if (res != ATM_AES_RES_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + return 0; +} + +int mbedtls_internal_aes_decrypt(mbedtls_aes_context *ctx, + const unsigned char input[16], unsigned char output[16]) +{ + atm_aes_params_t params = { + .mode = ATM_AES_MODE_ECB, + .key_len = ctx->nr, + .encrypt = false, + .key = (uint8_t *)(ctx->buf + ctx->rk_offset), + }; + +#ifdef CONFIG_SOC_FAMILY_ATM + if (k_mutex_lock(&aes_hw_mutex, K_MSEC(100))) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } +#endif + + atm_aes_res_t res = atm_aes_init(¶ms); + if (res != ATM_AES_RES_SUCCESS) { +#ifdef CONFIG_SOC_FAMILY_ATM + k_mutex_unlock(&aes_hw_mutex); +#endif + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + res = atm_aes_update(output, input, 16); +#ifdef CONFIG_SOC_FAMILY_ATM + k_mutex_unlock(&aes_hw_mutex); +#endif + if (res != ATM_AES_RES_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + return 0; +} diff --git a/ATM33xx-5/drivers/atm_aes/atm_aes.c b/ATM33xx-5/drivers/atm_aes/atm_aes.c new file mode 100644 index 0000000..5c7b133 --- /dev/null +++ b/ATM33xx-5/drivers/atm_aes/atm_aes.c @@ -0,0 +1,170 @@ +/** + ******************************************************************************* + * + * @file atm_aes.c + * + * @brief Atmosic AES driver + * + * Copyright (C) Atmosic 2022 + * + ******************************************************************************* + */ + +#include "atm_aes.h" +#include "arch.h" +#include "at_wrpr.h" +#include "at_apb_aes_regs_core_macro.h" +#include "atm_utils_reg.h" +#ifdef SECURE_MODE +#include "key_sideload.h" +#endif + +#define AES_ID 0x414553 +#define BYTES_PER_WORD sizeof(uint32_t) +#define KEY_WORDS_128 (ATM_AES_128_KEY_LEN_BYTES / BYTES_PER_WORD) +#define KEY_WORDS_256 (ATM_AES_256_KEY_LEN_BYTES / BYTES_PER_WORD) +#define BLOCK_WORDS (ATM_AES_BLOCK_LEN_BYTES / BYTES_PER_WORD) + +atm_aes_res_t atm_aes_init(atm_aes_params_t const *params) +{ + if (!params->key) { + return ATM_AES_RES_INVALID_INPUT_ERR; + } + if (params->mode >= ATM_AES_MODE_COUNT) { + return ATM_AES_RES_INVALID_INPUT_ERR; + } + if (params->key_len != ATM_AES_KEY_LEN_128 && + params->key_len != ATM_AES_KEY_LEN_256) { + return ATM_AES_RES_INVALID_INPUT_ERR; + } + if (params->mode != ATM_AES_MODE_ECB && !params->iv) { + return ATM_AES_RES_INVALID_INPUT_ERR; + } + WRPR_CTRL_SET(CMSDK_AES, WRPR_CTRL__CLK_ENABLE); + if (CMSDK_AES->ID != AES_ID) { + return ATM_AES_RES_AES_ID_ERR; + } + uint32_t ctrl = 0; + // Note: mode and key_len are 1-hot encoded + ctrl |= 1 << (params->mode + AES_CTRL_SHADOWED__MODE__SHIFT); + ctrl |= 1 << (params->key_len + AES_CTRL_SHADOWED__KEY_LEN__SHIFT); + if (!params->encrypt) { + ctrl |= 1 << AES_CTRL_SHADOWED__OPERATION__SHIFT; + } + // CTRL must be written now even if we are sideloading + CMSDK_AES->CTRL_SHADOWED = ctrl; + CMSDK_AES->CTRL_SHADOWED = ctrl; + // wait for idle bit in status + while (!(CMSDK_AES->STATUS & AES_STATUS__IDLE__MASK)) { + YIELD(); + } + size_t const key_bytes = (params->key_len == ATM_AES_KEY_LEN_128) ? + ATM_AES_128_KEY_LEN_BYTES : ATM_AES_256_KEY_LEN_BYTES; +#ifdef SECURE_MODE + if (key_sideload_address_valid(params->key)) { + if (key_sideload_slot_size_valid_aes(params->key, key_bytes)) { + // sideload must be complete before CTRL is written + ctrl |= AES_CTRL_SHADOWED__SIDELOAD__WRITE(1); + + CMSDK_AES->SIDELOAD_CTRL = + AES_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__WRITE(1); + key_sideload_slot_load(params->key); + CMSDK_AES->SIDELOAD_CTRL = + AES_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__WRITE(0) | + AES_SIDELOAD_CTRL__SIDELOAD_VAL__WRITE(1); + // rewrite CTRL register with sideload bit + CMSDK_AES->CTRL_SHADOWED = ctrl; + CMSDK_AES->CTRL_SHADOWED = ctrl; + // wait for idle bit in status + while (!(CMSDK_AES->STATUS & AES_STATUS__IDLE__MASK)) { + YIELD(); + } + } else { + return ATM_AES_RES_INVALID_INPUT_ERR; + } + } else +#endif + { + uint32_t volatile *key_reg = &(CMSDK_AES->KEY_SHARE0_0); + atm_reg_write_multiple(&(CMSDK_AES->KEY_SHARE0_0), params->key, + key_bytes); + // load remaining words with 0s + for (size_t i = key_bytes / sizeof(uint32_t); i < KEY_WORDS_256; i++) { + key_reg[i] = 0; + } + // load keyshare 1 with 0s + key_reg = &(CMSDK_AES->KEY_SHARE1_0); + for (size_t i = 0; i < KEY_WORDS_256; i++) { + key_reg[i] = 0; + } + } + if (params->mode != ATM_AES_MODE_ECB) { + atm_reg_write_multiple(&(CMSDK_AES->IV_0), params->iv, + ATM_AES_IV_LEN_BYTES); + } + return ATM_AES_RES_SUCCESS; +} + +atm_aes_res_t atm_aes_update(uint8_t *dest, uint8_t const *src, + size_t num_bytes) +{ + // for all modes that aren't CFB or CTR, input must be an exact number of + // blocks + if (AES_CTRL_SHADOWED__MODE__READ(CMSDK_AES->CTRL_SHADOWED) != + (1 << ATM_AES_MODE_CFB) && + AES_CTRL_SHADOWED__MODE__READ(CMSDK_AES->CTRL_SHADOWED) != + (1 << ATM_AES_MODE_CTR)) { + if (num_bytes % ATM_AES_BLOCK_LEN_BYTES) { + return ATM_AES_RES_INVALID_INPUT_ERR; + } + } + + if (!(CMSDK_AES->STATUS & AES_STATUS__INPUT_READY__MASK)) { + return ATM_AES_RES_INTERNAL_ERR; + } + // first process full blocks + for (size_t j = 0; j < num_bytes / ATM_AES_BLOCK_LEN_BYTES; j++) { + atm_reg_write_multiple(&(CMSDK_AES->DATA_IN_0), src, + ATM_AES_BLOCK_LEN_BYTES); + src += ATM_AES_BLOCK_LEN_BYTES; + while (!(CMSDK_AES->STATUS & AES_STATUS__OUTPUT_VALID__MASK)) { + YIELD(); + } + atm_reg_read_multiple(&(CMSDK_AES->DATA_OUT_0), dest, + ATM_AES_BLOCK_LEN_BYTES); + dest += ATM_AES_BLOCK_LEN_BYTES; + } + if (num_bytes % ATM_AES_BLOCK_LEN_BYTES) { + // handle incomplete blocks for CTR and CFB modes + size_t remaining_bytes = num_bytes % ATM_AES_BLOCK_LEN_BYTES; + atm_reg_write_multiple(&(CMSDK_AES->DATA_IN_0), src, remaining_bytes); + // write remaining words to zero, if needed + size_t zero_words = (ATM_AES_BLOCK_LEN_BYTES - remaining_bytes) / 4; + for (size_t i = BLOCK_WORDS - zero_words; i < BLOCK_WORDS; i++) { + uint32_t volatile *data_in_reg = &(CMSDK_AES->DATA_IN_0); + data_in_reg[i] = 0; + } + while (!(CMSDK_AES->STATUS & AES_STATUS__OUTPUT_VALID__MASK)) { + YIELD(); + } + atm_reg_read_multiple(&(CMSDK_AES->DATA_OUT_0), dest, remaining_bytes); + // read remaining words to leave engine in a good state + uint32_t const volatile *data_out_reg = &(CMSDK_AES->DATA_OUT_0); + for (size_t i = 0; i < BLOCK_WORDS; i++) { + data_out_reg[i]; + } + } + + return ATM_AES_RES_SUCCESS; +} + +void atm_aes_disable(void) +{ + CMSDK_AES->CTRL_SHADOWED = AES_CTRL_SHADOWED__MANUAL_OPERATION__MASK; + CMSDK_AES->CTRL_SHADOWED = AES_CTRL_SHADOWED__MANUAL_OPERATION__MASK; + CMSDK_AES->TRIGGER = AES_TRIGGER__KEY_IV_DATA_IN_CLEAR__MASK | + AES_TRIGGER__DATA_OUT_CLEAR__MASK; + + // disable clocks + WRPR_CTRL_SET(CMSDK_AES, 0); +} diff --git a/ATM33xx-5/drivers/atm_aes/atm_aes.h b/ATM33xx-5/drivers/atm_aes/atm_aes.h new file mode 100644 index 0000000..774ca55 --- /dev/null +++ b/ATM33xx-5/drivers/atm_aes/atm_aes.h @@ -0,0 +1,118 @@ +/** + ******************************************************************************* + * + * @file atm_aes.h + * + * @brief Atmosic AES driver + * + * Copyright (C) Atmosic 2022 + * + ******************************************************************************* + */ + +#pragma once + +/** + ******************************************************************************* + * @defgroup ATM_AES AES + * @ingroup DRIVERS + * @brief ATM AES driver + * + * This module contains the necessary functions to perform AES encryption and + * decryption. + * + * @{ + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include "compiler.h" + +#define ATM_AES_IV_LEN_BYTES 16 +#define ATM_AES_BLOCK_LEN_BYTES 16 +#define ATM_AES_128_KEY_LEN_BYTES 16 +#define ATM_AES_256_KEY_LEN_BYTES 32 + +typedef enum atm_aes_mode { + /// AES-ECB mode + ATM_AES_MODE_ECB, + /// AES-CBC mode + ATM_AES_MODE_CBC, + /// AES-CFB mode + ATM_AES_MODE_CFB, + /// AES-OFB mode + ATM_AES_MODE_OFB, + /// AES-CTR mode + ATM_AES_MODE_CTR, + ATM_AES_MODE_COUNT, +} atm_aes_mode_t; + +typedef enum atm_aes_key_len { + /// 128-bit key length + ATM_AES_KEY_LEN_128 = 0, + // 192-bit key length is not supported + // ATM_AES_KEY_LEN_192 = 1, + /// 256-bit key length + ATM_AES_KEY_LEN_256 = 2, + ATM_AES_KEY_LEN_COUNT, +} atm_aes_key_len_t; + +typedef enum atm_aes_res { + /// Success + ATM_AES_RES_SUCCESS, + /// Error reading AES ID + ATM_AES_RES_AES_ID_ERR, + /// Error on input values + ATM_AES_RES_INVALID_INPUT_ERR, + /// Error in AES Engine + ATM_AES_RES_INTERNAL_ERR, +} atm_aes_res_t; + +typedef struct { + atm_aes_mode_t mode; + atm_aes_key_len_t key_len; + bool encrypt; + uint8_t const *key; + /// initial value or initial counter. can be null for ECB mode. + uint8_t const *iv; +} atm_aes_params_t; + +/** + * @brief Initialize AES module + * + * @param[in] params aes parameters + * @return atm_aes_res_t result + */ +atm_aes_res_t atm_aes_init(atm_aes_params_t const *params); + +/** + * @brief Disable AES + * @note this will clear the IV, KEY, and DATA_IN registers + */ +void atm_aes_disable(void); + +/** + * @brief Process more data through the AES engine + * + * @note len must be a multiple of 16 bytes for ECB, CBC, and CFB modes. + * + * @param[out] dest Pointer to write the data after processing + * @param[in] src Pointer to the data to be processed + * @param[in] num_bytes Length of the input data, in bytes. + * @return atm_aes_res_t result + */ +__NONNULL(1, 2) +atm_aes_res_t atm_aes_update(uint8_t *dest, uint8_t const *src, + size_t num_bytes); + +#ifdef __cplusplus +} +#endif + +///@} diff --git a/ATM33xx-5/drivers/atm_bp_clock/atm_bp_clock.c b/ATM33xx-5/drivers/atm_bp_clock/atm_bp_clock.c new file mode 100644 index 0000000..81ab78d --- /dev/null +++ b/ATM33xx-5/drivers/atm_bp_clock/atm_bp_clock.c @@ -0,0 +1,83 @@ +/** + ******************************************************************************* + * + * @file atm_bp_clock.c + * + * @brief Wrapper for atm_bp_clock related functions + * + * Copyright (C) Atmosic 2023 + * + ******************************************************************************* + */ + +#include +#include +#include "arch.h" +#include "atm_bp_clock.h" +#define __CLKRSTGEN_GET_STATIC_INLINE __STATIC +#define __CLKRSTGEN_SET_STATIC_INLINE \ + __attribute__((section(".data_text"))) __STATIC +#include "at_clkrstgen.h" +#ifdef SECURE_MODE +#include "rep_vec.h" +#endif + +#if PLF_DEBUG +static uint32_t atm_bp_clock_max_freq; +#endif + +uint32_t atm_bp_clock_get(void) +{ + return at_clkrstgen_get_bp(); +} + +#if PLF_DEBUG +uint32_t atm_bp_clock_max_get(void) +{ + return atm_bp_clock_max_freq; +} +#endif + +__attribute__((noinline, section(".data_text"))) void +atm_bp_clock_set_hint(uint32_t freq, bool set, bool commit) +{ + ASSERT_INFO(!atm_bp_clock_max_freq || (freq <= atm_bp_clock_max_freq), + freq, atm_bp_clock_max_freq); + at_clkrstgen_set_bp_hint(freq, set, commit); +} + +__attribute__((noinline, section(".data_text"))) void +atm_bp_clock_set(uint32_t freq) +{ + ASSERT_INFO(!atm_bp_clock_max_freq || (freq <= atm_bp_clock_max_freq), + freq, atm_bp_clock_max_freq); + at_clkrstgen_set_bp(freq); +} + +bool atm_bp_clock_critical_section_allowed(uint32_t freq) +{ +#ifdef SECURE_MODE + return true; +#else + uint32_t min_freq = 0; + uint32_t bp_freq = atm_bp_clock_get(); + if (bp_freq <= freq) { + return true; + } + rep_vec__uint32_t__uint32_t_p__invoke(rv_plf_bp_throttle, NULL, bp_freq, + &min_freq); + DEBUG_TRACE_COND(min_freq > freq, + "atm_bp_clock critical section not allowed due to bp " + "throttle at %" PRIu32 "Hz", + min_freq); + return min_freq <= freq; +#endif +} + +#if PLF_DEBUG +__CONSTRUCTOR_PRIO(CONSTRUCTOR_USER_INIT) +static void atm_bp_clock_constructor(void) +{ + atm_bp_clock_max_freq = at_clkrstgen_get_bp(); +} +#endif diff --git a/ATM33xx-5/drivers/atm_bp_clock/atm_bp_clock.h b/ATM33xx-5/drivers/atm_bp_clock/atm_bp_clock.h new file mode 100644 index 0000000..e4bf31a --- /dev/null +++ b/ATM33xx-5/drivers/atm_bp_clock/atm_bp_clock.h @@ -0,0 +1,105 @@ +/** + ******************************************************************************* + * + * @file atm_bp_clock.h + * + * @brief Wrapper for backplane clock related functions + * + * Copyright (C) Atmosic 2023 + * + ******************************************************************************* + */ + +#pragma once + +/** + * @defgroup ATM_BP_CLOCK Atmosic BP clock wrapper + * @ingroup DRIVERS + * @brief Wrapper for bp clocking related functions for use where inlines are + * not needed. + * @{ + */ + +#include "arch.h" +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef CFG_ATM_BP_CLOCK_DEBUG +#define ATM_BP_CLOCK_DEBUG 1 +#else +#define ATM_BP_CLOCK_DEBUG 0 +#endif + +#define ATM_BP_CLOCK_ENTER_CRITICAL_SECTION(_bp_freq) \ + do { \ + uint32_t bp_saved = atm_bp_clock_get(); \ + if (bp_saved > _bp_freq) { \ + DEBUG_TRACE_COND(ATM_BP_CLOCK_DEBUG, "BP adjust from: %" PRIu32, \ + bp_saved); \ + __disable_irq(); \ + atm_bp_clock_set(_bp_freq); \ + } else { \ + bp_saved = 0; \ + } + +#define ATM_BP_CLOCK_LEAVE_CRITICAL_SECTION() \ + if (bp_saved) { \ + DEBUG_TRACE_COND(ATM_BP_CLOCK_DEBUG, "BP restore to: %" PRIu32, \ + bp_saved); \ + atm_bp_clock_set(bp_saved); \ + __enable_irq(); \ + } \ + } while (0) + +#define ATM_BP_XTAL_FREQ 16000000U + +/** + * @brief Get current backplane frequency + * + * @return current frequency in hertz + */ +uint32_t atm_bp_clock_get(void); + +#if PLF_DEBUG +/** + * @brief Get maximal backplane frequency + * + * @return current frequency in hertz + */ +uint32_t atm_bp_clock_max_get(void); +#endif + +/** + * @brief Set the backplane clock + * + * @param[in] freq Frequency in hertz + */ +void atm_bp_clock_set(uint32_t freq); + +/** + * @brief Set the backplane clock + * + * @param[in] freq Frequency in hertz + * @param[in] set true to set clock change + * @param[in] commit true to commit clock change + */ +void atm_bp_clock_set_hint(uint32_t freq, bool set, bool commit); + +/** + * @brief Check if bp clock can be lowered safely + * + * @param[in] freq desired frequency for backplane clock + * + * @return true if lowering bp clock can be enabled safely + */ +bool atm_bp_clock_critical_section_allowed(uint32_t freq); +#ifdef __cplusplus +} +#endif + +/// @} diff --git a/ATM33xx-5/drivers/atm_sha2/atm_sha2.c b/ATM33xx-5/drivers/atm_sha2/atm_sha2.c new file mode 100644 index 0000000..be944e1 --- /dev/null +++ b/ATM33xx-5/drivers/atm_sha2/atm_sha2.c @@ -0,0 +1,669 @@ +/** + ******************************************************************************* + * + * @file atm_sha2.c + * + * @brief Atmosic SHA256 driver + * + * Copyright (C) Atmosic 2022-2024 + * + ******************************************************************************* + */ + +#include +#include +#include +#include "atm_sha2.h" +#include "ARMv8MBL.h" +#include "base_addr.h" +#include "at_ahb_dma_regs_core_macro.h" +#include "at_ahb_sha2_regs_core_macro.h" +#include "at_apb_clkrstgen_regs_core_macro.h" +#include "at_apb_wrpr_pins_regs_core_macro.h" +#include "ll.h" +#include "atm_utils_c.h" +#include "atm_utils_reg.h" +#if defined(SECURE_MODE) +#if defined(ENABLE_HMAC_SIDELOAD) +#include "key_sideload.h" +#endif +// Must be set to dedicate SHA2 driver to SECURE only mode. +#ifdef SECURE_SHA2_MODE +#define CMSDK_SHA2 CMSDK_SHA2_SECURE +#else +#define CMSDK_SHA2 CMSDK_SHA2_NONSECURE +#endif +#else // defined(SECURE_MODE) +#define CMSDK_SHA2 CMSDK_SHA2_NONSECURE +#ifdef SECURE_SHA2_MODE +#error "SHA2 access is limited to SECURE when SECURE_SHA2_MODE is enabled." +#endif +#endif // defined(SECURE_MODE) + + +#define IS_ALIGNED(ptr, alignment) \ + (((uintptr_t)(ptr)) % (alignment) == 0) + +#define SHA2_ID 0x53484132 // 'S' 'H' 'A' '2' + +#ifndef ATM_SHA2_DEBUG +#define ATM_SHA2_DEBUG 0 +#endif + +#if ATM_SHA2_DEBUG +static void dump_buffer(uint8_t const *buffer, uint32_t len, char const *descr) +{ + uint32_t column = 0; + printf("HEX Dump: %s, %" PRIu32 " bytes \n ", descr, len); + for (uint32_t i = 0; i < len; i++) { + printf(" %02x", buffer[i]); + column++; + if (column > 16) { + column = 0; + printf("\n "); + } + } + printf("\n"); +} +#define SHA2_DUMP_BUFFER(b, l, desc) dump_buffer(b, l, desc) +#else +#define SHA2_DUMP_BUFFER(b, l, desc) \ + do { \ + } while (0) +#endif // ATM_SHA2_DEBUG + +#define SHA2_CONTROL_VALUE(param) \ + (AT_SHA2_CONTROL__HMAC_EN__WRITE((param)->mode) | \ + AT_SHA2_CONTROL__SHA_EN__WRITE(1) | \ + AT_SHA2_CONTROL__BYTE_SWIZZLE__WRITE((param)->byte_endianess) | \ + AT_SHA2_CONTROL__DIGEST_SWIZZLE__WRITE((param)->digest_endianess)) + +static inline void load_hmac_key(uint8_t const *hmac_key) +{ +#if defined(SECURE_MODE) && defined(ENABLE_HMAC_SIDELOAD) + if (key_sideload_address_valid(hmac_key)) { + CMSDK_SHA2->SIDELOAD_CTRL = + AT_SHA2_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__WRITE(1); + key_sideload_slot_load(hmac_key); + } else +#endif + { + atm_reg_write_multiple(&(CMSDK_SHA2->KEY_0), hmac_key, + HMAC_KEY_LEN); + } +} + +#if (ATM_SHA2_API == SHA_MULTI_CTXT) +static uint32_t sha2_clk_en_ref; +#endif + +static inline atm_sha256_res_t sha2_clock_enable(void) +{ +#if (ATM_SHA2_API == SHA_MULTI_CTXT) + uint32_t prev = sha2_clk_en_ref; + sha2_clk_en_ref++; + if (prev) { + // already on + return ATM_SHA256_RES_SUCCESS; + } +#endif + + // enable clock to sha2 block + CLKRSTGEN_USER_CLK_GATE_CTRL__SHA_HCLK__MODIFY(CMSDK_CLKRSTGEN_NONSECURE + ->USER_CLK_GATE_CTRL, + 1); + if (CMSDK_SHA2->ID != SHA2_ID) { + ASSERT_ERR(CMSDK_SHA2->ID); + return ATM_SHA256_RES_SHA_ID_ERR; + } + return ATM_SHA256_RES_SUCCESS; +} + +static inline atm_sha256_res_t sha2_clock_disable(void) +{ +#if (ATM_SHA2_API == SHA_MULTI_CTXT) + if (!sha2_clk_en_ref) { + ASSERT_ERR(0); + return ATM_SHA256_RES_INVALID_CTXT; + } + sha2_clk_en_ref--; + if (sha2_clk_en_ref) { + // stay on + return ATM_SHA256_RES_SUCCESS; + } +#endif + // disable clock to sha2 block + CMSDK_SHA2->CONTROL = 0; + CLKRSTGEN_USER_CLK_GATE_CTRL__SHA_HCLK__MODIFY(CMSDK_CLKRSTGEN_NONSECURE + ->USER_CLK_GATE_CTRL, + 0); + return ATM_SHA256_RES_SUCCESS; +} + +#if (ATM_SHA2_API == SHA_MULTI_CTXT) + +#if ATM_SHA2_DEBUG +static void dump_sha2_context(atm_sha2_ctxt_t *ctxt, char const *descr) +{ + printf("SHA2 (%p) ctxt dump: %s \n", ctxt, descr); + printf(" mode 0x%" PRIx32 "\n", ctxt->params->mode); + printf(" control 0x%" PRIx32 "\n", ctxt->control); + printf(" flags 0x%" PRIx32 "\n", ctxt->flags); + printf(" msg_len_bits HI:0x%" PRIx32 " LO:0x%" PRIx32 "\n", + (uint32_t)(ctxt->msg_len_bits << 32), (uint32_t)ctxt->msg_len_bits); + printf(" sha_txcount_bits HI:0x%" PRIx32 " LO:0x%" PRIx32 "\n", + (uint32_t)(ctxt->sha_txcount_bits << 32), + (uint32_t)ctxt->sha_txcount_bits); + printf(" txcount_bits HI:0x%" PRIx32 " LO:0x%" PRIx32 "\n", + (uint32_t)(ctxt->txcount_bits << 32), (uint32_t)ctxt->txcount_bits); + printf(" msg_len_bytes %" PRIu32 "\n", ctxt->msg_len_bytes); + printf(" partial_len %" PRIu32 "\n", ctxt->partial_len); + printf(" int_digest[0] 0x%" PRIx32 "\n", ctxt->int_digest[0]); +} +#endif // ATM_SHA2_DEBUG + +static void store_partial_block(atm_sha2_ctxt_t *ctxt, void const *buffer, + uint32_t count) +{ + if ((ctxt->partial_len + count) > sizeof(ctxt->partial_block)) { + ASSERT_INFO(0, ctxt->partial_len, count); + return; + } + memcpy(&ctxt->partial_block[ctxt->partial_len], buffer, count); + ctxt->partial_len += count; + DEBUG_TRACE_COND(ATM_SHA2_DEBUG, + "SHA2 (%p) bytes:%" PRIu32 " copied, new partial:%" PRIu32, ctxt, count, + ctxt->partial_len); + SHA2_DUMP_BUFFER(ctxt->partial_block, ctxt->partial_len, "Store Partial"); +} + +static atm_sha256_res_t sha2_load_context(atm_sha2_ctxt_t *ctxt, + void const *input, uint32_t *num_bytes, + atm_sha256_res_t (*data_push)(void const *input, uint32_t count)) +{ + if ((ctxt->magic != SHA2_ID) || (ctxt->flags & SHA2_CTXT_FLAGS_FINI)) { + DEBUG_TRACE("SHA2 rel-inv-ctxt"); + return ATM_SHA256_RES_INVALID_CTXT; + } + // clock must be on + ASSERT_ERR(sha2_clk_en_ref); + + uint32_t update_bytes = num_bytes ? *num_bytes : 0; + uint32_t residue = 0; + if (!input) { + // no input data to update (finalize), continue and start controller + goto start_controller; + } + + SHA2_DUMP_BUFFER(input, update_bytes, "User Input"); + // check if the current updated bytes plus the accumulated partial block + // meets the block size threshold + if ((update_bytes + ctxt->partial_len) < SHA256_BLK_SIZE_BYTES) { + // still a partial block, consume the update into the partial block + DEBUG_TRACE_COND(ATM_SHA2_DEBUG, + "SHA2 (%p) defer, pushed:%" PRIu32 " update:%" PRIu32 + " curr partial:%" PRIu32, + ctxt, ctxt->msg_len_bytes, update_bytes, ctxt->partial_len); + store_partial_block(ctxt, input, update_bytes); + // defer and do nothing + return ATM_SHA256_RES_DEFER_PROC; + } + + // this transfer will result in residue that has to be saved for the next + // update or finalization + residue = (update_bytes + ctxt->partial_len) & (SHA256_BLK_SIZE_BYTES - 1); + +start_controller: + + // reset to clear state before loading or establishing a new context + WRPRPINS_SOC_MISC_CTRL__SHA_RESET__SET( + CMSDK_WRPR0_NONSECURE->SOC_MISC_CTRL); + WRPRPINS_SOC_MISC_CTRL__SHA_RESET__CLR( + CMSDK_WRPR0_NONSECURE->SOC_MISC_CTRL); + // load control value to enable the core, required step to load + // counters/digest + CMSDK_SHA2->CONTROL = ctxt->control; + + uint32_t cmd; + if (ctxt->flags & SHA2_CTXT_FLAGS_STARTED) { +#if ATM_SHA2_DEBUG + dump_sha2_context(ctxt, !input ? "reload-fini" : "reload"); +#endif + // HW context already established, just restore + CMSDK_SHA2->MESSAGE_LENGTH_LO = (uint32_t)ctxt->msg_len_bits; + CMSDK_SHA2->MESSAGE_LENGTH_HI = ctxt->msg_len_bits >> 32; + CMSDK_SHA2->SHA_TXCOUNT_LO = (uint32_t)ctxt->sha_txcount_bits; + CMSDK_SHA2->SHA_TXCOUNT_HI = ctxt->sha_txcount_bits >> 32; + CMSDK_SHA2->TXCOUNT_LO = (uint32_t)ctxt->txcount_bits; + CMSDK_SHA2->TXCOUNT_HI = ctxt->txcount_bits >> 32; + for (uint32_t i = 0; i < SHA256_DIG_WORDS; i++) { + *(&CMSDK_SHA2->DIGEST0 + i) = ctxt->int_digest[i]; + } + // this is a continuation after a context is restored + cmd = AT_SHA2_CMD__HASH_CONTINUE__MASK | AT_SHA2_CMD__HASH_START__MASK; + DEBUG_TRACE_COND(ATM_SHA2_DEBUG, "SHA2 (%p) reload-ctxt-%s", ctxt, + !input ? "fini" : ""); + } else { + // first time to establish the HW context + // the HW context will be established + cmd = AT_SHA2_CMD__HASH_START__MASK; + ctxt->flags |= SHA2_CTXT_FLAGS_STARTED; + DEBUG_TRACE_COND(ATM_SHA2_DEBUG, "SHA2 (%p) start-ctxt", ctxt); + } + + if (ctxt->params->mode == ATM_SHA256_HMAC_MODE) { + // for HMAC reload the key + load_hmac_key(ctxt->params->key); + } + + // start the engine + DEBUG_TRACE_COND(ATM_SHA2_DEBUG, "SHA2 (%p) run cmd: 0x%" PRIx32, ctxt, + cmd); + CMSDK_SHA2->CMD = cmd; + + if (ctxt->partial_len) { + // flush partial block first + DEBUG_TRACE_COND(ATM_SHA2_DEBUG, + "SHA2 (%p) push partial bytes:%" PRIu32, ctxt, ctxt->partial_len); + SHA2_DUMP_BUFFER(ctxt->partial_block, ctxt->partial_len, + "Flush partial"); + uint32_t retv = data_push(ctxt->partial_block, ctxt->partial_len); + ctxt->partial_len = 0; + if (retv != ATM_SHA256_RES_SUCCESS) { + return retv; + } + } + + if (residue) { + ASSERT_ERR(input); + ASSERT_INFO(*num_bytes >= residue, *num_bytes, residue); + DEBUG_TRACE_COND(ATM_SHA2_DEBUG, + "SHA2 (%p) residue: %" PRIu32 " update: %" PRIu32, ctxt, residue, + *num_bytes); + store_partial_block(ctxt, + &((uint8_t const *)input)[*num_bytes - residue], residue); + // caller does not need to transfer the residue portion, we'll buffer it + // for the next update + *num_bytes -= residue; + } + + return ATM_SHA256_RES_SUCCESS; +} + +static void sync_controller_ctxt(void) +{ + // synchronize with the hardware, FIFO has to be empty + while (!(AT_SHA2_STATUS__FIFO_EMPTY__READ(CMSDK_SHA2->STATUS))) { + YIELD(); + } + // if the FIFO is empty wait for computation engine to be idle + while ( + AT_SHA2_STATUS__HASH_COMPUTE_BUSY__READ(CMSDK_SHA2->STATUS)) { + YIELD(); + } +} + +static atm_sha256_res_t sha2_save_context(atm_sha2_ctxt_t *ctxt, + void const *input, uint32_t num_bytes) +{ + if (!(ctxt->flags & SHA2_CTXT_FLAGS_STARTED)) { + ASSERT_INFO(0, ctxt->flags, 0); + return ATM_SHA256_RES_INVALID_CTXT; + } + sync_controller_ctxt(); + // controller is idle, now it is safe to extract the HW context + ctxt->control = CMSDK_SHA2->CONTROL; + ctxt->msg_len_bits = + (((uint64_t)CMSDK_SHA2->MESSAGE_LENGTH_HI) << 32) | + CMSDK_SHA2->MESSAGE_LENGTH_LO; + ctxt->sha_txcount_bits = + (((uint64_t)CMSDK_SHA2->SHA_TXCOUNT_HI) << 32) | + CMSDK_SHA2->SHA_TXCOUNT_LO; + ctxt->txcount_bits = (((uint64_t)CMSDK_SHA2->TXCOUNT_HI) << 32) | + CMSDK_SHA2->TXCOUNT_LO; + // partial blocks are buffered and held + // there should be no residue when we sync these registers + __UNUSED uint32_t blk_bit_mask = SHA256_BLK_SIZE_BITS - 1; + ASSERT_INFO(!(CMSDK_SHA2->MESSAGE_LENGTH_LO & blk_bit_mask), + CMSDK_SHA2->MESSAGE_LENGTH_LO, 0); + ASSERT_INFO(!(CMSDK_SHA2->SHA_TXCOUNT_LO & blk_bit_mask), + CMSDK_SHA2->SHA_TXCOUNT_LO, 0); + ASSERT_INFO(!(CMSDK_SHA2->TXCOUNT_LO & blk_bit_mask), + CMSDK_SHA2->TXCOUNT_LO, 0); + // save our progress + ctxt->msg_len_bytes = ctxt->msg_len_bits >> 3; + // save intermediate digest for the next load + for (uint32_t i = 0; i < SHA256_DIG_WORDS; i++) { + ctxt->int_digest[i] = *(&CMSDK_SHA2->DIGEST0 + i); + } +#if ATM_SHA2_DEBUG + dump_sha2_context(ctxt, "saved"); +#endif + return ATM_SHA256_RES_SUCCESS; +} + +#endif // SHA_MULTI_CTXT + +/* TODO: add support for sha engine mode (DMA or not) */ +atm_sha256_res_t +#if (ATM_SHA2_API == SHA_MULTI_CTXT) +atm_sha256_init_ctxt(atm_sha256_params_t const *params, atm_sha2_ctxt_t *ctxt) +#else +atm_sha256_init(atm_sha256_params_t const *params) +#endif +{ + if (params->mode >= ATM_SHA256_MAX_MODE) { + return ATM_SHA256_RES_INVALID_INPUT_ERR; + } + if ((params->mode == ATM_SHA256_HMAC_MODE) && (!params->key)) { + return ATM_SHA256_RES_INVALID_INPUT_ERR; + } + +#if (ATM_SHA2_API == SHA_MULTI_CTXT) + if (ctxt->magic == SHA2_ID) { + DEBUG_TRACE("SHA2 ctxt already init"); + // already initialized + return ATM_SHA256_RES_INVALID_CTXT; + } +#endif + + atm_sha256_res_t retv = sha2_clock_enable(); + if (retv != ATM_SHA256_RES_SUCCESS) { + return retv; + } + +#if (ATM_SHA2_API == SHA_MULTI_CTXT) + ctxt->magic = SHA2_ID; + ctxt->flags = 0; + ctxt->msg_len_bits = 0; + ctxt->msg_len_bytes = 0; + ctxt->sha_txcount_bits = 0; + ctxt->control = SHA2_CONTROL_VALUE(params); + ctxt->params = params; + ctxt->partial_len = 0; +#else + // enable SHA and set endianess + // system is little endian, standard vectors and most hash generators + // operate on big-endian words enable byte swizzle to swap in hardware + CMSDK_SHA2->CONTROL = SHA2_CONTROL_VALUE(params); + + if (params->mode == ATM_SHA256_HMAC_MODE) { + load_hmac_key(params->key); + } + + CMSDK_SHA2->CMD = AT_SHA2_CMD__HASH_START__WRITE(1); +#endif + return ATM_SHA256_RES_SUCCESS; +} + +#if (ATM_SHA2_API == SHA_MULTI_CTXT) +atm_sha256_res_t atm_sha256_disable_ctxt(atm_sha2_ctxt_t *ctxt) +#else +void atm_sha256_disable(void) +#endif +{ +#if (ATM_SHA2_API == SHA_MULTI_CTXT) + if (ctxt->magic != SHA2_ID) { + DEBUG_TRACE("SHA2 ctxt not init!"); + return ATM_SHA256_RES_INVALID_CTXT; + } + ctxt->magic = 0; + ctxt->flags = 0; +#endif + __UNUSED atm_sha256_res_t retv = sha2_clock_disable(); +#if (ATM_SHA2_API == SHA_MULTI_CTXT) + return retv; +#endif +} + +static atm_sha256_res_t push_data_dma(void const *input, uint32_t num_bytes) +{ + uint8_t const *buf_ptr = input; + CMSDK_AT_DMA_NONSECURE->INTERRUPT_MASK = + AT_DMA_INTERRUPT_STATUS__DMA_DONE__MASK | + AT_DMA_INTERRUPT_STATUS__DMA_ERR__MASK; + while (num_bytes) { + // poll for FIFO to drain before reloading the next block + while (!(CMSDK_SHA2->STATUS & + AT_SHA2_STATUS__FIFO_EMPTY__MASK)) { + YIELD(); + } + // clear the status bit (this is latched in) + CMSDK_SHA2->RESET_INTERRUPT = + AT_SHA2_RESET_INTERRUPT__INTRPT_RESET__MASK; + // SHA2 registers are not self-resetting. + CMSDK_SHA2->RESET_INTERRUPT = 0; + uint32_t dma_bytes = (num_bytes > SHA256_BLK_SIZE_BYTES) ? + SHA256_BLK_SIZE_BYTES : num_bytes; + uint32_t int_status; + GLOBAL_INT_DISABLE(); + // clear interrupts + CMSDK_AT_DMA_NONSECURE->RESET_INTERRUPT = + AT_DMA_INTERRUPT_STATUS__DMA_DONE__MASK | + AT_DMA_INTERRUPT_STATUS__DMA_ERR__MASK; + CMSDK_AT_DMA_NONSECURE->TAR_ADDR = + (uint32_t)(&CMSDK_SHA2->FIFO_PUSH); + CMSDK_AT_DMA_NONSECURE->SRC_ADDR = (uint32_t)buf_ptr; + CMSDK_AT_DMA_NONSECURE->SIZE = dma_bytes; + // target address is constant (FIFO mode) + CMSDK_AT_DMA_NONSECURE->OPMODE = + AT_DMA_OPMODE__GO__MASK | AT_DMA_OPMODE__CONST_TAR_ADDR__MASK; + num_bytes -= dma_bytes; + buf_ptr += dma_bytes; + // wait for DMA done for this block + while (!(CMSDK_AT_DMA_NONSECURE->INTERRUPT_STATUS & + (AT_DMA_INTERRUPT_STATUS__DMA_DONE__MASK | + AT_DMA_INTERRUPT_STATUS__DMA_ERR__MASK))) { + YIELD(); + } + int_status = CMSDK_AT_DMA_NONSECURE->INTERRUPT_STATUS; + GLOBAL_INT_RESTORE(); + if (int_status & AT_DMA_INTERRUPT_STATUS__DMA_ERR__MASK) { + return ATM_SHA256_RES_DMA_ERR; + } + } + return ATM_SHA256_RES_SUCCESS; +} + +atm_sha256_res_t +#if (ATM_SHA2_API == SHA_MULTI_CTXT) +atm_sha256_update_ctxt(atm_sha2_ctxt_t *ctxt, void const *input, + uint32_t num_bytes) +#else +atm_sha256_update(void const *input, uint32_t num_bytes) +#endif +{ + if (!num_bytes) { + return ATM_SHA256_RES_INVALID_INPUT_ERR; + } + atm_sha256_res_t retv; +#if (ATM_SHA2_API == SHA_MULTI_CTXT) + // restore context + retv = sha2_load_context(ctxt, input, &num_bytes, push_data_dma); + if (retv != ATM_SHA256_RES_SUCCESS) { + if (retv == ATM_SHA256_RES_DEFER_PROC) { + retv = ATM_SHA256_RES_SUCCESS; + } + return retv; + } +#endif + SHA2_DUMP_BUFFER(input, num_bytes, "push user (DMA)"); + retv = push_data_dma(input, num_bytes); + if (retv != ATM_SHA256_RES_SUCCESS) { + return retv; + } +#if (ATM_SHA2_API == SHA_MULTI_CTXT) + // save context between each update + retv = sha2_save_context(ctxt, input, num_bytes); +#endif + return retv; +} + +static atm_sha256_res_t push_data_pio(void const *input, uint32_t num_bytes) +{ + uint8_t const *buf_ptr = input; + while (num_bytes) { + // poll for FIFO to drain before reloading the next block + while (!(CMSDK_SHA2->STATUS & + AT_SHA2_STATUS__FIFO_EMPTY__MASK)) { + YIELD(); + } + // clear the status bit (this is latched in) + CMSDK_SHA2->RESET_INTERRUPT = + AT_SHA2_RESET_INTERRUPT__INTRPT_RESET__MASK; + // SHA2 registers are not self-resetting. + CMSDK_SHA2->RESET_INTERRUPT = 0; + while ((!IS_ALIGNED(buf_ptr, sizeof(uint32_t))) && (num_bytes)) { + *((uint8_t volatile *)&CMSDK_SHA2->FIFO_PUSH) = *buf_ptr; + buf_ptr++; + num_bytes--; + } + uint32_t transfer_bytes = (num_bytes > SHA256_BLK_SIZE_BYTES) ? + SHA256_BLK_SIZE_BYTES : num_bytes; + uint32_t transfer_words = transfer_bytes / sizeof(uint32_t); + uint32_t remaining_bytes = transfer_bytes % sizeof(uint32_t); + while (transfer_words--) { + CMSDK_SHA2->FIFO_PUSH = *(const uint32_t *)buf_ptr; + buf_ptr += sizeof(uint32_t); + } + while (remaining_bytes--) { + *((uint8_t volatile *)&CMSDK_SHA2->FIFO_PUSH) = *buf_ptr; + buf_ptr++; + } + num_bytes -= transfer_bytes; + } + + return ATM_SHA256_RES_SUCCESS; +} + +atm_sha256_res_t +#if (ATM_SHA2_API == SHA_MULTI_CTXT) +atm_sha256_update_pio_ctxt(atm_sha2_ctxt_t *ctxt, void const *input, + uint32_t num_bytes) +#else +atm_sha256_update_pio(void const *input, uint32_t num_bytes) +#endif +{ + if (!num_bytes) { + return ATM_SHA256_RES_INVALID_INPUT_ERR; + } + atm_sha256_res_t retv; +#if (ATM_SHA2_API == SHA_MULTI_CTXT) + retv = sha2_load_context(ctxt, input, &num_bytes, push_data_pio); + if (retv != ATM_SHA256_RES_SUCCESS) { + if (retv == ATM_SHA256_RES_DEFER_PROC) { + retv = ATM_SHA256_RES_SUCCESS; + } + return retv; + } +#endif + SHA2_DUMP_BUFFER(input, num_bytes, "push user (PIO)"); + retv = push_data_pio(input, num_bytes); + if (retv != ATM_SHA256_RES_SUCCESS) { + return retv; + } +#if (ATM_SHA2_API == SHA_MULTI_CTXT) + retv = sha2_save_context(ctxt, input, num_bytes); +#endif + return retv; +} + +#if (ATM_SHA2_API == SHA_MULTI_CTXT) +atm_sha256_res_t atm_sha256_final_ctxt(atm_sha2_ctxt_t *ctxt, + uint8_t digest[SHA256_DIG_LEN]) +#else +uint8_t *atm_sha256_final(uint8_t digest[SHA256_DIG_LEN]) +#endif +{ +#if (ATM_SHA2_API == SHA_MULTI_CTXT) + atm_sha256_res_t retv = sha2_load_context(ctxt, NULL, NULL, push_data_pio); + if (retv != ATM_SHA256_RES_SUCCESS) { + return retv; + } + // sync before triggering hash process + sync_controller_ctxt(); +#endif + AT_SHA2_INTERRUPT_MASK__HMAC_DONE__SET( + CMSDK_SHA2->INTERRUPT_MASK); + CMSDK_SHA2->CMD = AT_SHA2_CMD__HASH_PROCESS__WRITE(1); + + DEBUG_TRACE_COND(ATM_SHA2_DEBUG, "SHA2 wait for hash done"); + while (!(CMSDK_SHA2->INTERRUPT_STATUS & + AT_SHA2_INTERRUPT_STATUS__HMAC_DONE__MASK)) { + YIELD(); + } + CMSDK_SHA2->RESET_INTERRUPT |= + AT_SHA2_INTERRUPT_STATUS__HMAC_DONE__MASK; + CMSDK_SHA2->RESET_INTERRUPT &= + ~AT_SHA2_INTERRUPT_STATUS__HMAC_DONE__MASK; + AT_SHA2_INTERRUPT_MASK__HMAC_DONE__CLR( + CMSDK_SHA2->INTERRUPT_MASK); + + if (IS_ALIGNED(digest, sizeof(uint32_t))) { + uint32_t *word_digest = (uint32_t *)digest; + // NOTE: digest gets reset when SHA is disabled + word_digest[0] = CMSDK_SHA2->DIGEST0; + word_digest[1] = CMSDK_SHA2->DIGEST1; + word_digest[2] = CMSDK_SHA2->DIGEST2; + word_digest[3] = CMSDK_SHA2->DIGEST3; + word_digest[4] = CMSDK_SHA2->DIGEST4; + word_digest[5] = CMSDK_SHA2->DIGEST5; + word_digest[6] = CMSDK_SHA2->DIGEST6; + word_digest[7] = CMSDK_SHA2->DIGEST7; + } else { + atm_set_le32(&digest[0], CMSDK_SHA2->DIGEST0); + atm_set_le32(&digest[4], CMSDK_SHA2->DIGEST1); + atm_set_le32(&digest[8], CMSDK_SHA2->DIGEST2); + atm_set_le32(&digest[12], CMSDK_SHA2->DIGEST3); + atm_set_le32(&digest[16], CMSDK_SHA2->DIGEST4); + atm_set_le32(&digest[20], CMSDK_SHA2->DIGEST5); + atm_set_le32(&digest[24], CMSDK_SHA2->DIGEST6); + atm_set_le32(&digest[28], CMSDK_SHA2->DIGEST7); + } +#if (ATM_SHA2_API == SHA_MULTI_CTXT) + ctxt->flags |= SHA2_CTXT_FLAGS_FINI; + DEBUG_TRACE_COND(ATM_SHA2_DEBUG, "SHA2 (%p) finalized", ctxt); + return ATM_SHA256_RES_SUCCESS; +#else + return digest; +#endif +} + +#if (ATM_SHA2_API == SHA_SINGLE_CTXT) +static atm_sha256_res_t +atm_sha256_digest_by_mode(atm_sha256_params_t const *params, void const *input, + uint32_t input_len, uint8_t digest[SHA256_DIG_LEN], bool pio) +{ + atm_sha256_res_t ret = atm_sha256_init(params); + + if (ret != ATM_SHA256_RES_SUCCESS) { + return ret; + } + if (pio) { + ret = atm_sha256_update_pio(input, input_len); + } else { + ret = atm_sha256_update(input, input_len); + } + if (ret != ATM_SHA256_RES_SUCCESS) { + goto digest_done; + } + atm_sha256_final(digest); + ret = ATM_SHA256_RES_SUCCESS; +digest_done: + atm_sha256_disable(); + return ret; +} + +atm_sha256_res_t atm_sha256_digest(atm_sha256_params_t const *params, + void const *input, uint32_t input_len, uint8_t digest[SHA256_DIG_LEN]) +{ + return atm_sha256_digest_by_mode(params, input, input_len, digest, false); +} + +atm_sha256_res_t atm_sha256_digest_pio(atm_sha256_params_t const *params, + void const *input, uint32_t input_len, uint8_t digest[SHA256_DIG_LEN]) +{ + return atm_sha256_digest_by_mode(params, input, input_len, digest, true); +} + +#endif diff --git a/ATM33xx-5/drivers/atm_sha2/atm_sha2.h b/ATM33xx-5/drivers/atm_sha2/atm_sha2.h new file mode 100644 index 0000000..af94efa --- /dev/null +++ b/ATM33xx-5/drivers/atm_sha2/atm_sha2.h @@ -0,0 +1,286 @@ +/** + ******************************************************************************* + * + * @file atm_sha2.h + * + * @brief Atmosic SHA256 driver + * + * Copyright (C) Atmosic 2022-2024 + * + ******************************************************************************* + */ + +#pragma once + +/** + ******************************************************************************* + * @defgroup ATM_SHA256 SHA 256 + * @ingroup DRIVERS + * @brief ATM SHA256 driver + * + * This module contains the necessary functions to compute SHA256. + * + * @{ + ******************************************************************************* + */ + +#include +#include +#include "compiler.h" +#define SHA_SINGLE_CTXT 1 +#define SHA_MULTI_CTXT 2 + +// By default the single context API is available. +// Multi-context APIs have to be explicitly enabled. +#if !defined(ATM_SHA2_API) +#define ATM_SHA2_API SHA_SINGLE_CTXT +#endif + +#if ((ATM_SHA2_API != SHA_SINGLE_CTXT) && (ATM_SHA2_API != SHA_MULTI_CTXT)) +#error "SHA2 API supports only SHA_SINGLE_CTXT or SHA_MULTI_CTXT" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/// digest length in bytes +#define SHA256_DIG_LEN 32 +/// digest length in words +#define SHA256_DIG_WORDS (SHA256_DIG_LEN / sizeof(uint32_t)) +/// HMAC key length in bytes +#define HMAC_KEY_LEN 32 +/// HMAC key length in words +#define HMAC_KEY_WORDS (HMAC_KEY_LEN / sizeof(uint32_t)) +/// SHA256 block size in bytes +#define SHA256_BLK_SIZE_BYTES 64 +/// SHA256 block size in bits (512) +#define SHA256_BLK_SIZE_BITS (SHA256_BLK_SIZE_BYTES * 8) + +typedef enum { + /// Success + ATM_SHA256_RES_SUCCESS, + /// Error reading SHA_ID + ATM_SHA256_RES_SHA_ID_ERR, + /// Error on input values + ATM_SHA256_RES_INVALID_INPUT_ERR, + /// Error from DMA engine + ATM_SHA256_RES_DMA_ERR, + /// invalid context + ATM_SHA256_RES_INVALID_CTXT, + /// inconsistency in context + ATM_SHA256_RES_ERR_CTXT, + /// Deferred processing + ATM_SHA256_RES_DEFER_PROC, +} atm_sha256_res_t; + +typedef enum { + /// compute little endian, do not enable HW swizzle + ATM_SHA256_ENDIANESS_LITTLE, + /// compute big endian, enable HW swizzle + ATM_SHA256_ENDIANESS_BIG, +} atm_sha256_endianess_t; + +typedef enum { + /// compute SHA256 + ATM_SHA256_SHA_MODE, + /// compute HMAC + ATM_SHA256_HMAC_MODE, + ATM_SHA256_MAX_MODE, +} atm_sha256_mode_t; + +typedef struct { + /// sha256 or hmac mode + atm_sha256_mode_t mode; + /// set hw byte swizzle + atm_sha256_endianess_t byte_endianess; + /// set hw digest swizzle. + atm_sha256_endianess_t digest_endianess; + /// key if in hmac mode + uint8_t const *key; +} atm_sha256_params_t; + +#if (ATM_SHA2_API == SHA_SINGLE_CTXT) +/** + * @brief Initialize SHA2 module + * + * @param[in] params parameters for initializing sha/hmac hardware + * @return atm_sha256_res_t result + */ +__NONNULL_ALL +atm_sha256_res_t atm_sha256_init(atm_sha256_params_t const *params); + + +/** + * @brief Disable SHA2 + * @note this will clear the digest registers, you must call + * atm_sha256_final() before this function to get the output. + * Should be called when the operation completes successfully or with an error. + */ +void atm_sha256_disable(void); + +/** + * @brief Stream more input data for an on-going SHA-256 calculation + * + * @note While this can be called an arbitrary amount of times, SHA256 + * algorithm has a max data limit equal to (2^64)-1 bits. If total + * accumulated data exceeds that, result is unpredictable + * + * @note If all of data is available in a contiguous buffer in memory, + * use atm_sha256_digest() instead. + * + * @param[in] input Pointer to the data the hash shall be calculated on + * @param[in] num_bytes Length of the input data, in bytes. + * @return atm_sha256_res_t result + */ +__NONNULL(1) +atm_sha256_res_t atm_sha256_update(void const *input, uint32_t num_bytes); + +/** + * @brief Identical to atm_sha256_update but doesn't use dma + * + * @param[in] input Pointer to the data the hash shall be calculated on + * @param[in] num_bytes Length of the input data, in bytes. + * @return atm_sha256_res_t result + */ +__NONNULL(1) +atm_sha256_res_t atm_sha256_update_pio(void const *input, + uint32_t num_bytes); + +/** + * @brief Get final digest + * + * @param[out] digest digest of SHA256 calculation + * @return uint8_t* pointer to the first element of passed digest + */ +uint8_t *atm_sha256_final(uint8_t digest[SHA256_DIG_LEN]); + +/** + * @brief Perform SHA-256 calculation on single contiguous memory chunk using + * DMA + * + * @param[in] params parameters for initializing sha/hmac hardware + * @param[in] input Pointer to the data the hash shall be calculated on + * @param[in] num_bytes Length of the input data, in bytes + * @param[out] digest digest of SHA256 calculation + * @return atm_sha256_res_t result + */ +__NONNULL(1,2) +atm_sha256_res_t atm_sha256_digest(atm_sha256_params_t const *params, + void const *input, uint32_t num_bytes, uint8_t digest[SHA256_DIG_LEN]); + +/** + * @brief Perform SHA-256 calculation on single contiguous memory chunk using + * PIO mode + * + * @param[in] params parameters for initializing sha/hmac hardware + * @param[in] input Pointer to the data the hash shall be calculated on + * @param[in] num_bytes Length of the input data, in bytes + * @param[out] digest digest of SHA256 calculation + * @return atm_sha256_res_t result + */ +atm_sha256_res_t atm_sha256_digest_pio(atm_sha256_params_t const *params, + void const *input, uint32_t num_bytes, uint8_t digest[SHA256_DIG_LEN]); + +#endif // ATM_SHA2_SINGLE_CTXT_API + +#if (ATM_SHA2_API == SHA_MULTI_CTXT) + +typedef struct { + /// context init magic + uint32_t magic; + /// flags + uint32_t flags; + /// saved control value + uint32_t control; + /// saved total message length in bits + uint64_t msg_len_bits; + /// saved total message length in bytes + uint32_t msg_len_bytes; + /// saved progress for SHA in bits + uint64_t sha_txcount_bits; + /// saved progress for HMAC in bits + uint64_t txcount_bits; + /// saved intermediate digest + uint32_t int_digest[SHA256_DIG_WORDS]; + /// partial block length + uint32_t partial_len; + /// saved partial block that needs to be replayed + uint8_t partial_block[SHA256_BLK_SIZE_BYTES]; + /// parameters for this context + atm_sha256_params_t const *params; +} atm_sha2_ctxt_t; + +// context has started +#define SHA2_CTXT_FLAGS_STARTED (1 << 0) +// context has finalized +#define SHA2_CTXT_FLAGS_FINI (1 << 1) + +/** + * @brief Initialize SHA2 module + * + * @param[in] params parameters for initializing sha/hmac hardware + * @param[out] ctxt context + * @return atm_sha256_res_t result + */ +__NONNULL_ALL +atm_sha256_res_t atm_sha256_init_ctxt(atm_sha256_params_t const *params, + atm_sha2_ctxt_t *ctxt); + +/** + * @brief Disable SHA2 + * @param[in,out] ctxt context + * @return atm_sha256_res_t result + * @note this will clear the digest registers, you must call + * atm_sha256_final_ctxt() before this function to get the output. + * Should be called when the operation completes successfully or with an error. + */ +__NONNULL_ALL +atm_sha256_res_t atm_sha256_disable_ctxt(atm_sha2_ctxt_t *ctxt); + +/** + * @brief Stream more input data for an on-going SHA-256 calculation + * + * @note While this can be called an arbitrary amount of times, SHA256 + * algorithm has a max data limit equal to (2^64)-1 bits. If total + * accumulated data exceeds that, result is unpredictable + * + * @param[in,out] ctxt context + * @param[in] input Pointer to the data the hash shall be calculated on + * @param[in] num_bytes Length of the input data, in bytes. + * @return atm_sha256_res_t result + */ +__NONNULL(1, 2) +atm_sha256_res_t atm_sha256_update_ctxt(atm_sha2_ctxt_t *ctxt, + void const *input, uint32_t num_bytes); + +/** + * @brief Identical to atm_sha256_update but doesn't use dma + * + * @param[in,out] ctxt context + * @param[in] input Pointer to the data the hash shall be calculated on + * @param[in] num_bytes Length of the input data, in bytes. + * @return atm_sha256_res_t result + */ +__NONNULL(1, 2) +atm_sha256_res_t atm_sha256_update_pio_ctxt(atm_sha2_ctxt_t *ctxt, + void const *input, uint32_t num_bytes); + +/** + * @brief Get final digest + * + * @param[in,out] ctxt context + * @param[out] digest digest of SHA256 calculation + * @return atm_sha256_res_t result + */ +__NONNULL(1) +atm_sha256_res_t atm_sha256_final_ctxt(atm_sha2_ctxt_t *ctxt, + uint8_t digest[SHA256_DIG_LEN]); + +#endif // (ATM_SHA2_API == SHA_MULTI_CTXT) + +#ifdef __cplusplus +} +#endif + +///@} diff --git a/ATM33xx-5/drivers/atm_sha2/sha256_alt.c b/ATM33xx-5/drivers/atm_sha2/sha256_alt.c new file mode 100644 index 0000000..8e0bb80 --- /dev/null +++ b/ATM33xx-5/drivers/atm_sha2/sha256_alt.c @@ -0,0 +1,100 @@ +/** + ******************************************************************************* + * + * @file sha256_alt.c + * + * @brief mbedtls glue for Atmosic SHA256 driver + * + * Copyright (C) Atmosic 2023 + * + ******************************************************************************* + */ + +#include "arch.h" +#include +#include "atm_sha2.h" + +#define MBEDTLS_ALLOW_PRIVATE_ACCESS + +#include "mbedtls/sha256.h" +#include "mbedtls/error.h" + +static mbedtls_sha256_context *hw_ctx; + +void mbedtls_sha256_init(mbedtls_sha256_context *ctx) +{ + if (hw_ctx == ctx) { + hw_ctx = NULL; + } + + ctx->state = MBEDTLS_SHA256_ALT_INIT; +} + +void mbedtls_sha256_free(mbedtls_sha256_context *ctx) +{ + if (!ctx) { + return; + } + + if (hw_ctx == ctx) { + hw_ctx = NULL; + } + + ctx->state = MBEDTLS_SHA256_ALT_FREE; +} + +int mbedtls_sha256_starts(mbedtls_sha256_context *ctx, int is224) +{ + if (is224) { + return MBEDTLS_ERR_SHA256_BAD_INPUT_DATA; + } + + hw_ctx = ctx; + ctx->state = MBEDTLS_SHA256_ALT_ACTIVE; + + atm_sha256_params_t const sha256_params = { + .mode = ATM_SHA256_SHA_MODE, + .byte_endianess = ATM_SHA256_ENDIANESS_BIG, + .digest_endianess = ATM_SHA256_ENDIANESS_BIG, + }; + + if (atm_sha256_init(&sha256_params) != ATM_SHA256_RES_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + return 0; +} + +int mbedtls_sha256_update(mbedtls_sha256_context *ctx, + const unsigned char *input, size_t ilen) +{ + if (hw_ctx != ctx) { + ctx->state = MBEDTLS_SHA256_ALT_ABORT; + return MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + } + if (ctx->state != MBEDTLS_SHA256_ALT_ACTIVE) { + return MBEDTLS_ERR_ERROR_GENERIC_ERROR; + } + + atm_sha256_res_t res = atm_sha256_update(input, ilen); + if (res == ATM_SHA256_RES_DMA_ERR) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + return 0; +} + +int mbedtls_sha256_finish(mbedtls_sha256_context *ctx, unsigned char *output) +{ + if (hw_ctx != ctx) { + ctx->state = MBEDTLS_SHA256_ALT_ABORT; + return MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + } + if (ctx->state != MBEDTLS_SHA256_ALT_ACTIVE) { + return MBEDTLS_ERR_ERROR_GENERIC_ERROR; + } + + atm_sha256_final(output); + + return 0; +} diff --git a/ATM33xx-5/drivers/atm_sha2/sha256_alt.h b/ATM33xx-5/drivers/atm_sha2/sha256_alt.h new file mode 100644 index 0000000..3825154 --- /dev/null +++ b/ATM33xx-5/drivers/atm_sha2/sha256_alt.h @@ -0,0 +1,25 @@ +/** + ******************************************************************************* + * + * @file sha256_alt.h + * + * @brief mbedtls glue for Atmosic SHA256 driver + * + * Copyright (C) Atmosic 2023 + * + ******************************************************************************* + */ + +#pragma once + +typedef enum { + MBEDTLS_SHA256_ALT_UNINIT = 0, + MBEDTLS_SHA256_ALT_INIT, + MBEDTLS_SHA256_ALT_FREE, + MBEDTLS_SHA256_ALT_ACTIVE, + MBEDTLS_SHA256_ALT_ABORT, +} sha256_alt_state_t; + +typedef struct mbedtls_sha256_context { + sha256_alt_state_t MBEDTLS_PRIVATE(state); +} mbedtls_sha256_context; diff --git a/ATM33xx-5/drivers/atmwstk/atmwstk.c b/ATM33xx-5/drivers/atmwstk/atmwstk.c new file mode 100644 index 0000000..4a5c474 --- /dev/null +++ b/ATM33xx-5/drivers/atmwstk/atmwstk.c @@ -0,0 +1,96 @@ +/** + ******************************************************************************* + * + * @file atmwstk.c + * + * @brief Application support for separate wireless stack image + * + * Copyright (C) Atmosic 2021-2024 + * + ******************************************************************************* + */ + +#ifdef CONFIG_SOC_FAMILY_ATM +#include +#include +#include +#include +#include +#endif + +#include "arch.h" +#include +#include +#include "atmwstk.h" +#ifndef CONFIG_SOC_FAMILY_ATM +#include "atm_ecc_port.h" +#endif + +#ifdef CONFIG_SOC_FAMILY_ATM +static int atmwstk_rand(void) +{ + return (sys_rand32_get()); +} + +static void atmwstk_srand(unsigned int seed) +{ +} + +#if PLF_DEBUG +static int atmwstk_putchar(int c) +{ + return putc(c, stdout); +} +#endif + +static int atmwstk_init(void) +{ + static libc_iface_t const libc_iface = { + .rf_init = rf_init, + .free = k_free, + .malloc = k_malloc, + .memcmp = memcmp, + .memmove = memmove, + .rand = atmwstk_rand, + .srand = atmwstk_srand, + .strncmp = strncmp, +#if PLF_DEBUG + .vprintf = vprintf, + .putchar = atmwstk_putchar, + .strlen = strlen, +#endif + }; + + atmwstk_main(&libc_iface); + + return 0; +} + +SYS_INIT(atmwstk_init, PRE_KERNEL_1, 1); +#else // CONFIG_SOC_FAMILY_ATM +__CONSTRUCTOR_PRIO(CONSTRUCTOR_WATCHDOG) +// NOTE: constructor function must be static for priority to be applied +static void atmwstk_init_constructor(void) +{ + static libc_iface_t const libc_iface = { + .rf_init = rf_init, + .free = free, + .malloc = malloc, + .memcmp = memcmp, + .memmove = memmove, + .rand = rand, + .srand = srand, + .strncmp = strncmp, +#if PLF_DEBUG + .vprintf = vprintf, + .putchar = putchar, + .strlen = strlen, +#endif + .ecc_valid_public_key_256r1 = ecc_valid_public_key_256r1, + .ecc_compute_public_key_256r1 = ecc_compute_public_key_256r1, + .ecc_shared_secret_256r1 = ecc_shared_secret_256r1, + }; + + atmwstk_main(&libc_iface); +} +#endif // CONFIG_SOC_FAMILY_ATM diff --git a/ATM33xx-5/drivers/atmwstk/atmwstk.h b/ATM33xx-5/drivers/atmwstk/atmwstk.h new file mode 100644 index 0000000..bcd834a --- /dev/null +++ b/ATM33xx-5/drivers/atmwstk/atmwstk.h @@ -0,0 +1,68 @@ +/** + ******************************************************************************* + * + * @file atmwstk.h + * + * @brief Application support for separate wireless stack image + * + * Copyright (C) Atmosic 2021-2024 + * + ******************************************************************************* + */ + +#pragma once + +/** + * @defgroup ATMWSTK Atmosic wireless stack + * @ingroup DRIVERS + * @brief Application support for separate wireless stack image + * @{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct rwip_rf_api; + +#ifdef __ICCARM__ +#define __VALIST __Va_list +#elif defined(__ARMCC_VERSION) +#define __VALIST va_list +#elif defined(CONFIG_SOC_FAMILY_ATM) && !defined(__VALIST) +#define __VALIST __gnuc_va_list +#endif + +/// Akin to shared library PLT +typedef struct { + void (*rf_init)(struct rwip_rf_api *api); + void (*free)(void *__ptr); + void *(*malloc)(size_t __size); + int (*memcmp)(const void *__s1, const void *__s2, size_t __n); + void *(*memmove)(void *__dest, const void *__src, size_t __n); + int (*rand)(void); + void (*srand)(unsigned int __seed); + int (*strncmp)(const char *__s1, const char *__s2, size_t __n); + int (*vprintf)(const char *__fmt, __VALIST __va); + int (*putchar)(int _c); + size_t (*strlen)(const char *__s); + int (*ecc_valid_public_key_256r1)(uint8_t const *pub_key); + void (*ecc_compute_public_key_256r1)(uint8_t const *priv_key, + uint8_t *pub_key); + void (*ecc_shared_secret_256r1)(uint8_t const *pub_key, + uint8_t const *priv_key, uint8_t *secret); +} libc_iface_t; + +/** + * @brief Entry point for separate image + * @param[in] libc_iface External functions needed by wireless stack. + */ +void atmwstk_main(libc_iface_t const *libc_iface); + +#ifdef __cplusplus +} +#endif + +/// @} ATMWSTK diff --git a/ATM33xx-5/drivers/atmwstk/atmwstk_CPD200_sha.h b/ATM33xx-5/drivers/atmwstk/atmwstk_CPD200_sha.h new file mode 100644 index 0000000..3439f48 --- /dev/null +++ b/ATM33xx-5/drivers/atmwstk/atmwstk_CPD200_sha.h @@ -0,0 +1,16 @@ +/** +******************************************************************************* + * + * @file atmwstk_CPD200_sha.h + * + * @brief Generated header file for atmwstk integrity checking + * + * Copyright (C) Atmosic 2024 + * + ******************************************************************************* + */ +#pragma once + +#define ATMWSTK_SHA {0x2bf33288, 0xeff61043, 0x045843d8, 0xfc4edbd4, 0xcf717fd6, 0xed3d0d59, 0xf93b1af7, 0x27378ab3} +#define ATMWSTK_SIZE 236032 +#define ATMWSTK_START 0x00055000 diff --git a/ATM33xx-5/drivers/atmwstk/atmwstk_PD100_sha.h b/ATM33xx-5/drivers/atmwstk/atmwstk_PD100_sha.h new file mode 100644 index 0000000..ef12d25 --- /dev/null +++ b/ATM33xx-5/drivers/atmwstk/atmwstk_PD100_sha.h @@ -0,0 +1,16 @@ +/** +******************************************************************************* + * + * @file atmwstk_PD100_sha.h + * + * @brief Generated header file for atmwstk integrity checking + * + * Copyright (C) Atmosic 2024 + * + ******************************************************************************* + */ +#pragma once + +#define ATMWSTK_SHA {0x765a9eab, 0x922eabcc, 0x92fe8b8f, 0x11a43979, 0xe7c2e21d, 0x9a08dcf9, 0x4b3daf84, 0x7d127f85} +#define ATMWSTK_SIZE 175332 +#define ATMWSTK_START 0x00064000 diff --git a/ATM33xx-5/drivers/atmwstk/atmwstk_PD150_sha.h b/ATM33xx-5/drivers/atmwstk/atmwstk_PD150_sha.h new file mode 100644 index 0000000..2fc8931 --- /dev/null +++ b/ATM33xx-5/drivers/atmwstk/atmwstk_PD150_sha.h @@ -0,0 +1,16 @@ +/** +******************************************************************************* + * + * @file atmwstk_PD150_sha.h + * + * @brief Generated header file for atmwstk integrity checking + * + * Copyright (C) Atmosic 2024 + * + ******************************************************************************* + */ +#pragma once + +#define ATMWSTK_SHA {0x716fa9d3, 0xa21e187d, 0xb58cefe0, 0xb0b698e0, 0xb6f70cfb, 0x3f8c21fc, 0x159bb469, 0x5fb0c207} +#define ATMWSTK_SIZE 200028 +#define ATMWSTK_START 0x0005e800 diff --git a/ATM33xx-5/drivers/dma/dma.h b/ATM33xx-5/drivers/dma/dma.h new file mode 100644 index 0000000..445a3aa --- /dev/null +++ b/ATM33xx-5/drivers/dma/dma.h @@ -0,0 +1,109 @@ +/** + **************************************************************************************** + * + * @file dma.h + * + * @brief DMA driver for memory copy + * + * Copyright (C) RivieraWaves 2009-2019 + * + * Copyright (C) Atmosic 2020-2023 + * + **************************************************************************************** + */ + +#ifndef DMA_H_ +#define DMA_H_ + +/** + **************************************************************************************** + * @addtogroup DMA + * @ingroup DRIVERS + * @brief DMA driver for memory copy + * + * @{ + **************************************************************************************** + */ + +/* + * INCLUDES + **************************************************************************************** + */ +#include + +/* + * DEFINES + **************************************************************************************** + */ + +/// List of available DMA channels +enum dma_channels +{ + /// DMA Channel reserved for data path + DMA_CHAN_DATA_PATH = 0, + /// DMA Channel available for other operation + DMA_CHAN_UNUSED, + + DMA_CHAN_MAX, +}; + +enum dma_fifo_rx_port { + DMA_FIFO_RX_UART0 = 0, + DMA_FIFO_RX_UART1 = 1, + DMA_FIFO_RX_PDM0 = 2, + DMA_FIFO_RX_PDM1 = 3, + DMA_FIFO_RX_I2S = 4, + DMA_FIFO_RX_RSVD = 5, +}; + +enum dma_fifo_tx_port { + DMA_FIFO_TX_UART0 = 0, + DMA_FIFO_TX_UART1 = 1, + DMA_FIFO_TX_RSVD = 2, + DMA_FIFO_TX_RSVD1 = 3, + DMA_FIFO_TX_I2S = 4, + DMA_FIFO_TX_PWM = 5, +}; + +typedef void (*dma_cb_t)(void const *ctx); + +/* + * FUNCTION DECLARATIONS + **************************************************************************************** + */ + +void *dma_memcpy(void *d, const void *s, size_t n); +void *dma_memset(void *m, int c, size_t n); + +void dma_fifo_rx_async(enum dma_fifo_rx_port port, void *dst, size_t len, + dma_cb_t cb, void const *ctx); +void dma_fifo_tx_async(enum dma_fifo_tx_port port, const void *src, size_t len, + dma_cb_t cb, void const *ctx); + +/** + * @brief Request an address to address memory copy using a DMA block (non blocking). + * + * If this function is called while DMA channel is in use, function is blocked till DMA channel is released + * + * @param[in] channel DMA channel used (@see enum dma_channels) + * @param[in] p_dst_addr Destination address of the memory copy + * @param[in] p_src_addr Source address of the memory copy + * @param[in] size Size of data to copy in octets. + */ +void dma_copy(uint8_t channel, void* p_dst_addr, const void* p_src_addr, uint16_t size); + +/** + * @brief Fetch power management status + * @param[in,out] min_freq Minimum frequency required by pending operations + * @return Avoid power saving modes when true + */ +bool dma_is_active(uint32_t *min_freq); + +/** + * @brief initialize DMA subsystem + */ +void dma_init(void); + +/// @} DMA + +#endif // DMA_H_ diff --git a/ATM33xx-5/drivers/micro-ecc/ecdsa_alt.c b/ATM33xx-5/drivers/micro-ecc/ecdsa_alt.c new file mode 100644 index 0000000..e09b073 --- /dev/null +++ b/ATM33xx-5/drivers/micro-ecc/ecdsa_alt.c @@ -0,0 +1,263 @@ +/** + ******************************************************************************* + * + * @file ecdsa_alt.c + * + * @brief mbedtls glue for uECC library + * + * Copyright (C) Atmosic 2023-2024 + * + ******************************************************************************* + */ + +#ifdef CONFIG_SOC_FAMILY_ATM +#include +#include + +static int default_RNG(uint8_t *dest, unsigned size) +{ + // use cryptographically secure rand + return !sys_csrand_get(dest, size); +} + +#define default_RNG_defined 1 +#endif // CONFIG_SOC_FAMILY_ATM + +#define MBEDTLS_ALLOW_PRIVATE_ACCESS + +#include "mbedtls/ecdsa.h" + +#define uECC_OPTIMIZATION_LEVEL 4 +#define uECC_SUPPORTS_secp160r1 0 +#ifndef MBEDTLS_ECP_DP_SECP192R1_ENABLED +#define uECC_SUPPORTS_secp192r1 0 +#endif +#ifndef MBEDTLS_ECP_DP_SECP224R1_ENABLED +#define uECC_SUPPORTS_secp224r1 0 +#endif +#ifndef MBEDTLS_ECP_DP_SECP256R1_ENABLED +#define uECC_SUPPORTS_secp256r1 0 +#endif +#ifndef MBEDTLS_ECP_DP_SECP256K1_ENABLED +#define uECC_SUPPORTS_secp256k1 0 +#endif +#define uECC_SUPPORT_COMPRESSED_POINT 0 + +#include "uECC.c" + +#ifdef MBEDTLS_ECDSA_GENKEY_ALT +int mbedtls_ecdsa_genkey(mbedtls_ecdsa_context *ctx, mbedtls_ecp_group_id gid, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng) +{ + int ret = mbedtls_ecp_group_load(&ctx->grp, gid); + if (ret) { + return ret; + } + + uECC_Curve curve; + + switch (gid) { +#ifdef MBEDTLS_ECP_DP_SECP192R1_ENABLED + case MBEDTLS_ECP_DP_SECP192R1: + curve = uECC_secp192r1(); + break; +#endif +#ifdef MBEDTLS_ECP_DP_SECP224R1_ENABLED + case MBEDTLS_ECP_DP_SECP224R1: + curve = uECC_secp224r1(); + break; +#endif +#ifdef MBEDTLS_ECP_DP_SECP256R1_ENABLED + case MBEDTLS_ECP_DP_SECP256R1: + curve = uECC_secp256r1(); + break; +#endif +#ifdef MBEDTLS_ECP_DP_SECP256K1_ENABLED + case MBEDTLS_ECP_DP_SECP256K1: + curve = uECC_secp256k1(); + break; +#endif + default: + return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + } + + size_t plen = ctx->grp.nbits / 8U; + uint8_t q_buf[plen * 2U]; + uint8_t d_buf[plen]; + + if (!uECC_make_key(q_buf, d_buf, curve)) { + return MBEDTLS_ERR_ECP_RANDOM_FAILED; + } + + ret = mbedtls_mpi_read_binary(&ctx->d, d_buf, plen); + if (ret) { + return ret; + } + + ret = mbedtls_mpi_read_binary(&(ctx->Q.X), q_buf, plen); + if (ret) { + return ret; + } + + ret = mbedtls_mpi_read_binary(&(ctx->Q.Y), q_buf + plen, plen); + if (ret) { + return ret; + } + + ret = mbedtls_mpi_lset(&(ctx->Q.Z), 1); + if (ret) { + return ret; + } + + return 0; +} +#endif + +#ifdef MBEDTLS_ECDSA_SIGN_ALT +int mbedtls_ecdsa_can_do(mbedtls_ecp_group_id gid) +{ + switch (gid) { +#ifdef MBEDTLS_ECP_DP_SECP192R1_ENABLED + case MBEDTLS_ECP_DP_SECP192R1: + return 1; +#endif +#ifdef MBEDTLS_ECP_DP_SECP224R1_ENABLED + case MBEDTLS_ECP_DP_SECP224R1: + return 1; +#endif +#ifdef MBEDTLS_ECP_DP_SECP256R1_ENABLED + case MBEDTLS_ECP_DP_SECP256R1: + return 1; +#endif +#ifdef MBEDTLS_ECP_DP_SECP256K1_ENABLED + case MBEDTLS_ECP_DP_SECP256K1: + return 1; +#endif + default: + break; + } + + return 0; +} + +int mbedtls_ecdsa_sign(mbedtls_ecp_group *grp, mbedtls_mpi *r, mbedtls_mpi *s, + const mbedtls_mpi *d, const unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng) +{ + uECC_Curve curve; + + switch (grp->id) { +#ifdef MBEDTLS_ECP_DP_SECP192R1_ENABLED + case MBEDTLS_ECP_DP_SECP192R1: + curve = uECC_secp192r1(); + break; +#endif +#ifdef MBEDTLS_ECP_DP_SECP224R1_ENABLED + case MBEDTLS_ECP_DP_SECP224R1: + curve = uECC_secp224r1(); + break; +#endif +#ifdef MBEDTLS_ECP_DP_SECP256R1_ENABLED + case MBEDTLS_ECP_DP_SECP256R1: + curve = uECC_secp256r1(); + break; +#endif +#ifdef MBEDTLS_ECP_DP_SECP256K1_ENABLED + case MBEDTLS_ECP_DP_SECP256K1: + curve = uECC_secp256k1(); + break; +#endif + default: + return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + } + + size_t plen = grp->nbits / 8U; + uint8_t d_buf[plen]; + uint8_t sig_buf[plen * 2U]; + + int ret = mbedtls_mpi_write_binary(d, d_buf, plen); + if (ret) { + return ret; + } + + if (!uECC_sign(d_buf, buf, blen, sig_buf, curve)) { + return MBEDTLS_ERR_ECP_RANDOM_FAILED; + } + + ret = mbedtls_mpi_read_binary(r, sig_buf, plen); + if (ret) { + return ret; + } + + ret = mbedtls_mpi_read_binary(s, sig_buf + plen, plen); + if (ret) { + return ret; + } + + return 0; +} +#endif // MBEDTLS_ECDSA_SIGN_ALT + +#ifdef MBEDTLS_ECDSA_VERIFY_ALT +int mbedtls_ecdsa_verify(mbedtls_ecp_group *grp, const unsigned char *buf, + size_t blen, const mbedtls_ecp_point *Q, const mbedtls_mpi *r, + const mbedtls_mpi *s) +{ + uECC_Curve curve; + + switch (grp->id) { +#ifdef MBEDTLS_ECP_DP_SECP192R1_ENABLED + case MBEDTLS_ECP_DP_SECP192R1: + curve = uECC_secp192r1(); + break; +#endif +#ifdef MBEDTLS_ECP_DP_SECP224R1_ENABLED + case MBEDTLS_ECP_DP_SECP224R1: + curve = uECC_secp224r1(); + break; +#endif +#ifdef MBEDTLS_ECP_DP_SECP256R1_ENABLED + case MBEDTLS_ECP_DP_SECP256R1: + curve = uECC_secp256r1(); + break; +#endif +#ifdef MBEDTLS_ECP_DP_SECP256K1_ENABLED + case MBEDTLS_ECP_DP_SECP256K1: + curve = uECC_secp256k1(); + break; +#endif + default: + return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + } + + size_t plen = grp->nbits / 8U; + uint8_t q_buf[plen * 2U]; + uint8_t sig_buf[plen * 2U]; + + int ret = mbedtls_mpi_write_binary(&(Q->X), q_buf, plen); + if (ret) { + return ret; + } + + ret = mbedtls_mpi_write_binary(&(Q->Y), q_buf + plen, plen); + if (ret) { + return ret; + } + + ret = mbedtls_mpi_write_binary(r, sig_buf, plen); + if (ret) { + return ret; + } + + ret = mbedtls_mpi_write_binary(s, sig_buf + plen, plen); + if (ret) { + return ret; + } + + if (!uECC_verify(q_buf, buf, blen, sig_buf, curve)) { + return MBEDTLS_ERR_ECP_VERIFY_FAILED; + } + + return 0; +} +#endif // MBEDTLS_ECDSA_VERIFY_ALT diff --git a/ATM33xx-5/drivers/rep_vec/rep_vec.h b/ATM33xx-5/drivers/rep_vec/rep_vec.h new file mode 100644 index 0000000..10593cc --- /dev/null +++ b/ATM33xx-5/drivers/rep_vec/rep_vec.h @@ -0,0 +1,517 @@ +/** + ******************************************************************************* + * + * @file rep_vec.h + * + * @brief Replacement vectors for strategic code paths + * + * Copyright (C) Atmosic 2017-2022 + * + ******************************************************************************* + */ + +#pragma once + +#define REP_VEC + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/// Generic add helper macro +#define RV_ADD(__t, __v, __f) do { \ + static rep_vec ## __t ## t user_ ## __v = { __f, NULL }; \ + rep_vec ## __t ## add(&__v, &user_ ## __v); \ +} while(0) + +/// Generic add_last helper macro +#define RV_ADD_LAST(__t, __v, __f) do { \ + static rep_vec ## __t ## t user_ ## __v = { __f, NULL }; \ + rep_vec ## __t ## add_last(&__v, &user_ ## __v); \ +} while(0) + +typedef enum rep_vec_err_e { + RV_DONE = 0, + RV_NEXT +} rep_vec_err_t; + + +/* void fn(void) */ +typedef rep_vec_err_t (*rep_vec_fn_t)(void); + +typedef struct rep_vec_s { + rep_vec_fn_t fn; + struct rep_vec_s *next; +} rep_vec_t; + +void rep_vec_add(rep_vec_t **head, rep_vec_t *new_entry); +void rep_vec_add_last(rep_vec_t **head, rep_vec_t *new_entry); +void rep_vec_invoke(rep_vec_t *rv, void (*def_fn)(void)); + +/** + * @brief After all active events have been processed by the main event loop, + * this vector is invoked before interrupts are disabled and power saving + * modes are handled. + */ +extern rep_vec_t *rv_plf_schedule; +#define RV_PLF_SCHEDULE_ADD(__f) RV_ADD(_, rv_plf_schedule, __f) +#define RV_PLF_SCHEDULE_ADD_LAST(__f) RV_ADD_LAST(_, rv_plf_schedule, __f) + +/** + * @brief When a system reset is requested, this vector will be invoked after + * interrupts are globally disabled but before asserting the hardware reset. + * It is the absolute last opportunity for drivers to take action before + * all system state is lost. + */ +extern rep_vec_t *rv_plf_reset; +#define RV_PLF_RESET_ADD(__f) RV_ADD(_, rv_plf_reset, __f) +#define RV_PLF_RESET_ADD_LAST(__f) RV_ADD_LAST(_, rv_plf_reset, __f) + +/** + * @brief At the end of BLE device initialization, this vector will be invoked + * to initialize the BLE application layer. It provides the final opportunity + * for customization before the main event loop is entered. + */ +extern rep_vec_t *rv_appm_init; +#define RV_APPM_INIT_ADD(__f) RV_ADD(_, rv_appm_init, __f) +#define RV_APPM_INIT_ADD_LAST(__f) RV_ADD_LAST(_, rv_appm_init, __f) + +/** + * @brief Invoked after the BLE sleep duration has been computed but before + * BLE sleep has been requested. + */ +extern rep_vec_t *rv_rf_sleep; +#define RV_RF_SLEEP_ADD(__f) RV_ADD(_, rv_rf_sleep, __f) +#define RV_RF_SLEEP_ADD_LAST(__f) RV_ADD_LAST(_, rv_rf_sleep, __f) + +/** + * @brief Invoked at interrupt level near the end of IP_SLPINTSTAT handler. + */ +extern rep_vec_t *rv_rf_wake; +#define RV_RF_WAKE_ADD(__f) RV_ADD(_, rv_rf_wake, __f) +#define RV_RF_WAKE_ADD_LAST(__f) RV_ADD_LAST(_, rv_rf_wake, __f) + +/** + * @brief This vector permits customization of the power saving logic. + * See driver/pseq for more information. + */ +extern rep_vec_t *rv_plf_back_from_retain_all; +#define RV_PLF_BACK_FROM_RETAIN_ALL_ADD(__f) \ + RV_ADD(_, rv_plf_back_from_retain_all, __f) +#define RV_PLF_BACK_FROM_RETAIN_ALL_ADD_LAST(__f) \ + RV_ADD_LAST(_, rv_plf_back_from_retain_all, __f) + +/** + * @brief Invoked after rwip reset is complete + */ +extern rep_vec_t *rv_notify_rwip_reset_cmpl; +#define RV_NOTIFY_RWIP_RESET_CMPL_ADD(__f) \ + RV_ADD(_, rv_notify_rwip_reset_cmpl, __f) +#define RV_NOTIFY_RWIP_RESET_CMPL_ADD_LAST(__f) \ + RV_ADD_LAST(_, rv_notify_rwip_reset_cmpl, __f) + + +/* const struct prf_task_cbs *fn(uint8_t) */ +struct prf_task_cbs; + +typedef rep_vec_err_t (*rep_vec_fn__ret_const_struct_prf_task_cbs_p__uint8_t__t)(const struct prf_task_cbs **, uint8_t); + +typedef struct rep_vec__ret_const_struct_prf_task_cbs_p__uint8_t__s { + rep_vec_fn__ret_const_struct_prf_task_cbs_p__uint8_t__t fn; + struct rep_vec__ret_const_struct_prf_task_cbs_p__uint8_t__s *next; +} rep_vec__ret_const_struct_prf_task_cbs_p__uint8_t__t; + +void +rep_vec__ret_const_struct_prf_task_cbs_p__uint8_t__add( + rep_vec__ret_const_struct_prf_task_cbs_p__uint8_t__t **head, + rep_vec__ret_const_struct_prf_task_cbs_p__uint8_t__t *new_entry); +void +rep_vec__ret_const_struct_prf_task_cbs_p__uint8_t__add_last( + rep_vec__ret_const_struct_prf_task_cbs_p__uint8_t__t **head, + rep_vec__ret_const_struct_prf_task_cbs_p__uint8_t__t *new_entry); +const struct prf_task_cbs * +rep_vec__ret_const_struct_prf_task_cbs_p__uint8_t__invoke( + rep_vec__ret_const_struct_prf_task_cbs_p__uint8_t__t *rv, + const struct prf_task_cbs *(*def_fn)(uint8_t), + uint8_t prf_id); + +/** + * @brief Along with rv_prf_id_get, this vector supports the addition and + * replacement of BLE profiles. See the HCI example for more information. + * @param[in] prf_id Profile ID + * @return Pointer to profile task callbacks + */ +extern rep_vec__ret_const_struct_prf_task_cbs_p__uint8_t__t *rv_prf_itf_get; +#define RV_PRF_ITF_GET_ADD(__f) \ + RV_ADD(__ret_const_struct_prf_task_cbs_p__uint8_t__, rv_prf_itf_get, __f) +#define RV_PRF_ITF_GET_ADD_LAST(__f) \ + RV_ADD_LAST(__ret_const_struct_prf_task_cbs_p__uint8_t__, rv_prf_itf_get, __f) + + +/* uint8_t fn(uint8_t) */ +typedef rep_vec_err_t (*rep_vec_fn__ret_uint8_t__uint8_t__t)(uint8_t *, uint8_t); + +typedef struct rep_vec__ret_uint8_t__uint8_t__s { + rep_vec_fn__ret_uint8_t__uint8_t__t fn; + struct rep_vec__ret_uint8_t__uint8_t__s *next; +} rep_vec__ret_uint8_t__uint8_t__t; + +void +rep_vec__ret_uint8_t__uint8_t__add( + rep_vec__ret_uint8_t__uint8_t__t **head, + rep_vec__ret_uint8_t__uint8_t__t *new_entry); +void +rep_vec__ret_uint8_t__uint8_t__add_last( + rep_vec__ret_uint8_t__uint8_t__t **head, + rep_vec__ret_uint8_t__uint8_t__t *new_entry); +uint8_t +rep_vec__ret_uint8_t__uint8_t__invoke( + rep_vec__ret_uint8_t__uint8_t__t *rv, + uint8_t (*def_fn)(uint8_t), + uint8_t api_id); + +/** + * @brief Along with rv_prf_itf_get, this vector supports the addition and + * replacement of BLE profiles. See the HCI example for more information. + * @param[in] api_id API ID + * @return Profile ID + */ +extern rep_vec__ret_uint8_t__uint8_t__t *rv_prf_id_get; +#define RV_PRF_ID_GET_ADD(__f) \ + RV_ADD(__ret_uint8_t__uint8_t__, rv_prf_id_get, __f) +#define RV_PRF_ID_GET_ADD_LAST(__f) \ + RV_ADD_LAST(__ret_uint8_t__uint8_t__, rv_prf_id_get, __f) + + +/* const struct rwip_eif_api *fn(uint8_t) */ +struct rwip_eif_api; + +typedef rep_vec_err_t (*rep_vec_fn__ret_const_struct_rwip_eif_api_p__uint8_t__t)(const struct rwip_eif_api **, uint8_t); + +typedef struct rep_vec__ret_const_struct_rwip_eif_api_p__uint8_t__s { + rep_vec_fn__ret_const_struct_rwip_eif_api_p__uint8_t__t fn; + struct rep_vec__ret_const_struct_rwip_eif_api_p__uint8_t__s *next; +} rep_vec__ret_const_struct_rwip_eif_api_p__uint8_t__t; + +void +rep_vec__ret_const_struct_rwip_eif_api_p__uint8_t__add( + rep_vec__ret_const_struct_rwip_eif_api_p__uint8_t__t **head, + rep_vec__ret_const_struct_rwip_eif_api_p__uint8_t__t *new_entry); +void +rep_vec__ret_const_struct_rwip_eif_api_p__uint8_t__add_last( + rep_vec__ret_const_struct_rwip_eif_api_p__uint8_t__t **head, + rep_vec__ret_const_struct_rwip_eif_api_p__uint8_t__t *new_entry); +const struct rwip_eif_api * +rep_vec__ret_const_struct_rwip_eif_api_p__uint8_t__invoke( + rep_vec__ret_const_struct_rwip_eif_api_p__uint8_t__t *rv, + const struct rwip_eif_api *(*def_fn)(uint8_t), + uint8_t idx); + +/** + * @brief Function to retrieve each external interface API + * @param[in] idx External interface index + * @return External interface api structure + */ +extern rep_vec__ret_const_struct_rwip_eif_api_p__uint8_t__t *rv_rwip_eif_get; +#define RV_RWIP_EIF_GET_ADD(__f) \ + RV_ADD(__ret_const_struct_rwip_eif_api_p__uint8_t__, rv_rwip_eif_get, __f) +#define RV_RWIP_EIF_GET_ADD_LAST(__f) \ + RV_ADD_LAST(__ret_const_struct_rwip_eif_api_p__uint8_t__, rv_rwip_eif_get, __f) + + +/* bool fn(void) */ +typedef rep_vec_err_t (*rep_vec_fn__ret_bool__t)(bool *); + +typedef struct rep_vec__ret_bool__s { + rep_vec_fn__ret_bool__t fn; + struct rep_vec__ret_bool__s *next; +} rep_vec__ret_bool__t; + +void +rep_vec__ret_bool__add(rep_vec__ret_bool__t **head, + rep_vec__ret_bool__t *new_entry); +void +rep_vec__ret_bool__add_last(rep_vec__ret_bool__t **head, + rep_vec__ret_bool__t *new_entry); +bool +rep_vec__ret_bool__invoke(rep_vec__ret_bool__t *rv, bool (*def_fn)(void)); + +/** + * @brief This vector can be used to prevent the BLE module from entering + * sleep. It will also prevent the rest of the system from entering any power + * saving mode. + * @return true to prevent sleep + */ +extern rep_vec__ret_bool__t *rv_prevent_ble_sleep; +#define RV_PREVENT_BLE_SLEEP_ADD(__f) \ + RV_ADD(__ret_bool__, rv_prevent_ble_sleep, __f) +#define RV_PREVENT_BLE_SLEEP_ADD_LAST(__f) \ + RV_ADD_LAST(__ret_bool__, rv_prevent_ble_sleep, __f) + + +/* uint32_t fn(void) */ +typedef rep_vec_err_t (*rep_vec_fn__ret_uint32_t__t)(uint32_t *); + +typedef struct rep_vec__ret_uint32_t__s { + rep_vec_fn__ret_uint32_t__t fn; + struct rep_vec__ret_uint32_t__s *next; +} rep_vec__ret_uint32_t__t; + +void +rep_vec__ret_uint32_t__add(rep_vec__ret_uint32_t__t **head, + rep_vec__ret_uint32_t__t *new_entry); +void +rep_vec__ret_uint32_t__add_last(rep_vec__ret_uint32_t__t **head, + rep_vec__ret_uint32_t__t *new_entry); +uint32_t +rep_vec__ret_uint32_t__invoke(rep_vec__ret_uint32_t__t *rv, + uint32_t (*def_fn)(void)); + +/** + * @brief This vector can be used to provide a secure source of random numbers + * to various BLE security functions, such as key generation. See driver/trng + * for more information. + * @return Secure random word + */ +extern rep_vec__ret_uint32_t__t *rv_secure_rand_word; +#define RV_SECURE_RAND_WORD_ADD(__f) \ + RV_ADD(__ret_uint32_t__, rv_secure_rand_word, __f) +#define RV_SECURE_RAND_WORD_ADD_LAST(__f) \ + RV_ADD_LAST(__ret_uint32_t__, rv_secure_rand_word, __f) + + +/* bool fn(int32_t *, int32_t) */ +typedef rep_vec_err_t (*rep_vec_fn__ret_bool__int32_t_p__int32_t__t)(bool *, int32_t *, int32_t); + +typedef struct rep_vec__ret_bool__int32_t_p__int32_t__s { + rep_vec_fn__ret_bool__int32_t_p__int32_t__t fn; + struct rep_vec__ret_bool__int32_t_p__int32_t__s *next; +} rep_vec__ret_bool__int32_t_p__int32_t__t; + +void +rep_vec__ret_bool__int32_t_p__int32_t__add( + rep_vec__ret_bool__int32_t_p__int32_t__t **head, + rep_vec__ret_bool__int32_t_p__int32_t__t *new_entry); +void +rep_vec__ret_bool__int32_t_p__int32_t__add_last( + rep_vec__ret_bool__int32_t_p__int32_t__t **head, + rep_vec__ret_bool__int32_t_p__int32_t__t *new_entry); +bool +rep_vec__ret_bool__int32_t_p__int32_t__invoke( + rep_vec__ret_bool__int32_t_p__int32_t__t *rv, + bool (*def_fn)(int32_t *, int32_t), int32_t *pseq_dur, int32_t ble_dur); + +/** + * @brief After the BLE module has gone to sleep, this vector can be used to + * prevent the system from entering the retention power saving mode. + * @param[out] pseq_dur Adjusted duration (32KHz) for platform power management + * @param[in] ble_dur Expected BLE sleep duration (32KHz) + * @return true to prevent retention + */ +extern rep_vec__ret_bool__int32_t_p__int32_t__t *rv_plf_prevent_retention; +#define RV_PLF_PREVENT_RETENTION_ADD(__f) \ + RV_ADD(__ret_bool__int32_t_p__int32_t__, rv_plf_prevent_retention, __f) +#define RV_PLF_PREVENT_RETENTION_ADD_LAST(__f) \ + RV_ADD_LAST(__ret_bool__int32_t_p__int32_t__, rv_plf_prevent_retention, __f) + +/** + * @brief After the BLE module has gone to sleep, this vector can be used to + * prevent the system from entering the hibernation power saving mode. + * The HID examples use this to protect the system state while there is an + * active connection to a central host. + * @param[out] pseq_dur Adjusted duration (32KHz) for platform power management + * @param[in] ble_dur Expected BLE sleep duration (32KHz) + * @return true to prevent hibernation + */ +extern rep_vec__ret_bool__int32_t_p__int32_t__t *rv_plf_prevent_hibernation; +#define RV_PLF_PREVENT_HIBERNATION_ADD(__f) \ + RV_ADD(__ret_bool__int32_t_p__int32_t__, rv_plf_prevent_hibernation, __f) +#define RV_PLF_PREVENT_HIBERNATION_ADD_LAST(__f) \ + RV_ADD_LAST(__ret_bool__int32_t_p__int32_t__, rv_plf_prevent_hibernation, __f) + + +/* void fn(uint32_t) */ +typedef rep_vec_err_t (*rep_vec_fn__uint32_t__t)(uint32_t); + +typedef struct rep_vec__uint32_t__s { + rep_vec_fn__uint32_t__t fn; + struct rep_vec__uint32_t__s *next; +} rep_vec__uint32_t__t; + +void +rep_vec__uint32_t__add(rep_vec__uint32_t__t **head, + rep_vec__uint32_t__t *new_entry); +void +rep_vec__uint32_t__add_last(rep_vec__uint32_t__t **head, + rep_vec__uint32_t__t *new_entry); +void +rep_vec__uint32_t__invoke(rep_vec__uint32_t__t *rv, void (*def_fn)(uint32_t), + uint32_t wake_status); + +/** + * @brief After the system wakes up from a power saving mode, this vector is + * invoked from a ke_event handler with the wakeup reason from the PSEQ STATUS + * register. Applications can decode this reason and take specific action. + * @param[in] wake_status Wakeup reason + */ +extern rep_vec__uint32_t__t *rv_plf_awoken; +#define RV_PLF_AWOKEN_ADD(__f) \ + RV_ADD(__uint32_t__, rv_plf_awoken, __f) +#define RV_PLF_AWOKEN_ADD_LAST(__f) \ + RV_ADD_LAST(__uint32_t__, rv_plf_awoken, __f) + + +/* void fn(uint32_t, uint32_t *) */ +typedef rep_vec_err_t (*rep_vec_fn__uint32_t__uint32_t_p__t)(uint32_t, uint32_t *); + +typedef struct rep_vec__uint32_t__uint32_t_p__s { + rep_vec_fn__uint32_t__uint32_t_p__t fn; + struct rep_vec__uint32_t__uint32_t_p__s *next; +} rep_vec__uint32_t__uint32_t_p__t; + +void +rep_vec__uint32_t__uint32_t_p__add(rep_vec__uint32_t__uint32_t_p__t **head, + rep_vec__uint32_t__uint32_t_p__t *new_entry); +void +rep_vec__uint32_t__uint32_t_p__add_last(rep_vec__uint32_t__uint32_t_p__t **head, + rep_vec__uint32_t__uint32_t_p__t *new_entry); +void +rep_vec__uint32_t__uint32_t_p__invoke(rep_vec__uint32_t__uint32_t_p__t *rv, + void (*def_fn)(uint32_t, uint32_t *), uint32_t bp_freq, uint32_t *min_freq); + +/** + * @brief Platform power management interface for backplane frequency + * throttling during CPU idle. Peripheral drivers can use this to + * implement minimum frequency requirements. + * @param[in] bp_freq Current BP frequency in Hz + * @param[out] min_freq Requested throttling frequency in Hz + */ +extern rep_vec__uint32_t__uint32_t_p__t *rv_plf_bp_throttle; +#define RV_PLF_BP_THROTTLE_ADD(__f) \ + RV_ADD(__uint32_t__uint32_t_p__, rv_plf_bp_throttle, __f) +#define RV_PLF_BP_THROTTLE_ADD_LAST(__f) \ + RV_ADD_LAST(__uint32_t__uint32_t_p__, rv_plf_bp_throttle, __f) + + +/* bool fn(int32_t, uint32_t *) */ +typedef rep_vec_err_t (*rep_vec_fn__ret_bool__int32_t__uint32_t_p__t)(bool *, int32_t, uint32_t *); + +typedef struct rep_vec__ret_bool__int32_t__uint32_t_p__s { + rep_vec_fn__ret_bool__int32_t__uint32_t_p__t fn; + struct rep_vec__ret_bool__int32_t__uint32_t_p__s *next; +} rep_vec__ret_bool__int32_t__uint32_t_p__t; + +void +rep_vec__ret_bool__int32_t__uint32_t_p__add( + rep_vec__ret_bool__int32_t__uint32_t_p__t **head, + rep_vec__ret_bool__int32_t__uint32_t_p__t *new_entry); +void +rep_vec__ret_bool__int32_t__uint32_t_p__add_last( + rep_vec__ret_bool__int32_t__uint32_t_p__t **head, + rep_vec__ret_bool__int32_t__uint32_t_p__t *new_entry); +bool +rep_vec__ret_bool__int32_t__uint32_t_p__invoke( + rep_vec__ret_bool__int32_t__uint32_t_p__t *rv, + bool (*def_fn)(int32_t, uint32_t *), int32_t duration, uint32_t *int_set); + +/** + * @brief This vector permits customization of the power saving logic. + * See driver/pseq for more information. + * @param[in] duration Hibernation duration (32KHz) + * @param[in] int_set Preserved interrupt enables + * @return false if platform power management was skipped + */ +extern rep_vec__ret_bool__int32_t__uint32_t_p__t *rv_plf_hibernate; +#define RV_PLF_HIBERNATE_ADD(__f) \ + RV_ADD(__ret_bool__int32_t__uint32_t_p__, rv_plf_hibernate, __f) +#define RV_PLF_HIBERNATE_ADD_LAST(__f) \ + RV_ADD_LAST(__ret_bool__int32_t__uint32_t_p__, rv_plf_hibernate, __f) + +/** + * @brief This vector permits customization of the power saving logic. + * See driver/pseq for more information. + * @param[in] duration Retention duration (32KHz) + * @param[in] int_set Preserved interrupt enables + * @return false if platform power management was skipped + */ +extern rep_vec__ret_bool__int32_t__uint32_t_p__t *rv_plf_retain_all; +#define RV_PLF_RETAIN_ALL_ADD(__f) \ + RV_ADD(__ret_bool__int32_t__uint32_t_p__, rv_plf_retain_all, __f) +#define RV_PLF_RETAIN_ALL_ADD_LAST(__f) \ + RV_ADD_LAST(__ret_bool__int32_t__uint32_t_p__, rv_plf_retain_all, __f) + + +/* void fn(bool *, uint32_t *, bool, int32_t) */ +typedef rep_vec_err_t (*rep_vec_fn__bool_p__uint32_t_p__bool__int32_t__t)(bool *, uint32_t *, bool, int32_t); + +typedef struct rep_vec__bool_p__uint32_t_p__bool__int32_t__s { + rep_vec_fn__bool_p__uint32_t_p__bool__int32_t__t fn; + struct rep_vec__bool_p__uint32_t_p__bool__int32_t__s *next; +} rep_vec__bool_p__uint32_t_p__bool__int32_t__t; + +void +rep_vec__bool_p__uint32_t_p__bool__int32_t__add( + rep_vec__bool_p__uint32_t_p__bool__int32_t__t **head, + rep_vec__bool_p__uint32_t_p__bool__int32_t__t *new_entry); +void +rep_vec__bool_p__uint32_t_p__bool__int32_t__add_last( + rep_vec__bool_p__uint32_t_p__bool__int32_t__t **head, + rep_vec__bool_p__uint32_t_p__bool__int32_t__t *new_entry); +void +rep_vec__bool_p__uint32_t_p__bool__int32_t__invoke( + rep_vec__bool_p__uint32_t_p__bool__int32_t__t *rv, + void (*def_fn)(bool *, uint32_t *, bool, int32_t), bool *pseq_sleep, + uint32_t *int_set, bool ble_asleep, int32_t ble_sleep_duration); + +/** + * @brief This vector permits customization of the power saving logic. + * See driver/pseq for more information. + * @param[out] pseq_sleep false if platform power management was skipped + * @param[out] int_set Preserved interrupt enables + * @param[in] ble_asleep BLE was already asleep + * @param[in] ble_sleep_duration Expected BLE sleep duration (32KHz) + */ +extern rep_vec__bool_p__uint32_t_p__bool__int32_t__t *rv_plf_to_deep_sleep; +#define RV_PLF_TO_DEEP_SLEEP_ADD(__f) \ + RV_ADD(__bool_p__uint32_t_p__bool__int32_t__, rv_plf_to_deep_sleep, __f) +#define RV_PLF_TO_DEEP_SLEEP_ADD_LAST(__f) \ + RV_ADD_LAST(__bool_p__uint32_t_p__bool__int32_t__, rv_plf_to_deep_sleep, __f) + + +/* void fn(bool, uint32_t *) */ +typedef rep_vec_err_t (*rep_vec_fn__bool__uint32_t_p__t)(bool, uint32_t *); + +typedef struct rep_vec__bool__uint32_t_p__s { + rep_vec_fn__bool__uint32_t_p__t fn; + struct rep_vec__bool__uint32_t_p__s *next; +} rep_vec__bool__uint32_t_p__t; + +void +rep_vec__bool__uint32_t_p__add(rep_vec__bool__uint32_t_p__t **head, + rep_vec__bool__uint32_t_p__t *new_entry); +void +rep_vec__bool__uint32_t_p__add_last(rep_vec__bool__uint32_t_p__t **head, + rep_vec__bool__uint32_t_p__t *new_entry); +void +rep_vec__bool__uint32_t_p__invoke(rep_vec__bool__uint32_t_p__t *rv, + void (*def_fn)(bool, uint32_t *), bool pseq_sleep, uint32_t *int_set); + +/** + * @brief This vector permits customization of the power saving logic. + * See driver/pseq for more information. + * @param[in] pseq_sleep false if platform power management was skipped + * @param[in] int_set Preserved interrupt enables + */ +extern rep_vec__bool__uint32_t_p__t *rv_plf_from_deep_sleep; +#define RV_PLF_FROM_DEEP_SLEEP_ADD(__f) \ + RV_ADD(__bool__uint32_t_p__, rv_plf_from_deep_sleep, __f) +#define RV_PLF_FROM_DEEP_SLEEP_ADD_LAST(__f) \ + RV_ADD_LAST(__bool__uint32_t_p__, rv_plf_from_deep_sleep, __f) + +#ifdef __cplusplus +} +#endif diff --git a/ATM33xx-5/drivers/reset/reset.c b/ATM33xx-5/drivers/reset/reset.c new file mode 100644 index 0000000..b259979 --- /dev/null +++ b/ATM33xx-5/drivers/reset/reset.c @@ -0,0 +1,228 @@ +/** + ****************************************************************************** + * + * @file reset.c + * + * @brief Reset Driver + * + * Copyright (C) Atmosic 2022-2023 + * + ****************************************************************************** + */ + +#ifdef CONFIG_SOC_FAMILY_ATM +#include +#include +#include +#endif + +#include "arch.h" +#include +#include "spi.h" +#include "reset.h" +#include "pmu.h" +#include "pmu_spi.h" +#include "at_wrpr.h" +#include "at_apb_pseq_regs_core_macro.h" +#include "pmu_top_regs_core_macro.h" +#include "sec_reset.h" +#include "pseq_status.h" + +static uint32_t reset_syndrome; + +boot_status_t boot_status(void) +{ + if (reset_syndrome & (SYS_CTRL_REG_SSE200_RESET_SYNDROME_LOCKUP0_Msk | + SYS_CTRL_REG_SSE200_RESET_SYNDROME_LOCKUP1_Msk)) { + /* LOCKUP0 and LOCKUP1 do not generate reset, but when HIGH, indicate + * that a processor has locked-up and could be a precursor to another + * reset event, for example, a watchdog timer reset request */ + return BOOT_STATUS_RESET_LOCKUP; + } + + if (reset_syndrome & SYS_CTRL_REG_SSE200_RESET_SYNDROME_NSWD_Msk) { + return BOOT_STATUS_RESET_WDOG; + } + + if (reset_syndrome & + (SYS_CTRL_REG_SSE200_RESET_SYNDROME_SWD_Msk | + SYS_CTRL_REG_SSE200_RESET_SYNDROME_S32KWD_Msk)) { + return BOOT_STATUS_RESET_SWDOG; + } + + if (reset_syndrome & (SYS_CTRL_REG_SSE200_RESET_SYNDROME_SYSRSTREQ0_Msk | + SYS_CTRL_REG_SSE200_RESET_SYNDROME_SYSRSTREQ1_Msk)) { + return BOOT_STATUS_RESET_SYS; + } + + if (reset_syndrome & SYS_CTRL_REG_SSE200_RESET_SYNDROME_SWRESETREQ_Msk) { + return BOOT_STATUS_RESET_SW; + } + + if (reset_syndrome & SYS_CTRL_REG_SSE200_RESET_SYNDROME_RESETREQ_Msk) { + return BOOT_STATUS_RESET_EXT; + } + + uint32_t pseq_boot_status; + WRPR_CTRL_SET(CMSDK_PSEQ, WRPR_CTRL__CLK_ENABLE); + { + pseq_boot_status = CMSDK_PSEQ->STATUS & PSEQ_STATUS__POWER_ON_REASONS; + } + WRPR_CTRL_SET(CMSDK_PSEQ, WRPR_CTRL__CLK_DISABLE); + + boot_status_t status = 0; + + if (!pseq_boot_status) { + uint8_t pmu_wkup_det = pmu_get_wkup_det(); + if (!pmu_wkup_det) { + ASSERT_ERR(reset_syndrome & + SYS_CTRL_REG_SSE200_RESET_SYNDROME_PoR_Msk); + return BOOT_STATUS_POWER_ON; + } + if (pmu_wkup_det & PMU_WKUP_PIN) { + status |= BOOT_STATUS_SOCOFF_WKUP_PIN; + } + if (pmu_wkup_det & PMU_WKUP_LPCOMP) { + status |= BOOT_STATUS_SOCOFF_WKUP_LPCOMP; + } + if (pmu_wkup_det & PMU_WKUP_TIMER) { + status |= BOOT_STATUS_SOCOFF_WKUP_TIMER; + } + if (pmu_get_soc_wdog_reset()) { + status |= BOOT_STATUS_SOCOFF_WDOG_RESET; + } + } else { + if (pseq_boot_status & PSEQ_STATUS__TIMER_TRIGGERED__MASK) { + status |= BOOT_STATUS_HIB_WKUP_TIMER; + } + if (pseq_boot_status & PSEQ_STATUS__GPIO_TRIGGERED__MASK) { + status |= BOOT_STATUS_HIB_WKUP_GPIO; + } + if (pseq_boot_status & PSEQ_STATUS__WURX0_TRIGGERED__MASK) { + status |= BOOT_STATUS_HIB_WKUP_WURX0; + } + if (pseq_boot_status & PSEQ_STATUS__WURX1_TRIGGERED__MASK) { + status |= BOOT_STATUS_HIB_WKUP_WURX1; + } + if (pseq_boot_status & PSEQ_STATUS__QDEC_TRIGGERED__MASK) { + status |= BOOT_STATUS_HIB_WKUP_QDEC; + } + if (pseq_boot_status & PSEQ_STATUS__KSM_TRIGGERED__MASK) { + status |= BOOT_STATUS_HIB_WKUP_KSM; + } + if (pseq_boot_status & PSEQ_STATUS__DBG_TRIGGERED__MASK) { + status |= BOOT_STATUS_HIB_WKUP_DBG; + } + if (pseq_boot_status & PSEQ_STATUS__SHUB_TRIGGERED__MASK) { + status |= BOOT_STATUS_HIB_WKUP_SHUB; + } + if (pseq_boot_status & PSEQ_STATUS__SPI_TRIGGERED__MASK) { + status |= BOOT_STATUS_HIB_WKUP_SPI; + } + if (pseq_boot_status & PSEQ_STATUS__I2C_TRIGGERED__MASK) { + status |= BOOT_STATUS_HIB_WKUP_I2C; + } + if (pseq_boot_status & PSEQ_STATUS__PMU_TIMER_TRIGGERED__MASK) { + status |= BOOT_STATUS_HIB_WKUP_PMU_TIMER; + } + if (pseq_boot_status & PSEQ_STATUS__PMU_LPCOMP_TRIGGERED__MASK) { + status |= BOOT_STATUS_HIB_WKUP_PMU_LPCOMP; + } + if (pseq_boot_status & PSEQ_STATUS__ENERGY4CPU_TRIGGERED__MASK) { + status |= BOOT_STATUS_HIB_WKUP_ENERGY4CPU; + } + if (pseq_boot_status & PSEQ_STATUS__ENERGY4TX_TRIGGERED__MASK) { + status |= BOOT_STATUS_HIB_WKUP_ENERGY4TX; + } + if (pseq_boot_status & PSEQ_STATUS__ENDOFLIFE_TRIGGERED__MASK) { + status |= BOOT_STATUS_HIB_WKUP_ENDOFLIFE; + } + if (pseq_boot_status & PSEQ_STATUS__BROWNOUT_TRIGGERED__MASK) { + status |= BOOT_STATUS_HIB_WKUP_BROWNOUT; + } + if (pseq_boot_status & PSEQ_STATUS__WURX_TRIGGERED__MASK) { + status |= BOOT_STATUS_HIB_WKUP_WURX; + } + } + + ASSERT_ERR(status); + + return status; +} + +#ifndef CONFIG_SOC_FAMILY_ATM +__CONSTRUCTOR_PRIO(CONSTRUCTOR_RESET) +#endif +static void reset_print(void) +{ + reset_syndrome = secure_rclr_reset_syndrome(); + + DEBUG_TRACE("boot_status = %x", boot_status()); + + if (is_boot_type(TYPE_POWER_ON)) { + DEBUG_TRACE("Cold boot"); + DEBUG_TRACE_COND(is_boot_type(TYPE_POWER_ON), " Power on Reset"); + } + if (is_boot_type(TYPE_RESET)) { + DEBUG_TRACE("System reset"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_RESET_LOCKUP), + " CPU Lock-up Status"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_RESET_WDOG), + " Non Secure WDOG"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_RESET_SWDOG), + " Secure WDOG"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_RESET_SYS), + " CPU System Reset Request"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_RESET_SW), + " Software Reset Request"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_RESET_EXT), + " External Reset Request"); + } + if (is_boot_type(TYPE_HIB)) { + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_HIB_WKUP_TIMER), "timer"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_HIB_WKUP_GPIO), "gpio"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_HIB_WKUP_WURX0), "wurx0"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_HIB_WKUP_WURX1), "wurx1"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_HIB_WKUP_QDEC), "qdec"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_HIB_WKUP_KSM), "ksm"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_HIB_WKUP_DBG), "dbg"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_HIB_WKUP_SHUB), "shub"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_HIB_WKUP_SPI), "spi"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_HIB_WKUP_I2C), "i2c"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_HIB_WKUP_PMU_TIMER), + "pmu_timer"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_HIB_WKUP_PMU_LPCOMP), + "pmu_lpcomp"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_HIB_WKUP_ENERGY4CPU), + "energy4CPU"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_HIB_WKUP_ENERGY4TX), + "energy4TX"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_HIB_WKUP_ENDOFLIFE), + "endoflife"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_HIB_WKUP_BROWNOUT), + "brownout"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_HIB_WKUP_WURX), "wurx"); + DEBUG_TRACE("triggered Hiberation wakeup"); + } + if (is_boot_type(TYPE_SOCOFF)) { + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_SOCOFF_WKUP_PIN), + " pin triggered"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_SOCOFF_WKUP_LPCOMP), + " lpcomp triggered"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_SOCOFF_WKUP_TIMER), + " timer triggered"); + DEBUG_TRACE_COND(is_boot_reason(BOOT_STATUS_SOCOFF_WDOG_RESET), + " wdog forced"); + DEBUG_TRACE("SOC off wakeup"); + } +} + +#ifdef CONFIG_SOC_FAMILY_ATM +static int reset_sys_init(void) +{ + reset_print(); + return 0; +} + +SYS_INIT(reset_sys_init, PRE_KERNEL_2, 4); +#endif diff --git a/ATM33xx-5/drivers/reset/reset.h b/ATM33xx-5/drivers/reset/reset.h new file mode 100644 index 0000000..556874f --- /dev/null +++ b/ATM33xx-5/drivers/reset/reset.h @@ -0,0 +1,226 @@ +/** + ****************************************************************************** + * + * @file reset.h + * + * @brief Reset driver + * + * Copyright (C) Atmosic 2022-2023 + * + ****************************************************************************** + */ + +#pragma once + +/** + * @defgroup RESET RESET + * @ingroup DRIVERS + * @brief Reset driver + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/// Boot type +typedef enum { + /// Power on. + TYPE_POWER_ON, + /// Reset. + TYPE_RESET, + /// Wake from SOC off. + TYPE_SOCOFF, + /// Wake from Hibernation. + TYPE_HIB, +} boot_type_t; + +/// Reset reason +typedef enum { + /// System reset. + RESET_SYS, + /// Reset by watchdog. + RESET_WDOG, + /// Reset by secure watchdog. + RESET_SWDOG, + /// Reset by LOCKUP cases. + RESET_LOCKUP, + /// Reset by software + RESET_SW, + /// External reset. + RESET_EXT, +} boot_reset_reason_t; + +/// Hibernation wakeup reason +typedef enum { + /// Wake up from hibernation by timer. + HIB_TIMER, + /// Wake up from hibernation by GPIO. + HIB_GPIO, + /// Wake up from hibernation by WURX0. + HIB_WURX0, + /// Wake up from hibernation by WURX1. + HIB_WURX1, + /// Wake up from hibernation by QDEC. + HIB_QDEC, + /// Wake up from hibernation by key scan matrix. + HIB_KSM, + /// Wake up from hibernation by debugger. + HIB_DBG, + /// Wake up from hibernation by sensor hub. + HIB_SHUB, + /// Boot from hibernation which is triggered by SPI. + HIB_SPI, + /// Boot from hibernation which is triggered by I2C. + HIB_I2C, + /// Boot from hibernation which is triggered by PMU_TIMER. + HIB_PMU_TIMER, + /// Boot from hibernation which is triggered by PMU_LPCOMP. + HIB_PMU_LPCOMP, + /// Boot from hibernation which is triggered by ENERGY4CPU. + HIB_ENERGY4CPU, + /// Boot from hibernation which is triggered by ENERGY4TX. + HIB_ENERGY4TX, + /// Boot from hibernation which is triggered by ENDOFLIFE. + HIB_ENDOFLIFE, + /// Boot from hibernation which is triggered by BROWNOUT. + HIB_BROWNOUT, + /// Boot from hibernation which is triggered by WURX. + HIB_WURX, +} boot_hib_reason_t; + +/// SOC off wakeup reason +typedef enum { + /// Wake up from SOC off by pin. + SOCOFF_PIN, + /// Wake up from SOC off by low power comparator. + SOCOFF_LPCOMP, + /// Wake up from SOC off by timer. + SOCOFF_TIMER, + /// SOC off forced by watchdog. + SOCOFF_WDOG, +} boot_socoff_reason_t; + +/// Generate reason mask +#define BOOT_MASK(reason) ((1 << (reason)) & 0xffffff) + +/// Generate boot status from boot type and reason +#define BOOT_STATUS(type, mask) ((1 << (24 + (type))) + (mask)) + +/// Boot status: highest 8 bit is mask of boot_type_t and lowest 24 bit is mask +/// of boot_reset_reason_t, boot_hib_reason_t or boot_socoff_reason_t. +typedef enum { + /// Reset was cold + BOOT_STATUS_POWER_ON = BOOT_STATUS(TYPE_POWER_ON, 0), + /// System reset. + BOOT_STATUS_RESET_SYS = BOOT_STATUS(TYPE_RESET, BOOT_MASK(RESET_SYS)), + /// Reset by watchdog. + BOOT_STATUS_RESET_WDOG = BOOT_STATUS(TYPE_RESET, BOOT_MASK(RESET_WDOG)), + /// Reset by secure watchdog. + BOOT_STATUS_RESET_SWDOG = BOOT_STATUS(TYPE_RESET, BOOT_MASK(RESET_SWDOG)), + /// Reset by LOCKUP cases. + BOOT_STATUS_RESET_LOCKUP = BOOT_STATUS(TYPE_RESET, BOOT_MASK(RESET_LOCKUP)), + /// Reset by LOCKUP cases. + BOOT_STATUS_RESET_SW = BOOT_STATUS(TYPE_RESET, BOOT_MASK(RESET_SW)), + /// Reset by LOCKUP cases. + BOOT_STATUS_RESET_EXT = BOOT_STATUS(TYPE_RESET, BOOT_MASK(RESET_EXT)), + /// Wake up from SOC off by pin. + BOOT_STATUS_SOCOFF_WKUP_PIN = BOOT_STATUS(TYPE_SOCOFF, + BOOT_MASK(SOCOFF_PIN)), + /// Wake up from SOC off by low power comparator. + BOOT_STATUS_SOCOFF_WKUP_LPCOMP = BOOT_STATUS(TYPE_SOCOFF, + BOOT_MASK(SOCOFF_LPCOMP)), + /// Wake up from SOC off by timer. + BOOT_STATUS_SOCOFF_WKUP_TIMER = BOOT_STATUS(TYPE_SOCOFF, + BOOT_MASK(SOCOFF_TIMER)), + /// SOC off forced by watchdog. + BOOT_STATUS_SOCOFF_WDOG_RESET = BOOT_STATUS(TYPE_SOCOFF, + BOOT_MASK(SOCOFF_WDOG)), + /// Wake up from hibernation by timer. + BOOT_STATUS_HIB_WKUP_TIMER = BOOT_STATUS(TYPE_HIB, BOOT_MASK(HIB_TIMER)), + /// Wake up from hibernation by GPIO. + BOOT_STATUS_HIB_WKUP_GPIO = BOOT_STATUS(TYPE_HIB, BOOT_MASK(HIB_GPIO)), + /// Wake up from hibernation by WURX0. + BOOT_STATUS_HIB_WKUP_WURX0 = BOOT_STATUS(TYPE_HIB, BOOT_MASK(HIB_WURX0)), + /// Wake up from hibernation by WURX1. + BOOT_STATUS_HIB_WKUP_WURX1 = BOOT_STATUS(TYPE_HIB, BOOT_MASK(HIB_WURX1)), + /// Wake up from hibernation by QDEC. + BOOT_STATUS_HIB_WKUP_QDEC = BOOT_STATUS(TYPE_HIB, BOOT_MASK(HIB_QDEC)), + /// Wake up from hibernation by key scan matrix. + BOOT_STATUS_HIB_WKUP_KSM = BOOT_STATUS(TYPE_HIB, BOOT_MASK(HIB_KSM)), + /// Wake up from hibernation by debugger. + BOOT_STATUS_HIB_WKUP_DBG = BOOT_STATUS(TYPE_HIB, BOOT_MASK(HIB_DBG)), + /// Wake up from hibernation by sensor hub. + BOOT_STATUS_HIB_WKUP_SHUB = BOOT_STATUS(TYPE_HIB, BOOT_MASK(HIB_SHUB)), + /// Boot from hibernation which is triggered by SPI + BOOT_STATUS_HIB_WKUP_SPI = BOOT_STATUS(TYPE_HIB, BOOT_MASK(HIB_SPI)), + /// Boot from hibernation which is triggered by I2C + BOOT_STATUS_HIB_WKUP_I2C = BOOT_STATUS(TYPE_HIB, BOOT_MASK(HIB_I2C)), + /// Boot from hibernation which is triggered by PMU_TIMER + BOOT_STATUS_HIB_WKUP_PMU_TIMER = + BOOT_STATUS(TYPE_HIB, BOOT_MASK(HIB_PMU_TIMER)), + /// Boot from hibernation which is triggered by PMU_LPCOMP + BOOT_STATUS_HIB_WKUP_PMU_LPCOMP = + BOOT_STATUS(TYPE_HIB, BOOT_MASK(HIB_PMU_LPCOMP)), + /// Boot from hibernation which is triggered by ENERGY4CPU + BOOT_STATUS_HIB_WKUP_ENERGY4CPU = + BOOT_STATUS(TYPE_HIB, BOOT_MASK(HIB_ENERGY4CPU)), + /// Boot from hibernation which is triggered by ENERGY4TX + BOOT_STATUS_HIB_WKUP_ENERGY4TX = + BOOT_STATUS(TYPE_HIB, BOOT_MASK(HIB_ENERGY4TX)), + /// Boot from hibernation which is triggered by ENDOFLIFE + BOOT_STATUS_HIB_WKUP_ENDOFLIFE = + BOOT_STATUS(TYPE_HIB, BOOT_MASK(HIB_ENDOFLIFE)), + /// Boot from hibernation which is triggered by BROWNOUT + BOOT_STATUS_HIB_WKUP_BROWNOUT = BOOT_STATUS(TYPE_HIB, + BOOT_MASK(HIB_BROWNOUT)), + /// Boot from hibernation which is triggered by WURX + BOOT_STATUS_HIB_WKUP_WURX = BOOT_STATUS(TYPE_HIB, BOOT_MASK(HIB_WURX)), +} boot_status_t; + +/** + * @brief Get boot status + * + * @return Boot status + */ +boot_status_t boot_status(void); + +/** + * @brief Judge if boot is a kind of type. + * + * @param[in] typ The type to be matched. + * @return True if the type is matched. + */ +__INLINE bool is_boot_type(boot_type_t typ) +{ + return (boot_status() & BOOT_STATUS(typ, 0)); +} + +/** + * @brief Judge if boot is a kind of reason. + * + * @param[in] sts The reason to be matched. + * @return True if the reason is matched. + */ +__INLINE bool is_boot_reason(boot_status_t sts) +{ + return ((boot_status() & sts) == sts); +} + +/** + * @brief Determine if the variables located in the .uninit section need to be + * assigned values due to the lost of values during boot process. + * + * @return True if the assignment is needed. + */ +__INLINE bool is_boot_uninit(void) +{ + return (is_boot_type(TYPE_POWER_ON) || is_boot_type(TYPE_SOCOFF) || + is_boot_type(TYPE_HIB)); +} + +#ifdef __cplusplus +} +#endif + +/// @} diff --git a/ATM33xx-5/drivers/rram_rom_prot/rram_rom_prot.c b/ATM33xx-5/drivers/rram_rom_prot/rram_rom_prot.c new file mode 100644 index 0000000..68ff68c --- /dev/null +++ b/ATM33xx-5/drivers/rram_rom_prot/rram_rom_prot.c @@ -0,0 +1,212 @@ +/** + ****************************************************************************** + * + * @file rram_rom_prot.c + * + * @brief RRAM and ROM Protection Driver + * + * Copyright (C) Atmosic 2022-2024 + * + ****************************************************************************** + */ + +#include "arch.h" +#include +#include +#include "rram_rom_prot.h" +#include "at_wrpr.h" +#include "at_apb_clkrstgen_regs_core_macro.h" +#ifndef SECURE_MODE +#include "rep_vec.h" +#include "atm_bp_clock.h" +#endif + +#ifdef CFG_RRAM_PROT_DEBUG +#define RR_PROT_DEBUG 1 +#else +#define RR_PROT_DEBUG 0 +#endif + +static bool prot_range_check(uint32_t offset, uint32_t length, + uint32_t max_size, bool force_align) +{ + DEBUG_TRACE_COND(RR_PROT_DEBUG, "Check range offset: 0x%" PRIx32 " len:%" + PRIu32, offset, length); + + if (force_align && ((offset % RRAM_ROM_PROT_BLOCK_SIZE) || + (length % RRAM_ROM_PROT_BLOCK_SIZE))) { + DEBUG_TRACE_COND(RR_PROT_DEBUG, "Check offset: 0x%" PRIx32 " length:%" PRIu32 + " mis-aligned!", offset, length); + return false; + } + + uint64_t end = (uint64_t)offset + (uint64_t)length; + + if (!length || (end > max_size)) { + DEBUG_TRACE_COND(RR_PROT_DEBUG, "Check offset: 0x%" PRIx32 " length:%" PRIu32 " invalid!", + offset, length); + return false; + } + return true; +} + +static void set_clr_bits(uint32_t volatile *rreg, uint32_t offset, + uint32_t length, bool set) +{ + DEBUG_TRACE_COND(RR_PROT_DEBUG, "Reg base (%p) off: 0x%" PRIx32 " len: %" + PRIu32, rreg, offset, length); + + uint32_t bit_offset = offset / RRAM_ROM_PROT_BLOCK_SIZE; + + // compute starting register and starting bit + uint32_t reg_offset = bit_offset / 32; + uint32_t start_bit = bit_offset % 32; + rreg = &rreg[reg_offset]; + + // compute the span of bits + uint32_t bit_offset_end = (offset + length) / RRAM_ROM_PROT_BLOCK_SIZE; + bit_offset_end += ((offset + length) % RRAM_ROM_PROT_BLOCK_SIZE) ? 1 : 0; + uint32_t num_bits = bit_offset_end - bit_offset; + + DEBUG_TRACE_COND(RR_PROT_DEBUG, "Reg start (%p) idx:%" PRIu32 ", startb:%" + PRIu32 " bits:%" PRIu32, rreg, reg_offset, start_bit, num_bits); + + while (num_bits) { + uint32_t reg_bits = 32 - start_bit; + if (reg_bits > num_bits) { + reg_bits = num_bits; + } + uint32_t bitmask = (1 << reg_bits) - 1; + bitmask <<= start_bit; + if (set) { + *rreg |= bitmask; + } else { + *rreg &= ~bitmask; + } + start_bit = 0; + num_bits -= reg_bits; + rreg++; + } +} + +bool rram_prot_write_enable(uint32_t offset, uint32_t length) +{ + if (!prot_range_check(offset, length, RRAM_WRITE_PROTECT_SIZE, false)) { + return false; + } + + // set bit to 0 to enable writes + set_clr_bits(&CMSDK_WRPR0_NONSECURE->RRAM_WRITE_PROTECTION0, offset, length, + false); + return true; +} + +bool rram_prot_write_disable(uint32_t offset, uint32_t length) +{ + // fast disable all of RRAM. + if (!offset && (length == RRAM_WRITE_PROTECT_SIZE)) { + CMSDK_WRPR0_NONSECURE->RRAM_WRITE_PROTECTION0 = 0xffffffff; + CMSDK_WRPR0_NONSECURE->RRAM_WRITE_PROTECTION1 = 0xffffffff; + CMSDK_WRPR0_NONSECURE->RRAM_WRITE_PROTECTION2 = 0xffffffff; + CMSDK_WRPR0_NONSECURE->RRAM_WRITE_PROTECTION3 = 0xffffffff; + CMSDK_WRPR0_NONSECURE->RRAM_WRITE_PROTECTION4 = 0xffffffff; + CMSDK_WRPR0_NONSECURE->RRAM_WRITE_PROTECTION5 = 0xffffffff; + CMSDK_WRPR0_NONSECURE->RRAM_WRITE_PROTECTION6 = 0xffffffff; + CMSDK_WRPR0_NONSECURE->RRAM_WRITE_PROTECTION7 = 0xffffffff; + return true; + } + + if (!prot_range_check(offset, length, RRAM_WRITE_PROTECT_SIZE, false)) { + return false; + } + + // set bit to 1 to disable writes + set_clr_bits(&CMSDK_WRPR0_NONSECURE->RRAM_WRITE_PROTECTION0, offset, length, + true); + return true; +} + +static void sticky_clock_control(uint32_t enable) +{ + WRPR_CTRL_PUSH(CMSDK_CLKRSTGEN_NONSECURE, WRPR_CTRL__CLK_ENABLE) + { + CLKRSTGEN_USER_CLK_GATE_CTRL__STICKY_CLK__MODIFY( + CMSDK_CLKRSTGEN_NONSECURE->USER_CLK_GATE_CTRL, enable); + } + WRPR_CTRL_POP(); +} + +bool rram_prot_sticky_write_disable(uint32_t offset, uint32_t length) +{ + if (!prot_range_check(offset, length, RRAM_STICKY_WRITE_PROTECT_SIZE, + true)) { + return false; + } + + sticky_clock_control(1); + + // set bit to 1 to sticky disable writes + set_clr_bits(&CMSDK_WRPR0_NONSECURE->RRAM_STICKY_WRITE_PROTECTION0, offset, + length, true); + + sticky_clock_control(0); + + return true; +} + +bool rram_prot_sticky_read_disable(uint32_t offset, uint32_t length) +{ + if (!prot_range_check(offset, length, RRAM_READ_PROTECT_SIZE, true)) { + return false; + } + + sticky_clock_control(1); + + // set bit to 1 to sticky disable reads + set_clr_bits(&CMSDK_WRPR0_NONSECURE->RRAM_STICKY_READ_PROTECTION0, offset, + length, true); + + // this register is not auto-clearing + CMSDK_WRPR0_NONSECURE->RRAM_STICKY_READ_PROTECTION0 = 0; + + sticky_clock_control(0); + + return true; +} + +bool rom_prot_sticky_read_disable(uint32_t offset, uint32_t length) +{ + if (!prot_range_check(offset, length, ROM_READ_PROTECT_SIZE, true)) { + return false; + } + + sticky_clock_control(1); + + // set bit to 1 to sticky disable reads + set_clr_bits(&CMSDK_WRPR0_NONSECURE->PROT_BITS_SET0, offset, length, true); + + sticky_clock_control(0); + + return true; +} + +bool rram_write_section_allowed(void) +{ + return atm_bp_clock_critical_section_allowed(RRAM_WRITE_MAX_BP_CLOCK); +} + +#define STICK_REG_COUNT \ + (RRAM_STICKY_WRITE_PROTECT_SIZE / RRAM_ROM_PROT_BLOCK_SIZE / 32) + +bool rram_prot_sticky_write_get_mask(uint8_t index, uint32_t *value) +{ + if (index >= STICK_REG_COUNT) { + return false; + } + uint32_t volatile *ptr = + &CMSDK_WRPR0_NONSECURE->RRAM_STICKY_WRITE_PROTECTION0; + sticky_clock_control(1); + *value = ptr[index]; + sticky_clock_control(0); + return true; +} diff --git a/ATM33xx-5/drivers/rram_rom_prot/rram_rom_prot.h b/ATM33xx-5/drivers/rram_rom_prot/rram_rom_prot.h new file mode 100644 index 0000000..e66c334 --- /dev/null +++ b/ATM33xx-5/drivers/rram_rom_prot/rram_rom_prot.h @@ -0,0 +1,162 @@ +/** + ****************************************************************************** + * + * @file rram_rom_prot.h + * + * @brief RRAM and ROM Protection Driver + * + * Copyright (C) Atmosic 2022-2023 + * + ****************************************************************************** + */ + +#pragma once + +/** + * @defgroup RRAM_ROM_PROT RRAM and ROM Protection + * @ingroup DRIVERS + * @brief RRAM and ROM Protection Driver + * @{ + */ + +#include "atm_bp_clock.h" +#include "ARMv8MBL.h" +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define RRAM_WRITE_MAX_BP_CLOCK 16000000U + +/// RRAM and ROM protection granularity +#define RRAM_ROM_PROT_BLOCK_SIZE 2048 + +/// Maximum RRAM write protection size +#define RRAM_WRITE_PROTECT_SIZE 0x80000 + +/// Maximum RRAM sticky write protection size +#define RRAM_STICKY_WRITE_PROTECT_SIZE RRAM_WRITE_PROTECT_SIZE + +/// Maximum RRAM sticky read protection size +#define RRAM_READ_PROTECT_SIZE 0x10000 + +/// Maximium ROM sticky read protection size +#define ROM_READ_PROTECT_SIZE 0x10000 + +/// Convert RRAM memory address to RRAM relative offset +#define RRAM_ADDR_TO_OFFSET(addr) ((uint32_t)(addr) - RRAM_BASE) + +/// Convert ROM memory address to ROM relative offset +#define ROM_ADDR_TO_OFFSET(addr) ((uint32_t)(addr) - CMSDK_FLASH_BASE) + +/// Convert a size to a multiple of the protection size (rounding up) +#define RRAM_ROM_PROT_SIZE_RNDUP(size) \ + ((((size) + RRAM_ROM_PROT_BLOCK_SIZE - 1) / RRAM_ROM_PROT_BLOCK_SIZE) * \ + RRAM_ROM_PROT_BLOCK_SIZE) + +/** + * @brief Enable writes to a RRAM region. + * + * @note The RRAM region that is enabled may cover one or more + * RRAM_ROM_PROT_BLOCK_SIZE blocks that spans the region. + * + * @param[in] offset offset of region from the start of RRAM + * @param[in] length length of region + * @return true on success + */ +bool rram_prot_write_enable(uint32_t offset, uint32_t length); + +/** + * @brief Disable writes to a RRAM region. + * + * @note The RRAM region that is disabled may cover one or more + * RRAM_ROM_PROT_BLOCK_SIZE blocks that spans the region. + * + * @param[in] offset offset of region from the start of RRAM + * @param[in] length length of region + * @return true on success + */ +bool rram_prot_write_disable(uint32_t offset, uint32_t length); + +/** + * @brief Disable writes to all of RRAM. + * + * @note Shortcut to disable all RRAM writes + * + * @return true on success + */ +static inline bool rram_prot_write_disable_all(void) +{ + return rram_prot_write_disable(0, RRAM_WRITE_PROTECT_SIZE); +} + +/** + * @brief Sticky write disable a RRAM region. + * + * @note Must be block aligned to RRAM_ROM_PROT_BLOCK_SIZE + * + * @param[in] offset offset of region from the start of RRAM + * @param[in] length length of region + * @return true on success + */ +bool rram_prot_sticky_write_disable(uint32_t offset, uint32_t length); + +/** + * @brief Sticky read disable a RRAM region. + * + * @note Must be block aligned to RRAM_ROM_PROT_BLOCK_SIZE + * + * @param[in] offset offset of region from the start of RRAM + * @param[in] length length of region + * @return true on success + */ +bool rram_prot_sticky_read_disable(uint32_t offset, uint32_t length); + +/** + * @brief Sticky read disable a ROM region. + * + * @note Must be block aligned to RRAM_ROM_PROT_BLOCK_SIZE + * + * @param[in] offset offset of region from the start of ROM + * @param[in] length length of region + * @return true on success + */ +bool rom_prot_sticky_read_disable(uint32_t offset, uint32_t length); + +/** + * @brief Check if entering an rram write section is safe + * + * @note Should be called before ENTER_RRAM_WRITE_SECTION if bp_throttle needs + * to be checked + * + * @return true if an rram write section can be enabled safely + */ +bool rram_write_section_allowed(void); + +#ifdef CFG_NO_RRAM_WRITE_CRIT_SECTION +#define ENTER_RRAM_WRITE_SECTION() do {} while(0) +#define LEAVE_RRAM_WRITE_SECTION() do {} while(0) +#else +#define ENTER_RRAM_WRITE_SECTION() \ + ATM_BP_CLOCK_ENTER_CRITICAL_SECTION(RRAM_WRITE_MAX_BP_CLOCK) + +#define LEAVE_RRAM_WRITE_SECTION() ATM_BP_CLOCK_LEAVE_CRITICAL_SECTION() +#endif + +/** + * @brief Get the sticky lock mask register + * @param[in] index index of register + * @param[out] value value of register + * + * @return true on success + */ +__NONNULL(2) +bool rram_prot_sticky_write_get_mask(uint8_t index, uint32_t *value); + +#ifdef __cplusplus +} +#endif + +/// @} diff --git a/ATM33xx-5/drivers/sec_cache/sec_cache.c b/ATM33xx-5/drivers/sec_cache/sec_cache.c new file mode 100644 index 0000000..16c125a --- /dev/null +++ b/ATM33xx-5/drivers/sec_cache/sec_cache.c @@ -0,0 +1,68 @@ +/** + ******************************************************************************* + * + * @file sec_cache.c + * + * @brief Secure cache driver implementation + * + * Copyright (C) Atmosic 2022-2024 + * + ******************************************************************************* + */ +#ifdef CFG_NO_SPE +// for no-SPE the base for the ICACHE control registers must be a secure address +#define SECURE_MODE +#endif +#include "arch.h" +#include "sec_service.h" +#include "sec_cache.h" + +#ifndef SECURE_MODE +#error "sec_cache is a secure-only driver" +#endif + +void icache_disable(void) +{ + ICACHE->ICCTRL &= ~ICACHE_ICCTRL_CACHEEN_Msk; +} + +void icache_enable(void) +{ + ICACHE->ICIRQSCLR |= ICACHE_ICIRQSTAT_IC_STATUS_Msk; + ICACHE->ICCTRL |= ICACHE_ICCTRL_FINV_Msk | ICACHE_ICCTRL_CACHEEN_Msk; +} + +void icache_flush(void) +{ + if (!(ICACHE->ICCTRL & ICACHE_ICCTRL_CACHEEN_Msk)) { + return; + } + + ICACHE->ICIRQSCLR |= ICACHE_ICIRQSTAT_IC_STATUS_Msk; + ICACHE->ICCTRL |= ICACHE_ICCTRL_FINV_Msk; + while (!(ICACHE->ICIRQSTAT & ICACHE_ICIRQSTAT_IC_STATUS_Msk)) { + __ASM volatile("yield"); + } +} + +#ifdef SECURE_PROC_ENV +__attribute__((cmse_nonsecure_entry)) __attribute__((used)) void +nsc_icache_disable(void) +{ + icache_disable(); +} + +__attribute__((cmse_nonsecure_entry)) __attribute__((used)) void +nsc_icache_enable(void) +{ + icache_enable(); +} + +__attribute__((cmse_nonsecure_entry)) __attribute__((used)) void +nsc_icache_flush(void) +{ + icache_flush(); +} + +#endif + diff --git a/ATM33xx-5/drivers/sec_cache/sec_cache.h b/ATM33xx-5/drivers/sec_cache/sec_cache.h new file mode 100644 index 0000000..00cead6 --- /dev/null +++ b/ATM33xx-5/drivers/sec_cache/sec_cache.h @@ -0,0 +1,73 @@ +/** + ******************************************************************************* + * + * @file sec_cache.h + * + * @brief Secure cache driver header file + * + * Copyright (C) Atmosic 2022-2024 + * + ******************************************************************************* + */ + +#pragma once + +/** + * @defgroup SEC_CACHE Secure cache + * @ingroup DRIVERS + * @brief Secure cache driver to manage CPU caches + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if (defined(SECURE_MODE) || defined(CFG_NO_SPE)) +/** + * @brief Disable instruction cache + */ +void icache_disable(void); + +/** + * @brief Enable instruction cache + */ +void icache_enable(void); + +/** + * @brief Flush instruction cache + */ +void icache_flush(void); + +#define ICACHE_DISABLE() icache_disable() +#define ICACHE_ENABLE() icache_enable() +#define ICACHE_FLUSH() icache_flush() + +#else + +#define ICACHE_DISABLE() nsc_icache_disable() +#define ICACHE_ENABLE() nsc_icache_enable() +#define ICACHE_FLUSH() nsc_icache_flush() + +#endif // (defined(SECURE_MODE) || defined(CFG_NO_SPE)) + +/** + * @brief NS-callable fucntion of icache_disable + */ +void nsc_icache_disable(void); + +/** + * @brief NS-callable fucntion of icache_enable + */ +void nsc_icache_enable(void); + +/** + * @brief NS-callable fucntion of icache_flush + */ +void nsc_icache_flush(void); + +#ifdef __cplusplus +} +#endif + +/// @} diff --git a/ATM33xx-5/drivers/sec_dev_lockout/sec_dev_lockout.c b/ATM33xx-5/drivers/sec_dev_lockout/sec_dev_lockout.c new file mode 100644 index 0000000..5c015a6 --- /dev/null +++ b/ATM33xx-5/drivers/sec_dev_lockout/sec_dev_lockout.c @@ -0,0 +1,56 @@ +/** + ****************************************************************************** + * + * @file sec_dev_lockout.c + * + * @brief Secure device feature lockout driver + * + * Copyright (C) Atmosic 2022-2023 + * + ****************************************************************************** + */ + +#include "arch.h" +#include +#include "sec_dev_lockout.h" +#include "at_wrpr.h" +#include "at_apb_clkrstgen_regs_core_macro.h" +#include "at_apb_pseq_regs_core_macro.h" +#include "at_apb_shub_regs_core_macro.h" + +bool sec_shutdown_shub(void) +{ + WRPR_CTRL_PUSH(CMSDK_PSEQ, WRPR_CTRL__CLK_ENABLE) + { + // make sure we fully disable the SHUB by clock gating, reseting + // AND cutting off VDD. the FLASH_CTRL1/FLASH_CTRL2 go to their + // reset values when powered back on. + // Once locked the reset value cannot be undone. + uint32_t val = CMSDK_PSEQ_NONSECURE->SENSOR_HUB_CONTROL; + PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN__CLR(val); + PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET__SET(val); + PSEQ_SENSOR_HUB_CONTROL__SHUB_ISO__SET(val); + PSEQ_SENSOR_HUB_CONTROL__SHUB_VDDCUT__SET(val); + CMSDK_PSEQ_NONSECURE->SENSOR_HUB_CONTROL = val; + } + WRPR_CTRL_POP(); + + return true; +} + +bool sec_device_pgm_lockout(uint32_t mask) +{ + WRPR_CTRL_PUSH(CMSDK_CLKRSTGEN_NONSECURE, WRPR_CTRL__CLK_ENABLE) + { + CLKRSTGEN_USER_CLK_GATE_CTRL__STICKY_CLK__MODIFY( + CMSDK_CLKRSTGEN_NONSECURE->USER_CLK_GATE_CTRL, 1); + + CMSDK_WRPR0_NONSECURE->PROT_BITS_SET1 |= mask; + + CLKRSTGEN_USER_CLK_GATE_CTRL__STICKY_CLK__MODIFY( + CMSDK_CLKRSTGEN_NONSECURE->USER_CLK_GATE_CTRL, 0); + } + WRPR_CTRL_POP(); + + return true; +} diff --git a/ATM33xx-5/drivers/sec_dev_lockout/sec_dev_lockout.h b/ATM33xx-5/drivers/sec_dev_lockout/sec_dev_lockout.h new file mode 100644 index 0000000..d7dfe6c --- /dev/null +++ b/ATM33xx-5/drivers/sec_dev_lockout/sec_dev_lockout.h @@ -0,0 +1,140 @@ +/** + ****************************************************************************** + * + * @file sec_dev_lockout.h + * + * @brief Secure device feature lockout driver + * + * Copyright (C) Atmosic 2022 + * + ****************************************************************************** + */ + +#pragma once + +/** + * @defgroup SEC_DEV_LOCKOUT Secure device feature lockout driver + * @ingroup DRIVERS + * @brief Secure device feature lockout driver + * @{ + */ + +#include "at_apb_wrpr_pins_regs_core_macro.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This driver provides APIs to sticky-lock device features to improve + * system security. Once a feature is locked out a system reset is required + * to restore functionality. A secure bootloader or SPE can enable lockouts + * prior to jumping to the next image in the boot chain. + * Lockouts that apply to configurations will only prevent altering the + * configuration post lockdown. + */ + +/// Device feature lockout type +typedef enum { + /// lockout UART0 Transmitter (output is disabled) + SEC_DEV_LOCKOUT_UART0_TX, + /// lockout UART1 Transmitter (output is disabled) + SEC_DEV_LOCKOUT_UART1_TX, + /// lockout sensor hub usage + SEC_DEV_LOCKOUT_SHUB_DISABLE, + /// lockout sensor hub memory access configuration + SEC_DEV_LOCKOUT_SHUB_ACCESS_CFG, + /// lockout QSPI from APB cores (disables usage) + SEC_DEV_LOCKOUT_QSPI_APB, + /// lockout OTP writes (OTP reads are still valid) + SEC_DEV_LOCKOUT_OTP_WR, + /// lockout ROM patch controller configuration (freezes configuration) + SEC_DEV_LOCKOUT_ROM_P_CFG, + SEC_DEV_LOCKOUT_MAX, +} sec_device_lockout_type_t; + +/** + * @brief Shutdown the shub + * + * @note: This function is called by sec_device_set_lockout if the SHUB is + * disabled. + * + * @return true on success + */ +bool sec_shutdown_shub(void); + +/** + * @brief Program device lockout settings + * + * @note: This function is called by sec_device_set_lockout + * + * @param[in] mask the lockout bit mask + * @return true on success + */ +bool sec_device_pgm_lockout(uint32_t mask); + + +/** + * @brief Get device lockout bit mask from type + * + * @note: This function is called by sec_device_set_lockout + * + * @param[in] type the lockout type + * @return mask value + */ +static inline uint32_t sec_dev_lock_get_mask(sec_device_lockout_type_t type) +{ + switch (type) { + case SEC_DEV_LOCKOUT_UART0_TX: + return WRPRPINS_PROT_BITS_SET1__UART0_LOCK_SET__MASK; + case SEC_DEV_LOCKOUT_UART1_TX: + return WRPRPINS_PROT_BITS_SET1__UART1_LOCK_SET__MASK; + case SEC_DEV_LOCKOUT_SHUB_DISABLE: + case SEC_DEV_LOCKOUT_SHUB_ACCESS_CFG: + return WRPRPINS_PROT_BITS_SET1__APB_SHUB_LOCK_SET__MASK; + case SEC_DEV_LOCKOUT_QSPI_APB: + return WRPRPINS_PROT_BITS_SET1__APB_QSPI_LOCK_SET__MASK; + case SEC_DEV_LOCKOUT_OTP_WR: + return WRPRPINS_PROT_BITS_SET1__SUPPRESS_OTP_WRITES__MASK; + case SEC_DEV_LOCKOUT_ROM_P_CFG: + return WRPRPINS_PROT_BITS_SET1__SUPPRESS_ROM_PATCH__MASK; + case SEC_DEV_LOCKOUT_MAX: + default: + return 0; + } +} + +/** + * @brief Lockout a device feature + * + * @note: The device feature is locked out until system reset + * + * @param[in] type the type of device feature to lockout + * @return true on success + */ +static inline bool sec_device_set_lockout(sec_device_lockout_type_t type) +{ + uint32_t mask = sec_dev_lock_get_mask(type); + + if (!mask) { + return false; + } + + if (!sec_device_pgm_lockout(mask)) { + return false; + } + + if (type == SEC_DEV_LOCKOUT_SHUB_DISABLE) { + // we need to shutdown the shub at least once to pin the flash ctrl + // registers to their isolation values + return sec_shutdown_shub(); + } + + return true; +} + +#ifdef __cplusplus +} +#endif + +/// @} diff --git a/ATM33xx-5/drivers/sec_jrnl/sec_jrnl.c b/ATM33xx-5/drivers/sec_jrnl/sec_jrnl.c new file mode 100644 index 0000000..a2a9f29 --- /dev/null +++ b/ATM33xx-5/drivers/sec_jrnl/sec_jrnl.c @@ -0,0 +1,364 @@ +/** + ****************************************************************************** + * + * @file sec_jrnl.c + * + * @brief Secure Journal Driver + * + * Copyright (C) Atmosic 2023-2024 + * + ****************************************************************************** + */ + +#include "arch.h" +#include "string.h" +#include +#include "sec_jrnl.h" +#include "stdio.h" +#include "atm_utils_c.h" +#ifdef SECURE_PROC_ENV +#include "sec_service.h" +#endif + +#if (!defined(SECURE_MODE) && !defined(CFG_NO_SPE)) +#error "sec_jrnl is a secure-only driver. Access APIs through NSC functions" +#endif + +// set to 1 for verbose printing +#define SEC_JRNL_DEBUG 0 + +// offset of magic number +#define SEC_JRNL_MAGIC_OFFSET 0 +// length of magic number (in bytes) +#define SEC_JRNL_MAGIC_LEN 4 +// offset of first tag +#define SEC_JRNL_FIRST_TAG_OFFSET (SEC_JRNL_MAGIC_OFFSET + SEC_JRNL_MAGIC_LEN) + +// Verify offset to sec journal +#define SEC_JRNL_VERIFY_OFFSET(offset) ((offset) < CMSDK_SEC_JOURNAL_SIZE) + +#define SEC_JRNL_VERIFY_OFFSET_BOUNDS(offset, len) \ + (SEC_JRNL_VERIFY_OFFSET(offset) && \ + (((offset) + (len)) < CMSDK_SEC_JOURNAL_SIZE)) + +// Convert offset to sec journal address +#define SEC_JRNL_OFF_TO_PTR(offset) \ + ((uint8_t const *)(SEC_JOURNAL_BASE + offset)) + +// tags are defined using a compressed length format +#define SEC_JRNL_HEADER_SIZE(header) \ + (sizeof(sec_jrnl_header_t) - (atm_get_le16(&(header)->length) & 0x80 ? \ + 0 : 1)) + +#define SEC_JRNL_TAG_SIZE(header) \ + ((atm_get_le16(&(header)->length) & 0x7f) | \ + ((atm_get_le16(&(header)->length) & 0x80) ? \ + ((atm_get_le16(&(header)->length) & 0xff00) >> 1) : 0)) + +#define SEC_JRNL_STATUS_IMMUTABLE_MASK 0x02 +// check if tag is immutable. Status bit is active low +#define SEC_JRNL_TAG_IS_IMMUTABLE(header) \ + (!((header)->status & SEC_JRNL_STATUS_IMMUTABLE_MASK)) + +#define SEC_JRNL_SEC_ONLY_TAG_MASK 0xFC // 0b111111XX +#define SEC_JRNL_SEC_ONLY_TAG_VAL 0xEC // 0b111011XX +#define IS_TAG_SECURE_ONLY(tag) \ + (((tag)&SEC_JRNL_SEC_ONLY_TAG_MASK) == SEC_JRNL_SEC_ONLY_TAG_VAL) + +typedef struct sec_jrnl_header { + uint8_t tag; + uint8_t status; + sec_jrnl_tag_len_t length; +} sec_jrnl_header_t; + +typedef struct sec_jrnl_walk_ctx { + uint32_t offset; + uint32_t next_offset; + uint8_t tag; + sec_jrnl_tag_len_t len; +} sec_jrnl_walk_ctx_t; + +#ifdef SECURE_PROC_ENV +static sec_jrnl_walk_ctx_t ns_walk_ctx; +#endif +static sec_jrnl_walk_ctx_t s_walk_ctx; + +static sec_jrnl_ret_status_t sec_jrnl_verify_magic(void) +{ + static uint8_t const sec_magic[SEC_JRNL_MAGIC_LEN] = {'N', 'V', 'D', 'S'}; + static bool magic_verified = false; + if (magic_verified) { + return SEC_JRNL_OK; + } + if (memcmp(SEC_JRNL_OFF_TO_PTR(SEC_JRNL_MAGIC_OFFSET), sec_magic, + SEC_JRNL_MAGIC_LEN)) { + return SEC_JRNL_BAD_MAGIC; + } + magic_verified = true; + return SEC_JRNL_OK; +} + +static sec_jrnl_ret_status_t sec_jrnl_find_tag(uint8_t tag, + sec_jrnl_tag_len_t *tag_length, uint16_t *tag_offset) +{ + sec_jrnl_ret_status_t ret = sec_jrnl_verify_magic(); + if (ret != SEC_JRNL_OK) { + DEBUG_TRACE_COND(SEC_JRNL_DEBUG, "sec_jrnl_verify_magic failed!"); + return ret; + } + DEBUG_TRACE_COND(SEC_JRNL_DEBUG, "sec_jrnl_find_tag(%#x)", tag); + sec_jrnl_header_t const *jrnl_header; + uint16_t found_tag_offset = SEC_JRNL_MAGIC_OFFSET; + uint16_t found_tag_size = 0; + uint16_t offset = SEC_JRNL_FIRST_TAG_OFFSET; + do { + jrnl_header = (sec_jrnl_header_t const *)SEC_JRNL_OFF_TO_PTR(offset); + if (jrnl_header->tag == tag) { + found_tag_offset = offset; + found_tag_size = SEC_JRNL_TAG_SIZE(jrnl_header); + if (SEC_JRNL_TAG_IS_IMMUTABLE(jrnl_header)) { + // short-circuit if immutable + break; + } + } + offset += + SEC_JRNL_HEADER_SIZE(jrnl_header) + SEC_JRNL_TAG_SIZE(jrnl_header); + } while (jrnl_header->tag != SEC_JRNL_INVALID_TAG); + + if (found_tag_offset == SEC_JRNL_MAGIC_OFFSET) { + DEBUG_TRACE_COND(SEC_JRNL_DEBUG, "No tag found for %#x!", + tag); + return SEC_JRNL_NO_TAG; + } + *tag_offset = found_tag_offset; + if (*tag_length < found_tag_size) { + return SEC_JRNL_LEN_TOO_LONG; + } + + return SEC_JRNL_OK; +} + +static sec_jrnl_ret_status_t sec_jrnl_walk_init_specific_ctx( + sec_jrnl_walk_ctx_t *ctx) +{ + ctx->offset = 0; + ctx->next_offset = SEC_JRNL_FIRST_TAG_OFFSET; + ctx->tag = SEC_JRNL_INVALID_TAG; + ctx->len = 0; + return SEC_JRNL_OK; +} + +static sec_jrnl_ret_status_t +sec_jrnl_walk_read_ctx_curr_tag(sec_jrnl_walk_ctx_t *ctx, uint32_t buf_len, + uint8_t *buffer) +{ + uint32_t offset = ctx->offset; + if (!SEC_JRNL_VERIFY_OFFSET_BOUNDS(offset, buf_len)) { + ASSERT_INFO(0, offset, buf_len); + return SEC_JRNL_BAD_OFFSET; + } + // Can only read up to size of current tag. + if (buf_len > ctx->len) { + return SEC_JRNL_LEN_BAD_LEN; + } + + sec_jrnl_header_t const *jrnl_header = + (sec_jrnl_header_t const *)SEC_JRNL_OFF_TO_PTR(offset); + memcpy(buffer, (SEC_JRNL_OFF_TO_PTR(offset) + + SEC_JRNL_HEADER_SIZE(jrnl_header)), buf_len); + return SEC_JRNL_OK; +} + +static sec_jrnl_ret_status_t sec_jrnl_walk_ctx_tag(sec_jrnl_walk_ctx_t *ctx, + uint8_t *tag, sec_jrnl_tag_len_t *tag_length) +{ + sec_jrnl_ret_status_t ret = sec_jrnl_verify_magic(); + if (ret != SEC_JRNL_OK) { + DEBUG_TRACE_COND(SEC_JRNL_DEBUG, "sec_jrnl_verify_magic failed!"); + return ret; + } + ctx->offset = ctx->next_offset; + if (!SEC_JRNL_VERIFY_OFFSET(ctx->offset)) { + return SEC_JRNL_BAD_OFFSET; + } + + sec_jrnl_header_t const *header = + (sec_jrnl_header_t const *)SEC_JRNL_OFF_TO_PTR(ctx->offset); + ctx->next_offset += + SEC_JRNL_HEADER_SIZE(header) + SEC_JRNL_TAG_SIZE(header); + ctx->tag = header->tag; + *tag = ctx->tag; + ctx->len = SEC_JRNL_TAG_SIZE(header); + *tag_length = ctx->len; + + if (*tag == SEC_JRNL_INVALID_TAG) { + return SEC_JRNL_NO_TAG; + } + return SEC_JRNL_OK; +} + +sec_jrnl_ret_status_t sec_jrnl_walk_init_ctx(void) +{ + return sec_jrnl_walk_init_specific_ctx(&s_walk_ctx); +} + +sec_jrnl_ret_status_t sec_jrnl_walk_read_curr_tag(uint32_t buf_len, + uint8_t *buffer) +{ + return sec_jrnl_walk_read_ctx_curr_tag(&s_walk_ctx, buf_len, buffer); +} + +sec_jrnl_ret_status_t sec_jrnl_walk_tag(uint8_t *tag, + sec_jrnl_tag_len_t *tag_length) +{ + return sec_jrnl_walk_ctx_tag(&s_walk_ctx, tag, tag_length); +} + +sec_jrnl_ret_status_t sec_jrnl_get(uint8_t tag, sec_jrnl_tag_len_t *tag_length, + uint8_t *tag_data) +{ + DEBUG_TRACE_COND(SEC_JRNL_DEBUG, "sec_jrnl_get(%#x)", tag); + sec_jrnl_tag_len_t length = *tag_length; + uint16_t found_tag_offset; + sec_jrnl_ret_status_t ret = + sec_jrnl_find_tag(tag, &length, &found_tag_offset); + if (ret != SEC_JRNL_OK) { + return ret; + } + sec_jrnl_header_t const *jrnl_header = + (sec_jrnl_header_t const *)SEC_JRNL_OFF_TO_PTR(found_tag_offset); + + memcpy(tag_data, (SEC_JRNL_OFF_TO_PTR(found_tag_offset) + + SEC_JRNL_HEADER_SIZE(jrnl_header)), SEC_JRNL_TAG_SIZE(jrnl_header)); + *tag_length = SEC_JRNL_TAG_SIZE(jrnl_header); + return SEC_JRNL_OK; +} + +sec_jrnl_ret_status_t sec_jrnl_get_aligned_32(uint8_t tag, + sec_jrnl_tag_len_t *tag_length, uint32_t *tag_data) +{ + DEBUG_TRACE_COND(SEC_JRNL_DEBUG, "sec_jrnl_get_aligned_32(%#x)", tag); + sec_jrnl_tag_len_t length = *tag_length; + uint16_t found_tag_offset; + sec_jrnl_ret_status_t ret = + sec_jrnl_find_tag(tag, &length, &found_tag_offset); + + if (ret != SEC_JRNL_OK) { + return ret; + } + sec_jrnl_header_t const *jrnl_header = + (sec_jrnl_header_t const *)SEC_JRNL_OFF_TO_PTR(found_tag_offset); + + length = SEC_JRNL_TAG_SIZE(jrnl_header); + // length from jrnl tag must be mod + if (length % 4) { + ASSERT_INFO(0,length, tag); + return SEC_JRNL_LEN_BAD_LEN; + } + uint16_t len_words = length / 4; + // move offset to front of tag data + found_tag_offset += SEC_JRNL_HEADER_SIZE(jrnl_header); + // explict uint32_t copy + for (uint16_t i = 0; i < len_words; i++) { + *tag_data = *(uint32_t const *)SEC_JRNL_OFF_TO_PTR(found_tag_offset); + found_tag_offset += 4; + tag_data++; + } + *tag_length = length; + return SEC_JRNL_OK; +} + +#ifdef SECURE_PROC_ENV + +__attribute__((cmse_nonsecure_entry)) __attribute__((used)) +sec_jrnl_ret_status_t +nsc_sec_jrnl_walk_init_ctx(void) +{ + return sec_jrnl_walk_init_specific_ctx(&ns_walk_ctx); +} + +__attribute__((cmse_nonsecure_entry)) __attribute__((used)) +sec_jrnl_ret_status_t +nsc_sec_jrnl_walk_read_curr_tag(uint32_t buf_len, uint8_t *buffer) +{ + if (!mem_check_has_access(buffer, buf_len, true, true)) { + return SEC_JRNL_NO_ACCESS; + } + if (IS_TAG_SECURE_ONLY(ns_walk_ctx.tag)) { + return SEC_JRNL_NO_ACCESS; + } + return sec_jrnl_walk_read_ctx_curr_tag(&ns_walk_ctx, buf_len, buffer); +} + +__attribute__((cmse_nonsecure_entry)) __attribute__((used)) +sec_jrnl_ret_status_t +nsc_sec_jrnl_walk_tag(uint8_t *tag, sec_jrnl_tag_len_t *tag_length) +{ + if (!mem_check_has_access(tag, sizeof(uint8_t), true, true)) { + return SEC_JRNL_NO_ACCESS; + } + if (!mem_check_has_access(tag_length, sizeof(sec_jrnl_tag_len_t), true, + true)) { + return SEC_JRNL_NO_ACCESS; + } + sec_jrnl_ret_status_t ret; + do { + ret = sec_jrnl_walk_ctx_tag(&ns_walk_ctx, tag, tag_length); + } while (IS_TAG_SECURE_ONLY(*tag)); + return ret; +} + +__attribute__((cmse_nonsecure_entry)) +__attribute__((used)) +sec_jrnl_ret_status_t nsc_sec_jrnl_get(uint8_t tag, sec_jrnl_tag_len_t *tag_length, + uint8_t *tag_data) +{ + if (!mem_check_has_access(tag_length, sizeof(sec_jrnl_tag_len_t), true, + true)) { + return SEC_JRNL_NO_ACCESS; + } + if (!mem_check_has_access(tag_data, *tag_length, true, true)) { + return SEC_JRNL_NO_ACCESS; + } + if (IS_TAG_SECURE_ONLY(tag)) { + return SEC_JRNL_TAG_SECURE_ONLY; + } + return sec_jrnl_get(tag, tag_length, tag_data); +} + +__attribute__((cmse_nonsecure_entry)) +__attribute__((used)) +sec_jrnl_ret_status_t nsc_sec_jrnl_get_aligned_32(uint8_t tag, + sec_jrnl_tag_len_t *tag_length, uint32_t *tag_data) +{ + if (!mem_check_has_access(tag_length, sizeof(sec_jrnl_tag_len_t), true, + true)) { + return SEC_JRNL_NO_ACCESS; + } + if (!mem_check_has_access(tag_data, *tag_length, true, true)) { + return SEC_JRNL_NO_ACCESS; + } + if (IS_TAG_SECURE_ONLY(tag)) { + return SEC_JRNL_TAG_SECURE_ONLY; + } + return sec_jrnl_get_aligned_32(tag, tag_length, tag_data); +} +#elif defined(CFG_NO_SPE) + +sec_jrnl_ret_status_t nsc_sec_jrnl_walk_init_ctx(void) + __attribute__((alias("sec_jrnl_walk_init_ctx"))); + +sec_jrnl_ret_status_t nsc_sec_jrnl_walk_read_curr_tag(uint32_t buf_len, + uint8_t *buffer) __attribute__((alias("sec_jrnl_walk_read_curr_tag"))); + +sec_jrnl_ret_status_t nsc_sec_jrnl_walk_tag(uint8_t *tag, + sec_jrnl_tag_len_t *tag_length) __attribute__((alias("sec_jrnl_walk_tag"))); + +sec_jrnl_ret_status_t nsc_sec_jrnl_get(uint8_t tag, uint16_t *tag_length, + uint8_t *tag_data) __attribute__((alias("sec_jrnl_get"))); + +sec_jrnl_ret_status_t nsc_sec_jrnl_get_aligned_32(uint8_t tag, + sec_jrnl_tag_len_t *tag_length, uint32_t *tag_data) + __attribute__((alias("sec_jrnl_get_aligned_32"))); + +#endif diff --git a/ATM33xx-5/drivers/sec_jrnl/sec_jrnl.h b/ATM33xx-5/drivers/sec_jrnl/sec_jrnl.h new file mode 100644 index 0000000..45df64a --- /dev/null +++ b/ATM33xx-5/drivers/sec_jrnl/sec_jrnl.h @@ -0,0 +1,180 @@ +/** + ****************************************************************************** + * + * @file sec_jrnl.h + * + * @brief Secure Jornal driver + * + * Copyright (C) Atmosic 2022-2024 + * + ****************************************************************************** + */ + +#pragma once + +/** + * @defgroup SEC_JRNL Secure Journal + * @ingroup DRIVERS + * @brief Secure Journal driver + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/// Secure Journal start address +#define CMSDK_SEC_JOURNAL_BASE 0x1008f800 +#ifndef SEC_JOURNAL_BASE +#define SEC_JOURNAL_BASE CMSDK_SEC_JOURNAL_BASE +#endif +/// Secure Journal journal size +#define CMSDK_SEC_JOURNAL_SIZE 1776 + +/// invalid tag value +#define SEC_JRNL_INVALID_TAG 0xff + +/// Secure Journal return values +typedef enum { + /// OK + SEC_JRNL_OK, + /// Tag not found + SEC_JRNL_NO_TAG, + /// Magic Number is corrupt + SEC_JRNL_BAD_MAGIC, + /// Caller doesnt have access to passed buffer + SEC_JRNL_NO_ACCESS, + /// Caller passed invalid offset + SEC_JRNL_BAD_OFFSET, + /// Stored length is not aligned to necessary boundary + SEC_JRNL_LEN_BAD_LEN, + /// Stored length exceeds pass buffer size + SEC_JRNL_LEN_TOO_LONG, + /// NS Caller doesnt have access to secure-only tag. + SEC_JRNL_TAG_SECURE_ONLY, +} sec_jrnl_ret_status_t; + +typedef uint16_t sec_jrnl_tag_len_t; + +#if (defined(SECURE_MODE) || defined(CFG_NO_SPE)) + +/** + * @brief Initialize walk context + * + * @note should be called prior to starting a walk via `sec_jrnl_walk_tag` + */ +sec_jrnl_ret_status_t sec_jrnl_walk_init_ctx(void); + +/** + * @brief Read tag data at given offset + * + * @param[in] buf_len lengh of input buffer + * @param[out] buffer output buffer + * @return sec_jrnl_ret_status_t SEC_JRNL_OK on success + */ +__NONNULL(2) +sec_jrnl_ret_status_t sec_jrnl_walk_read_curr_tag(uint32_t buf_len, + uint8_t *buffer); + +/** + * @brief Walk a single tag in memory + * + * @param[out] tag tag found from walk + * @param[out] tag_length length of tag data + * @return sec_jrnl_ret_status_t SEC_JRNL_OK on success + */ +__NONNULL_ALL +sec_jrnl_ret_status_t sec_jrnl_walk_tag(uint8_t *tag, + sec_jrnl_tag_len_t *tag_length); + +/** + * @brief Get secure journal tag + * + * @param[in] tag specified tag to return + * @param[in,out] tag_length length of tag data + * @param[out] tag_data output buffer of tag data + * @return sec_jrnl_ret_status_t return status + */ +__NONNULL(2, 3) +sec_jrnl_ret_status_t sec_jrnl_get(uint8_t tag, uint16_t *tag_length, + uint8_t *tag_data); + +/** + * @brief Get secure journal tag (write aligned 32bit) + * + * @param[in] tag specified tag to return + * @param[in,out] tag_length length of tag data + * @param[out] tag_data output buffer of tag data + * @return sec_jrnl_ret_status_t return status + */ +__NONNULL(2, 3) +sec_jrnl_ret_status_t sec_jrnl_get_aligned_32(uint8_t tag, + sec_jrnl_tag_len_t *tag_length, uint32_t *tag_data); +#endif + +/** + * @brief Initialize walk context (NS-callable) + * + * @note should be called prior to starting a walk via `nsc_sec_jrnl_walk_tag` + */ +sec_jrnl_ret_status_t nsc_sec_jrnl_walk_init_ctx(void); + +/** + * @brief Read current tag in sec_jrnl_walk (NS-callable) + * + * @param[in] buf_len lengh of input buffer + * @param[out] buffer output buffer + * @return sec_jrnl_ret_status_t SEC_JRNL_OK on success + */ +__NONNULL(2) +sec_jrnl_ret_status_t nsc_sec_jrnl_walk_read_curr_tag(uint32_t buf_len, + uint8_t *buffer); + +/** + * @brief Walk a single tag in memory (NS-callable) + * + * @note Internally, the walk will skip all secure-only tags. + * + * @param[out] tag tag found from walk + * @param[out] tag_length length of tag data + * @return sec_jrnl_ret_status_t SEC_JRNL_OK on success + */ +__NONNULL_ALL +sec_jrnl_ret_status_t nsc_sec_jrnl_walk_tag(uint8_t *tag, + sec_jrnl_tag_len_t *tag_length); + +/** + * @brief Get secure journal tag (NS-callable) + * + * If return value is SEC_JRNL_TAG_SECURE_ONLY, then requested tag is a + * secure-only tag. These tags cannot be read out by NSC functions + * + * @param[in] tag specified tag to return + * @param[in,out] tag_length length of tag data + * @param[out] tag_data output buffer of tag data + * @return sec_jrnl_ret_status_t return status + */ +__NONNULL(2, 3) +sec_jrnl_ret_status_t nsc_sec_jrnl_get(uint8_t tag, uint16_t *tag_length, + uint8_t *tag_data); + +/** + * @brief Get secure journal tag (write aligned 32bit) (NS-callable) + * + * If return value is SEC_JRNL_TAG_SECURE_ONLY, then requested tag is a + * secure-only tag. These tags cannot be read out by NSC functions + * + * @param[in] tag specified tag to return + * @param[in,out] tag_length length of tag data + * @param[out] tag_data output buffer of tag data + * @return sec_jrnl_ret_status_t return status + */ +__NONNULL(2, 3) +sec_jrnl_ret_status_t nsc_sec_jrnl_get_aligned_32(uint8_t tag, + sec_jrnl_tag_len_t *tag_length, uint32_t *tag_data); + +#ifdef __cplusplus +} +#endif + +/// @} diff --git a/ATM33xx-5/drivers/sec_reset/sec_reset.c b/ATM33xx-5/drivers/sec_reset/sec_reset.c new file mode 100644 index 0000000..4a185ae --- /dev/null +++ b/ATM33xx-5/drivers/sec_reset/sec_reset.c @@ -0,0 +1,99 @@ +/** + ******************************************************************************* + * + * @file sec_reset.c + * + * @brief Secure reset driver implementation + * + * Copyright (C) Atmosic 2022-2024 + * + ******************************************************************************* + */ + +#include "arch.h" +#include "sec_service.h" +#include "sec_reset.h" + +#if (!defined(SECURE_MODE) && !defined(CFG_NO_SPE)) +#error "sec_reset is a secure-only driver" +#endif + +#ifdef MCUBOOT +#include "at_wrpr.h" +#include "at_apb_pseq_regs_core_macro.h" +#include "pseq_status.h" +#endif + +static uint32_t get_and_clear_reset_syndrome(bool clear) +{ + static uint32_t reset_syndrome_check; + if (!reset_syndrome_check) { + reset_syndrome_check = SYS_CTRL_REG->RESET_SYNDROME; + if (clear) { + SYS_CTRL_REG->RESET_SYNDROME = 0; + } + } + return reset_syndrome_check; +} + +#ifdef MCUBOOT + +#define PSEQ_STATUS_TRIGGER_ALLOW_MASK \ + (PSEQ_STATUS__TIMER_TRIGGERED__MASK | PSEQ_STATUS__GPIO_TRIGGERED__MASK | \ + PSEQ_STATUS__WURX0_TRIGGERED__MASK | \ + PSEQ_STATUS__WURX1_TRIGGERED__MASK | \ + PSEQ_STATUS__QDEC_TRIGGERED__MASK | PSEQ_STATUS__KSM_TRIGGERED__MASK | \ + PSEQ_STATUS__SHUB_TRIGGERED__MASK | PSEQ_STATUS__SPI_TRIGGERED__MASK | \ + PSEQ_STATUS__I2C_TRIGGERED__MASK | PSEQ_STATUS__WURX_TRIGGERED__MASK) + +#define SYS_WARM_RESET_MASK \ + (SYS_CTRL_REG_SSE200_RESET_SYNDROME_NSWD_Msk | \ + SYS_CTRL_REG_SSE200_RESET_SYNDROME_SWD_Msk | \ + SYS_CTRL_REG_SSE200_RESET_SYNDROME_RESETREQ_Msk | \ + SYS_CTRL_REG_SSE200_RESET_SYNDROME_SWRESETREQ_Msk | \ + SYS_CTRL_REG_SSE200_RESET_SYNDROME_SYSRSTREQ0_Msk | \ + SYS_CTRL_REG_SSE200_RESET_SYNDROME_SYSRSTREQ1_Msk | \ + SYS_CTRL_REG_SSE200_RESET_SYNDROME_LOCKUP0_Msk | \ + SYS_CTRL_REG_SSE200_RESET_SYNDROME_LOCKUP1_Msk) + +uint32_t secure_reset_get_syndrome(void) +{ + return get_and_clear_reset_syndrome(false); +} + +secure_reset_type secure_reset_get_type(void) +{ + if (secure_reset_get_syndrome() & SYS_WARM_RESET_MASK) { + return SECURE_RESET_TYPE_WARM; + } + + static uint32_t pseq_po_reason; + static bool check_pseq_po; + if (!check_pseq_po) { + WRPR_CTRL_PUSH(CMSDK_PSEQ, WRPR_CTRL__CLK_ENABLE) + { + pseq_po_reason = CMSDK_PSEQ->STATUS & PSEQ_STATUS__POWER_ON_REASONS; + } + WRPR_CTRL_POP(); + check_pseq_po = true; + } + + if (pseq_po_reason & PSEQ_STATUS_TRIGGER_ALLOW_MASK) { + return SECURE_RESET_TYPE_HIB_ALLOW_IMG_SKIP; + } + + if (pseq_po_reason) { + return SECURE_RESET_TYPE_HIB; + } + + // treat everything else from a security prespective as power-on + return SECURE_RESET_TYPE_POR; +} + +#else +__SPE_NSC +uint32_t secure_rclr_reset_syndrome(void) +{ + return get_and_clear_reset_syndrome(true); +} +#endif // MCUBOOT \ No newline at end of file diff --git a/ATM33xx-5/drivers/sec_reset/sec_reset.h b/ATM33xx-5/drivers/sec_reset/sec_reset.h new file mode 100644 index 0000000..96d2b8e --- /dev/null +++ b/ATM33xx-5/drivers/sec_reset/sec_reset.h @@ -0,0 +1,66 @@ +/** + ******************************************************************************* + * + * @file sec_reset.h + * + * @brief Secure reset driver header file + * + * Copyright (C) Atmosic 2022-2024 + * + ******************************************************************************* + */ + +#pragma once + +/** + * @defgroup SEC_RESET Secure reset + * @ingroup DRIVERS + * @brief Secure reset driver + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef MCUBOOT + +typedef enum { + SECURE_RESET_TYPE_UNKNOWN, + SECURE_RESET_TYPE_POR, // power on reset + SECURE_RESET_TYPE_WARM, // warm reset + SECURE_RESET_TYPE_HIB_ALLOW_IMG_SKIP, // hibernate triggers that allow image + // skip + SECURE_RESET_TYPE_HIB, // other wake from hibernate triggers occurred +} secure_reset_type; + +/** + * @brief Get the current system reset syndrome value. + * + * @return SOC specific reset syndrome value + * @note Only reads and does not clear the syndrome. + */ +uint32_t secure_reset_get_syndrome(void); + +/** + * @brief Get the reset type at bootup + * + * @return the reset type + * @note This should be called in early boot before the syndrome is cleared. + */ +secure_reset_type secure_reset_get_type(void); + +#else +/** + * @brief Read and clear reset syndrome + * @return Reset syndrome value + * + */ +uint32_t secure_rclr_reset_syndrome(void); +#endif // MCUBOOT + +#ifdef __cplusplus +} +#endif + +/// @} diff --git a/ATM33xx-5/drivers/spi/qspi.h b/ATM33xx-5/drivers/spi/qspi.h new file mode 100644 index 0000000..7fa5f51 --- /dev/null +++ b/ATM33xx-5/drivers/spi/qspi.h @@ -0,0 +1,220 @@ +/** + ******************************************************************************* + * + * @file qspi.h + * + * @brief QSPI driver + * + * Copyright (C) Atmosic 2018-2022 + * + ******************************************************************************* + */ + +#ifndef __QSPI_H__ +#define __QSPI_H__ + +/** + * @defgroup QSPI QSPI + * @ingroup DRIVERS + * @brief User driver for QSPI master interface + * @{ + */ + +#include + +#include "at_apb_qspi_regs_core_macro.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Begin QSPI transaction + */ +#ifndef __GNUC__ +__INLINE void +#else +static inline void +#endif +qspi_drive_start(void) +{ + CMSDK_QSPI->TRANSACTION_SETUP = QSPI_TRANSACTION_SETUP__CSN_VAL__MASK; +} + +/** + * @brief Drive serial SPI command + * @param[in] cmd 8-bit command to drive on DOUT_0 + */ +#ifndef __GNUC__ +__INLINE void +#else +static inline void +#endif +qspi_drive_serial_cmd(uint8_t cmd) +{ + for (int i=0; i<8; i++, cmd<<=1) { + uint32_t oe = ((cmd & 0x80) ? 0x0003 : 0x0002) + << QSPI_TRANSACTION_SETUP__DOUT_0_CTRL__SHIFT; + + CMSDK_QSPI->TRANSACTION_SETUP = oe; + CMSDK_QSPI->TRANSACTION_SETUP = oe | + QSPI_TRANSACTION_SETUP__CLK_VAL__MASK; + } +} + +/** + * @brief Read SPI input for 8 cycles + * @return read byte + */ +#ifndef CFG_ROM +__INLINE uint8_t +qspi_read_serial_byte(void) +{ + uint8_t data = 0; + for (uint8_t i = 0x80; i; i >>= 1) { + CMSDK_QSPI->TRANSACTION_SETUP = 0; + CMSDK_QSPI->TRANSACTION_SETUP = QSPI_TRANSACTION_SETUP__CLK_VAL__MASK; + CMSDK_QSPI->TRANSACTION_SETUP = QSPI_TRANSACTION_SETUP__CLK_VAL__MASK | + QSPI_TRANSACTION_SETUP__SAMPLE_DIN__WRITE(0x02); + + if (CMSDK_QSPI->READ_DATA & 0x02) { + data |= i; + } + } + return (data); +} +#endif + +/** + * @brief Convert nibble to OE/val format for TRANSACTION_SETUP register + * @param[in] nibble 4-bit value to convert + * @return OE/val format for TRANSACTION_SETUP register + */ +#ifndef __GNUC__ +__INLINE uint32_t +to_oe_format_quad(uint8_t nibble) +{ + if (nibble > 0xf) { + return 0; + } + return (0x2222 | (nibble & 0x1) | ((nibble & 0x2) << 3) | + ((nibble & 0x4) << 6) | ((nibble & 0x8) << 9)); +} +#else +static inline uint32_t +to_oe_format_quad(uint8_t nibble) +{ + switch (nibble) { + case 0x0: return 0x2222; + case 0x1: return 0x2223; + case 0x2: return 0x2232; + case 0x3: return 0x2233; + case 0x4: return 0x2322; + case 0x5: return 0x2323; + case 0x6: return 0x2332; + case 0x7: return 0x2333; + case 0x8: return 0x3222; + case 0x9: return 0x3223; + case 0xa: return 0x3232; + case 0xb: return 0x3233; + case 0xc: return 0x3322; + case 0xd: return 0x3323; + case 0xe: return 0x3332; + case 0xf: return 0x3333; + default: break; + } + return 0; +} +#endif + +/** + * @brief Drive all QSPI outputs for a single cycle + * @param[in] nibble 4-bit value to drive + */ +#ifndef __GNUC__ +__INLINE void +#else +static inline void +#endif +qspi_drive_nibble(uint8_t nibble) +{ + uint32_t oe = to_oe_format_quad(nibble) + << QSPI_TRANSACTION_SETUP__DOUT_0_CTRL__SHIFT; + CMSDK_QSPI->TRANSACTION_SETUP = oe; + CMSDK_QSPI->TRANSACTION_SETUP = QSPI_TRANSACTION_SETUP__CLK_VAL__MASK | oe; +} + +/** + * @brief Drive all QSPI outputs for two cycles + * @param[in] byte 8-bit value to drive + */ +#ifndef __GNUC__ +__INLINE void +#else +static inline void +#endif +qspi_drive_byte(uint8_t byte) +{ + qspi_drive_nibble((byte & 0xf0) >> 4); + qspi_drive_nibble(byte & 0x0f); +} + +/** + * @brief Drive dummy cycles on QSPI bus + * @param[in] cycles Number of dummy cycles to drive + */ +#ifndef __GNUC__ +__INLINE void +#else +static inline void +#endif +qspi_dummy(uint8_t cycles) +{ + for (; cycles; cycles--) { + CMSDK_QSPI->TRANSACTION_SETUP = 0; + CMSDK_QSPI->TRANSACTION_SETUP = QSPI_TRANSACTION_SETUP__CLK_VAL__MASK; + } +} + +/** + * @brief Read all QSPI inputs for two cycles + */ +#ifndef __GNUC__ +__INLINE void +#else +static inline void +#endif +qspi_capture_byte(void) +{ + CMSDK_QSPI->TRANSACTION_SETUP = 0; + CMSDK_QSPI->TRANSACTION_SETUP = QSPI_TRANSACTION_SETUP__CLK_VAL__MASK; + CMSDK_QSPI->TRANSACTION_SETUP = QSPI_TRANSACTION_SETUP__CLK_VAL__MASK | + QSPI_TRANSACTION_SETUP__SAMPLE_DIN__WRITE(0xf0); + + CMSDK_QSPI->TRANSACTION_SETUP = 0; + CMSDK_QSPI->TRANSACTION_SETUP = QSPI_TRANSACTION_SETUP__CLK_VAL__MASK; + CMSDK_QSPI->TRANSACTION_SETUP = QSPI_TRANSACTION_SETUP__CLK_VAL__MASK | + QSPI_TRANSACTION_SETUP__SAMPLE_DIN__WRITE(0x0f); +} + +/** + * @brief End QSPI transaction + */ +#ifndef __GNUC__ +__INLINE void +#else +static inline void +#endif +qspi_drive_stop(void) +{ + CMSDK_QSPI->TRANSACTION_SETUP = 0; + CMSDK_QSPI->TRANSACTION_SETUP = QSPI_TRANSACTION_SETUP__CSN_VAL__MASK; +} + +#ifdef __cplusplus +} +#endif + +/// @} QSPI + +#endif // __QSPI_H__ diff --git a/ATM33xx-5/drivers/spi/spi.c b/ATM33xx-5/drivers/spi/spi.c new file mode 100644 index 0000000..8f1021f --- /dev/null +++ b/ATM33xx-5/drivers/spi/spi.c @@ -0,0 +1,211 @@ +/***************************************************************************************** +* +* @file spi.c +* +* @brief Sydney 1.0 SPI driver +* +* Copyright (C) Atmosic 2018-2023 +* +* +*****************************************************************************************/ + +#ifdef CONFIG_SOC_FAMILY_ATM +#include +#include +#include +#endif + +#include "arch.h" +#include "spi.h" +#include "pmu_spi.h" +#include "radio_spi.h" +#include "at_wrpr.h" +#include "at_apb_pseq_regs_core_macro.h" +#include "atm_bp_clock.h" + +#if defined(CFG_ROM) || defined(CFG_USER) +const +#else +// Make certain this structure isn't located in flash +__attribute__((section(".data"))) +#endif +spi_dev_t spi2_8MHz_0 = { CMSDK_SPI2, 0, 0 }; + +#if defined(CFG_ROM) || defined(CFG_USER) +const +#endif +spi_dev_t spi_pmu = { CMSDK_PMU, 0, PMU_SPI__DUMMY_CYCLES }; + +#if defined(CFG_ROM) || defined(CFG_USER) +const +#else +// Make certain this structure isn't located in flash +__attribute__((section(".data"))) +#endif +spi_dev_t spi_radio = { CMSDK_RADIO, 0, RADIO_SPI__DUMMY_CYCLES }; + +uint8_t +spi_read(const spi_dev_t *spi, uint8_t opcode) +{ + do_spi_transaction(spi, 0, opcode, 1, 0x0, 0x0); + return (spi->base->DATA_BYTES_LOWER); +} + +uint16_t +spi_read_2(const spi_dev_t *spi, uint8_t opcode) +{ + do_spi_transaction(spi, 0, opcode, 2, 0x0, 0x0); + return (spi->base->DATA_BYTES_LOWER); +} + +uint32_t +spi_read_3(const spi_dev_t *spi, uint8_t opcode) +{ + do_spi_transaction(spi, 0, opcode, 3, 0x0, 0x0); + return (spi->base->DATA_BYTES_LOWER & 0xffffff); +} + +uint32_t +spi_read_4(const spi_dev_t *spi, uint8_t opcode) +{ + do_spi_transaction(spi, 0, opcode, 4, 0x0, 0x0); + return (spi->base->DATA_BYTES_LOWER); +} + +void +spi_write(const spi_dev_t *spi, uint8_t opcode, uint8_t data) +{ + do_spi_transaction(spi, 0, opcode, 1, 0x0, data); +} + +void +spi_write_2(const spi_dev_t *spi, uint8_t opcode, uint16_t data) +{ + do_spi_transaction(spi, 0, opcode, 2, 0x0, data); +} + +void +spi_write_3(const spi_dev_t *spi, uint8_t opcode, uint32_t data) +{ + do_spi_transaction(spi, 0, opcode, 3, 0x0, data); +} + +void +spi_write_4(const spi_dev_t *spi, uint8_t opcode, uint32_t data) +{ + do_spi_transaction(spi, 0, opcode, 4, 0x0, data); +} + +uint32_t +spi_pmuradio_read_word(const spi_dev_t *spi, uint8_t block, uint8_t addr) +{ + uint8_t opcode = block << 4; + + do_spi_transaction(spi, 0, opcode, 5, 0x0, addr); + return ((spi->base->DATA_BYTES_UPPER << 24) | + (spi->base->DATA_BYTES_LOWER >> 8)); +} + +void +spi_pmuradio_write_word(const spi_dev_t *spi, uint8_t block, uint8_t addr, + uint32_t data) +{ + uint8_t opcode = (block << 4) | 0x1; + uint32_t lower = (data << 8) | addr; + uint32_t upper = data >> 24; + + do_spi_transaction(spi, 0, opcode, 5, upper, lower); +} + +#ifdef SPI_TRANS_WFI +#include "vectors.h" + +__INLINE void spi_interrupt_handler(CMSDK_AT_APB_SPI_TypeDef *base) +{ + // Nothing to do here but clear the interrupt source. + uint32_t status = base->INTERRUPT_STATUS; + base->RESET_INTERRUPT = status; + base->RESET_INTERRUPT = 0; + // WFI will wake up and continue. +} + +#ifndef OVERRIDE_SPI_ISR +void SPI0_Handler(void) +{ + spi_interrupt_handler(CMSDK_SPI0); +} + +void SPI1_Handler(void) +{ + spi_interrupt_handler(CMSDK_SPI1); +} +#endif + +void SPI2_Handler(void) +{ + spi_interrupt_handler(CMSDK_SPI2); +} + +void SPI_RADIO_Handler(void) +{ + spi_interrupt_handler(CMSDK_RADIO); +} + +void SPI_PMU_Handler(void) +{ + spi_interrupt_handler(CMSDK_PMU); +} + +#ifdef PSEQ_CTRL0__SPI_LATCH_OPEN__CLR +__FAST +static void spi_pseq_latch_close(void) +{ + WRPR_CTRL_SET(CMSDK_PSEQ, WRPR_CTRL__CLK_ENABLE); + { + PSEQ_CTRL0__SPI_LATCH_OPEN__CLR(CMSDK_PSEQ->CTRL0); + } + WRPR_CTRL_SET(CMSDK_PSEQ, WRPR_CTRL__CLK_DISABLE); +} + +__FAST +static rep_vec_err_t spi_back_from_retain_all(void) +{ + spi_pseq_latch_close(); + return RV_NEXT; +} +#endif +#endif // SPI_TRANS_WFI + +#ifndef CONFIG_SOC_FAMILY_ATM +__CONSTRUCTOR_PRIO(CONSTRUCTOR_SPI) +#endif +static void spi_constructor(void) +{ +#if !(defined(CFG_ROM) || defined(CFG_USER)) + uint32_t bp_freq = atm_bp_clock_get(); + uint16_t clkdiv = (bp_freq / 16000000U) - 1; + + spi2_8MHz_0.clkdiv = spi_pmu.clkdiv = spi_radio.clkdiv = clkdiv; +#endif + +#ifdef SPI_TRANS_WFI + NVIC_EnableIRQ(SPI0_IRQn); + NVIC_EnableIRQ(SPI1_IRQn); + NVIC_EnableIRQ(SPI2_IRQn); + NVIC_EnableIRQ(SPI_RADIO_IRQn); + NVIC_EnableIRQ(SPI_PMU_IRQn); +#ifdef PSEQ_CTRL0__SPI_LATCH_OPEN__CLR + RV_PLF_BACK_FROM_RETAIN_ALL_ADD(spi_back_from_retain_all); +#endif +#endif // SPI_TRANS_WFI +} + +#ifdef CONFIG_SOC_FAMILY_ATM +static int spi_sys_init(void) +{ + spi_constructor(); + return 0; +} + +SYS_INIT(spi_sys_init, PRE_KERNEL_2, 2); +#endif diff --git a/ATM33xx-5/drivers/spi/spi.h b/ATM33xx-5/drivers/spi/spi.h new file mode 100644 index 0000000..cc2cf56 --- /dev/null +++ b/ATM33xx-5/drivers/spi/spi.h @@ -0,0 +1,271 @@ +/** + ******************************************************************************* + * + * @file spi.h + * + * @brief SPI driver + * + * Copyright (C) Atmosic 2018-2023 + * + ******************************************************************************* + */ + +#pragma once + +/** + * @defgroup SPI SPI + * @ingroup DRIVERS + * @brief User driver for SPI master interface + * @{ + */ + +#include +#include + +#include "at_apb_spi_regs_core_macro.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/// Device structure +typedef struct spi_dev_s { + CMSDK_AT_APB_SPI_TypeDef *base; + uint16_t clkdiv; + uint8_t dummy_cycles; +} spi_dev_t; + +/// SPI2 device, 8MHz clk, no dummy cycles +extern +#if defined(CFG_ROM) || defined(CFG_USER) +const +#endif +spi_dev_t spi2_8MHz_0; + +/// SPI interface to PMU +extern +#if defined(CFG_ROM) || defined(CFG_USER) +const +#endif +spi_dev_t spi_pmu; + +/// SPI interface to RADIO +extern +#if defined(CFG_ROM) || defined(CFG_USER) +const +#endif +spi_dev_t spi_radio; + +/** + * @brief Base function for all SPI transactions. + * @param[in] spi Device structure. + * @param[in] csn_stays_low State of select at end of transaction. + * @param[in] opcode First byte written to bus by master. + * @param[in] num_data_bytes Total bytes in transaction. + * @param[in] upper Upper 4 bytes to read/write. + * @param[in] lower Lower 4 bytes to read/write. + */ +#ifdef CFG_ROM +static inline +#else +__INLINE +#endif +void +do_spi_transaction(const spi_dev_t *spi, bool csn_stays_low, + uint8_t opcode, uint8_t num_data_bytes, uint32_t upper, uint32_t lower) +{ + uint32_t transaction = + SPI_TRANSACTION_SETUP__DUMMY_CYCLES__WRITE(spi->dummy_cycles) | + SPI_TRANSACTION_SETUP__CSN_STAYS_LOW__WRITE(csn_stays_low) | + SPI_TRANSACTION_SETUP__OPCODE__WRITE(opcode) | + SPI_TRANSACTION_SETUP__CLKDIV__WRITE(spi->clkdiv) | + SPI_TRANSACTION_SETUP__RWB__MASK | + SPI_TRANSACTION_SETUP__NUM_DATA_BYTES__WRITE(num_data_bytes); + + spi->base->DATA_BYTES_LOWER = lower; + spi->base->DATA_BYTES_UPPER = upper; +#ifdef SPI_TRANS_WFI + spi->base->RESET_INTERRUPT = SPI_RESET_INTERRUPT__WRITE; + spi->base->RESET_INTERRUPT = 0; + IPSR_Type psr = {.w = __get_IPSR()}; + // check if we can use WFI + // - Not in an interrupt handler + // - Only when interrupts are enabled by the driver constructor + bool can_use_wfi = !psr.b.ISR && NVIC_GetEnableIRQ(SPI_PMU_IRQn); + if (can_use_wfi) { + spi->base->INTERRUPT_MASK = SPI_INTERRUPT_MASK__WRITE; + } +#endif + spi->base->TRANSACTION_SETUP = transaction; + spi->base->TRANSACTION_SETUP = transaction | + SPI_TRANSACTION_SETUP__START__MASK; + +#ifdef SPI_TRANS_WFI + if (!can_use_wfi) { + // can't use WFI at the moment + while (spi->base->TRANSACTION_STATUS & + SPI_TRANSACTION_STATUS__RUNNING__MASK) { + YIELD(); + } + } else { + WFI_COND(!(spi->base->TRANSACTION_STATUS & + SPI_TRANSACTION_STATUS__RUNNING__MASK)); + } + spi->base->INTERRUPT_MASK = 0; +#else + while (spi->base->TRANSACTION_STATUS & + SPI_TRANSACTION_STATUS__RUNNING__MASK) { + YIELD(); + } +#endif +} + +/** + * @brief Read addressed single byte from SPI slave device. + * @param[in] spi Device structure. + * @param[in] opcode Single byte opcode/address of data to read. + * @return Data read from SPI slave device. + */ +uint8_t spi_read(const spi_dev_t *spi, uint8_t opcode); + +/** + * @brief Read addressed 2 bytes from SPI slave device. + * @param[in] spi Device structure. + * @param[in] opcode Single byte opcode/address of data to read. + * @return Data read from SPI slave device. + */ +uint16_t spi_read_2(const spi_dev_t *spi, uint8_t opcode); + +/** + * @brief Read addressed 3 bytes from SPI slave device. + * @param[in] spi Device structure. + * @param[in] opcode Single byte opcode/address of data to read. + * @return Data read from SPI slave device. + */ +uint32_t spi_read_3(const spi_dev_t *spi, uint8_t opcode); + +/** + * @brief Read addressed 4 bytes from SPI slave device. + * @param[in] spi Device structure. + * @param[in] opcode Single byte opcode/address of data to read. + * @return Data read from SPI slave device. + */ +uint32_t spi_read_4(const spi_dev_t *spi, uint8_t opcode); + + +/** + * @brief Write addressed single byte to SPI slave device. + * @param[in] spi Device structure. + * @param[in] opcode Single byte opcode/address of data to write. + * @param[in] data Data to write to SPI slave device. + */ +void spi_write(const spi_dev_t *spi, uint8_t opcode, uint8_t data); + +/** + * @brief Write addressed 2 bytes to SPI slave device. + * @param[in] spi Device structure. + * @param[in] opcode Single byte opcode/address of data to write. + * @param[in] data Data to write to SPI slave device. + */ +void spi_write_2(const spi_dev_t *spi, uint8_t opcode, uint16_t data); + +/** + * @brief Write addressed 3 bytes to SPI slave device. + * @param[in] spi Device structure. + * @param[in] opcode Single byte opcode/address of data to write. + * @param[in] data Data to write to SPI slave device. + */ +void spi_write_3(const spi_dev_t *spi, uint8_t opcode, uint32_t data); + +/** + * @brief Write addressed 4 bytes to SPI slave device. + * @param[in] spi Device structure. + * @param[in] opcode Single byte opcode/address of data to write. + * @param[in] data Data to write to SPI slave device. + */ +void spi_write_4(const spi_dev_t *spi, uint8_t opcode, uint32_t data); + + +/** + * @brief Read PMU or RADIO module register. + * @param[in] spi Device structure. + * @param[in] block Single byte module block to read. + * @param[in] addr Single byte address of data to read. + * @return Data read from PMU or RADIO module. + */ +uint32_t spi_pmuradio_read_word(const spi_dev_t *spi, uint8_t block, uint8_t addr); + +/** + * @brief Write PMU or RADIO module register. + * @param[in] spi Device structure. + * @param[in] block Single byte module block to write. + * @param[in] addr Single byte address of data to write. + * @param[in] data Data to write to PMU or RADIO module. + */ +void spi_pmuradio_write_word(const spi_dev_t *spi, uint8_t block, uint8_t addr, uint32_t data); + +#ifndef VERIFY_SPI_CAL +#define VERIFY_SPI_CAL PLF_DEBUG +#endif + +#define SPR_READ(__d, __m, __reg) \ + spi_pmuradio_read_word(__d, __m ## __REG_BLADDR, __m ## __ ## __reg) + +#if VERIFY_SPI_CAL +#define SPR_VERIFY(__d, __m, __reg, __val) do { \ + uint32_t read_back = SPR_READ(__d, __m, __reg); \ + ASSERT_INFO((__val) == read_back, (__val), read_back); \ +} while (0) +#else +#define SPR_VERIFY(__d, __m, __reg, __val) do {} while (0) +#endif + +#define SPR_WRITE(__d, __m, __reg, __val) do { \ + uint32_t tmp_val = (__val); \ + spi_pmuradio_write_word(__d, __m ## __REG_BLADDR, __m ## __ ## __reg, \ + tmp_val); \ + SPR_VERIFY(__d, __m, __reg, tmp_val); \ +} while (0) + +#define PMU_READ(__m, __reg) SPR_READ(&spi_pmu, PMU_ ## __m, __reg) +#define PMU_VERIFY(__m, __reg, __val) \ + SPR_VERIFY(&spi_pmu, PMU_ ## __m, __reg, __val) +#define PMU_WRITE(__m, __reg, __val) \ + SPR_WRITE(&spi_pmu, PMU_ ## __m, __reg, __val) + +#define SWREG_READ(__m, __reg) SPR_READ(&spi_pmu, SWREG_ ## __m, __reg) +#define SWREG_WRITE(__m, __reg, __val) \ + SPR_WRITE(&spi_pmu, SWREG_ ## __m, __reg, __val) + +#define PMU_GADC_READ(__reg) PMU_READ(GADC, __reg) +#define PMU_GADC_WRITE(__reg, __val) PMU_WRITE(GADC, __reg, __val) + +#define PMU_SWREG_READ(__reg) PMU_READ(SWREG, __reg) +#define PMU_SWREG_WRITE(__reg, __val) PMU_WRITE(SWREG, __reg, __val) + +#define PMU_TOP_READ(__reg) PMU_READ(TOP, __reg) +#define PMU_TOP_WRITE(__reg, __val) PMU_WRITE(TOP, __reg, __val) + +#define PMU_WURX_READ(__reg) PMU_READ(WURX, __reg) +#define PMU_WURX_WRITE(__reg, __val) PMU_WRITE(WURX, __reg, __val) + +#define RADIO_READ(__m, __reg) SPR_READ(&spi_radio, RADIO_ ## __m, __reg) +#define RADIO_VERIFY(__m, __reg, __val) \ + SPR_VERIFY(&spi_radio, RADIO_ ## __m, __reg, __val) +#define RADIO_WRITE(__m, __reg, __val) \ + SPR_WRITE(&spi_radio, RADIO_ ## __m, __reg, __val) + +#define RADIO_RX_READ(__reg) RADIO_READ(RX, __reg) +#define RADIO_RX_WRITE(__reg, __val) RADIO_WRITE(RX, __reg, __val) + +#define RADIO_SYNTH_READ(__reg) RADIO_READ(SYNTH, __reg) +#define RADIO_SYNTH_WRITE(__reg, __val) RADIO_WRITE(SYNTH, __reg, __val) + +#define RADIO_TOP_READ(__reg) RADIO_READ(TOP, __reg) +#define RADIO_TOP_WRITE(__reg, __val) RADIO_WRITE(TOP, __reg, __val) + +#ifdef __cplusplus +} +#endif + +/// @} SPI diff --git a/ATM33xx-5/drivers/spi/spi_flash.c b/ATM33xx-5/drivers/spi/spi_flash.c new file mode 100644 index 0000000..ad7c872 --- /dev/null +++ b/ATM33xx-5/drivers/spi/spi_flash.c @@ -0,0 +1,214 @@ +/***************************************************************************************** +* +* @file spi_flash.c +* +* @brief Sydney 1.0 SPI flash driver +* +* Copyright (C) Atmosic 2019 +* +* +*****************************************************************************************/ + +#include "arch.h" +#include "spi.h" +#include "spi_flash.h" + +__NR_STATIC uint32_t +spi_flash_addr_to_lower(uint32_t addr) +{ + return (((addr & 0xff) << 16) | + ((addr & 0xff00) << 0) | + ((addr & 0xff0000) >> 16)); +} + +uint8_t +spi_flash_read_byte(const spi_dev_t *spi, uint32_t addr) +{ + const uint8_t opcode = 0x03; // READ + do_spi_transaction(spi, 0, opcode, 4, 0x0, spi_flash_addr_to_lower(addr)); + return (spi->base->DATA_BYTES_LOWER >> 24); +} + +uint16_t +spi_flash_read_short(const spi_dev_t *spi, uint32_t addr) +{ + const uint8_t opcode = 0x03; // READ + do_spi_transaction(spi, 0, opcode, 5, 0x0, spi_flash_addr_to_lower(addr)); + return (((spi->base->DATA_BYTES_UPPER & 0xff) << 8) | + (spi->base->DATA_BYTES_LOWER >> 24)); +} + +uint32_t +spi_flash_read_word(const spi_dev_t *spi, uint32_t addr) +{ + const uint8_t opcode = 0x03; // READ + do_spi_transaction(spi, 0, opcode, 7, 0x0, spi_flash_addr_to_lower(addr)); + return ((spi->base->DATA_BYTES_UPPER << 8) | + (spi->base->DATA_BYTES_LOWER >> 24)); +} + +__NR_STATIC uint8_t +spi_flash_wait_for_no_wip(const spi_dev_t *spi) +{ + uint8_t ret; + + // FIXME: timeout + for (;;) { + ret = spi_read(spi, 0x05); // READ STATUS + if (!(ret & 0x1)) { + break; + } + YIELD(); + } + return ret; +} + +__NR_STATIC void +spi_flash_write_enable(const spi_dev_t *spi) +{ + do_spi_transaction(spi, 0, 0x06, 0, 0x0, 0x0); // WRITE ENABLE +} + +__NR_STATIC void +spi_flash_vsr_write_enable(const spi_dev_t *spi) +{ + do_spi_transaction(spi, 0, 0x50, 0, 0x0, 0x0); // VSR WRITE ENABLE +} + +#ifdef UNUSED +__NR_STATIC void +spi_flash_write_disable(const spi_dev_t *spi) +{ + do_spi_transaction(spi, 0, 0x04, 0, 0x0, 0x0); // WRITE DISABLE +} +#endif + +void +spi_flash_write_byte(const spi_dev_t *spi, uint32_t addr, uint8_t data) +{ + const uint8_t opcode = 0x02; // PAGE PROGRAM + uint32_t lower = (((uint32_t)data) << 24) | spi_flash_addr_to_lower(addr); + + spi_flash_write_enable(spi); + do_spi_transaction(spi, 0, opcode, 4, 0x0, lower); + + spi_flash_wait_for_no_wip(spi); +} + +void +spi_flash_write_short(const spi_dev_t *spi, uint32_t addr, uint16_t data) +{ + const uint8_t opcode = 0x02; // PAGE PROGRAM + uint32_t lower = (((uint32_t)data) << 24) | spi_flash_addr_to_lower(addr); + uint32_t upper = data >> 8; + + spi_flash_write_enable(spi); + do_spi_transaction(spi, 0, opcode, 5, upper, lower); + + spi_flash_wait_for_no_wip(spi); +} + +void +spi_flash_write_word(const spi_dev_t *spi, uint32_t addr, uint32_t data) +{ + const uint8_t opcode = 0x02; // PAGE PROGRAM + uint32_t lower = (((uint32_t)data) << 24) | spi_flash_addr_to_lower(addr); + uint32_t upper = data >> 8; + + spi_flash_write_enable(spi); + do_spi_transaction(spi, 0, opcode, 7, upper, lower); + + spi_flash_wait_for_no_wip(spi); +} + +bool +spi_macronix_make_quad(const spi_dev_t *spi) +{ + spi_flash_wait_for_no_wip(spi); + spi_flash_write_enable(spi); + + // WRITE STATUS REG - High perf, Quad Enable + do_spi_transaction(spi, 0, 0x01, 3, 0x0, 0x020040); + + return ((spi_flash_wait_for_no_wip(spi) & 0x40) == 0x40); +} + +/** + * @brief Command external flash device to exit performance mode. + * + * @note For FlashROM images, __FAST will locate this function in RAM. + */ +__FAST +void +spi_macronix_exit_performance_mode(const spi_dev_t *spi) +{ + do_spi_transaction(spi, 0, 0xff, 0, 0x0, 0x0); +} + +bool +spi_giga_make_quad(const spi_dev_t *spi) +{ + if (spi_read(spi, 0x35) & 0x02) { // READ STATUS REG-2 + // QE already set + return true; + } + + spi_flash_wait_for_no_wip(spi); + spi_flash_write_enable(spi); + + // WRITE STATUS REG - Quad Enable + do_spi_transaction(spi, 0, 0x01, 2, 0x0, 0x0200); + + spi_flash_wait_for_no_wip(spi); + + return ((spi_read(spi, 0x35) & 0x02) == 0x02); +} + +bool +spi_winbond_make_quad(const spi_dev_t *spi) +{ + if (spi_read(spi, 0x35) & 0x02) { // READ STATUS REG-2 + // QE already set + return true; + } + spi_flash_vsr_write_enable(spi); + + // WRITE STATUS REG-2 + do_spi_transaction(spi, 0, 0x31, 1, 0x0, 0x02); + + return ((spi_read(spi, 0x35) & 0x02) == 0x02); +} + +/** + * @brief Command external flash device to power down. + * + * @note For FlashROM images, __FAST will locate this function in RAM. + */ +__FAST +void +spi_macronix_deep_power_down(const spi_dev_t *spi) +{ + // Also works as Winbond power-down + do_spi_transaction(spi, 0, 0xb9, 0, 0x0, 0x0); +} + +void +spi_macronix_exit_deep_power_down(const spi_dev_t *spi) +{ + // Winbond release power-down + // Also works as Macronix release deep power-down + do_spi_transaction(spi, 0, 0xab, 0, 0x0, 0x0); +} + +void +spi_micron_make_quad(const spi_dev_t *spi) +{ + // READ ENHANCED VOLATILE CONFIGURATION REGISTER + uint8_t evcr = spi_read(spi, 0x65); + + spi_flash_wait_for_no_wip(spi); + spi_flash_write_enable(spi); + + // WRITE ENHANCED VOLATILE CONFIGURATION REGISTER + do_spi_transaction(spi, 0, 0x61, 1, 0x0, evcr & ~0xd0); +} diff --git a/ATM33xx-5/drivers/spi/spi_flash.h b/ATM33xx-5/drivers/spi/spi_flash.h new file mode 100644 index 0000000..be5e6bd --- /dev/null +++ b/ATM33xx-5/drivers/spi/spi_flash.h @@ -0,0 +1,182 @@ +/** + ******************************************************************************* + * + * @file spi_flash.h + * + * @brief SPI flash driver + * + * Copyright (C) Atmosic 2019-2022 + * + ******************************************************************************* + */ + +#ifndef __SPI_FLASH_H__ +#define __SPI_FLASH_H__ + +/** + * @defgroup SPI_FLASH SPI flash + * @ingroup SPI + * @brief User driver for SPI-connected flash device + * @{ + */ + +#include "spi.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + SPI_FLASH_FREAD = 0x0b, // Read Array (fast) + SPI_FLASH_READ = 0x03, // Read Array (low power) + SPI_FLASH_DREAD = 0x3b, // Read Dual Output + SPI_FLASH_2READ = 0xbb, // Read 2x I/O + SPI_FLASH_QREAD = 0x6b, // Read Quad Output + SPI_FLASH_4READ = 0xeb, // Read 4x I/O + + SPI_FLASH_PE = 0x81, // Page Erase + SPI_FLASH_SE = 0x20, // Sector Erase (4K bytes) + SPI_FLASH_BE32 = 0x52, // Block Erase (32K bytes) + SPI_FLASH_BE64 = 0xd8, // Block Erase (64K bytes) + SPI_FLASH_CE = 0x60, // Chip Erase + SPI_FLASH_CE_ALT = 0xc7, // Chip Erase + SPI_FLASH_PP = 0x02, // Page Program + SPI_FLASH_2PP = 0xa2, // Dual-IN Page Program + SPI_FLASH_QPP = 0x32, // Quad Page Program + SPI_FLASH_PES = 0x75, // Program/Erase Suspend + SPI_FLASH_PES_ALT = 0xb0, // Program/Erase Suspend + SPI_FLASH_PER = 0x7a, // Program/Erase Resume + SPI_FLASH_PER_ALT = 0x30, // Program/Erase Resume + + SPI_FLASH_WREN = 0x06, // Write Enable + SPI_FLASH_WRDI = 0x04, // Write Disable + SPI_FLASH_VWREN = 0x50, // Volatile SR Write Enable + + SPI_FLASH_ERSCUR = 0x44, // Erase Security Registers + SPI_FLASH_PRSCUR = 0x42, // Program Security Registers + SPI_FLASH_RDSCUR = 0x48, // Read Security Registers + + SPI_FLASH_RDSR = 0x05, // Read Status Register + SPI_FLASH_RDSR2 = 0x35, // Read Status Register + SPI_FLASH_ASI = 0x25, // Active Status Interrupt + SPI_FLASH_WRSR = 0x01, // Write Status Register + + SPI_FLASH_RSTEN = 0x66, // Reset Enable + SPI_FLASH_RST = 0x99, // Reset + SPI_FLASH_RDID = 0x9f, // Read Manufacturer/Device ID + SPI_FLASH_REMS = 0x90, // Read Manufacturer ID + SPI_FLASH_DREMS = 0x92, // Dual Read Manufacturer ID + SPI_FLASH_QREMS = 0x94, // Quad Read Manufacturer ID + SPI_FLASH_DP = 0xb9, // Deep Power-down + SPI_FLASH_RDP = 0xab, // Release Deep Power-down + SPI_FLASH_SBL = 0x77, // Set Burst Length + SPI_FLASH_RDSFDP = 0x5a, // Read SFDP + SPI_FLASH_RRE = 0xff, // Release Read Enhanced + SPI_FLASH_RUID = 0x4b, // Read Unique ID +} spi_flash_cmd_t; + +/** + * @brief Read data from SPI-connected flash device. + * @param[in] spi Device structure. + * @param[in] addr 3-byte address of data in flash. + * @return Data read from flash device. + */ +uint8_t spi_flash_read_byte(const spi_dev_t *spi, uint32_t addr); + +/** + * @brief Read data from SPI-connected flash device. + * @param[in] spi Device structure. + * @param[in] addr 3-byte address of data in flash. + * @return Data read from flash device. + */ +uint16_t spi_flash_read_short(const spi_dev_t *spi, uint32_t addr); + +/** + * @brief Read data from SPI-connected flash device. + * @param[in] spi Device structure. + * @param[in] addr 3-byte address of data in flash. + * @return Data read from flash device. + */ +uint32_t spi_flash_read_word(const spi_dev_t *spi, uint32_t addr); + + +/** + * @brief Write data to SPI-connected flash device. + * @param[in] spi Device structure. + * @param[in] addr 3-byte address of data in flash. + * @param[in] data Data to write to flash device. + */ +void spi_flash_write_byte(const spi_dev_t *spi, uint32_t addr, uint8_t data); + +/** + * @brief Write data to SPI-connected flash device. + * @param[in] spi Device structure. + * @param[in] addr 3-byte address of data in flash. + * @param[in] data Data to write to flash device. + */ +void spi_flash_write_short(const spi_dev_t *spi, uint32_t addr, uint16_t data); + +/** + * @brief Write data to SPI-connected flash device. + * @param[in] spi Device structure. + * @param[in] addr 3-byte address of data in flash. + * @param[in] data Data to write to flash device. + */ +void spi_flash_write_word(const spi_dev_t *spi, uint32_t addr, uint32_t data); + + +/** + * @brief Turn on QE in remote flash device. + * @param[in] spi Device structure. + * @return Success: true + * Failure: false + */ +bool spi_macronix_make_quad(const spi_dev_t *spi); + +/** + * @brief Force remote flash device out of performance enhance mode. + * @param[in] spi Device structure. + */ +void spi_macronix_exit_performance_mode(const spi_dev_t *spi); + +/** + * @brief Turn on QE in remote flash device. + * @param[in] spi Device structure. + * @return Success: true + * Failure: false + */ +bool spi_giga_make_quad(const spi_dev_t *spi); + +/** + * @brief Turn on QE in remote flash device. + * @param[in] spi Device structure. + * @return Success: true + * Failure: false + */ +bool spi_winbond_make_quad(const spi_dev_t *spi); + +/** + * @brief Place remote flash device in deep power down mode. + * @param[in] spi Device structure. + */ +void spi_macronix_deep_power_down(const spi_dev_t *spi); + +/** + * @brief Wake up remote flash device from deep power down mode. + * @param[in] spi Device structure. + */ +void spi_macronix_exit_deep_power_down(const spi_dev_t *spi); + +/** + * @brief Enable Quad I/O protocol in remote flash device. + * @param[in] spi Device structure. + */ +void spi_micron_make_quad(const spi_dev_t *spi); + +#ifdef __cplusplus +} +#endif + +/// @} SPI_FLASH + +#endif // __SPI_FLASH_H__ diff --git a/ATM33xx-5/drivers/spi/spi_multi.c b/ATM33xx-5/drivers/spi/spi_multi.c new file mode 100644 index 0000000..63eefaa --- /dev/null +++ b/ATM33xx-5/drivers/spi/spi_multi.c @@ -0,0 +1,122 @@ +/** + ******************************************************************************* + * + * @file spi_multi.c + * + * @brief SPI multi transaction driver + * + * Copyright (C) Atmosic 2022 + * + ******************************************************************************* + */ + +#include "arch.h" +#include "spi_multi.h" +#include "atm_utils_math.h" + +void spi_multi_transaction(spi_dev_t const *spi, uint32_t tx_size, + uint8_t const *tx_buffer, uint32_t rx_size, uint8_t *rx_buffer, + uint8_t flags) +{ + // Assert both size are buffer are zero or both are non-zero + ASSERT_INFO(!((!!tx_size) ^ (!!tx_buffer)), tx_size, tx_buffer); + ASSERT_INFO(!((!!rx_size) ^ (!!rx_buffer)), rx_size, rx_buffer); + // Assert if both tx and rx zero + ASSERT_INFO(!((tx_size == 0) && (rx_size == 0)), tx_size, rx_size); + + bool csn_stays_low = true; + bool tx_csn_stays_low = true; + bool rx_csn_stays_low = true; + int8_t tx_num_data_bytes = -1; + int8_t rx_num_data_bytes = -1; + uint32_t tx_current_data_byte = 0; + uint32_t rx_current_data_byte = 0; + uint8_t tx_opcode = 0; + bool write_flag = false; + uint32_t lower = 0; + uint32_t upper = 0; + while ((tx_size) || (rx_size)) { + if (tx_size > 8) { + tx_num_data_bytes = 8; + // Upto 9 bytes of data can be transmitted in one transaction + tx_size = tx_size - 9; + } else if (tx_size > 0) { + tx_num_data_bytes = tx_size - 1; + tx_size = 0; + if (flags & SPI_MULTI_FLAG_CS_DISABLE) { + tx_csn_stays_low = false; + } + } else { + tx_num_data_bytes = -1; + tx_csn_stays_low = false; + } + if (rx_size > 8) { + rx_num_data_bytes = 8; + // Upto 9 bytes of data can be received in one transaction + rx_size = rx_size - 9; + } else if (rx_size > 0) { + rx_num_data_bytes = rx_size - 1; + rx_size = 0; + if (flags & SPI_MULTI_FLAG_CS_DISABLE) { + rx_csn_stays_low = false; + } + } else { + rx_num_data_bytes = -1; + rx_csn_stays_low = false; + } + csn_stays_low = tx_csn_stays_low | rx_csn_stays_low; + for (uint8_t local_count = 0; local_count <= tx_num_data_bytes; + local_count++) { + if (!local_count) { + tx_opcode = tx_buffer[tx_current_data_byte++]; + write_flag = true; + } else if (local_count <= 4) { + lower |= (tx_buffer[tx_current_data_byte++] + << ((local_count - 1) * 8)); + } else { + upper |= (tx_buffer[tx_current_data_byte++] + << ((local_count - 5) * 8)); + } + } + uint32_t transaction = + SPI_TRANSACTION_SETUP__DUMMY_CYCLES__WRITE(spi->dummy_cycles) | + SPI_TRANSACTION_SETUP__CSN_STAYS_LOW__WRITE(csn_stays_low); + if (write_flag) { + transaction |= SPI_TRANSACTION_SETUP__OPCODE__WRITE(tx_opcode); + tx_opcode = 0; + write_flag = false; + } + transaction |= + SPI_TRANSACTION_SETUP__CLKDIV__WRITE(spi->clkdiv) | + SPI_TRANSACTION_SETUP__RWB__MASK | + SPI_TRANSACTION_SETUP__NUM_DATA_BYTES__WRITE( + ATM_MAX(tx_num_data_bytes, rx_num_data_bytes)); + spi->base->DATA_BYTES_LOWER = lower; + spi->base->DATA_BYTES_UPPER = upper; + lower = 0; + upper = 0; + spi->base->TRANSACTION_SETUP = transaction; + spi->base->TRANSACTION_SETUP |= SPI_TRANSACTION_SETUP__START__MASK; + // Wait for transaction to complete + while (spi->base->TRANSACTION_STATUS & + SPI_TRANSACTION_STATUS__RUNNING__MASK) { + YIELD(); + } + for (uint8_t local_count = 0; local_count <= rx_num_data_bytes; + local_count++) { + if (!local_count) { + rx_buffer[rx_current_data_byte] = + ((spi->base->TRANSACTION_STATUS) >> 8) & 0xFF; + } else if (local_count <= 4) { + rx_buffer[rx_current_data_byte] = + (spi->base->DATA_BYTES_LOWER >> (8 * (local_count - 1))) & + 0xFF; + } else { + rx_buffer[rx_current_data_byte] = + (spi->base->DATA_BYTES_UPPER >> (8 * (local_count - 5))) & + 0xFF; + } + rx_current_data_byte++; + } + } +} diff --git a/ATM33xx-5/drivers/spi/spi_multi.h b/ATM33xx-5/drivers/spi/spi_multi.h new file mode 100644 index 0000000..9cae58e --- /dev/null +++ b/ATM33xx-5/drivers/spi/spi_multi.h @@ -0,0 +1,49 @@ +/** + ******************************************************************************* + * + * @file spi_multi.h + * + * @brief SPI multiple transaction driver + * + * Copyright (C) Atmosic 2022 + * + ******************************************************************************* + */ + +#pragma once + +/** + * @defgroup SPI_MULTI SPI multiple read / write transaction + * @ingroup DRIVERS + * @brief User driver for SPI-connected devices + * @{ + */ + +#include "spi.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define SPI_MULTI_FLAG_CS_ENABLE (1 << 0) +#define SPI_MULTI_FLAG_CS_DISABLE (1 << 1) + +/** + * @brief Multi Byte transaction + * + * @param[in] spi Device structure. + * @param[in] tx_size tx buffer size in bytes + * @param[in] tx_buffer Data to write to SPI slave device. + * @param[in] rx_size rx buffer size in bytes + * @param[out] rx_buffer Data to be read from SPI slave device. + * @param[in] flags Flags specifying SPI operations. + */ +void spi_multi_transaction(spi_dev_t const *spi, uint32_t tx_size, + uint8_t const *tx_buffer, uint32_t rx_size, uint8_t *rx_buffer, + uint8_t flags); + +#ifdef __cplusplus +} +#endif + +/// @} diff --git a/ATM33xx-5/drivers/timer/timer.h b/ATM33xx-5/drivers/timer/timer.h new file mode 100644 index 0000000..27eb34b --- /dev/null +++ b/ATM33xx-5/drivers/timer/timer.h @@ -0,0 +1,305 @@ +/** + ****************************************************************************** + * + * @file timer.h + * + * @brief Atmosic Timer Driver + * + * Copyright (C) Atmosic 2019-2024 + * + ****************************************************************************** + */ + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#include "at_wrpr.h" + +/** + * @defgroup TIMER HW Timer APIs + * @ingroup DRIVERS + * @brief User driver for application to use HW timers + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/// Number of centisecond per second +#define CS_PER_SEC 100 + +/// Number of millisecond per second +#define MS_PER_SEC 1000 + +/// Number of millisecond per centisecond +#define MS_PER_CS 10 + +/// Number of microsecond per millisecond +#define US_PER_MS 1000 + +/// Number of second per minute +#ifndef SEC_PER_MIN +#define SEC_PER_MIN 60 +#endif + +/// Number of minute per hour +#ifndef MIN_PER_HOUR +#define MIN_PER_HOUR 60 +#endif + +/// Number of centisecond per minute +#define CS_PER_MINUTE (CS_PER_SEC * SEC_PER_MIN) + +typedef enum { + ATM_TIMER0 = 0, + ATM_TIMER1 = 1, + ATM_DUALTIMER1 = 2, + ATM_DUALTIMER2 = 3, + ATM_SYSTICK = 4, + ATM_SLWTIMER = 5, // Runs off 32Khz clock + ATM_TIMERS_MAX = 6 +} atm_timer_id_t; + +typedef enum { + ATM_TIMER_MODE_SINGLE_SHOT = 0, + ATM_TIMER_MODE_PERIODIC = 1, + ATM_TIMER_MODE_MAX = 2 +} atm_timer_mode_t; + +typedef enum { + ATM_TIMER_SUCCESS = 0, + ATM_TIMER_INVALID_PARAM = 1, + ATM_TIMER_RESOURCE_BUSY = 2, + ATM_TIMER_GENERIC_ERROR = 3 +} atm_timer_error_t; + +typedef void (*atm_timer_callback_t) (void *app_context); + +/** + * @brief Setup timer. + * @param[in] id Timer ID + * @param[in] mode SingleShot vs Periodic + * @param[in] timeout_handler Application layer callback handler + * (called from interrupt context) + * @return Success or Error status + */ +atm_timer_error_t atm_timer_setup(atm_timer_id_t id, atm_timer_mode_t mode, + atm_timer_callback_t timeout_handler); + +/** + * @brief Start timer. + * @param[in] id Timer ID + * @param[in] timeout_us Timer value in micro seconds + * @param[in] app_context Application specific context + * @return Success or Error status + */ +atm_timer_error_t atm_timer_start(atm_timer_id_t id, uint32_t timeout_us, + void *app_context); + +/** + * @brief Start dual timer with more accurate unit.(Only for single shot mode) + * @param[in] id Dual timer ID + * @param[in] timeout_cycles Timer value in cycles + */ +void atm_dual_timer_single_shot_quick_start(atm_timer_id_t id, + uint32_t timeout_cycles); + +/** + * @brief Stop timer. + * @param[in] id Timer ID + * @return Success or Error status + */ +atm_timer_error_t atm_timer_stop(atm_timer_id_t id); + +/** + * @brief Busy wait using CMSDK_PSEQ->CURRENT_REAL_TIME. + * @param[in] msec Delay value in milliseconds + * @return Success or Error status + */ +atm_timer_error_t atm_timer_mdelay(uint32_t msec); + +/** + * @brief Busy wait using the Cortex-M0 SysTick. + * @param[in] usec Delay value in microseconds + * @return Success or Error status + */ +atm_timer_error_t atm_timer_udelay(uint32_t usec); + +/** + * @brief Sleep in WFI using a timer. + * @param[in] id Timer ID + * @param[in] usec Timer value in microseconds + * @return Success or Error status + */ +atm_timer_error_t atm_timer_usleep(atm_timer_id_t id, uint32_t usec); + +// Permit customization for restrictive calling contexts +// or to analyze rt{,1,2,3} locals +#ifndef TIMER_ASSERT_ERR +#define TIMER_ASSERT_ERR ASSERT_ERR +#endif + +/** + * @brief Get the current system time based on the 32kHz clock + */ +__INLINE uint32_t atm_get_sys_time(void) +{ + // The high clock domain latch low clock domain signal directly + // would probably get bad value due to metastability. Considering + // the combinations, it could have 3 conditions: + // 1. bad -> good -> good + // 2. good -> good + // 3. good -> bad -> good -> good + + uint32_t rt; + WRPR_CTRL_PUSH(CMSDK_PSEQ, WRPR_CTRL__CLK_ENABLE) { + GLOBAL_INT_DISABLE(); + uint32_t rt1 = CMSDK_PSEQ->CURRENT_REAL_TIME; + rt = CMSDK_PSEQ->CURRENT_REAL_TIME; + if (rt != rt1) { + uint32_t rt3 = CMSDK_PSEQ->CURRENT_REAL_TIME; + if (rt != rt3) { + __UNUSED uint32_t rt2 = rt; + rt = CMSDK_PSEQ->CURRENT_REAL_TIME; + TIMER_ASSERT_ERR(rt == rt3); + } + } + GLOBAL_INT_RESTORE(); + } WRPR_CTRL_POP(); + return rt; +} + +/** + * @brief Fetch LP clock frequency + * + * @return Value in Hz + */ +__attribute__((weak)) uint32_t lpc_rcos_hz(void); + +/** + * @brief Busy wait using CMSDK_PSEQ->CURRENT_REAL_TIME. + * @param[in] ticks Delay value in counts of CMSDK_PSEQ->CURRENT_REAL_TIME. + * @return Success or Error status + */ +__INLINE void atm_timer_lpc_delay(uint32_t ticks) +{ + uint32_t then = atm_get_sys_time(); + while (atm_get_sys_time() - then < ticks) { + YIELD(); + } +} + +/** + * @brief Translate duration to LPC cycles + * @param[in] freq In Hertz + * @param[in] cnt Number of cycles at freq + * @return LPC cycles + */ +static inline uint64_t atm_to_lpc(uint32_t freq, uint64_t cnt) +{ + if (lpc_rcos_hz) { + return (cnt * lpc_rcos_hz()) / freq; + } else { + return (cnt * 32768) / freq; + } +} + +/** + * @brief Translate duration to LPC cycles while rounding to nearest integer + * @param[in] freq In Hertz + * @param[in] cnt Number of cycles at freq + * @return LPC cycles + */ +static inline uint64_t atm_to_lpc_round(uint32_t freq, uint64_t cnt) +{ + if (lpc_rcos_hz) { + return ((cnt * lpc_rcos_hz()) + (freq / 2)) / freq; + } else { + return ((cnt * 32768) + (freq / 2)) / freq; + } +} + +/** + * @brief Translate centiseconds to LPC cycles + * @param[in] cs Number of centiseconds + * @return LPC cycles + */ +static inline uint32_t atm_cs_to_lpc(uint32_t cs) +{ + return atm_to_lpc(CS_PER_SEC, cs); +} + +/** + * @brief Translate milliseconds to LPC cycles + * @param[in] ms Number of milliseconds + * @return LPC cycles + */ +static inline uint32_t atm_ms_to_lpc(uint32_t ms) +{ + return atm_to_lpc(MS_PER_SEC, ms); +} + +/** + * @brief Translate microseconds to LPC cycles + * @param[in] us Number of microseconds + * @return LPC cycles + */ +static inline uint32_t atm_us_to_lpc(uint64_t us) +{ + return atm_to_lpc(US_PER_MS * MS_PER_SEC, us); +} + +/** + * @brief Translate LPC cycles to duration + * @param[in] freq In Hertz + * @param[in] lpc Number of LPC cycles + * @return Number of cycles at freq + */ +static inline uint64_t atm_lpc_to(uint32_t freq, uint64_t lpc) +{ + if (lpc_rcos_hz) { + return (lpc * freq) / lpc_rcos_hz(); + } else { + return (lpc * freq) / 32768; + } +} + +/** + * @brief Translate LPC cycles to centiseconds + * @param[in] lpc Number of LPC cycles + * @return Number of centiseconds + */ +static inline uint32_t atm_lpc_to_cs(uint32_t lpc) +{ + return atm_lpc_to(CS_PER_SEC, lpc); +} + +/** + * @brief Translate LPC cycles to milliseconds + * @param[in] lpc Number of LPC cycles + * @return Number of milliseconds + */ +static inline uint32_t atm_lpc_to_ms(uint32_t lpc) +{ + return atm_lpc_to(MS_PER_SEC, lpc); +} + +/** + * @brief Translate LPC cycles to microseconds + * @param[in] lpc Number of LPC cycles + * @return Number of microseconds + */ +static inline uint64_t atm_lpc_to_us(uint32_t lpc) +{ + return atm_lpc_to(US_PER_MS * MS_PER_SEC, lpc); +} + + +#ifdef __cplusplus +} +#endif + +/// @} TIMER + +#endif // __TIMER_H__ diff --git a/ATM33xx-5/drivers/trng/trng_internal.h b/ATM33xx-5/drivers/trng/trng_internal.h new file mode 100644 index 0000000..8bf3d95 --- /dev/null +++ b/ATM33xx-5/drivers/trng/trng_internal.h @@ -0,0 +1,199 @@ +/** + ******************************************************************************* + * + * @file trng_internal.h + * + * @brief True Random Number Generator driver internal components + * + * Copyright (C) Atmosic 2018-2024 + * + ******************************************************************************* + */ + +#pragma once + +#ifndef TRNG_INTERNAL_DIRECT_INCLUDE_GUARD +#error "trng_internal.h should only be included in trng source files" +#endif + +/** + * @defgroup TRNG_INTERNAL TRNG_INTERNAL + * @ingroup DRIVERS + * @brief Internal components for TRNG drivers + * @{ + */ + +#include "arch.h" +#include "timer.h" + +#include "at_wrpr.h" +#include "rif_regs_core_macro.h" +#include "at_apb_trng_regs_core_macro.h" +#include "mdm_macro.h" +#include "at_clkrstgen.h" +#include "spi.h" +#include "radio_spi.h" +#include "at_apb_pseq_regs_core_macro.h" + +#ifndef WRPR_CTRL__CLK_SEL +#define WRPR_CTRL__CLK_SEL 0 +#endif + +static bool is_fpga; +static bool sidet; + +/** + * @brief initializes the trng module. + */ +__INLINE void trng_internal_constructor(void) +{ +#ifdef PSEQ_PMU_STATUS__SI_DET__READ + WRPR_CTRL_SET(CMSDK_PSEQ, WRPR_CTRL__CLK_ENABLE); + { + sidet = PSEQ_PMU_STATUS__SI_DET__READ(CMSDK_PSEQ->PMU_STATUS); + } + WRPR_CTRL_SET(CMSDK_PSEQ, WRPR_CTRL__CLK_DISABLE); +#endif + +#ifdef __CLKRSTGEN_CONFIGURATION_MACRO__ + is_fpga = CLKRSTGEN_CONFIGURATION__INDEX__READ( + CMSDK_CLKRSTGEN_NONSECURE->CONFIGURATION); +#endif + + WRPR_CTRL_SET(CMSDK_TRNG, WRPR_CTRL__SRESET); +} + +/** + * @brief Initiate DC calibration + * + * @return true if DC cal can be skipped + */ +#ifdef __MDM_DCCAL_CTRL_MACRO__ +__INLINE bool trng_internal_dccal_init(void) +{ + if (is_fpga) { + // Skip DC offset calibration on FPGA + return true; + } + WRPR_CTRL_SET(CMSDK_MDM, WRPR_CTRL__CLK_ENABLE); + if (MDM_TIA_RETENT_DCCALRESULTS__DONE__READ( + CMSDK_MDM->TIA_RETENT_DCCALRESULTS)) { + // No need to repeat dccal + WRPR_CTRL_SET(CMSDK_MDM, WRPR_CTRL__CLK_DISABLE); + return true; + } + + WRPR_CTRL_SET(CMSDK_RIF, WRPR_CTRL__CLK_ENABLE); + uint32_t mode_cntl = CMSDK_RIF->MODE_CNTL; + RIF_MODE_CNTL__RX_EN__SET(mode_cntl); + RIF_MODE_CNTL__RX_EN_OVR__SET(mode_cntl); + RIF_MODE_CNTL__RXGAIN_OVR__SET(mode_cntl); + CMSDK_RIF->MODE_CNTL = mode_cntl; + RIF_RX0__LNA_PROTECT_OVR__MODIFY(CMSDK_RIF->RX0, 3); + atm_timer_lpc_delay(3); + + MDM_DCCAL_CTRL__START__CLR(CMSDK_MDM->DCCAL_CTRL); + MDM_DCCAL_CTRL__START__SET(CMSDK_MDM->DCCAL_CTRL); + return false; +} + +/** + * @brief complete dc calibration + */ +__INLINE void trng_internal_dccal_complete(void) +{ + MDM_DCCAL_CTRL__START__CLR(CMSDK_MDM->DCCAL_CTRL); + WRPR_CTRL_SET(CMSDK_MDM, WRPR_CTRL__CLK_DISABLE); + + uint32_t mode_cntl = CMSDK_RIF->MODE_CNTL; + RIF_MODE_CNTL__RX_EN__CLR(mode_cntl); + RIF_MODE_CNTL__RX_EN_OVR__CLR(mode_cntl); + RIF_MODE_CNTL__RXGAIN_OVR__CLR(mode_cntl); + RIF_MODE_CNTL__RXGAIN__MODIFY(mode_cntl, + 45 + RIF_LNA__STEP1__READ(CMSDK_RIF->LNA)); + CMSDK_RIF->MODE_CNTL = mode_cntl; + RIF_RX0__LNA_PROTECT_OVR__MODIFY(CMSDK_RIF->RX0, 0); + WRPR_CTRL_SET(CMSDK_RIF, WRPR_CTRL__CLK_DISABLE); +} +#endif // __MDM_DCCAL_CTRL_MACRO__ + +#ifdef __RIF_TRNG_CONF_MACRO__ +/** + * @brief Check whether TRNG needs to be triggered + */ +__INLINE bool trng_internal_go_pulse_needed(void) +{ + return (TRNG_CONTROL__LAUNCH_ON_RADIO_UP__READ(CMSDK_TRNG->CONTROL) && + !CMSDK_TRNG->STATUS && + ATLC_LC_LP_ST5__RADIO_EN__READ(CMSDK_ATLC_NONSECURE->LC_LP_ST5)); +} +#endif + +/** + * @brief Set radio warmup cnt based on whether radio is already on + */ +__INLINE void trng_internal_set_radio_warmup_cnt(bool radio_already_on) +{ + if (radio_already_on) { +#define TRNG_RADIO_SETTLING_TIME 800 + TRNG_CONTROL__RADIO_WARMUP_CNT__MODIFY(CMSDK_TRNG->CONTROL, + TRNG_RADIO_SETTLING_TIME); + } else { +#ifdef __RIF_TRNG_CONF_MACRO__ + // use lower radio warmup time for FPGA + CMSDK_TRNG->CONTROL = TRNG_CONTROL__RADIO_WARMUP_CNT__WRITE( + is_fpga ? 0x400 : TRNG_CONTROL__RADIO_WARMUP_CNT__RESET_VALUE); +#else + // use default radio warmup time for FPGA + CMSDK_TRNG->CONTROL = TRNG_CONTROL__RADIO_WARMUP_CNT__WRITE( + is_fpga ? TRNG_CONTROL__RADIO_WARMUP_CNT__RESET_VALUE : 0x7ff); +#endif + } +} + +/** + * @brief (re)configure trng module + */ +__INLINE void trng_internal_config(void) +{ + WRPR_CTRL_SET(CMSDK_TRNG, WRPR_CTRL__CLK_SEL | WRPR_CTRL__CLK_ENABLE); + + trng_internal_set_radio_warmup_cnt(false); + + // Enable interrupt + CMSDK_TRNG->INTERRUPT_MASK = TRNG_INTERRUPT_STATUS__TRNG_TROUBLE__MASK | + TRNG_INTERRUPT_STATUS__TRNG_READY__MASK; +} + +/** + * @brief Collect a new random word immediately + */ +__INLINE void trng_internal_force_go_pulse(void) +{ + TRNG_CONTROL__GO__CLR(CMSDK_TRNG->CONTROL); + TRNG_CONTROL__GO__SET(CMSDK_TRNG->CONTROL); + + if (sidet) { + return; + } + + // Set synthesizer override + WRPR_CTRL_PUSH(CMSDK_RADIO, WRPR_CTRL__CLK_ENABLE) { + RADIO_TOP_WRITE(MODE_REG_ADDR, 0x3); + } WRPR_CTRL_POP(); +} + +/** + * @brief Clear synthesizer override set in trng_internal_force_go_pulse + */ +__INLINE void trng_internal_clear_synth_override(void) +{ + if (!sidet) { + // Clear synthesizer override + WRPR_CTRL_PUSH(CMSDK_RADIO, WRPR_CTRL__CLK_ENABLE) { + RADIO_TOP_WRITE(MODE_REG_ADDR, 0x0); + } WRPR_CTRL_POP(); + } +} + +/// @} TRNG_INTERNAL diff --git a/ATM33xx-5/drivers/user_debug.c b/ATM33xx-5/drivers/user_debug.c new file mode 100644 index 0000000..9c8c84a --- /dev/null +++ b/ATM33xx-5/drivers/user_debug.c @@ -0,0 +1,174 @@ +/** + ******************************************************************************* + * + * @file user_debug.c + * + * @brief Print-based debug interface + * + * Copyright (C) Atmosic 2021-2023 + * + ******************************************************************************* + */ + +#ifdef CONFIG_SOC_FAMILY_ATM +#include +#include +#define PRINTF printk +#else +#define PRINTF printf +#endif + +#include "arch.h" +#include +#if defined(CFG_BLE_EMB) || defined(CFG_BLE_HOST) +#include "dbg.h" +#endif +#include "at_wrpr.h" + +#if PLF_DEBUG +/// Variable to enable infinite loop on assert +volatile int dbg_assert_block = 1; + +void assert_err(const char *condition, const char * file, int line) +{ + PRINTF("ASSERT ERR(%s) at %s:%d\n", condition, file, line); +#ifdef TRC_REQ_SW_ASS_ERR + TRC_REQ_SW_ASS_ERR(file, line, 0, 0); +#endif + +#if RW_DEBUG + // Trigger assert message + rwip_assert(file, line, 0, 0, ASSERT_TYPE_ERROR); + // Let time for the message transfer + for (int i = 0; i<2000;i++) { + dbg_assert_block = 1; + } +#endif + +#ifdef FIXME + asrt_line_set(line); + asrt_addr_setf((uint32_t)file); + asrt_trigg_setf(1); +#endif + + GLOBAL_INT_STOP(); + __BKPT(0); + while (dbg_assert_block); +} + +void assert_param(int param0, int param1, const char * file, int line) +{ + PRINTF("ASSERT PARAM(%#x, %#x) at %s:%d\n", (unsigned int)param0, + (unsigned int)param1, file, line); +#ifdef TRC_REQ_SW_ASS_ERR + TRC_REQ_SW_ASS_ERR(file, line, param0, param1); +#endif + +#if RW_DEBUG + // Trigger assert message + rwip_assert(file, line, param0, param1, ASSERT_TYPE_ERROR); + // Let time for the message transfer + for (int i = 0; i<2000;i++) { + dbg_assert_block = 1; + } +#endif + +#ifdef FIXME + asrt_line_set(line); + asrt_addr_setf((uint32_t)file); + asrt_params_setf(1); + asrt_param_1_setf(param0); + asrt_param_2_setf(param1); + asrt_params_setf(1); + asrt_trigg_setf(1); +#endif + + GLOBAL_INT_STOP(); + __BKPT(1); + while (dbg_assert_block); +} + +void assert_warn(int param0, int param1, const char * file, int line) +{ + PRINTF("ASSERT WARN(%#x, %#x) at %s:%d\n", (unsigned int)param0, + (unsigned int)param1, file, line); +#ifdef TRC_REQ_SW_ASS_WARN + TRC_REQ_SW_ASS_WARN(file, line, param0, param1); +#endif + +#if RW_DEBUG + // Trigger assert message + rwip_assert(file, line, param0, param1, ASSERT_TYPE_WARNING); +#endif + +#ifdef FIXME + asrt_line_set(line); + asrt_addr_setf((uint32_t)file); + asrt_params_setf(0); + asrt_warn_setf(1); +#endif +} + +int +debug_trace(const char *fmt, ...) +{ + uint32_t rt; + WRPR_CTRL_PUSH(CMSDK_PSEQ, WRPR_CTRL__CLK_ENABLE) { + rt = CMSDK_PSEQ->CURRENT_REAL_TIME; + } WRPR_CTRL_POP(); + + PRINTF("@%08" PRIx32 " ", rt); + + va_list ap; + va_start(ap, fmt); +#ifdef CONFIG_SOC_FAMILY_ATM + int ret = 0; + vprintk(fmt, ap); +#else + int ret = vprintf(fmt, ap); +#endif + va_end(ap); + +#ifdef CONFIG_SOC_FAMILY_ATM + printk("\n"); +#else + putchar('\n'); +#endif + + return (ret); +} + +void dump_hci(uint8_t type, uint8_t direction, uint8_t* p_data, uint16_t length, uint8_t* p_hdr_data, uint16_t hdr_length) +{ +#ifdef FIXME + asrt_dump_ext_cfg_set(hdr_length); + asrt_dump_ext_data_addr_setf((uint32_t)p_hdr_data); + asrt_dump_data_addr_setf((uint32_t)p_data); + asrt_dump_cfg_pack(/*log*/ 0, + /*hci*/ 1, + /*ext*/ ((hdr_length > 0) ? 1 : 0), + /*packed*/ 1, + /*level*/ 0, + /*dir*/ ((direction == 1) ? 1 : 0), + /*type*/ type, + /*length*/ length); +#endif +} + +void dump_upk_hci(uint8_t evttype, uint8_t direction, uint16_t code, uint8_t* p_data, uint16_t length) +{ +#ifdef FIXME + asrt_dump_ext_cfg_set(code); + asrt_dump_data_addr_setf((uint32_t)p_data); + asrt_dump_cfg_pack(/*log*/ 0, + /*hci*/ 1, + /*ext*/ 0, + /*packed*/ 0, + /*level*/ 0, + /*dir*/ ((direction == 1) ? 1 : 0), + /*type*/ evttype, + /*length*/ length); + +#endif +} +#endif //PLF_DEBUG diff --git a/ATM33xx-5/drivers/workarounds/workarounds.c b/ATM33xx-5/drivers/workarounds/workarounds.c new file mode 100644 index 0000000..90e39e5 --- /dev/null +++ b/ATM33xx-5/drivers/workarounds/workarounds.c @@ -0,0 +1,292 @@ +/** + ******************************************************************************* + * + * @file workarounds.c + * + * @brief SoC initialization workarounds + * + * Copyright (C) Atmosic 2018-2024 + * + ******************************************************************************* + */ + +#include "arch.h" +#include "at_wrpr.h" + +#ifdef APB0_NONSECURE_BASE +#define USE_SEC_JRNL +#endif + +#if ((defined(PLF_NVDS) && PLF_NVDS) || defined(USE_SEC_JRNL)) +#include +#include + +#include "workarounds.h" +#include "calibration.h" +#include "spi.h" + +#ifdef USE_SEC_JRNL +#include "sec_jrnl.h" +#else +#include "nvds.h" +#endif + +struct wa_wrpr_state { + uint16_t touched; + uint32_t *ctrl_save; +}; + +struct wa_module_state { + struct wa_wrpr_state apb0; + struct wa_wrpr_state apb1; +#ifdef APB2_NUM_MODULES + struct wa_wrpr_state apb2; +#endif +}; + +#ifndef APB0_NONSECURE_BASE +#define APB0_NONSECURE_BASE CMSDK_APB_BASE +#endif +#ifndef APB1_NONSECURE_BASE +#define APB1_NONSECURE_BASE CMSDK_APB1_BASE +#endif + +static void +wa_enable_module(struct wa_module_state *mod_state, volatile const void *addr) +{ + uintptr_t address = (uintptr_t)addr; + struct wa_wrpr_state *state; + int i; + + if ((address >= APB0_NONSECURE_BASE) && + (address < APB0_NONSECURE_BASE + (APB_MOD_SIZE * APB0_NUM_MODULES))) { + state = &mod_state->apb0; + i = (address - APB0_NONSECURE_BASE) / APB_MOD_SIZE; + } else if ((address >= APB1_NONSECURE_BASE) && + (address < APB1_NONSECURE_BASE + (APB_MOD_SIZE * APB1_NUM_MODULES))) { + state = &mod_state->apb1; + i = (address - APB1_NONSECURE_BASE) / APB_MOD_SIZE; + } +#ifdef APB2_NUM_MODULES + else if ((address >= APB2_NONSECURE_BASE) && + (address < APB2_NONSECURE_BASE + (APB_MOD_SIZE * APB2_NUM_MODULES))) { + state = &mod_state->apb2; + i = (address - APB2_NONSECURE_BASE) / APB_MOD_SIZE; + } +#endif + else { + return; + } + + uint32_t mask = 0x1 << i; + if (state->touched & mask) { + // Already enabled + return; + } + uint32_t volatile *ctrl_ptr = module_to_ctrl(addr); + if (!ctrl_ptr) { + return; + } + uint32_t ctrl = *ctrl_ptr; + if (ctrl == WRPR_CTRL__CLK_ENABLE) { + // Already enabled + return; + } + + // Leave out of reset when restoring + state->ctrl_save[i] = ctrl & ~WRPR_CTRL__SRESET; + state->touched |= mask; + + // Make sure module has clock and is out of reset + *ctrl_ptr = WRPR_CTRL__CLK_ENABLE; +} + +#ifndef CMSDK_WRPR +#define CMSDK_WRPR CMSDK_WRPR0_NONSECURE +#endif +#ifndef CMSDK_WRPR1 +#define CMSDK_WRPR1 CMSDK_WRPR1_NONSECURE +#endif + +static void +wa_restore_modules(struct wa_module_state *mod_state) +{ + int i; + uint16_t touched; + + for (i=0,touched=mod_state->apb0.touched; i>=1) { + if (touched & 0x1) { + (&CMSDK_WRPR->APB0_CTRL)[i] = mod_state->apb0.ctrl_save[i]; + } + } + + for (i=0,touched=mod_state->apb1.touched; i>=1) { + if (touched & 0x1) { + (&CMSDK_WRPR1->APB0_CTRL)[i] = mod_state->apb1.ctrl_save[i]; + } + } + +#ifdef APB2_NUM_MODULES + for (i=0,touched=mod_state->apb2.touched; i>=1) { + if (touched & 0x1) { + (&CMSDK_WRPR2_NONSECURE->APB0_CTRL)[i] = mod_state->apb2.ctrl_save[i]; + } + } +#endif +} + +struct mem_rmw { + union { + struct { + volatile uint32_t *addr; + uint32_t data; + uint32_t mask; + } __PACKED w; + struct { + volatile uint16_t *addr; + uint16_t data; + uint16_t mask; + } __PACKED s; + struct { + volatile uint8_t *addr; + uint8_t data; + uint8_t mask; + } __PACKED b; + }; +}; + +struct pmu_w { + uint8_t block; + uint8_t addr; + uint32_t data; +} __PACKED; + +static int wa_walk_callback(uint8_t tag, +#ifdef USE_SEC_JRNL + sec_jrnl_tag_len_t len, + sec_jrnl_ret_status_t (*nvds_read)(uint32_t len, uint8_t *buf), +#else + uint32_t addr, nvds_tag_len_t len, + void (*nvds_read)(uint32_t addr, uint32_t len, uint8_t *buf), +#endif + void *ctx) +{ + struct wa_module_state *mod_state = ctx; + + switch (tag) { + case ATM_TAG_PMU_W: { + struct pmu_w pmu_op; +#ifdef USE_SEC_JRNL + sec_jrnl_ret_status_t ret = nvds_read(len, (uint8_t *)&pmu_op); + if (ret != SEC_JRNL_OK) { + DEBUG_TRACE("Invalid nvds_read parameters"); + break; + } +#else + nvds_read(addr, len, (uint8_t*)&pmu_op); +#endif + DEBUG_TRACE("Writing %#" PRIx32 " to PMU block %#x, addr %#x", + pmu_op.data, pmu_op.block, pmu_op.addr); + wa_enable_module(mod_state, spi_pmu.base); + spi_pmuradio_write_word(&spi_pmu, pmu_op.block, pmu_op.addr, + pmu_op.data); +#if (PLF_DEBUG) + uint32_t read_back = spi_pmuradio_read_word(&spi_pmu, pmu_op.block, + pmu_op.addr); + ASSERT_INFO(pmu_op.data == read_back, pmu_op.data, read_back); +#endif + break; + } + case ATM_TAG_MEM_W: { + struct mem_rmw rmw_op; +#ifdef USE_SEC_JRNL + sec_jrnl_ret_status_t ret = nvds_read(len, (uint8_t *)&rmw_op); + if (ret != SEC_JRNL_OK) { + DEBUG_TRACE("Invalid nvds_read parameters"); + break; + } +#else + nvds_read(addr, len, (uint8_t*)&rmw_op); +#endif + if (len == __OFFSET(rmw_op.w, mask)) { + wa_enable_module(mod_state, rmw_op.w.addr); + *rmw_op.w.addr = rmw_op.w.data; + } else if (len == __OFFSET(rmw_op.s, mask)) { + wa_enable_module(mod_state, rmw_op.s.addr); + *rmw_op.s.addr = rmw_op.s.data; + } else if (len == __OFFSET(rmw_op.b, mask)) { + wa_enable_module(mod_state, rmw_op.b.addr); + *rmw_op.b.addr = rmw_op.b.data; + } + break; + } + case ATM_TAG_MEM_RMW: { + struct mem_rmw rmw_op; +#ifdef USE_SEC_JRNL + sec_jrnl_ret_status_t ret = nvds_read(len, (uint8_t *)&rmw_op); + if (ret != SEC_JRNL_OK) { + DEBUG_TRACE("Invalid nvds_read parameters"); + break; + } +#else + nvds_read(addr, len, (uint8_t*)&rmw_op); +#endif + if (len == sizeof(rmw_op.w)) { + wa_enable_module(mod_state, rmw_op.w.addr); + *rmw_op.w.addr = (*rmw_op.w.addr & ~rmw_op.w.mask) | + (rmw_op.w.data & rmw_op.w.mask); + } else if (len == sizeof(rmw_op.s)) { + wa_enable_module(mod_state, rmw_op.s.addr); + *rmw_op.s.addr = (*rmw_op.s.addr & ~rmw_op.s.mask) | + (rmw_op.s.data & rmw_op.s.mask); + } else if (len == sizeof(rmw_op.b)) { + wa_enable_module(mod_state, rmw_op.b.addr); + *rmw_op.b.addr = (*rmw_op.b.addr & ~rmw_op.b.mask) | + (rmw_op.b.data & rmw_op.b.mask); + } + break; + } + default: + break; + } + return 0; +} + +void +workarounds_init(void) +{ + uint32_t apb0_ctrl_save[APB0_NUM_MODULES]; + uint32_t apb1_ctrl_save[APB1_NUM_MODULES]; +#ifdef APB2_NUM_MODULES + uint32_t apb2_ctrl_save[APB2_NUM_MODULES]; +#endif + struct wa_module_state mod_state = { + { 0, apb0_ctrl_save }, + { 0, apb1_ctrl_save }, +#ifdef APB2_NUM_MODULES + { 0, apb2_ctrl_save }, +#endif + }; + +#ifdef USE_SEC_JRNL + nsc_sec_jrnl_walk_init_ctx(); + uint8_t tag = SEC_JRNL_INVALID_TAG; + sec_jrnl_tag_len_t len = 0; + for (;;) { + sec_jrnl_ret_status_t ret = nsc_sec_jrnl_walk_tag(&tag, &len); + if (ret != SEC_JRNL_OK) { + break; + } + wa_walk_callback(tag, len, nsc_sec_jrnl_walk_read_curr_tag, &mod_state); + } +#else + nvds_walk(wa_walk_callback, &mod_state); +#endif + + wa_restore_modules(&mod_state); +} + +#endif // ((PLF_NVDS) || defined(USE_SEC_JRNL) diff --git a/ATM33xx-5/drivers/workarounds/workarounds.h b/ATM33xx-5/drivers/workarounds/workarounds.h new file mode 100644 index 0000000..e6ff9ba --- /dev/null +++ b/ATM33xx-5/drivers/workarounds/workarounds.h @@ -0,0 +1,41 @@ +/***************************************************************************************** +* +* @file workarounds.h +* +* @brief ROM initialization workarounds +* +* Copyright (C) Atmosic 2018-2019 +* +* +*****************************************************************************************/ + +#ifndef __WORKAROUNDS_H__ +#define __WORKAROUNDS_H__ + +/** + * @defgroup WORKAROUNDS WORKAROUNDS + * @ingroup DRIVERS + * @brief ROM driver for OTP-based register workarounds + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Apply manufacturing hardware workarounds. + * + * Normally called during late ROM init. + * User applications that never return to the ROM (and third party OSes) + * must call this during initialization. + */ +void workarounds_init(void); + +#ifdef __cplusplus +} +#endif + +/// @} WORKAROUNDS + +#endif // __WORKAROUNDS_H__ diff --git a/ATM33xx-5/examples/spe/CMakeLists.txt b/ATM33xx-5/examples/spe/CMakeLists.txt new file mode 100644 index 0000000..ec962c2 --- /dev/null +++ b/ATM33xx-5/examples/spe/CMakeLists.txt @@ -0,0 +1,20 @@ +# +# Copyright (c) 2022 Atmosic +# +# SPDX-License-Identifier: Apache-2.0 +# + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(bootloader) + +target_sources(app PRIVATE + src/main.c +) + +target_sources_ifdef(CONFIG_ATM_ENABLE_NSC_EXAMPLE app PRIVATE src/cust_sec_func/cust_sec_func.c) + +zephyr_compile_options( + -DSECURE_PROC_ENV=1 +) diff --git a/ATM33xx-5/examples/spe/Kconfig b/ATM33xx-5/examples/spe/Kconfig new file mode 100644 index 0000000..c0f3a91 --- /dev/null +++ b/ATM33xx-5/examples/spe/Kconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Atmosic +# +# SPDX-License-Identifier: Apache-2.0 + +source "Kconfig.zephyr" + +config ATM_SPE_DISABLE_SAU + bool "Disable SAU" + default n + +config ATM_SPE_DISABLE_SHUB + bool "Disable Sensor Hub" + default y diff --git a/ATM33xx-5/examples/spe/prj.conf b/ATM33xx-5/examples/spe/prj.conf new file mode 100644 index 0000000..527de4b --- /dev/null +++ b/ATM33xx-5/examples/spe/prj.conf @@ -0,0 +1,24 @@ +# +# Copyright (c) 2022-2023 Atmosic +# +# SPDX-License-Identifier: Apache-2.0 +# + +# Single-threaded, no timer support in the kernel +CONFIG_MULTITHREADING=n +CONFIG_KERNEL_MEM_POOL=n +# Designate bootloader as a spe +CONFIG_TRUSTED_EXECUTION_SECURE=y +CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS=y + +# Minimize size of bootloader +CONFIG_ASSERT=n +CONFIG_BOOT_BANNER=n +CONFIG_ERRNO=n +CONFIG_PM=n +CONFIG_CBPRINTF_NANO=y + +# Flash driver debug +#CONFIG_LOG=y +#CONFIG_LOG_MODE_IMMEDIATE=y +#CONFIG_FLASH_LOG_LEVEL_INF=y diff --git a/ATM33xx-5/examples/spe/sample.yaml b/ATM33xx-5/examples/spe/sample.yaml new file mode 100644 index 0000000..c965480 --- /dev/null +++ b/ATM33xx-5/examples/spe/sample.yaml @@ -0,0 +1,7 @@ +# Copyright (c) 2022-2024 Atmosic +# +# SPDX-License-Identifier: Apache-2.0 + +sample: + description: ATM33xx SPE + name: Secure Processing Env. sample diff --git a/ATM33xx-5/examples/spe/src/cust_sec_func/cust_sec_func.c b/ATM33xx-5/examples/spe/src/cust_sec_func/cust_sec_func.c new file mode 100644 index 0000000..ad65220 --- /dev/null +++ b/ATM33xx-5/examples/spe/src/cust_sec_func/cust_sec_func.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2024 Atmosic + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "string.h" +#include "atm_utils_c.h" +#include "cust_sec_func.h" +#include "sec_service.h" + +__attribute__((cmse_nonsecure_entry)) __attribute__((used)) bool +nsc_hello_world(uint8_t *buffer, uint32_t *buf_len) +{ + // before checking if we have access to the buffer, need to check access + // to buf_len + if (!mem_check_has_access(buf_len, sizeof(uint32_t), true, true)) { + return false; + } + uint32_t length = *buf_len; + // Verify access to the whole range of the buffer itself + if (!mem_check_has_access(buffer, length, true, true)) { + return false; + } + +#define OUTPUT_STR "Hello from Secure World" + uint32_t total_len = strlen(OUTPUT_STR); + if (length < total_len) { + return false; + } + + memcpy(buffer, OUTPUT_STR, total_len); + *buf_len = total_len; + return true; +} diff --git a/ATM33xx-5/examples/spe/src/cust_sec_func/cust_sec_func.h b/ATM33xx-5/examples/spe/src/cust_sec_func/cust_sec_func.h new file mode 100644 index 0000000..46d9216 --- /dev/null +++ b/ATM33xx-5/examples/spe/src/cust_sec_func/cust_sec_func.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2024 Atmosic + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "stdbool.h" + +/** + * @brief Populates a nonsecure buffer with a string + * + * @note Does *not* append a null terminator ('\0'). Caller can check buf_len + * to check how many characters were populated. + * + * @param[out] buffer buffer to fill + * @param[in,out] buf_len length of buffer, length of populate characters + * @return true if buffer filled successfully, false otherwise + */ +bool nsc_hello_world(uint8_t *buffer, uint32_t *buf_len); \ No newline at end of file diff --git a/ATM33xx-5/examples/spe/src/main.c b/ATM33xx-5/examples/spe/src/main.c new file mode 100644 index 0000000..cd166f1 --- /dev/null +++ b/ATM33xx-5/examples/spe/src/main.c @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2022-2024 Atmosic + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include "arch.h" +#include +#include +#include +#include +#include +#include "vectors.h" +#include +#include "at_tz_sau.h" +#include "at_tz_ppc.h" +#include "at_tz_mpc.h" + +#include "at_wrpr.h" +#include "at_pinmux.h" +#include "rram_rom_prot.h" +#include "sec_dev_lockout.h" + +#ifndef SEC_ASSERT +// FIXME, port sec_assert library +#define SEC_ASSERT(t) \ + do { \ + if (!t) { \ + printk("sec_assert: %s, %d\n", __FUNCTION__, __LINE__); \ + k_fatal_halt(K_ERR_KERNEL_PANIC); \ + } \ + } while (0) +#endif + +extern irq_target_state_t irq_target_state_set(unsigned int irq, + irq_target_state_t target_state); + +#define PART_ADDR(label) ( \ + DT_REG_ADDR(DT_MTD_FROM_FIXED_PARTITION(DT_NODELABEL(label))) + \ + DT_REG_ADDR(DT_NODELABEL(label)) \ +) + +#define PART_OFFSET(label) (DT_REG_ADDR(DT_NODELABEL(label))) + +#ifdef CONFIG_BOOTLOADER_MCUBOOT +// the merged SPE/NSPE slot needs the physical base address of the parent of +// slot0_partition +#define PART_SPE_NSPE_ADDR(label) \ + (DT_REG_ADDR(DT_MTD_FROM_FIXED_PARTITION(DT_NODELABEL(slot0_partition))) + \ + DT_REG_ADDR(DT_NODELABEL(label))) +#else +#define PART_SPE_NSPE_ADDR(label) PART_ADDR(label) +#endif + +static void mpc_cfg(void) +{ + // Configuring MPC of Flash + at_tz_mpc_enable_int(AT_TZ_MPC_DEV_FLASH); + + uint32_t nspe_baddr = PART_SPE_NSPE_ADDR(nspe_partition); + uint32_t nspe_laddr = nspe_baddr + DT_REG_SIZE(DT_NODELABEL(nspe_partition)) - 1; + at_tz_mpc_config_region(nspe_baddr, nspe_laddr, AT_TZ_MPC_ATTR_NONSECURE); + +#ifdef CONFIG_BOOTLOADER_MCUBOOT +#if CONFIG_ROM_START_OFFSET % AT_TZ_MPC_FLS_BLK_SIZE != 0 +#error CONFIG_ROM_START_OFFSET must be aligned to 2k boundary +#endif + // Allow mcumgr to read image header. + uint32_t boot_hdr_baddr = PART_SPE_NSPE_ADDR(spe_partition); + uint32_t boot_hdr_laddr = boot_hdr_baddr + CONFIG_ROM_START_OFFSET - 1; + at_tz_mpc_config_region(boot_hdr_baddr, boot_hdr_laddr, + AT_TZ_MPC_ATTR_NONSECURE); +#endif // CONFIG_BOOTLOADER_MCUBOOT + + // allocate storage partition + uint32_t storage_baddr = PART_ADDR(storage_partition); + uint32_t storage_laddr = storage_baddr + + DT_REG_SIZE(DT_NODELABEL(storage_partition)) - 1; + at_tz_mpc_config_region(storage_baddr, storage_laddr, + AT_TZ_MPC_ATTR_NONSECURE); + +#if DT_NODE_EXISTS(DT_NODELABEL(slot1_partition)) + uint32_t slot1_baddr = PART_ADDR(slot1_partition); + uint32_t slot1_laddr = slot1_baddr + + DT_REG_SIZE(DT_NODELABEL(slot1_partition)) - 1; + at_tz_mpc_config_region(slot1_baddr, slot1_laddr, AT_TZ_MPC_ATTR_NONSECURE); +#endif + +#if DT_NODE_EXISTS(DT_NODELABEL(slot2_partition)) + uint32_t slot2_baddr = PART_ADDR(slot2_partition); + uint32_t slot2_laddr = slot2_baddr + + DT_REG_SIZE(DT_NODELABEL(slot2_partition)) - 1; + at_tz_mpc_config_region(slot2_baddr, slot2_laddr, AT_TZ_MPC_ATTR_NONSECURE); +#endif + +#if DT_NODE_EXISTS(DT_NODELABEL(fast_code_partition)) + uint32_t fast_code_baddr = PART_ADDR(fast_code_partition); + uint32_t fast_code_laddr = fast_code_baddr + + DT_REG_SIZE(DT_NODELABEL(fast_code_partition)) - 1; + at_tz_mpc_config_region(fast_code_baddr, fast_code_laddr, AT_TZ_MPC_ATTR_NONSECURE); +#endif + + // Permit access to RRAM registers + at_tz_mpc_config_region(ROM_RRAM_SIZE, ROM_RRAM_SIZE + 0x800 - 1, + AT_TZ_MPC_ATTR_NONSECURE); + // permit AT_PRRF_NONSECURE access and external Flash + at_tz_mpc_config_region(CMSDK_EXT_FLASH_NONSECURE_BASE - 0x800, + CMSDK_EXT_FLASH_NONSECURE_BASE + AT_TZ_MPC_EXT_FLASH_MPC_SIZE - 1, + AT_TZ_MPC_ATTR_NONSECURE); + at_tz_mpc_config_remaining_ext_flash(AT_TZ_MPC_ATTR_NONSECURE); + + // Configuring MPC of RAM + at_tz_mpc_enable_int(AT_TZ_MPC_DEV_RAM); + at_tz_mpc_config_region(DT_REG_ADDR(DT_NODELABEL(sram0)) + + DT_REG_SIZE(DT_NODELABEL(sram0)), + DT_REG_ADDR(DT_NODELABEL(sram0)) + RAM_SIZE - 1, + AT_TZ_MPC_ATTR_NONSECURE); + at_tz_mpc_enable_bus_fault(AT_TZ_MPC_DEV_FLASH); + at_tz_mpc_enable_bus_fault(AT_TZ_MPC_DEV_RAM); + + return; +} + +// Strip off IDAU bit to get physical address +#define GET_PHYS_ADDR(addr) ((addr) & ~0x10000000) + +extern uint32_t __sg_start; +extern uint32_t __sg_end; +#define NSC_EN_REGION_START ((uint32_t)&__sg_start) +#define NSC_EN_REGION_END ((uint32_t)&__sg_end - 1) + +static void sau_cfg(void) +{ +#ifdef CONFIG_ATM_SPE_DISABLE_SAU + at_tz_sau_disable(); +#else + at_tz_sau_enable(); + + uint8_t sau_region = 0; + + // Allocate RRAM, RRAM regs, prrf, and ext_flash as NS to save on SAU regions + // Relies on NS region immediately following SPE. + uint32_t rram_ns_start = PART_SPE_NSPE_ADDR(spe_partition) + + DT_REG_SIZE(DT_NODELABEL(spe_partition)); + uint32_t rram_flash_baddr = GET_PHYS_ADDR(rram_ns_start); + uint32_t rram_flash_laddr = + GET_PHYS_ADDR(DT_REG_ADDR(DT_NODELABEL(flash_controller))) + + DT_REG_SIZE(DT_NODELABEL(flash_controller)) - 1; + at_tz_sau_ret_t ret = at_tz_sau_enable_region(sau_region++, + AT_TZ_SAU_BADDR_MASK(rram_flash_baddr), + AT_TZ_SAU_LADDR_MASK(rram_flash_laddr), AT_TZ_SAU_NS); + + uint32_t ns_sram_baddr = GET_PHYS_ADDR(DT_REG_ADDR(DT_NODELABEL(sram0))) + + DT_REG_SIZE(DT_NODELABEL(sram0)); + uint32_t ns_sram_laddr = + GET_PHYS_ADDR(DT_REG_ADDR(DT_NODELABEL(sram0))) + RAM_SIZE - 1; + ret = at_tz_sau_enable_region(sau_region++, + AT_TZ_SAU_BADDR_MASK(ns_sram_baddr), + AT_TZ_SAU_LADDR_MASK(ns_sram_laddr), AT_TZ_SAU_NS); + + // Allocate non-secure callable region + ret = at_tz_sau_enable_region(sau_region++, + AT_TZ_SAU_BADDR_MASK((unsigned int)NSC_EN_REGION_START), + AT_TZ_SAU_LADDR_MASK((unsigned int)NSC_EN_REGION_END), AT_TZ_SAU_NSC); + + // Allocate peripheral region + uint32_t peripheral_baddr = GET_PHYS_ADDR( + DT_RANGES_PARENT_BUS_ADDRESS_BY_IDX(DT_PATH(soc, peripheral_50000000), + 0)); + uint32_t peripheral_laddr = peripheral_baddr + + DT_RANGES_LENGTH_BY_IDX(DT_PATH(soc, peripheral_50000000), 0) - 1; + ret = at_tz_sau_enable_region(sau_region++, + AT_TZ_SAU_BADDR_MASK(peripheral_baddr), + AT_TZ_SAU_LADDR_MASK(peripheral_laddr), AT_TZ_SAU_NS); + +#ifdef CONFIG_BOOTLOADER_MCUBOOT + // Allow mcumgr to read image header. + uint32_t boot_hdr_baddr = GET_PHYS_ADDR(PART_SPE_NSPE_ADDR(spe_partition)); + uint32_t boot_hdr_laddr = boot_hdr_baddr + CONFIG_ROM_START_OFFSET - 1; + ret = at_tz_sau_enable_region(sau_region++, + AT_TZ_SAU_BADDR_MASK(boot_hdr_baddr), + AT_TZ_SAU_LADDR_MASK(boot_hdr_laddr), AT_TZ_SAU_NS); +#endif // CONFIG_BOOTLOADER_MCUBOOT +#endif // CONFIG_ATM_SPE_DISABLE_SAU + __DSB(); + __ISB(); + // SAU programming done early enough that only secure code has executed. + // No need to invalidate the caches. +} + +// security lockdowns before the SAU is enabled +// At this stage all peripherals can be accessed by +// both their SECURE and NON-SECURE aliases +static void pre_sau_security_lockdown(void) +{ + bool sec_s; + + // lock out the ROM patch controller + sec_s = sec_device_set_lockout(SEC_DEV_LOCKOUT_ROM_P_CFG); + SEC_ASSERT(sec_s); + // lock out the OTP controller's write capability + sec_s = sec_device_set_lockout(SEC_DEV_LOCKOUT_OTP_WR); + SEC_ASSERT(sec_s); + +#ifdef CONFIG_ATM_SPE_DISABLE_SHUB + // lock out shub + sec_s = sec_device_set_lockout(SEC_DEV_LOCKOUT_SHUB_DISABLE); + SEC_ASSERT(sec_s); + printk("SHUB disabled\n"); +#endif + + // lock out the ROM + uint32_t rom_offset = ROM_ADDR_TO_OFFSET(CMSDK_FLASH_BASE); + printk("ROM RP: 0x%x, 0x%lx \n", rom_offset, ROM_SIZE); + sec_s = rom_prot_sticky_read_disable(rom_offset, ROM_SIZE); + SEC_ASSERT(sec_s); + +#if DT_NODE_EXISTS(DT_NODELABEL(boot_partition)) + // read/write protect MCUBOOT partition + uint32_t mcuboot_offset = PART_OFFSET(boot_partition); + uint32_t mcuboot_size = DT_REG_SIZE(DT_NODELABEL(boot_partition)); + printk("MCUBoot RWP: 0x%x, 0x%x \n", mcuboot_offset, mcuboot_size); + sec_s = rram_prot_sticky_write_disable(mcuboot_offset, mcuboot_size); + SEC_ASSERT(sec_s); + sec_s = rram_prot_sticky_read_disable(mcuboot_offset, mcuboot_size); + SEC_ASSERT(sec_s); +#endif + +#if DT_NODE_EXISTS(DT_NODELABEL(slot2_partition)) + // sticky lock atmwstk + uint32_t atmwstk_offset = PART_OFFSET(slot2_partition); + uint32_t atmwstk_size = DT_REG_SIZE(DT_NODELABEL(slot2_partition)); + printk("ATMWSTK WP: 0x%x, 0x%x \n", atmwstk_offset, atmwstk_size); + sec_s = rram_prot_sticky_write_disable(atmwstk_offset, atmwstk_size); + SEC_ASSERT(sec_s); +#endif + + // NOTE: primary slot locking happens in MCUBOOT +} + +// Perform any post-SAU security lock down. +// At this point memory/peripherals have been assigned to secure or non-secure. +static void post_sau_security_lockdown(void) +{ +} + +FUNC_NORETURN void spe_main(void) +{ + ICACHE->ICCTRL = ICACHE_ICCTRL_CACHEEN_Msk; + + printk("*** Zephyr SPE ***\n"); + printk("* SPE range: [0x%08x - 0x%08x]\n", + (unsigned int)PART_SPE_NSPE_ADDR(spe_partition), + (unsigned int)PART_SPE_NSPE_ADDR(spe_partition) + + (unsigned int)DT_REG_SIZE(DT_NODELABEL(spe_partition))); + printk("* NSPE range: [0x%08x - 0x%08x]\n", + (unsigned int)PART_SPE_NSPE_ADDR(nspe_partition), + (unsigned int)PART_SPE_NSPE_ADDR(nspe_partition) + + (unsigned int)DT_REG_SIZE(DT_NODELABEL(nspe_partition))); + printk("***\n"); + + // Enables BusFault, MemFault, UsageFault and SecureFault + SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk | + SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_SECUREFAULTENA_Msk; + + // Allow fpu access in nonsecure mode. + SCB->NSACR |= (1UL << SCB_NSACR_CP10_Pos) | (1UL << SCB_NSACR_CP11_Pos); + + // TODO: Handle Watchdog. + + // Permit NS Watchdog to reset system + SYS_CTRL_REG->RESET_MASK |= SYS_CTRL_REG_SSE200_RESET_MASK_NSWD_EN_Msk; + + pre_sau_security_lockdown(); + + // Enable and configure security controllers (SAU and MPC) + sau_cfg(); + mpc_cfg(); + + // Redirect interrupts to non-secure handlers + IRQn_Type irq; + for (irq = NSECUREWDOG_RESETREQ_IRQn; irq <= DUALTIMER_IRQn; irq++) { + irq_target_state_set(irq, IRQ_TARGET_STATE_NON_SECURE); + } + for (irq = UARTRX0_IRQn; irq <= PORT1_15_IRQn; irq++) { + irq_target_state_set(irq, IRQ_TARGET_STATE_NON_SECURE); + } + // configure PPC to set peripherals to NS space. + at_tz_ppc_init_ns_cfg(); + + post_sau_security_lockdown(); + + uint32_t *application_addr = + (uint32_t *)(PART_SPE_NSPE_ADDR(nspe_partition) & ~0x10000000); + // // jump to application image. + SCB_NS->VTOR = (uint32_t)application_addr; + __TZ_set_MSP_NS(application_addr[0]); + register uint32_t addr = application_addr[1] & ~0x1; // S->NS: clear LSB + __ASM volatile("BXNS %0" : : "r"(addr)); + __builtin_unreachable(); +} + +int main(void) +{ + spe_main(); + return 0; +} diff --git a/ATM33xx-5/include/arch.h b/ATM33xx-5/include/arch.h new file mode 100644 index 0000000..c542fb1 --- /dev/null +++ b/ATM33xx-5/include/arch.h @@ -0,0 +1,638 @@ +/** + **************************************************************************************** + * + * @file arch.h + * + * @brief This file contains the definitions of the macros and functions that are + * architecture dependent. The implementation of those is implemented in the + * appropriate architecture directory. + * + * Copyright (C) RivieraWaves 2009-2015 + * Copyright (C) Atmosic 2020-2024 + * + **************************************************************************************** + */ + + +#ifndef _ARCH_H_ +#define _ARCH_H_ + +/** + **************************************************************************************** + * @defgroup REFIP + * @brief Reference IP Platform + * + * This module contains reference platform components - REFIP. + * + * + * @{ + **************************************************************************************** + */ + +/** + **************************************************************************************** + * @defgroup DRIVERS + * @ingroup REFIP + * @brief Reference IP Platform Drivers + * + * This module contains the necessary drivers to run the platform with the + * RW BT SW protocol stack. + * + * This has the declaration of the platform architecture API. + * + * + * @{ + **************************************************************************************** + */ + +/* + * INCLUDE FILES + **************************************************************************************** + */ +#if defined(CFG_BLE_EMB) || defined(CFG_BLE_HOST) +#include "rwip_config.h" // SW configuration +#endif + +#include // standard integer definition +#include // standard boolean definition +#include "compiler.h" // inline functions +#include "ll.h" +#include "ARMv8MBL.h" +#include "base_addr.h" +#ifndef CONFIG_SOC_FAMILY_ATM +#include "retarget_uart.h" +#undef printf +#endif + +#include "rep_vec.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * CPU WORD SIZE + **************************************************************************************** + */ +/// ARM is a 32-bit CPU +#define CPU_WORD_SIZE 4 + +/* + * CPU Endianness + **************************************************************************************** + */ +/// ARM is little endian +#define CPU_LE 1 + +/* + * Constructor ordering + */ +#define CONSTRUCTOR_WATCHDOG 101 // Very first constructor +#define CONSTRUCTOR_SPI 102 // Needed by reset driver +#define CONSTRUCTOR_PSEQ 103 // Power-on management +#define CONSTRUCTOR_RESET 104 // Reset reason +#define CONSTRUCTOR_HW_CFG 105 // HW calibration +#define CONSTRUCTOR_LED 106 // Before drivers configure pinmux +#define CONSTRUCTOR_DTOP_BYPASS 107 // Can change sysclk +#define CONSTRUCTOR_PINMUX 108 // After HW_CFG; check BOARD +#define CONSTRUCTOR_MAIN 198 // Main constructor +#define CONSTRUCTOR_USER_INIT 199 // Last numbered constructor +// Followed by unnumbered constructors + +/* + * DEBUG configuration + **************************************************************************************** + */ +#if defined(CFG_DBG) || defined(CFG_PLF_DEBUG) +#define PLF_DEBUG 1 +#else //CFG_DBG +#define PLF_DEBUG 0 +#endif //CFG_DBG + + +#if defined(CFG_PROFILING) +#define PLF_PROFILING 1 +#else //CFG_DBG +#define PLF_PROFILING 0 +#endif //CFG_PROFILING + +#if defined(CFG_MEM_PROTECTION) +#define PLF_MEM_PROTECTION 1 +#else //CFG_DBG +#define PLF_MEM_PROTECTION 0 +#endif //CFG_PROFILING + +/* + * NVDS + **************************************************************************************** + */ + +/// NVDS +#ifdef CFG_NVDS +#define PLF_NVDS 1 +#else // CFG_NVDS +#define PLF_NVDS 0 +#endif // CFG_NVDS + + +/* + * UART + **************************************************************************************** + */ + +/// UART +#define PLF_UART 1 + +/// UART 2 +#define PLF_UART2 0 + +/* + * DMA + **************************************************************************************** + */ + +/// DMA +#define PLF_DMA (BLE_EMB_PRESENT && BLE_ISO_PRESENT) + +/* + * SBC + **************************************************************************************** + */ + +/// SBC Generator +#define PLF_SBCGEN (defined(CFG_SBCGEN)) +/// SBC Forwarder +#define PLF_SBCFWD (defined(CFG_BLUEBUD_TWS_TX)) +/// SBC Receiver +#define PLF_SBCRX (defined(CFG_BLUEBUD_TWS_RX)) + +/* + * DEFINES + **************************************************************************************** + */ + +/// Hardware compatibility +#define CMSDK_AES CMSDK_AES_NONSECURE +#define CMSDK_GADC CMSDK_GADC_NONSECURE +#define CMSDK_I2C0 CMSDK_I2C0_NONSECURE +#define CMSDK_I2C1 CMSDK_I2C1_NONSECURE +#define CMSDK_I2S CMSDK_I2S_NONSECURE +#define CMSDK_KSM CMSDK_KSM_NONSECURE +#define CMSDK_MDM CMSDK_MDM_NONSECURE +#define CMSDK_PDM CMSDK_PDM0_NONSECURE +#define CMSDK_AHB_PDM_PP_BASE CMSDK_PDM0_PP_NONSECURE_BASE +#define CMSDK_PMU CMSDK_PMU_NONSECURE +#define CMSDK_PWM CMSDK_PWM_NONSECURE +#define CMSDK_PSEQ CMSDK_PSEQ_NONSECURE +#define CMSDK_QDEC CMSDK_QDEC_NONSECURE +#define CMSDK_QSPI CMSDK_QSPI_NONSECURE +#define CMSDK_RADIO CMSDK_RADIO_NONSECURE +#define CMSDK_RIF CMSDK_RIF_NONSECURE +#define CMSDK_SHUB CMSDK_SHUB_NONSECURE +#define CMSDK_SLWTIMER CMSDK_SLWTIMER_NONSECURE +#define CMSDK_SPI0 CMSDK_SPI0_NONSECURE +#define CMSDK_SPI1 CMSDK_SPI1_NONSECURE +#define CMSDK_SPI2 CMSDK_SPI2_NONSECURE +#define CMSDK_SWD CMSDK_SWD_NONSECURE +#define CMSDK_TRNG CMSDK_TRNG_NONSECURE +#undef CMSDK_AT_UART0 +#define CMSDK_AT_UART0 CMSDK_AT_UART0_NONSECURE +#undef CMSDK_UART1 +#define CMSDK_UART1 CMSDK_AT_UART1_NONSECURE +#define UARTOVF0_IRQn UART0_OVERFLOW_IRQn +#define UARTOVF1_IRQn UART1_OVERFLOW_IRQn +#define CMSDK_WATCHDOG NONSECURE_WATCHDOG + +/// Possible errors detected by FW +#define RESET_NO_ERROR 0x00000000 +#define RESET_MEM_ALLOC_FAIL 0xF2F2F2F2 +#define RESET_WATCHDOG 0xDEDEDEDE + +/// Reset platform and stay in ROM +#define RESET_TO_ROM 0xA5A5A5A5 +/// Reset platform and reload FW +#define RESET_AND_LOAD_FW 0xC3C3C3C3 + +#if defined(CFG_BLE_EMB) || defined(CFG_BLE_HOST) +/// Exchange memory size limit +#if (BT_DUAL_MODE) +#define EM_SIZE_LIMIT 0x10000 +#else +#define EM_SIZE_LIMIT 0x8000 +#endif +#endif // CFG_BLE_EMB || CFG_BLE_HOST + + +/** + * EM Fetch time (in us) + * - EM fetch: 30us (worst case at 26Mhz) + * - HW logic: 10us (worst case at 26Mhz) + */ +#define PLF_EM_FETCH_TIME_US 40 + +/** + * EM update time (in us): + * - HW CS Update is 18 access + * - HW Tx Desc Update is 1 access + * - HW Rx Desc Update is 5 access + * => EM update at 26MHz Tx, Rx and CS is (18+1+5)*0.04*4 = 4us + * - HW logic: 10us (worst case) + */ +#define PLF_EM_UPDATE_TIME_US 14 + + +/// Power saving modes +#define SLEEP_ENABLE_NONE 0 +#define SLEEP_ENABLE_DEEP 1 +#define SLEEP_ENABLE_RETAIN 2 +#define SLEEP_ENABLE_RETAIN_DROP 3 +#define SLEEP_ENABLE_HIBERNATE 4 +#define SLEEP_ENABLE_SOC_OFF 5 +#define SLEEP_ENABLE_TEST_MASK 0x80 + +/* + * EXPORTED FUNCTION DECLARATION + **************************************************************************************** + */ + +/** + * @brief System was power on boot. + * @return true when digital domain was reset before boot + */ +bool boot_was_cold(void); + +#if defined(CFG_BLE_EMB) || defined(CFG_BLE_HOST) +#ifndef RWIP_CONFIG_H_ + +#if (RW_DEBUG_STACK_PROF) +/** +**************************************************************************************** +* @brief Initialise stack memory area. +* +* This function initialises the stack memory with pattern for use in stack profiling. +**************************************************************************************** +*/ +void stack_init(void); + +/** + **************************************************************************************** + * @brief Compute size of SW stack used. + * + * This function is compute the maximum size stack used by SW. + * + * @return Size of stack used (in bytes) + **************************************************************************************** + */ +uint16_t get_stack_usage(void); +#endif //(RW_DEBUG_STACK_PROF) + +#endif // RWIP_CONFIG_H_ +#endif // CFG_BLE_EMB || CFG_BLE_HOST + +/** + **************************************************************************************** + * @brief Re-boot FW. + * + * This function is used to re-boot the FW when error has been detected, it is the end of + * the current FW execution. + * After waiting transfers on UART to be finished, and storing the information that + * FW has re-booted by itself in a non-loaded area, the FW restart by branching at FW + * entry point. + * + * Note: when calling this function, the code after it will not be executed. + * + * @param[in] error Error detected by FW + **************************************************************************************** + */ +__NORETURN void platform_reset(uint32_t error); + +/** + * @brief User application main function + * @returns nothing - ignored + */ +int user_main(void); + +/** + * @brief RW main function. + * + * This function is called right after user_main(). + */ +void rw_main(void); + +#if PLF_DEBUG +/** + **************************************************************************************** + * @brief Print the assertion error reason and loop forever. + * + * @param condition C string containing the condition. + * @param file C string containing file where the assertion is located. + * @param line Line number in the file where the assertion is located. + **************************************************************************************** + */ +void assert_err(const char *condition, const char * file, int line); + +/** + **************************************************************************************** + * @brief Print the assertion error reason and loop forever. + * The parameter value that is causing the assertion will also be disclosed. + * + * @param param0 parameter value 0. + * @param param1 parameter value 1. + * @param file C string containing file where the assertion is located. + * @param line Line number in the file where the assertion is located. + **************************************************************************************** + */ +void assert_param(int param0, int param1, const char * file, int line); + +/** + **************************************************************************************** + * @brief Print the assertion warning reason. + * + * @param param0 parameter value 0. + * @param param1 parameter value 1. + * @param file C string containing file where the assertion is located. + * @param line Line number in the file where the assertion is located. + **************************************************************************************** + */ +void assert_warn(int param0, int param1, const char * file, int line); + + +/** + **************************************************************************************** + * @brief Dump HCI data + * + * @param[in] type HCI Packet type + * @param[in] direction 0: Output, 1: Input + * @param[in] p_data Pointer to HCI data + * @param[in] length Length of HCI data + * @param[in] p_hdr_data Pointer to HCI Header data + * @param[in] hdr_length Length of HCI header data + **************************************************************************************** + */ +void dump_hci(uint8_t type, uint8_t direction, uint8_t* p_data, uint16_t length, uint8_t* p_hdr_data, uint16_t hdr_length); + +/** + **************************************************************************************** + * @brief Dump HCI data in unpacked format + * + * @param[in] evttype HCI Packet type (@see enum hl_hci_evt_type) + * @param[in] direction 0: Output, 1: Input + * @param[in] code Event of Command Operation code + * @param[in] p_data Pointer to HCI data + * @param[in] length Length of HCI data + **************************************************************************************** + */ +void dump_upk_hci(uint8_t evttype, uint8_t direction, uint16_t code, uint8_t* p_data, uint16_t length); + +#ifdef RTT_DBG +__PRINTF(1, 2) int debug_trace_rtt(const char *format, ...); +#define DEBUG_TRACE_SEL debug_trace_rtt +#else +#define DEBUG_TRACE_SEL debug_trace +#endif +#endif //PLF_DEBUG + +/** + * @brief Debug trace log with timestamp + * @param[in] format Printf-style formatter + * @param ... Arguments for formatter + * @returns Number of characters logged + */ +__PRINTF(1, 2) int debug_trace(const char *format, ...); + +#if (defined(CFG_PROFILING)) +/** + **************************************************************************************** + * @brief Trace enter into a function + * + * @param[in] p_func_ptr Pointer of the function + * @param[in] p_func_name_ptr Pointer of the function name + **************************************************************************************** + */ +void func_enter(const void* p_func_ptr, const void* p_func_name_ptr); + +/** + **************************************************************************************** + * @brief Trace exit of a function + * + * @param[in] p_func_ptr Pointer of the function + * @param[in] p_func_name_ptr Pointer of the function name + **************************************************************************************** + */ +void func_exit(const void* p_func_ptr, const void* p_func_name_ptr); + +/** + **************************************************************************************** + * @brief Trace data into a VCD + * + * @param[in] p_ptr Data pointer address + * @param[in] p_name_ptr Data variable name pointer address + * @param[in] data_size Size of data to trace in bytes (8, 16 or 32 only) + **************************************************************************************** + */ +void data_trace(const void* p_ptr, const void* p_name_ptr, uint8_t data_size); + +#endif // (defined(CFG_PROFILING)) + +#if (defined(CFG_MEM_LEAK_DETECT)) +/** + **************************************************************************************** + * @brief Trace data pointer allocation + * + * @param[in] p_ptr Data pointer address + **************************************************************************************** + */ +void data_trace_alloc(const void* p_ptr, const char* filename, uint16_t line); + +/** + **************************************************************************************** + * @brief Trace data pointer free + * + * @param[in] p_ptr Data pointer address + **************************************************************************************** + */ +void data_trace_free(const void* p_ptr); + +#endif // (defined(CFG_MEM_LEAK_DETECT)) + +#if (defined(CFG_MEM_PROTECTION)) +/** + **************************************************************************************** + * @brief Control memory access + * + * @param[in] p_mem_ptr Pointer to memory block + * @param[in] enable True to grant complete access on memory block, False to flow memory permissions + **************************************************************************************** + */ +void mem_grant_access_ctrl(const void* p_mem_ptr, bool enable); + + +/** + **************************************************************************************** + * @brief Set permission onto a specific memory block + * + * @param[in] p_mem_ptr Pointer to memory block + * @param[in] size Size of the memory block + * @param[in] write_en True to enable write permission, False to disable write + * @param[in] read_en True to enable read permission, False to disable read + * @param[in] init_clr True to mark memory block not initialized, False: no action + **************************************************************************************** + */ +void mem_perm_set(const void* p_mem_ptr, uint16_t size, bool write_en, bool read_en, bool init_clr); + +/** + **************************************************************************************** + * @brief Mark memory block initialized - without modifying memory data + * + * @param[in] p_mem_ptr Pointer to memory block + * @param[in] size Size of the memory block + **************************************************************************************** + */ +void mem_init(const void* p_mem_ptr, uint16_t size); + +/// Store memory protection grant context +void mem_grant_store_context(void); +/// Restore memory protection grant context +void mem_grant_restore_context(void); +#endif // (defined(CFG_MEM_PROTECTION)) + +/* + * ASSERTION CHECK + **************************************************************************************** + */ +#if PLF_DEBUG +/// Assertions showing a critical error that could require a full system reset +#define ASSERT_ERR(cond) \ + do { \ + if (!(cond)) { \ + assert_err(#cond, __MODULE__, __LINE__); \ + } \ + } while(0) + +/// Assertions showing a critical error that could require a full system reset +#define ASSERT_INFO(cond, param0, param1) \ + do { \ + if (!(cond)) { \ + assert_param((int)param0, (int)param1, __MODULE__, __LINE__); \ + } \ + } while(0) + +/// Assertions showing a non-critical problem that has to be fixed by the SW +#define ASSERT_WARN(cond, param0, param1) \ + do { \ + if (!(cond)) { \ + assert_warn((int)param0, (int)param1, __MODULE__, __LINE__); \ + } \ + } while(0) + +/// DUMP HCI packet +#define DUMP_HCI(type, direction, data, length)\ + dump_hci(type, direction, (uint8_t*)data, length, NULL, 0) + +/// DUMP HCI packet +#define DUMP_HCI_2(type, direction, hdr_data, hdr_length, data, length)\ + dump_hci(type, direction, (uint8_t*)data, length, (uint8_t*)hdr_data, hdr_length) + +/// DUMP HCI packet in unpacked format +#define DUMP_UPK_HCI(evttype, direction, code, data, length)\ + dump_upk_hci(evttype, direction, code, (uint8_t*)data, length) + +#define DEBUG_TRACE(fmt, ...) \ + DEBUG_TRACE_SEL(fmt, ##__VA_ARGS__) +#define DEBUG_TRACE_COND(cond, fmt, ...) do { \ + if (cond) { \ + DEBUG_TRACE_SEL(fmt, ##__VA_ARGS__); \ + } \ +} while(0) + +#else +/// Assertions showing a critical error that could require a full system reset +#define ASSERT_ERR(cond) + +/// Assertions showing a critical error that could require a full system reset +#define ASSERT_INFO(cond, param0, param1) + +/// Assertions showing a non-critical problem that has to be fixed by the SW +#define ASSERT_WARN(cond, param0, param1) + +/// DUMP HCI packet +#define DUMP_HCI(type, direction, data, length) +/// DUMP HCI packet +#define DUMP_HCI_2(type, direction, hdr_data, hdr_length, data, length) +/// DUMP HCI packet in unpacked format +#define DUMP_UPK_HCI(evttype, direction, code, data, length) + +#define DEBUG_TRACE(fmt, ...) do { \ + if (0) { \ + debug_trace(fmt, ##__VA_ARGS__); \ + } \ +} while(0) +#define DEBUG_TRACE_COND(cond, fmt, ...) do { \ + if (0) { \ + debug_trace(fmt, ##__VA_ARGS__); \ + } \ +} while(0) + +#endif //PLF_DEBUG + +#if (defined(CFG_PROFILING)) +/// Trace data into a VCD +#define DBG_DATA_TRACE(data, size) data_trace(&data, #data, size) + +/// Trace Function Enter +#define DBG_FUNC_ENTER(func) func_enter(func, #func) + +/// Trace Function Exit +#define DBG_FUNC_EXIT(func) func_exit(func, #func) +#else +/// Trace data into a VCD +#define DBG_DATA_TRACE(data, size) +/// Trace Function Enter +#define DBG_FUNC_ENTER(func) +/// Trace Function Exit +#define DBG_FUNC_EXIT(func) +#endif // (defined(CFG_PROFILING)) + +#if (defined(CFG_MEM_LEAK_DETECT)) +/// Trace data allocation +#define DBG_DATA_ALLOC(data, filename, line) data_trace_alloc(data, filename, line) +/// Trace data free +#define DBG_DATA_FREE(data) data_trace_free(data) +#else +/// Trace data allocation +#define DBG_DATA_ALLOC(...) +/// Trace data free +#define DBG_DATA_FREE(data) +#endif // (defined(CFG_MEM_LEAK_DETECT)) + +#if (defined(CFG_MEM_PROTECTION)) +/// Control memory access +#define DBG_MEM_GRANT_CTRL(mem_ptr, enable) mem_grant_access_ctrl(mem_ptr, enable) +/// Set permission onto a specific memory block +#define DBG_MEM_PERM_SET(mem_ptr, size, write_en, read_en, init_clr) mem_perm_set(mem_ptr, size, write_en, read_en, init_clr) +/// Mark memory initialized +#define DBG_MEM_INIT(mem_ptr, size) mem_init(mem_ptr, size) +/// Store grant context when executing ISR +#define DBG_MEM_ISR_ENTER() mem_grant_store_context() +/// Restore grant context when ISR execution is over +#define DBG_MEM_ISR_EXIT() mem_grant_restore_context() +#else // !(defined(CFG_MEM_PROTECTION)) +/// Control memory access +#define DBG_MEM_GRANT_CTRL(mem_ptr, enable) +/// Set permission onto a specific memory block +#define DBG_MEM_PERM_SET(mem_ptr, size, write_en, read_en, init_clr) +/// Mark memory initialized +#define DBG_MEM_INIT(mem_ptr, size) +#define DBG_MEM_ISR_ENTER() +#define DBG_MEM_ISR_EXIT() +#endif // (defined(CFG_MEM_PROTECTION)) + +#ifdef __cplusplus +} +#endif + +// required to define GLOBAL_INT_** macros as inline assembly. This file is included after +// definition of ASSERT macros as they are used inside ll.h +#include "ll.h" // ll definitions +/// @} DRIVERS +#endif // _ARCH_H_ diff --git a/ATM33xx-5/include/arm/ARMv8MBL.h b/ATM33xx-5/include/arm/ARMv8MBL.h new file mode 100755 index 0000000..a661a1a --- /dev/null +++ b/ATM33xx-5/include/arm/ARMv8MBL.h @@ -0,0 +1,4152 @@ +/**************************************************************************//** + * @file ARMv8MBL.h + * @brief CMSIS Core Peripheral Access Layer Header File for + * ARMv8MBL Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2024 Atmosic Technologies. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ARMv8MBL_H +#define ARMv8MBL_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/* ------------------- Processor Exceptions Numbers ----------------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + MemManage_IRQn = -12, /* 4 MemManage Fault Interrupt */ + BusFault_IRQn = -11, /* 5 BusManage Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 UsageManage Fault Interrupt */ + SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ + + + + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMon_IRQn = -4, /* 12 Debug Monitor Interrupt */ + + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/* ------------------- Processor Interrupt Numbers ------------------------------ */ +/* NAME PORT DESCRIPTION SSE200 SECURE */ + NSECUREWDOG_RESETREQ_IRQn = 0, /* Non-secure watchdog reset request Y */ + NSECUREWDOG_INT_IRQn = 1, /* Non-secure watchdog interrupt Y */ + S32K_TIMER_IRQn = 2, /* S32K TIMER Y */ + TIMER0_IRQn = 3, /* TIMER0 irq */ + TIMER1_IRQn = 4, /* TIMER1 irq */ + DUALTIMER_IRQn = 5, /* DUALTIMER irq */ + MHU0_CPU0_IRQn = 6, /* MHU0 CPU0 Interrupt */ + MHU1_CPU0_IRQn = 7, /* MHU1 CPU0 Interrupt */ + CRYPTO_IRQn = 8, /* Cryptocell Interrupt */ + MPC_COMB_SEC_IRQn = 9, /* MPC Combined Interrupt Y Y */ + PPC_COMB_SEC_IRQn = 10, /* PPC Combined Interrupt Y Y */ + MSC_COMB_SEC_IRQn = 11, /* MSC Combined Interrupt Y Y */ + BRD_ERR_COMB_IRQn = 12, /* Bridge Error Combined Interrupt Y Y */ + ICACHE_IRQn = 13, /* Icache Invalidate Interrupt */ + RESERVED_14_IRQn = 14, /* RESERVED */ + SYS_PPU_IRQn = 15, /* SYS PPU */ + CPU0_PPU_IRQn = 16, /* CPU0 PPU */ + CPU1_PPU_IRQn = 17, /* CPU1 PPU */ + CPU0DBG_PPU_IRQn = 18, /* CPU0 DBG PPU */ + CPU1DBG_PPU_IRQn = 19, /* CPU1 DBG PPU */ + CRYPT_PPU_IRQn = 20, /* CRYPT PPU */ + RESERVED_21_IRQn = 21, /* RESERVED */ + RAM0_PPU_IRQn = 22, /* RAM0 PPU */ + RAM1_PPU_IRQn = 23, /* RAM1 PPU */ + RAM2_PPU_IRQn = 24, /* RAM2 PPU */ + RAM3_PPU_IRQn = 25, /* RAM3 PPU */ + DBG_PPU_IRQn = 26, /* CPU0 PPU */ + RESERVED_27_IRQn = 27, /* RESERVED */ + RESERVED_28_IRQn = 28, /* RESERVED */ + RESERVED_29_IRQn = 29, /* RESERVED */ + RESERVED_30_IRQn = 30, /* RESERVED */ + RESERVED_31_IRQn = 31, /* RESERVED */ + UARTRX0_IRQn = 32, /* APB0 irq[0] <-- uart0 rx */ + UARTTX0_IRQn = 33, /* APB0 irq[1] <-- uart0 tx */ + UARTRX1_IRQn = 34, /* APB0 irq[2] <-- uart1 rx */ + UARTTX1_IRQn = 35, /* APB0 irq[3] <-- uart1 tx */ + SPI1_IRQn = 36, /* APB0 irq[4] <-- spi1 */ + EXPIRQn_37 = 37, /* APB0 irq[5] <-- */ + EXPIRQn_38 = 38, /* APB0 irq[6] <-- */ + EXPIRQn_39 = 39, /* APB0 irq[7] <-- */ + SPI0_IRQn = 40, /* APB0 irq[8] <-- spi0 */ + UART0_OVERFLOW_IRQn = 41, /* APB0 irq[9] <-- uart0 overflow */ + UART1_OVERFLOW_IRQn = 42, /* APB0 irq[10] <-- uart1 overflow */ + KSM_IRQn = 43, /* APB0 irq[11] <-- ksm */ + SLWTIMER_IRQn = 44, /* APB0 irq[12] <-- slwtimer */ + SPI2_IRQn = 45, /* APB0 irq[13] <-- spi2 */ + PWM_IRQn = 46, /* APB0 irq[14] <-- pwm */ + EXPIRQn_47 = 47, /* APB0 irq[15] */ + SPI_RADIO_IRQn = 48, /* APB1 irq[0] <-- radio */ + SPI_PMU_IRQn = 49, /* APB1 irq[1] <-- pmu */ + I2C0_IRQn = 50, /* APB1 irq[2] <-- i2c0 */ + I2C1_IRQn = 51, /* APB1 irq[3] <-- i2c1 */ + NVM_IRQn = 52, /* APB1 irq[4] <-- nvm */ + GADC_IRQn = 53, /* APB1 irq[5] <-- gadc */ + TRNG_IRQn = 54, /* APB1 irq[6] <-- trng */ + RCOS_IRQn = 55, /* APB1 irq[7] <-- rcos */ + PDM0_IRQn = 56, /* APB2 irq[0] <-- pdm0 */ + PDM1_IRQn = 57, /* APB2 irq[1] <-- pdm1 */ + PDM2_IRQn = 58, /* APB2 irq[2] <-- pdm2 */ + PDM3_IRQn = 59, /* APB2 irq[3] <-- pdm3 */ + I2S_IRQn = 60, /* APB2 irq[4] <-- i2s */ + EXPIRQn_61 = 61, /* APB2 irq[5] */ + EXPIRQn_62 = 62, /* APB2 irq[6] */ + EXPIRQn_63 = 63, /* APB2 irq[7] */ + MDM_IRQn = 64, /* mdm_irq */ + EXPIRQn_65 = 65, /* */ + EXPIRQn_66 = 66, /* */ + EXPIRQn_67 = 67, /* */ + DMA0_IRQn = 68, /* dma0_done|dma0_err */ + DMA1_IRQn = 69, /* dma1_done|dma1_err */ + DMA2_IRQn = 70, /* dma2_done|dma2_err */ + DMA3_IRQn = 71, /* dma3_done|dma3_err */ + BLE_SW_IRQn = 72, /* ble_sw_irq */ + BLE_FINETGT_IRQn = 73, /* ble_finetgt_irq */ + BLE_TIMESTAMP_TGT1_IRQn = 74, /* ble_timestamp_tgt1_irq */ + BLE_TIMESTAMP_TGT2_IRQn = 75, /* ble_timestamp_tgt2_irq */ + BLE_TIMESTAMP_TGT3_IRQn = 76, /* ble_timestamp_tgt3_irq */ + BLE_CRYPT_IRQn = 77, /* ble_crypt_irq */ + BLE_SLP_IRQn = 78, /* ble_slp_irq */ + BLE_HSLOT_IRQn = 79, /* ble_hslot_irq */ + BLE_FIFO_IRQn = 80, /* ble_fifo_irq */ + BLE_ERROR_IRQn = 81, /* ble_error_irq */ + BLE_HOP_IRQn = 82, /* ble_hop_irq */ + BLE_ISOTS_0_IRQn = 83, /* ble_isots_irq[0] */ + BLE_ISOTS_1_IRQn = 84, /* ble_isots_irq[1] */ + BLE_ISOTS_2_IRQn = 85, /* ble_isots_irq[2] */ + BLE_ISOTS_3_IRQn = 86, /* ble_isots_irq[3] */ + BLE_ISOTS_4_IRQn = 87, /* ble_isots_irq[4] */ + BLE_ISOTS_5_IRQn = 88, /* ble_isots_irq[5] */ + BLE_ISOTS_6_IRQn = 89, /* ble_isots_irq[6] */ + BLE_ISOTS_7_IRQn = 90, /* ble_isots_irq[7] */ + PSEQ_IRQn = 91, /* pseq irq */ + PMU_IRQn = 92, /* pmu irq */ + PORT0_ALL_IRQn = 93, /* GPIO port 0 combined interrupt */ + PORT1_ALL_IRQn = 94, /* GPIO port 1 combined interrupt */ + ATLC_IRQn = 95, /* at_lc_irq */ + PORT0_0_IRQn = 96, /* GPIO port 0 bit 0 */ + PORT0_1_IRQn = 97, /* GPIO port 0 bit 1 */ + PORT0_2_IRQn = 98, /* GPIO port 0 bit 2 */ + PORT0_3_IRQn = 99, /* GPIO port 0 bit 3 */ + PORT0_4_IRQn = 100, /* GPIO port 0 bit 4 */ + PORT0_5_IRQn = 101, /* GPIO port 0 bit 5 */ + PORT0_6_IRQn = 102, /* GPIO port 0 bit 6 */ + PORT0_7_IRQn = 103, /* GPIO port 0 bit 7 */ + PORT0_8_IRQn = 104, /* GPIO port 0 bit 8 */ + PORT0_9_IRQn = 105, /* GPIO port 0 bit 9 */ + PORT0_10_IRQn = 106, /* GPIO port 0 bit 10 */ + PORT0_11_IRQn = 107, /* GPIO port 0 bit 11 */ + PORT0_12_IRQn = 108, /* GPIO port 0 bit 12 */ + PORT0_13_IRQn = 109, /* GPIO port 0 bit 13 */ + PORT0_14_IRQn = 110, /* GPIO port 0 bit 14 */ + PORT0_15_IRQn = 111, /* GPIO port 0 bit 15 */ + PORT1_0_IRQn = 112, /* GPIO port 1 bit 0 */ + PORT1_1_IRQn = 113, /* GPIO port 1 bit 1 */ + PORT1_2_IRQn = 114, /* GPIO port 1 bit 2 */ + PORT1_3_IRQn = 115, /* GPIO port 1 bit 3 */ + PORT1_4_IRQn = 116, /* GPIO port 1 bit 4 */ + PORT1_5_IRQn = 117, /* GPIO port 1 bit 5 */ + PORT1_6_IRQn = 118, /* GPIO port 1 bit 6 */ + PORT1_7_IRQn = 119, /* GPIO port 1 bit 7 */ + PORT1_8_IRQn = 120, /* GPIO port 1 bit 8 */ + PORT1_9_IRQn = 121, /* GPIO port 1 bit 9 */ + PORT1_10_IRQn = 122, /* GPIO port 1 bit 10 */ + PORT1_11_IRQn = 123, /* GPIO port 1 bit 11 */ + PORT1_12_IRQn = 124, /* GPIO port 1 bit 12 */ + PORT1_13_IRQn = 125, /* GPIO port 1 bit 13 */ + PORT1_14_IRQn = 126, /* GPIO port 1 bit 14 */ + PORT1_15_IRQn = 127, /* GPIO port 1 bit 15 */ + EXPIRQn_128 = 128, /* RESERVED */ + EXPIRQn_129 = 129, /* RESERVED */ + EXPIRQn_130 = 130, /* RESERVED */ + EXPIRQn_131 = 131, /* RESERVED */ + EXPIRQn_132 = 132, /* RESERVED */ + EXPIRQn_133 = 133, /* RESERVED */ + EXPIRQn_134 = 134, /* RESERVED */ + EXPIRQn_135 = 135, /* RESERVED */ + EXPIRQn_136 = 136, /* RESERVED */ + EXPIRQn_137 = 137, /* RESERVED */ + EXPIRQn_138 = 138, /* RESERVED */ + EXPIRQn_139 = 139, /* RESERVED */ + EXPIRQn_140 = 140, /* RESERVED */ + EXPIRQn_141 = 141, /* RESERVED */ + EXPIRQn_142 = 142, /* RESERVED */ + EXPIRQn_143 = 143, /* RESERVED */ + EXPIRQn_144 = 144, /* RESERVED */ + EXPIRQn_145 = 145, /* RESERVED */ + EXPIRQn_146 = 146, /* RESERVED */ + EXPIRQn_147 = 147, /* RESERVED */ + EXPIRQn_148 = 148, /* RESERVED */ + EXPIRQn_149 = 149, /* RESERVED */ + EXPIRQn_150 = 150, /* RESERVED */ + EXPIRQn_151 = 151, /* RESERVED */ + EXPIRQn_152 = 152, /* RESERVED */ + EXPIRQn_153 = 153, /* RESERVED */ + EXPIRQn_154 = 154, /* RESERVED */ + EXPIRQn_155 = 155, /* RESERVED */ + EXPIRQn_156 = 156, /* RESERVED */ + EXPIRQn_157 = 157, /* RESERVED */ + EXPIRQn_158 = 158, /* RESERVED */ + EXPIRQn_159 = 159, /* RESERVED */ + EXPIRQn_160 = 160, /* RESERVED */ + EXPIRQn_161 = 161, /* RESERVED */ + EXPIRQn_162 = 162, /* RESERVED */ + EXPIRQn_163 = 163, /* RESERVED */ + EXPIRQn_164 = 164, /* RESERVED */ + EXPIRQn_165 = 165, /* RESERVED */ + EXPIRQn_166 = 166, /* RESERVED */ + EXPIRQn_167 = 167, /* RESERVED */ + EXPIRQn_168 = 168, /* RESERVED */ + EXPIRQn_169 = 169, /* RESERVED */ + EXPIRQn_170 = 170, /* RESERVED */ + EXPIRQn_171 = 171, /* RESERVED */ + EXPIRQn_172 = 172, /* RESERVED */ + EXPIRQn_173 = 173, /* RESERVED */ + EXPIRQn_174 = 174, /* RESERVED */ + EXPIRQn_175 = 175, /* RESERVED */ + EXPIRQn_176 = 176, /* RESERVED */ + EXPIRQn_177 = 177, /* RESERVED */ + EXPIRQn_178 = 178, /* RESERVED */ + EXPIRQn_179 = 179, /* RESERVED */ + EXPIRQn_180 = 180, /* RESERVED */ + EXPIRQn_181 = 181, /* RESERVED */ + EXPIRQn_182 = 182, /* RESERVED */ + EXPIRQn_183 = 183, /* RESERVED */ + EXPIRQn_184 = 184, /* RESERVED */ + EXPIRQn_185 = 185, /* RESERVED */ + EXPIRQn_186 = 186, /* RESERVED */ + EXPIRQn_187 = 187, /* RESERVED */ + EXPIRQn_188 = 188, /* RESERVED */ + EXPIRQn_189 = 189, /* RESERVED */ + EXPIRQn_190 = 190, /* RESERVED */ + EXPIRQn_191 = 191, /* RESERVED */ + EXPIRQn_192 = 192, /* RESERVED */ + EXPIRQn_193 = 193, /* RESERVED */ + EXPIRQn_194 = 194, /* RESERVED */ + EXPIRQn_195 = 195, /* RESERVED */ + EXPIRQn_196 = 196, /* RESERVED */ + EXPIRQn_197 = 197, /* RESERVED */ + EXPIRQn_198 = 198, /* RESERVED */ + EXPIRQn_199 = 199, /* RESERVED */ + EXPIRQn_200 = 200, /* RESERVED */ + EXPIRQn_201 = 201, /* RESERVED */ + EXPIRQn_202 = 202, /* RESERVED */ + EXPIRQn_203 = 203, /* RESERVED */ + EXPIRQn_204 = 204, /* RESERVED */ + EXPIRQn_205 = 205, /* RESERVED */ + EXPIRQn_206 = 206, /* RESERVED */ + EXPIRQn_207 = 207, /* RESERVED */ + EXPIRQn_208 = 208, /* RESERVED */ + EXPIRQn_209 = 209, /* RESERVED */ + EXPIRQn_210 = 210, /* RESERVED */ + EXPIRQn_211 = 211, /* RESERVED */ + EXPIRQn_212 = 212, /* RESERVED */ + EXPIRQn_213 = 213, /* RESERVED */ + EXPIRQn_214 = 214, /* RESERVED */ + EXPIRQn_215 = 215, /* RESERVED */ + EXPIRQn_216 = 216, /* RESERVED */ + EXPIRQn_217 = 217, /* RESERVED */ + EXPIRQn_218 = 218, /* RESERVED */ + EXPIRQn_219 = 219, /* RESERVED */ + EXPIRQn_220 = 220, /* RESERVED */ + EXPIRQn_221 = 221, /* RESERVED */ + EXPIRQn_222 = 222, /* RESERVED */ + EXPIRQn_223 = 223, /* RESERVED */ + EXPIRQn_224 = 224, /* RESERVED */ + EXPIRQn_225 = 225, /* RESERVED */ + EXPIRQn_226 = 226, /* RESERVED */ + EXPIRQn_227 = 227, /* RESERVED */ + EXPIRQn_228 = 228, /* RESERVED */ + EXPIRQn_229 = 229, /* RESERVED */ + EXPIRQn_230 = 230, /* RESERVED */ + EXPIRQn_231 = 231, /* RESERVED */ + EXPIRQn_232 = 232, /* RESERVED */ + EXPIRQn_233 = 233, /* RESERVED */ + EXPIRQn_234 = 234, /* RESERVED */ + EXPIRQn_235 = 235, /* RESERVED */ + EXPIRQn_236 = 236, /* RESERVED */ + EXPIRQn_237 = 237, /* RESERVED */ + EXPIRQn_238 = 238, /* RESERVED */ + EXPIRQn_239 = 239, /* RESERVED */ + EXPIRQn_240 = 240, /* RESERVED */ + EXPIRQn_241 = 241, /* RESERVED */ + EXPIRQn_242 = 242, /* RESERVED */ + EXPIRQn_243 = 243, /* RESERVED */ + EXPIRQn_244 = 244, /* RESERVED */ + EXPIRQn_245 = 245, /* RESERVED */ + EXPIRQn_246 = 246, /* RESERVED */ + EXPIRQn_247 = 247, /* RESERVED */ + EXPIRQn_248 = 248, /* RESERVED */ + EXPIRQn_249 = 249, /* RESERVED */ + EXPIRQn_250 = 250, /* RESERVED */ + EXPIRQn_251 = 251, /* RESERVED */ + EXPIRQn_252 = 252, /* RESERVED */ + EXPIRQn_253 = 253, /* RESERVED */ + EXPIRQn_254 = 254, /* RESERVED */ + EXPIRQn_255 = 255, /* RESERVED */ + EXPIRQn_256 = 256, /* RESERVED */ + EXPIRQn_257 = 257, /* RESERVED */ + EXPIRQn_258 = 258, /* RESERVED */ + EXPIRQn_259 = 259, /* RESERVED */ + EXPIRQn_260 = 260, /* RESERVED */ + EXPIRQn_261 = 261, /* RESERVED */ + EXPIRQn_262 = 262, /* RESERVED */ + EXPIRQn_263 = 263, /* RESERVED */ + EXPIRQn_264 = 264, /* RESERVED */ + EXPIRQn_265 = 265, /* RESERVED */ + EXPIRQn_266 = 266, /* RESERVED */ + EXPIRQn_267 = 267, /* RESERVED */ + EXPIRQn_268 = 268, /* RESERVED */ + EXPIRQn_269 = 269, /* RESERVED */ + EXPIRQn_270 = 270, /* RESERVED */ + EXPIRQn_271 = 271, /* RESERVED */ + EXPIRQn_272 = 272, /* RESERVED */ + EXPIRQn_273 = 273, /* RESERVED */ + EXPIRQn_274 = 274, /* RESERVED */ + EXPIRQn_275 = 275, /* RESERVED */ + EXPIRQn_276 = 276, /* RESERVED */ + EXPIRQn_277 = 277, /* RESERVED */ + EXPIRQn_278 = 278, /* RESERVED */ + EXPIRQn_279 = 279, /* RESERVED */ + EXPIRQn_280 = 280, /* RESERVED */ + EXPIRQn_281 = 281, /* RESERVED */ + EXPIRQn_282 = 282, /* RESERVED */ + EXPIRQn_283 = 283, /* RESERVED */ + EXPIRQn_284 = 284, /* RESERVED */ + EXPIRQn_285 = 285, /* RESERVED */ + EXPIRQn_286 = 286, /* RESERVED */ + EXPIRQn_287 = 287, /* RESERVED */ + EXPIRQn_288 = 288, /* RESERVED */ + EXPIRQn_289 = 289, /* RESERVED */ + EXPIRQn_290 = 290, /* RESERVED */ + EXPIRQn_291 = 291, /* RESERVED */ + EXPIRQn_292 = 292, /* RESERVED */ + EXPIRQn_293 = 293, /* RESERVED */ + EXPIRQn_294 = 294, /* RESERVED */ + EXPIRQn_295 = 295, /* RESERVED */ + EXPIRQn_296 = 296, /* RESERVED */ + EXPIRQn_297 = 297, /* RESERVED */ + EXPIRQn_298 = 298, /* RESERVED */ + EXPIRQn_299 = 299, /* RESERVED */ + EXPIRQn_300 = 300, /* RESERVED */ + EXPIRQn_301 = 301, /* RESERVED */ + EXPIRQn_302 = 302, /* RESERVED */ + EXPIRQn_303 = 303, /* RESERVED */ + EXPIRQn_304 = 304, /* RESERVED */ + EXPIRQn_305 = 305, /* RESERVED */ + EXPIRQn_306 = 306, /* RESERVED */ + EXPIRQn_307 = 307, /* RESERVED */ + EXPIRQn_308 = 308, /* RESERVED */ + EXPIRQn_309 = 309, /* RESERVED */ + EXPIRQn_310 = 310, /* RESERVED */ + EXPIRQn_311 = 311, /* RESERVED */ + EXPIRQn_312 = 312, /* RESERVED */ + EXPIRQn_313 = 313, /* RESERVED */ + EXPIRQn_314 = 314, /* RESERVED */ + EXPIRQn_315 = 315, /* RESERVED */ + EXPIRQn_316 = 316, /* RESERVED */ + EXPIRQn_317 = 317, /* RESERVED */ + EXPIRQn_318 = 318, /* RESERVED */ + EXPIRQn_319 = 319, /* RESERVED */ + EXPIRQn_320 = 320, /* RESERVED */ + EXPIRQn_321 = 321, /* RESERVED */ + EXPIRQn_322 = 322, /* RESERVED */ + EXPIRQn_323 = 323, /* RESERVED */ + EXPIRQn_324 = 324, /* RESERVED */ + EXPIRQn_325 = 325, /* RESERVED */ + EXPIRQn_326 = 326, /* RESERVED */ + EXPIRQn_327 = 327, /* RESERVED */ + EXPIRQn_328 = 328, /* RESERVED */ + EXPIRQn_329 = 329, /* RESERVED */ + EXPIRQn_330 = 330, /* RESERVED */ + EXPIRQn_331 = 331, /* RESERVED */ + EXPIRQn_332 = 332, /* RESERVED */ + EXPIRQn_333 = 333, /* RESERVED */ + EXPIRQn_334 = 334, /* RESERVED */ + EXPIRQn_335 = 335, /* RESERVED */ + EXPIRQn_336 = 336, /* RESERVED */ + EXPIRQn_337 = 337, /* RESERVED */ + EXPIRQn_338 = 338, /* RESERVED */ + EXPIRQn_339 = 339, /* RESERVED */ + EXPIRQn_340 = 340, /* RESERVED */ + EXPIRQn_341 = 341, /* RESERVED */ + EXPIRQn_342 = 342, /* RESERVED */ + EXPIRQn_343 = 343, /* RESERVED */ + EXPIRQn_344 = 344, /* RESERVED */ + EXPIRQn_345 = 345, /* RESERVED */ + EXPIRQn_346 = 346, /* RESERVED */ + EXPIRQn_347 = 347, /* RESERVED */ + EXPIRQn_348 = 348, /* RESERVED */ + EXPIRQn_349 = 349, /* RESERVED */ + EXPIRQn_350 = 350, /* RESERVED */ + EXPIRQn_351 = 351, /* RESERVED */ + EXPIRQn_352 = 352, /* RESERVED */ + EXPIRQn_353 = 353, /* RESERVED */ + EXPIRQn_354 = 354, /* RESERVED */ + EXPIRQn_355 = 355, /* RESERVED */ + EXPIRQn_356 = 356, /* RESERVED */ + EXPIRQn_357 = 357, /* RESERVED */ + EXPIRQn_358 = 358, /* RESERVED */ + EXPIRQn_359 = 359, /* RESERVED */ + EXPIRQn_360 = 360, /* RESERVED */ + EXPIRQn_361 = 361, /* RESERVED */ + EXPIRQn_362 = 362, /* RESERVED */ + EXPIRQn_363 = 363, /* RESERVED */ + EXPIRQn_364 = 364, /* RESERVED */ + EXPIRQn_365 = 365, /* RESERVED */ + EXPIRQn_366 = 366, /* RESERVED */ + EXPIRQn_367 = 367, /* RESERVED */ + EXPIRQn_368 = 368, /* RESERVED */ + EXPIRQn_369 = 369, /* RESERVED */ + EXPIRQn_370 = 370, /* RESERVED */ + EXPIRQn_371 = 371, /* RESERVED */ + EXPIRQn_372 = 372, /* RESERVED */ + EXPIRQn_373 = 373, /* RESERVED */ + EXPIRQn_374 = 374, /* RESERVED */ + EXPIRQn_375 = 375, /* RESERVED */ + EXPIRQn_376 = 376, /* RESERVED */ + EXPIRQn_377 = 377, /* RESERVED */ + EXPIRQn_378 = 378, /* RESERVED */ + EXPIRQn_379 = 379, /* RESERVED */ + EXPIRQn_380 = 380, /* RESERVED */ + EXPIRQn_381 = 381, /* RESERVED */ + EXPIRQn_382 = 382, /* RESERVED */ + EXPIRQn_383 = 383, /* RESERVED */ + EXPIRQn_384 = 384, /* RESERVED */ + EXPIRQn_385 = 385, /* RESERVED */ + EXPIRQn_386 = 386, /* RESERVED */ + EXPIRQn_387 = 387, /* RESERVED */ + EXPIRQn_388 = 388, /* RESERVED */ + EXPIRQn_389 = 389, /* RESERVED */ + EXPIRQn_390 = 390, /* RESERVED */ + EXPIRQn_391 = 391, /* RESERVED */ + EXPIRQn_392 = 392, /* RESERVED */ + EXPIRQn_393 = 393, /* RESERVED */ + EXPIRQn_394 = 394, /* RESERVED */ + EXPIRQn_395 = 395, /* RESERVED */ + EXPIRQn_396 = 396, /* RESERVED */ + EXPIRQn_397 = 397, /* RESERVED */ + EXPIRQn_398 = 398, /* RESERVED */ + EXPIRQn_399 = 399, /* RESERVED */ + EXPIRQn_400 = 400, /* RESERVED */ + EXPIRQn_401 = 401, /* RESERVED */ + EXPIRQn_402 = 402, /* RESERVED */ + EXPIRQn_403 = 403, /* RESERVED */ + EXPIRQn_404 = 404, /* RESERVED */ + EXPIRQn_405 = 405, /* RESERVED */ + EXPIRQn_406 = 406, /* RESERVED */ + EXPIRQn_407 = 407, /* RESERVED */ + EXPIRQn_408 = 408, /* RESERVED */ + EXPIRQn_409 = 409, /* RESERVED */ + EXPIRQn_410 = 410, /* RESERVED */ + EXPIRQn_411 = 411, /* RESERVED */ + EXPIRQn_412 = 412, /* RESERVED */ + EXPIRQn_413 = 413, /* RESERVED */ + EXPIRQn_414 = 414, /* RESERVED */ + EXPIRQn_415 = 415, /* RESERVED */ + EXPIRQn_416 = 416, /* RESERVED */ + EXPIRQn_417 = 417, /* RESERVED */ + EXPIRQn_418 = 418, /* RESERVED */ + EXPIRQn_419 = 419, /* RESERVED */ + EXPIRQn_420 = 420, /* RESERVED */ + EXPIRQn_421 = 421, /* RESERVED */ + EXPIRQn_422 = 422, /* RESERVED */ + EXPIRQn_423 = 423, /* RESERVED */ + EXPIRQn_424 = 424, /* RESERVED */ + EXPIRQn_425 = 425, /* RESERVED */ + EXPIRQn_426 = 426, /* RESERVED */ + EXPIRQn_427 = 427, /* RESERVED */ + EXPIRQn_428 = 428, /* RESERVED */ + EXPIRQn_429 = 429, /* RESERVED */ + EXPIRQn_430 = 430, /* RESERVED */ + EXPIRQn_431 = 431, /* RESERVED */ + EXPIRQn_432 = 432, /* RESERVED */ + EXPIRQn_433 = 433, /* RESERVED */ + EXPIRQn_434 = 434, /* RESERVED */ + EXPIRQn_435 = 435, /* RESERVED */ + EXPIRQn_436 = 436, /* RESERVED */ + EXPIRQn_437 = 437, /* RESERVED */ + EXPIRQn_438 = 438, /* RESERVED */ + EXPIRQn_439 = 439, /* RESERVED */ + EXPIRQn_440 = 440, /* RESERVED */ + EXPIRQn_441 = 441, /* RESERVED */ + EXPIRQn_442 = 442, /* RESERVED */ + EXPIRQn_443 = 443, /* RESERVED */ + EXPIRQn_444 = 444, /* RESERVED */ + EXPIRQn_445 = 445, /* RESERVED */ + EXPIRQn_446 = 446, /* RESERVED */ + EXPIRQn_447 = 447, /* RESERVED */ + EXPIRQn_448 = 448 /* RESERVED */ +} IRQn_Type; + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of Core Peripherals ----------------------------------- */ +#define __ARMv8MBL_REV 0x0000U /* Core revision r0p0 */ +#define __SAUREGION_PRESENT 1U /* SAU regions are present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ + +#include "core_armv8mml.h" /* Processor and core peripherals */ +#include "system_ARMv8MBL.h" /* System Header */ + + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/*----------------------------- Timer (TIMER) -------------------------------*/ +typedef struct +{ + __IOM uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ + __IOM uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ + union { + __IM uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __OM uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + +} CMSDK_TIMER_TypeDef; + +/* CMSDK_TIMER CTRL Register Definitions */ +#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */ +#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01UL << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */ +#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01UL << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */ +#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01UL << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */ + +#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */ +#define CMSDK_TIMER_CTRL_EN_Msk (0x01UL /*<< CMSDK_TIMER_CTRL_EN_Pos*/) /* CMSDK_TIMER CTRL: EN Mask */ + +/* CMSDK_TIMER VAL Register Definitions */ +#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */ +#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFUL /*<< CMSDK_TIMER_VAL_CURRENT_Pos*/) /* CMSDK_TIMER VALUE: CURRENT Mask */ + +/* CMSDK_TIMER RELOAD Register Definitions */ +#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */ +#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFUL /*<< CMSDK_TIMER_RELOAD_VAL_Pos*/) /* CMSDK_TIMER RELOAD: RELOAD Mask */ + +/* CMSDK_TIMER INTSTATUS Register Definitions */ +#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */ +#define CMSDK_TIMER_INTSTATUS_Msk (0x01UL /*<< CMSDK_TIMER_INTSTATUS_Pos*/) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */ + +/* CMSDK_TIMER INTCLEAR Register Definitions */ +#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */ +#define CMSDK_TIMER_INTCLEAR_Msk (0x01UL /*<< CMSDK_TIMER_INTCLEAR_Pos*/) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */ + + +/*------------- Timer (TIM) --------------------------------------------------*/ +typedef struct +{ + __IOM uint32_t T1LOAD; /* Offset: 0x000 (R/W) Timer 1 Load */ + __IM uint32_t T1VALUE; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ + __IOM uint32_t T1CTRL; /* Offset: 0x008 (R/W) Timer 1 Control */ + __OM uint32_t T1INTCLR; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ + __IM uint32_t T1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ + __IM uint32_t T1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ + __IOM uint32_t T1BGLOAD; /* Offset: 0x018 (R/W) Background Load Register */ + uint32_t RESERVED0; + __IOM uint32_t T2LOAD; /* Offset: 0x020 (R/W) Timer 2 Load */ + __IM uint32_t T2VALUE; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ + __IOM uint32_t T2CTRL; /* Offset: 0x028 (R/W) Timer 2 Control */ + __OM uint32_t T2INTCLR; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ + __IM uint32_t T2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ + __IM uint32_t T2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ + __IOM uint32_t T2BGLOAD; /* Offset: 0x038 (R/W) Background Load Register */ + uint32_t RESERVED1[945]; + __IOM uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ + __OM uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ +} CMSDK_DUALTIMER_BOTH_TypeDef; + + +typedef struct +{ + __IOM uint32_t LOAD; /* Offset: 0x000 (R/W) Timer Load */ + __IM uint32_t VALUE; /* Offset: 0x000 (R/W) Timer Counter Current Value */ + __IOM uint32_t CTRL; /* Offset: 0x000 (R/W) Timer Control */ + __OM uint32_t INTCLR; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ + __IM uint32_t RIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ + __IM uint32_t MIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ + __IOM uint32_t BGLOAD; /* Offset: 0x000 (R/W) Background Load Register */ +} CMSDK_DUALTIMER_SINGLE_TypeDef; + +/* CMSDK_DUALTIMER_SINGLE LOAD Register Definitions */ +#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ +#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_LOAD_Pos*/) /* CMSDK_DUALTIMER LOAD: LOAD Mask */ + +/* CMSDK_DUALTIMER_SINGLE VALUE Register Definitions */ +#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */ +#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_VALUE_Pos*/) /* CMSDK_DUALTIMER VALUE: VALUE Mask */ + +/* CMSDK_DUALTIMER_SINGLE CTRL Register Definitions */ +#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3UL << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1UL /*<< CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos*/) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +/* CMSDK_DUALTIMER_SINGLE INTCLR Register Definitions */ +#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER_INTCLR_Msk (0x1UL /*<< CMSDK_DUALTIMER_INTCLR_Pos*/) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */ + +/* CMSDK_DUALTIMER_SINGLE RIS Register Definitions */ +#define CMSDK_DUALTIMER_RIS_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER_RIS_Msk (0x1UL /*<< CMSDK_DUALTIMER_RAWINTSTAT_Pos*/) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */ + +/* CMSDK_DUALTIMER_SINGLE MIS Register Definitions */ +#define CMSDK_DUALTIMER_MIS_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER_MIS_Msk (0x1UL /*<< CMSDK_DUALTIMER_MASKINTSTAT_Pos*/) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */ + +/* CMSDK_DUALTIMER_SINGLE BGLOAD Register Definitions */ +#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_BGLOAD_Pos*/) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */ + + +/*-------------------- General Purpose Input Output (GPIO) -------------------*/ +typedef struct +{ + __IOM uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ + __IOM uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ + __IO uint32_t INENSET; /* Offset: 0x008 (R/W) Input Enable Set Register (R/W) */ + __IO uint32_t INENCLR; /* Offset: 0x00C (R/W) Input Enable clear Register (R/W) */ + __IOM uint32_t OUTENSET; /* Offset: 0x010 (R/W) Output Enable Set Register */ + __IOM uint32_t OUTENCLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ + __IOM uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ + __IOM uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ + __IOM uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ + __IOM uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ + __IOM uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ + __IOM uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ + __IOM uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ + __IOM uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ + union { + __IM uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ + __OM uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ + }; + uint32_t RESERVED0[8]; /* Offset: ( /W) Interrupt Clear Register */ + __IO uint32_t PUENSET; /* Offset: 0x05C PU Enable Set Register (R/W) */ + __IO uint32_t PUENCLR; /* Offset: 0x060 PU Enable clear Register (R/W) */ + __IO uint32_t PDENSET; /* Offset: 0x064 PD Enable Set Register (R/W) */ + __IO uint32_t PDENCLR; /* Offset: 0x068 PD Enable clear Register (R/W) */ + uint32_t RESERVED1[229]; + __IOM uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ + __IOM uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ +} CMSDK_GPIO_TypeDef; + +/* CMSDK_GPIO DATA Register Definitions */ +#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ +#define CMSDK_GPIO_DATA_Msk (0xFFFFUL /*<< CMSDK_GPIO_DATA_Pos*/) /* CMSDK_GPIO DATA: DATA Mask */ + +/* CMSDK_GPIO DATAOUT Register Definitions */ +#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */ +#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFUL /*<< CMSDK_GPIO_DATAOUT_Pos*/) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */ + +/* CMSDK_GPIO PUENSET Register Definitions */ +#define CMSDK_GPIO_PUENSET_Pos 0 /* CMSDK_GPIO PUEN: PUEN Position */ +#define CMSDK_GPIO_PUENSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_PUEN_Pos*/) /* CMSDK_GPIO PUEN: PUEN Mask */ + +/* CMSDK_GPIO PUENCLR Register Definitions */ +#define CMSDK_GPIO_PUENCLR_Pos 0 /* CMSDK_GPIO PUEN: PUEN Position */ +#define CMSDK_GPIO_PUENCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_PUEN_Pos*/) /* CMSDK_GPIO PUEN: PUEN Mask */ + +/* CMSDK_GPIO INENSET Register Definitions */ +#define CMSDK_GPIO_INENSET_Pos 0 /* CMSDK_GPIO INEN: INEN Position */ +#define CMSDK_GPIO_INENSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_INEN_Pos*/) /* CMSDK_GPIO INEN: INEN Mask */ + +/* CMSDK_GPIO INENCLR Register Definitions */ +#define CMSDK_GPIO_INENCLR_Pos 0 /* CMSDK_GPIO INEN: INEN Position */ +#define CMSDK_GPIO_INENCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_INEN_Pos*/) /* CMSDK_GPIO INEN: INEN Mask */ + +/* CMSDK_GPIO OUTENSET Register Definitions */ +#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_OUTEN_Pos*/) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +/* CMSDK_GPIO OUTENCLR Register Definitions */ +#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_OUTEN_Pos*/) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +/* CMSDK_GPIO ALTFUNCSET Register Definitions */ +#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_ALTFUNC_Pos*/) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +/* CMSDK_GPIO ALTFUNCCLR Register Definitions */ +#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_ALTFUNC_Pos*/) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +/* CMSDK_GPIO INTENSET Register Definitions */ +#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTEN_Pos*/) /* CMSDK_GPIO INTEN: INTEN Mask */ + +/* CMSDK_GPIO INTENCLR Register Definitions */ +#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTEN_Pos*/) /* CMSDK_GPIO INTEN: INTEN Mask */ + +/* CMSDK_GPIO INTTYPESET Register Definitions */ +#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTTYPE_Pos*/) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +/* CMSDK_GPIO INTTYPECLR Register Definitions */ +#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTTYPE_Pos*/) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +/* CMSDK_GPIO INTPOLSET Register Definitions */ +#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTPOL_Pos*/) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +/* CMSDK_GPIO INTPOLCLR Register Definitions */ +#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTPOL_Pos*/) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +/* CMSDK_GPIO INTCLEAR Register Definitions */ +#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */ +#define CMSDK_GPIO_INTCLEAR_Msk (0xFFUL /*<< CMSDK_GPIO_INTSTATUS_Pos*/) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */ + +/* CMSDK_GPIO INTCLEAR Register Definitions */ +#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */ +#define CMSDK_GPIO_INTCLEAR_Msk (0xFFUL /*<< CMSDK_GPIO_INTCLEAR_Pos*/) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */ + +/* CMSDK_GPIO MASKLOWBYTE Register Definitions */ +#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */ +#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFUL /*<< CMSDK_GPIO_MASKLOWBYTE_Pos*/) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */ + +/* CMSDK_GPIO MASKHIGHBYTE Register Definitions */ +#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */ +#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00UL /*<< CMSDK_GPIO_MASKHIGHBYTE_Pos*/) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */ + + +/*---------------- SYS_CTRL_REG_SSE200 ----------------*/ +typedef struct +{ +__IM uint32_t SECDBGSTAT; /* Offset: 0x0 (read-only) SECDBGSTAT Register */ +__OM uint32_t SECDBGSET; /* Offset: 0x4 (write-only) SECDBGSET Register */ +__OM uint32_t SECDBGCLR; /* Offset: 0x8 (write-only) SECDBGCLR Register */ +__IOM uint32_t SCSECCTRL; /* Offset: 0xC (read-write) SCSECCTRL Register */ +__IOM uint32_t FCLK_DIV; /* Offset: 0x10 (read-write) FCLK_DIV Register */ +__IOM uint32_t SYSCLK_DIV; /* Offset: 0x14 (read-write) SYSCLK_DIV Register */ +__IOM uint32_t CLOCK_FORCE; /* Offset: 0x18 (read-write) CLOCK_FORCE Register */ + uint32_t RESERVED0[57]; +__IOM uint32_t RESET_SYNDROME; /* Offset: 0x100 (read-write) RESET_SYNDROME Register */ +__IOM uint32_t RESET_MASK; /* Offset: 0x104 (read-write) RESET_MASK Register */ +__OM uint32_t SWRESET; /* Offset: 0x108 (write-only) SWRESET Register */ +__IOM uint32_t GRETREG; /* Offset: 0x10C (read-write) GRETREG Register */ +__IOM uint32_t INITSVTOR0; /* Offset: 0x110 (read-write) INITSVTOR0 Register */ +__IOM uint32_t INITSVTOR1; /* Offset: 0x114 (read-write) INITSVTOR1 Register */ +__IOM uint32_t CPUWAIT; /* Offset: 0x118 (read-write) CPUWAIT Register */ +__IOM uint32_t NMI_ENABLE; /* Offset: 0x11C (read-write) NMI_ENABLE Register */ +__IOM uint32_t WICCTRL; /* Offset: 0x120 (read-write) WICCTRL Register */ +__IOM uint32_t EWCTRL; /* Offset: 0x124 (read-write) EWCTRL Register */ + uint32_t RESERVED1[54]; +__IOM uint32_t PDCM_PD_SYS_SENSE; /* Offset: 0x200 (read-write) PDCM_PD_SYS_SENSE Register */ + uint32_t RESERVED4[2]; +__IOM uint32_t PDCM_PD_SRAM0_SENSE; /* Offset: 0x20C (read-write) PDCM_PD_SRAM0_SENSE Register */ +__IOM uint32_t PDCM_PD_SRAM1_SENSE; /* Offset: 0x210 (read-write) PDCM_PD_SRAM1_SENSE Register */ +__IOM uint32_t PDCM_PD_SRAM2_SENSE; /* Offset: 0x214 (read-write) PDCM_PD_SRAM2_SENSE Register */ +__IOM uint32_t PDCM_PD_SRAM3_SENSE; /* Offset: 0x218 (read-write) PDCM_PD_SRAM3_SENSE Register */ + uint32_t RESERVED2[877]; +__IM uint32_t PIDR4; /* Offset: 0xFD0 (read-only) PIDR4 Register */ + uint32_t RESERVED3[3]; +__IM uint32_t PIDR0; /* Offset: 0xFE0 (read-only) PIDR0 Register */ +__IM uint32_t PIDR1; /* Offset: 0xFE4 (read-only) PIDR1 Register */ +__IM uint32_t PIDR2; /* Offset: 0xFE8 (read-only) PIDR2 Register */ +__IM uint32_t PIDR3; /* Offset: 0xFEC (read-only) PIDR3 Register */ +__IM uint32_t CIDR0; /* Offset: 0xFF0 (read-only) CIDR0 Register */ +__IM uint32_t CIDR1; /* Offset: 0xFF4 (read-only) CIDR1 Register */ +__IM uint32_t CIDR2; /* Offset: 0xFF8 (read-only) CIDR2 Register */ +__IM uint32_t CIDR3; /* Offset: 0xFFC (read-only) CIDR3 Register */ +}SYS_CTRL_REG_SSE200_TypeDef; + +/* SYS_CTRL_REG_SSE200 SECDBGSTAT Register Definitions */ +#define SYS_CTRL_REG_SSE200_SECDBGSTAT_LLCDBGEN_SEL_STATUS_Pos 9 /* SYS_CTRL_REG_SSE200 SECDBGSTAT: LLCDBGEN_SEL_STATUS Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGSTAT_LLCDBGEN_SEL_STATUS_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGSTAT_LLCDBGEN_SEL_STATUS_Pos) /* SYS_CTRL_REG_SSE200 SECDBGSTAT: LLCDBGEN_SEL_STATUS Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGSTAT_LLCDBGEN_STATUS_Pos 8 /* SYS_CTRL_REG_SSE200 SECDBGSTAT: LLCDBGEN_STATUS Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGSTAT_LLCDBGEN_STATUS_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGSTAT_LLCDBGEN_STATUS_Pos) /* SYS_CTRL_REG_SSE200 SECDBGSTAT: LLCDBGEN_STATUS Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGSTAT_SPNIDEN_SEL_STATUS_Pos 7 /* SYS_CTRL_REG_SSE200 SECDBGSTAT: SPNIDEN_SEL_STATUS Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGSTAT_SPNIDEN_SEL_STATUS_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGSTAT_SPNIDEN_SEL_STATUS_Pos) /* SYS_CTRL_REG_SSE200 SECDBGSTAT: SPNIDEN_SEL_STATUS Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGSTAT_SPNIDEN_STATUS_Pos 6 /* SYS_CTRL_REG_SSE200 SECDBGSTAT: SPNIDEN_STATUS Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGSTAT_SPNIDEN_STATUS_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGSTAT_SPNIDEN_STATUS_Pos) /* SYS_CTRL_REG_SSE200 SECDBGSTAT: SPNIDEN_STATUS Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGSTAT_SPIDEN_SEL_STATUS_Pos 5 /* SYS_CTRL_REG_SSE200 SECDBGSTAT: SPIDEN_SEL_STATUS Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGSTAT_SPIDEN_SEL_STATUS_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGSTAT_SPIDEN_SEL_STATUS_Pos) /* SYS_CTRL_REG_SSE200 SECDBGSTAT: SPIDEN_SEL_STATUS Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGSTAT_SPIDEN_STATUS_Pos 4 /* SYS_CTRL_REG_SSE200 SECDBGSTAT: SPIDEN_STATUS Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGSTAT_SPIDEN_STATUS_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGSTAT_SPIDEN_STATUS_Pos) /* SYS_CTRL_REG_SSE200 SECDBGSTAT: SPIDEN_STATUS Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGSTAT_NIDEN_SEL_STATUS_Pos 3 /* SYS_CTRL_REG_SSE200 SECDBGSTAT: NIDEN_SEL_STATUS Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGSTAT_NIDEN_SEL_STATUS_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGSTAT_NIDEN_SEL_STATUS_Pos) /* SYS_CTRL_REG_SSE200 SECDBGSTAT: NIDEN_SEL_STATUS Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGSTAT_NIDEN_STATUS_Pos 2 /* SYS_CTRL_REG_SSE200 SECDBGSTAT: NIDEN_STATUS Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGSTAT_NIDEN_STATUS_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGSTAT_NIDEN_STATUS_Pos) /* SYS_CTRL_REG_SSE200 SECDBGSTAT: NIDEN_STATUS Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGSTAT_DBGEN_SEL_STATUS_Pos 1 /* SYS_CTRL_REG_SSE200 SECDBGSTAT: DBGEN_SEL_STATUS Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGSTAT_DBGEN_SEL_STATUS_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGSTAT_DBGEN_SEL_STATUS_Pos) /* SYS_CTRL_REG_SSE200 SECDBGSTAT: DBGEN_SEL_STATUS Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGSTAT_DBGEN_STATUS_Pos 0 /* SYS_CTRL_REG_SSE200 SECDBGSTAT: DBGEN_STATUS Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGSTAT_DBGEN_STATUS_Msk (0x1UL /*<< SYS_CTRL_REG_SSE200_SECDBGSTAT_DBGEN_STATUS_Pos*/) /* SYS_CTRL_REG_SSE200 SECDBGSTAT: DBGEN_STATUS Mask */ + +/* SYS_CTRL_REG_SSE200 SECDBGSET Register Definitions */ +#define SYS_CTRL_REG_SSE200_SECDBGSET_LLCDBGEN_SEL_SET_Pos 9 /* SYS_CTRL_REG_SSE200 SECDBGSET: LLCDBGEN_SEL_SET Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGSET_LLCDBGEN_SEL_SET_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGSET_LLCDBGEN_SEL_SET_Pos) /* SYS_CTRL_REG_SSE200 SECDBGSET: LLCDBGEN_SEL_SET Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGSET_LLCDBGEN_SET_Pos 8 /* SYS_CTRL_REG_SSE200 SECDBGSET: LLCDBGEN_SET Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGSET_LLCDBGEN_SET_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGSET_LLCDBGEN_SET_Pos) /* SYS_CTRL_REG_SSE200 SECDBGSET: LLCDBGEN_SET Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGSET_SPNIDEN_SEL_SET_Pos 7 /* SYS_CTRL_REG_SSE200 SECDBGSET: SPNIDEN_SEL_SET Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGSET_SPNIDEN_SEL_SET_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGSET_SPNIDEN_SEL_SET_Pos) /* SYS_CTRL_REG_SSE200 SECDBGSET: SPNIDEN_SEL_SET Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGSET_SPNIDEN_SET_Pos 6 /* SYS_CTRL_REG_SSE200 SECDBGSET: SPNIDEN_SET Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGSET_SPNIDEN_SET_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGSET_SPNIDEN_SET_Pos) /* SYS_CTRL_REG_SSE200 SECDBGSET: SPNIDEN_SET Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGSET_SPIDEN_SEL_SET_Pos 5 /* SYS_CTRL_REG_SSE200 SECDBGSET: SPIDEN_SEL_SET Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGSET_SPIDEN_SEL_SET_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGSET_SPIDEN_SEL_SET_Pos) /* SYS_CTRL_REG_SSE200 SECDBGSET: SPIDEN_SEL_SET Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGSET_SPIDEN_SET_Pos 4 /* SYS_CTRL_REG_SSE200 SECDBGSET: SPIDEN_SET Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGSET_SPIDEN_SET_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGSET_SPIDEN_SET_Pos) /* SYS_CTRL_REG_SSE200 SECDBGSET: SPIDEN_SET Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGSET_NIDEN_SEL_SET_Pos 3 /* SYS_CTRL_REG_SSE200 SECDBGSET: NIDEN_SEL_SET Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGSET_NIDEN_SEL_SET_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGSET_NIDEN_SEL_SET_Pos) /* SYS_CTRL_REG_SSE200 SECDBGSET: NIDEN_SEL_SET Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGSET_NIDEN_SET_Pos 2 /* SYS_CTRL_REG_SSE200 SECDBGSET: NIDEN_SET Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGSET_NIDEN_SET_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGSET_NIDEN_SET_Pos) /* SYS_CTRL_REG_SSE200 SECDBGSET: NIDEN_SET Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGSET_DBGEN_SEL_SET_Pos 1 /* SYS_CTRL_REG_SSE200 SECDBGSET: DBGEN_SEL_SET Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGSET_DBGEN_SEL_SET_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGSET_DBGEN_SEL_SET_Pos) /* SYS_CTRL_REG_SSE200 SECDBGSET: DBGEN_SEL_SET Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGSET_DBGEN_SET_Pos 0 /* SYS_CTRL_REG_SSE200 SECDBGSET: DBGEN_SET Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGSET_DBGEN_SET_Msk (0x1UL /*<< SYS_CTRL_REG_SSE200_SECDBGSET_DBGEN_SET_Pos*/) /* SYS_CTRL_REG_SSE200 SECDBGSET: DBGEN_SET Mask */ + +/* SYS_CTRL_REG_SSE200 SECDBGCLR Register Definitions */ +#define SYS_CTRL_REG_SSE200_SECDBGCLR_LLCDBGEN_SEL_CLR_Pos 9 /* SYS_CTRL_REG_SSE200 SECDBGCLR: LLCDBGEN_SEL_CLR Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGCLR_LLCDBGEN_SEL_CLR_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGCLR_LLCDBGEN_SEL_CLR_Pos) /* SYS_CTRL_REG_SSE200 SECDBGCLR: LLCDBGEN_SEL_CLR Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGCLR_LLCDBGEN_CLR_Pos 8 /* SYS_CTRL_REG_SSE200 SECDBGCLR: LLCDBGEN_CLR Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGCLR_LLCDBGEN_CLR_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGCLR_LLCDBGEN_CLR_Pos) /* SYS_CTRL_REG_SSE200 SECDBGCLR: LLCDBGEN_CLR Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGCLR_SPNIDEN_SEL_CLR_Pos 7 /* SYS_CTRL_REG_SSE200 SECDBGCLR: SPNIDEN_SEL_CLR Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGCLR_SPNIDEN_SEL_CLR_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGCLR_SPNIDEN_SEL_CLR_Pos) /* SYS_CTRL_REG_SSE200 SECDBGCLR: SPNIDEN_SEL_CLR Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGCLR_SPNIDEN_CLR_Pos 6 /* SYS_CTRL_REG_SSE200 SECDBGCLR: SPNIDEN_CLR Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGCLR_SPNIDEN_CLR_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGCLR_SPNIDEN_CLR_Pos) /* SYS_CTRL_REG_SSE200 SECDBGCLR: SPNIDEN_CLR Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGCLR_SPIDEN_SEL_CLR_Pos 5 /* SYS_CTRL_REG_SSE200 SECDBGCLR: SPIDEN_SEL_CLR Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGCLR_SPIDEN_SEL_CLR_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGCLR_SPIDEN_SEL_CLR_Pos) /* SYS_CTRL_REG_SSE200 SECDBGCLR: SPIDEN_SEL_CLR Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGCLR_SPIDEN_CLR_Pos 4 /* SYS_CTRL_REG_SSE200 SECDBGCLR: SPIDEN_CLR Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGCLR_SPIDEN_CLR_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGCLR_SPIDEN_CLR_Pos) /* SYS_CTRL_REG_SSE200 SECDBGCLR: SPIDEN_CLR Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGCLR_NIDEN_SEL_CLR_Pos 3 /* SYS_CTRL_REG_SSE200 SECDBGCLR: NIDEN_SEL_CLR Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGCLR_NIDEN_SEL_CLR_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGCLR_NIDEN_SEL_CLR_Pos) /* SYS_CTRL_REG_SSE200 SECDBGCLR: NIDEN_SEL_CLR Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGCLR_NIDEN_CLR_Pos 2 /* SYS_CTRL_REG_SSE200 SECDBGCLR: NIDEN_CLR Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGCLR_NIDEN_CLR_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGCLR_NIDEN_CLR_Pos) /* SYS_CTRL_REG_SSE200 SECDBGCLR: NIDEN_CLR Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGCLR_DBGEN_SEL_CLR_Pos 1 /* SYS_CTRL_REG_SSE200 SECDBGCLR: DBGEN_SEL_CLR Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGCLR_DBGEN_SEL_CLR_Msk (0x1UL << SYS_CTRL_REG_SSE200_SECDBGCLR_DBGEN_SEL_CLR_Pos) /* SYS_CTRL_REG_SSE200 SECDBGCLR: DBGEN_SEL_CLR Mask */ + +#define SYS_CTRL_REG_SSE200_SECDBGCLR_DBGEN_CLR_Pos 0 /* SYS_CTRL_REG_SSE200 SECDBGCLR: DBGEN_CLR Positions */ +#define SYS_CTRL_REG_SSE200_SECDBGCLR_DBGEN_CLR_Msk (0x1UL /*<< SYS_CTRL_REG_SSE200_SECDBGCLR_DBGEN_CLR_Pos*/) /* SYS_CTRL_REG_SSE200 SECDBGCLR: DBGEN_CLR Mask */ + +/* SYS_CTRL_REG_SSE200 SCSECCTRL Register Definitions */ +#define SYS_CTRL_REG_SSE200_SCSECCTRL_CERTREADENABLED_Pos 17 /* SYS_CTRL_REG_SSE200 SCSECCTRL: CERTREADENABLED Positions */ +#define SYS_CTRL_REG_SSE200_SCSECCTRL_CERTREADENABLED_Msk (0x1UL << SYS_CTRL_REG_SSE200_SCSECCTRL_CERTREADENABLED_Pos) /* SYS_CTRL_REG_SSE200 SCSECCTRL: CERTREADENABLED Mask */ + +#define SYS_CTRL_REG_SSE200_SCSECCTRL_CERTDISABLED_Pos 16 /* SYS_CTRL_REG_SSE200 SCSECCTRL: CERTDISABLED Positions */ +#define SYS_CTRL_REG_SSE200_SCSECCTRL_CERTDISABLED_Msk (0x1UL << SYS_CTRL_REG_SSE200_SCSECCTRL_CERTDISABLED_Pos) /* SYS_CTRL_REG_SSE200 SCSECCTRL: CERTDISABLED Mask */ + +#define SYS_CTRL_REG_SSE200_SCSECCTRL_SCSECCFGLOCK_Pos 2 /* SYS_CTRL_REG_SSE200 SCSECCTRL: SCSECCFGLOCK Positions */ +#define SYS_CTRL_REG_SSE200_SCSECCTRL_SCSECCFGLOCK_Msk (0x1UL << SYS_CTRL_REG_SSE200_SCSECCTRL_SCSECCFGLOCK_Pos) /* SYS_CTRL_REG_SSE200 SCSECCTRL: SCSECCFGLOCK Mask */ + +#define SYS_CTRL_REG_SSE200_SCSECCTRL_CERTREADEN_Pos 1 /* SYS_CTRL_REG_SSE200 SCSECCTRL: CERTREADEN Positions */ +#define SYS_CTRL_REG_SSE200_SCSECCTRL_CERTREADEN_Msk (0x1UL << SYS_CTRL_REG_SSE200_SCSECCTRL_CERTREADEN_Pos) /* SYS_CTRL_REG_SSE200 SCSECCTRL: CERTREADEN Mask */ + +#define SYS_CTRL_REG_SSE200_SCSECCTRL_CERTDISABLE_Pos 0 /* SYS_CTRL_REG_SSE200 SCSECCTRL: CERTDISABLE Positions */ +#define SYS_CTRL_REG_SSE200_SCSECCTRL_CERTDISABLE_Msk (0x1UL /*<< SYS_CTRL_REG_SSE200_SCSECCTRL_CERTDISABLE_Pos*/) /* SYS_CTRL_REG_SSE200 SCSECCTRL: CERTDISABLE Mask */ + +/* SYS_CTRL_REG_SSE200 FCLK_DIV Register Definitions */ +#define SYS_CTRL_REG_SSE200_FCLK_DIV_FCLKDIV_CUR_Pos 16 /* SYS_CTRL_REG_SSE200 FCLK_DIV: FCLKDIV_CUR Positions */ +#define SYS_CTRL_REG_SSE200_FCLK_DIV_FCLKDIV_CUR_Msk (0x1FUL << SYS_CTRL_REG_SSE200_FCLK_DIV_FCLKDIV_CUR_Pos) /* SYS_CTRL_REG_SSE200 FCLK_DIV: FCLKDIV_CUR Mask */ + +#define SYS_CTRL_REG_SSE200_FCLK_DIV_FCLKDIV_Pos 0 /* SYS_CTRL_REG_SSE200 FCLK_DIV: FCLKDIV Positions */ +#define SYS_CTRL_REG_SSE200_FCLK_DIV_FCLKDIV_Msk (0x1FUL /*<< SYS_CTRL_REG_SSE200_FCLK_DIV_FCLKDIV_Pos*/) /* SYS_CTRL_REG_SSE200 FCLK_DIV: FCLKDIV Mask */ + +/* SYS_CTRL_REG_SSE200 SYSCLK_DIV Register Definitions */ +#define SYS_CTRL_REG_SSE200_SYSCLK_DIV_SYSCLKDIV_CUR_Pos 16 /* SYS_CTRL_REG_SSE200 SYSCLK_DIV: SYSCLKDIV_CUR Positions */ +#define SYS_CTRL_REG_SSE200_SYSCLK_DIV_SYSCLKDIV_CUR_Msk (0x1FUL << SYS_CTRL_REG_SSE200_SYSCLK_DIV_SYSCLKDIV_CUR_Pos) /* SYS_CTRL_REG_SSE200 SYSCLK_DIV: SYSCLKDIV_CUR Mask */ + +#define SYS_CTRL_REG_SSE200_SYSCLK_DIV_SYSCLKDIV_Pos 0 /* SYS_CTRL_REG_SSE200 SYSCLK_DIV: SYSCLKDIV Positions */ +#define SYS_CTRL_REG_SSE200_SYSCLK_DIV_SYSCLKDIV_Msk (0x1FUL /*<< SYS_CTRL_REG_SSE200_SYSCLK_DIV_SYSCLKDIV_Pos*/) /* SYS_CTRL_REG_SSE200 SYSCLK_DIV: SYSCLKDIV Mask */ + +/* SYS_CTRL_REG_SSE200 CLOCK_FORCE Register Definitions */ +#define SYS_CTRL_REG_SSE200_CLOCK_FORCE_FCLKHINTGATE_ENABLE_Pos 8 /* SYS_CTRL_REG_SSE200 CLOCK_FORCE: FCLKHINTGATE_ENABLE Positions */ +#define SYS_CTRL_REG_SSE200_CLOCK_FORCE_FCLKHINTGATE_ENABLE_Msk (0x1UL << SYS_CTRL_REG_SSE200_CLOCK_FORCE_FCLKHINTGATE_ENABLE_Pos) /* SYS_CTRL_REG_SSE200 CLOCK_FORCE: FCLKHINTGATE_ENABLE Mask */ + +#define SYS_CTRL_REG_SSE200_CLOCK_FORCE_CRYPTOSYSCLK_FORCE_Pos 7 /* SYS_CTRL_REG_SSE200 CLOCK_FORCE: CRYPTOSYSCLK_FORCE Positions */ +#define SYS_CTRL_REG_SSE200_CLOCK_FORCE_CRYPTOSYSCLK_FORCE_Msk (0x1UL << SYS_CTRL_REG_SSE200_CLOCK_FORCE_CRYPTOSYSCLK_FORCE_Pos) /* SYS_CTRL_REG_SSE200 CLOCK_FORCE: CRYPTOSYSCLK_FORCE Mask */ + +#define SYS_CTRL_REG_SSE200_CLOCK_FORCE_CPUFCLK_FORCE_Pos 6 /* SYS_CTRL_REG_SSE200 CLOCK_FORCE: CPUFCLK_FORCE Positions */ +#define SYS_CTRL_REG_SSE200_CLOCK_FORCE_CPUFCLK_FORCE_Msk (0x1UL << SYS_CTRL_REG_SSE200_CLOCK_FORCE_CPUFCLK_FORCE_Pos) /* SYS_CTRL_REG_SSE200 CLOCK_FORCE: CPUFCLK_FORCE Mask */ + +#define SYS_CTRL_REG_SSE200_CLOCK_FORCE_CPUSYSCLK_FORCE_Pos 5 /* SYS_CTRL_REG_SSE200 CLOCK_FORCE: CPUSYSCLK_FORCE Positions */ +#define SYS_CTRL_REG_SSE200_CLOCK_FORCE_CPUSYSCLK_FORCE_Msk (0x1UL << SYS_CTRL_REG_SSE200_CLOCK_FORCE_CPUSYSCLK_FORCE_Pos) /* SYS_CTRL_REG_SSE200 CLOCK_FORCE: CPUSYSCLK_FORCE Mask */ + +#define SYS_CTRL_REG_SSE200_CLOCK_FORCE_SRAMFCLK_FORCE_Pos 4 /* SYS_CTRL_REG_SSE200 CLOCK_FORCE: SRAMFCLK_FORCE Positions */ +#define SYS_CTRL_REG_SSE200_CLOCK_FORCE_SRAMFCLK_FORCE_Msk (0x1UL << SYS_CTRL_REG_SSE200_CLOCK_FORCE_SRAMFCLK_FORCE_Pos) /* SYS_CTRL_REG_SSE200 CLOCK_FORCE: SRAMFCLK_FORCE Mask */ + +#define SYS_CTRL_REG_SSE200_CLOCK_FORCE_SRAMSYSCLK_FORCE_Pos 3 /* SYS_CTRL_REG_SSE200 CLOCK_FORCE: SRAMSYSCLK_FORCE Positions */ +#define SYS_CTRL_REG_SSE200_CLOCK_FORCE_SRAMSYSCLK_FORCE_Msk (0x1UL << SYS_CTRL_REG_SSE200_CLOCK_FORCE_SRAMSYSCLK_FORCE_Pos) /* SYS_CTRL_REG_SSE200 CLOCK_FORCE: SRAMSYSCLK_FORCE Mask */ + +#define SYS_CTRL_REG_SSE200_CLOCK_FORCE_SYSFCLK_FORCE_Pos 2 /* SYS_CTRL_REG_SSE200 CLOCK_FORCE: SYSFCLK_FORCE Positions */ +#define SYS_CTRL_REG_SSE200_CLOCK_FORCE_SYSFCLK_FORCE_Msk (0x1UL << SYS_CTRL_REG_SSE200_CLOCK_FORCE_SYSFCLK_FORCE_Pos) /* SYS_CTRL_REG_SSE200 CLOCK_FORCE: SYSFCLK_FORCE Mask */ + +#define SYS_CTRL_REG_SSE200_CLOCK_FORCE_SYSSYSCLK_FORCE_Pos 1 /* SYS_CTRL_REG_SSE200 CLOCK_FORCE: SYSSYSCLK_FORCE Positions */ +#define SYS_CTRL_REG_SSE200_CLOCK_FORCE_SYSSYSCLK_FORCE_Msk (0x1UL << SYS_CTRL_REG_SSE200_CLOCK_FORCE_SYSSYSCLK_FORCE_Pos) /* SYS_CTRL_REG_SSE200 CLOCK_FORCE: SYSSYSCLK_FORCE Mask */ + +#define SYS_CTRL_REG_SSE200_CLOCK_FORCE_MAINCLK_FORCE_Pos 0 /* SYS_CTRL_REG_SSE200 CLOCK_FORCE: MAINCLK_FORCE Positions */ +#define SYS_CTRL_REG_SSE200_CLOCK_FORCE_MAINCLK_FORCE_Msk (0x1UL /*<< SYS_CTRL_REG_SSE200_CLOCK_FORCE_MAINCLK_FORCE_Pos*/) /* SYS_CTRL_REG_SSE200 CLOCK_FORCE: MAINCLK_FORCE Mask */ + +/* SYS_CTRL_REG_SSE200 RESET_SYNDROME Register Definitions */ +#define SYS_CTRL_REG_SSE200_RESET_SYNDROME_SWRESETREQ_Pos 9 /* SYS_CTRL_REG_SSE200 RESET_SYNDROME: SWRESETREQ Positions */ +#define SYS_CTRL_REG_SSE200_RESET_SYNDROME_SWRESETREQ_Msk (0x1UL << SYS_CTRL_REG_SSE200_RESET_SYNDROME_SWRESETREQ_Pos) /* SYS_CTRL_REG_SSE200 RESET_SYNDROME: SWRESETREQ Mask */ + +#define SYS_CTRL_REG_SSE200_RESET_SYNDROME_RESETREQ_Pos 8 /* SYS_CTRL_REG_SSE200 RESET_SYNDROME: RESETREQ Positions */ +#define SYS_CTRL_REG_SSE200_RESET_SYNDROME_RESETREQ_Msk (0x1UL << SYS_CTRL_REG_SSE200_RESET_SYNDROME_RESETREQ_Pos) /* SYS_CTRL_REG_SSE200 RESET_SYNDROME: RESETREQ Mask */ + +#define SYS_CTRL_REG_SSE200_RESET_SYNDROME_LOCKUP1_Pos 7 /* SYS_CTRL_REG_SSE200 RESET_SYNDROME: LOCKUP1 Positions */ +#define SYS_CTRL_REG_SSE200_RESET_SYNDROME_LOCKUP1_Msk (0x1UL << SYS_CTRL_REG_SSE200_RESET_SYNDROME_LOCKUP1_Pos) /* SYS_CTRL_REG_SSE200 RESET_SYNDROME: LOCKUP1 Mask */ + +#define SYS_CTRL_REG_SSE200_RESET_SYNDROME_LOCKUP0_Pos 6 /* SYS_CTRL_REG_SSE200 RESET_SYNDROME: LOCKUP0 Positions */ +#define SYS_CTRL_REG_SSE200_RESET_SYNDROME_LOCKUP0_Msk (0x1UL << SYS_CTRL_REG_SSE200_RESET_SYNDROME_LOCKUP0_Pos) /* SYS_CTRL_REG_SSE200 RESET_SYNDROME: LOCKUP0 Mask */ + +#define SYS_CTRL_REG_SSE200_RESET_SYNDROME_SYSRSTREQ1_Pos 5 /* SYS_CTRL_REG_SSE200 RESET_SYNDROME: SYSRSTREQ1 Positions */ +#define SYS_CTRL_REG_SSE200_RESET_SYNDROME_SYSRSTREQ1_Msk (0x1UL << SYS_CTRL_REG_SSE200_RESET_SYNDROME_SYSRSTREQ1_Pos) /* SYS_CTRL_REG_SSE200 RESET_SYNDROME: SYSRSTREQ1 Mask */ + +#define SYS_CTRL_REG_SSE200_RESET_SYNDROME_SYSRSTREQ0_Pos 4 /* SYS_CTRL_REG_SSE200 RESET_SYNDROME: SYSRSTREQ0 Positions */ +#define SYS_CTRL_REG_SSE200_RESET_SYNDROME_SYSRSTREQ0_Msk (0x1UL << SYS_CTRL_REG_SSE200_RESET_SYNDROME_SYSRSTREQ0_Pos) /* SYS_CTRL_REG_SSE200 RESET_SYNDROME: SYSRSTREQ0 Mask */ + +#define SYS_CTRL_REG_SSE200_RESET_SYNDROME_S32KWD_Pos 3 /* SYS_CTRL_REG_SSE200 RESET_SYNDROME: S32KWD Positions */ +#define SYS_CTRL_REG_SSE200_RESET_SYNDROME_S32KWD_Msk (0x1UL << SYS_CTRL_REG_SSE200_RESET_SYNDROME_S32KWD_Pos) /* SYS_CTRL_REG_SSE200 RESET_SYNDROME: S32KWD Mask */ + +#define SYS_CTRL_REG_SSE200_RESET_SYNDROME_SWD_Pos 2 /* SYS_CTRL_REG_SSE200 RESET_SYNDROME: SWD Positions */ +#define SYS_CTRL_REG_SSE200_RESET_SYNDROME_SWD_Msk (0x1UL << SYS_CTRL_REG_SSE200_RESET_SYNDROME_SWD_Pos) /* SYS_CTRL_REG_SSE200 RESET_SYNDROME: SWD Mask */ + +#define SYS_CTRL_REG_SSE200_RESET_SYNDROME_NSWD_Pos 1 /* SYS_CTRL_REG_SSE200 RESET_SYNDROME: NSWD Positions */ +#define SYS_CTRL_REG_SSE200_RESET_SYNDROME_NSWD_Msk (0x1UL << SYS_CTRL_REG_SSE200_RESET_SYNDROME_NSWD_Pos) /* SYS_CTRL_REG_SSE200 RESET_SYNDROME: NSWD Mask */ + +#define SYS_CTRL_REG_SSE200_RESET_SYNDROME_PoR_Pos 0 /* SYS_CTRL_REG_SSE200 RESET_SYNDROME: PoR Positions */ +#define SYS_CTRL_REG_SSE200_RESET_SYNDROME_PoR_Msk (0x1UL /*<< SYS_CTRL_REG_SSE200_RESET_SYNDROME_PoR_Pos*/) /* SYS_CTRL_REG_SSE200 RESET_SYNDROME: PoR Mask */ + +/* SYS_CTRL_REG_SSE200 RESET_MASK Register Definitions */ +#define SYS_CTRL_REG_SSE200_RESET_MASK_SYSRSTREQ1_EN_Pos 5 /* SYS_CTRL_REG_SSE200 RESET_MASK: SYSRSTREQ1_EN Positions */ +#define SYS_CTRL_REG_SSE200_RESET_MASK_SYSRSTREQ1_EN_Msk (0x1UL << SYS_CTRL_REG_SSE200_RESET_MASK_SYSRSTREQ1_EN_Pos) /* SYS_CTRL_REG_SSE200 RESET_MASK: SYSRSTREQ1_EN Mask */ + +#define SYS_CTRL_REG_SSE200_RESET_MASK_SYSRSTREQ0_EN_Pos 4 /* SYS_CTRL_REG_SSE200 RESET_MASK: SYSRSTREQ0_EN Positions */ +#define SYS_CTRL_REG_SSE200_RESET_MASK_SYSRSTREQ0_EN_Msk (0x1UL << SYS_CTRL_REG_SSE200_RESET_MASK_SYSRSTREQ0_EN_Pos) /* SYS_CTRL_REG_SSE200 RESET_MASK: SYSRSTREQ0_EN Mask */ + +#define SYS_CTRL_REG_SSE200_RESET_MASK_NSWD_EN_Pos 1 /* SYS_CTRL_REG_SSE200 RESET_MASK: NSWD_EN Positions */ +#define SYS_CTRL_REG_SSE200_RESET_MASK_NSWD_EN_Msk (0x1UL << SYS_CTRL_REG_SSE200_RESET_MASK_NSWD_EN_Pos) /* SYS_CTRL_REG_SSE200 RESET_MASK: NSWD_EN Mask */ + +/* SYS_CTRL_REG_SSE200 SWRESET Register Definitions */ +#define SYS_CTRL_REG_SSE200_SWRESET_SWRESETREQ_Pos 9 /* SYS_CTRL_REG_SSE200 SWRESET: SWRESETREQ Positions */ +#define SYS_CTRL_REG_SSE200_SWRESET_SWRESETREQ_Msk (0x1UL << SYS_CTRL_REG_SSE200_SWRESET_SWRESETREQ_Pos) /* SYS_CTRL_REG_SSE200 SWRESET: SWRESETREQ Mask */ + +/* SYS_CTRL_REG_SSE200 GRETREG Register Definitions */ +#define SYS_CTRL_REG_SSE200_GRETREG_GRETREG_Pos 0 /* SYS_CTRL_REG_SSE200 GRETREG: GRETREG Positions */ +#define SYS_CTRL_REG_SSE200_GRETREG_GRETREG_Msk (0xFFFFUL /*<< SYS_CTRL_REG_SSE200_GRETREG_GRETREG_Pos*/) /* SYS_CTRL_REG_SSE200 GRETREG: GRETREG Mask */ + +/* SYS_CTRL_REG_SSE200 INITSVTOR0 Register Definitions */ +#define SYS_CTRL_REG_SSE200_INITSVTOR0_INITSVRTOR0_Pos 7 /* SYS_CTRL_REG_SSE200 INITSVTOR0: INITSVRTOR0 Positions */ +#define SYS_CTRL_REG_SSE200_INITSVTOR0_INITSVRTOR0_Msk (0x1FFFFFFUL << SYS_CTRL_REG_SSE200_INITSVTOR0_INITSVRTOR0_Pos) /* SYS_CTRL_REG_SSE200 INITSVTOR0: INITSVRTOR0 Mask */ + +/* SYS_CTRL_REG_SSE200 INITSVTOR1 Register Definitions */ +#define SYS_CTRL_REG_SSE200_INITSVTOR1_INITSVRTOR1_Pos 7 /* SYS_CTRL_REG_SSE200 INITSVTOR1: INITSVRTOR1 Positions */ +#define SYS_CTRL_REG_SSE200_INITSVTOR1_INITSVRTOR1_Msk (0x1FFFFFFUL << SYS_CTRL_REG_SSE200_INITSVTOR1_INITSVRTOR1_Pos) /* SYS_CTRL_REG_SSE200 INITSVTOR1: INITSVRTOR1 Mask */ + +/* SYS_CTRL_REG_SSE200 CPUWAIT Register Definitions */ +#define SYS_CTRL_REG_SSE200_CPUWAIT_CPU1WAIT_Pos 1 /* SYS_CTRL_REG_SSE200 CPUWAIT: CPU1WAIT Positions */ +#define SYS_CTRL_REG_SSE200_CPUWAIT_CPU1WAIT_Msk (0x1UL << SYS_CTRL_REG_SSE200_CPUWAIT_CPU1WAIT_Pos) /* SYS_CTRL_REG_SSE200 CPUWAIT: CPU1WAIT Mask */ + +#define SYS_CTRL_REG_SSE200_CPUWAIT_CPU0WAIT_Pos 0 /* SYS_CTRL_REG_SSE200 CPUWAIT: CPU0WAIT Positions */ +#define SYS_CTRL_REG_SSE200_CPUWAIT_CPU0WAIT_Msk (0x1UL /*<< SYS_CTRL_REG_SSE200_CPUWAIT_CPU0WAIT_Pos*/) /* SYS_CTRL_REG_SSE200 CPUWAIT: CPU0WAIT Mask */ + +/* SYS_CTRL_REG_SSE200 NMI_ENABLE Register Definitions */ +#define SYS_CTRL_REG_SSE200_NMI_ENABLE_CPU1_EXPNMI_ENABLE_Pos 17 /* SYS_CTRL_REG_SSE200 NMI_ENABLE: CPU1_EXPNMI_ENABLE Positions */ +#define SYS_CTRL_REG_SSE200_NMI_ENABLE_CPU1_EXPNMI_ENABLE_Msk (0x1UL << SYS_CTRL_REG_SSE200_NMI_ENABLE_CPU1_EXPNMI_ENABLE_Pos) /* SYS_CTRL_REG_SSE200 NMI_ENABLE: CPU1_EXPNMI_ENABLE Mask */ + +#define SYS_CTRL_REG_SSE200_NMI_ENABLE_CPU0_EXPNMI_ENABLE_Pos 16 /* SYS_CTRL_REG_SSE200 NMI_ENABLE: CPU0_EXPNMI_ENABLE Positions */ +#define SYS_CTRL_REG_SSE200_NMI_ENABLE_CPU0_EXPNMI_ENABLE_Msk (0x1UL << SYS_CTRL_REG_SSE200_NMI_ENABLE_CPU0_EXPNMI_ENABLE_Pos) /* SYS_CTRL_REG_SSE200 NMI_ENABLE: CPU0_EXPNMI_ENABLE Mask */ + +#define SYS_CTRL_REG_SSE200_NMI_ENABLE_CPU1_INTNMI_ENABLE_Pos 1 /* SYS_CTRL_REG_SSE200 NMI_ENABLE: CPU1_INTNMI_ENABLE Positions */ +#define SYS_CTRL_REG_SSE200_NMI_ENABLE_CPU1_INTNMI_ENABLE_Msk (0x1UL << SYS_CTRL_REG_SSE200_NMI_ENABLE_CPU1_INTNMI_ENABLE_Pos) /* SYS_CTRL_REG_SSE200 NMI_ENABLE: CPU1_INTNMI_ENABLE Mask */ + +#define SYS_CTRL_REG_SSE200_NMI_ENABLE_CPU0_INTNMI_ENABLE_Pos 0 /* SYS_CTRL_REG_SSE200 NMI_ENABLE: CPU0_INTNMI_ENABLE Positions */ +#define SYS_CTRL_REG_SSE200_NMI_ENABLE_CPU0_INTNMI_ENABLE_Msk (0x1UL /*<< SYS_CTRL_REG_SSE200_NMI_ENABLE_CPU0_INTNMI_ENABLE_Pos*/) /* SYS_CTRL_REG_SSE200 NMI_ENABLE: CPU0_INTNMI_ENABLE Mask */ + +/* SYS_CTRL_REG_SSE200 WICCTRL Register Definitions */ +#define SYS_CTRL_REG_SSE200_WICCTRL_CPU1WICRDY_Pos 17 /* SYS_CTRL_REG_SSE200 WICCTRL: CPU1WICRDY Positions */ +#define SYS_CTRL_REG_SSE200_WICCTRL_CPU1WICRDY_Msk (0x1UL << SYS_CTRL_REG_SSE200_WICCTRL_CPU1WICRDY_Pos) /* SYS_CTRL_REG_SSE200 WICCTRL: CPU1WICRDY Mask */ + +#define SYS_CTRL_REG_SSE200_WICCTRL_CPU0WICRDY_Pos 16 /* SYS_CTRL_REG_SSE200 WICCTRL: CPU0WICRDY Positions */ +#define SYS_CTRL_REG_SSE200_WICCTRL_CPU0WICRDY_Msk (0x1UL << SYS_CTRL_REG_SSE200_WICCTRL_CPU0WICRDY_Pos) /* SYS_CTRL_REG_SSE200 WICCTRL: CPU0WICRDY Mask */ + +#define SYS_CTRL_REG_SSE200_WICCTRL_CPU1WICEN_CLR_Pos 9 /* SYS_CTRL_REG_SSE200 WICCTRL: CPU1WICEN_CLR Positions */ +#define SYS_CTRL_REG_SSE200_WICCTRL_CPU1WICEN_CLR_Msk (0x1UL << SYS_CTRL_REG_SSE200_WICCTRL_CPU1WICEN_CLR_Pos) /* SYS_CTRL_REG_SSE200 WICCTRL: CPU1WICEN_CLR Mask */ + +#define SYS_CTRL_REG_SSE200_WICCTRL_CPU0WICEN_CLR_Pos 8 /* SYS_CTRL_REG_SSE200 WICCTRL: CPU0WICEN_CLR Positions */ +#define SYS_CTRL_REG_SSE200_WICCTRL_CPU0WICEN_CLR_Msk (0x1UL << SYS_CTRL_REG_SSE200_WICCTRL_CPU0WICEN_CLR_Pos) /* SYS_CTRL_REG_SSE200 WICCTRL: CPU0WICEN_CLR Mask */ + +#define SYS_CTRL_REG_SSE200_WICCTRL_CPU1WICEN_SET_Pos 5 /* SYS_CTRL_REG_SSE200 WICCTRL: CPU1WICEN_SET Positions */ +#define SYS_CTRL_REG_SSE200_WICCTRL_CPU1WICEN_SET_Msk (0x1UL << SYS_CTRL_REG_SSE200_WICCTRL_CPU1WICEN_SET_Pos) /* SYS_CTRL_REG_SSE200 WICCTRL: CPU1WICEN_SET Mask */ + +#define SYS_CTRL_REG_SSE200_WICCTRL_CPU0WICEN_SET_Pos 4 /* SYS_CTRL_REG_SSE200 WICCTRL: CPU0WICEN_SET Positions */ +#define SYS_CTRL_REG_SSE200_WICCTRL_CPU0WICEN_SET_Msk (0x1UL << SYS_CTRL_REG_SSE200_WICCTRL_CPU0WICEN_SET_Pos) /* SYS_CTRL_REG_SSE200 WICCTRL: CPU0WICEN_SET Mask */ + +#define SYS_CTRL_REG_SSE200_WICCTRL_CPU1WICEN_STATUS_Pos 1 /* SYS_CTRL_REG_SSE200 WICCTRL: CPU1WICEN_STATUS Positions */ +#define SYS_CTRL_REG_SSE200_WICCTRL_CPU1WICEN_STATUS_Msk (0x1UL << SYS_CTRL_REG_SSE200_WICCTRL_CPU1WICEN_STATUS_Pos) /* SYS_CTRL_REG_SSE200 WICCTRL: CPU1WICEN_STATUS Mask */ + +#define SYS_CTRL_REG_SSE200_WICCTRL_CPU0WICEN_STATUS_Pos 0 /* SYS_CTRL_REG_SSE200 WICCTRL: CPU0WICEN_STATUS Positions */ +#define SYS_CTRL_REG_SSE200_WICCTRL_CPU0WICEN_STATUS_Msk (0x1UL /*<< SYS_CTRL_REG_SSE200_WICCTRL_CPU0WICEN_STATUS_Pos*/) /* SYS_CTRL_REG_SSE200 WICCTRL: CPU0WICEN_STATUS Mask */ + +/* SYS_CTRL_REG_SSE200 EWCTRL Register Definitions */ +#define SYS_CTRL_REG_SSE200_EWCTRL_EWC1EN_CLR_Pos 9 /* SYS_CTRL_REG_SSE200 EWCTRL: EWC1EN_CLR Positions */ +#define SYS_CTRL_REG_SSE200_EWCTRL_EWC1EN_CLR_Msk (0x1UL << SYS_CTRL_REG_SSE200_EWCTRL_EWC1EN_CLR_Pos) /* SYS_CTRL_REG_SSE200 EWCTRL: EWC1EN_CLR Mask */ + +#define SYS_CTRL_REG_SSE200_EWCTRL_EWC0EN_CLR_Pos 8 /* SYS_CTRL_REG_SSE200 EWCTRL: EWC0EN_CLR Positions */ +#define SYS_CTRL_REG_SSE200_EWCTRL_EWC0EN_CLR_Msk (0x1UL << SYS_CTRL_REG_SSE200_EWCTRL_EWC0EN_CLR_Pos) /* SYS_CTRL_REG_SSE200 EWCTRL: EWC0EN_CLR Mask */ + +#define SYS_CTRL_REG_SSE200_EWCTRL_EWC1EN_SET_Pos 5 /* SYS_CTRL_REG_SSE200 EWCTRL: EWC1EN_SET Positions */ +#define SYS_CTRL_REG_SSE200_EWCTRL_EWC1EN_SET_Msk (0x1UL << SYS_CTRL_REG_SSE200_EWCTRL_EWC1EN_SET_Pos) /* SYS_CTRL_REG_SSE200 EWCTRL: EWC1EN_SET Mask */ + +#define SYS_CTRL_REG_SSE200_EWCTRL_EWC0EN_SET_Pos 4 /* SYS_CTRL_REG_SSE200 EWCTRL: EWC0EN_SET Positions */ +#define SYS_CTRL_REG_SSE200_EWCTRL_EWC0EN_SET_Msk (0x1UL << SYS_CTRL_REG_SSE200_EWCTRL_EWC0EN_SET_Pos) /* SYS_CTRL_REG_SSE200 EWCTRL: EWC0EN_SET Mask */ + +#define SYS_CTRL_REG_SSE200_EWCTRL_EWC1EN_STATUS_Pos 1 /* SYS_CTRL_REG_SSE200 EWCTRL: EWC1EN_STATUS Positions */ +#define SYS_CTRL_REG_SSE200_EWCTRL_EWC1EN_STATUS_Msk (0x1UL << SYS_CTRL_REG_SSE200_EWCTRL_EWC1EN_STATUS_Pos) /* SYS_CTRL_REG_SSE200 EWCTRL: EWC1EN_STATUS Mask */ + +#define SYS_CTRL_REG_SSE200_EWCTRL_EWC0EN_STATUS_Pos 0 /* SYS_CTRL_REG_SSE200 EWCTRL: EWC0EN_STATUS Positions */ +#define SYS_CTRL_REG_SSE200_EWCTRL_EWC0EN_STATUS_Msk (0x1UL /*<< SYS_CTRL_REG_SSE200_EWCTRL_EWC0EN_STATUS_Pos*/) /* SYS_CTRL_REG_SSE200 EWCTRL: EWC0EN_STATUS Mask */ + +/* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE Register Definitions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_EXP3_IN_Pos 19 /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_EXP3_IN Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_EXP3_IN_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_EXP3_IN_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_EXP3_IN Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_EXP2_IN_Pos 18 /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_EXP2_IN Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_EXP2_IN_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_EXP2_IN_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_EXP2_IN Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_EXP1_IN_Pos 17 /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_EXP1_IN Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_EXP1_IN_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_EXP1_IN_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_EXP1_IN Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_EXP0_IN_Pos 16 /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_EXP0_IN Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_EXP0_IN_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_EXP0_IN_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_EXP0_IN Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_CRYPTO_ON_Pos 12 /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_CRYPTO_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_CRYPTO_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_CRYPTO_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_CRYPTO_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_SRAM3_ON_Pos 6 /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_SRAM3_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_SRAM3_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_SRAM3_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_SRAM3_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_SRAM2_ON_Pos 5 /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_SRAM2_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_SRAM2_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_SRAM2_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_SRAM2_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_SRAM1_ON_Pos 4 /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_SRAM1_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_SRAM1_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_SRAM1_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_SRAM1_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_SRAM0_ON_Pos 3 /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_SRAM0_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_SRAM0_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_SRAM0_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_SRAM0_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_CPU1CORE_ON_Pos 2 /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_CPU1CORE_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_CPU1CORE_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_CPU1CORE_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_CPU1CORE_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_CPU0CORE_ON_Pos 1 /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_CPU0CORE_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_CPU0CORE_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_CPU0CORE_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_CPU0CORE_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_SYS_ON_Pos 0 /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_SYS_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_SYS_ON_Msk (0x1UL /*<< SYS_CTRL_REG_SSE200_PDCM_PD_SYS_SENSE_S_PD_SYS_ON_Pos*/) /* SYS_CTRL_REG_SSE200 PDCM_PD_SYS_SENSE: S_PD_SYS_ON Mask */ + +/* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE Register Definitions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_EXP3_IN_Pos 19 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_EXP3_IN Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_EXP3_IN_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_EXP3_IN_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_EXP3_IN Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_EXP2_IN_Pos 18 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_EXP2_IN Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_EXP2_IN_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_EXP2_IN_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_EXP2_IN Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_EXP1_IN_Pos 17 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_EXP1_IN Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_EXP1_IN_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_EXP1_IN_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_EXP1_IN Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_EXP0_IN_Pos 16 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_EXP0_IN Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_EXP0_IN_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_EXP0_IN_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_EXP0_IN Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_CRYPTO_ON_Pos 12 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_CRYPTO_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_CRYPTO_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_CRYPTO_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_CRYPTO_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_SRAM3_ON_Pos 6 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_SRAM3_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_SRAM3_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_SRAM3_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_SRAM3_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_SRAM2_ON_Pos 5 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_SRAM2_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_SRAM2_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_SRAM2_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_SRAM2_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_SRAM1_ON_Pos 4 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_SRAM1_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_SRAM1_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_SRAM1_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_SRAM1_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_SRAM0_ON_Pos 3 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_SRAM0_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_SRAM0_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_SRAM0_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_SRAM0_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_CPU1CORE_ON_Pos 2 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_CPU1CORE_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_CPU1CORE_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_CPU1CORE_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_CPU1CORE_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_CPU0CORE_ON_Pos 1 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_CPU0CORE_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_CPU0CORE_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_CPU0CORE_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_CPU0CORE_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_SYS_ON_Pos 0 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_SYS_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_SYS_ON_Msk (0x1UL /*<< SYS_CTRL_REG_SSE200_PDCM_PD_SRAM0_SENSE_S_PD_SYS_ON_Pos*/) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM0_SENSE: S_PD_SYS_ON Mask */ + +/* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE Register Definitions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_EXP3_IN_Pos 19 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_EXP3_IN Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_EXP3_IN_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_EXP3_IN_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_EXP3_IN Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_EXP2_IN_Pos 18 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_EXP2_IN Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_EXP2_IN_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_EXP2_IN_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_EXP2_IN Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_EXP1_IN_Pos 17 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_EXP1_IN Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_EXP1_IN_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_EXP1_IN_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_EXP1_IN Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_EXP0_IN_Pos 16 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_EXP0_IN Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_EXP0_IN_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_EXP0_IN_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_EXP0_IN Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_CRYPTO_ON_Pos 12 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_CRYPTO_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_CRYPTO_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_CRYPTO_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_CRYPTO_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_SRAM3_ON_Pos 6 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_SRAM3_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_SRAM3_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_SRAM3_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_SRAM3_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_SRAM2_ON_Pos 5 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_SRAM2_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_SRAM2_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_SRAM2_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_SRAM2_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_SRAM1_ON_Pos 4 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_SRAM1_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_SRAM1_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_SRAM1_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_SRAM1_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_SRAM0_ON_Pos 3 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_SRAM0_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_SRAM0_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_SRAM0_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_SRAM0_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_CPU1CORE_ON_Pos 2 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_CPU1CORE_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_CPU1CORE_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_CPU1CORE_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_CPU1CORE_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_CPU0CORE_ON_Pos 1 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_CPU0CORE_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_CPU0CORE_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_CPU0CORE_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_CPU0CORE_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_SYS_ON_Pos 0 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_SYS_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_SYS_ON_Msk (0x1UL /*<< SYS_CTRL_REG_SSE200_PDCM_PD_SRAM1_SENSE_S_PD_SYS_ON_Pos*/) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM1_SENSE: S_PD_SYS_ON Mask */ + +/* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE Register Definitions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_EXP3_IN_Pos 19 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_EXP3_IN Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_EXP3_IN_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_EXP3_IN_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_EXP3_IN Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_EXP2_IN_Pos 18 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_EXP2_IN Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_EXP2_IN_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_EXP2_IN_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_EXP2_IN Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_EXP1_IN_Pos 17 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_EXP1_IN Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_EXP1_IN_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_EXP1_IN_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_EXP1_IN Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_EXP0_IN_Pos 16 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_EXP0_IN Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_EXP0_IN_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_EXP0_IN_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_EXP0_IN Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_CRYPTO_ON_Pos 12 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_CRYPTO_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_CRYPTO_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_CRYPTO_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_CRYPTO_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_SRAM3_ON_Pos 6 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_SRAM3_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_SRAM3_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_SRAM3_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_SRAM3_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_SRAM2_ON_Pos 5 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_SRAM2_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_SRAM2_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_SRAM2_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_SRAM2_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_SRAM1_ON_Pos 4 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_SRAM1_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_SRAM1_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_SRAM1_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_SRAM1_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_SRAM0_ON_Pos 3 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_SRAM0_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_SRAM0_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_SRAM0_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_SRAM0_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_CPU1CORE_ON_Pos 2 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_CPU1CORE_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_CPU1CORE_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_CPU1CORE_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_CPU1CORE_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_CPU0CORE_ON_Pos 1 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_CPU0CORE_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_CPU0CORE_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_CPU0CORE_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_CPU0CORE_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_SYS_ON_Pos 0 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_SYS_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_SYS_ON_Msk (0x1UL /*<< SYS_CTRL_REG_SSE200_PDCM_PD_SRAM2_SENSE_S_PD_SYS_ON_Pos*/) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM2_SENSE: S_PD_SYS_ON Mask */ + +/* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE Register Definitions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_EXP3_IN_Pos 19 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_EXP3_IN Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_EXP3_IN_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_EXP3_IN_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_EXP3_IN Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_EXP2_IN_Pos 18 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_EXP2_IN Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_EXP2_IN_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_EXP2_IN_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_EXP2_IN Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_EXP1_IN_Pos 17 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_EXP1_IN Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_EXP1_IN_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_EXP1_IN_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_EXP1_IN Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_EXP0_IN_Pos 16 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_EXP0_IN Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_EXP0_IN_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_EXP0_IN_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_EXP0_IN Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_CRYPTO_ON_Pos 12 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_CRYPTO_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_CRYPTO_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_CRYPTO_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_CRYPTO_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_SRAM3_ON_Pos 6 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_SRAM3_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_SRAM3_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_SRAM3_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_SRAM3_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_SRAM2_ON_Pos 5 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_SRAM2_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_SRAM2_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_SRAM2_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_SRAM2_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_SRAM1_ON_Pos 4 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_SRAM1_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_SRAM1_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_SRAM1_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_SRAM1_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_SRAM0_ON_Pos 3 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_SRAM0_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_SRAM0_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_SRAM0_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_SRAM0_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_CPU1CORE_ON_Pos 2 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_CPU1CORE_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_CPU1CORE_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_CPU1CORE_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_CPU1CORE_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_CPU0CORE_ON_Pos 1 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_CPU0CORE_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_CPU0CORE_ON_Msk (0x1UL << SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_CPU0CORE_ON_Pos) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_CPU0CORE_ON Mask */ + +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_SYS_ON_Pos 0 /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_SYS_ON Positions */ +#define SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_SYS_ON_Msk (0x1UL /*<< SYS_CTRL_REG_SSE200_PDCM_PD_SRAM3_SENSE_S_PD_SYS_ON_Pos*/) /* SYS_CTRL_REG_SSE200 PDCM_PD_SRAM3_SENSE: S_PD_SYS_ON Mask */ + +/* SYS_CTRL_REG_SSE200 PIDR4 Register Definitions */ +#define SYS_CTRL_REG_SSE200_PIDR4_SIZE_Pos 4 /* SYS_CTRL_REG_SSE200 PIDR4: SIZE Positions */ +#define SYS_CTRL_REG_SSE200_PIDR4_SIZE_Msk (0xFUL << SYS_CTRL_REG_SSE200_PIDR4_SIZE_Pos) /* SYS_CTRL_REG_SSE200 PIDR4: SIZE Mask */ + +#define SYS_CTRL_REG_SSE200_PIDR4_DES_2_Pos 0 /* SYS_CTRL_REG_SSE200 PIDR4: DES_2 Positions */ +#define SYS_CTRL_REG_SSE200_PIDR4_DES_2_Msk (0xFUL /*<< SYS_CTRL_REG_SSE200_PIDR4_DES_2_Pos*/) /* SYS_CTRL_REG_SSE200 PIDR4: DES_2 Mask */ + +/* SYS_CTRL_REG_SSE200 PIDR0 Register Definitions */ +#define SYS_CTRL_REG_SSE200_PIDR0_PART_0_Pos 0 /* SYS_CTRL_REG_SSE200 PIDR0: PART_0 Positions */ +#define SYS_CTRL_REG_SSE200_PIDR0_PART_0_Msk (0xFFUL /*<< SYS_CTRL_REG_SSE200_PIDR0_PART_0_Pos*/) /* SYS_CTRL_REG_SSE200 PIDR0: PART_0 Mask */ + +/* SYS_CTRL_REG_SSE200 PIDR1 Register Definitions */ +#define SYS_CTRL_REG_SSE200_PIDR1_DES_0_Pos 4 /* SYS_CTRL_REG_SSE200 PIDR1: DES_0 Positions */ +#define SYS_CTRL_REG_SSE200_PIDR1_DES_0_Msk (0xFUL << SYS_CTRL_REG_SSE200_PIDR1_DES_0_Pos) /* SYS_CTRL_REG_SSE200 PIDR1: DES_0 Mask */ + +#define SYS_CTRL_REG_SSE200_PIDR1_PART_1_Pos 0 /* SYS_CTRL_REG_SSE200 PIDR1: PART_1 Positions */ +#define SYS_CTRL_REG_SSE200_PIDR1_PART_1_Msk (0xFUL /*<< SYS_CTRL_REG_SSE200_PIDR1_PART_1_Pos*/) /* SYS_CTRL_REG_SSE200 PIDR1: PART_1 Mask */ + +/* SYS_CTRL_REG_SSE200 PIDR2 Register Definitions */ +#define SYS_CTRL_REG_SSE200_PIDR2_REVISION_Pos 4 /* SYS_CTRL_REG_SSE200 PIDR2: REVISION Positions */ +#define SYS_CTRL_REG_SSE200_PIDR2_REVISION_Msk (0xFUL << SYS_CTRL_REG_SSE200_PIDR2_REVISION_Pos) /* SYS_CTRL_REG_SSE200 PIDR2: REVISION Mask */ + +#define SYS_CTRL_REG_SSE200_PIDR2_JEDEC_Pos 3 /* SYS_CTRL_REG_SSE200 PIDR2: JEDEC Positions */ +#define SYS_CTRL_REG_SSE200_PIDR2_JEDEC_Msk (0x1UL << SYS_CTRL_REG_SSE200_PIDR2_JEDEC_Pos) /* SYS_CTRL_REG_SSE200 PIDR2: JEDEC Mask */ + +#define SYS_CTRL_REG_SSE200_PIDR2_DES_1_Pos 0 /* SYS_CTRL_REG_SSE200 PIDR2: DES_1 Positions */ +#define SYS_CTRL_REG_SSE200_PIDR2_DES_1_Msk (0x7UL /*<< SYS_CTRL_REG_SSE200_PIDR2_DES_1_Pos*/) /* SYS_CTRL_REG_SSE200 PIDR2: DES_1 Mask */ + +/* SYS_CTRL_REG_SSE200 PIDR3 Register Definitions */ +#define SYS_CTRL_REG_SSE200_PIDR3_REVAND_Pos 4 /* SYS_CTRL_REG_SSE200 PIDR3: REVAND Positions */ +#define SYS_CTRL_REG_SSE200_PIDR3_REVAND_Msk (0xFUL << SYS_CTRL_REG_SSE200_PIDR3_REVAND_Pos) /* SYS_CTRL_REG_SSE200 PIDR3: REVAND Mask */ + +#define SYS_CTRL_REG_SSE200_PIDR3_CMOD_Pos 0 /* SYS_CTRL_REG_SSE200 PIDR3: CMOD Positions */ +#define SYS_CTRL_REG_SSE200_PIDR3_CMOD_Msk (0xFUL /*<< SYS_CTRL_REG_SSE200_PIDR3_CMOD_Pos*/) /* SYS_CTRL_REG_SSE200 PIDR3: CMOD Mask */ + +/* SYS_CTRL_REG_SSE200 CIDR0 Register Definitions */ +#define SYS_CTRL_REG_SSE200_CIDR0_PRMBL_0_Pos 0 /* SYS_CTRL_REG_SSE200 CIDR0: PRMBL_0 Positions */ +#define SYS_CTRL_REG_SSE200_CIDR0_PRMBL_0_Msk (0xFFUL /*<< SYS_CTRL_REG_SSE200_CIDR0_PRMBL_0_Pos*/) /* SYS_CTRL_REG_SSE200 CIDR0: PRMBL_0 Mask */ + +/* SYS_CTRL_REG_SSE200 CIDR1 Register Definitions */ +#define SYS_CTRL_REG_SSE200_CIDR1_CLASS_Pos 4 /* SYS_CTRL_REG_SSE200 CIDR1: CLASS Positions */ +#define SYS_CTRL_REG_SSE200_CIDR1_CLASS_Msk (0xFUL << SYS_CTRL_REG_SSE200_CIDR1_CLASS_Pos) /* SYS_CTRL_REG_SSE200 CIDR1: CLASS Mask */ + +#define SYS_CTRL_REG_SSE200_CIDR1_PRMBL_1_Pos 0 /* SYS_CTRL_REG_SSE200 CIDR1: PRMBL_1 Positions */ +#define SYS_CTRL_REG_SSE200_CIDR1_PRMBL_1_Msk (0xFUL /*<< SYS_CTRL_REG_SSE200_CIDR1_PRMBL_1_Pos*/) /* SYS_CTRL_REG_SSE200 CIDR1: PRMBL_1 Mask */ + +/* SYS_CTRL_REG_SSE200 CIDR2 Register Definitions */ +#define SYS_CTRL_REG_SSE200_CIDR2_PRMBL_2_Pos 0 /* SYS_CTRL_REG_SSE200 CIDR2: PRMBL_2 Positions */ +#define SYS_CTRL_REG_SSE200_CIDR2_PRMBL_2_Msk (0xFFUL /*<< SYS_CTRL_REG_SSE200_CIDR2_PRMBL_2_Pos*/) /* SYS_CTRL_REG_SSE200 CIDR2: PRMBL_2 Mask */ + +/* SYS_CTRL_REG_SSE200 CIDR3 Register Definitions */ +#define SYS_CTRL_REG_SSE200_CIDR3_PRMBL_3_Pos 0 /* SYS_CTRL_REG_SSE200 CIDR3: PRMBL_3 Positions */ +#define SYS_CTRL_REG_SSE200_CIDR3_PRMBL_3_Msk (0xFFUL /*<< SYS_CTRL_REG_SSE200_CIDR3_PRMBL_3_Pos*/) /* SYS_CTRL_REG_SSE200 CIDR3: PRMBL_3 Mask */ + + +/*---------------- SYSTEM INFO REGISTER (SYSINFO) ----------------*/ +typedef struct +{ +__IM uint32_t SYS_VERSION; /* Offset: 0x0 (read-only) SYS_VERSION Register */ +__IM uint32_t SYS_CONFIG; /* Offset: 0x4 (read-only) SYS_CONFIG Register */ + uint32_t RESERVED0[1010]; +__IM uint32_t PIDR4; /* Offset: 0xFD0 (read-only) PIDR4 Register */ + uint32_t RESERVED1[3]; +__IM uint32_t PIDR0; /* Offset: 0xFE0 (read-only) PIDR0 Register */ +__IM uint32_t PIDR1; /* Offset: 0xFE4 (read-only) PIDR1 Register */ +__IM uint32_t PIDR2; /* Offset: 0xFE8 (read-only) PIDR2 Register */ +__IM uint32_t PIDR3; /* Offset: 0xFEC (read-only) PIDR3 Register */ +__IM uint32_t CIDR0; /* Offset: 0xFF0 (read-only) CIDR0 Register */ +__IM uint32_t CIDR1; /* Offset: 0xFF4 (read-only) CIDR1 Register */ +__IM uint32_t CIDR2; /* Offset: 0xFF8 (read-only) CIDR2 Register */ +__IM uint32_t CIDR3; /* Offset: 0xFFC (read-only) CIDR3 Register */ +}SYSINFO_TypeDef; + +/* SYSINFO SYS_VERSION Register Definitions */ +#define SYSINFO_SYS_VERSION_CONFIGURATION_Pos 28 /* SYSINFO SYS_VERSION: CONFIGURATION Positions */ +#define SYSINFO_SYS_VERSION_CONFIGURATION_Msk (0xFUL << SYSINFO_SYS_VERSION_CONFIGURATION_Pos) /* SYSINFO SYS_VERSION: CONFIGURATION Mask */ + +#define SYSINFO_SYS_VERSION_MAJOR_REVISION_Pos 24 /* SYSINFO SYS_VERSION: MAJOR_REVISION Positions */ +#define SYSINFO_SYS_VERSION_MAJOR_REVISION_Msk (0xFUL << SYSINFO_SYS_VERSION_MAJOR_REVISION_Pos) /* SYSINFO SYS_VERSION: MAJOR_REVISION Mask */ + +#define SYSINFO_SYS_VERSION_MINOR_REVISION_Pos 20 /* SYSINFO SYS_VERSION: MINOR_REVISION Positions */ +#define SYSINFO_SYS_VERSION_MINOR_REVISION_Msk (0xFUL << SYSINFO_SYS_VERSION_MINOR_REVISION_Pos) /* SYSINFO SYS_VERSION: MINOR_REVISION Mask */ + +#define SYSINFO_SYS_VERSION_DESIGNER_ID_Pos 12 /* SYSINFO SYS_VERSION: DESIGNER_ID Positions */ +#define SYSINFO_SYS_VERSION_DESIGNER_ID_Msk (0xFFUL << SYSINFO_SYS_VERSION_DESIGNER_ID_Pos) /* SYSINFO SYS_VERSION: DESIGNER_ID Mask */ + +#define SYSINFO_SYS_VERSION_PART_NUMBER_Pos 0 /* SYSINFO SYS_VERSION: PART_NUMBER Positions */ +#define SYSINFO_SYS_VERSION_PART_NUMBER_Msk (0xFFFUL /*<< SYSINFO_SYS_VERSION_PART_NUMBER_Pos*/) /* SYSINFO SYS_VERSION: PART_NUMBER Mask */ + +/* SYSINFO SYS_CONFIG Register Definitions */ +#define SYSINFO_SYS_CONFIG_CPU1_TYPE_Pos 28 /* SYSINFO SYS_CONFIG: CPU1_TYPE Positions */ +#define SYSINFO_SYS_CONFIG_CPU1_TYPE_Msk (0xFUL << SYSINFO_SYS_CONFIG_CPU1_TYPE_Pos) /* SYSINFO SYS_CONFIG: CPU1_TYPE Mask */ + +#define SYSINFO_SYS_CONFIG_CPU0_TYPE_Pos 24 /* SYSINFO SYS_CONFIG: CPU0_TYPE Positions */ +#define SYSINFO_SYS_CONFIG_CPU0_TYPE_Msk (0xFUL << SYSINFO_SYS_CONFIG_CPU0_TYPE_Pos) /* SYSINFO SYS_CONFIG: CPU0_TYPE Mask */ + +#define SYSINFO_SYS_CONFIG_CPU1_TCM_BANK_NUM_Pos 20 /* SYSINFO SYS_CONFIG: CPU1_TCM_BANK_NUM Positions */ +#define SYSINFO_SYS_CONFIG_CPU1_TCM_BANK_NUM_Msk (0xFUL << SYSINFO_SYS_CONFIG_CPU1_TCM_BANK_NUM_Pos) /* SYSINFO SYS_CONFIG: CPU1_TCM_BANK_NUM Mask */ + +#define SYSINFO_SYS_CONFIG_CPU0_TCM_BANK_NUM_Pos 16 /* SYSINFO SYS_CONFIG: CPU0_TCM_BANK_NUM Positions */ +#define SYSINFO_SYS_CONFIG_CPU0_TCM_BANK_NUM_Msk (0xFUL << SYSINFO_SYS_CONFIG_CPU0_TCM_BANK_NUM_Pos) /* SYSINFO SYS_CONFIG: CPU0_TCM_BANK_NUM Mask */ + +#define SYSINFO_SYS_CONFIG_HAS_CRYPTO_Pos 12 /* SYSINFO SYS_CONFIG: HAS_CRYPTO Positions */ +#define SYSINFO_SYS_CONFIG_HAS_CRYPTO_Msk (0x1UL << SYSINFO_SYS_CONFIG_HAS_CRYPTO_Pos) /* SYSINFO SYS_CONFIG: HAS_CRYPTO Mask */ + +#define SYSINFO_SYS_CONFIG_HAS_CORDIO_Pos 11 /* SYSINFO SYS_CONFIG: HAS_CORDIO Positions */ +#define SYSINFO_SYS_CONFIG_HAS_CORDIO_Msk (0x1UL << SYSINFO_SYS_CONFIG_HAS_CORDIO_Pos) /* SYSINFO SYS_CONFIG: HAS_CORDIO Mask */ + +#define SYSINFO_SYS_CONFIG_CPU1_HAS_TCM_Pos 10 /* SYSINFO SYS_CONFIG: CPU1_HAS_TCM Positions */ +#define SYSINFO_SYS_CONFIG_CPU1_HAS_TCM_Msk (0x1UL << SYSINFO_SYS_CONFIG_CPU1_HAS_TCM_Pos) /* SYSINFO SYS_CONFIG: CPU1_HAS_TCM Mask */ + +#define SYSINFO_SYS_CONFIG_CPU0_HAS_TCM_Pos 9 /* SYSINFO SYS_CONFIG: CPU0_HAS_TCM Positions */ +#define SYSINFO_SYS_CONFIG_CPU0_HAS_TCM_Msk (0x1UL << SYSINFO_SYS_CONFIG_CPU0_HAS_TCM_Pos) /* SYSINFO SYS_CONFIG: CPU0_HAS_TCM Mask */ + +#define SYSINFO_SYS_CONFIG_SRAM_ADDR_WIDTH_Pos 4 /* SYSINFO SYS_CONFIG: SRAM_ADDR_WIDTH Positions */ +#define SYSINFO_SYS_CONFIG_SRAM_ADDR_WIDTH_Msk (0x1FUL << SYSINFO_SYS_CONFIG_SRAM_ADDR_WIDTH_Pos) /* SYSINFO SYS_CONFIG: SRAM_ADDR_WIDTH Mask */ + +#define SYSINFO_SYS_CONFIG_SRAM_NUM_BANK_Pos 0 /* SYSINFO SYS_CONFIG: SRAM_NUM_BANK Positions */ +#define SYSINFO_SYS_CONFIG_SRAM_NUM_BANK_Msk (0xFUL /*<< SYSINFO_SYS_CONFIG_SRAM_NUM_BANK_Pos*/) /* SYSINFO SYS_CONFIG: SRAM_NUM_BANK Mask */ + +/* SYSINFO PIDR4 Register Definitions */ +#define SYSINFO_PIDR4_SIZE_Pos 4 /* SYSINFO PIDR4: SIZE Positions */ +#define SYSINFO_PIDR4_SIZE_Msk (0xFUL << SYSINFO_PIDR4_SIZE_Pos) /* SYSINFO PIDR4: SIZE Mask */ + +#define SYSINFO_PIDR4_DES_2_Pos 0 /* SYSINFO PIDR4: DES_2 Positions */ +#define SYSINFO_PIDR4_DES_2_Msk (0xFUL /*<< SYSINFO_PIDR4_DES_2_Pos*/) /* SYSINFO PIDR4: DES_2 Mask */ + +/* SYSINFO PIDR0 Register Definitions */ +#define SYSINFO_PIDR0_PART_0_Pos 0 /* SYSINFO PIDR0: PART_0 Positions */ +#define SYSINFO_PIDR0_PART_0_Msk (0xFFUL /*<< SYSINFO_PIDR0_PART_0_Pos*/) /* SYSINFO PIDR0: PART_0 Mask */ + +/* SYSINFO PIDR1 Register Definitions */ +#define SYSINFO_PIDR1_DES_0_Pos 4 /* SYSINFO PIDR1: DES_0 Positions */ +#define SYSINFO_PIDR1_DES_0_Msk (0xFUL << SYSINFO_PIDR1_DES_0_Pos) /* SYSINFO PIDR1: DES_0 Mask */ + +#define SYSINFO_PIDR1_PART_1_Pos 0 /* SYSINFO PIDR1: PART_1 Positions */ +#define SYSINFO_PIDR1_PART_1_Msk (0xFUL /*<< SYSINFO_PIDR1_PART_1_Pos*/) /* SYSINFO PIDR1: PART_1 Mask */ + +/* SYSINFO PIDR2 Register Definitions */ +#define SYSINFO_PIDR2_REVISION_Pos 4 /* SYSINFO PIDR2: REVISION Positions */ +#define SYSINFO_PIDR2_REVISION_Msk (0xFUL << SYSINFO_PIDR2_REVISION_Pos) /* SYSINFO PIDR2: REVISION Mask */ + +#define SYSINFO_PIDR2_JEDEC_Pos 3 /* SYSINFO PIDR2: JEDEC Positions */ +#define SYSINFO_PIDR2_JEDEC_Msk (0x1UL << SYSINFO_PIDR2_JEDEC_Pos) /* SYSINFO PIDR2: JEDEC Mask */ + +#define SYSINFO_PIDR2_DES_1_Pos 0 /* SYSINFO PIDR2: DES_1 Positions */ +#define SYSINFO_PIDR2_DES_1_Msk (0x7UL /*<< SYSINFO_PIDR2_DES_1_Pos*/) /* SYSINFO PIDR2: DES_1 Mask */ + +/* SYSINFO PIDR3 Register Definitions */ +#define SYSINFO_PIDR3_REVAND_Pos 4 /* SYSINFO PIDR3: REVAND Positions */ +#define SYSINFO_PIDR3_REVAND_Msk (0xFUL << SYSINFO_PIDR3_REVAND_Pos) /* SYSINFO PIDR3: REVAND Mask */ + +#define SYSINFO_PIDR3_CMOD_Pos 0 /* SYSINFO PIDR3: CMOD Positions */ +#define SYSINFO_PIDR3_CMOD_Msk (0xFUL /*<< SYSINFO_PIDR3_CMOD_Pos*/) /* SYSINFO PIDR3: CMOD Mask */ + +/* SYSINFO CIDR0 Register Definitions */ +#define SYSINFO_CIDR0_PRMBL_0_Pos 0 /* SYSINFO CIDR0: PRMBL_0 Positions */ +#define SYSINFO_CIDR0_PRMBL_0_Msk (0xFFUL /*<< SYSINFO_CIDR0_PRMBL_0_Pos*/) /* SYSINFO CIDR0: PRMBL_0 Mask */ + +/* SYSINFO CIDR1 Register Definitions */ +#define SYSINFO_CIDR1_CLASS_Pos 4 /* SYSINFO CIDR1: CLASS Positions */ +#define SYSINFO_CIDR1_CLASS_Msk (0xFUL << SYSINFO_CIDR1_CLASS_Pos) /* SYSINFO CIDR1: CLASS Mask */ + +#define SYSINFO_CIDR1_PRMBL_1_Pos 0 /* SYSINFO CIDR1: PRMBL_1 Positions */ +#define SYSINFO_CIDR1_PRMBL_1_Msk (0xFUL /*<< SYSINFO_CIDR1_PRMBL_1_Pos*/) /* SYSINFO CIDR1: PRMBL_1 Mask */ + +/* SYSINFO CIDR2 Register Definitions */ +#define SYSINFO_CIDR2_PRMBL_2_Pos 0 /* SYSINFO CIDR2: PRMBL_2 Positions */ +#define SYSINFO_CIDR2_PRMBL_2_Msk (0xFFUL /*<< SYSINFO_CIDR2_PRMBL_2_Pos*/) /* SYSINFO CIDR2: PRMBL_2 Mask */ + +/* SYSINFO CIDR3 Register Definitions */ +#define SYSINFO_CIDR3_PRMBL_3_Pos 0 /* SYSINFO CIDR3: PRMBL_3 Positions */ +#define SYSINFO_CIDR3_PRMBL_3_Msk (0xFFUL /*<< SYSINFO_CIDR3_PRMBL_3_Pos*/) /* SYSINFO CIDR3: PRMBL_3 Mask */ + + +/*------------------- Watchdog ----------------------------------------------*/ +typedef struct +{ + + __IOM uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ + __IM uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ + __IOM uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ + __OM uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ + __IM uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ + __IM uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ + uint32_t RESERVED0[762]; + __IOM uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ + uint32_t RESERVED1[191]; + __IOM uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ + __OM uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ +}CMSDK_WATCHDOG_TypeDef; + +/* CMSDK_WATCHDOG LOAD Register Definitions */ +#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ +#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFUL /*<< CMSDK_Watchdog_LOAD_Pos*/) /* CMSDK_Watchdog LOAD: LOAD Mask */ + +/* CMSDK_WATCHDOG VALUE Register Definitions */ +#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */ +#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFUL /*<< CMSDK_Watchdog_VALUE_Pos*/) /* CMSDK_Watchdog VALUE: VALUE Mask */ + +/* CMSDK_WATCHDOG CTRL Register Definitions */ +#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */ +#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1UL << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */ + +#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */ +#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1UL /*<< CMSDK_Watchdog_CTRL_INTEN_Pos*/) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */ + +/* CMSDK_WATCHDOG INTCLR Register Definitions */ +#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */ +#define CMSDK_Watchdog_INTCLR_Msk (0x1UL /*<< CMSDK_Watchdog_INTCLR_Pos*/) /* CMSDK_Watchdog INTCLR: Int Clear Mask */ + +/* CMSDK_WATCHDOG RAWINTSTAT Register Definitions */ +#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1UL /*<< CMSDK_Watchdog_RAWINTSTAT_Pos*/) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */ + +/* CMSDK_WATCHDOG MASKINTSTAT Register Definitions */ +#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1UL /*<< CMSDK_Watchdog_MASKINTSTAT_Pos*/) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */ + +/* CMSDK_WATCHDOG LOCK Register Definitions */ +#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */ +#define CMSDK_Watchdog_LOCK_Msk (0x1UL /*<< CMSDK_Watchdog_LOCK_Pos*/) /* CMSDK_Watchdog LOCK: LOCK Mask */ + +/* CMSDK_WATCHDOG INTEGTESTEN Register Definitions */ +#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */ +#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1UL /*<< CMSDK_Watchdog_INTEGTESTEN_Pos*/) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */ + +/* CMSDK_WATCHDOG INTEGTESTOUTSET Register Definitions */ +#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */ +#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1UL /*<< CMSDK_Watchdog_INTEGTESTOUTSET_Pos*/) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */ + + +/*------------------- Power Policy Unit ----------------------------------------------*/ +typedef struct { + __IO uint32_t PWPR; // Offset: 0x000 (R/W) Power Policy Register + __IO uint32_t PMER; // Offset: 0x004 (R/W) Power Mode Emulation Register + __I uint32_t PWSR; // Offset: 0x008 (R/ ) Power Status Register + __I uint32_t SCSR; // Offset: 0x00C (R/ ) Static Configuration Status Register - REMOVED because it was redundant, same info as in IDR0 + __I uint32_t DISR; // Offset: 0x010 (R/ ) Device Interface Input Current Status Register + __I uint32_t MISR; // Offset: 0x014 (R/ ) Miscellaneous Input Current Status Register + __I uint32_t STSR; // Offset: 0x018 (R/ ) Stored Status Register + __O uint32_t UNLK; // Offset: 0x01C ( /W) OFF and MEM_RET Unlock register + __IO uint32_t PWCR; // Offset: 0x020 (R/W) Power Configuration Register + __IO uint32_t PTCR; // Offset: 0x024 (R/W) Power Mode Transition Configuration Register + uint32_t RES0[2]; // Reserved + + __IO uint32_t IMR; // Offset: 0x030 (R/W) Interrupt Mask Register + __IO uint32_t AIMR; // Offset: 0x034 (R/W) Additional Interrupt Mask Register + __IO uint32_t ISR; // Offset: 0x038 (R/W) Interrupt Status Register + __IO uint32_t AISR; // Offset: 0x03C (R/W) Additional Interrupt Status Register + __IO uint32_t IESR; // Offset: 0x040 (R/W) Input Edge Sensitivity Register + uint32_t RES1[3]; // Reserved + + __IO uint32_t FUNRR; // Offset: 0x050 (R/W) Functional Retention RAM Configuration Register + __IO uint32_t FULRR; // Offset: 0x054 (R/W) Full Retention RAM Configuration Register + __IO uint32_t MEMRR; // Offset: 0x058 (R/W) Memory Retention RAM Configuration Register + uint32_t RES2[65]; // Reserved + + __IO uint32_t EDTR0; // Offset: 0x160 (R/W) Mode Entry Delay Time Register 0 + __IO uint32_t EDTR1; // Offset: 0x164 (R/W) Mode Entry Delay Time Register 1 + uint32_t RES3[2]; // Reserved + + __IO uint32_t DCCR0; // Offset: 0x170 (R/W) Device Control Delay Configuration Register 0 + __IO uint32_t DCCR1; // Offset: 0x174 (R/W) Device Control Delay Configuration Register 1 + uint32_t RES4[910]; // Reserved + + __I uint32_t IDR0; // Offset: 0xFB0 (R/ ) PPU Identification Register 0 + __I uint32_t IDR1; // Offset: 0xFB4 (R/ ) PPU Identification Register 1 + uint32_t RES5[4]; // Reserved + + __I uint32_t IIDR; // Offset: 0xFC8 (R/ ) Implementation Identification Register + __I uint32_t AIDR; // Offset: 0xFCC (R/ ) Architecture Identification Register + + __I uint32_t PID4; // Offset: 0xFD0 (R/ ) Peripheral ID Register 4 + __I uint32_t PID5; // Offset: 0xFD4 (R/0) Peripheral ID Register 5 - Reserved + __I uint32_t PID6; // Offset: 0xFD8 (R/0) Peripheral ID Register 6 - Reserved + __I uint32_t PID7; // Offset: 0xFDC (R/0) Peripheral ID Register 7 - Reserved + __I uint32_t PID0; // Offset: 0xFE0 (R/ ) Peripheral ID Register 0 + __I uint32_t PID1; // Offset: 0xFE4 (R/ ) Peripheral ID Register 1 + __I uint32_t PID2; // Offset: 0xFE8 (R/ ) Peripheral ID Register 2 + __I uint32_t PID3; // Offset: 0xFEC (R/0) Peripheral ID Register 3 - Reserved + + __I uint32_t CID0; // Offset: 0xFF0 (R/ ) Component ID Register 0 + __I uint32_t CID1; // Offset: 0xFF4 (R/ ) Component ID Register 1 + __I uint32_t CID2; // Offset: 0xFF8 (R/ ) Component ID Register 2 + __I uint32_t CID3; // Offset: 0xFFC (R/ ) Component ID Register 3 +} PPU_TypeDef; + +typedef struct { + __I uint32_t CPUID; + uint32_t RES0[1011]; + __I uint32_t PID4; // Offset: 0xFD0 (R/ ) Peripheral ID Register 4 + __I uint32_t PID5; // Offset: 0xFD4 (RAZ) Peripheral ID Register 5 - Reserved + __I uint32_t PID6; // Offset: 0xFD8 (RAZ) Peripheral ID Register 6 - Reserved + __I uint32_t PID7; // Offset: 0xFDC (RAZ) Peripheral ID Register 7 - Reserved + __I uint32_t PID0; // Offset: 0xFE0 (R/ ) Peripheral ID Register 0 + __I uint32_t PID1; // Offset: 0xFE4 (R/ ) Peripheral ID Register 1 + __I uint32_t PID2; // Offset: 0xFE8 (R/ ) Peripheral ID Register 2 + __I uint32_t PID3; // Offset: 0xFEC (RAZ) Peripheral ID Register 3 - Reserved + + __I uint32_t CID0; // Offset: 0xFF0 (R/ ) Component ID Register 0 + __I uint32_t CID1; // Offset: 0xFF4 (R/ ) Component ID Register 1 + __I uint32_t CID2; // Offset: 0xFF8 (R/ ) Component ID Register 2 + __I uint32_t CID3; // Offset: 0xFFC (R/ ) Component ID Register 3 +} CPU_Identity_TypeDef; + + + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ +#ifdef SECURE_MODE + /* Secure Peripheral and SRAM base address */ + #define CMSDK_FLASH_BASE (0x10000000UL) + #define CMSDK_SRAM_BASE (0x30000000UL) + #define MASTER_EXP_PORT_0_BASE (0x38000000UL) + #define SSE200_PERIPH_BASE (0x50000000UL) + + #define CMSDK_RAM_BASE (0x30000000UL) + #define CMSDK_APB_BASE (0x50000000UL) + #define CMSDK_AHB_BASE (0x50010000UL) + + #define MASTER_EXP_PORT_1_BASE (0x50100000UL) + + + #define RAM_WB_BASE (0x70000000UL) + #define RAM_WT_BASE (0x90000000UL) + #define DEVICE_SH_BASE (0xB0000000UL) + #define DEVICE_NSH_BASE (0xD0000000UL) +#ifdef __ARMCC_VERSION +#define __secure_flash_size Image$$NS_USER_RRAM$$Base +#endif +#else + /* Non-secure Peripheral and SRAM base address */ + #define CMSDK_FLASH_BASE (0x00000000UL) + #define CMSDK_SRAM_BASE (0x20000000UL) + #define MASTER_EXP_PORT_0_BASE (0x28000000UL) + #define SSE200_PERIPH_BASE (0x40000000UL) + + #define CMSDK_RAM_BASE (0x20000000UL) + #define CMSDK_APB_BASE (0x40000000UL) + #define CMSDK_AHB_BASE (0x40010000UL) + + #define MASTER_EXP_PORT_1_BASE (0x40100000UL) + + #define RAM_WB_BASE (0x60000000UL) + #define RAM_WT_BASE (0x80000000UL) + #define DEVICE_SH_BASE (0xA0000000UL) + #define DEVICE_NSH_BASE (0xC0000000UL) +#ifdef __ARMCC_VERSION +#define __secure_flash_size Load$$LR$$LR_NONSECURE$$Base +#endif +#endif + +#define SYS_PPB_BASE (0xE0000000UL) +#define SYS_VEND_BASE (0xF0000000UL) + +#define ROM_SIZE 0x00010000UL +#define RRAM_BASE (CMSDK_FLASH_BASE + ROM_SIZE) +extern uint32_t __secure_flash_size; +#define FLASH_SECURE_SIZE ((uint32_t)&__secure_flash_size) +#define ROM_RRAM_SIZE 0x00090000UL +#define RAM_SECURE_SIZE 0x00004000UL +#define RAM_SIZE 0x00020000UL +#define QSPI_SIZE 0x01000000UL +#define MPC_FLS_BASE 0x50114000UL +#define MPC_QSPI_BASE 0x50115000UL +#define MPC_RAM0_BASE 0x50083000UL +#define MPC_RAM1_BASE 0x50084000UL +#define MPC_RAM2_BASE 0x50085000UL +#define MPC_RAM3_BASE 0x50086000UL + +/* APB peripherals */ +#define CMSDK_TIMER0_BASE (SSE200_PERIPH_BASE + 0x0000UL) +#define CMSDK_TIMER1_BASE (SSE200_PERIPH_BASE + 0x1000UL) +#define CMSDK_DUALTIMER_BASE (SSE200_PERIPH_BASE + 0x2000UL) +#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE) +#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL) + +#define SECURE_WATCHDOG_BASE (0x50081000UL) +#define NONSECURE_WATCHDOG_BASE (0x40081000UL) + +#define S32_WATCHDOG_BASE (SSE200_PERIPH_BASE + 0x2E000UL) +#define S32_TIMER_BASE (SSE200_PERIPH_BASE + 0x2F000UL) + +#define SEC_PRIV_CTRL_BASE 0x50080000UL +#define NONSEC_PRIV_CTRL_BASE 0x40080000UL + +/* AHB peripherals */ +#define CMSDK_GPIO0_BASE (SSE200_PERIPH_BASE + 0x100000UL) +#define CMSDK_GPIO1_BASE (SSE200_PERIPH_BASE + 0x101000UL) + +#define SYSINFO_BASE (SSE200_PERIPH_BASE + 0x20000UL) +#define SYS_CTRL_BASE 0x50021000UL + +#define MHU_0_BASE (SSE200_PERIPH_BASE + 0x3000UL) +#define MHU_1_BASE (SSE200_PERIPH_BASE + 0x4000UL) + +/* Power Peripherals - Secure Privilege Access only*/ +#define SYS_PPU_BASE 0x50022000 +#define CPU0CORE_PPU_BASE 0x50023000 +#define CPU0DBG_PPU_BASE 0x50024000 +#define CPU1CORE_PPU_BASE 0x50025000 +#define CPU1DBG_PPU_BASE 0x50026000 +#define DBG_PPU_BASE 0x50029000 +#define SRAM_BANK0_PPU_BASE 0x5002A000 +#define SRAM_BANK1_PPU_BASE 0x5002B000 +#define SRAM_BANK2_PPU_BASE 0x5002C000 +#define SRAM_BANK3_PPU_BASE 0x5002D000 +#define CRYPTO_PPU_BASE 0x50027000 +#define CORDIO_PPU_BASE 0x50028000 + +#define CPU_IDENTITY_BASE (SSE200_PERIPH_BASE + 0x1F000ul) +#define ICACHE_BASE (SSE200_PERIPH_BASE + 0x10000ul) + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) +#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) +#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) +#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE ) +#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE ) +#define SECURE_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) SECURE_WATCHDOG_BASE ) +#define NONSECURE_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) NONSECURE_WATCHDOG_BASE ) +#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE ) +#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE ) + +#define S32_TIMER ((CMSDK_TIMER_TypeDef *) S32_TIMER_BASE ) +#define S32_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) S32_WATCHDOG_BASE ) + +#define SEC_CTRL_REG ((SEC_PRIV_CTRL_TypeDef *) SEC_PRIV_CTRL_BASE ) +#define NONSEC_CTRL_REG ((NONSEC_PRIV_CTRL_TypeDef *) NONSEC_PRIV_CTRL_BASE ) + +#define SYSINFO ((SYSINFO_TypeDef *) SYSINFO_BASE ) +#define SYS_CTRL_REG ((SYS_CTRL_REG_SSE200_TypeDef *) SYS_CTRL_BASE ) + +#define MPC_FLS ((MPC_TypeDef *) MPC_FLS_BASE ) +#define MPC_QSPI ((MPC_TypeDef *) MPC_QSPI_BASE ) +#define MPC_RAM0 ((MPC_TypeDef *) MPC_RAM0_BASE ) +#define MPC_RAM1 ((MPC_TypeDef *) MPC_RAM1_BASE ) +#define MPC_RAM2 ((MPC_TypeDef *) MPC_RAM2_BASE ) +#define MPC_RAM3 ((MPC_TypeDef *) MPC_RAM3_BASE ) + +#define MHU_0 ((MHU_TypeDef *) MHU_0_BASE ) +#define MHU_1 ((MHU_TypeDef *) MHU_1_BASE ) + +#define SYS_PPU ((PPU_TypeDef *) SYS_PPU_BASE ) +#define CPU0CORE_PPU ((PPU_TypeDef *) CPU0CORE_PPU_BASE ) +#define CPU1CORE_PPU ((PPU_TypeDef *) CPU1CORE_PPU_BASE ) +#define CPU0DBG_PPU ((PPU_TypeDef *) CPU0DBG_PPU_BASE ) +#define CPU1DBG_PPU ((PPU_TypeDef *) CPU1DBG_PPU_BASE ) +#define DBG_PPU ((PPU_TypeDef *) DBG_PPU_BASE ) +#define SRAM_BANK0_PPU ((PPU_TypeDef *) SRAM_BANK0_PPU_BASE ) +#define SRAM_BANK1_PPU ((PPU_TypeDef *) SRAM_BANK1_PPU_BASE ) +#define SRAM_BANK2_PPU ((PPU_TypeDef *) SRAM_BANK2_PPU_BASE ) +#define SRAM_BANK3_PPU ((PPU_TypeDef *) SRAM_BANK3_PPU_BASE ) +#define CRYPTO_PPU ((PPU_TypeDef *) CRYPTO_PPU_BASE ) +#define CORDIO_PPU ((PPU_TypeDef *) CORDIO_PPU_BASE ) + +#define CPU_IDENTITY ((CPU_Identity_TypeDef *) CPU_IDENTITY_BASE ) +#define ICACHE ((ICACHE_TypeDef *) ICACHE_BASE ) + + +/*----------------------------- MPC (AHB5 Memory Protection Controller) -------------------------------*/ +/** + * @brief AHB5 MPC Registers + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 Control Register (R/W) */ + __I uint32_t RSVD0[3]; + __I uint32_t BLK_MAX; /*!< Offset: 0x010 Status Register (R/ ) */ + __I uint32_t BLK_CFG; /*!< Offset: 0x014 Status Register (R/ ) */ + __IO uint32_t BLK_IDX; /*!< Offset: 0x018 Control Register (R/W) */ + __IO uint32_t BLK_LUT; /*!< Offset: 0x01C Control Register (R/W) */ + __I uint32_t INT_STAT; /*!< Offset: 0x020 Status Register (R/ ) */ + __O uint32_t INT_CLEAR; /*!< Offset: 0x024 Control Register ( /W) */ + __IO uint32_t INT_EN ; /*!< Offset: 0x028 Control Register (R/W) */ + __I uint32_t INT_INFO1; /*!< Offset: 0x02C Status Register (R/ ) */ + __I uint32_t INT_INFO2; /*!< Offset: 0x030 Status Register (R/ ) */ + __I uint32_t RSVD1[999]; + __I uint32_t PIDR4; /*!< Offset: 0xFD0 Status Register (R/ ) */ + __I uint32_t PIDR5; /*!< Offset: 0xFD4 Status Register (R/ ) */ + __I uint32_t PIDR6; /*!< Offset: 0xFD8 Status Register (R/ ) */ + __I uint32_t PIDR7; /*!< Offset: 0xFDC Status Register (R/ ) */ + __I uint32_t PIDR0; /*!< Offset: 0xFE0 Status Register (R/ ) */ + __I uint32_t PIDR1; /*!< Offset: 0xFE4 Status Register (R/ ) */ + __I uint32_t PIDR2; /*!< Offset: 0xFE8 Status Register (R/ ) */ + __I uint32_t PIDR3; /*!< Offset: 0xFEC Status Register (R/ ) */ + __I uint32_t CIDR0; /*!< Offset: 0xFF0 Status Register (R/ ) */ + __I uint32_t CIDR1; /*!< Offset: 0xFF4 Status Register (R/ ) */ + __I uint32_t CIDR2; /*!< Offset: 0xFF8 Status Register (R/ ) */ + __I uint32_t CIDR3; /*!< Offset: 0xFFC Status Register (R/ ) */ + +} MPC_TypeDef; + +/* MPC CTRL Register Definitions */ +#define MPC_CTRL_CFG_SEC_RESP_Pos 4 /*!< MPC CTRL: CFG_SEC_RESP Position */ +#define MPC_CTRL_CFG_SEC_RESP_Msk (0x1ul << MPC_CTRL_CFG_SEC_RESP_Pos) /*!< MPC CTRL: CFG_SEC_RESP Mask */ + +#define MPC_CTRL_DATA_INTERFACE_GATING_REQ_Pos 6 /*!< MPC CTRL: DATA_INTERFACE_GATING_REQ Position */ +#define MPC_CTRL_DATA_INTERFACE_GATING_REQ_Msk (0x1ul << MPC_CTRL_DATA_INTERFACE_GATING_REQ_Pos) /*!< MPC CTRL: DATA_INTERFACE_GATING_REQ Mask */ + +#define MPC_CTRL_DATA_INTERFACE_GATING_ACK_Pos 7 /*!< MPC CTRL: DATA_INTERFACE_GATING_ACK Position */ +#define MPC_CTRL_DATA_INTERFACE_GATING_ACK_Msk (0x1ul << MPC_CTRL_DATA_INTERFACE_GATING_ACK_Pos) /*!< MPC CTRL: DATA_INTERFACE_GATING_ACK Mask */ + +#define MPC_CTRL_AUTO_INCREMENT_Pos 8 /*!< MPC CTRL: AUTO_INCREMENT Position */ +#define MPC_CTRL_AUTO_INCREMENT_Msk (0x1ul << MPC_CTRL_AUTO_INCREMENT_Pos) /*!< MPC CTRL: AUTO_INCREMENT Mask */ + +#define MPC_CTRL_SEC_LOCK_Pos 31 /*!< MPC CTRL: SEC_LOCK Position */ +#define MPC_CTRL_SEC_LOCK_Msk (0x1ul << MPC_CTRL_SEC_LOCK_Pos) /*!< MPC CTRL: SEC_LOCK Mask */ + +/* MPC INT_STAT Register Definitions */ +#define MPC_INT_STAT_IRQ_TRIGGERED_Pos 0 /*!< MPC INT_STAT: IRQ_TRIGGERED Position */ +#define MPC_INT_STAT_IRQ_TRIGGERED_Msk (0x1ul << MPC_INT_STAT_IRQ_TRIGGERED_Pos) /*!< MPC INT_STAT: IRQ_TRIGGERED Mask */ + +/* MPC INT_CLEAR Register Definitions */ +#define MPC_INT_CLEAR_IRQ_CLEAR_Pos 0 /*!< MPC INT_CLEAR: IRQ_CLEAR Position */ +#define MPC_INT_CLEAR_IRQ_CLEAR_Msk (0x1ul << MPC_INT_CLEAR_IRQ_CLEAR_Pos) /*!< MPC INT_CLEAR: IRQ_CLEAR Mask */ + +/* MPC INT_EN Register Definitions */ +#define MPC_INT_EN_IRQ_EN_Pos 0 /*!< MPC INT_EN: IRQ_EN Position */ +#define MPC_INT_EN_IRQ_EN_Msk (0x1ul << MPC_INT_EN_IRQ_EN_Pos) /*!< MPC INT_EN: IRQ_EN Mask */ + +/* MPC INT_INFO2 Register Definitions */ +#define MPC_INT_INFO2_HMASTER_Pos 0 /*!< MPC INT_INFO2: HMASTER Position */ +#define MPC_INT_INFO2_HMASTER_Msk (0xFFFFul << MPC_INT_INFO2_HMASTER_Pos) /*!< MPC INT_INFO2: HMASTER Mask */ + +#define MPC_INT_INFO2_HNONSEC_Pos 16 /*!< MPC INT_INFO2: HNONSEC Position */ +#define MPC_INT_INFO2_HNONSEC_Msk (0x1ul << MPC_INT_INFO2_HNONSEC_Pos) /*!< MPC INT_INFO2: HNONSEC Mask */ + +#define MPC_INT_INFO2_CFG_NS_Pos 17 /*!< MPC INT_INFO2: CFG_NS Position */ +#define MPC_INT_INFO2_CFG_NS_Msk (0x1ul << MPC_INT_INFO2_CFG_NS_Pos) /*!< MPC INT_INFO2: CFG_NS Mask */ + +/* MPC INT_SET Register Definiton */ +#define MPC_INT_SET_IRQ_SET_Pos 0 /*!< MPC INT_SET: IRQ_SET Position */ +#define MPC_INT_SET_IRQ_SET_Msk (0x1ul << MPC_INT_SET_IRQ_SET_Pos) /*!< MPC INT_SET: IRQ_SET Mask */ + +/* MPC PIDR4 Register Definition */ +#define MPC_PIDR4_JEP106_C_CODE_Pos 0 /*!< MPC PIDR4: JEP106_C_CODE Position */ +#define MPC_PIDR4_JEP106_C_CODE_Msk (0xFul << MPC_PIDR4_JEP106_C_CODE_Pos) /*!< MPC PIDR4: JEP106_C_CODE Mask */ + +#define MPC_PIDR4_BLK_COUNT_Pos 4 /*!< MPC PIDR4: BLK_COUNT Position */ +#define MPC_PIDR4_BLK_COUNT_Msk (0xFul << MPC_PIDR4_BLK_COUNT_Pos) /*!< MPC PIDR4: BLK_COUNT Mask */ + +/* MPC PIDR0 Register Definition */ +#define MPC_PIDR0_PART_NUM_Pos 0 /*!< MPC PIDR0: PART_NUM Position */ +#define MPC_PIDR0_PART_NUM_Msk (0xFFul << MPC_PIDR0_PART_NUM_Pos) /*!< MPC PIDR0: PART_NUM Mask */ + +/* MPC PIDR1 Register Definition */ +#define MPC_PIDR1_PART_NUM_Pos 0 /*!< MPC PIDR1: PART_NUM Position */ +#define MPC_PIDR1_PART_NUM_Msk (0xFul << MPC_PIDR1_PART_NUM_Pos) /*!< MPC PIDR1: PART_NUM Mask */ + +#define MPC_PIDR1_JEP106_ID_3_0_Pos 4 /*!< MPC PIDR1: JEP106_ID_3_0 Position */ +#define MPC_PIDR1_JEP106_ID_3_0_Msk (0xFul << MPC_PIDR1_JEP106_ID_3_0_Pos) /*!< MPC PIDR1: JEP106_ID_3_0 Mask */ + +/* MPC PIDR2 Register Definition*/ +#define MPC_PIDR2_JEP106_ID_6_4_Pos 0 /*!< MPC PIDR1: JEP106_ID_6_4 Position */ +#define MPC_PIDR2_JEP106_ID_6_4_Msk (0x7ul << MPC_PIDR2_JEP106_ID_6_4_Pos) /*!< MPC PIDR2: JEP106_ID_6_4 Mask */ + +#define MPC_PIDR2_JEDEC_Pos 3 /*!< MPC PIDR2: JEDEC Position */ +#define MPC_PIDR2_JEDEC_Msk (0x1ul << MPC_PIDR2_JEDEC_Pos) /*!< MPC PIDR2: JEDEC Mask */ + +#define MPC_PIDR2_REV_Pos 4 /*!< MPC PIDR2: REV Position */ +#define MPC_PIDR2_REV_Msk (0xFul << MPC_PIDR2_REVISION_Pos) /*!< MPC PIDR2: REV Mask */ + +/* MPC PIDR3 Register Definition */ +#define MPC_PIDR3_CMOD_Pos 0 /*!< MPC PIDR3: CMOD Position */ +#define MPC_PIDR3_CMOD_Msk (0xFul << MPC_PIDR3_CMOD_Pos) /*!< MPC PIDR3: CMOD Mask */ + +#define MPC_PIDR3_ECO_REV_Pos 4 /*!< MPC PIDR3: ECO_REV Position */ +#define MPC_PIDR3_ECO_REV_Msk (0xFul << MPC_PIDR3_ECO_REV_Pos) /*!< MPC PIDR3: ECO_REV Mask */ + +/*@}*/ /* end of group MPC */ + +/*----------------------------- SECURE PRIVILEGE CONTROL REGISTER -------------------------------------------------*/ +typedef struct +{ +__IOM uint32_t SPCSECCTRL; /* Offset: 0x0 (read-write) SPCSECCTRL Register */ +__IOM uint32_t BUSWAIT; /* Offset: 0x4 (read-write) BUSWAIT Register */ + uint32_t RESERVED0[2]; +__IOM uint32_t SECRESPCFG; /* Offset: 0x10 (read-write) SECRESPCFG Register */ +__IOM uint32_t NSCCFG; /* Offset: 0x14 (read-write) NSCCFG Register */ + uint32_t RESERVED1[1]; +__IM uint32_t SECMPCINTSTATUS; /* Offset: 0x1C (read-only) SECMPCINTSTATUS Register */ +__IM uint32_t SECPPCINTSTAT; /* Offset: 0x20 (read-only) SECPPCINTSTAT Register */ +__OM uint32_t SECPPCINTCLR; /* Offset: 0x24 (write-only) SECPPCINTCLR Register */ +__IOM uint32_t SECPPCINTEN; /* Offset: 0x28 (read-write) SECPPCINTEN Register */ + uint32_t RESERVED2[1]; +__IM uint32_t SECMSCINTSTAT; /* Offset: 0x30 (read-only) SECMSCINTSTAT Register */ +__OM uint32_t SECMSCINTCLR; /* Offset: 0x34 (write-only) SECMSCINTCLR Register */ +__IOM uint32_t SECMSCINTEN; /* Offset: 0x38 (read-write) SECMSCINTEN Register */ + uint32_t RESERVED3[1]; +__IM uint32_t BRGINTSTAT; /* Offset: 0x40 (read-only) BRGINTSTAT Register */ +__OM uint32_t BRGINTCLR; /* Offset: 0x44 (write-only) BRGINTCLR Register */ +__IOM uint32_t BRGINTEN; /* Offset: 0x48 (read-write) BRGINTEN Register */ + uint32_t RESERVED4[5]; +__IOM uint32_t AHBNSPPCEXP0; /* Offset: 0x60 (read-write) AHBNSPPCEXP0 Register */ +__IOM uint32_t AHBNSPPCEXP1; /* Offset: 0x64 (read-write) AHBNSPPCEXP1 Register */ +__IOM uint32_t AHBNSPPCEXP2; /* Offset: 0x68 (read-write) AHBNSPPCEXP2 Register */ +__IOM uint32_t AHBNSPPCEXP3; /* Offset: 0x6C (read-write) AHBNSPPCEXP3 Register */ +__IOM uint32_t APBNSPPC0; /* Offset: 0x70 (read-write) APBNSPPC0 Register */ +__IOM uint32_t APBNSPPC1; /* Offset: 0x74 (read-write) APBNSPPC1 Register */ + uint32_t RESERVED5[2]; +__IOM uint32_t APBNSPPCEXP0; /* Offset: 0x80 (read-write) APBNSPPCEXP0 Register */ +__IOM uint32_t APBNSPPCEXP1; /* Offset: 0x84 (read-write) APBNSPPCEXP1 Register */ +__IOM uint32_t APBNSPPCEXP2; /* Offset: 0x88 (read-write) APBNSPPCEXP2 Register */ +__IOM uint32_t APBNSPPCEXP3; /* Offset: 0x8C (read-write) APBNSPPCEXP3 Register */ + uint32_t RESERVED6[4]; +__IOM uint32_t AHBSPPPCEXP0; /* Offset: 0xA0 (read-write) AHBSPPPCEXP0 Register */ +__IOM uint32_t AHBSPPPCEXP1; /* Offset: 0xA4 (read-write) AHBSPPPCEXP1 Register */ +__IOM uint32_t AHBSPPPCEXP2; /* Offset: 0xA8 (read-write) AHBSPPPCEXP2 Register */ +__IOM uint32_t AHBSPPPCEXP3; /* Offset: 0xAC (read-write) AHBSPPPCEXP3 Register */ +__IOM uint32_t APBSPPPC0; /* Offset: 0xB0 (read-write) APBSPPPC0 Register */ +__IOM uint32_t APBSPPPC1; /* Offset: 0xB4 (read-write) APBSPPPC1 Register */ + uint32_t RESERVED7[2]; +__IOM uint32_t APBSPPPCEXP0; /* Offset: 0xC0 (read-write) APBSPPPCEXP0 Register */ +__IOM uint32_t APBSPPPCEXP1; /* Offset: 0xC4 (read-write) APBSPPPCEXP1 Register */ +__IOM uint32_t APBSPPPCEXP2; /* Offset: 0xC8 (read-write) APBSPPPCEXP2 Register */ +__IOM uint32_t APBSPPPCEXP3; /* Offset: 0xCC (read-write) APBSPPPCEXP3 Register */ +__IOM uint32_t NSMSCEXP; /* Offset: 0xD0 (read-write) NSMSCEXP Register */ + uint32_t RESERVED8[959]; +__IM uint32_t PIDR4; /* Offset: 0xFD0 (read-only) PIDR4 Register */ + uint32_t RESERVED9[3]; +__IM uint32_t PIDR0; /* Offset: 0xFE0 (read-only) PIDR0 Register */ +__IM uint32_t PIDR1; /* Offset: 0xFE4 (read-only) PIDR1 Register */ +__IM uint32_t PIDR2; /* Offset: 0xFE8 (read-only) PIDR2 Register */ +__IM uint32_t PIDR3; /* Offset: 0xFEC (read-only) PIDR3 Register */ +__IM uint32_t CIDR0; /* Offset: 0xFF0 (read-only) CIDR0 Register */ +__IM uint32_t CIDR1; /* Offset: 0xFF4 (read-only) CIDR1 Register */ +__IM uint32_t CIDR2; /* Offset: 0xFF8 (read-only) CIDR2 Register */ +__IM uint32_t CIDR3; /* Offset: 0xFFC (read-only) CIDR3 Register */ +}SEC_PRIV_CTRL_TypeDef; + +/* SEC_PRIV_CTRL SPCSECCTRL Register Definitions */ +#define SEC_PRIV_CTRL_SPCSECCTRL_SPCSECCFGLOCK_Pos 0 /* SEC_PRIV_CTRL SPCSECCTRL: SPCSECCFGLOCK Positions */ +#define SEC_PRIV_CTRL_SPCSECCTRL_SPCSECCFGLOCK_Msk (0x1UL /*<< SEC_PRIV_CTRL_SPCSECCTRL_SPCSECCFGLOCK_Pos*/) /* SEC_PRIV_CTRL SPCSECCTRL: SPCSECCFGLOCK Mask */ + +/* SEC_PRIV_CTRL BUSWAIT Register Definitions */ +#define SEC_PRIV_CTRL_BUSWAIT_ACC_WAITN_Pos 0 /* SEC_PRIV_CTRL BUSWAIT: ACC_WAITN Positions */ +#define SEC_PRIV_CTRL_BUSWAIT_ACC_WAITN_Msk (0x1UL /*<< SEC_PRIV_CTRL_BUSWAIT_ACC_WAITN_Pos*/) /* SEC_PRIV_CTRL BUSWAIT: ACC_WAITN Mask */ + +/* SEC_PRIV_CTRL SECRESPCFG Register Definitions */ +#define SEC_PRIV_CTRL_SECRESPCFG_SECRESPCFG_Pos 0 /* SEC_PRIV_CTRL SECRESPCFG: SECRESPCFG Positions */ +#define SEC_PRIV_CTRL_SECRESPCFG_SECRESPCFG_Msk (0x1UL /*<< SEC_PRIV_CTRL_SECRESPCFG_SECRESPCFG_Pos*/) /* SEC_PRIV_CTRL SECRESPCFG: SECRESPCFG Mask */ + +/* SEC_PRIV_CTRL NSCCFG Register Definitions */ +#define SEC_PRIV_CTRL_NSCCFG_RAMNSC_Pos 1 /* SEC_PRIV_CTRL NSCCFG: RAMNSC Positions */ +#define SEC_PRIV_CTRL_NSCCFG_RAMNSC_Msk (0x1UL << SEC_PRIV_CTRL_NSCCFG_RAMNSC_Pos) /* SEC_PRIV_CTRL NSCCFG: RAMNSC Mask */ + +#define SEC_PRIV_CTRL_NSCCFG_CODENSC_Pos 0 /* SEC_PRIV_CTRL NSCCFG: CODENSC Positions */ +#define SEC_PRIV_CTRL_NSCCFG_CODENSC_Msk (0x1UL /*<< SEC_PRIV_CTRL_NSCCFG_CODENSC_Pos*/) /* SEC_PRIV_CTRL NSCCFG: CODENSC Mask */ + +/* SEC_PRIV_CTRL SECMPCINTSTATUS Register Definitions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS15_Pos 31 /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS15 Positions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS15_Msk (0x1UL << SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS15_Pos) /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS15 Mask */ + +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS14_Pos 30 /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS14 Positions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS14_Msk (0x1UL << SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS14_Pos) /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS14 Mask */ + +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS13_Pos 29 /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS13 Positions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS13_Msk (0x1UL << SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS13_Pos) /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS13 Mask */ + +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS12_Pos 28 /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS12 Positions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS12_Msk (0x1UL << SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS12_Pos) /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS12 Mask */ + +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS11_Pos 27 /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS11 Positions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS11_Msk (0x1UL << SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS11_Pos) /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS11 Mask */ + +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS10_Pos 26 /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS10 Positions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS10_Msk (0x1UL << SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS10_Pos) /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS10 Mask */ + +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS9_Pos 25 /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS9 Positions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS9_Msk (0x1UL << SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS9_Pos) /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS9 Mask */ + +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS8_Pos 24 /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS8 Positions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS8_Msk (0x1UL << SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS8_Pos) /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS8 Mask */ + +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS7_Pos 23 /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS7 Positions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS7_Msk (0x1UL << SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS7_Pos) /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS7 Mask */ + +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS6_Pos 22 /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS6 Positions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS6_Msk (0x1UL << SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS6_Pos) /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS6 Mask */ + +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS5_Pos 21 /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS5 Positions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS5_Msk (0x1UL << SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS5_Pos) /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS5 Mask */ + +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS4_Pos 20 /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS4 Positions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS4_Msk (0x1UL << SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS4_Pos) /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS4 Mask */ + +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS3_Pos 19 /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS3 Positions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS3_Msk (0x1UL << SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS3_Pos) /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS3 Mask */ + +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS2_Pos 18 /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS2 Positions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS2_Msk (0x1UL << SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS2_Pos) /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS2 Mask */ + +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS1_Pos 17 /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS1 Positions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS1_Msk (0x1UL << SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS1_Pos) /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS1 Mask */ + +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS0_Pos 16 /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS0 Positions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS0_Msk (0x1UL << SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCEXP_STATUS0_Pos) /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCEXP_STATUS0 Mask */ + +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCSRAM3_STATUS_Pos 3 /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCSRAM3_STATUS Positions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCSRAM3_STATUS_Msk (0x1UL << SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCSRAM3_STATUS_Pos) /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCSRAM3_STATUS Mask */ + +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCSRAM2_STATUS_Pos 2 /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCSRAM2_STATUS Positions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCSRAM2_STATUS_Msk (0x1UL << SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCSRAM2_STATUS_Pos) /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCSRAM2_STATUS Mask */ + +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCSRAM1_STATUS_Pos 1 /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCSRAM1_STATUS Positions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCSRAM1_STATUS_Msk (0x1UL << SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCSRAM1_STATUS_Pos) /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCSRAM1_STATUS Mask */ + +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCSRAM0_STATUS_Pos 0 /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCSRAM0_STATUS Positions */ +#define SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCSRAM0_STATUS_Msk (0x1UL /*<< SEC_PRIV_CTRL_SECMPCINTSTATUS_S_MPCSRAM0_STATUS_Pos*/) /* SEC_PRIV_CTRL SECMPCINTSTATUS: S_MPCSRAM0_STATUS Mask */ + +/* SEC_PRIV_CTRL SECPPCINTSTAT Register Definitions */ +#define SEC_PRIV_CTRL_SECPPCINTSTAT_S_AHBPPCEXP_STATUS_Pos 20 /* SEC_PRIV_CTRL SECPPCINTSTAT: S_AHBPPCEXP_STATUS Positions */ +#define SEC_PRIV_CTRL_SECPPCINTSTAT_S_AHBPPCEXP_STATUS_Msk (0xFUL << SEC_PRIV_CTRL_SECPPCINTSTAT_S_AHBPPCEXP_STATUS_Pos) /* SEC_PRIV_CTRL SECPPCINTSTAT: S_AHBPPCEXP_STATUS Mask */ + +#define SEC_PRIV_CTRL_SECPPCINTSTAT_S_APBPPCEXP_STATUS_Pos 4 /* SEC_PRIV_CTRL SECPPCINTSTAT: S_APBPPCEXP_STATUS Positions */ +#define SEC_PRIV_CTRL_SECPPCINTSTAT_S_APBPPCEXP_STATUS_Msk (0xFUL << SEC_PRIV_CTRL_SECPPCINTSTAT_S_APBPPCEXP_STATUS_Pos) /* SEC_PRIV_CTRL SECPPCINTSTAT: S_APBPPCEXP_STATUS Mask */ + +#define SEC_PRIV_CTRL_SECPPCINTSTAT_S_APBPPC1PERIP_STATUS_Pos 1 /* SEC_PRIV_CTRL SECPPCINTSTAT: S_APBPPC1PERIP_STATUS Positions */ +#define SEC_PRIV_CTRL_SECPPCINTSTAT_S_APBPPC1PERIP_STATUS_Msk (0x1UL << SEC_PRIV_CTRL_SECPPCINTSTAT_S_APBPPC1PERIP_STATUS_Pos) /* SEC_PRIV_CTRL SECPPCINTSTAT: S_APBPPC1PERIP_STATUS Mask */ + +#define SEC_PRIV_CTRL_SECPPCINTSTAT_S_APBPPC0PERIP_STATUS_Pos 0 /* SEC_PRIV_CTRL SECPPCINTSTAT: S_APBPPC0PERIP_STATUS Positions */ +#define SEC_PRIV_CTRL_SECPPCINTSTAT_S_APBPPC0PERIP_STATUS_Msk (0x1UL /*<< SEC_PRIV_CTRL_SECPPCINTSTAT_S_APBPPC0PERIP_STATUS_Pos*/) /* SEC_PRIV_CTRL SECPPCINTSTAT: S_APBPPC0PERIP_STATUS Mask */ + +/* SEC_PRIV_CTRL SECPPCINTCLR Register Definitions */ +#define SEC_PRIV_CTRL_SECPPCINTCLR_S_AHBPPCEXP_CLR_Pos 20 /* SEC_PRIV_CTRL SECPPCINTCLR: S_AHBPPCEXP_CLR Positions */ +#define SEC_PRIV_CTRL_SECPPCINTCLR_S_AHBPPCEXP_CLR_Msk (0xFUL << SEC_PRIV_CTRL_SECPPCINTCLR_S_AHBPPCEXP_CLR_Pos) /* SEC_PRIV_CTRL SECPPCINTCLR: S_AHBPPCEXP_CLR Mask */ + +#define SEC_PRIV_CTRL_SECPPCINTCLR_S_APBPPCEXP_CLR_Pos 4 /* SEC_PRIV_CTRL SECPPCINTCLR: S_APBPPCEXP_CLR Positions */ +#define SEC_PRIV_CTRL_SECPPCINTCLR_S_APBPPCEXP_CLR_Msk (0xFUL << SEC_PRIV_CTRL_SECPPCINTCLR_S_APBPPCEXP_CLR_Pos) /* SEC_PRIV_CTRL SECPPCINTCLR: S_APBPPCEXP_CLR Mask */ + +#define SEC_PRIV_CTRL_SECPPCINTCLR_S_APBPPC1PERIP_CLR_Pos 1 /* SEC_PRIV_CTRL SECPPCINTCLR: S_APBPPC1PERIP_CLR Positions */ +#define SEC_PRIV_CTRL_SECPPCINTCLR_S_APBPPC1PERIP_CLR_Msk (0x1UL << SEC_PRIV_CTRL_SECPPCINTCLR_S_APBPPC1PERIP_CLR_Pos) /* SEC_PRIV_CTRL SECPPCINTCLR: S_APBPPC1PERIP_CLR Mask */ + +#define SEC_PRIV_CTRL_SECPPCINTCLR_S_APBPPC0PERIP_CLR_Pos 0 /* SEC_PRIV_CTRL SECPPCINTCLR: S_APBPPC0PERIP_CLR Positions */ +#define SEC_PRIV_CTRL_SECPPCINTCLR_S_APBPPC0PERIP_CLR_Msk (0x1UL /*<< SEC_PRIV_CTRL_SECPPCINTCLR_S_APBPPC0PERIP_CLR_Pos*/) /* SEC_PRIV_CTRL SECPPCINTCLR: S_APBPPC0PERIP_CLR Mask */ + +/* SEC_PRIV_CTRL SECPPCINTEN Register Definitions */ +#define SEC_PRIV_CTRL_SECPPCINTEN_S_AHBPPCEXP_EN_Pos 20 /* SEC_PRIV_CTRL SECPPCINTEN: S_AHBPPCEXP_EN Positions */ +#define SEC_PRIV_CTRL_SECPPCINTEN_S_AHBPPCEXP_EN_Msk (0xFUL << SEC_PRIV_CTRL_SECPPCINTEN_S_AHBPPCEXP_EN_Pos) /* SEC_PRIV_CTRL SECPPCINTEN: S_AHBPPCEXP_EN Mask */ + +#define SEC_PRIV_CTRL_SECPPCINTEN_S_APBPPCEXP_EN_Pos 4 /* SEC_PRIV_CTRL SECPPCINTEN: S_APBPPCEXP_EN Positions */ +#define SEC_PRIV_CTRL_SECPPCINTEN_S_APBPPCEXP_EN_Msk (0xFUL << SEC_PRIV_CTRL_SECPPCINTEN_S_APBPPCEXP_EN_Pos) /* SEC_PRIV_CTRL SECPPCINTEN: S_APBPPCEXP_EN Mask */ + +#define SEC_PRIV_CTRL_SECPPCINTEN_S_APBPPC1PERIP_EN_Pos 1 /* SEC_PRIV_CTRL SECPPCINTEN: S_APBPPC1PERIP_EN Positions */ +#define SEC_PRIV_CTRL_SECPPCINTEN_S_APBPPC1PERIP_EN_Msk (0x1UL << SEC_PRIV_CTRL_SECPPCINTEN_S_APBPPC1PERIP_EN_Pos) /* SEC_PRIV_CTRL SECPPCINTEN: S_APBPPC1PERIP_EN Mask */ + +#define SEC_PRIV_CTRL_SECPPCINTEN_S_APBPPC0PERIP_EN_Pos 0 /* SEC_PRIV_CTRL SECPPCINTEN: S_APBPPC0PERIP_EN Positions */ +#define SEC_PRIV_CTRL_SECPPCINTEN_S_APBPPC0PERIP_EN_Msk (0x1UL /*<< SEC_PRIV_CTRL_SECPPCINTEN_S_APBPPC0PERIP_EN_Pos*/) /* SEC_PRIV_CTRL SECPPCINTEN: S_APBPPC0PERIP_EN Mask */ + +/* SEC_PRIV_CTRL SECMSCINTSTAT Register Definitions */ +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS15_Pos 31 /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS15 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS15_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS15_Pos) /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS15 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS14_Pos 30 /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS14 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS14_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS14_Pos) /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS14 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS13_Pos 29 /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS13 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS13_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS13_Pos) /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS13 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS12_Pos 28 /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS12 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS12_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS12_Pos) /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS12 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS11_Pos 27 /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS11 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS11_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS11_Pos) /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS11 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS10_Pos 26 /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS10 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS10_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS10_Pos) /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS10 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS9_Pos 25 /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS9 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS9_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS9_Pos) /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS9 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS8_Pos 24 /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS8 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS8_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS8_Pos) /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS8 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS7_Pos 23 /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS7 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS7_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS7_Pos) /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS7 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS6_Pos 22 /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS6 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS6_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS6_Pos) /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS6 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS5_Pos 21 /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS5 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS5_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS5_Pos) /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS5 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS4_Pos 20 /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS4 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS4_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS4_Pos) /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS4 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS3_Pos 19 /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS3 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS3_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS3_Pos) /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS3 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS2_Pos 18 /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS2 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS2_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS2_Pos) /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS2 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS1_Pos 17 /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS1 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS1_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS1_Pos) /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS1 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS0_Pos 16 /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS0 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS0_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSCEXP_STATUS0_Pos) /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSCEXP_STATUS0 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSC_CRYPTO_STATUS_Pos 0 /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSC_CRYPTO_STATUS Positions */ +#define SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSC_CRYPTO_STATUS_Msk (0x1UL /*<< SEC_PRIV_CTRL_SECMSCINTSTAT_S_MSC_CRYPTO_STATUS_Pos*/) /* SEC_PRIV_CTRL SECMSCINTSTAT: S_MSC_CRYPTO_STATUS Mask */ + +/* SEC_PRIV_CTRL SECMSCINTCLR Register Definitions */ +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR15_Pos 31 /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR15 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR15_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR15_Pos) /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR15 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR14_Pos 30 /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR14 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR14_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR14_Pos) /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR14 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR13_Pos 29 /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR13 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR13_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR13_Pos) /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR13 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR12_Pos 28 /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR12 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR12_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR12_Pos) /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR12 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR11_Pos 27 /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR11 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR11_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR11_Pos) /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR11 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR10_Pos 26 /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR10 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR10_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR10_Pos) /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR10 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR9_Pos 25 /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR9 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR9_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR9_Pos) /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR9 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR8_Pos 24 /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR8 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR8_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR8_Pos) /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR8 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR7_Pos 23 /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR7 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR7_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR7_Pos) /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR7 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR6_Pos 22 /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR6 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR6_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR6_Pos) /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR6 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR5_Pos 21 /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR5 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR5_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR5_Pos) /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR5 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR4_Pos 20 /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR4 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR4_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR4_Pos) /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR4 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR3_Pos 19 /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR3 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR3_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR3_Pos) /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR3 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR2_Pos 18 /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR2 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR2_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR2_Pos) /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR2 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR1_Pos 17 /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR1 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR1_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR1_Pos) /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR1 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR0_Pos 16 /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR0 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR0_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTCLR_S_MSCEXP_CLR0_Pos) /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSCEXP_CLR0 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSC_CRYPTO_CLR_Pos 0 /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSC_CRYPTO_CLR Positions */ +#define SEC_PRIV_CTRL_SECMSCINTCLR_S_MSC_CRYPTO_CLR_Msk (0x1UL /*<< SEC_PRIV_CTRL_SECMSCINTCLR_S_MSC_CRYPTO_CLR_Pos*/) /* SEC_PRIV_CTRL SECMSCINTCLR: S_MSC_CRYPTO_CLR Mask */ + +/* SEC_PRIV_CTRL SECMSCINTEN Register Definitions */ +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN15_Pos 31 /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN15 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN15_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN15_Pos) /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN15 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN14_Pos 30 /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN14 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN14_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN14_Pos) /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN14 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN13_Pos 29 /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN13 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN13_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN13_Pos) /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN13 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN12_Pos 28 /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN12 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN12_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN12_Pos) /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN12 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN11_Pos 27 /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN11 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN11_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN11_Pos) /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN11 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN10_Pos 26 /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN10 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN10_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN10_Pos) /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN10 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN9_Pos 25 /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN9 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN9_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN9_Pos) /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN9 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN8_Pos 24 /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN8 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN8_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN8_Pos) /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN8 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN7_Pos 23 /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN7 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN7_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN7_Pos) /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN7 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN6_Pos 22 /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN6 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN6_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN6_Pos) /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN6 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN5_Pos 21 /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN5 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN5_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN5_Pos) /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN5 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN4_Pos 20 /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN4 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN4_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN4_Pos) /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN4 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN3_Pos 19 /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN3 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN3_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN3_Pos) /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN3 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN2_Pos 18 /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN2 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN2_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN2_Pos) /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN2 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN1_Pos 17 /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN1 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN1_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN1_Pos) /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN1 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN0_Pos 16 /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN0 Positions */ +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN0_Msk (0x1UL << SEC_PRIV_CTRL_SECMSCINTEN_S_MSCEXP_EN0_Pos) /* SEC_PRIV_CTRL SECMSCINTEN: S_MSCEXP_EN0 Mask */ + +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSC_CRYPTO_EN_Pos 0 /* SEC_PRIV_CTRL SECMSCINTEN: S_MSC_CRYPTO_EN Positions */ +#define SEC_PRIV_CTRL_SECMSCINTEN_S_MSC_CRYPTO_EN_Msk (0x1UL /*<< SEC_PRIV_CTRL_SECMSCINTEN_S_MSC_CRYPTO_EN_Pos*/) /* SEC_PRIV_CTRL SECMSCINTEN: S_MSC_CRYPTO_EN Mask */ + +/* SEC_PRIV_CTRL BRGINTSTAT Register Definitions */ +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS15_Pos 31 /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS15 Positions */ +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS15_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS15_Pos) /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS15 Mask */ + +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS14_Pos 30 /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS14 Positions */ +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS14_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS14_Pos) /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS14 Mask */ + +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS13_Pos 29 /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS13 Positions */ +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS13_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS13_Pos) /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS13 Mask */ + +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS12_Pos 28 /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS12 Positions */ +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS12_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS12_Pos) /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS12 Mask */ + +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS11_Pos 27 /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS11 Positions */ +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS11_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS11_Pos) /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS11 Mask */ + +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS10_Pos 26 /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS10 Positions */ +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS10_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS10_Pos) /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS10 Mask */ + +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS9_Pos 25 /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS9 Positions */ +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS9_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS9_Pos) /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS9 Mask */ + +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS8_Pos 24 /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS8 Positions */ +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS8_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS8_Pos) /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS8 Mask */ + +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS7_Pos 23 /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS7 Positions */ +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS7_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS7_Pos) /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS7 Mask */ + +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS6_Pos 22 /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS6 Positions */ +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS6_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS6_Pos) /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS6 Mask */ + +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS5_Pos 21 /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS5 Positions */ +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS5_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS5_Pos) /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS5 Mask */ + +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS4_Pos 20 /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS4 Positions */ +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS4_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS4_Pos) /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS4 Mask */ + +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS3_Pos 19 /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS3 Positions */ +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS3_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS3_Pos) /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS3 Mask */ + +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS2_Pos 18 /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS2 Positions */ +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS2_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS2_Pos) /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS2 Mask */ + +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS1_Pos 17 /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS1 Positions */ +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS1_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS1_Pos) /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS1 Mask */ + +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS0_Pos 16 /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS0 Positions */ +#define SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS0_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTSTAT_BRGEXP_STATUS0_Pos) /* SEC_PRIV_CTRL BRGINTSTAT: BRGEXP_STATUS0 Mask */ + +#define SEC_PRIV_CTRL_BRGINTSTAT_BRG_CPU1SYS_STATUS_Pos 0 /* SEC_PRIV_CTRL BRGINTSTAT: BRG_CPU1SYS_STATUS Positions */ +#define SEC_PRIV_CTRL_BRGINTSTAT_BRG_CPU1SYS_STATUS_Msk (0x1UL /*<< SEC_PRIV_CTRL_BRGINTSTAT_BRG_CPU1SYS_STATUS_Pos*/) /* SEC_PRIV_CTRL BRGINTSTAT: BRG_CPU1SYS_STATUS Mask */ + +/* SEC_PRIV_CTRL BRGINTCLR Register Definitions */ +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR15_Pos 31 /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR15 Positions */ +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR15_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR15_Pos) /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR15 Mask */ + +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR14_Pos 30 /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR14 Positions */ +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR14_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR14_Pos) /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR14 Mask */ + +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR13_Pos 29 /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR13 Positions */ +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR13_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR13_Pos) /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR13 Mask */ + +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR12_Pos 28 /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR12 Positions */ +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR12_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR12_Pos) /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR12 Mask */ + +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR11_Pos 27 /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR11 Positions */ +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR11_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR11_Pos) /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR11 Mask */ + +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR10_Pos 26 /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR10 Positions */ +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR10_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR10_Pos) /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR10 Mask */ + +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR9_Pos 25 /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR9 Positions */ +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR9_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR9_Pos) /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR9 Mask */ + +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR8_Pos 24 /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR8 Positions */ +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR8_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR8_Pos) /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR8 Mask */ + +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR7_Pos 23 /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR7 Positions */ +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR7_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR7_Pos) /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR7 Mask */ + +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR6_Pos 22 /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR6 Positions */ +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR6_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR6_Pos) /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR6 Mask */ + +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR5_Pos 21 /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR5 Positions */ +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR5_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR5_Pos) /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR5 Mask */ + +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR4_Pos 20 /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR4 Positions */ +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR4_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR4_Pos) /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR4 Mask */ + +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR3_Pos 19 /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR3 Positions */ +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR3_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR3_Pos) /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR3 Mask */ + +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR2_Pos 18 /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR2 Positions */ +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR2_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR2_Pos) /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR2 Mask */ + +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR1_Pos 17 /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR1 Positions */ +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR1_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR1_Pos) /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR1 Mask */ + +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR0_Pos 16 /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR0 Positions */ +#define SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR0_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTCLR_BRGEXP_CLR0_Pos) /* SEC_PRIV_CTRL BRGINTCLR: BRGEXP_CLR0 Mask */ + +#define SEC_PRIV_CTRL_BRGINTCLR_BRG_CPU1SYS_CLR_Pos 0 /* SEC_PRIV_CTRL BRGINTCLR: BRG_CPU1SYS_CLR Positions */ +#define SEC_PRIV_CTRL_BRGINTCLR_BRG_CPU1SYS_CLR_Msk (0x1UL /*<< SEC_PRIV_CTRL_BRGINTCLR_BRG_CPU1SYS_CLR_Pos*/) /* SEC_PRIV_CTRL BRGINTCLR: BRG_CPU1SYS_CLR Mask */ + +/* SEC_PRIV_CTRL BRGINTEN Register Definitions */ +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN15_Pos 31 /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN15 Positions */ +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN15_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN15_Pos) /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN15 Mask */ + +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN14_Pos 30 /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN14 Positions */ +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN14_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN14_Pos) /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN14 Mask */ + +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN13_Pos 29 /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN13 Positions */ +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN13_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN13_Pos) /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN13 Mask */ + +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN12_Pos 28 /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN12 Positions */ +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN12_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN12_Pos) /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN12 Mask */ + +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN11_Pos 27 /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN11 Positions */ +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN11_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN11_Pos) /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN11 Mask */ + +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN10_Pos 26 /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN10 Positions */ +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN10_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN10_Pos) /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN10 Mask */ + +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN9_Pos 25 /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN9 Positions */ +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN9_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN9_Pos) /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN9 Mask */ + +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN8_Pos 24 /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN8 Positions */ +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN8_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN8_Pos) /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN8 Mask */ + +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN7_Pos 23 /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN7 Positions */ +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN7_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN7_Pos) /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN7 Mask */ + +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN6_Pos 22 /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN6 Positions */ +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN6_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN6_Pos) /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN6 Mask */ + +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN5_Pos 21 /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN5 Positions */ +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN5_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN5_Pos) /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN5 Mask */ + +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN4_Pos 20 /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN4 Positions */ +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN4_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN4_Pos) /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN4 Mask */ + +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN3_Pos 19 /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN3 Positions */ +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN3_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN3_Pos) /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN3 Mask */ + +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN2_Pos 18 /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN2 Positions */ +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN2_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN2_Pos) /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN2 Mask */ + +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN1_Pos 17 /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN1 Positions */ +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN1_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN1_Pos) /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN1 Mask */ + +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN0_Pos 16 /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN0 Positions */ +#define SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN0_Msk (0x1UL << SEC_PRIV_CTRL_BRGINTEN_BRGEXP_EN0_Pos) /* SEC_PRIV_CTRL BRGINTEN: BRGEXP_EN0 Mask */ + +#define SEC_PRIV_CTRL_BRGINTEN_BRG_CPU1SYS_EN_Pos 0 /* SEC_PRIV_CTRL BRGINTEN: BRG_CPU1SYS_EN Positions */ +#define SEC_PRIV_CTRL_BRGINTEN_BRG_CPU1SYS_EN_Msk (0x1UL /*<< SEC_PRIV_CTRL_BRGINTEN_BRG_CPU1SYS_EN_Pos*/) /* SEC_PRIV_CTRL BRGINTEN: BRG_CPU1SYS_EN Mask */ + +/* SEC_PRIV_CTRL AHBNSPPCEXP0 Register Definitions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP015_Pos 15 /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP015 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP015_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP015_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP015 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP014_Pos 14 /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP014 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP014_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP014_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP014 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP013_Pos 13 /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP013 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP013_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP013_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP013 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP012_Pos 12 /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP012 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP012_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP012_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP012 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP011_Pos 11 /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP011 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP011_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP011_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP011 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP010_Pos 10 /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP010 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP010_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP010_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP010 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP09_Pos 9 /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP09 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP09_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP09_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP09 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP08_Pos 8 /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP08 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP08_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP08_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP08 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP07_Pos 7 /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP07 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP07_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP07_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP07 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP06_Pos 6 /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP06 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP06_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP06_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP06 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP05_Pos 5 /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP05 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP05_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP05_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP05 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP04_Pos 4 /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP04 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP04_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP04_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP04 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP03_Pos 3 /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP03 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP03_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP03_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP03 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP02_Pos 2 /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP02 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP02_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP02_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP02 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP01_Pos 1 /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP01 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP01_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP01_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP01 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP00_Pos 0 /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP00 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP00_Msk (0x1UL /*<< SEC_PRIV_CTRL_AHBNSPPCEXP0_AHBNSPPCEXP00_Pos*/) /* SEC_PRIV_CTRL AHBNSPPCEXP0: AHBNSPPCEXP00 Mask */ + +/* SEC_PRIV_CTRL AHBNSPPCEXP1 Register Definitions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP115_Pos 15 /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP115 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP115_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP115_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP115 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP114_Pos 14 /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP114 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP114_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP114_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP114 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP113_Pos 13 /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP113 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP113_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP113_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP113 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP112_Pos 12 /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP112 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP112_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP112_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP112 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP111_Pos 11 /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP111 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP111_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP111_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP111 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP110_Pos 10 /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP110 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP110_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP110_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP110 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_BLE52_Pos 9 /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP19 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_BLE52_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP1_BLE52_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP19 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_I2S_Pos 8 /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP18 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_I2S_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP1_I2S_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP18 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_PDM1_Pos 7 /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP17 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_PDM1_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP1_PDM1_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP17 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_PDM0_Pos 6 /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP16 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_PDM0_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP1_PDM0_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP16 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP15_Pos 5 /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP15 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP15_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP15_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP15 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP14_Pos 4 /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP14 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP14_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP1_AHBNSPPCEXP14_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP14 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_DMA_Pos 3 /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP13 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_DMA_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP1_DMA_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP13 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_SHA2_Pos 2 /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP12 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_SHA2_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP1_SHA2_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP12 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_GPIO1_Pos 1 /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP11 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_GPIO1_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP1_GPIO1_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP11 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_GPIO0_Pos 0 /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP10 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP1_GPIO0_Msk (0x1UL /*<< SEC_PRIV_CTRL_AHBNSPPCEXP1_GPIO0_Pos*/) /* SEC_PRIV_CTRL AHBNSPPCEXP1: AHBNSPPCEXP10 Mask */ + +/* SEC_PRIV_CTRL AHBNSPPCEXP2 Register Definitions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP215_Pos 15 /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP215 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP215_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP215_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP215 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP214_Pos 14 /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP214 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP214_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP214_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP214 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP213_Pos 13 /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP213 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP213_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP213_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP213 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP212_Pos 12 /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP212 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP212_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP212_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP212 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP211_Pos 11 /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP211 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP211_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP211_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP211 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP210_Pos 10 /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP210 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP210_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP210_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP210 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP29_Pos 9 /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP29 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP29_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP29_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP29 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP28_Pos 8 /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP28 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP28_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP28_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP28 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP27_Pos 7 /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP27 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP27_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP27_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP27 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP26_Pos 6 /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP26 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP26_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP26_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP26 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP25_Pos 5 /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP25 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP25_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP25_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP25 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP24_Pos 4 /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP24 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP24_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP24_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP24 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP23_Pos 3 /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP23 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP23_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP23_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP23 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP22_Pos 2 /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP22 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP22_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP22_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP22 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP21_Pos 1 /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP21 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP21_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP21_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP21 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP20_Pos 0 /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP20 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP20_Msk (0x1UL /*<< SEC_PRIV_CTRL_AHBNSPPCEXP2_AHBNSPPCEXP20_Pos*/) /* SEC_PRIV_CTRL AHBNSPPCEXP2: AHBNSPPCEXP20 Mask */ + +/* SEC_PRIV_CTRL AHBNSPPCEXP3 Register Definitions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP315_Pos 15 /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP315 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP315_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP315_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP315 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP314_Pos 14 /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP314 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP314_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP314_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP314 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP313_Pos 13 /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP313 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP313_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP313_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP313 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP312_Pos 12 /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP312 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP312_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP312_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP312 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP311_Pos 11 /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP311 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP311_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP311_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP311 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP310_Pos 10 /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP310 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP310_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP310_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP310 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP39_Pos 9 /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP39 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP39_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP39_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP39 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP38_Pos 8 /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP38 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP38_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP38_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP38 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP37_Pos 7 /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP37 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP37_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP37_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP37 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP36_Pos 6 /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP36 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP36_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP36_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP36 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP35_Pos 5 /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP35 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP35_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP35_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP35 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP34_Pos 4 /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP34 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP34_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP34_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP34 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP33_Pos 3 /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP33 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP33_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP33_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP33 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP32_Pos 2 /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP32 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP32_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP32_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP32 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP31_Pos 1 /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP31 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP31_Msk (0x1UL << SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP31_Pos) /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP31 Mask */ + +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP30_Pos 0 /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP30 Positions */ +#define SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP30_Msk (0x1UL /*<< SEC_PRIV_CTRL_AHBNSPPCEXP3_AHBNSPPCEXP30_Pos*/) /* SEC_PRIV_CTRL AHBNSPPCEXP3: AHBNSPPCEXP30 Mask */ + +/* SEC_PRIV_CTRL APBNSPPC0 Register Definitions */ +#define SEC_PRIV_CTRL_APBNSPPC0_NS_MHU1_Pos 4 /* SEC_PRIV_CTRL APBNSPPC0: NS_MHU1 Positions */ +#define SEC_PRIV_CTRL_APBNSPPC0_NS_MHU1_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPC0_NS_MHU1_Pos) /* SEC_PRIV_CTRL APBNSPPC0: NS_MHU1 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPC0_NS_MHU0_Pos 3 /* SEC_PRIV_CTRL APBNSPPC0: NS_MHU0 Positions */ +#define SEC_PRIV_CTRL_APBNSPPC0_NS_MHU0_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPC0_NS_MHU0_Pos) /* SEC_PRIV_CTRL APBNSPPC0: NS_MHU0 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPC0_NS_DTIMER_Pos 2 /* SEC_PRIV_CTRL APBNSPPC0: NS_DTIMER Positions */ +#define SEC_PRIV_CTRL_APBNSPPC0_NS_DTIMER_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPC0_NS_DTIMER_Pos) /* SEC_PRIV_CTRL APBNSPPC0: NS_DTIMER Mask */ + +#define SEC_PRIV_CTRL_APBNSPPC0_NS_TIMER1_Pos 1 /* SEC_PRIV_CTRL APBNSPPC0: NS_TIMER1 Positions */ +#define SEC_PRIV_CTRL_APBNSPPC0_NS_TIMER1_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPC0_NS_TIMER1_Pos) /* SEC_PRIV_CTRL APBNSPPC0: NS_TIMER1 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPC0_NS_TIMER0_Pos 0 /* SEC_PRIV_CTRL APBNSPPC0: NS_TIMER0 Positions */ +#define SEC_PRIV_CTRL_APBNSPPC0_NS_TIMER0_Msk (0x1UL /*<< SEC_PRIV_CTRL_APBNSPPC0_NS_TIMER0_Pos*/) /* SEC_PRIV_CTRL APBNSPPC0: NS_TIMER0 Mask */ + +/* SEC_PRIV_CTRL APBNSPPC1 Register Definitions */ +#define SEC_PRIV_CTRL_APBNSPPC1_NS_S32K_Timer_Pos 0 /* SEC_PRIV_CTRL APBNSPPC1: NS_S32K_Timer Positions */ +#define SEC_PRIV_CTRL_APBNSPPC1_NS_S32K_Timer_Msk (0x1UL /*<< SEC_PRIV_CTRL_APBNSPPC1_NS_S32K_Timer_Pos*/) /* SEC_PRIV_CTRL APBNSPPC1: NS_S32K_Timer Mask */ + +/* SEC_PRIV_CTRL APBNSPPCEXP0 Register Definitions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP0_QSPI_Pos 15 /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP015 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP0_QSPI_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP0_QSPI_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP015 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP0_SLWTIMER_Pos 14 /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP014 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP0_SLWTIMER_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP0_SLWTIMER_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP014 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP0_SPI1_Pos 13 /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP013 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP0_SPI1_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP0_SPI1_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP013 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP0_QDEC_Pos 12 /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP012 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP0_QDEC_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP0_QDEC_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP012 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP0_SPI2_Pos 11 /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP011 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP0_SPI2_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP0_SPI2_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP011 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP0_KSM_Pos 10 /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP010 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP0_KSM_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP0_KSM_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP010 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP0_APBNSPPCEXP09_Pos 9 /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP09 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP0_APBNSPPCEXP09_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP0_APBNSPPCEXP09_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP09 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP0_APBNSPPCEXP08_Pos 8 /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP08 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP0_APBNSPPCEXP08_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP0_APBNSPPCEXP08_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP08 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP0_SPI0_Pos 7 /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP07 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP0_SPI0_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP0_SPI0_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP07 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP0_PWM_Pos 6 /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP06 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP0_PWM_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP0_PWM_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP06 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP0_UART1_Pos 5 /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP05 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP0_UART1_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP0_UART1_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP05 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP0_UART0_Pos 4 /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP04 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP0_UART0_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP0_UART0_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP04 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP0_WRPR_Pos 3 /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP03 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP0_WRPR_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP0_WRPR_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP03 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP0_APBNSPPCEXP02_Pos 2 /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP02 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP0_APBNSPPCEXP02_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP0_APBNSPPCEXP02_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP02 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP0_APBNSPPCEXP01_Pos 1 /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP01 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP0_APBNSPPCEXP01_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP0_APBNSPPCEXP01_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP01 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP0_APBNSPPCEXP00_Pos 0 /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP00 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP0_APBNSPPCEXP00_Msk (0x1UL /*<< SEC_PRIV_CTRL_APBNSPPCEXP0_APBNSPPCEXP00_Pos*/) /* SEC_PRIV_CTRL APBNSPPCEXP0: APBNSPPCEXP00 Mask */ + +/* SEC_PRIV_CTRL APBNSPPCEXP1 Register Definitions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP1_APBNSPPCEXP115_Pos 15 /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP115 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP1_APBNSPPCEXP115_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP1_APBNSPPCEXP115_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP115 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP1_ATLC_Pos 14 /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP114 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP1_ATLC_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP1_ATLC_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP114 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP1_SHUB_Pos 13 /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP113 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP1_SHUB_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP1_SHUB_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP113 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP1_RCOS_CAL_Pos 12 /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP112 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP1_RCOS_CAL_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP1_RCOS_CAL_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP112 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP1_TRNG_Pos 11 /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP111 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP1_TRNG_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP1_TRNG_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP111 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP1_GADC_Pos 10 /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP110 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP1_GADC_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP1_GADC_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP110 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP1_SWD_Pos 9 /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP19 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP1_SWD_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP1_SWD_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP19 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP1_PSEQ_Pos 8 /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP18 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP1_PSEQ_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP1_PSEQ_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP18 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP1_PMU_Pos 7 /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP17 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP1_PMU_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP1_PMU_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP17 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP1_MDM_Pos 6 /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP16 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP1_MDM_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP1_MDM_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP16 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP1_RADIO_Pos 5 /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP15 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP1_RADIO_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP1_RADIO_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP15 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP1_RIF_Pos 4 /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP14 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP1_RIF_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP1_RIF_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP14 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP1_WRPR_Pos 3 /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP13 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP1_WRPR_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP1_WRPR_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP13 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP1_NVM_Pos 2 /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP12 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP1_NVM_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP1_NVM_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP12 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP1_I2C1_Pos 1 /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP11 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP1_I2C1_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP1_I2C1_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP11 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP1_I2C0_Pos 0 /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP10 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP1_I2C0_Msk (0x1UL /*<< SEC_PRIV_CTRL_APBNSPPCEXP1_I2C0_Pos*/) /* SEC_PRIV_CTRL APBNSPPCEXP1: APBNSPPCEXP10 Mask */ + +/* SEC_PRIV_CTRL APBNSPPCEXP2 Register Definitions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP215_Pos 15 /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP215 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP215_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP215_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP215 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP214_Pos 14 /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP214 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP214_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP214_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP214 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP213_Pos 13 /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP213 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP213_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP213_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP213 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP212_Pos 12 /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP212 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP212_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP212_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP212 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP211_Pos 11 /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP211 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP211_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP211_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP211 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP210_Pos 10 /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP210 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP210_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP210_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP210 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP29_Pos 9 /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP29 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP29_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP29_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP29 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP28_Pos 8 /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP28 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP28_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP28_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP28 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP2_AES_Pos 7 /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP27 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP2_AES_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP2_AES_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP27 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP2_CLKRSTGEN_Pos 6 /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP26 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP2_CLKRSTGEN_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP2_CLKRSTGEN_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP26 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP2_I2S_Pos 5 /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP25 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP2_I2S_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP2_I2S_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP25 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP24_Pos 4 /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP24 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP24_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP24_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP24 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP2_WRPR_Pos 3 /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP23 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP2_WRPR_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP2_WRPR_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP23 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP22_Pos 2 /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP22 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP22_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP2_APBNSPPCEXP22_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP22 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP2_PDM1_Pos 1 /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP21 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP2_PDM1_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP2_PDM1_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP21 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP2_PDM0_Pos 0 /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP20 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP2_PDM0_Msk (0x1UL /*<< SEC_PRIV_CTRL_APBNSPPCEXP2_PDM0_Pos*/) /* SEC_PRIV_CTRL APBNSPPCEXP2: APBNSPPCEXP20 Mask */ + +/* SEC_PRIV_CTRL APBNSPPCEXP3 Register Definitions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP315_Pos 15 /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP315 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP315_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP315_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP315 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP314_Pos 14 /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP314 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP314_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP314_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP314 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP313_Pos 13 /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP313 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP313_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP313_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP313 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP312_Pos 12 /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP312 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP312_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP312_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP312 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP311_Pos 11 /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP311 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP311_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP311_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP311 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP310_Pos 10 /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP310 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP310_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP310_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP310 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP39_Pos 9 /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP39 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP39_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP39_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP39 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP38_Pos 8 /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP38 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP38_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP38_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP38 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP37_Pos 7 /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP37 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP37_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP37_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP37 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP36_Pos 6 /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP36 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP36_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP36_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP36 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP35_Pos 5 /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP35 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP35_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP35_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP35 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP34_Pos 4 /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP34 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP34_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP34_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP34 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP33_Pos 3 /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP33 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP33_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP33_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP33 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP32_Pos 2 /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP32 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP32_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP32_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP32 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP31_Pos 1 /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP31 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP31_Msk (0x1UL << SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP31_Pos) /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP31 Mask */ + +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP30_Pos 0 /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP30 Positions */ +#define SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP30_Msk (0x1UL /*<< SEC_PRIV_CTRL_APBNSPPCEXP3_APBNSPPCEXP30_Pos*/) /* SEC_PRIV_CTRL APBNSPPCEXP3: APBNSPPCEXP30 Mask */ + +/* SEC_PRIV_CTRL AHBSPPPCEXP0 Register Definitions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP015_Pos 15 /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP015 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP015_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP015_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP015 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP014_Pos 14 /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP014 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP014_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP014_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP014 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP013_Pos 13 /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP013 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP013_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP013_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP013 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP012_Pos 12 /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP012 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP012_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP012_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP012 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP011_Pos 11 /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP011 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP011_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP011_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP011 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP010_Pos 10 /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP010 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP010_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP010_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP010 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP09_Pos 9 /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP09 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP09_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP09_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP09 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP08_Pos 8 /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP08 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP08_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP08_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP08 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP07_Pos 7 /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP07 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP07_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP07_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP07 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP06_Pos 6 /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP06 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP06_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP06_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP06 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP05_Pos 5 /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP05 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP05_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP05_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP05 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP04_Pos 4 /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP04 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP04_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP04_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP04 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP03_Pos 3 /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP03 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP03_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP03_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP03 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP02_Pos 2 /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP02 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP02_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP02_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP02 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP01_Pos 1 /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP01 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP01_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP01_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP01 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP00_Pos 0 /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP00 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP00_Msk (0x1UL /*<< SEC_PRIV_CTRL_AHBSPPPCEXP0_AHBSPPPCEXP00_Pos*/) /* SEC_PRIV_CTRL AHBSPPPCEXP0: AHBSPPPCEXP00 Mask */ + +/* SEC_PRIV_CTRL AHBSPPPCEXP1 Register Definitions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP115_Pos 15 /* SEC_PRIV_CTRL AHBSPPPCEXP1: AHBSPPPCEXP115 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP115_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP115_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP1: AHBSPPPCEXP115 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP114_Pos 14 /* SEC_PRIV_CTRL AHBSPPPCEXP1: AHBSPPPCEXP114 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP114_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP114_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP1: AHBSPPPCEXP114 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP113_Pos 13 /* SEC_PRIV_CTRL AHBSPPPCEXP1: AHBSPPPCEXP113 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP113_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP113_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP1: AHBSPPPCEXP113 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP112_Pos 12 /* SEC_PRIV_CTRL AHBSPPPCEXP1: AHBSPPPCEXP112 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP112_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP112_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP1: AHBSPPPCEXP112 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP111_Pos 11 /* SEC_PRIV_CTRL AHBSPPPCEXP1: AHBSPPPCEXP111 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP111_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP111_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP1: AHBSPPPCEXP111 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP110_Pos 10 /* SEC_PRIV_CTRL AHBSPPPCEXP1: AHBSPPPCEXP110 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP110_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP110_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP1: AHBSPPPCEXP110 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_BLE52_Pos 9 /* SEC_PRIV_CTRL AHBSPPPCEXP1: BLE52 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_BLE52_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP1_BLE52_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP1: BLE52 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_I2S_Pos 8 /* SEC_PRIV_CTRL AHBSPPPCEXP1: I2S Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_I2S_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP1_I2S_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP1: I2S Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_PDM1_Pos 7 /* SEC_PRIV_CTRL AHBSPPPCEXP1: PDM1 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_PDM1_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP1_PDM1_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP1: PDM1 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_PDM0_Pos 6 /* SEC_PRIV_CTRL AHBSPPPCEXP1: PDM0 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_PDM0_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP1_PDM0_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP1: PDM0 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP15_Pos 5 /* SEC_PRIV_CTRL AHBSPPPCEXP1: AHBSPPPCEXP15 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP15_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP15_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP1: AHBSPPPCEXP15 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP14_Pos 4 /* SEC_PRIV_CTRL AHBSPPPCEXP1: AHBSPPPCEXP14 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP14_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP1_AHBSPPPCEXP14_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP1: AHBSPPPCEXP14 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_DMA_Pos 3 /* SEC_PRIV_CTRL AHBSPPPCEXP1: DMA Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_DMA_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP1_DMA_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP1: DMA Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_SHA2_Pos 2 /* SEC_PRIV_CTRL AHBSPPPCEXP1: SHA2 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_SHA2_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP1_SHA2_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP1: SHA2 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_GPIO1_Pos 1 /* SEC_PRIV_CTRL AHBSPPPCEXP1: GPIO1 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_GPIO1_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP1_GPIO1_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP1: GPIO1 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_GPIO0_Pos 0 /* SEC_PRIV_CTRL AHBSPPPCEXP1: GPIO0 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP1_GPIO0_Msk (0x1UL /*<< SEC_PRIV_CTRL_AHBSPPPCEXP1_GPIO0_Pos*/) /* SEC_PRIV_CTRL AHBSPPPCEXP1: GPIO0 Mask */ + +/* SEC_PRIV_CTRL AHBSPPPCEXP2 Register Definitions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP215_Pos 15 /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP215 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP215_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP215_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP215 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP214_Pos 14 /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP214 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP214_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP214_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP214 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP213_Pos 13 /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP213 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP213_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP213_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP213 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP212_Pos 12 /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP212 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP212_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP212_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP212 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP211_Pos 11 /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP211 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP211_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP211_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP211 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP210_Pos 10 /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP210 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP210_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP210_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP210 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP29_Pos 9 /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP29 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP29_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP29_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP29 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP28_Pos 8 /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP28 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP28_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP28_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP28 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP27_Pos 7 /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP27 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP27_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP27_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP27 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP26_Pos 6 /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP26 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP26_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP26_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP26 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP25_Pos 5 /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP25 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP25_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP25_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP25 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP24_Pos 4 /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP24 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP24_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP24_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP24 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP23_Pos 3 /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP23 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP23_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP23_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP23 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP22_Pos 2 /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP22 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP22_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP22_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP22 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP21_Pos 1 /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP21 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP21_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP21_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP21 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP20_Pos 0 /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP20 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP20_Msk (0x1UL /*<< SEC_PRIV_CTRL_AHBSPPPCEXP2_AHBSPPPCEXP20_Pos*/) /* SEC_PRIV_CTRL AHBSPPPCEXP2: AHBSPPPCEXP20 Mask */ + +/* SEC_PRIV_CTRL AHBSPPPCEXP3 Register Definitions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP315_Pos 15 /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP315 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP315_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP315_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP315 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP314_Pos 14 /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP314 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP314_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP314_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP314 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP313_Pos 13 /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP313 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP313_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP313_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP313 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP312_Pos 12 /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP312 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP312_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP312_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP312 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP311_Pos 11 /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP311 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP311_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP311_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP311 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP310_Pos 10 /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP310 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP310_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP310_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP310 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP39_Pos 9 /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP39 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP39_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP39_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP39 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP38_Pos 8 /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP38 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP38_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP38_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP38 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP37_Pos 7 /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP37 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP37_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP37_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP37 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP36_Pos 6 /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP36 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP36_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP36_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP36 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP35_Pos 5 /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP35 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP35_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP35_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP35 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP34_Pos 4 /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP34 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP34_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP34_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP34 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP33_Pos 3 /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP33 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP33_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP33_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP33 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP32_Pos 2 /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP32 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP32_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP32_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP32 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP31_Pos 1 /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP31 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP31_Msk (0x1UL << SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP31_Pos) /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP31 Mask */ + +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP30_Pos 0 /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP30 Positions */ +#define SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP30_Msk (0x1UL /*<< SEC_PRIV_CTRL_AHBSPPPCEXP3_AHBSPPPCEXP30_Pos*/) /* SEC_PRIV_CTRL AHBSPPPCEXP3: AHBSPPPCEXP30 Mask */ + +/* SEC_PRIV_CTRL APBSPPPC0 Register Definitions */ +#define SEC_PRIV_CTRL_APBSPPPC0_SP_MHU1_Pos 4 /* SEC_PRIV_CTRL APBSPPPC0: SP_MHU1 Positions */ +#define SEC_PRIV_CTRL_APBSPPPC0_SP_MHU1_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPC0_SP_MHU1_Pos) /* SEC_PRIV_CTRL APBSPPPC0: SP_MHU1 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPC0_SP_MHU0_Pos 3 /* SEC_PRIV_CTRL APBSPPPC0: SP_MHU0 Positions */ +#define SEC_PRIV_CTRL_APBSPPPC0_SP_MHU0_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPC0_SP_MHU0_Pos) /* SEC_PRIV_CTRL APBSPPPC0: SP_MHU0 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPC0_SP_DTIMER_Pos 2 /* SEC_PRIV_CTRL APBSPPPC0: SP_DTIMER Positions */ +#define SEC_PRIV_CTRL_APBSPPPC0_SP_DTIMER_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPC0_SP_DTIMER_Pos) /* SEC_PRIV_CTRL APBSPPPC0: SP_DTIMER Mask */ + +#define SEC_PRIV_CTRL_APBSPPPC0_SP_TIMER1_Pos 1 /* SEC_PRIV_CTRL APBSPPPC0: SP_TIMER1 Positions */ +#define SEC_PRIV_CTRL_APBSPPPC0_SP_TIMER1_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPC0_SP_TIMER1_Pos) /* SEC_PRIV_CTRL APBSPPPC0: SP_TIMER1 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPC0_SP_TIMER0_Pos 0 /* SEC_PRIV_CTRL APBSPPPC0: SP_TIMER0 Positions */ +#define SEC_PRIV_CTRL_APBSPPPC0_SP_TIMER0_Msk (0x1UL /*<< SEC_PRIV_CTRL_APBSPPPC0_SP_TIMER0_Pos*/) /* SEC_PRIV_CTRL APBSPPPC0: SP_TIMER0 Mask */ + +/* SEC_PRIV_CTRL APBSPPPC1 Register Definitions */ +#define SEC_PRIV_CTRL_APBSPPPC1_SP_S32K_Timer_Pos 0 /* SEC_PRIV_CTRL APBSPPPC1: SP_S32K_Timer Positions */ +#define SEC_PRIV_CTRL_APBSPPPC1_SP_S32K_Timer_Msk (0x1UL /*<< SEC_PRIV_CTRL_APBSPPPC1_SP_S32K_Timer_Pos*/) /* SEC_PRIV_CTRL APBSPPPC1: SP_S32K_Timer Mask */ + +/* SEC_PRIV_CTRL APBSPPPCEXP0 Register Definitions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP0_QSPI_Pos 15 /* SEC_PRIV_CTRL APBSPPPCEXP0: QSPI Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP0_QSPI_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP0_QSPI_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP0: QSPI Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP0_SLWTIMER_Pos 14 /* SEC_PRIV_CTRL APBSPPPCEXP0: SLWTIMER Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP0_SLWTIMER_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP0_SLWTIMER_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP0: SLWTIMER Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP0_SPI1_Pos 13 /* SEC_PRIV_CTRL APBSPPPCEXP0: SPI1 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP0_SPI1_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP0_SPI1_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP0: SPI1 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP0_QDEC_Pos 12 /* SEC_PRIV_CTRL APBSPPPCEXP0: QDEC Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP0_QDEC_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP0_QDEC_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP0: QDEC Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP0_SPI2_Pos 11 /* SEC_PRIV_CTRL APBSPPPCEXP0: SPI2 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP0_SPI2_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP0_SPI2_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP0: SPI2 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP0_KSM_Pos 10 /* SEC_PRIV_CTRL APBSPPPCEXP0: KSM Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP0_KSM_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP0_KSM_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP0: KSM Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP0_APBSPPPCEXP09_Pos 9 /* SEC_PRIV_CTRL APBSPPPCEXP0: APBSPPPCEXP09 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP0_APBSPPPCEXP09_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP0_APBSPPPCEXP09_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP0: APBSPPPCEXP09 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP0_APBSPPPCEXP08_Pos 8 /* SEC_PRIV_CTRL APBSPPPCEXP0: APBSPPPCEXP08 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP0_APBSPPPCEXP08_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP0_APBSPPPCEXP08_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP0: APBSPPPCEXP08 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP0_SPI0_Pos 7 /* SEC_PRIV_CTRL APBSPPPCEXP0: SPI0 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP0_SPI0_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP0_SPI0_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP0: SPI0 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP0_PWM_Pos 6 /* SEC_PRIV_CTRL APBSPPPCEXP0: PWM Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP0_PWM_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP0_PWM_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP0: PWM Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP0_UART1_Pos 5 /* SEC_PRIV_CTRL APBSPPPCEXP0: UART1 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP0_UART1_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP0_UART1_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP0: UART1 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP0_UART0_Pos 4 /* SEC_PRIV_CTRL APBSPPPCEXP0: UART0 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP0_UART0_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP0_UART0_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP0: UART0 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP0_WRPR_Pos 3 /* SEC_PRIV_CTRL APBSPPPCEXP0: WRPR Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP0_WRPR_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP0_WRPR_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP0: WRPR Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP0_APBSPPPCEXP02_Pos 2 /* SEC_PRIV_CTRL APBSPPPCEXP0: APBSPPPCEXP02 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP0_APBSPPPCEXP02_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP0_APBSPPPCEXP02_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP0: APBSPPPCEXP02 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP0_APBSPPPCEXP01_Pos 1 /* SEC_PRIV_CTRL APBSPPPCEXP0: APBSPPPCEXP01 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP0_APBSPPPCEXP01_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP0_APBSPPPCEXP01_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP0: APBSPPPCEXP01 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP0_APBSPPPCEXP00_Pos 0 /* SEC_PRIV_CTRL APBSPPPCEXP0: APBSPPPCEXP00 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP0_APBSPPPCEXP00_Msk (0x1UL /*<< SEC_PRIV_CTRL_APBSPPPCEXP0_APBSPPPCEXP00_Pos*/) /* SEC_PRIV_CTRL APBSPPPCEXP0: APBSPPPCEXP00 Mask */ + +/* SEC_PRIV_CTRL APBSPPPCEXP1 Register Definitions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP1_APBSPPPCEXP115_Pos 15 /* SEC_PRIV_CTRL APBSPPPCEXP1: APBSPPPCEXP115 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP1_APBSPPPCEXP115_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP1_APBSPPPCEXP115_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP1: APBSPPPCEXP115 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP1_ATLC_Pos 14 /* SEC_PRIV_CTRL APBSPPPCEXP1: ATLC Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP1_ATLC_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP1_ATLC_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP1: ATLC Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP1_SHUB_Pos 13 /* SEC_PRIV_CTRL APBSPPPCEXP1: SHUB Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP1_SHUB_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP1_SHUB_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP1: SHUB Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP1_RCOS_CAL_Pos 12 /* SEC_PRIV_CTRL APBSPPPCEXP1: RCOS_CAL Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP1_RCOS_CAL_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP1_RCOS_CAL_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP1: RCOS_CAL Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP1_TRNG_Pos 11 /* SEC_PRIV_CTRL APBSPPPCEXP1: TRNG Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP1_TRNG_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP1_TRNG_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP1: TRNG Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP1_GADC_Pos 10 /* SEC_PRIV_CTRL APBSPPPCEXP1: GADC Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP1_GADC_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP1_GADC_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP1: GADC Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP1_SWD_Pos 9 /* SEC_PRIV_CTRL APBSPPPCEXP1: SWD Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP1_SWD_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP1_SWD_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP1: SWD Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP1_PSEQ_Pos 8 /* SEC_PRIV_CTRL APBSPPPCEXP1: PSEQ Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP1_PSEQ_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP1_PSEQ_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP1: PSEQ Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP1_PMU_Pos 7 /* SEC_PRIV_CTRL APBSPPPCEXP1: PMU Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP1_PMU_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP1_PMU_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP1: PMU Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP1_MDM_Pos 6 /* SEC_PRIV_CTRL APBSPPPCEXP1: MDM Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP1_MDM_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP1_MDM_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP1: MDM Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP1_RADIO_Pos 5 /* SEC_PRIV_CTRL APBSPPPCEXP1: RADIO Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP1_RADIO_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP1_RADIO_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP1: RADIO Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP1_RIF_Pos 4 /* SEC_PRIV_CTRL APBSPPPCEXP1: RIF Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP1_RIF_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP1_RIF_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP1: RIF Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP1_WRPR_Pos 3 /* SEC_PRIV_CTRL APBSPPPCEXP1: WRPR Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP1_WRPR_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP1_WRPR_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP1: WRPR Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP1_NVM_Pos 2 /* SEC_PRIV_CTRL APBSPPPCEXP1: NVM Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP1_NVM_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP1_NVM_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP1: NVM Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP1_I2C1_Pos 1 /* SEC_PRIV_CTRL APBSPPPCEXP1: I2C1 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP1_I2C1_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP1_I2C1_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP1: I2C1 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP1_I2C0_Pos 0 /* SEC_PRIV_CTRL APBSPPPCEXP1: I2C0 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP1_I2C0_Msk (0x1UL /*<< SEC_PRIV_CTRL_APBSPPPCEXP1_I2C0_Pos*/) /* SEC_PRIV_CTRL APBSPPPCEXP1: I2C0 Mask */ + +/* SEC_PRIV_CTRL APBSPPPCEXP2 Register Definitions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP215_Pos 15 /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP215 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP215_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP215_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP215 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP214_Pos 14 /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP214 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP214_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP214_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP214 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP213_Pos 13 /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP213 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP213_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP213_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP213 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP212_Pos 12 /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP212 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP212_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP212_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP212 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP211_Pos 11 /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP211 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP211_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP211_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP211 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP210_Pos 10 /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP210 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP210_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP210_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP210 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP29_Pos 9 /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP29 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP29_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP29_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP29 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP28_Pos 8 /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP28 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP28_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP28_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP28 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP2_AES_Pos 7 /* SEC_PRIV_CTRL APBSPPPCEXP2: AES Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP2_AES_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP2_AES_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP2: AES Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP2_CLKRSTGEN_Pos 6 /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP26 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP2_CLKRSTGEN_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP2_CLKRSTGEN_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP26 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP2_I2S_Pos 5 /* SEC_PRIV_CTRL APBSPPPCEXP2: I2S Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP2_I2S_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP2_I2S_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP2: I2S Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP24_Pos 4 /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP24 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP24_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPPCEXP24_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP24 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP2_WRPR_Pos 3 /* SEC_PRIV_CTRL APBSPPPCEXP2: WRPR Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP2_WRPR_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP2_WRPR_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP2: WRPR Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPCEXP22_Pos 2 /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP22 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPCEXP22_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP2_APBSPPCEXP22_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP2: APBSPPPCEXP22 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP2_PDM1_Pos 1 /* SEC_PRIV_CTRL APBSPPPCEXP2: PDM1 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP2_PDM1_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP2_PDM1_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP2: PDM1 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP2_PDM0_Pos 0 /* SEC_PRIV_CTRL APBSPPPCEXP2: PDM0 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP2_PDM0_Msk (0x1UL /*<< SEC_PRIV_CTRL_APBSPPPCEXP2_PDM0_Pos*/) /* SEC_PRIV_CTRL APBSPPPCEXP2: PDM0 Mask */ + +/* SEC_PRIV_CTRL APBSPPPCEXP3 Register Definitions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP315_Pos 15 /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP315 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP315_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP315_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP315 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP314_Pos 14 /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP314 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP314_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP314_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP314 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP313_Pos 13 /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP313 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP313_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP313_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP313 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP312_Pos 12 /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP312 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP312_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP312_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP312 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP311_Pos 11 /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP311 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP311_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP311_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP311 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP310_Pos 10 /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP310 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP310_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP310_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP310 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP39_Pos 9 /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP39 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP39_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP39_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP39 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP38_Pos 8 /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP38 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP38_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP38_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP38 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP37_Pos 7 /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP37 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP37_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP37_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP37 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP36_Pos 6 /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP36 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP36_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP36_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP36 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP35_Pos 5 /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP35 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP35_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP35_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP35 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP34_Pos 4 /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP34 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP34_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP34_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP34 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP33_Pos 3 /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP33 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP33_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP33_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP33 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP32_Pos 2 /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP32 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP32_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP32_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP32 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP31_Pos 1 /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP31 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP31_Msk (0x1UL << SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP31_Pos) /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP31 Mask */ + +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP30_Pos 0 /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP30 Positions */ +#define SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP30_Msk (0x1UL /*<< SEC_PRIV_CTRL_APBSPPPCEXP3_APBSPPPCEXP30_Pos*/) /* SEC_PRIV_CTRL APBSPPPCEXP3: APBSPPPCEXP30 Mask */ + +/* SEC_PRIV_CTRL NSMSCEXP Register Definitions */ +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP15_Pos 31 /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP15 Positions */ +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP15_Msk (0x1UL << SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP15_Pos) /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP15 Mask */ + +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP14_Pos 30 /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP14 Positions */ +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP14_Msk (0x1UL << SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP14_Pos) /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP14 Mask */ + +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP13_Pos 29 /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP13 Positions */ +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP13_Msk (0x1UL << SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP13_Pos) /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP13 Mask */ + +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP12_Pos 28 /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP12 Positions */ +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP12_Msk (0x1UL << SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP12_Pos) /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP12 Mask */ + +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP11_Pos 27 /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP11 Positions */ +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP11_Msk (0x1UL << SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP11_Pos) /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP11 Mask */ + +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP10_Pos 26 /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP10 Positions */ +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP10_Msk (0x1UL << SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP10_Pos) /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP10 Mask */ + +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP9_Pos 25 /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP9 Positions */ +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP9_Msk (0x1UL << SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP9_Pos) /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP9 Mask */ + +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP8_Pos 24 /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP8 Positions */ +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP8_Msk (0x1UL << SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP8_Pos) /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP8 Mask */ + +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP7_Pos 23 /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP7 Positions */ +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP7_Msk (0x1UL << SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP7_Pos) /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP7 Mask */ + +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP6_Pos 22 /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP6 Positions */ +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP6_Msk (0x1UL << SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP6_Pos) /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP6 Mask */ + +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP5_Pos 21 /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP5 Positions */ +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP5_Msk (0x1UL << SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP5_Pos) /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP5 Mask */ + +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP4_Pos 20 /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP4 Positions */ +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP4_Msk (0x1UL << SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP4_Pos) /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP4 Mask */ + +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP3_Pos 19 /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP3 Positions */ +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP3_Msk (0x1UL << SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP3_Pos) /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP3 Mask */ + +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP2_Pos 18 /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP2 Positions */ +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP2_Msk (0x1UL << SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP2_Pos) /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP2 Mask */ + +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP1_Pos 17 /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP1 Positions */ +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP1_Msk (0x1UL << SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP1_Pos) /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP1 Mask */ + +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP0_Pos 16 /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP0 Positions */ +#define SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP0_Msk (0x1UL << SEC_PRIV_CTRL_NSMSCEXP_NS_MSCEXP0_Pos) /* SEC_PRIV_CTRL NSMSCEXP: NS_MSCEXP0 Mask */ + +/* SEC_PRIV_CTRL PIDR4 Register Definitions */ +#define SEC_PRIV_CTRL_PIDR4_SIZE_Pos 4 /* SEC_PRIV_CTRL PIDR4: SIZE Positions */ +#define SEC_PRIV_CTRL_PIDR4_SIZE_Msk (0xFUL << SEC_PRIV_CTRL_PIDR4_SIZE_Pos) /* SEC_PRIV_CTRL PIDR4: SIZE Mask */ + +#define SEC_PRIV_CTRL_PIDR4_DES_2_Pos 0 /* SEC_PRIV_CTRL PIDR4: DES_2 Positions */ +#define SEC_PRIV_CTRL_PIDR4_DES_2_Msk (0xFUL /*<< SEC_PRIV_CTRL_PIDR4_DES_2_Pos*/) /* SEC_PRIV_CTRL PIDR4: DES_2 Mask */ + +/* SEC_PRIV_CTRL PIDR0 Register Definitions */ +#define SEC_PRIV_CTRL_PIDR0_PART_0_Pos 0 /* SEC_PRIV_CTRL PIDR0: PART_0 Positions */ +#define SEC_PRIV_CTRL_PIDR0_PART_0_Msk (0xFFUL /*<< SEC_PRIV_CTRL_PIDR0_PART_0_Pos*/) /* SEC_PRIV_CTRL PIDR0: PART_0 Mask */ + +/* SEC_PRIV_CTRL PIDR1 Register Definitions */ +#define SEC_PRIV_CTRL_PIDR1_DES_0_Pos 4 /* SEC_PRIV_CTRL PIDR1: DES_0 Positions */ +#define SEC_PRIV_CTRL_PIDR1_DES_0_Msk (0xFUL << SEC_PRIV_CTRL_PIDR1_DES_0_Pos) /* SEC_PRIV_CTRL PIDR1: DES_0 Mask */ + +#define SEC_PRIV_CTRL_PIDR1_PART_1_Pos 0 /* SEC_PRIV_CTRL PIDR1: PART_1 Positions */ +#define SEC_PRIV_CTRL_PIDR1_PART_1_Msk (0xFUL /*<< SEC_PRIV_CTRL_PIDR1_PART_1_Pos*/) /* SEC_PRIV_CTRL PIDR1: PART_1 Mask */ + +/* SEC_PRIV_CTRL PIDR2 Register Definitions */ +#define SEC_PRIV_CTRL_PIDR2_REVISION_Pos 4 /* SEC_PRIV_CTRL PIDR2: REVISION Positions */ +#define SEC_PRIV_CTRL_PIDR2_REVISION_Msk (0xFUL << SEC_PRIV_CTRL_PIDR2_REVISION_Pos) /* SEC_PRIV_CTRL PIDR2: REVISION Mask */ + +#define SEC_PRIV_CTRL_PIDR2_JEDEC_Pos 3 /* SEC_PRIV_CTRL PIDR2: JEDEC Positions */ +#define SEC_PRIV_CTRL_PIDR2_JEDEC_Msk (0x1UL << SEC_PRIV_CTRL_PIDR2_JEDEC_Pos) /* SEC_PRIV_CTRL PIDR2: JEDEC Mask */ + +#define SEC_PRIV_CTRL_PIDR2_DES_1_Pos 0 /* SEC_PRIV_CTRL PIDR2: DES_1 Positions */ +#define SEC_PRIV_CTRL_PIDR2_DES_1_Msk (0x7UL /*<< SEC_PRIV_CTRL_PIDR2_DES_1_Pos*/) /* SEC_PRIV_CTRL PIDR2: DES_1 Mask */ + +/* SEC_PRIV_CTRL PIDR3 Register Definitions */ +#define SEC_PRIV_CTRL_PIDR3_REVAND_Pos 4 /* SEC_PRIV_CTRL PIDR3: REVAND Positions */ +#define SEC_PRIV_CTRL_PIDR3_REVAND_Msk (0xFUL << SEC_PRIV_CTRL_PIDR3_REVAND_Pos) /* SEC_PRIV_CTRL PIDR3: REVAND Mask */ + +#define SEC_PRIV_CTRL_PIDR3_CMOD_Pos 0 /* SEC_PRIV_CTRL PIDR3: CMOD Positions */ +#define SEC_PRIV_CTRL_PIDR3_CMOD_Msk (0xFUL /*<< SEC_PRIV_CTRL_PIDR3_CMOD_Pos*/) /* SEC_PRIV_CTRL PIDR3: CMOD Mask */ + +/* SEC_PRIV_CTRL CIDR0 Register Definitions */ +#define SEC_PRIV_CTRL_CIDR0_PRMBL_0_Pos 0 /* SEC_PRIV_CTRL CIDR0: PRMBL_0 Positions */ +#define SEC_PRIV_CTRL_CIDR0_PRMBL_0_Msk (0xFFUL /*<< SEC_PRIV_CTRL_CIDR0_PRMBL_0_Pos*/) /* SEC_PRIV_CTRL CIDR0: PRMBL_0 Mask */ + +/* SEC_PRIV_CTRL CIDR1 Register Definitions */ +#define SEC_PRIV_CTRL_CIDR1_CLASS_Pos 4 /* SEC_PRIV_CTRL CIDR1: CLASS Positions */ +#define SEC_PRIV_CTRL_CIDR1_CLASS_Msk (0xFUL << SEC_PRIV_CTRL_CIDR1_CLASS_Pos) /* SEC_PRIV_CTRL CIDR1: CLASS Mask */ + +#define SEC_PRIV_CTRL_CIDR1_PRMBL_1_Pos 0 /* SEC_PRIV_CTRL CIDR1: PRMBL_1 Positions */ +#define SEC_PRIV_CTRL_CIDR1_PRMBL_1_Msk (0xFUL /*<< SEC_PRIV_CTRL_CIDR1_PRMBL_1_Pos*/) /* SEC_PRIV_CTRL CIDR1: PRMBL_1 Mask */ + +/* SEC_PRIV_CTRL CIDR2 Register Definitions */ +#define SEC_PRIV_CTRL_CIDR2_PRMBL_2_Pos 0 /* SEC_PRIV_CTRL CIDR2: PRMBL_2 Positions */ +#define SEC_PRIV_CTRL_CIDR2_PRMBL_2_Msk (0xFFUL /*<< SEC_PRIV_CTRL_CIDR2_PRMBL_2_Pos*/) /* SEC_PRIV_CTRL CIDR2: PRMBL_2 Mask */ + +/* SEC_PRIV_CTRL CIDR3 Register Definitions */ +#define SEC_PRIV_CTRL_CIDR3_PRMBL_3_Pos 0 /* SEC_PRIV_CTRL CIDR3: PRMBL_3 Positions */ +#define SEC_PRIV_CTRL_CIDR3_PRMBL_3_Msk (0xFFUL /*<< SEC_PRIV_CTRL_CIDR3_PRMBL_3_Pos*/) /* SEC_PRIV_CTRL CIDR3: PRMBL_3 Mask */ + + +/*----------------------------- NONSECURE PRIVILEGE CONTROL REGISTER ---------------------------------------------*/ +typedef struct +{ + uint32_t RESERVED0[40]; +__IOM uint32_t AHBNSPPPCEXP0; /* Offset: 0xA0 (read-write) AHBNSPPPCEXP0 Register */ +__IOM uint32_t AHBNSPPPCEXP1; /* Offset: 0xA4 (read-write) AHBNSPPPCEXP1 Register */ +__IOM uint32_t AHBNSPPPCEXP2; /* Offset: 0xA8 (read-write) AHBNSPPPCEXP2 Register */ +__IOM uint32_t AHBNSPPPCEXP3; /* Offset: 0xAC (read-write) AHBNSPPPCEXP3 Register */ +__IOM uint32_t APBNSPPPC0; /* Offset: 0xB0 (read-write) APBNSPPPC0 Register */ +__IOM uint32_t APBNSPPPC1; /* Offset: 0xB4 (read-write) APBNSPPPC1 Register */ + uint32_t RESERVED1[2]; +__IOM uint32_t APBNSPPPCEXP0; /* Offset: 0xC0 (read-write) APBNSPPPCEXP0 Register */ +__IOM uint32_t APBNSPPPCEXP1; /* Offset: 0xC4 (read-write) APBNSPPPCEXP1 Register */ +__IOM uint32_t APBNSPPPCEXP2; /* Offset: 0xC8 (read-write) APBNSPPPCEXP2 Register */ +__IOM uint32_t APBNSPPPCEXP3; /* Offset: 0xCC (read-write) APBNSPPPCEXP3 Register */ + uint32_t RESERVED2[960]; +__IM uint32_t PIDR4; /* Offset: 0xFD0 (read-only) PIDR4 Register */ + uint32_t RESERVED3[3]; +__IM uint32_t PIDR0; /* Offset: 0xFE0 (read-only) PIDR0 Register */ +__IM uint32_t PIDR1; /* Offset: 0xFE4 (read-only) PIDR1 Register */ +__IM uint32_t PIDR2; /* Offset: 0xFE8 (read-only) PIDR2 Register */ +__IM uint32_t PIDR3; /* Offset: 0xFEC (read-only) PIDR3 Register */ +__IM uint32_t CIDR0; /* Offset: 0xFF0 (read-only) CIDR0 Register */ +__IM uint32_t CIDR1; /* Offset: 0xFF4 (read-only) CIDR1 Register */ +__IM uint32_t CIDR2; /* Offset: 0xFF8 (read-only) CIDR2 Register */ +__IM uint32_t CIDR3; /* Offset: 0xFFC (read-only) CIDR3 Register */ +}NONSEC_PRIV_CTRL_TypeDef; + +/* NONSEC_PRIV_CTRL AHBNSPPPCEXP0 Register Definitions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP015_Pos 15 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP015 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP015_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP015_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP015 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP014_Pos 14 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP014 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP014_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP014_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP014 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP013_Pos 13 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP013 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP013_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP013_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP013 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP012_Pos 12 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP012 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP012_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP012_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP012 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP011_Pos 11 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP011 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP011_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP011_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP011 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP010_Pos 10 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP010 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP010_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP010_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP010 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP09_Pos 9 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP09 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP09_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP09_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP09 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP08_Pos 8 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP08 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP08_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP08_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP08 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP07_Pos 7 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP07 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP07_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP07_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP07 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP06_Pos 6 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP06 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP06_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP06_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP06 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP05_Pos 5 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP05 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP05_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP05_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP05 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP04_Pos 4 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP04 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP04_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP04_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP04 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP03_Pos 3 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP03 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP03_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP03_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP03 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP02_Pos 2 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP02 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP02_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP02_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP02 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP01_Pos 1 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP01 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP01_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP01_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP01 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP00_Pos 0 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP00 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP00_Msk (0x1UL /*<< NONSEC_PRIV_CTRL_AHBNSPPPCEXP0_AHBNSPPPCEXP00_Pos*/) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP0: AHBNSPPPCEXP00 Mask */ + +/* NONSEC_PRIV_CTRL AHBNSPPPCEXP1 Register Definitions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP115_Pos 15 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: AHBNSPPPCEXP115 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP115_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP115_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: AHBNSPPPCEXP115 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP114_Pos 14 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: AHBNSPPPCEXP114 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP114_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP114_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: AHBNSPPPCEXP114 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP113_Pos 13 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: AHBNSPPPCEXP113 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP113_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP113_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: AHBNSPPPCEXP113 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP112_Pos 12 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: AHBNSPPPCEXP112 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP112_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP112_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: AHBNSPPPCEXP112 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP111_Pos 11 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: AHBNSPPPCEXP111 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP111_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP111_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: AHBNSPPPCEXP111 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP110_Pos 10 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: AHBNSPPPCEXP110 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP110_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP110_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: AHBNSPPPCEXP110 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_BLE52_Pos 9 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: BLE52 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_BLE52_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_BLE52_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: BLE52 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_I2S_Pos 8 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: I2S Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_I2S_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_I2S_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: I2S Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_PDM1_Pos 7 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: PDM1 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_PDM1_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_PDM1_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: PDM1 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_PDM0_Pos 6 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: PDM0 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_PDM0_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_PDM0_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: PDM0 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP15_Pos 5 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: AHBNSPPPCEXP15 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP15_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP15_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: AHBNSPPPCEXP15 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP14_Pos 4 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: AHBNSPPPCEXP14 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP14_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_AHBNSPPPCEXP14_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: AHBNSPPPCEXP14 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_DMA_Pos 3 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: DMA Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_DMA_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_DMA_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: DMA Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_SHA2_Pos 2 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: SHA2 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_SHA2_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_SHA2_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: SHA2 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_GPIO1_Pos 1 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: GPIO1 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_GPIO1_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_GPIO1_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: GPIO1 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_GPIO0_Pos 0 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: GPIO0 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_GPIO0_Msk (0x1UL /*<< NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_GPIO0_Pos*/) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP1: GPIO0 Mask */ + +/* NONSEC_PRIV_CTRL AHBNSPPPCEXP2 Register Definitions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP215_Pos 15 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP215 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP215_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP215_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP215 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP214_Pos 14 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP214 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP214_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP214_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP214 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP213_Pos 13 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP213 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP213_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP213_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP213 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP212_Pos 12 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP212 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP212_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP212_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP212 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP211_Pos 11 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP211 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP211_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP211_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP211 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP210_Pos 10 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP210 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP210_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP210_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP210 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP29_Pos 9 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP29 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP29_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP29_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP29 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP28_Pos 8 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP28 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP28_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP28_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP28 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP27_Pos 7 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP27 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP27_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP27_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP27 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP26_Pos 6 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP26 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP26_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP26_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP26 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP25_Pos 5 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP25 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP25_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP25_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP25 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP24_Pos 4 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP24 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP24_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP24_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP24 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP23_Pos 3 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP23 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP23_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP23_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP23 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP22_Pos 2 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP22 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP22_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP22_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP22 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP21_Pos 1 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP21 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP21_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP21_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP21 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP20_Pos 0 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP20 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP20_Msk (0x1UL /*<< NONSEC_PRIV_CTRL_AHBNSPPPCEXP2_AHBNSPPPCEXP20_Pos*/) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP2: AHBNSPPPCEXP20 Mask */ + +/* NONSEC_PRIV_CTRL AHBNSPPPCEXP3 Register Definitions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP315_Pos 15 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP315 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP315_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP315_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP315 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP314_Pos 14 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP314 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP314_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP314_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP314 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP313_Pos 13 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP313 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP313_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP313_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP313 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP312_Pos 12 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP312 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP312_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP312_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP312 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP311_Pos 11 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP311 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP311_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP311_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP311 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP310_Pos 10 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP310 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP310_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP310_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP310 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP39_Pos 9 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP39 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP39_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP39_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP39 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP38_Pos 8 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP38 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP38_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP38_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP38 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP37_Pos 7 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP37 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP37_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP37_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP37 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP36_Pos 6 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP36 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP36_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP36_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP36 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP35_Pos 5 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP35 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP35_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP35_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP35 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP34_Pos 4 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP34 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP34_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP34_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP34 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP33_Pos 3 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP33 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP33_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP33_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP33 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP32_Pos 2 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP32 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP32_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP32_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP32 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP31_Pos 1 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP31 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP31_Msk (0x1UL << NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP31_Pos) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP31 Mask */ + +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP30_Pos 0 /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP30 Positions */ +#define NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP30_Msk (0x1UL /*<< NONSEC_PRIV_CTRL_AHBNSPPPCEXP3_AHBNSPPPCEXP30_Pos*/) /* NONSEC_PRIV_CTRL AHBNSPPPCEXP3: AHBNSPPPCEXP30 Mask */ + +/* NONSEC_PRIV_CTRL APBNSPPPC0 Register Definitions */ +#define NONSEC_PRIV_CTRL_APBNSPPPC0_NSP_MHU1_Pos 4 /* NONSEC_PRIV_CTRL APBNSPPPC0: NSP_MHU1 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPC0_NSP_MHU1_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPC0_NSP_MHU1_Pos) /* NONSEC_PRIV_CTRL APBNSPPPC0: NSP_MHU1 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPC0_NSP_MHU0_Pos 3 /* NONSEC_PRIV_CTRL APBNSPPPC0: NSP_MHU0 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPC0_NSP_MHU0_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPC0_NSP_MHU0_Pos) /* NONSEC_PRIV_CTRL APBNSPPPC0: NSP_MHU0 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPC0_NSP_DTIMER_Pos 2 /* NONSEC_PRIV_CTRL APBNSPPPC0: NSP_DTIMER Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPC0_NSP_DTIMER_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPC0_NSP_DTIMER_Pos) /* NONSEC_PRIV_CTRL APBNSPPPC0: NSP_DTIMER Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPC0_NSP_TIMER1_Pos 1 /* NONSEC_PRIV_CTRL APBNSPPPC0: NSP_TIMER1 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPC0_NSP_TIMER1_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPC0_NSP_TIMER1_Pos) /* NONSEC_PRIV_CTRL APBNSPPPC0: NSP_TIMER1 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPC0_NSP_TIMER0_Pos 0 /* NONSEC_PRIV_CTRL APBNSPPPC0: NSP_TIMER0 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPC0_NSP_TIMER0_Msk (0x1UL /*<< NONSEC_PRIV_CTRL_APBNSPPPC0_NSP_TIMER0_Pos*/) /* NONSEC_PRIV_CTRL APBNSPPPC0: NSP_TIMER0 Mask */ + +/* NONSEC_PRIV_CTRL APBNSPPPC1 Register Definitions */ +#define NONSEC_PRIV_CTRL_APBNSPPPC1_NSP_S32K_Timer_Pos 0 /* NONSEC_PRIV_CTRL APBNSPPPC1: NSP_S32K_Timer Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPC1_NSP_S32K_Timer_Msk (0x1UL /*<< NONSEC_PRIV_CTRL_APBNSPPPC1_NSP_S32K_Timer_Pos*/) /* NONSEC_PRIV_CTRL APBNSPPPC1: NSP_S32K_Timer Mask */ + +/* NONSEC_PRIV_CTRL APBNSPPPCEXP0 Register Definitions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_QSPI_Pos 15 /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: QSPI Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_QSPI_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP0_QSPI_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: QSPI Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_SLWTIMER_Pos 14 /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: SLWTIMER Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_SLWTIMER_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP0_SLWTIMER_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: SLWTIMER Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_SPI1_Pos 13 /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: SPI1 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_SPI1_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP0_SPI1_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: SPI1 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_QDEC_Pos 12 /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: QDEC Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_QDEC_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP0_QDEC_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: QDEC Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_SPI2_Pos 11 /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: SPI2 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_SPI2_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP0_SPI2_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: SPI2 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_KSM_Pos 10 /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: KSM Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_KSM_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP0_KSM_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: KSM Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_APBNSPPPCEXP09_Pos 9 /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: APBNSPPPCEXP09 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_APBNSPPPCEXP09_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP0_APBNSPPPCEXP09_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: APBNSPPPCEXP09 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_APBNSPPPCEXP08_Pos 8 /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: APBNSPPPCEXP08 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_APBNSPPPCEXP08_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP0_APBNSPPPCEXP08_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: APBNSPPPCEXP08 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_SPI0_Pos 7 /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: SPI0 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_SPI0_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP0_SPI0_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: SPI0 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_PWM_Pos 6 /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: PWM Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_PWM_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP0_PWM_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: PWM Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_UART1_Pos 5 /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: UART1 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_UART1_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP0_UART1_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: UART1 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_UART0_Pos 4 /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: UART0 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_UART0_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP0_UART0_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: UART0 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_WRPR_Pos 3 /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: WRPR Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_WRPR_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP0_WRPR_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: WRPR Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_APBNSPPPCEXP02_Pos 2 /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: APBNSPPPCEXP02 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_APBNSPPPCEXP02_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP0_APBNSPPPCEXP02_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: APBNSPPPCEXP02 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_APBNSPPPCEXP01_Pos 1 /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: APBNSPPPCEXP01 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_APBNSPPPCEXP01_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP0_APBNSPPPCEXP01_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: APBNSPPPCEXP01 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_APBNSPPPCEXP00_Pos 0 /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: APBNSPPPCEXP00 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP0_APBNSPPPCEXP00_Msk (0x1UL /*<< NONSEC_PRIV_CTRL_APBNSPPPCEXP0_APBNSPPPCEXP00_Pos*/) /* NONSEC_PRIV_CTRL APBNSPPPCEXP0: APBNSPPPCEXP00 Mask */ + +/* NONSEC_PRIV_CTRL APBNSPPPCEXP1 Register Definitions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_APBNSPPPCEXP115_Pos 15 /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: APBNSPPPCEXP115 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_APBNSPPPCEXP115_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP1_APBNSPPPCEXP115_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: APBNSPPPCEXP115 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_ATLC_Pos 14 /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: ATLC Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_ATLC_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP1_ATLC_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: ATLC Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_SHUB_Pos 13 /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: SHUB Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_SHUB_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP1_SHUB_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: SHUB Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_RCOS_CAL_Pos 12 /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: RCOS_CAL Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_RCOS_CAL_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP1_RCOS_CAL_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: RCOS_CAL Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_TRNG_Pos 11 /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: TRNG Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_TRNG_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP1_TRNG_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: TRNG Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_GADC_Pos 10 /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: GADC Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_GADC_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP1_GADC_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: GADC Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_SWD_Pos 9 /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: SWD Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_SWD_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP1_SWD_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: SWD Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_PSEQ_Pos 8 /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: PSEQ Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_PSEQ_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP1_PSEQ_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: PSEQ Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_PMU_Pos 7 /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: PMU Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_PMU_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP1_PMU_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: PMU Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_MDM_Pos 6 /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: MDM Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_MDM_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP1_MDM_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: MDM Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_RADIO_Pos 5 /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: RADIO Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_RADIO_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP1_RADIO_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: RADIO Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_RIF_Pos 4 /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: RIF Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_RIF_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP1_RIF_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: RIF Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_WRPR_Pos 3 /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: WRPR Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_WRPR_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP1_WRPR_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: WRPR Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_NVM_Pos 2 /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: NVM Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_NVM_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP1_NVM_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: NVM Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_I2C1_Pos 1 /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: I2C1 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_I2C1_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP1_I2C1_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: I2C1 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_I2C0_Pos 0 /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: I2C0 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP1_I2C0_Msk (0x1UL /*<< NONSEC_PRIV_CTRL_APBNSPPPCEXP1_I2C0_Pos*/) /* NONSEC_PRIV_CTRL APBNSPPPCEXP1: I2C0 Mask */ + +/* NONSEC_PRIV_CTRL APBNSPPPCEXP2 Register Definitions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP215_Pos 15 /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: APBNSPPPCEXP215 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP215_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP215_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: APBNSPPPCEXP215 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP214_Pos 14 /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: APBNSPPPCEXP214 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP214_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP214_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: APBNSPPPCEXP214 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP213_Pos 13 /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: APBNSPPPCEXP213 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP213_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP213_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: APBNSPPPCEXP213 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP212_Pos 12 /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: APBNSPPPCEXP212 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP212_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP212_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: APBNSPPPCEXP212 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP211_Pos 11 /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: APBNSPPPCEXP211 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP211_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP211_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: APBNSPPPCEXP211 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP210_Pos 10 /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: APBNSPPPCEXP210 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP210_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP210_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: APBNSPPPCEXP210 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP29_Pos 9 /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: APBNSPPPCEXP29 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP29_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP29_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: APBNSPPPCEXP29 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP28_Pos 8 /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: APBNSPPPCEXP28 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP28_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP28_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: APBNSPPPCEXP28 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_AES_Pos 7 /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: AES Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_AES_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP2_AES_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: AES Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_CLKRSTGEN_Pos 6 /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: CLKRSTGEN Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_CLKRSTGEN_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP2_CLKRSTGEN_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: CLKRSTGEN Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_I2S_Pos 5 /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: I2S Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_I2S_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP2_I2S_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: I2S Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP24_Pos 4 /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: APBNSPPPCEXP24 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP24_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP24_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: APBNSPPPCEXP24 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_WRPR_Pos 3 /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: WRPR Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_WRPR_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP2_WRPR_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: WRPR Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP22_Pos 2 /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: APBNSPPPCEXP22 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP22_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP2_APBNSPPPCEXP22_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: APBNSPPPCEXP22 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_PDM1_Pos 1 /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: PDM1 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_PDM1_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP2_PDM1_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: PDM1 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_PDM0_Pos 0 /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: PDM0 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP2_PDM0_Msk (0x1UL /*<< NONSEC_PRIV_CTRL_APBNSPPPCEXP2_PDM0_Pos*/) /* NONSEC_PRIV_CTRL APBNSPPPCEXP2: PDM0 Mask */ + +/* NONSEC_PRIV_CTRL APBNSPPPCEXP3 Register Definitions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP315_Pos 15 /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP315 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP315_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP315_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP315 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP314_Pos 14 /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP314 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP314_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP314_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP314 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP313_Pos 13 /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP313 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP313_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP313_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP313 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP312_Pos 12 /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP312 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP312_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP312_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP312 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP311_Pos 11 /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP311 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP311_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP311_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP311 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP310_Pos 10 /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP310 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP310_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP310_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP310 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP39_Pos 9 /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP39 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP39_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP39_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP39 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP38_Pos 8 /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP38 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP38_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP38_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP38 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP37_Pos 7 /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP37 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP37_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP37_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP37 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP36_Pos 6 /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP36 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP36_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP36_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP36 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP35_Pos 5 /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP35 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP35_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP35_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP35 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP34_Pos 4 /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP34 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP34_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP34_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP34 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP33_Pos 3 /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP33 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP33_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP33_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP33 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP32_Pos 2 /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP32 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP32_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP32_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP32 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP31_Pos 1 /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP31 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP31_Msk (0x1UL << NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP31_Pos) /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP31 Mask */ + +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP30_Pos 0 /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP30 Positions */ +#define NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP30_Msk (0x1UL /*<< NONSEC_PRIV_CTRL_APBNSPPPCEXP3_APBNSPPPCEXP30_Pos*/) /* NONSEC_PRIV_CTRL APBNSPPPCEXP3: APBNSPPPCEXP30 Mask */ + +/* NONSEC_PRIV_CTRL PIDR4 Register Definitions */ +#define NONSEC_PRIV_CTRL_PIDR4_SIZE_Pos 4 /* NONSEC_PRIV_CTRL PIDR4: SIZE Positions */ +#define NONSEC_PRIV_CTRL_PIDR4_SIZE_Msk (0xFUL << NONSEC_PRIV_CTRL_PIDR4_SIZE_Pos) /* NONSEC_PRIV_CTRL PIDR4: SIZE Mask */ + +#define NONSEC_PRIV_CTRL_PIDR4_DES_2_Pos 0 /* NONSEC_PRIV_CTRL PIDR4: DES_2 Positions */ +#define NONSEC_PRIV_CTRL_PIDR4_DES_2_Msk (0xFUL /*<< NONSEC_PRIV_CTRL_PIDR4_DES_2_Pos*/) /* NONSEC_PRIV_CTRL PIDR4: DES_2 Mask */ + +/* NONSEC_PRIV_CTRL PIDR0 Register Definitions */ +#define NONSEC_PRIV_CTRL_PIDR0_PART_0_Pos 0 /* NONSEC_PRIV_CTRL PIDR0: PART_0 Positions */ +#define NONSEC_PRIV_CTRL_PIDR0_PART_0_Msk (0xFFUL /*<< NONSEC_PRIV_CTRL_PIDR0_PART_0_Pos*/) /* NONSEC_PRIV_CTRL PIDR0: PART_0 Mask */ + +/* NONSEC_PRIV_CTRL PIDR1 Register Definitions */ +#define NONSEC_PRIV_CTRL_PIDR1_DES_0_Pos 4 /* NONSEC_PRIV_CTRL PIDR1: DES_0 Positions */ +#define NONSEC_PRIV_CTRL_PIDR1_DES_0_Msk (0xFUL << NONSEC_PRIV_CTRL_PIDR1_DES_0_Pos) /* NONSEC_PRIV_CTRL PIDR1: DES_0 Mask */ + +#define NONSEC_PRIV_CTRL_PIDR1_PART_1_Pos 0 /* NONSEC_PRIV_CTRL PIDR1: PART_1 Positions */ +#define NONSEC_PRIV_CTRL_PIDR1_PART_1_Msk (0xFUL /*<< NONSEC_PRIV_CTRL_PIDR1_PART_1_Pos*/) /* NONSEC_PRIV_CTRL PIDR1: PART_1 Mask */ + +/* NONSEC_PRIV_CTRL PIDR2 Register Definitions */ +#define NONSEC_PRIV_CTRL_PIDR2_REVISION_Pos 4 /* NONSEC_PRIV_CTRL PIDR2: REVISION Positions */ +#define NONSEC_PRIV_CTRL_PIDR2_REVISION_Msk (0xFUL << NONSEC_PRIV_CTRL_PIDR2_REVISION_Pos) /* NONSEC_PRIV_CTRL PIDR2: REVISION Mask */ + +#define NONSEC_PRIV_CTRL_PIDR2_JEDEC_Pos 3 /* NONSEC_PRIV_CTRL PIDR2: JEDEC Positions */ +#define NONSEC_PRIV_CTRL_PIDR2_JEDEC_Msk (0x1UL << NONSEC_PRIV_CTRL_PIDR2_JEDEC_Pos) /* NONSEC_PRIV_CTRL PIDR2: JEDEC Mask */ + +#define NONSEC_PRIV_CTRL_PIDR2_DES_1_Pos 0 /* NONSEC_PRIV_CTRL PIDR2: DES_1 Positions */ +#define NONSEC_PRIV_CTRL_PIDR2_DES_1_Msk (0x7UL /*<< NONSEC_PRIV_CTRL_PIDR2_DES_1_Pos*/) /* NONSEC_PRIV_CTRL PIDR2: DES_1 Mask */ + +/* NONSEC_PRIV_CTRL PIDR3 Register Definitions */ +#define NONSEC_PRIV_CTRL_PIDR3_REVAND_Pos 4 /* NONSEC_PRIV_CTRL PIDR3: REVAND Positions */ +#define NONSEC_PRIV_CTRL_PIDR3_REVAND_Msk (0xFUL << NONSEC_PRIV_CTRL_PIDR3_REVAND_Pos) /* NONSEC_PRIV_CTRL PIDR3: REVAND Mask */ + +#define NONSEC_PRIV_CTRL_PIDR3_CMOD_Pos 0 /* NONSEC_PRIV_CTRL PIDR3: CMOD Positions */ +#define NONSEC_PRIV_CTRL_PIDR3_CMOD_Msk (0xFUL /*<< NONSEC_PRIV_CTRL_PIDR3_CMOD_Pos*/) /* NONSEC_PRIV_CTRL PIDR3: CMOD Mask */ + +/* NONSEC_PRIV_CTRL CIDR0 Register Definitions */ +#define NONSEC_PRIV_CTRL_CIDR0_PRMBL_0_Pos 0 /* NONSEC_PRIV_CTRL CIDR0: PRMBL_0 Positions */ +#define NONSEC_PRIV_CTRL_CIDR0_PRMBL_0_Msk (0xFFUL /*<< NONSEC_PRIV_CTRL_CIDR0_PRMBL_0_Pos*/) /* NONSEC_PRIV_CTRL CIDR0: PRMBL_0 Mask */ + +/* NONSEC_PRIV_CTRL CIDR1 Register Definitions */ +#define NONSEC_PRIV_CTRL_CIDR1_CLASS_Pos 4 /* NONSEC_PRIV_CTRL CIDR1: CLASS Positions */ +#define NONSEC_PRIV_CTRL_CIDR1_CLASS_Msk (0xFUL << NONSEC_PRIV_CTRL_CIDR1_CLASS_Pos) /* NONSEC_PRIV_CTRL CIDR1: CLASS Mask */ + +#define NONSEC_PRIV_CTRL_CIDR1_PRMBL_1_Pos 0 /* NONSEC_PRIV_CTRL CIDR1: PRMBL_1 Positions */ +#define NONSEC_PRIV_CTRL_CIDR1_PRMBL_1_Msk (0xFUL /*<< NONSEC_PRIV_CTRL_CIDR1_PRMBL_1_Pos*/) /* NONSEC_PRIV_CTRL CIDR1: PRMBL_1 Mask */ + +/* NONSEC_PRIV_CTRL CIDR2 Register Definitions */ +#define NONSEC_PRIV_CTRL_CIDR2_PRMBL_2_Pos 0 /* NONSEC_PRIV_CTRL CIDR2: PRMBL_2 Positions */ +#define NONSEC_PRIV_CTRL_CIDR2_PRMBL_2_Msk (0xFFUL /*<< NONSEC_PRIV_CTRL_CIDR2_PRMBL_2_Pos*/) /* NONSEC_PRIV_CTRL CIDR2: PRMBL_2 Mask */ + +/* NONSEC_PRIV_CTRL CIDR3 Register Definitions */ +#define NONSEC_PRIV_CTRL_CIDR3_PRMBL_3_Pos 0 /* NONSEC_PRIV_CTRL CIDR3: PRMBL_3 Positions */ +#define NONSEC_PRIV_CTRL_CIDR3_PRMBL_3_Msk (0xFFUL /*<< NONSEC_PRIV_CTRL_CIDR3_PRMBL_3_Pos*/) /* NONSEC_PRIV_CTRL CIDR3: PRMBL_3 Mask */ + +/*---------------- MHU ----------------*/ +typedef struct +{ +__IM uint32_t CPU0INTR_STAT; /* Offset: 0x0 (read-only) CPU0INTR_STAT Register */ +__OM uint32_t CPU0INTR_SET; /* Offset: 0x4 (write-only) CPU0INTR_SET Register */ +__OM uint32_t CPU0INTR_CLR; /* Offset: 0x8 (write-only) CPU0INTR_CLR Register */ + uint32_t RESERVED0[1]; +__IM uint32_t CPU1INTR_STAT; /* Offset: 0x10 (read-only) CPU1INTR_STAT Register */ +__OM uint32_t CPU1INTR_SET; /* Offset: 0x14 (write-only) CPU1INTR_SET Register */ +__OM uint32_t CPU1INTR_CLR; /* Offset: 0x18 (write-only) CPU1INTR_CLR Register */ + uint32_t RESERVED1[1005]; +__IM uint32_t PIDR4; /* Offset: 0xFD0 (read-only) PIDR4 Register */ + uint32_t RESERVED2[3]; +__IM uint32_t PIDR0; /* Offset: 0xFE0 (read-only) PIDR0 Register */ +__IM uint32_t PIDR1; /* Offset: 0xFE4 (read-only) PIDR1 Register */ +__IM uint32_t PIDR2; /* Offset: 0xFE8 (read-only) PIDR2 Register */ +__IM uint32_t PIDR3; /* Offset: 0xFEC (read-only) PIDR3 Register */ +__IM uint32_t CIDR0; /* Offset: 0xFF0 (read-only) CIDR0 Register */ +__IM uint32_t CIDR1; /* Offset: 0xFF4 (read-only) CIDR1 Register */ +__IM uint32_t CIDR2; /* Offset: 0xFF8 (read-only) CIDR2 Register */ +__IM uint32_t CIDR3; /* Offset: 0xFFC (read-only) CIDR3 Register */ +}MHU_TypeDef; + +/* MHU CPU0INTR_STAT Register Definitions */ +#define MHU_CPU0INTR_STAT_CPU0INTR_STAT_Pos 0 /* MHU CPU0INTR_STAT: CPU0INTR_STAT Positions */ +#define MHU_CPU0INTR_STAT_CPU0INTR_STAT_Msk (0xFUL /*<< MHU_CPU0INTR_STAT_CPU0INTR_STAT_Pos*/) /* MHU CPU0INTR_STAT: CPU0INTR_STAT Mask */ + +/* MHU CPU0INTR_SET Register Definitions */ +#define MHU_CPU0INTR_SET_CPU0INTR_SET_Pos 0 /* MHU CPU0INTR_SET: CPU0INTR_SET Positions */ +#define MHU_CPU0INTR_SET_CPU0INTR_SET_Msk (0xFUL /*<< MHU_CPU0INTR_SET_CPU0INTR_SET_Pos*/) /* MHU CPU0INTR_SET: CPU0INTR_SET Mask */ + +/* MHU CPU0INTR_CLR Register Definitions */ +#define MHU_CPU0INTR_CLR_CPU0INTR_CLR_Pos 0 /* MHU CPU0INTR_CLR: CPU0INTR_CLR Positions */ +#define MHU_CPU0INTR_CLR_CPU0INTR_CLR_Msk (0xFUL /*<< MHU_CPU0INTR_CLR_CPU0INTR_CLR_Pos*/) /* MHU CPU0INTR_CLR: CPU0INTR_CLR Mask */ + +/* MHU CPU1INTR_STAT Register Definitions */ +#define MHU_CPU1INTR_STAT_CPU1INTR_STAT_Pos 0 /* MHU CPU1INTR_STAT: CPU1INTR_STAT Positions */ +#define MHU_CPU1INTR_STAT_CPU1INTR_STAT_Msk (0xFUL /*<< MHU_CPU1INTR_STAT_CPU1INTR_STAT_Pos*/) /* MHU CPU1INTR_STAT: CPU1INTR_STAT Mask */ + +/* MHU CPU1INTR_SET Register Definitions */ +#define MHU_CPU1INTR_SET_CPU1INTR_SET_Pos 0 /* MHU CPU1INTR_SET: CPU1INTR_SET Positions */ +#define MHU_CPU1INTR_SET_CPU1INTR_SET_Msk (0xFUL /*<< MHU_CPU1INTR_SET_CPU1INTR_SET_Pos*/) /* MHU CPU1INTR_SET: CPU1INTR_SET Mask */ + +/* MHU CPU1INTR_CLR Register Definitions */ +#define MHU_CPU1INTR_CLR_CPU1INTR_CLR_Pos 0 /* MHU CPU1INTR_CLR: CPU1INTR_CLR Positions */ +#define MHU_CPU1INTR_CLR_CPU1INTR_CLR_Msk (0xFUL /*<< MHU_CPU1INTR_CLR_CPU1INTR_CLR_Pos*/) /* MHU CPU1INTR_CLR: CPU1INTR_CLR Mask */ + +/* MHU PIDR4 Register Definitions */ +#define MHU_PIDR4_SIZE_Pos 4 /* MHU PIDR4: SIZE Positions */ +#define MHU_PIDR4_SIZE_Msk (0xFUL << MHU_PIDR4_SIZE_Pos) /* MHU PIDR4: SIZE Mask */ + +#define MHU_PIDR4_DES_2_Pos 0 /* MHU PIDR4: DES_2 Positions */ +#define MHU_PIDR4_DES_2_Msk (0xFUL /*<< MHU_PIDR4_DES_2_Pos*/) /* MHU PIDR4: DES_2 Mask */ + +/* MHU PIDR0 Register Definitions */ +#define MHU_PIDR0_PART_0_Pos 0 /* MHU PIDR0: PART_0 Positions */ +#define MHU_PIDR0_PART_0_Msk (0xFFUL /*<< MHU_PIDR0_PART_0_Pos*/) /* MHU PIDR0: PART_0 Mask */ + +/* MHU PIDR1 Register Definitions */ +#define MHU_PIDR1_DES_0_Pos 4 /* MHU PIDR1: DES_0 Positions */ +#define MHU_PIDR1_DES_0_Msk (0xFUL << MHU_PIDR1_DES_0_Pos) /* MHU PIDR1: DES_0 Mask */ + +#define MHU_PIDR1_PART_1_Pos 0 /* MHU PIDR1: PART_1 Positions */ +#define MHU_PIDR1_PART_1_Msk (0xFUL /*<< MHU_PIDR1_PART_1_Pos*/) /* MHU PIDR1: PART_1 Mask */ + +/* MHU PIDR2 Register Definitions */ +#define MHU_PIDR2_REVISION_Pos 4 /* MHU PIDR2: REVISION Positions */ +#define MHU_PIDR2_REVISION_Msk (0xFUL << MHU_PIDR2_REVISION_Pos) /* MHU PIDR2: REVISION Mask */ + +#define MHU_PIDR2_JEDEC_Pos 3 /* MHU PIDR2: JEDEC Positions */ +#define MHU_PIDR2_JEDEC_Msk (0x1UL << MHU_PIDR2_JEDEC_Pos) /* MHU PIDR2: JEDEC Mask */ + +#define MHU_PIDR2_DES_1_Pos 0 /* MHU PIDR2: DES_1 Positions */ +#define MHU_PIDR2_DES_1_Msk (0x7UL /*<< MHU_PIDR2_DES_1_Pos*/) /* MHU PIDR2: DES_1 Mask */ + +/* MHU PIDR3 Register Definitions */ +#define MHU_PIDR3_REVAND_Pos 4 /* MHU PIDR3: REVAND Positions */ +#define MHU_PIDR3_REVAND_Msk (0xFUL << MHU_PIDR3_REVAND_Pos) /* MHU PIDR3: REVAND Mask */ + +#define MHU_PIDR3_CMOD_Pos 0 /* MHU PIDR3: CMOD Positions */ +#define MHU_PIDR3_CMOD_Msk (0xFUL /*<< MHU_PIDR3_CMOD_Pos*/) /* MHU PIDR3: CMOD Mask */ + +/* MHU CIDR0 Register Definitions */ +#define MHU_CIDR0_PRMBL_0_Pos 0 /* MHU CIDR0: PRMBL_0 Positions */ +#define MHU_CIDR0_PRMBL_0_Msk (0xFFUL /*<< MHU_CIDR0_PRMBL_0_Pos*/) /* MHU CIDR0: PRMBL_0 Mask */ + +/* MHU CIDR1 Register Definitions */ +#define MHU_CIDR1_CLASS_Pos 4 /* MHU CIDR1: CLASS Positions */ +#define MHU_CIDR1_CLASS_Msk (0xFUL << MHU_CIDR1_CLASS_Pos) /* MHU CIDR1: CLASS Mask */ + +#define MHU_CIDR1_PRMBL_1_Pos 0 /* MHU CIDR1: PRMBL_1 Positions */ +#define MHU_CIDR1_PRMBL_1_Msk (0xFUL /*<< MHU_CIDR1_PRMBL_1_Pos*/) /* MHU CIDR1: PRMBL_1 Mask */ + +/* MHU CIDR2 Register Definitions */ +#define MHU_CIDR2_PRMBL_2_Pos 0 /* MHU CIDR2: PRMBL_2 Positions */ +#define MHU_CIDR2_PRMBL_2_Msk (0xFFUL /*<< MHU_CIDR2_PRMBL_2_Pos*/) /* MHU CIDR2: PRMBL_2 Mask */ + +/* MHU CIDR3 Register Definitions */ +#define MHU_CIDR3_PRMBL_3_Pos 0 /* MHU CIDR3: PRMBL_3 Positions */ +#define MHU_CIDR3_PRMBL_3_Msk (0xFFUL /*<< MHU_CIDR3_PRMBL_3_Pos*/) /* MHU CIDR3: PRMBL_3 Mask */ + +/*----------------------------- ICACHE ---------------------------------------------*/ +typedef struct +{ +__IM uint32_t ICHWPARAMS; /* Offset: 0x0 (read-only) ICHWPARAMS Register */ +__IOM uint32_t ICCTRL; /* Offset: 0x4 (read-write) ICCTRL Register */ + uint32_t RESERVED1[62]; +__IM uint32_t ICIRQSTAT; /* Offset: 0x100 (read-only) ICIRQSTAT Register */ +__OM uint32_t ICIRQSCLR; /* Offset: 0x104 (write-only) ICIRQSCLR Register */ +__IOM uint32_t ICIRQEN; /* Offset: 0x108 (read-write) ICIRQEN Register */ +__IM uint32_t ICDBGFILLERR; /* Offset: 0x10C (read-only) ICDBGFILLERR Register */ + uint32_t RESERVED2[124]; +__IM uint32_t ICSH; /* Offset: 0x300 (read-only) ICSH Register */ +__IM uint32_t ICSM; /* Offset: 0x304 (read-only) ICSM Register */ +__IM uint32_t ICSUC; /* Offset: 0x308 (read-only) ICSUC Register */ + uint32_t RESERVED3[817]; +__IM uint32_t PIDR4; /* Offset: 0xFD0 (read-only) PIDR4 Register */ + uint32_t RESERVED4[3]; +__IM uint32_t PIDR0; /* Offset: 0xFE0 (read-only) PIDR0 Register */ +__IM uint32_t PIDR1; /* Offset: 0xFE4 (read-only) PIDR1 Register */ +__IM uint32_t PIDR2; /* Offset: 0xFE8 (read-only) PIDR2 Register */ +__IM uint32_t PIDR3; /* Offset: 0xFEC (read-only) PIDR3 Register */ +__IM uint32_t CIDR0; /* Offset: 0xFF0 (read-only) CIDR0 Register */ +__IM uint32_t CIDR1; /* Offset: 0xFF4 (read-only) CIDR1 Register */ +__IM uint32_t CIDR2; /* Offset: 0xFF8 (read-only) CIDR2 Register */ +__IM uint32_t CIDR3; /* Offset: 0xFFC (read-only) CIDR3 Register */ +}ICACHE_TypeDef; + +/* ICACHE ICHWPARAMS Register Definitions */ +#define ICACHE_ICHWPARAMS_COFFSET_Pos 16 /* ICACHE ICHWPARAMS: COFFSET Positions */ +#define ICACHE_ICHWPARAMS_COFFSET_Msk (0xFFFFUL << ICACHE_ICHWPARAMS_COFFSET_Pos) /* ICACHE ICHWPARAMS: COFFSET Mask */ + +#define ICACHE_ICHWPARAMS_COFFSIZE_Pos 12 /* ICACHE ICHWPARAMS: COFFSIZE Positions */ +#define ICACHE_ICHWPARAMS_COFFSIZE_Msk (0xFUL << ICACHE_ICHWPARAMS_COFFSIZE_Pos) /* ICACHE ICHWPARAMS: COFFSIZE Mask */ + +#define ICACHE_ICHWPARAMS_INVMAT_Pos 6 /* ICACHE ICHWPARAMS: INVMAT Positions */ +#define ICACHE_ICHWPARAMS_INVMAT_Msk (0x1UL << ICACHE_ICHWPARAMS_INVMAT_Pos) /* ICACHE ICHWPARAMS: INVMAT Mask */ + +#define ICACHE_ICHWPARAMS_DMA_Pos 5 /* ICACHE ICHWPARAMS: DMA Positions */ +#define ICACHE_ICHWPARAMS_DMA_Msk (0x1UL << ICACHE_ICHWPARAMS_DMA_Pos) /* ICACHE ICHWPARAMS: DMA Mask */ + +#define ICACHE_ICHWPARAMS_STATS_Pos 4 /* ICACHE ICHWPARAMS: STATS Positions */ +#define ICACHE_ICHWPARAMS_STATS_Msk (0x1UL << ICACHE_ICHWPARAMS_STATS_Pos) /* ICACHE ICHWPARAMS: STATS Mask */ + +#define ICACHE_ICHWPARAMS_CSIZE_Pos 0 /* ICACHE ICHWPARAMS: CSIZE Positions */ +#define ICACHE_ICHWPARAMS_CSIZE_Msk (0xFUL /*<< ICACHE_ICHWPARAMS_CSIZE_Pos*/) /* ICACHE ICHWPARAMS: CSIZE Mask */ + +/* ICACHE ICCTRL Register Definitions */ +#define ICACHE_ICCTRL_HALLOC_Pos 5 /* ICACHE ICCTRL: HALLOC Positions */ +#define ICACHE_ICCTRL_HALLOC_Msk (0x1UL << ICACHE_ICCTRL_HALLOC_Pos) /* ICACHE ICCTRL: HALLOC Mask */ + +#define ICACHE_ICCTRL_STATC_Pos 4 /* ICACHE ICCTRL: STATC Positions */ +#define ICACHE_ICCTRL_STATC_Msk (0x1UL << ICACHE_ICCTRL_STATC_Pos) /* ICACHE ICCTRL: STATC Mask */ + +#define ICACHE_ICCTRL_STATEN_Pos 3 /* ICACHE ICCTRL: STATEN Positions */ +#define ICACHE_ICCTRL_STATEN_Msk (0x1UL << ICACHE_ICCTRL_STATEN_Pos) /* ICACHE ICCTRL: STATEN Mask */ + +#define ICACHE_ICCTRL_FINV_Pos 2 /* ICACHE ICCTRL: FINV Positions */ +#define ICACHE_ICCTRL_FINV_Msk (0x1UL << ICACHE_ICCTRL_FINV_Pos) /* ICACHE ICCTRL: FINV Mask */ + +#define ICACHE_ICCTRL_PINV_Pos 1 /* ICACHE ICCTRL: PINV Positions */ +#define ICACHE_ICCTRL_PINV_Msk (0x1UL << ICACHE_ICCTRL_PINV_Pos) /* ICACHE ICCTRL: PINV Mask */ + +#define ICACHE_ICCTRL_CACHEEN_Pos 0 /* ICACHE ICCTRL: CACHEEN Positions */ +#define ICACHE_ICCTRL_CACHEEN_Msk (0x1UL /*<< ICACHE_ICCTRL_CACHEEN_Pos*/) /* ICACHE ICCTRL: CACHEEN Mask */ + +/* ICACHE ICIRQSTAT Register Definitions */ +#define ICACHE_ICIRQSTAT_DLE_STATUS_Pos 8 /* ICACHE ICIRQSTAT: DLE_STATUS Positions */ +#define ICACHE_ICIRQSTAT_DLE_STATUS_Msk (0x1UL << ICACHE_ICIRQSTAT_DLE_STATUS_Pos) /* ICACHE ICIRQSTAT: DLE_STATUS Mask */ + +#define ICACHE_ICIRQSTAT_DFA_STATUS_Pos 7 /* ICACHE ICIRQSTAT: DFA_STATUS Positions */ +#define ICACHE_ICIRQSTAT_DFA_STATUS_Msk (0x1UL << ICACHE_ICIRQSTAT_DFA_STATUS_Pos) /* ICACHE ICIRQSTAT: DFA_STATUS Mask */ + +#define ICACHE_ICIRQSTAT_DFC_STATUS_Pos 6 /* ICACHE ICIRQSTAT: DFC_STATUS Positions */ +#define ICACHE_ICIRQSTAT_DFC_STATUS_Msk (0x1UL << ICACHE_ICIRQSTAT_DFC_STATUS_Pos) /* ICACHE ICIRQSTAT: DFC_STATUS Mask */ + +#define ICACHE_ICIRQSTAT_SS_STATUS_Pos 5 /* ICACHE ICIRQSTAT: SS_STATUS Positions */ +#define ICACHE_ICIRQSTAT_SS_STATUS_Msk (0x1UL << ICACHE_ICIRQSTAT_SS_STATUS_Pos) /* ICACHE ICIRQSTAT: SS_STATUS Mask */ + +#define ICACHE_ICIRQSTAT_SV_STATUS_Pos 4 /* ICACHE ICIRQSTAT: SV_STATUS Positions */ +#define ICACHE_ICIRQSTAT_SV_STATUS_Msk (0x1UL << ICACHE_ICIRQSTAT_SV_STATUS_Pos) /* ICACHE ICIRQSTAT: SV_STATUS Mask */ + +#define ICACHE_ICIRQSTAT_CFE_STATUS_Pos 3 /* ICACHE ICIRQSTAT: CFE_STATUS Positions */ +#define ICACHE_ICIRQSTAT_CFE_STATUS_Msk (0x1UL << ICACHE_ICIRQSTAT_CFE_STATUS_Pos) /* ICACHE ICIRQSTAT: CFE_STATUS Mask */ + +#define ICACHE_ICIRQSTAT_CEC_STATUS_Pos 2 /* ICACHE ICIRQSTAT: CEC_STATUS Positions */ +#define ICACHE_ICIRQSTAT_CEC_STATUS_Msk (0x1UL << ICACHE_ICIRQSTAT_CEC_STATUS_Pos) /* ICACHE ICIRQSTAT: CEC_STATUS Mask */ + +#define ICACHE_ICIRQSTAT_CDC_STATUS_Pos 1 /* ICACHE ICIRQSTAT: CDC_STATUS Positions */ +#define ICACHE_ICIRQSTAT_CDC_STATUS_Msk (0x1UL << ICACHE_ICIRQSTAT_CDC_STATUS_Pos) /* ICACHE ICIRQSTAT: CDC_STATUS Mask */ + +#define ICACHE_ICIRQSTAT_IC_STATUS_Pos 0 /* ICACHE ICIRQSTAT: IC_STATUS Positions */ +#define ICACHE_ICIRQSTAT_IC_STATUS_Msk (0x1UL /*<< ICACHE_ICIRQSTAT_IC_STATUS_Pos*/) /* ICACHE ICIRQSTAT: IC_STATUS Mask */ + +/* ICACHE ICIRQSCLR Register Definitions */ +#define ICACHE_ICIRQSCLR_DLE_CLR_Pos 8 /* ICACHE ICIRQSCLR: DLE_CLR Positions */ +#define ICACHE_ICIRQSCLR_DLE_CLR_Msk (0x1UL << ICACHE_ICIRQSCLR_DLE_CLR_Pos) /* ICACHE ICIRQSCLR: DLE_CLR Mask */ + +#define ICACHE_ICIRQSCLR_DFA_CLR_Pos 7 /* ICACHE ICIRQSCLR: DFA_CLR Positions */ +#define ICACHE_ICIRQSCLR_DFA_CLR_Msk (0x1UL << ICACHE_ICIRQSCLR_DFA_CLR_Pos) /* ICACHE ICIRQSCLR: DFA_CLR Mask */ + +#define ICACHE_ICIRQSCLR_DFC_CLR_Pos 6 /* ICACHE ICIRQSCLR: DFC_CLR Positions */ +#define ICACHE_ICIRQSCLR_DFC_CLR_Msk (0x1UL << ICACHE_ICIRQSCLR_DFC_CLR_Pos) /* ICACHE ICIRQSCLR: DFC_CLR Mask */ + +#define ICACHE_ICIRQSCLR_SS_CLR_Pos 5 /* ICACHE ICIRQSCLR: SS_CLR Positions */ +#define ICACHE_ICIRQSCLR_SS_CLR_Msk (0x1UL << ICACHE_ICIRQSCLR_SS_CLR_Pos) /* ICACHE ICIRQSCLR: SS_CLR Mask */ + +#define ICACHE_ICIRQSCLR_SV_CLR_Pos 4 /* ICACHE ICIRQSCLR: SV_CLR Positions */ +#define ICACHE_ICIRQSCLR_SV_CLR_Msk (0x1UL << ICACHE_ICIRQSCLR_SV_CLR_Pos) /* ICACHE ICIRQSCLR: SV_CLR Mask */ + +#define ICACHE_ICIRQSCLR_CFE_CLR_Pos 3 /* ICACHE ICIRQSCLR: CFE_CLR Positions */ +#define ICACHE_ICIRQSCLR_CFE_CLR_Msk (0x1UL << ICACHE_ICIRQSCLR_CFE_CLR_Pos) /* ICACHE ICIRQSCLR: CFE_CLR Mask */ + +#define ICACHE_ICIRQSCLR_CEC_CLR_Pos 2 /* ICACHE ICIRQSCLR: CEC_CLR Positions */ +#define ICACHE_ICIRQSCLR_CEC_CLR_Msk (0x1UL << ICACHE_ICIRQSCLR_CEC_CLR_Pos) /* ICACHE ICIRQSCLR: CEC_CLR Mask */ + +#define ICACHE_ICIRQSCLR_CDC_CLR_Pos 1 /* ICACHE ICIRQSCLR: CDC_CLR Positions */ +#define ICACHE_ICIRQSCLR_CDC_CLR_Msk (0x1UL << ICACHE_ICIRQSCLR_CDC_CLR_Pos) /* ICACHE ICIRQSCLR: CDC_CLR Mask */ + +#define ICACHE_ICIRQSCLR_IC_CLR_Pos 0 /* ICACHE ICIRQSCLR: IC_CLR Positions */ +#define ICACHE_ICIRQSCLR_IC_CLR_Msk (0x1UL /*<< ICACHE_ICIRQSCLR_IC_CLR_Pos*/) /* ICACHE ICIRQSCLR: IC_CLR Mask */ + +/* ICACHE ICIRQEN Register Definitions */ +#define ICACHE_ICIRQEN_DLE_EN_Pos 8 /* ICACHE ICIRQEN: DLE_EN Positions */ +#define ICACHE_ICIRQEN_DLE_EN_Msk (0x1UL << ICACHE_ICIRQEN_DLE_EN_Pos) /* ICACHE ICIRQEN: DLE_EN Mask */ + +#define ICACHE_ICIRQEN_DFA_EN_Pos 7 /* ICACHE ICIRQEN: DFA_EN Positions */ +#define ICACHE_ICIRQEN_DFA_EN_Msk (0x1UL << ICACHE_ICIRQEN_DFA_EN_Pos) /* ICACHE ICIRQEN: DFA_EN Mask */ + +#define ICACHE_ICIRQEN_DFC_EN_Pos 6 /* ICACHE ICIRQEN: DFC_EN Positions */ +#define ICACHE_ICIRQEN_DFC_EN_Msk (0x1UL << ICACHE_ICIRQEN_DFC_EN_Pos) /* ICACHE ICIRQEN: DFC_EN Mask */ + +#define ICACHE_ICIRQEN_SS_EN_Pos 5 /* ICACHE ICIRQEN: SS_EN Positions */ +#define ICACHE_ICIRQEN_SS_EN_Msk (0x1UL << ICACHE_ICIRQEN_SS_EN_Pos) /* ICACHE ICIRQEN: SS_EN Mask */ + +#define ICACHE_ICIRQEN_SV_EN_Pos 4 /* ICACHE ICIRQEN: SV_EN Positions */ +#define ICACHE_ICIRQEN_SV_EN_Msk (0x1UL << ICACHE_ICIRQEN_SV_EN_Pos) /* ICACHE ICIRQEN: SV_EN Mask */ + +#define ICACHE_ICIRQEN_CFE_EN_Pos 3 /* ICACHE ICIRQEN: CFE_EN Positions */ +#define ICACHE_ICIRQEN_CFE_EN_Msk (0x1UL << ICACHE_ICIRQEN_CFE_EN_Pos) /* ICACHE ICIRQEN: CFE_EN Mask */ + +#define ICACHE_ICIRQEN_CEC_EN_Pos 2 /* ICACHE ICIRQEN: CEC_EN Positions */ +#define ICACHE_ICIRQEN_CEC_EN_Msk (0x1UL << ICACHE_ICIRQEN_CEC_EN_Pos) /* ICACHE ICIRQEN: CEC_EN Mask */ + +#define ICACHE_ICIRQEN_CDC_EN_Pos 1 /* ICACHE ICIRQEN: CDC_EN Positions */ +#define ICACHE_ICIRQEN_CDC_EN_Msk (0x1UL << ICACHE_ICIRQEN_CDC_EN_Pos) /* ICACHE ICIRQEN: CDC_EN Mask */ + +#define ICACHE_ICIRQEN_IC_EN_Pos 0 /* ICACHE ICIRQEN: IC_EN Positions */ +#define ICACHE_ICIRQEN_IC_EN_Msk (0x1UL /*<< ICACHE_ICIRQEN_IC_EN_Pos*/) /* ICACHE ICIRQEN: IC_EN Mask */ + +/* ICACHE ICDBGFILLERR Register Definitions */ +#define ICACHE_ICDBGFILLERR_ERRADDR_Pos 0 /* ICACHE ICDBGFILLERR: ERRADDR Positions */ +#define ICACHE_ICDBGFILLERR_ERRADDR_Msk (0xFFFFFFFFUL /*<< ICACHE_ICDBGFILLERR_ERRADDR_Pos*/) /* ICACHE ICDBGFILLERR: ERRADDR Mask */ + +/* ICACHE ICFBSADD Register Definitions */ +#define ICACHE_ICFBSADD_FBSADD_Pos 4 /* ICACHE ICFBSADD: FBSADD Positions */ +#define ICACHE_ICFBSADD_FBSADD_Msk (0xFFFFFFFUL << ICACHE_ICFBSADD_FBSADD_Pos) /* ICACHE ICFBSADD: FBSADD Mask */ + +/* ICACHE ICFBSIZE Register Definitions */ +#define ICACHE_ICFBSIZE_FBSIZE_Pos 4 /* ICACHE ICFBSIZE: FBSIZE Positions */ +#define ICACHE_ICFBSIZE_FBSIZE_Msk (0xFFFUL << ICACHE_ICFBSIZE_FBSIZE_Pos) /* ICACHE ICFBSIZE: FBSIZE Mask */ + +/* ICACHE ICFBSTAT Register Definitions */ +#define ICACHE_ICFBSTAT_CURRADR_Pos 2 /* ICACHE ICFBSTAT: CURRADR Positions */ +#define ICACHE_ICFBSTAT_CURRADR_Msk (0x3FFFFFFFUL << ICACHE_ICFBSTAT_CURRADR_Pos) /* ICACHE ICFBSTAT: CURRADR Mask */ + +#define ICACHE_ICFBSTAT_FIP_Pos 0 /* ICACHE ICFBSTAT: FIP Positions */ +#define ICACHE_ICFBSTAT_FIP_Msk (0x1UL /*<< ICACHE_ICFBSTAT_FIP_Pos*/) /* ICACHE ICFBSTAT: FIP Mask */ + +/* ICACHE ICFBCTRL Register Definitions */ +#define ICACHE_ICFBCTRL_ARBOV_Pos 3 /* ICACHE ICFBCTRL: ARBOV Positions */ +#define ICACHE_ICFBCTRL_ARBOV_Msk (0x1UL << ICACHE_ICFBCTRL_ARBOV_Pos) /* ICACHE ICFBCTRL: ARBOV Mask */ + +#define ICACHE_ICFBCTRL_ARBS_Pos 2 /* ICACHE ICFBCTRL: ARBS Positions */ +#define ICACHE_ICFBCTRL_ARBS_Msk (0x1UL << ICACHE_ICFBCTRL_ARBS_Pos) /* ICACHE ICFBCTRL: ARBS Mask */ + +#define ICACHE_ICFBCTRL_SEC_Pos 1 /* ICACHE ICFBCTRL: SEC Positions */ +#define ICACHE_ICFBCTRL_SEC_Msk (0x1UL << ICACHE_ICFBCTRL_SEC_Pos) /* ICACHE ICFBCTRL: SEC Mask */ + +#define ICACHE_ICFBCTRL_SF_Pos 0 /* ICACHE ICFBCTRL: SF Positions */ +#define ICACHE_ICFBCTRL_SF_Msk (0x1UL /*<< ICACHE_ICFBCTRL_SF_Pos*/) /* ICACHE ICFBCTRL: SF Mask */ + +/* ICACHE ICSH Register Definitions */ +#define ICACHE_ICSH_CSH_Pos 0 /* ICACHE ICSH: CSH Positions */ +#define ICACHE_ICSH_CSH_Msk (0xFFFFFFFFUL /*<< ICACHE_ICSH_CSH_Pos*/) /* ICACHE ICSH: CSH Mask */ + +/* ICACHE ICSM Register Definitions */ +#define ICACHE_ICSM_CSM_Pos 0 /* ICACHE ICSM: CSM Positions */ +#define ICACHE_ICSM_CSM_Msk (0xFFFFFFFFUL /*<< ICACHE_ICSM_CSM_Pos*/) /* ICACHE ICSM: CSM Mask */ + +/* ICACHE CSUC Register Definitions */ +#define ICACHE_CSUC_CSUC_Pos 0 /* ICACHE CSUC: CSUC Positions */ +#define ICACHE_CSUC_CSUC_Msk (0xFFFFFFFFUL /*<< ICACHE_CSUC_CSUC_Pos*/) /* ICACHE CSUC: CSUC Mask */ + +/* ICACHE PIDR4 Register Definitions */ +#define ICACHE_PIDR4_SIZE_Pos 4 /* ICACHE PIDR4: SIZE Positions */ +#define ICACHE_PIDR4_SIZE_Msk (0xFUL << ICACHE_PIDR4_SIZE_Pos) /* ICACHE PIDR4: SIZE Mask */ + +#define ICACHE_PIDR4_DES_2_Pos 0 /* ICACHE PIDR4: DES_2 Positions */ +#define ICACHE_PIDR4_DES_2_Msk (0xFUL /*<< ICACHE_PIDR4_DES_2_Pos*/) /* ICACHE PIDR4: DES_2 Mask */ + +/* ICACHE PIDR0 Register Definitions */ +#define ICACHE_PIDR0_PART_0_Pos 0 /* ICACHE PIDR0: PART_0 Positions */ +#define ICACHE_PIDR0_PART_0_Msk (0xFFUL /*<< ICACHE_PIDR0_PART_0_Pos*/) /* ICACHE PIDR0: PART_0 Mask */ + +/* ICACHE PIDR1 Register Definitions */ +#define ICACHE_PIDR1_DES_0_Pos 4 /* ICACHE PIDR1: DES_0 Positions */ +#define ICACHE_PIDR1_DES_0_Msk (0xFUL << ICACHE_PIDR1_DES_0_Pos) /* ICACHE PIDR1: DES_0 Mask */ + +#define ICACHE_PIDR1_PART_1_Pos 0 /* ICACHE PIDR1: PART_1 Positions */ +#define ICACHE_PIDR1_PART_1_Msk (0xFUL /*<< ICACHE_PIDR1_PART_1_Pos*/) /* ICACHE PIDR1: PART_1 Mask */ + +/* ICACHE PIDR2 Register Definitions */ +#define ICACHE_PIDR2_REVISION_Pos 4 /* ICACHE PIDR2: REVISION Positions */ +#define ICACHE_PIDR2_REVISION_Msk (0xFUL << ICACHE_PIDR2_REVISION_Pos) /* ICACHE PIDR2: REVISION Mask */ + +#define ICACHE_PIDR2_JEDEC_Pos 3 /* ICACHE PIDR2: JEDEC Positions */ +#define ICACHE_PIDR2_JEDEC_Msk (0x1UL << ICACHE_PIDR2_JEDEC_Pos) /* ICACHE PIDR2: JEDEC Mask */ + +#define ICACHE_PIDR2_DES_1_Pos 0 /* ICACHE PIDR2: DES_1 Positions */ +#define ICACHE_PIDR2_DES_1_Msk (0x7UL /*<< ICACHE_PIDR2_DES_1_Pos*/) /* ICACHE PIDR2: DES_1 Mask */ + +/* ICACHE PIDR3 Register Definitions */ +#define ICACHE_PIDR3_REVAND_Pos 4 /* ICACHE PIDR3: REVAND Positions */ +#define ICACHE_PIDR3_REVAND_Msk (0xFUL << ICACHE_PIDR3_REVAND_Pos) /* ICACHE PIDR3: REVAND Mask */ + +#define ICACHE_PIDR3_CMOD_Pos 0 /* ICACHE PIDR3: CMOD Positions */ +#define ICACHE_PIDR3_CMOD_Msk (0xFUL /*<< ICACHE_PIDR3_CMOD_Pos*/) /* ICACHE PIDR3: CMOD Mask */ + +/* ICACHE CIDR0 Register Definitions */ +#define ICACHE_CIDR0_PRMBL_0_Pos 0 /* ICACHE CIDR0: PRMBL_0 Positions */ +#define ICACHE_CIDR0_PRMBL_0_Msk (0xFFUL /*<< ICACHE_CIDR0_PRMBL_0_Pos*/) /* ICACHE CIDR0: PRMBL_0 Mask */ + +/* ICACHE CIDR1 Register Definitions */ +#define ICACHE_CIDR1_CLASS_Pos 4 /* ICACHE CIDR1: CLASS Positions */ +#define ICACHE_CIDR1_CLASS_Msk (0xFUL << ICACHE_CIDR1_CLASS_Pos) /* ICACHE CIDR1: CLASS Mask */ + +#define ICACHE_CIDR1_PRMBL_1_Pos 0 /* ICACHE CIDR1: PRMBL_1 Positions */ +#define ICACHE_CIDR1_PRMBL_1_Msk (0xFUL /*<< ICACHE_CIDR1_PRMBL_1_Pos*/) /* ICACHE CIDR1: PRMBL_1 Mask */ + +/* ICACHE CIDR2 Register Definitions */ +#define ICACHE_CIDR2_PRMBL_2_Pos 0 /* ICACHE CIDR2: PRMBL_2 Positions */ +#define ICACHE_CIDR2_PRMBL_2_Msk (0xFFUL /*<< ICACHE_CIDR2_PRMBL_2_Pos*/) /* ICACHE CIDR2: PRMBL_2 Mask */ + +/* ICACHE CIDR3 Register Definitions */ +#define ICACHE_CIDR3_PRMBL_3_Pos 0 /* ICACHE CIDR3: PRMBL_3 Positions */ +#define ICACHE_CIDR3_PRMBL_3_Msk (0xFFUL /*<< ICACHE_CIDR3_PRMBL_3_Pos*/) /* ICACHE CIDR3: PRMBL_3 Mask */ + +#ifdef __cplusplus +} +#endif + +#endif /* ARMv8MBL_H */ diff --git a/ATM33xx-5/include/arm/system_ARMv8MBL.h b/ATM33xx-5/include/arm/system_ARMv8MBL.h new file mode 100644 index 0000000..3c739cd --- /dev/null +++ b/ATM33xx-5/include/arm/system_ARMv8MBL.h @@ -0,0 +1,64 @@ +/**************************************************************************//** + * @file system_ARMv8MBL.h + * @brief CMSIS Device System Header File for + * ARMv8MBL Device + * @version V5.3.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2024 Atmosic Technologies. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SYSTEM_ARMv8MBL_H +#define SYSTEM_ARMv8MBL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); + +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; + + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_ARMv8MBL_H */ diff --git a/ATM33xx-5/include/armgcc/compiler.h b/ATM33xx-5/include/armgcc/compiler.h new file mode 100644 index 0000000..ec55023 --- /dev/null +++ b/ATM33xx-5/include/armgcc/compiler.h @@ -0,0 +1,150 @@ +/** + ******************************************************************************* + * + * @file armgcc/compiler.h + * + * @brief Definitions of compiler specific directives. + * + * Copyright (C) RivieraWaves 2009-2015 + * Copyright (C) Atmosic 2021 + * + ******************************************************************************* + */ + +#pragma once + +/** + * @defgroup COMPILER Compiler + * @ingroup ATMx3 + * @brief GNU gcc compiler interface + * @{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __GNUC__ +#error "File only included with ARM GCC" +#endif // __GNUC__ + +/// define the static keyword for this compiler +#define __STATIC static + +#ifdef CONFIG_SOC_FAMILY_ATM +#undef __INLINE +#endif +/// define the force inlining attribute for this compiler +#define __INLINE __attribute__((__always_inline__)) static inline + +/// define the IRQ handler attribute for this compiler +#define __IRQ __attribute__((__interrupt__("IRQ"))) + +/// define the BLE IRQ handler attribute for this compiler +#define __BTIRQ + +/// define the BLE IRQ handler attribute for this compiler +#define __BLEIRQ + +/// define the FIQ handler attribute for this compiler +#define __FIQ __attribute__((__interrupt__("FIQ"))) + +/// define size of an empty array (used to declare structure with an array size not defined) +#define __ARRAY_EMPTY + +/// Function returns struct in registers (4 in rvds, var with gnuarm). +/// With Gnuarm, feature depends on command line options and +/// impacts ALL functions returning 2-words max structs +/// (check -freg-struct-return and -mabi=xxx) +#define __VIR + +/// function has no side effect and return depends only on arguments +#define __PURE __attribute__((const)) +#define __PUREISH __attribute__((pure)) + +/// Function never returns +#define __NORETURN __attribute__((noreturn)) + +/// Align instantiated lvalue or struct member on 4 bytes +#define __ALIGN4 __attribute__((aligned(4))) + +/// __MODULE__ comes from the RVDS compiler that supports it +#ifndef __MODULE__ +#define __MODULE__ __BASE_FILE__ +#endif + +#ifndef __PACKED +/// Pack a structure field +#define __PACKED __attribute__ ((__packed__)) +#endif + +/// Put a variable in a memory maintained during deep sleep +#define __LOWPOWER_SAVED + +#ifndef STRINGIFY +#define STRINGIFY(x) #x +#endif +#define TOSTRING(x) STRINGIFY(x) +#define AT __MODULE__ ":" TOSTRING(__LINE__) + +/// Do not initialize variable at startup +/// Create unique section header @file+line +#ifdef __ARMCC_VERSION +#define __UNINIT __attribute__((section(".bss.uninit." AT))) +#else +#define __UNINIT __attribute__((section(".uninit." AT))) +#endif + +/// Locate code in high performance memory +#define __FAST + +/// Not ROM, so keep private +#define __NR_STATIC static + +/// Compile-time assertion +#define STATIC_ASSERT _Static_assert + +/// Unused variable +#define __UNUSED __attribute__((unused)) + +/// Convert context pointer from const to non-const +#define CONTEXT_VOID_P(__p) ({ \ + __typeof__(__p) __tmp = (__p); \ + __builtin_choose_expr( \ + __builtin_types_compatible_p(__typeof__(__tmp), void const *), \ + (void *)(uintptr_t)__tmp, __tmp); \ +}) + +/// Printf-like function +#define __PRINTF(...) __attribute__((format(printf, ##__VA_ARGS__))) + +/// Arguments not permitting NULL value +#define __NONNULL_ALL __attribute__((nonnull)) +#define __NONNULL(...) __attribute__((nonnull(__VA_ARGS__))) + +/// Field position in compound object +#define __OFFSET(__s, __f) offsetof(__typeof__(__s), __f) + +/// Constructor priority +#define __CONSTRUCTOR_PRIO(__p) __attribute__((constructor(__p))) + +/// Convert structured struct with different type name +#define TYPE_CONVERT(src_type, var, dst_type) ({ \ + STATIC_ASSERT(__builtin_types_compatible_p(src_type, __typeof__(var)) && \ + (sizeof(src_type) == sizeof(dst_type)), "incompatable"); \ + *(dst_type const *)&var;}) + +/// Variables that may not be aligned +#ifdef __ARMCC_VERSION +#define __UNALIGNED __unaligned +#else +#define __UNALIGNED +#endif + +#ifdef __cplusplus +} +#endif + +/// @} COMPILER diff --git a/ATM33xx-5/include/at_tz_ppc.h b/ATM33xx-5/include/at_tz_ppc.h new file mode 100644 index 0000000..a487c62 --- /dev/null +++ b/ATM33xx-5/include/at_tz_ppc.h @@ -0,0 +1,446 @@ +/** + ******************************************************************************* + * + * @file at_tz_ppc.h + * + * @brief Peripheral protection controller driver + * + * Copyright (C) Atmosic 2022 + * + ******************************************************************************* + */ + +#pragma once + +#include "arch.h" + +/** + * @defgroup AT_TZ_PPC PPC + * @ingroup DRIVERS + * @brief Trustzone PPC driver + * + * This module contains the necessary functions to manage peripheral + * protection controllers + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/// PERIPHERAL(peripheral, name prefix, bus, peripheral controller) +#define CMSDK_PPC_PERIPHERALS \ + PERIPHERAL(DMA, AT_, AHB, PPCEXP1) \ + PERIPHERAL(SHA2,, AHB, PPCEXP1) \ + PERIPHERAL(QSPI,, APB, PPCEXP0) \ + PERIPHERAL(SLWTIMER,, APB, PPCEXP0) \ + PERIPHERAL(SPI1,, APB, PPCEXP0) \ + PERIPHERAL(QDEC,, APB, PPCEXP0) \ + PERIPHERAL(SPI2,, APB, PPCEXP0) \ + PERIPHERAL(KSM,, APB, PPCEXP0) \ + PERIPHERAL(SPI0,, APB, PPCEXP0) \ + PERIPHERAL(PWM,, APB, PPCEXP0) \ + PERIPHERAL(UART1, AT_, APB, PPCEXP0) \ + PERIPHERAL(UART0, AT_, APB, PPCEXP0) \ + PERIPHERAL(SHUB,, APB, PPCEXP1) \ + PERIPHERAL(RCOS_CAL,, APB, PPCEXP1) \ + PERIPHERAL(SWD,, APB, PPCEXP1) \ + PERIPHERAL(TRNG,, APB, PPCEXP1) \ + PERIPHERAL(GADC,, APB, PPCEXP1) \ + PERIPHERAL(PSEQ,, APB, PPCEXP1) \ + PERIPHERAL(PMU,, APB, PPCEXP1) \ + PERIPHERAL(MDM,, APB, PPCEXP1) \ + PERIPHERAL(RADIO,, APB, PPCEXP1) \ + PERIPHERAL(RIF,, APB, PPCEXP1) \ + PERIPHERAL(NVM,, APB, PPCEXP1) \ + PERIPHERAL(I2C0,, APB, PPCEXP1) \ + PERIPHERAL(AES,, APB, PPCEXP2) \ + PERIPHERAL(CLKRSTGEN,, APB, PPCEXP2) \ + +/// These are peripherals that follow an alternative address naming conv. +/// ALT_PERIPHERAL(peripheral, address, bus, controller) +#define ALT_PPC_PERIPHERALS \ + ALT_PERIPHERAL(GPIO0, CMSDK_GPIO0, AHB, PPCEXP1) \ + ALT_PERIPHERAL(GPIO1, CMSDK_GPIO1, AHB, PPCEXP1) \ + ALT_PERIPHERAL(BLE52, ((void *)BLE_NONSECURE_BASE), AHB, PPCEXP1) \ + ALT_PERIPHERAL(BLE52, ((void *)BLE_SECURE_BASE), AHB, PPCEXP1) \ + ALT_PERIPHERAL(WRPR, CMSDK_WRPR0_SECURE, APB, PPCEXP0) \ + ALT_PERIPHERAL(WRPR, CMSDK_WRPR0_NONSECURE, APB, PPCEXP0) \ + ALT_PERIPHERAL(WRPR, CMSDK_WRPR1_SECURE, APB, PPCEXP1) \ + ALT_PERIPHERAL(WRPR, CMSDK_WRPR1_NONSECURE, APB, PPCEXP1) \ + ALT_PERIPHERAL(WRPR, CMSDK_WRPR2_SECURE, APB, PPCEXP2) \ + ALT_PERIPHERAL(WRPR, CMSDK_WRPR2_NONSECURE, APB, PPCEXP2) \ + +/// DUAL_PERIPHERAL(peripheral, ext, bus1, controller1, bus2, controller2) +#define DUAL_PPC_PERIPHERALS \ + DUAL_PERIPHERAL(I2S,, AHB, PPCEXP1, APB, PPCEXP2) \ + DUAL_PERIPHERAL(PDM0,, AHB, PPCEXP1, APB, PPCEXP2) \ + DUAL_PERIPHERAL(PDM1,, AHB, PPCEXP1, APB, PPCEXP2) \ + +/// SSE200 base peripherals follow separate PPC mask naming conv. +/// BASE_PERIPHERAL(peripheral, address, bus, controller) +#define BASE_PPC_PERIPHERALS \ + BASE_PERIPHERAL(MHU1, MHU_1, APB, PPC0) \ + BASE_PERIPHERAL(MHU0, MHU_0, APB, PPC0) \ + BASE_PERIPHERAL(DTIMER, CMSDK_DUALTIMER, APB, PPC0) \ + BASE_PERIPHERAL(TIMER1, CMSDK_TIMER1, APB, PPC0) \ + BASE_PERIPHERAL(TIMER0, CMSDK_TIMER0, APB, PPC0) \ + BASE_PERIPHERAL(S32K_Timer, S32_TIMER, APB, PPC1) \ + + +/// Set bit at ppc bank +#define PPC_BANK_MODIFY_BIT(bank, pos, value) do { \ + bank = ((bank) & ~(1UL << (pos))) | (((value) << (pos))); \ +} while (0) + +/* Privilege attribute used to configure the peripheral */ +typedef enum { + /// Allows both privileged access only + ATM_PPC_PRIV_ONLY, + /// Allows both privileged and unprivileged access + ATM_PPC_PRIV_UNPRIV, +} atm_ppc_priv_attr_t; + +#ifdef SECURE_MODE + +/* Secure attribute used to configure the peripheral */ +typedef enum { + ATM_PPC_SECURE, + ATM_PPC_NONSECURE, +} atm_ppc_sec_attr_t; + +/** + * @brief Set peripheral to secure or non-secure state + * + * @param[in] peripheral pointer to peripheral + * @param[in] secure sets peripheral to secure or non-secure + */ +__NONNULL(1) +__STATIC_INLINE void at_tz_ppc_configure(void const *peripheral, + atm_ppc_sec_attr_t secure) +{ +#define PERIPHERAL(PERI, EXT, BUS, BANK) \ + case ((uintptr_t) CMSDK_##EXT##PERI##_NONSECURE): \ + case ((uintptr_t) CMSDK_##EXT##PERI##_SECURE): \ + PPC_BANK_MODIFY_BIT(SEC_CTRL_REG->BUS##NS##BANK, \ + SEC_PRIV_CTRL_##BUS##NS##BANK##_##PERI##_Pos, secure);\ + break; +// Alt peripherals follow a diff address naming vs reg peripherals +#define ALT_PERIPHERAL(PERI, ADDR, BUS, BANK) \ + case ((uintptr_t) ADDR): \ + PPC_BANK_MODIFY_BIT(SEC_CTRL_REG->BUS##NS##BANK, \ + SEC_PRIV_CTRL_##BUS##NS##BANK##_##PERI##_Pos, secure); \ + break; +// Dual periphals are peripherals that require setting two controllers. +// register file on APB and fifo on AHB +#define DUAL_PERIPHERAL(PERI, EXT, BUS1, BANK1, BUS2, BANK2) \ + case ((uintptr_t) CMSDK_##EXT##PERI##_NONSECURE): \ + case ((uintptr_t) CMSDK_##EXT##PERI##_SECURE): \ + PPC_BANK_MODIFY_BIT(SEC_CTRL_REG->BUS1##NS##BANK1, \ + SEC_PRIV_CTRL_##BUS1##NS##BANK1##_##PERI##_Pos, secure); \ + PPC_BANK_MODIFY_BIT(SEC_CTRL_REG->BUS2##NS##BANK2, \ + SEC_PRIV_CTRL_##BUS2##NS##BANK2##_##PERI##_Pos, secure); \ + break; +// Base peripherals follow a diff address naming vs reg peripherals +#define BASE_PERIPHERAL(PERI, ADDR, BUS, BANK) \ + case ((uintptr_t) ADDR): \ + PPC_BANK_MODIFY_BIT(SEC_CTRL_REG->BUS##NS##BANK, \ + SEC_PRIV_CTRL_##BUS##NS##BANK##_NS_##PERI##_Pos, secure); \ + break; + + uintptr_t peri = (uintptr_t) peripheral; + switch(peri) { + // handle common cmsdk peripherals + CMSDK_PPC_PERIPHERALS + // handle peripherals with non-standard naming + ALT_PPC_PERIPHERALS + // handle dual ppc peripherals + DUAL_PPC_PERIPHERALS + // handle base peripherals + BASE_PPC_PERIPHERALS + default: ASSERT_INFO(0, peripheral, secure); + } +#undef PERIPHERAL +#undef ALT_PERIPHERAL +#undef DUAL_PERIPHERAL +#undef BASE_PERIPHERAL +} + +/** + * @brief Set peripheral privilege in secure state + * + * @param[in] peripheral pointer to peripheral + * @param[in] priv sets peripheral to priv or unpriv in secure space + */ +__NONNULL(1) +__STATIC_INLINE void at_tz_ppc_configure_sec_priv(void const *peripheral, + atm_ppc_priv_attr_t priv) +{ +#define PERIPHERAL(PERI, EXT, BUS, BANK) \ + case ((uintptr_t) CMSDK_##EXT##PERI##_SECURE): \ + case ((uintptr_t) CMSDK_##EXT##PERI##_NONSECURE): \ + PPC_BANK_MODIFY_BIT(SEC_CTRL_REG->BUS##SP##BANK, \ + SEC_PRIV_CTRL_##BUS##SP##BANK##_##PERI##_Pos, priv);\ + break; +// Alt peripherals follow a diff address naming vs reg peripherals +#define ALT_PERIPHERAL(PERI, ADDR, BUS, BANK) \ + case ((uintptr_t) ADDR): \ + PPC_BANK_MODIFY_BIT(SEC_CTRL_REG->BUS##SP##BANK, \ + SEC_PRIV_CTRL_##BUS##SP##BANK##_##PERI##_Pos, priv); \ + break; +// Dual periphals are peripherals that require setting two controllers. +// register file on APB and fifo on AHB +#define DUAL_PERIPHERAL(PERI, EXT, BUS1, BANK1, BUS2, BANK2) \ + case ((uintptr_t) CMSDK_##EXT##PERI##_SECURE): \ + case ((uintptr_t) CMSDK_##EXT##PERI##_NONSECURE): \ + PPC_BANK_MODIFY_BIT(SEC_CTRL_REG->BUS1##SP##BANK1, \ + SEC_PRIV_CTRL_##BUS1##SP##BANK1##_##PERI##_Pos, priv); \ + PPC_BANK_MODIFY_BIT(SEC_CTRL_REG->BUS2##SP##BANK2, \ + SEC_PRIV_CTRL_##BUS2##SP##BANK2##_##PERI##_Pos, priv); \ + break; +// Base peripherals follow a diff address naming vs reg peripherals +#define BASE_PERIPHERAL(PERI, ADDR, BUS, BANK) \ + case ((uintptr_t) ADDR): \ + PPC_BANK_MODIFY_BIT(SEC_CTRL_REG->BUS##SP##BANK, \ + SEC_PRIV_CTRL_##BUS##SP##BANK##_SP_##PERI##_Pos, priv); \ + break; + + uintptr_t peri = (uintptr_t) peripheral; + switch(peri) { + // handle common cmsdk peripherals + CMSDK_PPC_PERIPHERALS + // handle peripherals with non-standard naming + ALT_PPC_PERIPHERALS + // handle dual ppc peripherals + DUAL_PPC_PERIPHERALS + // handle base peripherals + BASE_PPC_PERIPHERALS + default: ASSERT_INFO(0, peripheral, priv); + } +#undef PERIPHERAL +#undef ALT_PERIPHERAL +#undef DUAL_PERIPHERAL +#undef BASE_PERIPHERAL +} + +/** + * @brief Configure all peripherals to non-secure for basic operation + */ +__STATIC_INLINE void at_tz_ppc_init_ns_cfg(void) +{ + SEC_CTRL_REG->AHBNSPPCEXP1 = SEC_PRIV_CTRL_AHBNSPPCEXP1_BLE52_Msk | + SEC_PRIV_CTRL_AHBNSPPCEXP1_I2S_Msk | + SEC_PRIV_CTRL_AHBNSPPCEXP1_PDM1_Msk | + SEC_PRIV_CTRL_AHBNSPPCEXP1_PDM0_Msk | + SEC_PRIV_CTRL_AHBNSPPCEXP1_DMA_Msk | + SEC_PRIV_CTRL_AHBNSPPCEXP1_SHA2_Msk | + SEC_PRIV_CTRL_AHBNSPPCEXP1_GPIO1_Msk | + SEC_PRIV_CTRL_AHBNSPPCEXP1_GPIO0_Msk; + + SEC_CTRL_REG->APBNSPPC0 = SEC_PRIV_CTRL_APBNSPPC0_NS_DTIMER_Msk | + SEC_PRIV_CTRL_APBNSPPC0_NS_TIMER1_Msk | + SEC_PRIV_CTRL_APBNSPPC0_NS_TIMER0_Msk | + SEC_PRIV_CTRL_APBNSPPC0_NS_MHU0_Msk | + SEC_PRIV_CTRL_APBNSPPC0_NS_MHU1_Msk; + + // Leave S32Ktimer as a secure peripheral. PPC1 incorrectly + // disables secure access to the SYS_CTRL_REG registers which are always + // secure. + // SEC_CTRL_REG->APBNSPPC1 = SEC_PRIV_CTRL_APBNSPPC1_NS_S32K_Timer_Msk; + + SEC_CTRL_REG->APBNSPPCEXP0 = SEC_PRIV_CTRL_APBNSPPCEXP0_QSPI_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP0_SLWTIMER_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP0_SPI1_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP0_QDEC_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP0_SPI2_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP0_KSM_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP0_SPI0_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP0_PWM_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP0_UART1_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP0_UART0_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP0_WRPR_Msk; + + SEC_CTRL_REG->APBNSPPCEXP1 = SEC_PRIV_CTRL_APBNSPPCEXP1_ATLC_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP1_SHUB_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP1_RCOS_CAL_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP1_TRNG_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP1_GADC_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP1_PSEQ_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP1_PMU_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP1_MDM_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP1_RADIO_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP1_RIF_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP1_WRPR_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP1_NVM_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP1_I2C1_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP1_SWD_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP1_I2C0_Msk; + + SEC_CTRL_REG->APBNSPPCEXP2 = SEC_PRIV_CTRL_APBNSPPCEXP2_AES_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP2_CLKRSTGEN_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP2_I2S_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP2_WRPR_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP2_PDM1_Msk | + SEC_PRIV_CTRL_APBNSPPCEXP2_PDM0_Msk; + + // Set all peripherals to unprivileged mode. + SEC_CTRL_REG->AHBSPPPCEXP1 = SEC_PRIV_CTRL_AHBSPPPCEXP1_BLE52_Msk | + SEC_PRIV_CTRL_AHBSPPPCEXP1_I2S_Msk | + SEC_PRIV_CTRL_AHBSPPPCEXP1_PDM1_Msk | + SEC_PRIV_CTRL_AHBSPPPCEXP1_PDM0_Msk | + SEC_PRIV_CTRL_AHBSPPPCEXP1_DMA_Msk | + SEC_PRIV_CTRL_AHBSPPPCEXP1_SHA2_Msk | + SEC_PRIV_CTRL_AHBSPPPCEXP1_GPIO1_Msk | + SEC_PRIV_CTRL_AHBSPPPCEXP1_GPIO0_Msk; + SEC_CTRL_REG->APBSPPPC0 = SEC_PRIV_CTRL_APBSPPPC0_SP_DTIMER_Msk | + SEC_PRIV_CTRL_APBSPPPC0_SP_TIMER1_Msk | + SEC_PRIV_CTRL_APBSPPPC0_SP_TIMER0_Msk | + SEC_PRIV_CTRL_APBSPPPC0_SP_MHU0_Msk | + SEC_PRIV_CTRL_APBSPPPC0_SP_MHU1_Msk; + SEC_CTRL_REG->APBSPPPC1 = SEC_PRIV_CTRL_APBSPPPC1_SP_S32K_Timer_Msk; + SEC_CTRL_REG->APBSPPPCEXP0 = SEC_PRIV_CTRL_APBSPPPCEXP0_QSPI_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP0_SLWTIMER_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP0_SPI1_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP0_QDEC_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP0_SPI2_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP0_KSM_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP0_SPI0_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP0_PWM_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP0_UART1_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP0_UART0_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP0_WRPR_Msk; + SEC_CTRL_REG->APBSPPPCEXP1 = SEC_PRIV_CTRL_APBSPPPCEXP1_ATLC_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP1_SHUB_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP1_RCOS_CAL_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP1_TRNG_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP1_GADC_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP1_PSEQ_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP1_PMU_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP1_MDM_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP1_RADIO_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP1_RIF_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP1_WRPR_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP1_NVM_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP1_I2C1_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP1_SWD_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP1_I2C0_Msk; + SEC_CTRL_REG->APBSPPPCEXP2 = SEC_PRIV_CTRL_APBSPPPCEXP2_AES_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP2_CLKRSTGEN_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP2_I2S_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP2_WRPR_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP2_PDM1_Msk | + SEC_PRIV_CTRL_APBSPPPCEXP2_PDM0_Msk; + + NONSEC_CTRL_REG->AHBNSPPPCEXP1 = NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_BLE52_Msk | + NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_I2S_Msk | + NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_PDM1_Msk | + NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_PDM0_Msk | + NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_DMA_Msk | + NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_SHA2_Msk | + NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_GPIO1_Msk | + NONSEC_PRIV_CTRL_AHBNSPPPCEXP1_GPIO0_Msk; + NONSEC_CTRL_REG->APBNSPPPC0 = NONSEC_PRIV_CTRL_APBNSPPPC0_NSP_DTIMER_Msk | + NONSEC_PRIV_CTRL_APBNSPPPC0_NSP_TIMER1_Msk | + NONSEC_PRIV_CTRL_APBNSPPPC0_NSP_TIMER0_Msk | + NONSEC_PRIV_CTRL_APBNSPPPC0_NSP_MHU0_Msk | + NONSEC_PRIV_CTRL_APBNSPPPC0_NSP_MHU1_Msk; + NONSEC_CTRL_REG->APBNSPPPC1 = + NONSEC_PRIV_CTRL_APBNSPPPC1_NSP_S32K_Timer_Msk; + NONSEC_CTRL_REG->APBNSPPPCEXP0 = NONSEC_PRIV_CTRL_APBNSPPPCEXP0_QSPI_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP0_SLWTIMER_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP0_SPI1_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP0_QDEC_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP0_SPI2_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP0_KSM_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP0_SPI0_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP0_PWM_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP0_UART1_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP0_UART0_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP0_WRPR_Msk; + NONSEC_CTRL_REG->APBNSPPPCEXP1 = NONSEC_PRIV_CTRL_APBNSPPPCEXP1_ATLC_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP1_SHUB_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP1_RCOS_CAL_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP1_TRNG_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP1_GADC_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP1_PSEQ_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP1_PMU_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP1_MDM_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP1_RADIO_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP1_RIF_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP1_WRPR_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP1_NVM_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP1_I2C1_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP1_SWD_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP1_I2C0_Msk; + NONSEC_CTRL_REG->APBNSPPPCEXP2 = NONSEC_PRIV_CTRL_APBNSPPPCEXP2_AES_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP2_CLKRSTGEN_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP2_I2S_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP2_WRPR_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP2_PDM1_Msk | + NONSEC_PRIV_CTRL_APBNSPPPCEXP2_PDM0_Msk; +} + +#endif //SECURE_MODE + +/** + * @brief Set peripheral privilege in non-secure state + * + * @param[in] peripheral pointer to peripheral + * @param[in] priv sets peripheral to priv or unpriv in non-secure space + */ +__NONNULL(1) +__STATIC_INLINE void at_tz_ppc_configure_nonsec_priv(void const *peripheral, + atm_ppc_priv_attr_t priv) +{ +#define PERIPHERAL(PERI, EXT, BUS, BANK) \ + case ((uintptr_t) CMSDK_##EXT##PERI##_NONSECURE): \ + PPC_BANK_MODIFY_BIT(NONSEC_CTRL_REG->BUS##NSP##BANK, \ + NONSEC_PRIV_CTRL_##BUS##NSP##BANK##_##PERI##_Pos, priv);\ + break; +// Alt peripherals follow a diff address naming vs reg peripherals +#define ALT_PERIPHERAL(PERI, ADDR, BUS, BANK) \ + case ((uintptr_t) ADDR): \ + PPC_BANK_MODIFY_BIT(NONSEC_CTRL_REG->BUS##NSP##BANK, \ + NONSEC_PRIV_CTRL_##BUS##NSP##BANK##_##PERI##_Pos, priv); \ + break; +// Dual periphals are peripherals that require setting two controllers. +// register file on APB and fifo on AHB +#define DUAL_PERIPHERAL(PERI, EXT, BUS1, BANK1, BUS2, BANK2) \ + case ((uintptr_t)CMSDK_##EXT##PERI##_NONSECURE): \ + PPC_BANK_MODIFY_BIT(NONSEC_CTRL_REG->BUS1##NSP##BANK1, \ + NONSEC_PRIV_CTRL_##BUS1##NSP##BANK1##_##PERI##_Pos, priv); \ + PPC_BANK_MODIFY_BIT(NONSEC_CTRL_REG->BUS2##NSP##BANK2, \ + NONSEC_PRIV_CTRL_##BUS2##NSP##BANK2##_##PERI##_Pos, priv); \ + break; +// Base peripherals follow a diff address naming vs reg peripherals +#define BASE_PERIPHERAL(PERI, ADDR, BUS, BANK) \ + case ((uintptr_t) ADDR): \ + PPC_BANK_MODIFY_BIT(NONSEC_CTRL_REG->BUS##NSP##BANK, \ + NONSEC_PRIV_CTRL_##BUS##NSP##BANK##_NSP_##PERI##_Pos, priv); \ + break; + + uintptr_t peri = (uintptr_t) peripheral; + switch(peri) { + // handle common cmsdk peripherals + CMSDK_PPC_PERIPHERALS + // handle peripherals with non-standard naming + ALT_PPC_PERIPHERALS + // handle dual ppc peripherals + DUAL_PPC_PERIPHERALS + // handle base peripherals + BASE_PPC_PERIPHERALS + default: ASSERT_INFO(0, peripheral, priv); + } +#undef PERIPHERAL +#undef ALT_PERIPHERAL +#undef DUAL_PERIPHERAL +#undef BASE_PERIPHERAL +} + + +#ifdef __cplusplus +} +#endif + +/// @} diff --git a/ATM33xx-5/include/at_tz_sau.h b/ATM33xx-5/include/at_tz_sau.h new file mode 100644 index 0000000..461f43f --- /dev/null +++ b/ATM33xx-5/include/at_tz_sau.h @@ -0,0 +1,194 @@ +/** + ******************************************************************************* + * + * @file at_tz_sau.h + * + * @brief Security Attribution Unit driver + * + * Copyright (C) Atmosic 2022 + * + ******************************************************************************* + */ + +#pragma once + +#include "arch.h" +#include "inttypes.h" + +/** + * @defgroup AT_TZ_SAU SAU + * @ingroup DRIVERS + * @brief Trustzone SAU driver + * + * This module contains the necessary functions to manage the SAU + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef SECURE_MODE +#error "at_tz_sau is a secure-only driver." +#endif + +/// Return values for sau APIs +typedef enum { + /// Successful operation + AT_TZ_SAU_OK, + /// passed region is invalid, make sure region is less than + /// at_tz_sau_num_regions() + AT_TZ_SAU_INVALID_REGION, + /// bad attribute. see at_tz_sau_attr_t + AT_TZ_SAU_INVALID_ATTR, + /// invalid base/limit address + AT_TZ_SAU_INVALID_ADDRESS, +} at_tz_sau_ret_t; + +/// Attributes for SAU regions +typedef enum { + /// set region to NS space + AT_TZ_SAU_NS, + /// set region to NS-callable space + AT_TZ_SAU_NSC, + AT_TZ_SAU_MAX, +} at_tz_sau_attr_t; + +/// SAU Base address entries must be aligned to SAU_RBAR_BADDR_Msk +#define AT_TZ_SAU_BADDR_MASK(addr) ((addr) & SAU_RBAR_BADDR_Msk) +/// SAU Limit address entries must be aligned to SAU_RBAR_BADDR_Msk +#define AT_TZ_SAU_LADDR_MASK(addr) ((addr) & SAU_RLAR_LADDR_Msk) + +/// Invalid number of regions. +#define AT_TZ_SAU_INVALID_REGION_COUNT 0xff + +/** + * @brief Gets number of regions in SAU + * @return number of regions present in SAU + */ +__STATIC_INLINE uint8_t at_tz_sau_num_regions(void) +{ + // valid region numbers are 0, 4, or 8 + static uint8_t num_regions = AT_TZ_SAU_INVALID_REGION_COUNT; + if (num_regions != AT_TZ_SAU_INVALID_REGION_COUNT) { + return num_regions; + } + num_regions = SAU->TYPE & SAU_TYPE_SREGION_Msk; + return num_regions; +} + + +/** + * @brief Returns unused region in the SAU + * + * @return region number, or AT_TZ_SAU_INVALID_REGION_COUNT on failure + */ +__STATIC_INLINE uint8_t at_tz_sau_get_unused_region(void) +{ + for (uint8_t i = 0; i < at_tz_sau_num_regions(); i++) { + SAU->RNR = i; + if (!(SAU->RLAR & SAU_RLAR_ENABLE_Msk)) { + return i; + } + } + return AT_TZ_SAU_INVALID_REGION_COUNT; +} + +/** + * @brief Enable the Security Attribution Unit (SAU) + * @note configures SAU to configure code to be NSCallable + * + * @return AT_TZ_SAU_OK on success + */ +__STATIC_INLINE at_tz_sau_ret_t at_tz_sau_enable(void) +{ + SAU->CTRL |= SAU_CTRL_ENABLE_Msk; + // Configure code to NS callable + SEC_CTRL_REG->NSCCFG = SEC_PRIV_CTRL_NSCCFG_CODENSC_Msk; + return AT_TZ_SAU_OK; +} + +/** + * @brief Disable the SAU + * @note this should be called if only using the IDAU to handle + * security isolation + * + * @return AT_TZ_SAU_OK on success + */ +__STATIC_INLINE at_tz_sau_ret_t at_tz_sau_disable(void) +{ + // clear enable bit and configure to all NS + SAU->CTRL = SAU_CTRL_ALLNS_Msk; + // Configure code and ram to NS callable + SEC_CTRL_REG->NSCCFG = SEC_PRIV_CTRL_NSCCFG_RAMNSC_Msk | + SEC_PRIV_CTRL_NSCCFG_CODENSC_Msk; + return AT_TZ_SAU_OK; +} + +/** + * @brief Configure a single region in the SAU + * + * @note API is not interrupt safe + * @note after all configurations are complete, caller must issue + * synchronization barriers (ISB/DSB) and flush caches + * + * @param[in] region region index of the SAU + * @param[in] base base address of address space to configure + * @param[in] limit limit address of address space to configure + * @param[in] attr attribute to configure region to + * @return AT_TZ_SAU_OK on success + */ +__STATIC_INLINE at_tz_sau_ret_t at_tz_sau_enable_region(uint8_t region, + uint32_t base, uint32_t limit, at_tz_sau_attr_t attr) +{ + if (attr >= AT_TZ_SAU_MAX) { + return AT_TZ_SAU_INVALID_ATTR; + } + if (region >= at_tz_sau_num_regions()) { + return AT_TZ_SAU_INVALID_REGION; + } + if (base > limit) { + return AT_TZ_SAU_INVALID_ADDRESS; + } + if ((base & ~SAU_RBAR_BADDR_Msk) || (limit & ~SAU_RLAR_LADDR_Msk)) { + // bounds must be 32-byte aligned + return AT_TZ_SAU_INVALID_ADDRESS; + } + uint32_t rlar_enable_mask = SAU_RLAR_ENABLE_Msk; + if (attr == AT_TZ_SAU_NSC) { + rlar_enable_mask |= SAU_RLAR_NSC_Msk; + } + + SAU->RNR = region; + SAU->RBAR = AT_TZ_SAU_BADDR_MASK(base); + SAU->RLAR = AT_TZ_SAU_LADDR_MASK(limit) | rlar_enable_mask; + return AT_TZ_SAU_OK; +} + +/** + * @brief Disable a single region in the SAU + * + * @note API is not interrupt safe + * @note after all configurations are complete, caller must issue + * synchronization barriers (ISB/DSB) and flush caches + * + * @param[in] region region index of the SAU + * @return AT_TZ_SAU_OK on success + */ +__STATIC_INLINE at_tz_sau_ret_t at_tz_sau_disable_region(uint8_t region) +{ + if (region >= at_tz_sau_num_regions()) { + return AT_TZ_SAU_INVALID_REGION; + } + SAU->RNR = region; + SAU->RBAR = 0; + SAU->RLAR = 0; + return AT_TZ_SAU_OK; +} + +#ifdef __cplusplus +} +#endif + +/// @} diff --git a/ATM33xx-5/include/calibration.h b/ATM33xx-5/include/calibration.h new file mode 100644 index 0000000..30fc2a0 --- /dev/null +++ b/ATM33xx-5/include/calibration.h @@ -0,0 +1,181 @@ +/** + ******************************************************************************* + * + * @file calibration.h + * + * @brief Calibration data + * + * Copyright (C) Atmosic 2021-2024 + * + ******************************************************************************* + */ + +#pragma once + +/** + * @defgroup CALIBRATION Calibration + * @ingroup DRIVERS + * @brief Calibration data + * @{ + */ + +#include +#include "compiler.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/// Duration for an RCOS measurement to remain valid in 32KHz cycles +#define LPC_RCOS_VALID (5U * 32768U) // 5 seconds + +/// Platform NVDS tags +/// @note the range should within PARAM_ID_CAL1_MIN and PARAM_ID_CAL1_MAX or +/// within PARAM_ID_CAL2_MIN and PARAM_ID_CAL2_MAX +enum atm_nvds_tag { + /// Identical to PARAM_ID_BD_ADDRESS + ATM_TAG_BD_ADDRESS = 0x01, // Introduced to decouple from BLE header files + + /// Manufacturing calibration for RIF module + ATM_TAG_RIF_CAL = 0xb0, + /// Manufacturing calibration for MDM module + ATM_TAG_MDM_CAL = 0xb1, + /// Manufacturing overrides for LC registers + ATM_TAG_BLE_RADIO_OVR = 0xb2, + ATM_TAG_UNUSED1 = 0xb3, + /// Customer configuration for WURX module + ATM_TAG_PMU_WURX = 0xb4, + ATM_TAG_UNUSED2 = 0xb5, + ATM_TAG_UNUSED3 = 0xb6, + ATM_TAG_UNUSED4 = 0xb7, + ATM_TAG_ATE = 0xb8, + ATM_TAG_CHIP_INFO = 0xb9, + ATM_TAG_UNUSED6 = 0xba, + ATM_TAG_UNUSED7 = 0xbb, + /// Manufacturing calibration for various registers + ATM_TAG_MISC_CAL = 0xbc, + /// Customer design-specific calibration for various registers + ATM_TAG_CUST_CFG = 0xbd, + + /* + * NOTE: Place new entires above this comment + */ + /// Reserved secure-only tags + ATM_SEC_ONLY_TAG_1 = 0xec, + ATM_SEC_ONLY_TAG_2 = 0xed, + ATM_SEC_ONLY_TAG_3 = 0xee, + ATM_SEC_ONLY_TAG_4 = 0xef, + + /// Arbitrary 32,16,8-bit register write + ATM_TAG_PMU_W = 0xfc, + + /// Arbitrary 32,16,8-bit register write + ATM_TAG_MEM_W = 0xfd, + + /// Arbitrary 32,16,8-bit register read-modify-write + ATM_TAG_MEM_RMW = 0xfe, +}; + +/// Manufacturing overrides for LC registers +struct BLE_radio_ovr_s { + uint32_t RADIOCNTL0; + uint32_t RADIOCNTL1; + uint32_t RADIOCNTL2; + uint32_t RADIOCNTL3; + uint32_t RADIOPWRUPDN0; + uint32_t RADIOPWRUPDN1; + uint32_t RADIOPWRUPDN2; + uint32_t RADIOPWRUPDN3; + uint32_t RADIOTXRXTIM0; + uint32_t RADIOTXRXTIM1; + uint32_t RADIOTXRXTIM2; + uint32_t RADIOTXRXTIM3; +}; + +struct chip_info_s { + uint16_t version; + uint8_t package; + uint8_t harvesting; + uint8_t test_day; + uint8_t test_month; + uint8_t test_year; + uint8_t otp_version; +}; +extern struct chip_info_s chip_info; +extern uint16_t chip_info_len; + +#define CHIP_INFO__PACKAGE__INVALID 0 +#define CHIP_INFO__PACKAGE__7x7 1 +#define CHIP_INFO__PACKAGE__5x5 2 +#define CHIP_INFO__PACKAGE__CSP 3 +#define CHIP_INFO__PACKAGE__5x5_STACKED 5 + +#define MISC_CAL__MISC_FLASH_WAIT_XTAL_STABLE__SHIFT 0 +#define MISC_CAL__MISC_FLASH_WAIT_XTAL_STABLE__MASK 0x01U +#define MISC_CAL__MISC_FLASH_WAIT_XTAL_STABLE__READ(src) \ + (((uint8_t)(src) & 0x01U) >> 0) + +#define MISC_CAL__MISC_WURX_BIAS_AMP__SHIFT 1 +#define MISC_CAL__MISC_WURX_BIAS_AMP__MASK 0x0EU +#define MISC_CAL__MISC_WURX_BIAS_AMP__READ(src) \ + (((uint8_t)(src) & 0x0EU) >> 1) + +/// Manufacturing calibration for various registers +struct misc_cal_s { + uint16_t version; + int8_t tx_gain_offset; + uint8_t misc; // See MISC_CAL__MISC above + + uint32_t GADC_GAIN_OFFSET[4]; + uint32_t PSEQ_XTAL_BITS1; + uint32_t PMU_TOP_PMU2A; + uint32_t PMU_TOP_PMU3; + uint32_t PMU_TOP_PMU4; + uint8_t pmu_otp[6]; + uint8_t pad; + uint8_t txmodgain2m_delta; +}; +extern struct misc_cal_s misc_cal; +extern uint16_t misc_cal_len; + +#define CUST_CAL__CUST_IGNORE_32KHZ_XTAL_CHECK__SHIFT 0 +#define CUST_CAL__CUST_IGNORE_32KHZ_XTAL_CHECK__MASK 0x01U +#define CUST_CAL__CUST_IGNORE_32KHZ_XTAL_CHECK__READ(src) \ + (((uint8_t)(src) & 0x01U) >> 0) + +#define CUST_CAL__CUST_NO_32KHZ_XTAL_ON_BOARD__SHIFT 1 +#define CUST_CAL__CUST_NO_32KHZ_XTAL_ON_BOARD__MASK 0x02U +#define CUST_CAL__CUST_NO_32KHZ_XTAL_ON_BOARD__READ(src) \ + (((uint8_t)(src) & 0x02U) >> 0) + +/// Customer design-specific calibration for various registers +struct cust_cfg_s { + uint16_t version; + int8_t external_pa_gain; + uint8_t cust; // See CUST_CAL__CUST above + + uint32_t PSEQ_XTAL_BITS0; + uint32_t PMU_TOP_PMU2; + uint32_t RIF_SYNTX5; +}; +extern struct cust_cfg_s cust_cfg; +extern uint16_t cust_cfg_len; + +extern uint8_t cal_pub_addr[6]; +extern uint16_t cal_pub_addr_len; + +/// Check for presence of calibration field +#define CAL_PRESENT(__s, __f) \ + (__s ## _len >= __OFFSET(__s, __f) + sizeof(__s.__f)) + +#define PMU_TOP_CAL(__s, __f, __reg) do { \ + if (CAL_PRESENT(__s, __f)) { \ + PMU_WRITE(TOP, __reg, __s.__f); \ + } \ +} while (0) + +#ifdef __cplusplus +} +#endif + +/// @} CALIBRATION diff --git a/ATM33xx-5/include/iccarm/compiler.h b/ATM33xx-5/include/iccarm/compiler.h new file mode 100644 index 0000000..c81f1ac --- /dev/null +++ b/ATM33xx-5/include/iccarm/compiler.h @@ -0,0 +1,122 @@ +/** + ******************************************************************************* + * + * @file compiler.h + * + * @brief Definitions of compiler specific directives. + * + * Copyright (C) Atmosic 2021 + * + ******************************************************************************* + */ + +#pragma once + +/** + * @defgroup COMPILER Compiler + * @ingroup ATMx3 + * @brief IAR ANSI C/C++ compiler interface + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __ICCARM__ +#error "File only included with IAR ANSI C/C++ Compiler for ARM" +#endif + +/// define the static keyword for this compiler +#define __STATIC static + +/// define the force inlining attribute for this compiler +#define __INLINE _Pragma("inline=forced") static inline + +/// define the IRQ handler attribute for this compiler +#define __IRQ __irq + +/// define the BLE IRQ handler attribute for this compiler +#define __BTIRQ + +/// define the BLE IRQ handler attribute for this compiler +#define __BLEIRQ + +/// define the FIQ handler attribute for this compiler +#define __FIQ __fiq + +/// define size of an empty array (used to declare structure with an array size not defined) +#define __ARRAY_EMPTY + +/// Function returns struct in registers (4 in rvds, var with gnuarm). +/// With Gnuarm, feature depends on command line options and +/// impacts ALL functions returning 2-words max structs +/// (check -freg-struct-return and -mabi=xxx) +#define __VIR + +/// function has no side effect and return depends only on arguments +#define __PURE +#define __PUREISH + +/// Function never returns +#define __NORETURN __noreturn + +/// Align instantiated lvalue or struct member on 4 bytes +#define __ALIGN4 __attribute__((aligned(4))) + +/// __MODULE__ comes from the RVDS compiler that supports it +#ifndef __MODULE__ +#define __MODULE__ __BASE_FILE__ +#endif + +/// Pack a structure field +#define __PACKED __attribute__ ((__packed__)) + +/// Put a variable in a memory maintained during deep sleep +#define __LOWPOWER_SAVED + +/// Do not initialize variable at startup +/// Create unique section header @file+line +#define __UNINIT __no_init + +/// Locate code in high performance memory +#define __FAST + +/// Not ROM, so keep private +#define __NR_STATIC static + +/// Compile-time assertion +#define STATIC_ASSERT _Static_assert + +/// Unused variable +#define __UNUSED __attribute__((unused)) + +/// Convert context pointer from const to non-const +#define CONTEXT_VOID_P(__p) ((void *)(uintptr_t)(__p)) + +/// Printf-like function +#define __PRINTF(...) + +/// Arguments not permitting NULL value +#define __NONNULL_ALL +#define __NONNULL(...) + +/// Field position in compound object +#define __OFFSET(__s, __f) (((char *)&(__s.__f)) - (char *)&(__s)) + +/// Constructor priority not supported - must be managed by linker script +#define __CONSTRUCTOR_PRIO(__p) __attribute__((constructor)) + +/// Convert structured struct with different type name +#define TYPE_CONVERT(src_type, var, dst_type) ({ \ + STATIC_ASSERT(sizeof(src_type) == sizeof(dst_type), "incompatable"); \ + *(dst_type const *)&var;}) + +/// Variables that may not be aligned +#define __UNALIGNED + +#ifdef __cplusplus +} +#endif + +/// @} COMPILER diff --git a/ATM33xx-5/include/ll.h b/ATM33xx-5/include/ll.h new file mode 100644 index 0000000..1717597 --- /dev/null +++ b/ATM33xx-5/include/ll.h @@ -0,0 +1,125 @@ +/** + ******************************************************************************* + * + * @file ll.h + * + * @brief Declaration of low level functions. + * + * Copyright (C) RivieraWaves 2009-2015 + * Copyright (C) Atmosic 2021 + * + ******************************************************************************* + */ + +#pragma once + +/** + * @defgroup LL Low level + * @ingroup ATMx3 + * @brief Low level functions + * @{ + */ + +#if !defined(__GNUC__) && !defined(__ICCARM__) +#error "File only included with ARM GCC or IAR ANSI C/C++ Compiler for ARM" +#endif + +#ifndef __ARM_FEATURE_DSP +#define __ARM_FEATURE_DSP 0 +#endif +#include "cmsis_compiler.h" + +#ifdef __ICCARM__ +#include +#endif + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/// Interrupt priorities +#define IRQ_PRI_RT 0 // Real time - highest priority +#define IRQ_PRI_VERY_HIGH 2 +#define IRQ_PRI_HIGH 4 +#define IRQ_PRI_MID 6 +#define IRQ_PRI_NORMAL 8 +#define IRQ_PRI_LOW 10 +#define IRQ_PRI_UI 12 // User interface - lowest priority + +/** @brief Enable interrupts globally in the system. + * This macro must be used when the initialization phase is over and the interrupts + * can start being handled by the system. + */ +#define GLOBAL_INT_START() \ +do { \ + __enable_irq(); \ +} while(0) + +/** @brief Disable interrupts globally in the system. + * This macro must be used when the system wants to disable all the interrupt + * it could handle. + */ +#define GLOBAL_INT_STOP() \ +do { \ + __disable_irq(); \ +} while(0) + +/** @brief Disable interrupts globally in the system. + * This macro must be used in conjunction with the @ref GLOBAL_INT_RESTORE macro since this + * last one will close the brace that the current macro opens. This means that both + * macros must be located at the same scope level. + */ +#define GLOBAL_INT_DISABLE() \ +do { \ + uint32_t __PRIMASK_save = __get_PRIMASK(); \ + __disable_irq() + +#define STATIC_GLOBAL_INT_DISABLE() \ +do { \ + static uint32_t __PRIMASK_save; \ + __PRIMASK_save = __get_PRIMASK(); \ + __disable_irq() + +/** @brief Restore interrupts from the previous global disable. + * @sa GLOBAL_INT_DISABLE + */ +#define GLOBAL_INT_RESTORE() \ + __set_PRIMASK(__PRIMASK_save); \ +} while(0) + +/** @brief Invoke the wait for interrupt procedure of the processor. + * + * @warning It is suggested that this macro is called while the interrupts are disabled + * to have performed the checks necessary to decide to move to sleep mode. + * + */ +#define WFI() __WFI() + +/** + * @brief Wait for a condition to be made true by an interrupt handler. + */ +#define WFI_COND(__c) do { \ + bool done = false; \ + do { \ + GLOBAL_INT_DISABLE(); \ + if (__c) { \ + done = true; \ + } else { \ + WFI(); \ + } \ + GLOBAL_INT_RESTORE(); \ + } while (!done); \ +} while(0) + +/** + * @brief Relax the running CPU thread, especially when spinning. + */ +#define YIELD() __ASM volatile ("yield") + +#ifdef __cplusplus +} +#endif + +/// @} LL diff --git a/ATM33xx-5/include/pseq_status.h b/ATM33xx-5/include/pseq_status.h new file mode 100644 index 0000000..b1891ac --- /dev/null +++ b/ATM33xx-5/include/pseq_status.h @@ -0,0 +1,35 @@ +/** + ******************************************************************************* + * + * @file pseq_status.h + * + * @brief System power management status + * + * Copyright (C) Atmosic 2023 + * + ******************************************************************************* + */ + +#pragma once + +/** + * @ingroup PSEQ + * @brief System power management status + * @{ + */ + +#include "at_apb_pseq_regs_core_macro.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PSEQ_STATUS_NON_POWER_ON (0xff) +#define PSEQ_STATUS__POWER_ON_REASONS \ + (PSEQ_STATUS__READ & ~PSEQ_STATUS_NON_POWER_ON) + +#ifdef __cplusplus +} +#endif + +/// @} diff --git a/ATM33xx-5/include/reg/at_ahb_dma_regs_core_macro.h b/ATM33xx-5/include/reg/at_ahb_dma_regs_core_macro.h new file mode 100644 index 0000000..0717cae --- /dev/null +++ b/ATM33xx-5/include/reg/at_ahb_dma_regs_core_macro.h @@ -0,0 +1,4650 @@ +/* */ +/* File: at_ahb_dma_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_ahb_dma_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_AHB_DMA_REGS_CORE_H__ +#define __REG_AT_AHB_DMA_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_AHB_DMA_REGS_CORE at_ahb_dma_regs_core + * @ingroup AT_REG + * @brief at_ahb_dma_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_opmode */ +/** + * @defgroup at_ahb_dma_regs_core_opmode opmode + * @brief Contains register fields associated with opmode. definitions. + * @{ + */ +#ifndef __AT_DMA_OPMODE_MACRO__ +#define __AT_DMA_OPMODE_MACRO__ + +/* macros for field const_trans */ +/** + * @defgroup at_ahb_dma_regs_core_const_trans_field const_trans_field + * @brief macros for field const_trans + * @details op code start when rising edge on 'go' is detected. + * @{ + */ +#define AT_DMA_OPMODE__CONST_TRANS__SHIFT 0 +#define AT_DMA_OPMODE__CONST_TRANS__WIDTH 1 +#define AT_DMA_OPMODE__CONST_TRANS__MASK 0x00000001U +#define AT_DMA_OPMODE__CONST_TRANS__READ(src) ((uint32_t)(src) & 0x00000001U) +#define AT_DMA_OPMODE__CONST_TRANS__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define AT_DMA_OPMODE__CONST_TRANS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AT_DMA_OPMODE__CONST_TRANS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AT_DMA_OPMODE__CONST_TRANS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_OPMODE__CONST_TRANS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_OPMODE__CONST_TRANS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dat_inv */ +/** + * @defgroup at_ahb_dma_regs_core_dat_inv_field dat_inv_field + * @brief macros for field dat_inv + * @details 0= non-inverted write ; 1= inverted write (write data are bit-wise inverted) + * @{ + */ +#define AT_DMA_OPMODE__DAT_INV__SHIFT 1 +#define AT_DMA_OPMODE__DAT_INV__WIDTH 1 +#define AT_DMA_OPMODE__DAT_INV__MASK 0x00000002U +#define AT_DMA_OPMODE__DAT_INV__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_DMA_OPMODE__DAT_INV__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define AT_DMA_OPMODE__DAT_INV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define AT_DMA_OPMODE__DAT_INV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define AT_DMA_OPMODE__DAT_INV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_DMA_OPMODE__DAT_INV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_DMA_OPMODE__DAT_INV__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field const_tar_addr */ +/** + * @defgroup at_ahb_dma_regs_core_const_tar_addr_field const_tar_addr_field + * @brief macros for field const_tar_addr + * @details 1= write address remains constant at tar_addr, which is required to be word-aligned in this mode. 0= write address increments as defined by the size parameter. + * @{ + */ +#define AT_DMA_OPMODE__CONST_TAR_ADDR__SHIFT 2 +#define AT_DMA_OPMODE__CONST_TAR_ADDR__WIDTH 1 +#define AT_DMA_OPMODE__CONST_TAR_ADDR__MASK 0x00000004U +#define AT_DMA_OPMODE__CONST_TAR_ADDR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define AT_DMA_OPMODE__CONST_TAR_ADDR__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define AT_DMA_OPMODE__CONST_TAR_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define AT_DMA_OPMODE__CONST_TAR_ADDR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define AT_DMA_OPMODE__CONST_TAR_ADDR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define AT_DMA_OPMODE__CONST_TAR_ADDR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define AT_DMA_OPMODE__CONST_TAR_ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field stop */ +/** + * @defgroup at_ahb_dma_regs_core_stop_field stop_field + * @brief macros for field stop + * @details to stop pending transaction . Not self clearing. + * @{ + */ +#define AT_DMA_OPMODE__STOP__SHIFT 30 +#define AT_DMA_OPMODE__STOP__WIDTH 1 +#define AT_DMA_OPMODE__STOP__MASK 0x40000000U +#define AT_DMA_OPMODE__STOP__READ(src) (((uint32_t)(src) & 0x40000000U) >> 30) +#define AT_DMA_OPMODE__STOP__WRITE(src) (((uint32_t)(src) << 30) & 0x40000000U) +#define AT_DMA_OPMODE__STOP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define AT_DMA_OPMODE__STOP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define AT_DMA_OPMODE__STOP__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define AT_DMA_OPMODE__STOP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define AT_DMA_OPMODE__STOP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field go */ +/** + * @defgroup at_ahb_dma_regs_core_go_field go_field + * @brief macros for field go + * @details op code start when rising edge on 'go' is detected. HW clears after. + * @{ + */ +#define AT_DMA_OPMODE__GO__SHIFT 31 +#define AT_DMA_OPMODE__GO__WIDTH 1 +#define AT_DMA_OPMODE__GO__MASK 0x80000000U +#define AT_DMA_OPMODE__GO__READ(src) (((uint32_t)(src) & 0x80000000U) >> 31) +#define AT_DMA_OPMODE__GO__WRITE(src) (((uint32_t)(src) << 31) & 0x80000000U) +#define AT_DMA_OPMODE__GO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define AT_DMA_OPMODE__GO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define AT_DMA_OPMODE__GO__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define AT_DMA_OPMODE__GO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define AT_DMA_OPMODE__GO__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_OPMODE__TYPE uint32_t +#define AT_DMA_OPMODE__READ 0xc0000007U +#define AT_DMA_OPMODE__WRITE 0xc0000007U +#define AT_DMA_OPMODE__PRESERVED 0x00000000U +#define AT_DMA_OPMODE__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_OPMODE_MACRO__ */ + +/** @} end of opmode */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_const_wdata */ +/** + * @defgroup at_ahb_dma_regs_core_const_wdata const_wdata + * @brief Contains register fields associated with const_wdata. definitions. + * @{ + */ +#ifndef __AT_DMA_CONST_WDATA_MACRO__ +#define __AT_DMA_CONST_WDATA_MACRO__ + +/* macros for field const_wdata */ +/** + * @defgroup at_ahb_dma_regs_core_const_wdata_field const_wdata_field + * @brief macros for field const_wdata + * @details constant value to be written to target when the operation is in const_trans mode. + * @{ + */ +#define AT_DMA_CONST_WDATA__CONST_WDATA__SHIFT 0 +#define AT_DMA_CONST_WDATA__CONST_WDATA__WIDTH 32 +#define AT_DMA_CONST_WDATA__CONST_WDATA__MASK 0xffffffffU +#define AT_DMA_CONST_WDATA__CONST_WDATA__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CONST_WDATA__CONST_WDATA__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CONST_WDATA__CONST_WDATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_DMA_CONST_WDATA__CONST_WDATA__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_DMA_CONST_WDATA__CONST_WDATA__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CONST_WDATA__TYPE uint32_t +#define AT_DMA_CONST_WDATA__READ 0xffffffffU +#define AT_DMA_CONST_WDATA__WRITE 0xffffffffU +#define AT_DMA_CONST_WDATA__PRESERVED 0x00000000U +#define AT_DMA_CONST_WDATA__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CONST_WDATA_MACRO__ */ + +/** @} end of const_wdata */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_src_addr */ +/** + * @defgroup at_ahb_dma_regs_core_src_addr src_addr + * @brief Contains register fields associated with src_addr. definitions. + * @{ + */ +#ifndef __AT_DMA_SRC_ADDR_MACRO__ +#define __AT_DMA_SRC_ADDR_MACRO__ + +/* macros for field src_addr */ +/** + * @defgroup at_ahb_dma_regs_core_src_addr_field src_addr_field + * @brief macros for field src_addr + * @details source address + * @{ + */ +#define AT_DMA_SRC_ADDR__SRC_ADDR__SHIFT 0 +#define AT_DMA_SRC_ADDR__SRC_ADDR__WIDTH 32 +#define AT_DMA_SRC_ADDR__SRC_ADDR__MASK 0xffffffffU +#define AT_DMA_SRC_ADDR__SRC_ADDR__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_DMA_SRC_ADDR__SRC_ADDR__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_DMA_SRC_ADDR__SRC_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_DMA_SRC_ADDR__SRC_ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_DMA_SRC_ADDR__SRC_ADDR__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_SRC_ADDR__TYPE uint32_t +#define AT_DMA_SRC_ADDR__READ 0xffffffffU +#define AT_DMA_SRC_ADDR__WRITE 0xffffffffU +#define AT_DMA_SRC_ADDR__PRESERVED 0x00000000U +#define AT_DMA_SRC_ADDR__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_SRC_ADDR_MACRO__ */ + +/** @} end of src_addr */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_tar_addr */ +/** + * @defgroup at_ahb_dma_regs_core_tar_addr tar_addr + * @brief Contains register fields associated with tar_addr. definitions. + * @{ + */ +#ifndef __AT_DMA_TAR_ADDR_MACRO__ +#define __AT_DMA_TAR_ADDR_MACRO__ + +/* macros for field tar_addr */ +/** + * @defgroup at_ahb_dma_regs_core_tar_addr_field tar_addr_field + * @brief macros for field tar_addr + * @details target address + * @{ + */ +#define AT_DMA_TAR_ADDR__TAR_ADDR__SHIFT 0 +#define AT_DMA_TAR_ADDR__TAR_ADDR__WIDTH 32 +#define AT_DMA_TAR_ADDR__TAR_ADDR__MASK 0xffffffffU +#define AT_DMA_TAR_ADDR__TAR_ADDR__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_DMA_TAR_ADDR__TAR_ADDR__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_DMA_TAR_ADDR__TAR_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_DMA_TAR_ADDR__TAR_ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_DMA_TAR_ADDR__TAR_ADDR__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_TAR_ADDR__TYPE uint32_t +#define AT_DMA_TAR_ADDR__READ 0xffffffffU +#define AT_DMA_TAR_ADDR__WRITE 0xffffffffU +#define AT_DMA_TAR_ADDR__PRESERVED 0x00000000U +#define AT_DMA_TAR_ADDR__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_TAR_ADDR_MACRO__ */ + +/** @} end of tar_addr */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_size */ +/** + * @defgroup at_ahb_dma_regs_core_size size + * @brief Contains register fields associated with size. definitions. + * @{ + */ +#ifndef __AT_DMA_SIZE_MACRO__ +#define __AT_DMA_SIZE_MACRO__ + +/* macros for field size */ +/** + * @defgroup at_ahb_dma_regs_core_size_field size_field + * @brief macros for field size + * @details payload size in bytes. + * @{ + */ +#define AT_DMA_SIZE__SIZE__SHIFT 0 +#define AT_DMA_SIZE__SIZE__WIDTH 24 +#define AT_DMA_SIZE__SIZE__MASK 0x00ffffffU +#define AT_DMA_SIZE__SIZE__READ(src) ((uint32_t)(src) & 0x00ffffffU) +#define AT_DMA_SIZE__SIZE__WRITE(src) ((uint32_t)(src) & 0x00ffffffU) +#define AT_DMA_SIZE__SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((uint32_t)(src) &\ + 0x00ffffffU) +#define AT_DMA_SIZE__SIZE__VERIFY(src) (!(((uint32_t)(src) & ~0x00ffffffU))) +#define AT_DMA_SIZE__SIZE__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_SIZE__TYPE uint32_t +#define AT_DMA_SIZE__READ 0x00ffffffU +#define AT_DMA_SIZE__WRITE 0x00ffffffU +#define AT_DMA_SIZE__PRESERVED 0x00000000U +#define AT_DMA_SIZE__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_SIZE_MACRO__ */ + +/** @} end of size */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_src_ctrl */ +/** + * @defgroup at_ahb_dma_regs_core_src_ctrl src_ctrl + * @brief Contains register fields associated with src_ctrl. definitions. + * @{ + */ +#ifndef __AT_DMA_SRC_CTRL_MACRO__ +#define __AT_DMA_SRC_CTRL_MACRO__ + +/* macros for field src_type */ +/** + * @defgroup at_ahb_dma_regs_core_src_type_field src_type_field + * @brief macros for field src_type + * @details 0=mem, 1=fifo, 2=periph master, 3=periph slave + * @{ + */ +#define AT_DMA_SRC_CTRL__SRC_TYPE__SHIFT 0 +#define AT_DMA_SRC_CTRL__SRC_TYPE__WIDTH 2 +#define AT_DMA_SRC_CTRL__SRC_TYPE__MASK 0x00000003U +#define AT_DMA_SRC_CTRL__SRC_TYPE__READ(src) ((uint32_t)(src) & 0x00000003U) +#define AT_DMA_SRC_CTRL__SRC_TYPE__WRITE(src) ((uint32_t)(src) & 0x00000003U) +#define AT_DMA_SRC_CTRL__SRC_TYPE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_SRC_CTRL__SRC_TYPE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_SRC_CTRL__SRC_TYPE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field src_bus_size */ +/** + * @defgroup at_ahb_dma_regs_core_src_bus_size_field src_bus_size_field + * @brief macros for field src_bus_size + * @details the width of fifo. one byte to 4 bytes. + * @{ + */ +#define AT_DMA_SRC_CTRL__SRC_BUS_SIZE__SHIFT 2 +#define AT_DMA_SRC_CTRL__SRC_BUS_SIZE__WIDTH 3 +#define AT_DMA_SRC_CTRL__SRC_BUS_SIZE__MASK 0x0000001cU +#define AT_DMA_SRC_CTRL__SRC_BUS_SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0x0000001cU) >> 2) +#define AT_DMA_SRC_CTRL__SRC_BUS_SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000001cU) +#define AT_DMA_SRC_CTRL__SRC_BUS_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((uint32_t)(src) <<\ + 2) & 0x0000001cU) +#define AT_DMA_SRC_CTRL__SRC_BUS_SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000001cU))) +#define AT_DMA_SRC_CTRL__SRC_BUS_SIZE__RESET_VALUE 0x00000001U +/** @} */ +#define AT_DMA_SRC_CTRL__TYPE uint32_t +#define AT_DMA_SRC_CTRL__READ 0x0000001fU +#define AT_DMA_SRC_CTRL__WRITE 0x0000001fU +#define AT_DMA_SRC_CTRL__PRESERVED 0x00000000U +#define AT_DMA_SRC_CTRL__RESET_VALUE 0x00000004U + +#endif /* __AT_DMA_SRC_CTRL_MACRO__ */ + +/** @} end of src_ctrl */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_tar_ctrl */ +/** + * @defgroup at_ahb_dma_regs_core_tar_ctrl tar_ctrl + * @brief Contains register fields associated with tar_ctrl. definitions. + * @{ + */ +#ifndef __AT_DMA_TAR_CTRL_MACRO__ +#define __AT_DMA_TAR_CTRL_MACRO__ + +/* macros for field tar_type */ +/** + * @defgroup at_ahb_dma_regs_core_tar_type_field tar_type_field + * @brief macros for field tar_type + * @details 0=mem, 1=fifo, 2=periph master, 3=periph slave + * @{ + */ +#define AT_DMA_TAR_CTRL__TAR_TYPE__SHIFT 0 +#define AT_DMA_TAR_CTRL__TAR_TYPE__WIDTH 2 +#define AT_DMA_TAR_CTRL__TAR_TYPE__MASK 0x00000003U +#define AT_DMA_TAR_CTRL__TAR_TYPE__READ(src) ((uint32_t)(src) & 0x00000003U) +#define AT_DMA_TAR_CTRL__TAR_TYPE__WRITE(src) ((uint32_t)(src) & 0x00000003U) +#define AT_DMA_TAR_CTRL__TAR_TYPE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_TAR_CTRL__TAR_TYPE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_TAR_CTRL__TAR_TYPE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tar_bus_size */ +/** + * @defgroup at_ahb_dma_regs_core_tar_bus_size_field tar_bus_size_field + * @brief macros for field tar_bus_size + * @details the width of fifo. one byte to 4 bytes. + * @{ + */ +#define AT_DMA_TAR_CTRL__TAR_BUS_SIZE__SHIFT 2 +#define AT_DMA_TAR_CTRL__TAR_BUS_SIZE__WIDTH 3 +#define AT_DMA_TAR_CTRL__TAR_BUS_SIZE__MASK 0x0000001cU +#define AT_DMA_TAR_CTRL__TAR_BUS_SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0x0000001cU) >> 2) +#define AT_DMA_TAR_CTRL__TAR_BUS_SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000001cU) +#define AT_DMA_TAR_CTRL__TAR_BUS_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((uint32_t)(src) <<\ + 2) & 0x0000001cU) +#define AT_DMA_TAR_CTRL__TAR_BUS_SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000001cU))) +#define AT_DMA_TAR_CTRL__TAR_BUS_SIZE__RESET_VALUE 0x00000001U +/** @} */ +#define AT_DMA_TAR_CTRL__TYPE uint32_t +#define AT_DMA_TAR_CTRL__READ 0x0000001fU +#define AT_DMA_TAR_CTRL__WRITE 0x0000001fU +#define AT_DMA_TAR_CTRL__PRESERVED 0x00000000U +#define AT_DMA_TAR_CTRL__RESET_VALUE 0x00000004U + +#endif /* __AT_DMA_TAR_CTRL_MACRO__ */ + +/** @} end of tar_ctrl */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_fifo_dpth_addr */ +/** + * @defgroup at_ahb_dma_regs_core_fifo_dpth_addr fifo_dpth_addr + * @brief Contains register fields associated with fifo_dpth_addr. definitions. + * @{ + */ +#ifndef __AT_DMA_FIFO_DPTH_ADDR_MACRO__ +#define __AT_DMA_FIFO_DPTH_ADDR_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_ahb_dma_regs_core_addr_field addr_field + * @brief macros for field addr + * @details address of the external fifo depth. Statemachine reads this to determine how many push/pull accesses to do per interrupt. + * @{ + */ +#define AT_DMA_FIFO_DPTH_ADDR__ADDR__SHIFT 0 +#define AT_DMA_FIFO_DPTH_ADDR__ADDR__WIDTH 32 +#define AT_DMA_FIFO_DPTH_ADDR__ADDR__MASK 0xffffffffU +#define AT_DMA_FIFO_DPTH_ADDR__ADDR__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_DMA_FIFO_DPTH_ADDR__ADDR__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_DMA_FIFO_DPTH_ADDR__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_DMA_FIFO_DPTH_ADDR__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_DMA_FIFO_DPTH_ADDR__ADDR__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_FIFO_DPTH_ADDR__TYPE uint32_t +#define AT_DMA_FIFO_DPTH_ADDR__READ 0xffffffffU +#define AT_DMA_FIFO_DPTH_ADDR__WRITE 0xffffffffU +#define AT_DMA_FIFO_DPTH_ADDR__PRESERVED 0x00000000U +#define AT_DMA_FIFO_DPTH_ADDR__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_FIFO_DPTH_ADDR_MACRO__ */ + +/** @} end of fifo_dpth_addr */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_fifo_port_sel */ +/** + * @defgroup at_ahb_dma_regs_core_fifo_port_sel fifo_port_sel + * @brief Contains register fields associated with fifo_port_sel. definitions. + * @{ + */ +#ifndef __AT_DMA_FIFO_PORT_SEL_MACRO__ +#define __AT_DMA_FIFO_PORT_SEL_MACRO__ + +/* macros for field src_port_sel */ +/** + * @defgroup at_ahb_dma_regs_core_src_port_sel_field src_port_sel_field + * @brief macros for field src_port_sel + * @details selecting the source fifo port; 5 = rsvd 4 = i2s fifo 3 = pdm1 fifo 2 = pdm0 fifo 1 = uart1 rx 0 = uart0 rx + * @{ + */ +#define AT_DMA_FIFO_PORT_SEL__SRC_PORT_SEL__SHIFT 0 +#define AT_DMA_FIFO_PORT_SEL__SRC_PORT_SEL__WIDTH 3 +#define AT_DMA_FIFO_PORT_SEL__SRC_PORT_SEL__MASK 0x00000007U +#define AT_DMA_FIFO_PORT_SEL__SRC_PORT_SEL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define AT_DMA_FIFO_PORT_SEL__SRC_PORT_SEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define AT_DMA_FIFO_PORT_SEL__SRC_PORT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define AT_DMA_FIFO_PORT_SEL__SRC_PORT_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define AT_DMA_FIFO_PORT_SEL__SRC_PORT_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tar_port_sel */ +/** + * @defgroup at_ahb_dma_regs_core_tar_port_sel_field tar_port_sel_field + * @brief macros for field tar_port_sel + * @details selecting the target fifo port; 5 = pwd fifo 4 = i2s fifo 3 = rsvd 2 = rsvd 1 = uart1 tx 0 = uart0 tx + * @{ + */ +#define AT_DMA_FIFO_PORT_SEL__TAR_PORT_SEL__SHIFT 16 +#define AT_DMA_FIFO_PORT_SEL__TAR_PORT_SEL__WIDTH 3 +#define AT_DMA_FIFO_PORT_SEL__TAR_PORT_SEL__MASK 0x00070000U +#define AT_DMA_FIFO_PORT_SEL__TAR_PORT_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00070000U) >> 16) +#define AT_DMA_FIFO_PORT_SEL__TAR_PORT_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00070000U) +#define AT_DMA_FIFO_PORT_SEL__TAR_PORT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((uint32_t)(src) <<\ + 16) & 0x00070000U) +#define AT_DMA_FIFO_PORT_SEL__TAR_PORT_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00070000U))) +#define AT_DMA_FIFO_PORT_SEL__TAR_PORT_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_FIFO_PORT_SEL__TYPE uint32_t +#define AT_DMA_FIFO_PORT_SEL__READ 0x00070007U +#define AT_DMA_FIFO_PORT_SEL__WRITE 0x00070007U +#define AT_DMA_FIFO_PORT_SEL__PRESERVED 0x00000000U +#define AT_DMA_FIFO_PORT_SEL__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_FIFO_PORT_SEL_MACRO__ */ + +/** @} end of fifo_port_sel */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_spi_port_sel */ +/** + * @defgroup at_ahb_dma_regs_core_spi_port_sel spi_port_sel + * @brief Contains register fields associated with spi_port_sel. definitions. + * @{ + */ +#ifndef __AT_DMA_SPI_PORT_SEL_MACRO__ +#define __AT_DMA_SPI_PORT_SEL_MACRO__ + +/* macros for field spi_sel */ +/** + * @defgroup at_ahb_dma_regs_core_spi_sel_field spi_sel_field + * @brief macros for field spi_sel + * @details 1=select spi1 for this channel, 0=select spi0 for this channel. + * @{ + */ +#define AT_DMA_SPI_PORT_SEL__SPI_SEL__SHIFT 0 +#define AT_DMA_SPI_PORT_SEL__SPI_SEL__WIDTH 1 +#define AT_DMA_SPI_PORT_SEL__SPI_SEL__MASK 0x00000001U +#define AT_DMA_SPI_PORT_SEL__SPI_SEL__READ(src) ((uint32_t)(src) & 0x00000001U) +#define AT_DMA_SPI_PORT_SEL__SPI_SEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_SPI_PORT_SEL__SPI_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AT_DMA_SPI_PORT_SEL__SPI_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AT_DMA_SPI_PORT_SEL__SPI_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_SPI_PORT_SEL__SPI_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_SPI_PORT_SEL__SPI_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_SPI_PORT_SEL__TYPE uint32_t +#define AT_DMA_SPI_PORT_SEL__READ 0x00000001U +#define AT_DMA_SPI_PORT_SEL__WRITE 0x00000001U +#define AT_DMA_SPI_PORT_SEL__PRESERVED 0x00000000U +#define AT_DMA_SPI_PORT_SEL__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_SPI_PORT_SEL_MACRO__ */ + +/** @} end of spi_port_sel */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_err_stat */ +/** + * @defgroup at_ahb_dma_regs_core_err_stat err_stat + * @brief The status is cleared when the err interrupt is cleared definitions. + * @{ + */ +#ifndef __AT_DMA_ERR_STAT_MACRO__ +#define __AT_DMA_ERR_STAT_MACRO__ + +/* macros for field size_0 */ +/** + * @defgroup at_ahb_dma_regs_core_size_0_field size_0_field + * @brief macros for field size_0 + * @details 0= size is not 0 when go is launched, 1= size is 0 when go is launched. + * @{ + */ +#define AT_DMA_ERR_STAT__SIZE_0__SHIFT 0 +#define AT_DMA_ERR_STAT__SIZE_0__WIDTH 1 +#define AT_DMA_ERR_STAT__SIZE_0__MASK 0x00000001U +#define AT_DMA_ERR_STAT__SIZE_0__READ(src) ((uint32_t)(src) & 0x00000001U) +#define AT_DMA_ERR_STAT__SIZE_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_ERR_STAT__SIZE_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_ERR_STAT__SIZE_0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field addr_ovlp */ +/** + * @defgroup at_ahb_dma_regs_core_addr_ovlp_field addr_ovlp_field + * @brief macros for field addr_ovlp + * @details 0= no overlap between src and tar addr range, 1= there is an overlap + * @{ + */ +#define AT_DMA_ERR_STAT__ADDR_OVLP__SHIFT 1 +#define AT_DMA_ERR_STAT__ADDR_OVLP__WIDTH 1 +#define AT_DMA_ERR_STAT__ADDR_OVLP__MASK 0x00000002U +#define AT_DMA_ERR_STAT__ADDR_OVLP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_DMA_ERR_STAT__ADDR_OVLP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_DMA_ERR_STAT__ADDR_OVLP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_DMA_ERR_STAT__ADDR_OVLP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bus_err */ +/** + * @defgroup at_ahb_dma_regs_core_bus_err_field bus_err_field + * @brief macros for field bus_err + * @details 0= no bus error, 1= a bus error occur during the transfer or at the launch of 'go'. + * @{ + */ +#define AT_DMA_ERR_STAT__BUS_ERR__SHIFT 2 +#define AT_DMA_ERR_STAT__BUS_ERR__WIDTH 1 +#define AT_DMA_ERR_STAT__BUS_ERR__MASK 0x00000004U +#define AT_DMA_ERR_STAT__BUS_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define AT_DMA_ERR_STAT__BUS_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define AT_DMA_ERR_STAT__BUS_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define AT_DMA_ERR_STAT__BUS_ERR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field addr_ovfl */ +/** + * @defgroup at_ahb_dma_regs_core_addr_ovfl_field addr_ovfl_field + * @brief macros for field addr_ovfl + * @details 0= no error, 1= error due to size + src_addr/tar_addr > 32'hffff_ffff. + * @{ + */ +#define AT_DMA_ERR_STAT__ADDR_OVFL__SHIFT 3 +#define AT_DMA_ERR_STAT__ADDR_OVFL__WIDTH 1 +#define AT_DMA_ERR_STAT__ADDR_OVFL__MASK 0x00000008U +#define AT_DMA_ERR_STAT__ADDR_OVFL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define AT_DMA_ERR_STAT__ADDR_OVFL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define AT_DMA_ERR_STAT__ADDR_OVFL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define AT_DMA_ERR_STAT__ADDR_OVFL__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_ERR_STAT__TYPE uint32_t +#define AT_DMA_ERR_STAT__READ 0x0000000fU +#define AT_DMA_ERR_STAT__PRESERVED 0x00000000U +#define AT_DMA_ERR_STAT__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_ERR_STAT_MACRO__ */ + +/** @} end of err_stat */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_status */ +/** + * @defgroup at_ahb_dma_regs_core_status status + * @brief Contains register fields associated with status. definitions. + * @{ + */ +#ifndef __AT_DMA_STATUS_MACRO__ +#define __AT_DMA_STATUS_MACRO__ + +/* macros for field running */ +/** + * @defgroup at_ahb_dma_regs_core_running_field running_field + * @brief macros for field running + * @details fsm is in an active state, not waiting for the bus or an interrupt. + * @{ + */ +#define AT_DMA_STATUS__RUNNING__SHIFT 0 +#define AT_DMA_STATUS__RUNNING__WIDTH 1 +#define AT_DMA_STATUS__RUNNING__MASK 0x00000001U +#define AT_DMA_STATUS__RUNNING__READ(src) ((uint32_t)(src) & 0x00000001U) +#define AT_DMA_STATUS__RUNNING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_STATUS__RUNNING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_STATUS__RUNNING__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field busy */ +/** + * @defgroup at_ahb_dma_regs_core_busy_field busy_field + * @brief macros for field busy + * @details fsm is in some non-idle state including waiting for the bus or an interrupt. + * @{ + */ +#define AT_DMA_STATUS__BUSY__SHIFT 1 +#define AT_DMA_STATUS__BUSY__WIDTH 1 +#define AT_DMA_STATUS__BUSY__MASK 0x00000002U +#define AT_DMA_STATUS__BUSY__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define AT_DMA_STATUS__BUSY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_DMA_STATUS__BUSY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_DMA_STATUS__BUSY__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_STATUS__TYPE uint32_t +#define AT_DMA_STATUS__READ 0x00000003U +#define AT_DMA_STATUS__PRESERVED 0x00000000U +#define AT_DMA_STATUS__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_STATUS_MACRO__ */ + +/** @} end of status */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_total_write_remainder */ +/** + * @defgroup at_ahb_dma_regs_core_total_write_remainder total_write_remainder + * @brief Contains register fields associated with total_write_remainder. definitions. + * @{ + */ +#ifndef __AT_DMA_TOTAL_WRITE_REMAINDER_MACRO__ +#define __AT_DMA_TOTAL_WRITE_REMAINDER_MACRO__ + +/* macros for field total_write_remainder */ +/** + * @defgroup at_ahb_dma_regs_core_total_write_remainder_field total_write_remainder_field + * @brief macros for field total_write_remainder + * @details number of bytes left to write at the time of stop + * @{ + */ +#define AT_DMA_TOTAL_WRITE_REMAINDER__TOTAL_WRITE_REMAINDER__SHIFT 0 +#define AT_DMA_TOTAL_WRITE_REMAINDER__TOTAL_WRITE_REMAINDER__WIDTH 24 +#define AT_DMA_TOTAL_WRITE_REMAINDER__TOTAL_WRITE_REMAINDER__MASK 0x00ffffffU +#define AT_DMA_TOTAL_WRITE_REMAINDER__TOTAL_WRITE_REMAINDER__READ(src) \ + ((uint32_t)(src)\ + & 0x00ffffffU) +#define AT_DMA_TOTAL_WRITE_REMAINDER__TOTAL_WRITE_REMAINDER__RESET_VALUE \ + 0x00000000U +/** @} */ +#define AT_DMA_TOTAL_WRITE_REMAINDER__TYPE uint32_t +#define AT_DMA_TOTAL_WRITE_REMAINDER__READ 0x00ffffffU +#define AT_DMA_TOTAL_WRITE_REMAINDER__PRESERVED 0x00000000U +#define AT_DMA_TOTAL_WRITE_REMAINDER__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_TOTAL_WRITE_REMAINDER_MACRO__ */ + +/** @} end of total_write_remainder */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_interrupt_status */ +/** + * @defgroup at_ahb_dma_regs_core_interrupt_status interrupt_status + * @brief Contains register fields associated with interrupt_status. definitions. + * @{ + */ +#ifndef __AT_DMA_INTERRUPT_STATUS_MACRO__ +#define __AT_DMA_INTERRUPT_STATUS_MACRO__ + +/* macros for field dma_done */ +/** + * @defgroup at_ahb_dma_regs_core_dma_done_field dma_done_field + * @brief macros for field dma_done + * @details source of interrupt due to completion (chan0). + * @{ + */ +#define AT_DMA_INTERRUPT_STATUS__DMA_DONE__SHIFT 0 +#define AT_DMA_INTERRUPT_STATUS__DMA_DONE__WIDTH 1 +#define AT_DMA_INTERRUPT_STATUS__DMA_DONE__MASK 0x00000001U +#define AT_DMA_INTERRUPT_STATUS__DMA_DONE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_INTERRUPT_STATUS__DMA_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_INTERRUPT_STATUS__DMA_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_INTERRUPT_STATUS__DMA_DONE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dma_err */ +/** + * @defgroup at_ahb_dma_regs_core_dma_err_field dma_err_field + * @brief macros for field dma_err + * @details source of interrupt due to an error (chan0). + * @{ + */ +#define AT_DMA_INTERRUPT_STATUS__DMA_ERR__SHIFT 1 +#define AT_DMA_INTERRUPT_STATUS__DMA_ERR__WIDTH 1 +#define AT_DMA_INTERRUPT_STATUS__DMA_ERR__MASK 0x00000002U +#define AT_DMA_INTERRUPT_STATUS__DMA_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_DMA_INTERRUPT_STATUS__DMA_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_DMA_INTERRUPT_STATUS__DMA_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_DMA_INTERRUPT_STATUS__DMA_ERR__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_INTERRUPT_STATUS__TYPE uint32_t +#define AT_DMA_INTERRUPT_STATUS__READ 0x00000003U +#define AT_DMA_INTERRUPT_STATUS__PRESERVED 0x00000000U +#define AT_DMA_INTERRUPT_STATUS__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_INTERRUPT_STATUS_MACRO__ */ + +/** @} end of interrupt_status */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_interrupt_mask */ +/** + * @defgroup at_ahb_dma_regs_core_interrupt_mask interrupt_mask + * @brief Contains register fields associated with interrupt_mask. definitions. + * @{ + */ +#ifndef __AT_DMA_INTERRUPT_MASK_MACRO__ +#define __AT_DMA_INTERRUPT_MASK_MACRO__ + +/* macros for field intrpt_mask */ +/** + * @defgroup at_ahb_dma_regs_core_intrpt_mask_field intrpt_mask_field + * @brief macros for field intrpt_mask + * @details if nth bit set, the nth interrupt is enabled + * @{ + */ +#define AT_DMA_INTERRUPT_MASK__INTRPT_MASK__SHIFT 0 +#define AT_DMA_INTERRUPT_MASK__INTRPT_MASK__WIDTH 2 +#define AT_DMA_INTERRUPT_MASK__INTRPT_MASK__MASK 0x00000003U +#define AT_DMA_INTERRUPT_MASK__INTRPT_MASK__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_INTERRUPT_MASK__INTRPT_MASK__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_INTERRUPT_MASK__INTRPT_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_INTERRUPT_MASK__INTRPT_MASK__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_INTERRUPT_MASK__INTRPT_MASK__RESET_VALUE 0x00000001U +/** @} */ +#define AT_DMA_INTERRUPT_MASK__TYPE uint32_t +#define AT_DMA_INTERRUPT_MASK__READ 0x00000003U +#define AT_DMA_INTERRUPT_MASK__WRITE 0x00000003U +#define AT_DMA_INTERRUPT_MASK__PRESERVED 0x00000000U +#define AT_DMA_INTERRUPT_MASK__RESET_VALUE 0x00000001U + +#endif /* __AT_DMA_INTERRUPT_MASK_MACRO__ */ + +/** @} end of interrupt_mask */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_set_interrupt */ +/** + * @defgroup at_ahb_dma_regs_core_set_interrupt set_interrupt + * @brief Contains register fields associated with set_interrupt. definitions. + * @{ + */ +#ifndef __AT_DMA_SET_INTERRUPT_MACRO__ +#define __AT_DMA_SET_INTERRUPT_MACRO__ + +/* macros for field intrpt_set */ +/** + * @defgroup at_ahb_dma_regs_core_intrpt_set_field intrpt_set_field + * @brief macros for field intrpt_set + * @details if nth bit set, the nth interrupt is set; HW clears all bits the next cycle. + * @{ + */ +#define AT_DMA_SET_INTERRUPT__INTRPT_SET__SHIFT 0 +#define AT_DMA_SET_INTERRUPT__INTRPT_SET__WIDTH 2 +#define AT_DMA_SET_INTERRUPT__INTRPT_SET__MASK 0x00000003U +#define AT_DMA_SET_INTERRUPT__INTRPT_SET__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_SET_INTERRUPT__INTRPT_SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_SET_INTERRUPT__INTRPT_SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_SET_INTERRUPT__INTRPT_SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_SET_INTERRUPT__INTRPT_SET__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_SET_INTERRUPT__TYPE uint32_t +#define AT_DMA_SET_INTERRUPT__READ 0x00000003U +#define AT_DMA_SET_INTERRUPT__WRITE 0x00000003U +#define AT_DMA_SET_INTERRUPT__PRESERVED 0x00000000U +#define AT_DMA_SET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_SET_INTERRUPT_MACRO__ */ + +/** @} end of set_interrupt */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_reset_interrupt */ +/** + * @defgroup at_ahb_dma_regs_core_reset_interrupt reset_interrupt + * @brief Contains register fields associated with reset_interrupt. definitions. + * @{ + */ +#ifndef __AT_DMA_RESET_INTERRUPT_MACRO__ +#define __AT_DMA_RESET_INTERRUPT_MACRO__ + +/* macros for field intrpt_reset */ +/** + * @defgroup at_ahb_dma_regs_core_intrpt_reset_field intrpt_reset_field + * @brief macros for field intrpt_reset + * @details if nth bit set, the nth interrupt is reset; HW clears all bits the next cycle. + * @{ + */ +#define AT_DMA_RESET_INTERRUPT__INTRPT_RESET__SHIFT 0 +#define AT_DMA_RESET_INTERRUPT__INTRPT_RESET__WIDTH 2 +#define AT_DMA_RESET_INTERRUPT__INTRPT_RESET__MASK 0x00000003U +#define AT_DMA_RESET_INTERRUPT__INTRPT_RESET__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_RESET_INTERRUPT__INTRPT_RESET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_RESET_INTERRUPT__INTRPT_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_RESET_INTERRUPT__INTRPT_RESET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_RESET_INTERRUPT__INTRPT_RESET__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_RESET_INTERRUPT__TYPE uint32_t +#define AT_DMA_RESET_INTERRUPT__READ 0x00000003U +#define AT_DMA_RESET_INTERRUPT__WRITE 0x00000003U +#define AT_DMA_RESET_INTERRUPT__PRESERVED 0x00000000U +#define AT_DMA_RESET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_RESET_INTERRUPT_MACRO__ */ + +/** @} end of reset_interrupt */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_cfg_hnonsec */ +/** + * @defgroup at_ahb_dma_regs_core_cfg_hnonsec cfg_hnonsec + * @brief Contains register fields associated with cfg_hnonsec. definitions. + * @{ + */ +#ifndef __AT_DMA_CFG_HNONSEC_MACRO__ +#define __AT_DMA_CFG_HNONSEC_MACRO__ + +/* macros for field cfg_hnonsec */ +/** + * @defgroup at_ahb_dma_regs_core_cfg_hnonsec_field cfg_hnonsec_field + * @brief macros for field cfg_hnonsec + * @details control HNONSEC output signal of this channel. This register is only Write-able by Secure program. + * @{ + */ +#define AT_DMA_CFG_HNONSEC__CFG_HNONSEC__SHIFT 0 +#define AT_DMA_CFG_HNONSEC__CFG_HNONSEC__WIDTH 1 +#define AT_DMA_CFG_HNONSEC__CFG_HNONSEC__MASK 0x00000001U +#define AT_DMA_CFG_HNONSEC__CFG_HNONSEC__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CFG_HNONSEC__CFG_HNONSEC__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CFG_HNONSEC__CFG_HNONSEC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AT_DMA_CFG_HNONSEC__CFG_HNONSEC__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AT_DMA_CFG_HNONSEC__CFG_HNONSEC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_CFG_HNONSEC__CFG_HNONSEC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_CFG_HNONSEC__CFG_HNONSEC__RESET_VALUE 0x00000001U +/** @} */ +#define AT_DMA_CFG_HNONSEC__TYPE uint32_t +#define AT_DMA_CFG_HNONSEC__READ 0x00000001U +#define AT_DMA_CFG_HNONSEC__WRITE 0x00000001U +#define AT_DMA_CFG_HNONSEC__PRESERVED 0x00000000U +#define AT_DMA_CFG_HNONSEC__RESET_VALUE 0x00000001U + +#endif /* __AT_DMA_CFG_HNONSEC_MACRO__ */ + +/** @} end of cfg_hnonsec */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan1_opmode */ +/** + * @defgroup at_ahb_dma_regs_core_chan1_opmode chan1_opmode + * @brief Contains register fields associated with chan1_opmode. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN1_OPMODE_MACRO__ +#define __AT_DMA_CHAN1_OPMODE_MACRO__ + +/* macros for field const_trans */ +/** + * @defgroup at_ahb_dma_regs_core_const_trans_field const_trans_field + * @brief macros for field const_trans + * @details op code start when rising edge on 'go' is detected. + * @{ + */ +#define AT_DMA_CHAN1_OPMODE__CONST_TRANS__SHIFT 0 +#define AT_DMA_CHAN1_OPMODE__CONST_TRANS__WIDTH 1 +#define AT_DMA_CHAN1_OPMODE__CONST_TRANS__MASK 0x00000001U +#define AT_DMA_CHAN1_OPMODE__CONST_TRANS__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN1_OPMODE__CONST_TRANS__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN1_OPMODE__CONST_TRANS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AT_DMA_CHAN1_OPMODE__CONST_TRANS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AT_DMA_CHAN1_OPMODE__CONST_TRANS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_CHAN1_OPMODE__CONST_TRANS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_CHAN1_OPMODE__CONST_TRANS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dat_inv */ +/** + * @defgroup at_ahb_dma_regs_core_dat_inv_field dat_inv_field + * @brief macros for field dat_inv + * @details 0= non-inverted write ; 1= inverted write (write data are bit-wise inverted) + * @{ + */ +#define AT_DMA_CHAN1_OPMODE__DAT_INV__SHIFT 1 +#define AT_DMA_CHAN1_OPMODE__DAT_INV__WIDTH 1 +#define AT_DMA_CHAN1_OPMODE__DAT_INV__MASK 0x00000002U +#define AT_DMA_CHAN1_OPMODE__DAT_INV__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_DMA_CHAN1_OPMODE__DAT_INV__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define AT_DMA_CHAN1_OPMODE__DAT_INV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define AT_DMA_CHAN1_OPMODE__DAT_INV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define AT_DMA_CHAN1_OPMODE__DAT_INV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_DMA_CHAN1_OPMODE__DAT_INV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_DMA_CHAN1_OPMODE__DAT_INV__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field const_tar_addr */ +/** + * @defgroup at_ahb_dma_regs_core_const_tar_addr_field const_tar_addr_field + * @brief macros for field const_tar_addr + * @details 1= write address remains constant at tar_addr, which is required to be word-aligned in this mode. 0= write address increments as defined by the size parameter. + * @{ + */ +#define AT_DMA_CHAN1_OPMODE__CONST_TAR_ADDR__SHIFT 2 +#define AT_DMA_CHAN1_OPMODE__CONST_TAR_ADDR__WIDTH 1 +#define AT_DMA_CHAN1_OPMODE__CONST_TAR_ADDR__MASK 0x00000004U +#define AT_DMA_CHAN1_OPMODE__CONST_TAR_ADDR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define AT_DMA_CHAN1_OPMODE__CONST_TAR_ADDR__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define AT_DMA_CHAN1_OPMODE__CONST_TAR_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define AT_DMA_CHAN1_OPMODE__CONST_TAR_ADDR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define AT_DMA_CHAN1_OPMODE__CONST_TAR_ADDR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define AT_DMA_CHAN1_OPMODE__CONST_TAR_ADDR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define AT_DMA_CHAN1_OPMODE__CONST_TAR_ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field stop */ +/** + * @defgroup at_ahb_dma_regs_core_stop_field stop_field + * @brief macros for field stop + * @details to stop pending transaction . Not self clearing. + * @{ + */ +#define AT_DMA_CHAN1_OPMODE__STOP__SHIFT 30 +#define AT_DMA_CHAN1_OPMODE__STOP__WIDTH 1 +#define AT_DMA_CHAN1_OPMODE__STOP__MASK 0x40000000U +#define AT_DMA_CHAN1_OPMODE__STOP__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define AT_DMA_CHAN1_OPMODE__STOP__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define AT_DMA_CHAN1_OPMODE__STOP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define AT_DMA_CHAN1_OPMODE__STOP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define AT_DMA_CHAN1_OPMODE__STOP__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define AT_DMA_CHAN1_OPMODE__STOP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define AT_DMA_CHAN1_OPMODE__STOP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field go */ +/** + * @defgroup at_ahb_dma_regs_core_go_field go_field + * @brief macros for field go + * @details op code start when rising edge on 'go' is detected. HW clears after. + * @{ + */ +#define AT_DMA_CHAN1_OPMODE__GO__SHIFT 31 +#define AT_DMA_CHAN1_OPMODE__GO__WIDTH 1 +#define AT_DMA_CHAN1_OPMODE__GO__MASK 0x80000000U +#define AT_DMA_CHAN1_OPMODE__GO__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define AT_DMA_CHAN1_OPMODE__GO__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define AT_DMA_CHAN1_OPMODE__GO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define AT_DMA_CHAN1_OPMODE__GO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define AT_DMA_CHAN1_OPMODE__GO__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define AT_DMA_CHAN1_OPMODE__GO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define AT_DMA_CHAN1_OPMODE__GO__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN1_OPMODE__TYPE uint32_t +#define AT_DMA_CHAN1_OPMODE__READ 0xc0000007U +#define AT_DMA_CHAN1_OPMODE__WRITE 0xc0000007U +#define AT_DMA_CHAN1_OPMODE__PRESERVED 0x00000000U +#define AT_DMA_CHAN1_OPMODE__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN1_OPMODE_MACRO__ */ + +/** @} end of chan1_opmode */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan1_const_wdata */ +/** + * @defgroup at_ahb_dma_regs_core_chan1_const_wdata chan1_const_wdata + * @brief Contains register fields associated with chan1_const_wdata. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN1_CONST_WDATA_MACRO__ +#define __AT_DMA_CHAN1_CONST_WDATA_MACRO__ + +/* macros for field const_wdata */ +/** + * @defgroup at_ahb_dma_regs_core_const_wdata_field const_wdata_field + * @brief macros for field const_wdata + * @details constant value to be written to target when the operation is in const_trans mode. + * @{ + */ +#define AT_DMA_CHAN1_CONST_WDATA__CONST_WDATA__SHIFT 0 +#define AT_DMA_CHAN1_CONST_WDATA__CONST_WDATA__WIDTH 32 +#define AT_DMA_CHAN1_CONST_WDATA__CONST_WDATA__MASK 0xffffffffU +#define AT_DMA_CHAN1_CONST_WDATA__CONST_WDATA__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN1_CONST_WDATA__CONST_WDATA__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN1_CONST_WDATA__CONST_WDATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_DMA_CHAN1_CONST_WDATA__CONST_WDATA__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_DMA_CHAN1_CONST_WDATA__CONST_WDATA__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN1_CONST_WDATA__TYPE uint32_t +#define AT_DMA_CHAN1_CONST_WDATA__READ 0xffffffffU +#define AT_DMA_CHAN1_CONST_WDATA__WRITE 0xffffffffU +#define AT_DMA_CHAN1_CONST_WDATA__PRESERVED 0x00000000U +#define AT_DMA_CHAN1_CONST_WDATA__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN1_CONST_WDATA_MACRO__ */ + +/** @} end of chan1_const_wdata */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan1_src_addr */ +/** + * @defgroup at_ahb_dma_regs_core_chan1_src_addr chan1_src_addr + * @brief Contains register fields associated with chan1_src_addr. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN1_SRC_ADDR_MACRO__ +#define __AT_DMA_CHAN1_SRC_ADDR_MACRO__ + +/* macros for field src_addr */ +/** + * @defgroup at_ahb_dma_regs_core_src_addr_field src_addr_field + * @brief macros for field src_addr + * @details source address + * @{ + */ +#define AT_DMA_CHAN1_SRC_ADDR__SRC_ADDR__SHIFT 0 +#define AT_DMA_CHAN1_SRC_ADDR__SRC_ADDR__WIDTH 32 +#define AT_DMA_CHAN1_SRC_ADDR__SRC_ADDR__MASK 0xffffffffU +#define AT_DMA_CHAN1_SRC_ADDR__SRC_ADDR__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN1_SRC_ADDR__SRC_ADDR__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN1_SRC_ADDR__SRC_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_DMA_CHAN1_SRC_ADDR__SRC_ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_DMA_CHAN1_SRC_ADDR__SRC_ADDR__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN1_SRC_ADDR__TYPE uint32_t +#define AT_DMA_CHAN1_SRC_ADDR__READ 0xffffffffU +#define AT_DMA_CHAN1_SRC_ADDR__WRITE 0xffffffffU +#define AT_DMA_CHAN1_SRC_ADDR__PRESERVED 0x00000000U +#define AT_DMA_CHAN1_SRC_ADDR__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN1_SRC_ADDR_MACRO__ */ + +/** @} end of chan1_src_addr */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan1_tar_addr */ +/** + * @defgroup at_ahb_dma_regs_core_chan1_tar_addr chan1_tar_addr + * @brief Contains register fields associated with chan1_tar_addr. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN1_TAR_ADDR_MACRO__ +#define __AT_DMA_CHAN1_TAR_ADDR_MACRO__ + +/* macros for field tar_addr */ +/** + * @defgroup at_ahb_dma_regs_core_tar_addr_field tar_addr_field + * @brief macros for field tar_addr + * @details target address + * @{ + */ +#define AT_DMA_CHAN1_TAR_ADDR__TAR_ADDR__SHIFT 0 +#define AT_DMA_CHAN1_TAR_ADDR__TAR_ADDR__WIDTH 32 +#define AT_DMA_CHAN1_TAR_ADDR__TAR_ADDR__MASK 0xffffffffU +#define AT_DMA_CHAN1_TAR_ADDR__TAR_ADDR__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN1_TAR_ADDR__TAR_ADDR__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN1_TAR_ADDR__TAR_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_DMA_CHAN1_TAR_ADDR__TAR_ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_DMA_CHAN1_TAR_ADDR__TAR_ADDR__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN1_TAR_ADDR__TYPE uint32_t +#define AT_DMA_CHAN1_TAR_ADDR__READ 0xffffffffU +#define AT_DMA_CHAN1_TAR_ADDR__WRITE 0xffffffffU +#define AT_DMA_CHAN1_TAR_ADDR__PRESERVED 0x00000000U +#define AT_DMA_CHAN1_TAR_ADDR__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN1_TAR_ADDR_MACRO__ */ + +/** @} end of chan1_tar_addr */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan1_size */ +/** + * @defgroup at_ahb_dma_regs_core_chan1_size chan1_size + * @brief Contains register fields associated with chan1_size. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN1_SIZE_MACRO__ +#define __AT_DMA_CHAN1_SIZE_MACRO__ + +/* macros for field size */ +/** + * @defgroup at_ahb_dma_regs_core_size_field size_field + * @brief macros for field size + * @details payload size in bytes. + * @{ + */ +#define AT_DMA_CHAN1_SIZE__SIZE__SHIFT 0 +#define AT_DMA_CHAN1_SIZE__SIZE__WIDTH 24 +#define AT_DMA_CHAN1_SIZE__SIZE__MASK 0x00ffffffU +#define AT_DMA_CHAN1_SIZE__SIZE__READ(src) ((uint32_t)(src) & 0x00ffffffU) +#define AT_DMA_CHAN1_SIZE__SIZE__WRITE(src) ((uint32_t)(src) & 0x00ffffffU) +#define AT_DMA_CHAN1_SIZE__SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((uint32_t)(src) &\ + 0x00ffffffU) +#define AT_DMA_CHAN1_SIZE__SIZE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00ffffffU))) +#define AT_DMA_CHAN1_SIZE__SIZE__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN1_SIZE__TYPE uint32_t +#define AT_DMA_CHAN1_SIZE__READ 0x00ffffffU +#define AT_DMA_CHAN1_SIZE__WRITE 0x00ffffffU +#define AT_DMA_CHAN1_SIZE__PRESERVED 0x00000000U +#define AT_DMA_CHAN1_SIZE__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN1_SIZE_MACRO__ */ + +/** @} end of chan1_size */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan1_src_ctrl */ +/** + * @defgroup at_ahb_dma_regs_core_chan1_src_ctrl chan1_src_ctrl + * @brief Contains register fields associated with chan1_src_ctrl. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN1_SRC_CTRL_MACRO__ +#define __AT_DMA_CHAN1_SRC_CTRL_MACRO__ + +/* macros for field src_type */ +/** + * @defgroup at_ahb_dma_regs_core_src_type_field src_type_field + * @brief macros for field src_type + * @details 0=mem, 1=fifo, 2=periph master, 3=periph slave + * @{ + */ +#define AT_DMA_CHAN1_SRC_CTRL__SRC_TYPE__SHIFT 0 +#define AT_DMA_CHAN1_SRC_CTRL__SRC_TYPE__WIDTH 2 +#define AT_DMA_CHAN1_SRC_CTRL__SRC_TYPE__MASK 0x00000003U +#define AT_DMA_CHAN1_SRC_CTRL__SRC_TYPE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN1_SRC_CTRL__SRC_TYPE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN1_SRC_CTRL__SRC_TYPE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_CHAN1_SRC_CTRL__SRC_TYPE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_CHAN1_SRC_CTRL__SRC_TYPE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field src_bus_size */ +/** + * @defgroup at_ahb_dma_regs_core_src_bus_size_field src_bus_size_field + * @brief macros for field src_bus_size + * @details the width of fifo. one byte to 4 bytes. + * @{ + */ +#define AT_DMA_CHAN1_SRC_CTRL__SRC_BUS_SIZE__SHIFT 2 +#define AT_DMA_CHAN1_SRC_CTRL__SRC_BUS_SIZE__WIDTH 3 +#define AT_DMA_CHAN1_SRC_CTRL__SRC_BUS_SIZE__MASK 0x0000001cU +#define AT_DMA_CHAN1_SRC_CTRL__SRC_BUS_SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0x0000001cU) >> 2) +#define AT_DMA_CHAN1_SRC_CTRL__SRC_BUS_SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000001cU) +#define AT_DMA_CHAN1_SRC_CTRL__SRC_BUS_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((uint32_t)(src) <<\ + 2) & 0x0000001cU) +#define AT_DMA_CHAN1_SRC_CTRL__SRC_BUS_SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000001cU))) +#define AT_DMA_CHAN1_SRC_CTRL__SRC_BUS_SIZE__RESET_VALUE 0x00000001U +/** @} */ +#define AT_DMA_CHAN1_SRC_CTRL__TYPE uint32_t +#define AT_DMA_CHAN1_SRC_CTRL__READ 0x0000001fU +#define AT_DMA_CHAN1_SRC_CTRL__WRITE 0x0000001fU +#define AT_DMA_CHAN1_SRC_CTRL__PRESERVED 0x00000000U +#define AT_DMA_CHAN1_SRC_CTRL__RESET_VALUE 0x00000004U + +#endif /* __AT_DMA_CHAN1_SRC_CTRL_MACRO__ */ + +/** @} end of chan1_src_ctrl */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan1_tar_ctrl */ +/** + * @defgroup at_ahb_dma_regs_core_chan1_tar_ctrl chan1_tar_ctrl + * @brief Contains register fields associated with chan1_tar_ctrl. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN1_TAR_CTRL_MACRO__ +#define __AT_DMA_CHAN1_TAR_CTRL_MACRO__ + +/* macros for field tar_type */ +/** + * @defgroup at_ahb_dma_regs_core_tar_type_field tar_type_field + * @brief macros for field tar_type + * @details 0=mem, 1=fifo, 2=periph master, 3=periph slave + * @{ + */ +#define AT_DMA_CHAN1_TAR_CTRL__TAR_TYPE__SHIFT 0 +#define AT_DMA_CHAN1_TAR_CTRL__TAR_TYPE__WIDTH 2 +#define AT_DMA_CHAN1_TAR_CTRL__TAR_TYPE__MASK 0x00000003U +#define AT_DMA_CHAN1_TAR_CTRL__TAR_TYPE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN1_TAR_CTRL__TAR_TYPE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN1_TAR_CTRL__TAR_TYPE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_CHAN1_TAR_CTRL__TAR_TYPE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_CHAN1_TAR_CTRL__TAR_TYPE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tar_bus_size */ +/** + * @defgroup at_ahb_dma_regs_core_tar_bus_size_field tar_bus_size_field + * @brief macros for field tar_bus_size + * @details the width of fifo. one byte to 4 bytes. + * @{ + */ +#define AT_DMA_CHAN1_TAR_CTRL__TAR_BUS_SIZE__SHIFT 2 +#define AT_DMA_CHAN1_TAR_CTRL__TAR_BUS_SIZE__WIDTH 3 +#define AT_DMA_CHAN1_TAR_CTRL__TAR_BUS_SIZE__MASK 0x0000001cU +#define AT_DMA_CHAN1_TAR_CTRL__TAR_BUS_SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0x0000001cU) >> 2) +#define AT_DMA_CHAN1_TAR_CTRL__TAR_BUS_SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000001cU) +#define AT_DMA_CHAN1_TAR_CTRL__TAR_BUS_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((uint32_t)(src) <<\ + 2) & 0x0000001cU) +#define AT_DMA_CHAN1_TAR_CTRL__TAR_BUS_SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000001cU))) +#define AT_DMA_CHAN1_TAR_CTRL__TAR_BUS_SIZE__RESET_VALUE 0x00000001U +/** @} */ +#define AT_DMA_CHAN1_TAR_CTRL__TYPE uint32_t +#define AT_DMA_CHAN1_TAR_CTRL__READ 0x0000001fU +#define AT_DMA_CHAN1_TAR_CTRL__WRITE 0x0000001fU +#define AT_DMA_CHAN1_TAR_CTRL__PRESERVED 0x00000000U +#define AT_DMA_CHAN1_TAR_CTRL__RESET_VALUE 0x00000004U + +#endif /* __AT_DMA_CHAN1_TAR_CTRL_MACRO__ */ + +/** @} end of chan1_tar_ctrl */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan1_fifo_dpth_addr */ +/** + * @defgroup at_ahb_dma_regs_core_chan1_fifo_dpth_addr chan1_fifo_dpth_addr + * @brief Contains register fields associated with chan1_fifo_dpth_addr. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN1_FIFO_DPTH_ADDR_MACRO__ +#define __AT_DMA_CHAN1_FIFO_DPTH_ADDR_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_ahb_dma_regs_core_addr_field addr_field + * @brief macros for field addr + * @details address of the external fifo depth. Statemachine reads this to determine how many push/pull accesses to do per interrupt. + * @{ + */ +#define AT_DMA_CHAN1_FIFO_DPTH_ADDR__ADDR__SHIFT 0 +#define AT_DMA_CHAN1_FIFO_DPTH_ADDR__ADDR__WIDTH 32 +#define AT_DMA_CHAN1_FIFO_DPTH_ADDR__ADDR__MASK 0xffffffffU +#define AT_DMA_CHAN1_FIFO_DPTH_ADDR__ADDR__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN1_FIFO_DPTH_ADDR__ADDR__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN1_FIFO_DPTH_ADDR__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_DMA_CHAN1_FIFO_DPTH_ADDR__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_DMA_CHAN1_FIFO_DPTH_ADDR__ADDR__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN1_FIFO_DPTH_ADDR__TYPE uint32_t +#define AT_DMA_CHAN1_FIFO_DPTH_ADDR__READ 0xffffffffU +#define AT_DMA_CHAN1_FIFO_DPTH_ADDR__WRITE 0xffffffffU +#define AT_DMA_CHAN1_FIFO_DPTH_ADDR__PRESERVED 0x00000000U +#define AT_DMA_CHAN1_FIFO_DPTH_ADDR__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN1_FIFO_DPTH_ADDR_MACRO__ */ + +/** @} end of chan1_fifo_dpth_addr */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan1_fifo_port_sel */ +/** + * @defgroup at_ahb_dma_regs_core_chan1_fifo_port_sel chan1_fifo_port_sel + * @brief Contains register fields associated with chan1_fifo_port_sel. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN1_FIFO_PORT_SEL_MACRO__ +#define __AT_DMA_CHAN1_FIFO_PORT_SEL_MACRO__ + +/* macros for field src_port_sel */ +/** + * @defgroup at_ahb_dma_regs_core_src_port_sel_field src_port_sel_field + * @brief macros for field src_port_sel + * @details selecting the source fifo port; 5 = rsvd 4 = i2s fifo 3 = pdm1 fifo 2 = pdm0 fifo 1 = uart1 rx 0 = uart0 rx + * @{ + */ +#define AT_DMA_CHAN1_FIFO_PORT_SEL__SRC_PORT_SEL__SHIFT 0 +#define AT_DMA_CHAN1_FIFO_PORT_SEL__SRC_PORT_SEL__WIDTH 3 +#define AT_DMA_CHAN1_FIFO_PORT_SEL__SRC_PORT_SEL__MASK 0x00000007U +#define AT_DMA_CHAN1_FIFO_PORT_SEL__SRC_PORT_SEL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define AT_DMA_CHAN1_FIFO_PORT_SEL__SRC_PORT_SEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define AT_DMA_CHAN1_FIFO_PORT_SEL__SRC_PORT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define AT_DMA_CHAN1_FIFO_PORT_SEL__SRC_PORT_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define AT_DMA_CHAN1_FIFO_PORT_SEL__SRC_PORT_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tar_port_sel */ +/** + * @defgroup at_ahb_dma_regs_core_tar_port_sel_field tar_port_sel_field + * @brief macros for field tar_port_sel + * @details selecting the target fifo port; 5 = pwd fifo 4 = i2s fifo 3 = rsvd 2 = rsvd 1 = uart1 tx 0 = uart0 tx + * @{ + */ +#define AT_DMA_CHAN1_FIFO_PORT_SEL__TAR_PORT_SEL__SHIFT 16 +#define AT_DMA_CHAN1_FIFO_PORT_SEL__TAR_PORT_SEL__WIDTH 3 +#define AT_DMA_CHAN1_FIFO_PORT_SEL__TAR_PORT_SEL__MASK 0x00070000U +#define AT_DMA_CHAN1_FIFO_PORT_SEL__TAR_PORT_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00070000U) >> 16) +#define AT_DMA_CHAN1_FIFO_PORT_SEL__TAR_PORT_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00070000U) +#define AT_DMA_CHAN1_FIFO_PORT_SEL__TAR_PORT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((uint32_t)(src) <<\ + 16) & 0x00070000U) +#define AT_DMA_CHAN1_FIFO_PORT_SEL__TAR_PORT_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00070000U))) +#define AT_DMA_CHAN1_FIFO_PORT_SEL__TAR_PORT_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN1_FIFO_PORT_SEL__TYPE uint32_t +#define AT_DMA_CHAN1_FIFO_PORT_SEL__READ 0x00070007U +#define AT_DMA_CHAN1_FIFO_PORT_SEL__WRITE 0x00070007U +#define AT_DMA_CHAN1_FIFO_PORT_SEL__PRESERVED 0x00000000U +#define AT_DMA_CHAN1_FIFO_PORT_SEL__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN1_FIFO_PORT_SEL_MACRO__ */ + +/** @} end of chan1_fifo_port_sel */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan1_spi_port_sel */ +/** + * @defgroup at_ahb_dma_regs_core_chan1_spi_port_sel chan1_spi_port_sel + * @brief Contains register fields associated with chan1_spi_port_sel. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN1_SPI_PORT_SEL_MACRO__ +#define __AT_DMA_CHAN1_SPI_PORT_SEL_MACRO__ + +/* macros for field spi_sel */ +/** + * @defgroup at_ahb_dma_regs_core_spi_sel_field spi_sel_field + * @brief macros for field spi_sel + * @details 1=select spi1 for this channel, 0=select spi0 for this channel. + * @{ + */ +#define AT_DMA_CHAN1_SPI_PORT_SEL__SPI_SEL__SHIFT 0 +#define AT_DMA_CHAN1_SPI_PORT_SEL__SPI_SEL__WIDTH 1 +#define AT_DMA_CHAN1_SPI_PORT_SEL__SPI_SEL__MASK 0x00000001U +#define AT_DMA_CHAN1_SPI_PORT_SEL__SPI_SEL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN1_SPI_PORT_SEL__SPI_SEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN1_SPI_PORT_SEL__SPI_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AT_DMA_CHAN1_SPI_PORT_SEL__SPI_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AT_DMA_CHAN1_SPI_PORT_SEL__SPI_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_CHAN1_SPI_PORT_SEL__SPI_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_CHAN1_SPI_PORT_SEL__SPI_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN1_SPI_PORT_SEL__TYPE uint32_t +#define AT_DMA_CHAN1_SPI_PORT_SEL__READ 0x00000001U +#define AT_DMA_CHAN1_SPI_PORT_SEL__WRITE 0x00000001U +#define AT_DMA_CHAN1_SPI_PORT_SEL__PRESERVED 0x00000000U +#define AT_DMA_CHAN1_SPI_PORT_SEL__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN1_SPI_PORT_SEL_MACRO__ */ + +/** @} end of chan1_spi_port_sel */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan1_err_stat */ +/** + * @defgroup at_ahb_dma_regs_core_chan1_err_stat chan1_err_stat + * @brief The status is cleared when the err interrupt is cleared definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN1_ERR_STAT_MACRO__ +#define __AT_DMA_CHAN1_ERR_STAT_MACRO__ + +/* macros for field size_0 */ +/** + * @defgroup at_ahb_dma_regs_core_size_0_field size_0_field + * @brief macros for field size_0 + * @details 0= size is not 0 when go is launched, 1= size is 0 when go is launched. + * @{ + */ +#define AT_DMA_CHAN1_ERR_STAT__SIZE_0__SHIFT 0 +#define AT_DMA_CHAN1_ERR_STAT__SIZE_0__WIDTH 1 +#define AT_DMA_CHAN1_ERR_STAT__SIZE_0__MASK 0x00000001U +#define AT_DMA_CHAN1_ERR_STAT__SIZE_0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN1_ERR_STAT__SIZE_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_CHAN1_ERR_STAT__SIZE_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_CHAN1_ERR_STAT__SIZE_0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field addr_ovlp */ +/** + * @defgroup at_ahb_dma_regs_core_addr_ovlp_field addr_ovlp_field + * @brief macros for field addr_ovlp + * @details 0= no overlap between src and tar addr range, 1= there is an overlap + * @{ + */ +#define AT_DMA_CHAN1_ERR_STAT__ADDR_OVLP__SHIFT 1 +#define AT_DMA_CHAN1_ERR_STAT__ADDR_OVLP__WIDTH 1 +#define AT_DMA_CHAN1_ERR_STAT__ADDR_OVLP__MASK 0x00000002U +#define AT_DMA_CHAN1_ERR_STAT__ADDR_OVLP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_DMA_CHAN1_ERR_STAT__ADDR_OVLP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_DMA_CHAN1_ERR_STAT__ADDR_OVLP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_DMA_CHAN1_ERR_STAT__ADDR_OVLP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bus_err */ +/** + * @defgroup at_ahb_dma_regs_core_bus_err_field bus_err_field + * @brief macros for field bus_err + * @details 0= no bus error, 1= a bus error occur during the transfer or at the launch of 'go'. + * @{ + */ +#define AT_DMA_CHAN1_ERR_STAT__BUS_ERR__SHIFT 2 +#define AT_DMA_CHAN1_ERR_STAT__BUS_ERR__WIDTH 1 +#define AT_DMA_CHAN1_ERR_STAT__BUS_ERR__MASK 0x00000004U +#define AT_DMA_CHAN1_ERR_STAT__BUS_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define AT_DMA_CHAN1_ERR_STAT__BUS_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define AT_DMA_CHAN1_ERR_STAT__BUS_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define AT_DMA_CHAN1_ERR_STAT__BUS_ERR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field addr_ovfl */ +/** + * @defgroup at_ahb_dma_regs_core_addr_ovfl_field addr_ovfl_field + * @brief macros for field addr_ovfl + * @details 0= no error, 1= error due to size + src_addr/tar_addr > 32'hffff_ffff. + * @{ + */ +#define AT_DMA_CHAN1_ERR_STAT__ADDR_OVFL__SHIFT 3 +#define AT_DMA_CHAN1_ERR_STAT__ADDR_OVFL__WIDTH 1 +#define AT_DMA_CHAN1_ERR_STAT__ADDR_OVFL__MASK 0x00000008U +#define AT_DMA_CHAN1_ERR_STAT__ADDR_OVFL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define AT_DMA_CHAN1_ERR_STAT__ADDR_OVFL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define AT_DMA_CHAN1_ERR_STAT__ADDR_OVFL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define AT_DMA_CHAN1_ERR_STAT__ADDR_OVFL__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN1_ERR_STAT__TYPE uint32_t +#define AT_DMA_CHAN1_ERR_STAT__READ 0x0000000fU +#define AT_DMA_CHAN1_ERR_STAT__PRESERVED 0x00000000U +#define AT_DMA_CHAN1_ERR_STAT__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN1_ERR_STAT_MACRO__ */ + +/** @} end of chan1_err_stat */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan1_status */ +/** + * @defgroup at_ahb_dma_regs_core_chan1_status chan1_status + * @brief Contains register fields associated with chan1_status. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN1_STATUS_MACRO__ +#define __AT_DMA_CHAN1_STATUS_MACRO__ + +/* macros for field running */ +/** + * @defgroup at_ahb_dma_regs_core_running_field running_field + * @brief macros for field running + * @details fsm is in an active state, not waiting for the bus or an interrupt. + * @{ + */ +#define AT_DMA_CHAN1_STATUS__RUNNING__SHIFT 0 +#define AT_DMA_CHAN1_STATUS__RUNNING__WIDTH 1 +#define AT_DMA_CHAN1_STATUS__RUNNING__MASK 0x00000001U +#define AT_DMA_CHAN1_STATUS__RUNNING__READ(src) ((uint32_t)(src) & 0x00000001U) +#define AT_DMA_CHAN1_STATUS__RUNNING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_CHAN1_STATUS__RUNNING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_CHAN1_STATUS__RUNNING__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field busy */ +/** + * @defgroup at_ahb_dma_regs_core_busy_field busy_field + * @brief macros for field busy + * @details fsm is in some non-idle state including waiting for the bus or an interrupt. + * @{ + */ +#define AT_DMA_CHAN1_STATUS__BUSY__SHIFT 1 +#define AT_DMA_CHAN1_STATUS__BUSY__WIDTH 1 +#define AT_DMA_CHAN1_STATUS__BUSY__MASK 0x00000002U +#define AT_DMA_CHAN1_STATUS__BUSY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_DMA_CHAN1_STATUS__BUSY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_DMA_CHAN1_STATUS__BUSY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_DMA_CHAN1_STATUS__BUSY__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN1_STATUS__TYPE uint32_t +#define AT_DMA_CHAN1_STATUS__READ 0x00000003U +#define AT_DMA_CHAN1_STATUS__PRESERVED 0x00000000U +#define AT_DMA_CHAN1_STATUS__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN1_STATUS_MACRO__ */ + +/** @} end of chan1_status */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan1_total_write_remainder */ +/** + * @defgroup at_ahb_dma_regs_core_chan1_total_write_remainder chan1_total_write_remainder + * @brief Contains register fields associated with chan1_total_write_remainder. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN1_TOTAL_WRITE_REMAINDER_MACRO__ +#define __AT_DMA_CHAN1_TOTAL_WRITE_REMAINDER_MACRO__ + +/* macros for field total_write_remainder */ +/** + * @defgroup at_ahb_dma_regs_core_total_write_remainder_field total_write_remainder_field + * @brief macros for field total_write_remainder + * @details number of bytes left to write at the time of stop + * @{ + */ +#define AT_DMA_CHAN1_TOTAL_WRITE_REMAINDER__TOTAL_WRITE_REMAINDER__SHIFT 0 +#define AT_DMA_CHAN1_TOTAL_WRITE_REMAINDER__TOTAL_WRITE_REMAINDER__WIDTH 24 +#define AT_DMA_CHAN1_TOTAL_WRITE_REMAINDER__TOTAL_WRITE_REMAINDER__MASK \ + 0x00ffffffU +#define AT_DMA_CHAN1_TOTAL_WRITE_REMAINDER__TOTAL_WRITE_REMAINDER__READ(src) \ + ((uint32_t)(src)\ + & 0x00ffffffU) +#define AT_DMA_CHAN1_TOTAL_WRITE_REMAINDER__TOTAL_WRITE_REMAINDER__RESET_VALUE \ + 0x00000000U +/** @} */ +#define AT_DMA_CHAN1_TOTAL_WRITE_REMAINDER__TYPE uint32_t +#define AT_DMA_CHAN1_TOTAL_WRITE_REMAINDER__READ 0x00ffffffU +#define AT_DMA_CHAN1_TOTAL_WRITE_REMAINDER__PRESERVED 0x00000000U +#define AT_DMA_CHAN1_TOTAL_WRITE_REMAINDER__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN1_TOTAL_WRITE_REMAINDER_MACRO__ */ + +/** @} end of chan1_total_write_remainder */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan1_interrupt_status */ +/** + * @defgroup at_ahb_dma_regs_core_chan1_interrupt_status chan1_interrupt_status + * @brief Contains register fields associated with chan1_interrupt_status. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN1_INTERRUPT_STATUS_MACRO__ +#define __AT_DMA_CHAN1_INTERRUPT_STATUS_MACRO__ + +/* macros for field dma_done */ +/** + * @defgroup at_ahb_dma_regs_core_dma_done_field dma_done_field + * @brief macros for field dma_done + * @details source of interrupt due to completion (chan0). + * @{ + */ +#define AT_DMA_CHAN1_INTERRUPT_STATUS__DMA_DONE__SHIFT 0 +#define AT_DMA_CHAN1_INTERRUPT_STATUS__DMA_DONE__WIDTH 1 +#define AT_DMA_CHAN1_INTERRUPT_STATUS__DMA_DONE__MASK 0x00000001U +#define AT_DMA_CHAN1_INTERRUPT_STATUS__DMA_DONE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN1_INTERRUPT_STATUS__DMA_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_CHAN1_INTERRUPT_STATUS__DMA_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_CHAN1_INTERRUPT_STATUS__DMA_DONE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dma_err */ +/** + * @defgroup at_ahb_dma_regs_core_dma_err_field dma_err_field + * @brief macros for field dma_err + * @details source of interrupt due to an error (chan0). + * @{ + */ +#define AT_DMA_CHAN1_INTERRUPT_STATUS__DMA_ERR__SHIFT 1 +#define AT_DMA_CHAN1_INTERRUPT_STATUS__DMA_ERR__WIDTH 1 +#define AT_DMA_CHAN1_INTERRUPT_STATUS__DMA_ERR__MASK 0x00000002U +#define AT_DMA_CHAN1_INTERRUPT_STATUS__DMA_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_DMA_CHAN1_INTERRUPT_STATUS__DMA_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_DMA_CHAN1_INTERRUPT_STATUS__DMA_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_DMA_CHAN1_INTERRUPT_STATUS__DMA_ERR__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN1_INTERRUPT_STATUS__TYPE uint32_t +#define AT_DMA_CHAN1_INTERRUPT_STATUS__READ 0x00000003U +#define AT_DMA_CHAN1_INTERRUPT_STATUS__PRESERVED 0x00000000U +#define AT_DMA_CHAN1_INTERRUPT_STATUS__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN1_INTERRUPT_STATUS_MACRO__ */ + +/** @} end of chan1_interrupt_status */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan1_interrupt_mask */ +/** + * @defgroup at_ahb_dma_regs_core_chan1_interrupt_mask chan1_interrupt_mask + * @brief Contains register fields associated with chan1_interrupt_mask. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN1_INTERRUPT_MASK_MACRO__ +#define __AT_DMA_CHAN1_INTERRUPT_MASK_MACRO__ + +/* macros for field intrpt_mask */ +/** + * @defgroup at_ahb_dma_regs_core_intrpt_mask_field intrpt_mask_field + * @brief macros for field intrpt_mask + * @details if nth bit set, the nth interrupt is enabled + * @{ + */ +#define AT_DMA_CHAN1_INTERRUPT_MASK__INTRPT_MASK__SHIFT 0 +#define AT_DMA_CHAN1_INTERRUPT_MASK__INTRPT_MASK__WIDTH 2 +#define AT_DMA_CHAN1_INTERRUPT_MASK__INTRPT_MASK__MASK 0x00000003U +#define AT_DMA_CHAN1_INTERRUPT_MASK__INTRPT_MASK__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN1_INTERRUPT_MASK__INTRPT_MASK__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN1_INTERRUPT_MASK__INTRPT_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_CHAN1_INTERRUPT_MASK__INTRPT_MASK__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_CHAN1_INTERRUPT_MASK__INTRPT_MASK__RESET_VALUE 0x00000001U +/** @} */ +#define AT_DMA_CHAN1_INTERRUPT_MASK__TYPE uint32_t +#define AT_DMA_CHAN1_INTERRUPT_MASK__READ 0x00000003U +#define AT_DMA_CHAN1_INTERRUPT_MASK__WRITE 0x00000003U +#define AT_DMA_CHAN1_INTERRUPT_MASK__PRESERVED 0x00000000U +#define AT_DMA_CHAN1_INTERRUPT_MASK__RESET_VALUE 0x00000001U + +#endif /* __AT_DMA_CHAN1_INTERRUPT_MASK_MACRO__ */ + +/** @} end of chan1_interrupt_mask */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan1_set_interrupt */ +/** + * @defgroup at_ahb_dma_regs_core_chan1_set_interrupt chan1_set_interrupt + * @brief Contains register fields associated with chan1_set_interrupt. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN1_SET_INTERRUPT_MACRO__ +#define __AT_DMA_CHAN1_SET_INTERRUPT_MACRO__ + +/* macros for field intrpt_set */ +/** + * @defgroup at_ahb_dma_regs_core_intrpt_set_field intrpt_set_field + * @brief macros for field intrpt_set + * @details if nth bit set, the nth interrupt is set; HW clears all bits the next cycle. + * @{ + */ +#define AT_DMA_CHAN1_SET_INTERRUPT__INTRPT_SET__SHIFT 0 +#define AT_DMA_CHAN1_SET_INTERRUPT__INTRPT_SET__WIDTH 2 +#define AT_DMA_CHAN1_SET_INTERRUPT__INTRPT_SET__MASK 0x00000003U +#define AT_DMA_CHAN1_SET_INTERRUPT__INTRPT_SET__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN1_SET_INTERRUPT__INTRPT_SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN1_SET_INTERRUPT__INTRPT_SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_CHAN1_SET_INTERRUPT__INTRPT_SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_CHAN1_SET_INTERRUPT__INTRPT_SET__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN1_SET_INTERRUPT__TYPE uint32_t +#define AT_DMA_CHAN1_SET_INTERRUPT__READ 0x00000003U +#define AT_DMA_CHAN1_SET_INTERRUPT__WRITE 0x00000003U +#define AT_DMA_CHAN1_SET_INTERRUPT__PRESERVED 0x00000000U +#define AT_DMA_CHAN1_SET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN1_SET_INTERRUPT_MACRO__ */ + +/** @} end of chan1_set_interrupt */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan1_reset_interrupt */ +/** + * @defgroup at_ahb_dma_regs_core_chan1_reset_interrupt chan1_reset_interrupt + * @brief Contains register fields associated with chan1_reset_interrupt. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN1_RESET_INTERRUPT_MACRO__ +#define __AT_DMA_CHAN1_RESET_INTERRUPT_MACRO__ + +/* macros for field intrpt_reset */ +/** + * @defgroup at_ahb_dma_regs_core_intrpt_reset_field intrpt_reset_field + * @brief macros for field intrpt_reset + * @details if nth bit set, the nth interrupt is reset; HW clears all bits the next cycle. + * @{ + */ +#define AT_DMA_CHAN1_RESET_INTERRUPT__INTRPT_RESET__SHIFT 0 +#define AT_DMA_CHAN1_RESET_INTERRUPT__INTRPT_RESET__WIDTH 2 +#define AT_DMA_CHAN1_RESET_INTERRUPT__INTRPT_RESET__MASK 0x00000003U +#define AT_DMA_CHAN1_RESET_INTERRUPT__INTRPT_RESET__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN1_RESET_INTERRUPT__INTRPT_RESET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN1_RESET_INTERRUPT__INTRPT_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_CHAN1_RESET_INTERRUPT__INTRPT_RESET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_CHAN1_RESET_INTERRUPT__INTRPT_RESET__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN1_RESET_INTERRUPT__TYPE uint32_t +#define AT_DMA_CHAN1_RESET_INTERRUPT__READ 0x00000003U +#define AT_DMA_CHAN1_RESET_INTERRUPT__WRITE 0x00000003U +#define AT_DMA_CHAN1_RESET_INTERRUPT__PRESERVED 0x00000000U +#define AT_DMA_CHAN1_RESET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN1_RESET_INTERRUPT_MACRO__ */ + +/** @} end of chan1_reset_interrupt */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan1_cfg_hnonsec */ +/** + * @defgroup at_ahb_dma_regs_core_chan1_cfg_hnonsec chan1_cfg_hnonsec + * @brief Contains register fields associated with chan1_cfg_hnonsec. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN1_CFG_HNONSEC_MACRO__ +#define __AT_DMA_CHAN1_CFG_HNONSEC_MACRO__ + +/* macros for field cfg_hnonsec */ +/** + * @defgroup at_ahb_dma_regs_core_cfg_hnonsec_field cfg_hnonsec_field + * @brief macros for field cfg_hnonsec + * @details control HNONSEC output signal of this channel. This register is only Write-able by Secure program. + * @{ + */ +#define AT_DMA_CHAN1_CFG_HNONSEC__CFG_HNONSEC__SHIFT 0 +#define AT_DMA_CHAN1_CFG_HNONSEC__CFG_HNONSEC__WIDTH 1 +#define AT_DMA_CHAN1_CFG_HNONSEC__CFG_HNONSEC__MASK 0x00000001U +#define AT_DMA_CHAN1_CFG_HNONSEC__CFG_HNONSEC__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN1_CFG_HNONSEC__CFG_HNONSEC__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN1_CFG_HNONSEC__CFG_HNONSEC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AT_DMA_CHAN1_CFG_HNONSEC__CFG_HNONSEC__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AT_DMA_CHAN1_CFG_HNONSEC__CFG_HNONSEC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_CHAN1_CFG_HNONSEC__CFG_HNONSEC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_CHAN1_CFG_HNONSEC__CFG_HNONSEC__RESET_VALUE 0x00000001U +/** @} */ +#define AT_DMA_CHAN1_CFG_HNONSEC__TYPE uint32_t +#define AT_DMA_CHAN1_CFG_HNONSEC__READ 0x00000001U +#define AT_DMA_CHAN1_CFG_HNONSEC__WRITE 0x00000001U +#define AT_DMA_CHAN1_CFG_HNONSEC__PRESERVED 0x00000000U +#define AT_DMA_CHAN1_CFG_HNONSEC__RESET_VALUE 0x00000001U + +#endif /* __AT_DMA_CHAN1_CFG_HNONSEC_MACRO__ */ + +/** @} end of chan1_cfg_hnonsec */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan2_opmode */ +/** + * @defgroup at_ahb_dma_regs_core_chan2_opmode chan2_opmode + * @brief Contains register fields associated with chan2_opmode. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN2_OPMODE_MACRO__ +#define __AT_DMA_CHAN2_OPMODE_MACRO__ + +/* macros for field const_trans */ +/** + * @defgroup at_ahb_dma_regs_core_const_trans_field const_trans_field + * @brief macros for field const_trans + * @details op code start when rising edge on 'go' is detected. + * @{ + */ +#define AT_DMA_CHAN2_OPMODE__CONST_TRANS__SHIFT 0 +#define AT_DMA_CHAN2_OPMODE__CONST_TRANS__WIDTH 1 +#define AT_DMA_CHAN2_OPMODE__CONST_TRANS__MASK 0x00000001U +#define AT_DMA_CHAN2_OPMODE__CONST_TRANS__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN2_OPMODE__CONST_TRANS__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN2_OPMODE__CONST_TRANS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AT_DMA_CHAN2_OPMODE__CONST_TRANS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AT_DMA_CHAN2_OPMODE__CONST_TRANS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_CHAN2_OPMODE__CONST_TRANS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_CHAN2_OPMODE__CONST_TRANS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dat_inv */ +/** + * @defgroup at_ahb_dma_regs_core_dat_inv_field dat_inv_field + * @brief macros for field dat_inv + * @details 0= non-inverted write ; 1= inverted write (write data are bit-wise inverted) + * @{ + */ +#define AT_DMA_CHAN2_OPMODE__DAT_INV__SHIFT 1 +#define AT_DMA_CHAN2_OPMODE__DAT_INV__WIDTH 1 +#define AT_DMA_CHAN2_OPMODE__DAT_INV__MASK 0x00000002U +#define AT_DMA_CHAN2_OPMODE__DAT_INV__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_DMA_CHAN2_OPMODE__DAT_INV__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define AT_DMA_CHAN2_OPMODE__DAT_INV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define AT_DMA_CHAN2_OPMODE__DAT_INV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define AT_DMA_CHAN2_OPMODE__DAT_INV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_DMA_CHAN2_OPMODE__DAT_INV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_DMA_CHAN2_OPMODE__DAT_INV__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field const_tar_addr */ +/** + * @defgroup at_ahb_dma_regs_core_const_tar_addr_field const_tar_addr_field + * @brief macros for field const_tar_addr + * @details 1= write address remains constant at tar_addr, which is required to be word-aligned in this mode. 0= write address increments as defined by the size parameter. + * @{ + */ +#define AT_DMA_CHAN2_OPMODE__CONST_TAR_ADDR__SHIFT 2 +#define AT_DMA_CHAN2_OPMODE__CONST_TAR_ADDR__WIDTH 1 +#define AT_DMA_CHAN2_OPMODE__CONST_TAR_ADDR__MASK 0x00000004U +#define AT_DMA_CHAN2_OPMODE__CONST_TAR_ADDR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define AT_DMA_CHAN2_OPMODE__CONST_TAR_ADDR__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define AT_DMA_CHAN2_OPMODE__CONST_TAR_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define AT_DMA_CHAN2_OPMODE__CONST_TAR_ADDR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define AT_DMA_CHAN2_OPMODE__CONST_TAR_ADDR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define AT_DMA_CHAN2_OPMODE__CONST_TAR_ADDR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define AT_DMA_CHAN2_OPMODE__CONST_TAR_ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field stop */ +/** + * @defgroup at_ahb_dma_regs_core_stop_field stop_field + * @brief macros for field stop + * @details to stop pending transaction . Not self clearing. + * @{ + */ +#define AT_DMA_CHAN2_OPMODE__STOP__SHIFT 30 +#define AT_DMA_CHAN2_OPMODE__STOP__WIDTH 1 +#define AT_DMA_CHAN2_OPMODE__STOP__MASK 0x40000000U +#define AT_DMA_CHAN2_OPMODE__STOP__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define AT_DMA_CHAN2_OPMODE__STOP__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define AT_DMA_CHAN2_OPMODE__STOP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define AT_DMA_CHAN2_OPMODE__STOP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define AT_DMA_CHAN2_OPMODE__STOP__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define AT_DMA_CHAN2_OPMODE__STOP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define AT_DMA_CHAN2_OPMODE__STOP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field go */ +/** + * @defgroup at_ahb_dma_regs_core_go_field go_field + * @brief macros for field go + * @details op code start when rising edge on 'go' is detected. HW clears after. + * @{ + */ +#define AT_DMA_CHAN2_OPMODE__GO__SHIFT 31 +#define AT_DMA_CHAN2_OPMODE__GO__WIDTH 1 +#define AT_DMA_CHAN2_OPMODE__GO__MASK 0x80000000U +#define AT_DMA_CHAN2_OPMODE__GO__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define AT_DMA_CHAN2_OPMODE__GO__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define AT_DMA_CHAN2_OPMODE__GO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define AT_DMA_CHAN2_OPMODE__GO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define AT_DMA_CHAN2_OPMODE__GO__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define AT_DMA_CHAN2_OPMODE__GO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define AT_DMA_CHAN2_OPMODE__GO__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN2_OPMODE__TYPE uint32_t +#define AT_DMA_CHAN2_OPMODE__READ 0xc0000007U +#define AT_DMA_CHAN2_OPMODE__WRITE 0xc0000007U +#define AT_DMA_CHAN2_OPMODE__PRESERVED 0x00000000U +#define AT_DMA_CHAN2_OPMODE__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN2_OPMODE_MACRO__ */ + +/** @} end of chan2_opmode */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan2_const_wdata */ +/** + * @defgroup at_ahb_dma_regs_core_chan2_const_wdata chan2_const_wdata + * @brief Contains register fields associated with chan2_const_wdata. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN2_CONST_WDATA_MACRO__ +#define __AT_DMA_CHAN2_CONST_WDATA_MACRO__ + +/* macros for field const_wdata */ +/** + * @defgroup at_ahb_dma_regs_core_const_wdata_field const_wdata_field + * @brief macros for field const_wdata + * @details constant value to be written to target when the operation is in const_trans mode. + * @{ + */ +#define AT_DMA_CHAN2_CONST_WDATA__CONST_WDATA__SHIFT 0 +#define AT_DMA_CHAN2_CONST_WDATA__CONST_WDATA__WIDTH 32 +#define AT_DMA_CHAN2_CONST_WDATA__CONST_WDATA__MASK 0xffffffffU +#define AT_DMA_CHAN2_CONST_WDATA__CONST_WDATA__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN2_CONST_WDATA__CONST_WDATA__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN2_CONST_WDATA__CONST_WDATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_DMA_CHAN2_CONST_WDATA__CONST_WDATA__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_DMA_CHAN2_CONST_WDATA__CONST_WDATA__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN2_CONST_WDATA__TYPE uint32_t +#define AT_DMA_CHAN2_CONST_WDATA__READ 0xffffffffU +#define AT_DMA_CHAN2_CONST_WDATA__WRITE 0xffffffffU +#define AT_DMA_CHAN2_CONST_WDATA__PRESERVED 0x00000000U +#define AT_DMA_CHAN2_CONST_WDATA__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN2_CONST_WDATA_MACRO__ */ + +/** @} end of chan2_const_wdata */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan2_src_addr */ +/** + * @defgroup at_ahb_dma_regs_core_chan2_src_addr chan2_src_addr + * @brief Contains register fields associated with chan2_src_addr. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN2_SRC_ADDR_MACRO__ +#define __AT_DMA_CHAN2_SRC_ADDR_MACRO__ + +/* macros for field src_addr */ +/** + * @defgroup at_ahb_dma_regs_core_src_addr_field src_addr_field + * @brief macros for field src_addr + * @details source address + * @{ + */ +#define AT_DMA_CHAN2_SRC_ADDR__SRC_ADDR__SHIFT 0 +#define AT_DMA_CHAN2_SRC_ADDR__SRC_ADDR__WIDTH 32 +#define AT_DMA_CHAN2_SRC_ADDR__SRC_ADDR__MASK 0xffffffffU +#define AT_DMA_CHAN2_SRC_ADDR__SRC_ADDR__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN2_SRC_ADDR__SRC_ADDR__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN2_SRC_ADDR__SRC_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_DMA_CHAN2_SRC_ADDR__SRC_ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_DMA_CHAN2_SRC_ADDR__SRC_ADDR__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN2_SRC_ADDR__TYPE uint32_t +#define AT_DMA_CHAN2_SRC_ADDR__READ 0xffffffffU +#define AT_DMA_CHAN2_SRC_ADDR__WRITE 0xffffffffU +#define AT_DMA_CHAN2_SRC_ADDR__PRESERVED 0x00000000U +#define AT_DMA_CHAN2_SRC_ADDR__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN2_SRC_ADDR_MACRO__ */ + +/** @} end of chan2_src_addr */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan2_tar_addr */ +/** + * @defgroup at_ahb_dma_regs_core_chan2_tar_addr chan2_tar_addr + * @brief Contains register fields associated with chan2_tar_addr. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN2_TAR_ADDR_MACRO__ +#define __AT_DMA_CHAN2_TAR_ADDR_MACRO__ + +/* macros for field tar_addr */ +/** + * @defgroup at_ahb_dma_regs_core_tar_addr_field tar_addr_field + * @brief macros for field tar_addr + * @details target address + * @{ + */ +#define AT_DMA_CHAN2_TAR_ADDR__TAR_ADDR__SHIFT 0 +#define AT_DMA_CHAN2_TAR_ADDR__TAR_ADDR__WIDTH 32 +#define AT_DMA_CHAN2_TAR_ADDR__TAR_ADDR__MASK 0xffffffffU +#define AT_DMA_CHAN2_TAR_ADDR__TAR_ADDR__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN2_TAR_ADDR__TAR_ADDR__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN2_TAR_ADDR__TAR_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_DMA_CHAN2_TAR_ADDR__TAR_ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_DMA_CHAN2_TAR_ADDR__TAR_ADDR__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN2_TAR_ADDR__TYPE uint32_t +#define AT_DMA_CHAN2_TAR_ADDR__READ 0xffffffffU +#define AT_DMA_CHAN2_TAR_ADDR__WRITE 0xffffffffU +#define AT_DMA_CHAN2_TAR_ADDR__PRESERVED 0x00000000U +#define AT_DMA_CHAN2_TAR_ADDR__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN2_TAR_ADDR_MACRO__ */ + +/** @} end of chan2_tar_addr */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan2_size */ +/** + * @defgroup at_ahb_dma_regs_core_chan2_size chan2_size + * @brief Contains register fields associated with chan2_size. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN2_SIZE_MACRO__ +#define __AT_DMA_CHAN2_SIZE_MACRO__ + +/* macros for field size */ +/** + * @defgroup at_ahb_dma_regs_core_size_field size_field + * @brief macros for field size + * @details payload size in bytes. + * @{ + */ +#define AT_DMA_CHAN2_SIZE__SIZE__SHIFT 0 +#define AT_DMA_CHAN2_SIZE__SIZE__WIDTH 24 +#define AT_DMA_CHAN2_SIZE__SIZE__MASK 0x00ffffffU +#define AT_DMA_CHAN2_SIZE__SIZE__READ(src) ((uint32_t)(src) & 0x00ffffffU) +#define AT_DMA_CHAN2_SIZE__SIZE__WRITE(src) ((uint32_t)(src) & 0x00ffffffU) +#define AT_DMA_CHAN2_SIZE__SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((uint32_t)(src) &\ + 0x00ffffffU) +#define AT_DMA_CHAN2_SIZE__SIZE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00ffffffU))) +#define AT_DMA_CHAN2_SIZE__SIZE__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN2_SIZE__TYPE uint32_t +#define AT_DMA_CHAN2_SIZE__READ 0x00ffffffU +#define AT_DMA_CHAN2_SIZE__WRITE 0x00ffffffU +#define AT_DMA_CHAN2_SIZE__PRESERVED 0x00000000U +#define AT_DMA_CHAN2_SIZE__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN2_SIZE_MACRO__ */ + +/** @} end of chan2_size */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan2_src_ctrl */ +/** + * @defgroup at_ahb_dma_regs_core_chan2_src_ctrl chan2_src_ctrl + * @brief Contains register fields associated with chan2_src_ctrl. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN2_SRC_CTRL_MACRO__ +#define __AT_DMA_CHAN2_SRC_CTRL_MACRO__ + +/* macros for field src_type */ +/** + * @defgroup at_ahb_dma_regs_core_src_type_field src_type_field + * @brief macros for field src_type + * @details 0=mem, 1=fifo, 2=periph master, 3=periph slave + * @{ + */ +#define AT_DMA_CHAN2_SRC_CTRL__SRC_TYPE__SHIFT 0 +#define AT_DMA_CHAN2_SRC_CTRL__SRC_TYPE__WIDTH 2 +#define AT_DMA_CHAN2_SRC_CTRL__SRC_TYPE__MASK 0x00000003U +#define AT_DMA_CHAN2_SRC_CTRL__SRC_TYPE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN2_SRC_CTRL__SRC_TYPE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN2_SRC_CTRL__SRC_TYPE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_CHAN2_SRC_CTRL__SRC_TYPE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_CHAN2_SRC_CTRL__SRC_TYPE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field src_bus_size */ +/** + * @defgroup at_ahb_dma_regs_core_src_bus_size_field src_bus_size_field + * @brief macros for field src_bus_size + * @details the width of fifo. one byte to 4 bytes. + * @{ + */ +#define AT_DMA_CHAN2_SRC_CTRL__SRC_BUS_SIZE__SHIFT 2 +#define AT_DMA_CHAN2_SRC_CTRL__SRC_BUS_SIZE__WIDTH 3 +#define AT_DMA_CHAN2_SRC_CTRL__SRC_BUS_SIZE__MASK 0x0000001cU +#define AT_DMA_CHAN2_SRC_CTRL__SRC_BUS_SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0x0000001cU) >> 2) +#define AT_DMA_CHAN2_SRC_CTRL__SRC_BUS_SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000001cU) +#define AT_DMA_CHAN2_SRC_CTRL__SRC_BUS_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((uint32_t)(src) <<\ + 2) & 0x0000001cU) +#define AT_DMA_CHAN2_SRC_CTRL__SRC_BUS_SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000001cU))) +#define AT_DMA_CHAN2_SRC_CTRL__SRC_BUS_SIZE__RESET_VALUE 0x00000001U +/** @} */ +#define AT_DMA_CHAN2_SRC_CTRL__TYPE uint32_t +#define AT_DMA_CHAN2_SRC_CTRL__READ 0x0000001fU +#define AT_DMA_CHAN2_SRC_CTRL__WRITE 0x0000001fU +#define AT_DMA_CHAN2_SRC_CTRL__PRESERVED 0x00000000U +#define AT_DMA_CHAN2_SRC_CTRL__RESET_VALUE 0x00000004U + +#endif /* __AT_DMA_CHAN2_SRC_CTRL_MACRO__ */ + +/** @} end of chan2_src_ctrl */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan2_tar_ctrl */ +/** + * @defgroup at_ahb_dma_regs_core_chan2_tar_ctrl chan2_tar_ctrl + * @brief Contains register fields associated with chan2_tar_ctrl. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN2_TAR_CTRL_MACRO__ +#define __AT_DMA_CHAN2_TAR_CTRL_MACRO__ + +/* macros for field tar_type */ +/** + * @defgroup at_ahb_dma_regs_core_tar_type_field tar_type_field + * @brief macros for field tar_type + * @details 0=mem, 1=fifo, 2=periph master, 3=periph slave + * @{ + */ +#define AT_DMA_CHAN2_TAR_CTRL__TAR_TYPE__SHIFT 0 +#define AT_DMA_CHAN2_TAR_CTRL__TAR_TYPE__WIDTH 2 +#define AT_DMA_CHAN2_TAR_CTRL__TAR_TYPE__MASK 0x00000003U +#define AT_DMA_CHAN2_TAR_CTRL__TAR_TYPE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN2_TAR_CTRL__TAR_TYPE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN2_TAR_CTRL__TAR_TYPE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_CHAN2_TAR_CTRL__TAR_TYPE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_CHAN2_TAR_CTRL__TAR_TYPE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tar_bus_size */ +/** + * @defgroup at_ahb_dma_regs_core_tar_bus_size_field tar_bus_size_field + * @brief macros for field tar_bus_size + * @details the width of fifo. one byte to 4 bytes. + * @{ + */ +#define AT_DMA_CHAN2_TAR_CTRL__TAR_BUS_SIZE__SHIFT 2 +#define AT_DMA_CHAN2_TAR_CTRL__TAR_BUS_SIZE__WIDTH 3 +#define AT_DMA_CHAN2_TAR_CTRL__TAR_BUS_SIZE__MASK 0x0000001cU +#define AT_DMA_CHAN2_TAR_CTRL__TAR_BUS_SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0x0000001cU) >> 2) +#define AT_DMA_CHAN2_TAR_CTRL__TAR_BUS_SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000001cU) +#define AT_DMA_CHAN2_TAR_CTRL__TAR_BUS_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((uint32_t)(src) <<\ + 2) & 0x0000001cU) +#define AT_DMA_CHAN2_TAR_CTRL__TAR_BUS_SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000001cU))) +#define AT_DMA_CHAN2_TAR_CTRL__TAR_BUS_SIZE__RESET_VALUE 0x00000001U +/** @} */ +#define AT_DMA_CHAN2_TAR_CTRL__TYPE uint32_t +#define AT_DMA_CHAN2_TAR_CTRL__READ 0x0000001fU +#define AT_DMA_CHAN2_TAR_CTRL__WRITE 0x0000001fU +#define AT_DMA_CHAN2_TAR_CTRL__PRESERVED 0x00000000U +#define AT_DMA_CHAN2_TAR_CTRL__RESET_VALUE 0x00000004U + +#endif /* __AT_DMA_CHAN2_TAR_CTRL_MACRO__ */ + +/** @} end of chan2_tar_ctrl */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan2_fifo_dpth_addr */ +/** + * @defgroup at_ahb_dma_regs_core_chan2_fifo_dpth_addr chan2_fifo_dpth_addr + * @brief Contains register fields associated with chan2_fifo_dpth_addr. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN2_FIFO_DPTH_ADDR_MACRO__ +#define __AT_DMA_CHAN2_FIFO_DPTH_ADDR_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_ahb_dma_regs_core_addr_field addr_field + * @brief macros for field addr + * @details address of the external fifo depth. Statemachine reads this to determine how many push/pull accesses to do per interrupt. + * @{ + */ +#define AT_DMA_CHAN2_FIFO_DPTH_ADDR__ADDR__SHIFT 0 +#define AT_DMA_CHAN2_FIFO_DPTH_ADDR__ADDR__WIDTH 32 +#define AT_DMA_CHAN2_FIFO_DPTH_ADDR__ADDR__MASK 0xffffffffU +#define AT_DMA_CHAN2_FIFO_DPTH_ADDR__ADDR__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN2_FIFO_DPTH_ADDR__ADDR__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN2_FIFO_DPTH_ADDR__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_DMA_CHAN2_FIFO_DPTH_ADDR__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_DMA_CHAN2_FIFO_DPTH_ADDR__ADDR__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN2_FIFO_DPTH_ADDR__TYPE uint32_t +#define AT_DMA_CHAN2_FIFO_DPTH_ADDR__READ 0xffffffffU +#define AT_DMA_CHAN2_FIFO_DPTH_ADDR__WRITE 0xffffffffU +#define AT_DMA_CHAN2_FIFO_DPTH_ADDR__PRESERVED 0x00000000U +#define AT_DMA_CHAN2_FIFO_DPTH_ADDR__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN2_FIFO_DPTH_ADDR_MACRO__ */ + +/** @} end of chan2_fifo_dpth_addr */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan2_fifo_port_sel */ +/** + * @defgroup at_ahb_dma_regs_core_chan2_fifo_port_sel chan2_fifo_port_sel + * @brief Contains register fields associated with chan2_fifo_port_sel. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN2_FIFO_PORT_SEL_MACRO__ +#define __AT_DMA_CHAN2_FIFO_PORT_SEL_MACRO__ + +/* macros for field src_port_sel */ +/** + * @defgroup at_ahb_dma_regs_core_src_port_sel_field src_port_sel_field + * @brief macros for field src_port_sel + * @details selecting the source fifo port; 5 = rsvd 4 = i2s fifo 3 = pdm1 fifo 2 = pdm0 fifo 1 = uart1 rx 0 = uart0 rx + * @{ + */ +#define AT_DMA_CHAN2_FIFO_PORT_SEL__SRC_PORT_SEL__SHIFT 0 +#define AT_DMA_CHAN2_FIFO_PORT_SEL__SRC_PORT_SEL__WIDTH 3 +#define AT_DMA_CHAN2_FIFO_PORT_SEL__SRC_PORT_SEL__MASK 0x00000007U +#define AT_DMA_CHAN2_FIFO_PORT_SEL__SRC_PORT_SEL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define AT_DMA_CHAN2_FIFO_PORT_SEL__SRC_PORT_SEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define AT_DMA_CHAN2_FIFO_PORT_SEL__SRC_PORT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define AT_DMA_CHAN2_FIFO_PORT_SEL__SRC_PORT_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define AT_DMA_CHAN2_FIFO_PORT_SEL__SRC_PORT_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tar_port_sel */ +/** + * @defgroup at_ahb_dma_regs_core_tar_port_sel_field tar_port_sel_field + * @brief macros for field tar_port_sel + * @details selecting the target fifo port; 5 = pwd fifo 4 = i2s fifo 3 = rsvd 2 = rsvd 1 = uart1 tx 0 = uart0 tx + * @{ + */ +#define AT_DMA_CHAN2_FIFO_PORT_SEL__TAR_PORT_SEL__SHIFT 16 +#define AT_DMA_CHAN2_FIFO_PORT_SEL__TAR_PORT_SEL__WIDTH 3 +#define AT_DMA_CHAN2_FIFO_PORT_SEL__TAR_PORT_SEL__MASK 0x00070000U +#define AT_DMA_CHAN2_FIFO_PORT_SEL__TAR_PORT_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00070000U) >> 16) +#define AT_DMA_CHAN2_FIFO_PORT_SEL__TAR_PORT_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00070000U) +#define AT_DMA_CHAN2_FIFO_PORT_SEL__TAR_PORT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((uint32_t)(src) <<\ + 16) & 0x00070000U) +#define AT_DMA_CHAN2_FIFO_PORT_SEL__TAR_PORT_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00070000U))) +#define AT_DMA_CHAN2_FIFO_PORT_SEL__TAR_PORT_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN2_FIFO_PORT_SEL__TYPE uint32_t +#define AT_DMA_CHAN2_FIFO_PORT_SEL__READ 0x00070007U +#define AT_DMA_CHAN2_FIFO_PORT_SEL__WRITE 0x00070007U +#define AT_DMA_CHAN2_FIFO_PORT_SEL__PRESERVED 0x00000000U +#define AT_DMA_CHAN2_FIFO_PORT_SEL__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN2_FIFO_PORT_SEL_MACRO__ */ + +/** @} end of chan2_fifo_port_sel */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan2_spi_port_sel */ +/** + * @defgroup at_ahb_dma_regs_core_chan2_spi_port_sel chan2_spi_port_sel + * @brief Contains register fields associated with chan2_spi_port_sel. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN2_SPI_PORT_SEL_MACRO__ +#define __AT_DMA_CHAN2_SPI_PORT_SEL_MACRO__ + +/* macros for field spi_sel */ +/** + * @defgroup at_ahb_dma_regs_core_spi_sel_field spi_sel_field + * @brief macros for field spi_sel + * @details 1=select spi1 for this channel, 0=select spi0 for this channel. + * @{ + */ +#define AT_DMA_CHAN2_SPI_PORT_SEL__SPI_SEL__SHIFT 0 +#define AT_DMA_CHAN2_SPI_PORT_SEL__SPI_SEL__WIDTH 1 +#define AT_DMA_CHAN2_SPI_PORT_SEL__SPI_SEL__MASK 0x00000001U +#define AT_DMA_CHAN2_SPI_PORT_SEL__SPI_SEL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN2_SPI_PORT_SEL__SPI_SEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN2_SPI_PORT_SEL__SPI_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AT_DMA_CHAN2_SPI_PORT_SEL__SPI_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AT_DMA_CHAN2_SPI_PORT_SEL__SPI_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_CHAN2_SPI_PORT_SEL__SPI_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_CHAN2_SPI_PORT_SEL__SPI_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN2_SPI_PORT_SEL__TYPE uint32_t +#define AT_DMA_CHAN2_SPI_PORT_SEL__READ 0x00000001U +#define AT_DMA_CHAN2_SPI_PORT_SEL__WRITE 0x00000001U +#define AT_DMA_CHAN2_SPI_PORT_SEL__PRESERVED 0x00000000U +#define AT_DMA_CHAN2_SPI_PORT_SEL__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN2_SPI_PORT_SEL_MACRO__ */ + +/** @} end of chan2_spi_port_sel */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan2_err_stat */ +/** + * @defgroup at_ahb_dma_regs_core_chan2_err_stat chan2_err_stat + * @brief The status is cleared when the err interrupt is cleared definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN2_ERR_STAT_MACRO__ +#define __AT_DMA_CHAN2_ERR_STAT_MACRO__ + +/* macros for field size_0 */ +/** + * @defgroup at_ahb_dma_regs_core_size_0_field size_0_field + * @brief macros for field size_0 + * @details 0= size is not 0 when go is launched, 1= size is 0 when go is launched. + * @{ + */ +#define AT_DMA_CHAN2_ERR_STAT__SIZE_0__SHIFT 0 +#define AT_DMA_CHAN2_ERR_STAT__SIZE_0__WIDTH 1 +#define AT_DMA_CHAN2_ERR_STAT__SIZE_0__MASK 0x00000001U +#define AT_DMA_CHAN2_ERR_STAT__SIZE_0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN2_ERR_STAT__SIZE_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_CHAN2_ERR_STAT__SIZE_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_CHAN2_ERR_STAT__SIZE_0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field addr_ovlp */ +/** + * @defgroup at_ahb_dma_regs_core_addr_ovlp_field addr_ovlp_field + * @brief macros for field addr_ovlp + * @details 0= no overlap between src and tar addr range, 1= there is an overlap + * @{ + */ +#define AT_DMA_CHAN2_ERR_STAT__ADDR_OVLP__SHIFT 1 +#define AT_DMA_CHAN2_ERR_STAT__ADDR_OVLP__WIDTH 1 +#define AT_DMA_CHAN2_ERR_STAT__ADDR_OVLP__MASK 0x00000002U +#define AT_DMA_CHAN2_ERR_STAT__ADDR_OVLP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_DMA_CHAN2_ERR_STAT__ADDR_OVLP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_DMA_CHAN2_ERR_STAT__ADDR_OVLP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_DMA_CHAN2_ERR_STAT__ADDR_OVLP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bus_err */ +/** + * @defgroup at_ahb_dma_regs_core_bus_err_field bus_err_field + * @brief macros for field bus_err + * @details 0= no bus error, 1= a bus error occur during the transfer or at the launch of 'go'. + * @{ + */ +#define AT_DMA_CHAN2_ERR_STAT__BUS_ERR__SHIFT 2 +#define AT_DMA_CHAN2_ERR_STAT__BUS_ERR__WIDTH 1 +#define AT_DMA_CHAN2_ERR_STAT__BUS_ERR__MASK 0x00000004U +#define AT_DMA_CHAN2_ERR_STAT__BUS_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define AT_DMA_CHAN2_ERR_STAT__BUS_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define AT_DMA_CHAN2_ERR_STAT__BUS_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define AT_DMA_CHAN2_ERR_STAT__BUS_ERR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field addr_ovfl */ +/** + * @defgroup at_ahb_dma_regs_core_addr_ovfl_field addr_ovfl_field + * @brief macros for field addr_ovfl + * @details 0= no error, 1= error due to size + src_addr/tar_addr > 32'hffff_ffff. + * @{ + */ +#define AT_DMA_CHAN2_ERR_STAT__ADDR_OVFL__SHIFT 3 +#define AT_DMA_CHAN2_ERR_STAT__ADDR_OVFL__WIDTH 1 +#define AT_DMA_CHAN2_ERR_STAT__ADDR_OVFL__MASK 0x00000008U +#define AT_DMA_CHAN2_ERR_STAT__ADDR_OVFL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define AT_DMA_CHAN2_ERR_STAT__ADDR_OVFL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define AT_DMA_CHAN2_ERR_STAT__ADDR_OVFL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define AT_DMA_CHAN2_ERR_STAT__ADDR_OVFL__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN2_ERR_STAT__TYPE uint32_t +#define AT_DMA_CHAN2_ERR_STAT__READ 0x0000000fU +#define AT_DMA_CHAN2_ERR_STAT__PRESERVED 0x00000000U +#define AT_DMA_CHAN2_ERR_STAT__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN2_ERR_STAT_MACRO__ */ + +/** @} end of chan2_err_stat */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan2_status */ +/** + * @defgroup at_ahb_dma_regs_core_chan2_status chan2_status + * @brief Contains register fields associated with chan2_status. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN2_STATUS_MACRO__ +#define __AT_DMA_CHAN2_STATUS_MACRO__ + +/* macros for field running */ +/** + * @defgroup at_ahb_dma_regs_core_running_field running_field + * @brief macros for field running + * @details fsm is in an active state, not waiting for the bus or an interrupt. + * @{ + */ +#define AT_DMA_CHAN2_STATUS__RUNNING__SHIFT 0 +#define AT_DMA_CHAN2_STATUS__RUNNING__WIDTH 1 +#define AT_DMA_CHAN2_STATUS__RUNNING__MASK 0x00000001U +#define AT_DMA_CHAN2_STATUS__RUNNING__READ(src) ((uint32_t)(src) & 0x00000001U) +#define AT_DMA_CHAN2_STATUS__RUNNING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_CHAN2_STATUS__RUNNING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_CHAN2_STATUS__RUNNING__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field busy */ +/** + * @defgroup at_ahb_dma_regs_core_busy_field busy_field + * @brief macros for field busy + * @details fsm is in some non-idle state including waiting for the bus or an interrupt. + * @{ + */ +#define AT_DMA_CHAN2_STATUS__BUSY__SHIFT 1 +#define AT_DMA_CHAN2_STATUS__BUSY__WIDTH 1 +#define AT_DMA_CHAN2_STATUS__BUSY__MASK 0x00000002U +#define AT_DMA_CHAN2_STATUS__BUSY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_DMA_CHAN2_STATUS__BUSY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_DMA_CHAN2_STATUS__BUSY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_DMA_CHAN2_STATUS__BUSY__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN2_STATUS__TYPE uint32_t +#define AT_DMA_CHAN2_STATUS__READ 0x00000003U +#define AT_DMA_CHAN2_STATUS__PRESERVED 0x00000000U +#define AT_DMA_CHAN2_STATUS__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN2_STATUS_MACRO__ */ + +/** @} end of chan2_status */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan2_total_write_remainder */ +/** + * @defgroup at_ahb_dma_regs_core_chan2_total_write_remainder chan2_total_write_remainder + * @brief Contains register fields associated with chan2_total_write_remainder. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN2_TOTAL_WRITE_REMAINDER_MACRO__ +#define __AT_DMA_CHAN2_TOTAL_WRITE_REMAINDER_MACRO__ + +/* macros for field total_write_remainder */ +/** + * @defgroup at_ahb_dma_regs_core_total_write_remainder_field total_write_remainder_field + * @brief macros for field total_write_remainder + * @details number of bytes left to write at the time of stop + * @{ + */ +#define AT_DMA_CHAN2_TOTAL_WRITE_REMAINDER__TOTAL_WRITE_REMAINDER__SHIFT 0 +#define AT_DMA_CHAN2_TOTAL_WRITE_REMAINDER__TOTAL_WRITE_REMAINDER__WIDTH 24 +#define AT_DMA_CHAN2_TOTAL_WRITE_REMAINDER__TOTAL_WRITE_REMAINDER__MASK \ + 0x00ffffffU +#define AT_DMA_CHAN2_TOTAL_WRITE_REMAINDER__TOTAL_WRITE_REMAINDER__READ(src) \ + ((uint32_t)(src)\ + & 0x00ffffffU) +#define AT_DMA_CHAN2_TOTAL_WRITE_REMAINDER__TOTAL_WRITE_REMAINDER__RESET_VALUE \ + 0x00000000U +/** @} */ +#define AT_DMA_CHAN2_TOTAL_WRITE_REMAINDER__TYPE uint32_t +#define AT_DMA_CHAN2_TOTAL_WRITE_REMAINDER__READ 0x00ffffffU +#define AT_DMA_CHAN2_TOTAL_WRITE_REMAINDER__PRESERVED 0x00000000U +#define AT_DMA_CHAN2_TOTAL_WRITE_REMAINDER__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN2_TOTAL_WRITE_REMAINDER_MACRO__ */ + +/** @} end of chan2_total_write_remainder */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan2_interrupt_status */ +/** + * @defgroup at_ahb_dma_regs_core_chan2_interrupt_status chan2_interrupt_status + * @brief Contains register fields associated with chan2_interrupt_status. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN2_INTERRUPT_STATUS_MACRO__ +#define __AT_DMA_CHAN2_INTERRUPT_STATUS_MACRO__ + +/* macros for field dma_done */ +/** + * @defgroup at_ahb_dma_regs_core_dma_done_field dma_done_field + * @brief macros for field dma_done + * @details source of interrupt due to completion (chan0). + * @{ + */ +#define AT_DMA_CHAN2_INTERRUPT_STATUS__DMA_DONE__SHIFT 0 +#define AT_DMA_CHAN2_INTERRUPT_STATUS__DMA_DONE__WIDTH 1 +#define AT_DMA_CHAN2_INTERRUPT_STATUS__DMA_DONE__MASK 0x00000001U +#define AT_DMA_CHAN2_INTERRUPT_STATUS__DMA_DONE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN2_INTERRUPT_STATUS__DMA_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_CHAN2_INTERRUPT_STATUS__DMA_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_CHAN2_INTERRUPT_STATUS__DMA_DONE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dma_err */ +/** + * @defgroup at_ahb_dma_regs_core_dma_err_field dma_err_field + * @brief macros for field dma_err + * @details source of interrupt due to an error (chan0). + * @{ + */ +#define AT_DMA_CHAN2_INTERRUPT_STATUS__DMA_ERR__SHIFT 1 +#define AT_DMA_CHAN2_INTERRUPT_STATUS__DMA_ERR__WIDTH 1 +#define AT_DMA_CHAN2_INTERRUPT_STATUS__DMA_ERR__MASK 0x00000002U +#define AT_DMA_CHAN2_INTERRUPT_STATUS__DMA_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_DMA_CHAN2_INTERRUPT_STATUS__DMA_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_DMA_CHAN2_INTERRUPT_STATUS__DMA_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_DMA_CHAN2_INTERRUPT_STATUS__DMA_ERR__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN2_INTERRUPT_STATUS__TYPE uint32_t +#define AT_DMA_CHAN2_INTERRUPT_STATUS__READ 0x00000003U +#define AT_DMA_CHAN2_INTERRUPT_STATUS__PRESERVED 0x00000000U +#define AT_DMA_CHAN2_INTERRUPT_STATUS__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN2_INTERRUPT_STATUS_MACRO__ */ + +/** @} end of chan2_interrupt_status */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan2_interrupt_mask */ +/** + * @defgroup at_ahb_dma_regs_core_chan2_interrupt_mask chan2_interrupt_mask + * @brief Contains register fields associated with chan2_interrupt_mask. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN2_INTERRUPT_MASK_MACRO__ +#define __AT_DMA_CHAN2_INTERRUPT_MASK_MACRO__ + +/* macros for field intrpt_mask */ +/** + * @defgroup at_ahb_dma_regs_core_intrpt_mask_field intrpt_mask_field + * @brief macros for field intrpt_mask + * @details if nth bit set, the nth interrupt is enabled + * @{ + */ +#define AT_DMA_CHAN2_INTERRUPT_MASK__INTRPT_MASK__SHIFT 0 +#define AT_DMA_CHAN2_INTERRUPT_MASK__INTRPT_MASK__WIDTH 2 +#define AT_DMA_CHAN2_INTERRUPT_MASK__INTRPT_MASK__MASK 0x00000003U +#define AT_DMA_CHAN2_INTERRUPT_MASK__INTRPT_MASK__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN2_INTERRUPT_MASK__INTRPT_MASK__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN2_INTERRUPT_MASK__INTRPT_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_CHAN2_INTERRUPT_MASK__INTRPT_MASK__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_CHAN2_INTERRUPT_MASK__INTRPT_MASK__RESET_VALUE 0x00000001U +/** @} */ +#define AT_DMA_CHAN2_INTERRUPT_MASK__TYPE uint32_t +#define AT_DMA_CHAN2_INTERRUPT_MASK__READ 0x00000003U +#define AT_DMA_CHAN2_INTERRUPT_MASK__WRITE 0x00000003U +#define AT_DMA_CHAN2_INTERRUPT_MASK__PRESERVED 0x00000000U +#define AT_DMA_CHAN2_INTERRUPT_MASK__RESET_VALUE 0x00000001U + +#endif /* __AT_DMA_CHAN2_INTERRUPT_MASK_MACRO__ */ + +/** @} end of chan2_interrupt_mask */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan2_set_interrupt */ +/** + * @defgroup at_ahb_dma_regs_core_chan2_set_interrupt chan2_set_interrupt + * @brief Contains register fields associated with chan2_set_interrupt. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN2_SET_INTERRUPT_MACRO__ +#define __AT_DMA_CHAN2_SET_INTERRUPT_MACRO__ + +/* macros for field intrpt_set */ +/** + * @defgroup at_ahb_dma_regs_core_intrpt_set_field intrpt_set_field + * @brief macros for field intrpt_set + * @details if nth bit set, the nth interrupt is set; HW clears all bits the next cycle. + * @{ + */ +#define AT_DMA_CHAN2_SET_INTERRUPT__INTRPT_SET__SHIFT 0 +#define AT_DMA_CHAN2_SET_INTERRUPT__INTRPT_SET__WIDTH 2 +#define AT_DMA_CHAN2_SET_INTERRUPT__INTRPT_SET__MASK 0x00000003U +#define AT_DMA_CHAN2_SET_INTERRUPT__INTRPT_SET__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN2_SET_INTERRUPT__INTRPT_SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN2_SET_INTERRUPT__INTRPT_SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_CHAN2_SET_INTERRUPT__INTRPT_SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_CHAN2_SET_INTERRUPT__INTRPT_SET__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN2_SET_INTERRUPT__TYPE uint32_t +#define AT_DMA_CHAN2_SET_INTERRUPT__READ 0x00000003U +#define AT_DMA_CHAN2_SET_INTERRUPT__WRITE 0x00000003U +#define AT_DMA_CHAN2_SET_INTERRUPT__PRESERVED 0x00000000U +#define AT_DMA_CHAN2_SET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN2_SET_INTERRUPT_MACRO__ */ + +/** @} end of chan2_set_interrupt */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan2_reset_interrupt */ +/** + * @defgroup at_ahb_dma_regs_core_chan2_reset_interrupt chan2_reset_interrupt + * @brief Contains register fields associated with chan2_reset_interrupt. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN2_RESET_INTERRUPT_MACRO__ +#define __AT_DMA_CHAN2_RESET_INTERRUPT_MACRO__ + +/* macros for field intrpt_reset */ +/** + * @defgroup at_ahb_dma_regs_core_intrpt_reset_field intrpt_reset_field + * @brief macros for field intrpt_reset + * @details if nth bit set, the nth interrupt is reset; HW clears all bits the next cycle. + * @{ + */ +#define AT_DMA_CHAN2_RESET_INTERRUPT__INTRPT_RESET__SHIFT 0 +#define AT_DMA_CHAN2_RESET_INTERRUPT__INTRPT_RESET__WIDTH 2 +#define AT_DMA_CHAN2_RESET_INTERRUPT__INTRPT_RESET__MASK 0x00000003U +#define AT_DMA_CHAN2_RESET_INTERRUPT__INTRPT_RESET__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN2_RESET_INTERRUPT__INTRPT_RESET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN2_RESET_INTERRUPT__INTRPT_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_CHAN2_RESET_INTERRUPT__INTRPT_RESET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_CHAN2_RESET_INTERRUPT__INTRPT_RESET__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN2_RESET_INTERRUPT__TYPE uint32_t +#define AT_DMA_CHAN2_RESET_INTERRUPT__READ 0x00000003U +#define AT_DMA_CHAN2_RESET_INTERRUPT__WRITE 0x00000003U +#define AT_DMA_CHAN2_RESET_INTERRUPT__PRESERVED 0x00000000U +#define AT_DMA_CHAN2_RESET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN2_RESET_INTERRUPT_MACRO__ */ + +/** @} end of chan2_reset_interrupt */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan2_cfg_hnonsec */ +/** + * @defgroup at_ahb_dma_regs_core_chan2_cfg_hnonsec chan2_cfg_hnonsec + * @brief Contains register fields associated with chan2_cfg_hnonsec. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN2_CFG_HNONSEC_MACRO__ +#define __AT_DMA_CHAN2_CFG_HNONSEC_MACRO__ + +/* macros for field cfg_hnonsec */ +/** + * @defgroup at_ahb_dma_regs_core_cfg_hnonsec_field cfg_hnonsec_field + * @brief macros for field cfg_hnonsec + * @details control HNONSEC output signal of this channel. This register is only Write-able by Secure program. + * @{ + */ +#define AT_DMA_CHAN2_CFG_HNONSEC__CFG_HNONSEC__SHIFT 0 +#define AT_DMA_CHAN2_CFG_HNONSEC__CFG_HNONSEC__WIDTH 1 +#define AT_DMA_CHAN2_CFG_HNONSEC__CFG_HNONSEC__MASK 0x00000001U +#define AT_DMA_CHAN2_CFG_HNONSEC__CFG_HNONSEC__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN2_CFG_HNONSEC__CFG_HNONSEC__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN2_CFG_HNONSEC__CFG_HNONSEC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AT_DMA_CHAN2_CFG_HNONSEC__CFG_HNONSEC__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AT_DMA_CHAN2_CFG_HNONSEC__CFG_HNONSEC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_CHAN2_CFG_HNONSEC__CFG_HNONSEC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_CHAN2_CFG_HNONSEC__CFG_HNONSEC__RESET_VALUE 0x00000001U +/** @} */ +#define AT_DMA_CHAN2_CFG_HNONSEC__TYPE uint32_t +#define AT_DMA_CHAN2_CFG_HNONSEC__READ 0x00000001U +#define AT_DMA_CHAN2_CFG_HNONSEC__WRITE 0x00000001U +#define AT_DMA_CHAN2_CFG_HNONSEC__PRESERVED 0x00000000U +#define AT_DMA_CHAN2_CFG_HNONSEC__RESET_VALUE 0x00000001U + +#endif /* __AT_DMA_CHAN2_CFG_HNONSEC_MACRO__ */ + +/** @} end of chan2_cfg_hnonsec */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan3_opmode */ +/** + * @defgroup at_ahb_dma_regs_core_chan3_opmode chan3_opmode + * @brief Contains register fields associated with chan3_opmode. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN3_OPMODE_MACRO__ +#define __AT_DMA_CHAN3_OPMODE_MACRO__ + +/* macros for field const_trans */ +/** + * @defgroup at_ahb_dma_regs_core_const_trans_field const_trans_field + * @brief macros for field const_trans + * @details op code start when rising edge on 'go' is detected. + * @{ + */ +#define AT_DMA_CHAN3_OPMODE__CONST_TRANS__SHIFT 0 +#define AT_DMA_CHAN3_OPMODE__CONST_TRANS__WIDTH 1 +#define AT_DMA_CHAN3_OPMODE__CONST_TRANS__MASK 0x00000001U +#define AT_DMA_CHAN3_OPMODE__CONST_TRANS__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN3_OPMODE__CONST_TRANS__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN3_OPMODE__CONST_TRANS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AT_DMA_CHAN3_OPMODE__CONST_TRANS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AT_DMA_CHAN3_OPMODE__CONST_TRANS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_CHAN3_OPMODE__CONST_TRANS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_CHAN3_OPMODE__CONST_TRANS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dat_inv */ +/** + * @defgroup at_ahb_dma_regs_core_dat_inv_field dat_inv_field + * @brief macros for field dat_inv + * @details 0= non-inverted write ; 1= inverted write (write data are bit-wise inverted) + * @{ + */ +#define AT_DMA_CHAN3_OPMODE__DAT_INV__SHIFT 1 +#define AT_DMA_CHAN3_OPMODE__DAT_INV__WIDTH 1 +#define AT_DMA_CHAN3_OPMODE__DAT_INV__MASK 0x00000002U +#define AT_DMA_CHAN3_OPMODE__DAT_INV__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_DMA_CHAN3_OPMODE__DAT_INV__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define AT_DMA_CHAN3_OPMODE__DAT_INV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define AT_DMA_CHAN3_OPMODE__DAT_INV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define AT_DMA_CHAN3_OPMODE__DAT_INV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_DMA_CHAN3_OPMODE__DAT_INV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_DMA_CHAN3_OPMODE__DAT_INV__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field const_tar_addr */ +/** + * @defgroup at_ahb_dma_regs_core_const_tar_addr_field const_tar_addr_field + * @brief macros for field const_tar_addr + * @details 1= write address remains constant at tar_addr, which is required to be word-aligned in this mode. 0= write address increments as defined by the size parameter. + * @{ + */ +#define AT_DMA_CHAN3_OPMODE__CONST_TAR_ADDR__SHIFT 2 +#define AT_DMA_CHAN3_OPMODE__CONST_TAR_ADDR__WIDTH 1 +#define AT_DMA_CHAN3_OPMODE__CONST_TAR_ADDR__MASK 0x00000004U +#define AT_DMA_CHAN3_OPMODE__CONST_TAR_ADDR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define AT_DMA_CHAN3_OPMODE__CONST_TAR_ADDR__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define AT_DMA_CHAN3_OPMODE__CONST_TAR_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define AT_DMA_CHAN3_OPMODE__CONST_TAR_ADDR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define AT_DMA_CHAN3_OPMODE__CONST_TAR_ADDR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define AT_DMA_CHAN3_OPMODE__CONST_TAR_ADDR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define AT_DMA_CHAN3_OPMODE__CONST_TAR_ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field stop */ +/** + * @defgroup at_ahb_dma_regs_core_stop_field stop_field + * @brief macros for field stop + * @details to stop pending transaction . Not self clearing. + * @{ + */ +#define AT_DMA_CHAN3_OPMODE__STOP__SHIFT 30 +#define AT_DMA_CHAN3_OPMODE__STOP__WIDTH 1 +#define AT_DMA_CHAN3_OPMODE__STOP__MASK 0x40000000U +#define AT_DMA_CHAN3_OPMODE__STOP__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define AT_DMA_CHAN3_OPMODE__STOP__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define AT_DMA_CHAN3_OPMODE__STOP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define AT_DMA_CHAN3_OPMODE__STOP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define AT_DMA_CHAN3_OPMODE__STOP__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define AT_DMA_CHAN3_OPMODE__STOP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define AT_DMA_CHAN3_OPMODE__STOP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field go */ +/** + * @defgroup at_ahb_dma_regs_core_go_field go_field + * @brief macros for field go + * @details op code start when rising edge on 'go' is detected. HW clears after. + * @{ + */ +#define AT_DMA_CHAN3_OPMODE__GO__SHIFT 31 +#define AT_DMA_CHAN3_OPMODE__GO__WIDTH 1 +#define AT_DMA_CHAN3_OPMODE__GO__MASK 0x80000000U +#define AT_DMA_CHAN3_OPMODE__GO__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define AT_DMA_CHAN3_OPMODE__GO__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define AT_DMA_CHAN3_OPMODE__GO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define AT_DMA_CHAN3_OPMODE__GO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define AT_DMA_CHAN3_OPMODE__GO__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define AT_DMA_CHAN3_OPMODE__GO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define AT_DMA_CHAN3_OPMODE__GO__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN3_OPMODE__TYPE uint32_t +#define AT_DMA_CHAN3_OPMODE__READ 0xc0000007U +#define AT_DMA_CHAN3_OPMODE__WRITE 0xc0000007U +#define AT_DMA_CHAN3_OPMODE__PRESERVED 0x00000000U +#define AT_DMA_CHAN3_OPMODE__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN3_OPMODE_MACRO__ */ + +/** @} end of chan3_opmode */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan3_const_wdata */ +/** + * @defgroup at_ahb_dma_regs_core_chan3_const_wdata chan3_const_wdata + * @brief Contains register fields associated with chan3_const_wdata. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN3_CONST_WDATA_MACRO__ +#define __AT_DMA_CHAN3_CONST_WDATA_MACRO__ + +/* macros for field const_wdata */ +/** + * @defgroup at_ahb_dma_regs_core_const_wdata_field const_wdata_field + * @brief macros for field const_wdata + * @details constant value to be written to target when the operation is in const_trans mode. + * @{ + */ +#define AT_DMA_CHAN3_CONST_WDATA__CONST_WDATA__SHIFT 0 +#define AT_DMA_CHAN3_CONST_WDATA__CONST_WDATA__WIDTH 32 +#define AT_DMA_CHAN3_CONST_WDATA__CONST_WDATA__MASK 0xffffffffU +#define AT_DMA_CHAN3_CONST_WDATA__CONST_WDATA__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN3_CONST_WDATA__CONST_WDATA__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN3_CONST_WDATA__CONST_WDATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_DMA_CHAN3_CONST_WDATA__CONST_WDATA__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_DMA_CHAN3_CONST_WDATA__CONST_WDATA__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN3_CONST_WDATA__TYPE uint32_t +#define AT_DMA_CHAN3_CONST_WDATA__READ 0xffffffffU +#define AT_DMA_CHAN3_CONST_WDATA__WRITE 0xffffffffU +#define AT_DMA_CHAN3_CONST_WDATA__PRESERVED 0x00000000U +#define AT_DMA_CHAN3_CONST_WDATA__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN3_CONST_WDATA_MACRO__ */ + +/** @} end of chan3_const_wdata */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan3_src_addr */ +/** + * @defgroup at_ahb_dma_regs_core_chan3_src_addr chan3_src_addr + * @brief Contains register fields associated with chan3_src_addr. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN3_SRC_ADDR_MACRO__ +#define __AT_DMA_CHAN3_SRC_ADDR_MACRO__ + +/* macros for field src_addr */ +/** + * @defgroup at_ahb_dma_regs_core_src_addr_field src_addr_field + * @brief macros for field src_addr + * @details source address + * @{ + */ +#define AT_DMA_CHAN3_SRC_ADDR__SRC_ADDR__SHIFT 0 +#define AT_DMA_CHAN3_SRC_ADDR__SRC_ADDR__WIDTH 32 +#define AT_DMA_CHAN3_SRC_ADDR__SRC_ADDR__MASK 0xffffffffU +#define AT_DMA_CHAN3_SRC_ADDR__SRC_ADDR__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN3_SRC_ADDR__SRC_ADDR__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN3_SRC_ADDR__SRC_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_DMA_CHAN3_SRC_ADDR__SRC_ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_DMA_CHAN3_SRC_ADDR__SRC_ADDR__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN3_SRC_ADDR__TYPE uint32_t +#define AT_DMA_CHAN3_SRC_ADDR__READ 0xffffffffU +#define AT_DMA_CHAN3_SRC_ADDR__WRITE 0xffffffffU +#define AT_DMA_CHAN3_SRC_ADDR__PRESERVED 0x00000000U +#define AT_DMA_CHAN3_SRC_ADDR__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN3_SRC_ADDR_MACRO__ */ + +/** @} end of chan3_src_addr */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan3_tar_addr */ +/** + * @defgroup at_ahb_dma_regs_core_chan3_tar_addr chan3_tar_addr + * @brief Contains register fields associated with chan3_tar_addr. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN3_TAR_ADDR_MACRO__ +#define __AT_DMA_CHAN3_TAR_ADDR_MACRO__ + +/* macros for field tar_addr */ +/** + * @defgroup at_ahb_dma_regs_core_tar_addr_field tar_addr_field + * @brief macros for field tar_addr + * @details target address + * @{ + */ +#define AT_DMA_CHAN3_TAR_ADDR__TAR_ADDR__SHIFT 0 +#define AT_DMA_CHAN3_TAR_ADDR__TAR_ADDR__WIDTH 32 +#define AT_DMA_CHAN3_TAR_ADDR__TAR_ADDR__MASK 0xffffffffU +#define AT_DMA_CHAN3_TAR_ADDR__TAR_ADDR__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN3_TAR_ADDR__TAR_ADDR__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN3_TAR_ADDR__TAR_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_DMA_CHAN3_TAR_ADDR__TAR_ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_DMA_CHAN3_TAR_ADDR__TAR_ADDR__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN3_TAR_ADDR__TYPE uint32_t +#define AT_DMA_CHAN3_TAR_ADDR__READ 0xffffffffU +#define AT_DMA_CHAN3_TAR_ADDR__WRITE 0xffffffffU +#define AT_DMA_CHAN3_TAR_ADDR__PRESERVED 0x00000000U +#define AT_DMA_CHAN3_TAR_ADDR__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN3_TAR_ADDR_MACRO__ */ + +/** @} end of chan3_tar_addr */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan3_size */ +/** + * @defgroup at_ahb_dma_regs_core_chan3_size chan3_size + * @brief Contains register fields associated with chan3_size. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN3_SIZE_MACRO__ +#define __AT_DMA_CHAN3_SIZE_MACRO__ + +/* macros for field size */ +/** + * @defgroup at_ahb_dma_regs_core_size_field size_field + * @brief macros for field size + * @details payload size in bytes. + * @{ + */ +#define AT_DMA_CHAN3_SIZE__SIZE__SHIFT 0 +#define AT_DMA_CHAN3_SIZE__SIZE__WIDTH 24 +#define AT_DMA_CHAN3_SIZE__SIZE__MASK 0x00ffffffU +#define AT_DMA_CHAN3_SIZE__SIZE__READ(src) ((uint32_t)(src) & 0x00ffffffU) +#define AT_DMA_CHAN3_SIZE__SIZE__WRITE(src) ((uint32_t)(src) & 0x00ffffffU) +#define AT_DMA_CHAN3_SIZE__SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((uint32_t)(src) &\ + 0x00ffffffU) +#define AT_DMA_CHAN3_SIZE__SIZE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00ffffffU))) +#define AT_DMA_CHAN3_SIZE__SIZE__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN3_SIZE__TYPE uint32_t +#define AT_DMA_CHAN3_SIZE__READ 0x00ffffffU +#define AT_DMA_CHAN3_SIZE__WRITE 0x00ffffffU +#define AT_DMA_CHAN3_SIZE__PRESERVED 0x00000000U +#define AT_DMA_CHAN3_SIZE__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN3_SIZE_MACRO__ */ + +/** @} end of chan3_size */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan3_src_ctrl */ +/** + * @defgroup at_ahb_dma_regs_core_chan3_src_ctrl chan3_src_ctrl + * @brief Contains register fields associated with chan3_src_ctrl. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN3_SRC_CTRL_MACRO__ +#define __AT_DMA_CHAN3_SRC_CTRL_MACRO__ + +/* macros for field src_type */ +/** + * @defgroup at_ahb_dma_regs_core_src_type_field src_type_field + * @brief macros for field src_type + * @details 0=mem, 1=fifo, 2=periph master, 3=periph slave + * @{ + */ +#define AT_DMA_CHAN3_SRC_CTRL__SRC_TYPE__SHIFT 0 +#define AT_DMA_CHAN3_SRC_CTRL__SRC_TYPE__WIDTH 2 +#define AT_DMA_CHAN3_SRC_CTRL__SRC_TYPE__MASK 0x00000003U +#define AT_DMA_CHAN3_SRC_CTRL__SRC_TYPE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN3_SRC_CTRL__SRC_TYPE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN3_SRC_CTRL__SRC_TYPE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_CHAN3_SRC_CTRL__SRC_TYPE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_CHAN3_SRC_CTRL__SRC_TYPE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field src_bus_size */ +/** + * @defgroup at_ahb_dma_regs_core_src_bus_size_field src_bus_size_field + * @brief macros for field src_bus_size + * @details the width of fifo. one byte to 4 bytes. + * @{ + */ +#define AT_DMA_CHAN3_SRC_CTRL__SRC_BUS_SIZE__SHIFT 2 +#define AT_DMA_CHAN3_SRC_CTRL__SRC_BUS_SIZE__WIDTH 3 +#define AT_DMA_CHAN3_SRC_CTRL__SRC_BUS_SIZE__MASK 0x0000001cU +#define AT_DMA_CHAN3_SRC_CTRL__SRC_BUS_SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0x0000001cU) >> 2) +#define AT_DMA_CHAN3_SRC_CTRL__SRC_BUS_SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000001cU) +#define AT_DMA_CHAN3_SRC_CTRL__SRC_BUS_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((uint32_t)(src) <<\ + 2) & 0x0000001cU) +#define AT_DMA_CHAN3_SRC_CTRL__SRC_BUS_SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000001cU))) +#define AT_DMA_CHAN3_SRC_CTRL__SRC_BUS_SIZE__RESET_VALUE 0x00000001U +/** @} */ +#define AT_DMA_CHAN3_SRC_CTRL__TYPE uint32_t +#define AT_DMA_CHAN3_SRC_CTRL__READ 0x0000001fU +#define AT_DMA_CHAN3_SRC_CTRL__WRITE 0x0000001fU +#define AT_DMA_CHAN3_SRC_CTRL__PRESERVED 0x00000000U +#define AT_DMA_CHAN3_SRC_CTRL__RESET_VALUE 0x00000004U + +#endif /* __AT_DMA_CHAN3_SRC_CTRL_MACRO__ */ + +/** @} end of chan3_src_ctrl */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan3_tar_ctrl */ +/** + * @defgroup at_ahb_dma_regs_core_chan3_tar_ctrl chan3_tar_ctrl + * @brief Contains register fields associated with chan3_tar_ctrl. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN3_TAR_CTRL_MACRO__ +#define __AT_DMA_CHAN3_TAR_CTRL_MACRO__ + +/* macros for field tar_type */ +/** + * @defgroup at_ahb_dma_regs_core_tar_type_field tar_type_field + * @brief macros for field tar_type + * @details 0=mem, 1=fifo, 2=periph master, 3=periph slave + * @{ + */ +#define AT_DMA_CHAN3_TAR_CTRL__TAR_TYPE__SHIFT 0 +#define AT_DMA_CHAN3_TAR_CTRL__TAR_TYPE__WIDTH 2 +#define AT_DMA_CHAN3_TAR_CTRL__TAR_TYPE__MASK 0x00000003U +#define AT_DMA_CHAN3_TAR_CTRL__TAR_TYPE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN3_TAR_CTRL__TAR_TYPE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN3_TAR_CTRL__TAR_TYPE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_CHAN3_TAR_CTRL__TAR_TYPE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_CHAN3_TAR_CTRL__TAR_TYPE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tar_bus_size */ +/** + * @defgroup at_ahb_dma_regs_core_tar_bus_size_field tar_bus_size_field + * @brief macros for field tar_bus_size + * @details the width of fifo. one byte to 4 bytes. + * @{ + */ +#define AT_DMA_CHAN3_TAR_CTRL__TAR_BUS_SIZE__SHIFT 2 +#define AT_DMA_CHAN3_TAR_CTRL__TAR_BUS_SIZE__WIDTH 3 +#define AT_DMA_CHAN3_TAR_CTRL__TAR_BUS_SIZE__MASK 0x0000001cU +#define AT_DMA_CHAN3_TAR_CTRL__TAR_BUS_SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0x0000001cU) >> 2) +#define AT_DMA_CHAN3_TAR_CTRL__TAR_BUS_SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000001cU) +#define AT_DMA_CHAN3_TAR_CTRL__TAR_BUS_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((uint32_t)(src) <<\ + 2) & 0x0000001cU) +#define AT_DMA_CHAN3_TAR_CTRL__TAR_BUS_SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000001cU))) +#define AT_DMA_CHAN3_TAR_CTRL__TAR_BUS_SIZE__RESET_VALUE 0x00000001U +/** @} */ +#define AT_DMA_CHAN3_TAR_CTRL__TYPE uint32_t +#define AT_DMA_CHAN3_TAR_CTRL__READ 0x0000001fU +#define AT_DMA_CHAN3_TAR_CTRL__WRITE 0x0000001fU +#define AT_DMA_CHAN3_TAR_CTRL__PRESERVED 0x00000000U +#define AT_DMA_CHAN3_TAR_CTRL__RESET_VALUE 0x00000004U + +#endif /* __AT_DMA_CHAN3_TAR_CTRL_MACRO__ */ + +/** @} end of chan3_tar_ctrl */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan3_fifo_dpth_addr */ +/** + * @defgroup at_ahb_dma_regs_core_chan3_fifo_dpth_addr chan3_fifo_dpth_addr + * @brief Contains register fields associated with chan3_fifo_dpth_addr. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN3_FIFO_DPTH_ADDR_MACRO__ +#define __AT_DMA_CHAN3_FIFO_DPTH_ADDR_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_ahb_dma_regs_core_addr_field addr_field + * @brief macros for field addr + * @details address of the external fifo depth. Statemachine reads this to determine how many push/pull accesses to do per interrupt. + * @{ + */ +#define AT_DMA_CHAN3_FIFO_DPTH_ADDR__ADDR__SHIFT 0 +#define AT_DMA_CHAN3_FIFO_DPTH_ADDR__ADDR__WIDTH 32 +#define AT_DMA_CHAN3_FIFO_DPTH_ADDR__ADDR__MASK 0xffffffffU +#define AT_DMA_CHAN3_FIFO_DPTH_ADDR__ADDR__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN3_FIFO_DPTH_ADDR__ADDR__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_DMA_CHAN3_FIFO_DPTH_ADDR__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_DMA_CHAN3_FIFO_DPTH_ADDR__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_DMA_CHAN3_FIFO_DPTH_ADDR__ADDR__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN3_FIFO_DPTH_ADDR__TYPE uint32_t +#define AT_DMA_CHAN3_FIFO_DPTH_ADDR__READ 0xffffffffU +#define AT_DMA_CHAN3_FIFO_DPTH_ADDR__WRITE 0xffffffffU +#define AT_DMA_CHAN3_FIFO_DPTH_ADDR__PRESERVED 0x00000000U +#define AT_DMA_CHAN3_FIFO_DPTH_ADDR__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN3_FIFO_DPTH_ADDR_MACRO__ */ + +/** @} end of chan3_fifo_dpth_addr */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan3_fifo_port_sel */ +/** + * @defgroup at_ahb_dma_regs_core_chan3_fifo_port_sel chan3_fifo_port_sel + * @brief Contains register fields associated with chan3_fifo_port_sel. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN3_FIFO_PORT_SEL_MACRO__ +#define __AT_DMA_CHAN3_FIFO_PORT_SEL_MACRO__ + +/* macros for field src_port_sel */ +/** + * @defgroup at_ahb_dma_regs_core_src_port_sel_field src_port_sel_field + * @brief macros for field src_port_sel + * @details selecting the source fifo port; 5 = rsvd 4 = i2s fifo 3 = pdm1 fifo 2 = pdm0 fifo 1 = uart1 rx 0 = uart0 rx + * @{ + */ +#define AT_DMA_CHAN3_FIFO_PORT_SEL__SRC_PORT_SEL__SHIFT 0 +#define AT_DMA_CHAN3_FIFO_PORT_SEL__SRC_PORT_SEL__WIDTH 3 +#define AT_DMA_CHAN3_FIFO_PORT_SEL__SRC_PORT_SEL__MASK 0x00000007U +#define AT_DMA_CHAN3_FIFO_PORT_SEL__SRC_PORT_SEL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define AT_DMA_CHAN3_FIFO_PORT_SEL__SRC_PORT_SEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define AT_DMA_CHAN3_FIFO_PORT_SEL__SRC_PORT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define AT_DMA_CHAN3_FIFO_PORT_SEL__SRC_PORT_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define AT_DMA_CHAN3_FIFO_PORT_SEL__SRC_PORT_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tar_port_sel */ +/** + * @defgroup at_ahb_dma_regs_core_tar_port_sel_field tar_port_sel_field + * @brief macros for field tar_port_sel + * @details selecting the target fifo port; 5 = pwd fifo 4 = i2s fifo 3 = rsvd 2 = rsvd 1 = uart1 tx 0 = uart0 tx + * @{ + */ +#define AT_DMA_CHAN3_FIFO_PORT_SEL__TAR_PORT_SEL__SHIFT 16 +#define AT_DMA_CHAN3_FIFO_PORT_SEL__TAR_PORT_SEL__WIDTH 3 +#define AT_DMA_CHAN3_FIFO_PORT_SEL__TAR_PORT_SEL__MASK 0x00070000U +#define AT_DMA_CHAN3_FIFO_PORT_SEL__TAR_PORT_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00070000U) >> 16) +#define AT_DMA_CHAN3_FIFO_PORT_SEL__TAR_PORT_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00070000U) +#define AT_DMA_CHAN3_FIFO_PORT_SEL__TAR_PORT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((uint32_t)(src) <<\ + 16) & 0x00070000U) +#define AT_DMA_CHAN3_FIFO_PORT_SEL__TAR_PORT_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00070000U))) +#define AT_DMA_CHAN3_FIFO_PORT_SEL__TAR_PORT_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN3_FIFO_PORT_SEL__TYPE uint32_t +#define AT_DMA_CHAN3_FIFO_PORT_SEL__READ 0x00070007U +#define AT_DMA_CHAN3_FIFO_PORT_SEL__WRITE 0x00070007U +#define AT_DMA_CHAN3_FIFO_PORT_SEL__PRESERVED 0x00000000U +#define AT_DMA_CHAN3_FIFO_PORT_SEL__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN3_FIFO_PORT_SEL_MACRO__ */ + +/** @} end of chan3_fifo_port_sel */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan3_spi_port_sel */ +/** + * @defgroup at_ahb_dma_regs_core_chan3_spi_port_sel chan3_spi_port_sel + * @brief Contains register fields associated with chan3_spi_port_sel. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN3_SPI_PORT_SEL_MACRO__ +#define __AT_DMA_CHAN3_SPI_PORT_SEL_MACRO__ + +/* macros for field spi_sel */ +/** + * @defgroup at_ahb_dma_regs_core_spi_sel_field spi_sel_field + * @brief macros for field spi_sel + * @details 1=select spi1 for this channel, 0=select spi0 for this channel. + * @{ + */ +#define AT_DMA_CHAN3_SPI_PORT_SEL__SPI_SEL__SHIFT 0 +#define AT_DMA_CHAN3_SPI_PORT_SEL__SPI_SEL__WIDTH 1 +#define AT_DMA_CHAN3_SPI_PORT_SEL__SPI_SEL__MASK 0x00000001U +#define AT_DMA_CHAN3_SPI_PORT_SEL__SPI_SEL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN3_SPI_PORT_SEL__SPI_SEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN3_SPI_PORT_SEL__SPI_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AT_DMA_CHAN3_SPI_PORT_SEL__SPI_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AT_DMA_CHAN3_SPI_PORT_SEL__SPI_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_CHAN3_SPI_PORT_SEL__SPI_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_CHAN3_SPI_PORT_SEL__SPI_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN3_SPI_PORT_SEL__TYPE uint32_t +#define AT_DMA_CHAN3_SPI_PORT_SEL__READ 0x00000001U +#define AT_DMA_CHAN3_SPI_PORT_SEL__WRITE 0x00000001U +#define AT_DMA_CHAN3_SPI_PORT_SEL__PRESERVED 0x00000000U +#define AT_DMA_CHAN3_SPI_PORT_SEL__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN3_SPI_PORT_SEL_MACRO__ */ + +/** @} end of chan3_spi_port_sel */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan3_err_stat */ +/** + * @defgroup at_ahb_dma_regs_core_chan3_err_stat chan3_err_stat + * @brief The status is cleared when the err interrupt is cleared definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN3_ERR_STAT_MACRO__ +#define __AT_DMA_CHAN3_ERR_STAT_MACRO__ + +/* macros for field size_0 */ +/** + * @defgroup at_ahb_dma_regs_core_size_0_field size_0_field + * @brief macros for field size_0 + * @details 0= size is not 0 when go is launched, 1= size is 0 when go is launched. + * @{ + */ +#define AT_DMA_CHAN3_ERR_STAT__SIZE_0__SHIFT 0 +#define AT_DMA_CHAN3_ERR_STAT__SIZE_0__WIDTH 1 +#define AT_DMA_CHAN3_ERR_STAT__SIZE_0__MASK 0x00000001U +#define AT_DMA_CHAN3_ERR_STAT__SIZE_0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN3_ERR_STAT__SIZE_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_CHAN3_ERR_STAT__SIZE_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_CHAN3_ERR_STAT__SIZE_0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field addr_ovlp */ +/** + * @defgroup at_ahb_dma_regs_core_addr_ovlp_field addr_ovlp_field + * @brief macros for field addr_ovlp + * @details 0= no overlap between src and tar addr range, 1= there is an overlap + * @{ + */ +#define AT_DMA_CHAN3_ERR_STAT__ADDR_OVLP__SHIFT 1 +#define AT_DMA_CHAN3_ERR_STAT__ADDR_OVLP__WIDTH 1 +#define AT_DMA_CHAN3_ERR_STAT__ADDR_OVLP__MASK 0x00000002U +#define AT_DMA_CHAN3_ERR_STAT__ADDR_OVLP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_DMA_CHAN3_ERR_STAT__ADDR_OVLP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_DMA_CHAN3_ERR_STAT__ADDR_OVLP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_DMA_CHAN3_ERR_STAT__ADDR_OVLP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bus_err */ +/** + * @defgroup at_ahb_dma_regs_core_bus_err_field bus_err_field + * @brief macros for field bus_err + * @details 0= no bus error, 1= a bus error occur during the transfer or at the launch of 'go'. + * @{ + */ +#define AT_DMA_CHAN3_ERR_STAT__BUS_ERR__SHIFT 2 +#define AT_DMA_CHAN3_ERR_STAT__BUS_ERR__WIDTH 1 +#define AT_DMA_CHAN3_ERR_STAT__BUS_ERR__MASK 0x00000004U +#define AT_DMA_CHAN3_ERR_STAT__BUS_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define AT_DMA_CHAN3_ERR_STAT__BUS_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define AT_DMA_CHAN3_ERR_STAT__BUS_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define AT_DMA_CHAN3_ERR_STAT__BUS_ERR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field addr_ovfl */ +/** + * @defgroup at_ahb_dma_regs_core_addr_ovfl_field addr_ovfl_field + * @brief macros for field addr_ovfl + * @details 0= no error, 1= error due to size + src_addr/tar_addr > 32'hffff_ffff. + * @{ + */ +#define AT_DMA_CHAN3_ERR_STAT__ADDR_OVFL__SHIFT 3 +#define AT_DMA_CHAN3_ERR_STAT__ADDR_OVFL__WIDTH 1 +#define AT_DMA_CHAN3_ERR_STAT__ADDR_OVFL__MASK 0x00000008U +#define AT_DMA_CHAN3_ERR_STAT__ADDR_OVFL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define AT_DMA_CHAN3_ERR_STAT__ADDR_OVFL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define AT_DMA_CHAN3_ERR_STAT__ADDR_OVFL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define AT_DMA_CHAN3_ERR_STAT__ADDR_OVFL__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN3_ERR_STAT__TYPE uint32_t +#define AT_DMA_CHAN3_ERR_STAT__READ 0x0000000fU +#define AT_DMA_CHAN3_ERR_STAT__PRESERVED 0x00000000U +#define AT_DMA_CHAN3_ERR_STAT__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN3_ERR_STAT_MACRO__ */ + +/** @} end of chan3_err_stat */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan3_status */ +/** + * @defgroup at_ahb_dma_regs_core_chan3_status chan3_status + * @brief Contains register fields associated with chan3_status. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN3_STATUS_MACRO__ +#define __AT_DMA_CHAN3_STATUS_MACRO__ + +/* macros for field running */ +/** + * @defgroup at_ahb_dma_regs_core_running_field running_field + * @brief macros for field running + * @details fsm is in an active state, not waiting for the bus or an interrupt. + * @{ + */ +#define AT_DMA_CHAN3_STATUS__RUNNING__SHIFT 0 +#define AT_DMA_CHAN3_STATUS__RUNNING__WIDTH 1 +#define AT_DMA_CHAN3_STATUS__RUNNING__MASK 0x00000001U +#define AT_DMA_CHAN3_STATUS__RUNNING__READ(src) ((uint32_t)(src) & 0x00000001U) +#define AT_DMA_CHAN3_STATUS__RUNNING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_CHAN3_STATUS__RUNNING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_CHAN3_STATUS__RUNNING__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field busy */ +/** + * @defgroup at_ahb_dma_regs_core_busy_field busy_field + * @brief macros for field busy + * @details fsm is in some non-idle state including waiting for the bus or an interrupt. + * @{ + */ +#define AT_DMA_CHAN3_STATUS__BUSY__SHIFT 1 +#define AT_DMA_CHAN3_STATUS__BUSY__WIDTH 1 +#define AT_DMA_CHAN3_STATUS__BUSY__MASK 0x00000002U +#define AT_DMA_CHAN3_STATUS__BUSY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_DMA_CHAN3_STATUS__BUSY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_DMA_CHAN3_STATUS__BUSY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_DMA_CHAN3_STATUS__BUSY__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN3_STATUS__TYPE uint32_t +#define AT_DMA_CHAN3_STATUS__READ 0x00000003U +#define AT_DMA_CHAN3_STATUS__PRESERVED 0x00000000U +#define AT_DMA_CHAN3_STATUS__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN3_STATUS_MACRO__ */ + +/** @} end of chan3_status */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan3_total_write_remainder */ +/** + * @defgroup at_ahb_dma_regs_core_chan3_total_write_remainder chan3_total_write_remainder + * @brief Contains register fields associated with chan3_total_write_remainder. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN3_TOTAL_WRITE_REMAINDER_MACRO__ +#define __AT_DMA_CHAN3_TOTAL_WRITE_REMAINDER_MACRO__ + +/* macros for field total_write_remainder */ +/** + * @defgroup at_ahb_dma_regs_core_total_write_remainder_field total_write_remainder_field + * @brief macros for field total_write_remainder + * @details number of bytes left to write at the time of stop + * @{ + */ +#define AT_DMA_CHAN3_TOTAL_WRITE_REMAINDER__TOTAL_WRITE_REMAINDER__SHIFT 0 +#define AT_DMA_CHAN3_TOTAL_WRITE_REMAINDER__TOTAL_WRITE_REMAINDER__WIDTH 24 +#define AT_DMA_CHAN3_TOTAL_WRITE_REMAINDER__TOTAL_WRITE_REMAINDER__MASK \ + 0x00ffffffU +#define AT_DMA_CHAN3_TOTAL_WRITE_REMAINDER__TOTAL_WRITE_REMAINDER__READ(src) \ + ((uint32_t)(src)\ + & 0x00ffffffU) +#define AT_DMA_CHAN3_TOTAL_WRITE_REMAINDER__TOTAL_WRITE_REMAINDER__RESET_VALUE \ + 0x00000000U +/** @} */ +#define AT_DMA_CHAN3_TOTAL_WRITE_REMAINDER__TYPE uint32_t +#define AT_DMA_CHAN3_TOTAL_WRITE_REMAINDER__READ 0x00ffffffU +#define AT_DMA_CHAN3_TOTAL_WRITE_REMAINDER__PRESERVED 0x00000000U +#define AT_DMA_CHAN3_TOTAL_WRITE_REMAINDER__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN3_TOTAL_WRITE_REMAINDER_MACRO__ */ + +/** @} end of chan3_total_write_remainder */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan3_interrupt_status */ +/** + * @defgroup at_ahb_dma_regs_core_chan3_interrupt_status chan3_interrupt_status + * @brief Contains register fields associated with chan3_interrupt_status. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN3_INTERRUPT_STATUS_MACRO__ +#define __AT_DMA_CHAN3_INTERRUPT_STATUS_MACRO__ + +/* macros for field dma_done */ +/** + * @defgroup at_ahb_dma_regs_core_dma_done_field dma_done_field + * @brief macros for field dma_done + * @details source of interrupt due to completion (chan0). + * @{ + */ +#define AT_DMA_CHAN3_INTERRUPT_STATUS__DMA_DONE__SHIFT 0 +#define AT_DMA_CHAN3_INTERRUPT_STATUS__DMA_DONE__WIDTH 1 +#define AT_DMA_CHAN3_INTERRUPT_STATUS__DMA_DONE__MASK 0x00000001U +#define AT_DMA_CHAN3_INTERRUPT_STATUS__DMA_DONE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN3_INTERRUPT_STATUS__DMA_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_CHAN3_INTERRUPT_STATUS__DMA_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_CHAN3_INTERRUPT_STATUS__DMA_DONE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dma_err */ +/** + * @defgroup at_ahb_dma_regs_core_dma_err_field dma_err_field + * @brief macros for field dma_err + * @details source of interrupt due to an error (chan0). + * @{ + */ +#define AT_DMA_CHAN3_INTERRUPT_STATUS__DMA_ERR__SHIFT 1 +#define AT_DMA_CHAN3_INTERRUPT_STATUS__DMA_ERR__WIDTH 1 +#define AT_DMA_CHAN3_INTERRUPT_STATUS__DMA_ERR__MASK 0x00000002U +#define AT_DMA_CHAN3_INTERRUPT_STATUS__DMA_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_DMA_CHAN3_INTERRUPT_STATUS__DMA_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_DMA_CHAN3_INTERRUPT_STATUS__DMA_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_DMA_CHAN3_INTERRUPT_STATUS__DMA_ERR__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN3_INTERRUPT_STATUS__TYPE uint32_t +#define AT_DMA_CHAN3_INTERRUPT_STATUS__READ 0x00000003U +#define AT_DMA_CHAN3_INTERRUPT_STATUS__PRESERVED 0x00000000U +#define AT_DMA_CHAN3_INTERRUPT_STATUS__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN3_INTERRUPT_STATUS_MACRO__ */ + +/** @} end of chan3_interrupt_status */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan3_interrupt_mask */ +/** + * @defgroup at_ahb_dma_regs_core_chan3_interrupt_mask chan3_interrupt_mask + * @brief Contains register fields associated with chan3_interrupt_mask. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN3_INTERRUPT_MASK_MACRO__ +#define __AT_DMA_CHAN3_INTERRUPT_MASK_MACRO__ + +/* macros for field intrpt_mask */ +/** + * @defgroup at_ahb_dma_regs_core_intrpt_mask_field intrpt_mask_field + * @brief macros for field intrpt_mask + * @details if nth bit set, the nth interrupt is enabled + * @{ + */ +#define AT_DMA_CHAN3_INTERRUPT_MASK__INTRPT_MASK__SHIFT 0 +#define AT_DMA_CHAN3_INTERRUPT_MASK__INTRPT_MASK__WIDTH 2 +#define AT_DMA_CHAN3_INTERRUPT_MASK__INTRPT_MASK__MASK 0x00000003U +#define AT_DMA_CHAN3_INTERRUPT_MASK__INTRPT_MASK__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN3_INTERRUPT_MASK__INTRPT_MASK__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN3_INTERRUPT_MASK__INTRPT_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_CHAN3_INTERRUPT_MASK__INTRPT_MASK__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_CHAN3_INTERRUPT_MASK__INTRPT_MASK__RESET_VALUE 0x00000001U +/** @} */ +#define AT_DMA_CHAN3_INTERRUPT_MASK__TYPE uint32_t +#define AT_DMA_CHAN3_INTERRUPT_MASK__READ 0x00000003U +#define AT_DMA_CHAN3_INTERRUPT_MASK__WRITE 0x00000003U +#define AT_DMA_CHAN3_INTERRUPT_MASK__PRESERVED 0x00000000U +#define AT_DMA_CHAN3_INTERRUPT_MASK__RESET_VALUE 0x00000001U + +#endif /* __AT_DMA_CHAN3_INTERRUPT_MASK_MACRO__ */ + +/** @} end of chan3_interrupt_mask */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan3_set_interrupt */ +/** + * @defgroup at_ahb_dma_regs_core_chan3_set_interrupt chan3_set_interrupt + * @brief Contains register fields associated with chan3_set_interrupt. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN3_SET_INTERRUPT_MACRO__ +#define __AT_DMA_CHAN3_SET_INTERRUPT_MACRO__ + +/* macros for field intrpt_set */ +/** + * @defgroup at_ahb_dma_regs_core_intrpt_set_field intrpt_set_field + * @brief macros for field intrpt_set + * @details if nth bit set, the nth interrupt is set; HW clears all bits the next cycle. + * @{ + */ +#define AT_DMA_CHAN3_SET_INTERRUPT__INTRPT_SET__SHIFT 0 +#define AT_DMA_CHAN3_SET_INTERRUPT__INTRPT_SET__WIDTH 2 +#define AT_DMA_CHAN3_SET_INTERRUPT__INTRPT_SET__MASK 0x00000003U +#define AT_DMA_CHAN3_SET_INTERRUPT__INTRPT_SET__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN3_SET_INTERRUPT__INTRPT_SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN3_SET_INTERRUPT__INTRPT_SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_CHAN3_SET_INTERRUPT__INTRPT_SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_CHAN3_SET_INTERRUPT__INTRPT_SET__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN3_SET_INTERRUPT__TYPE uint32_t +#define AT_DMA_CHAN3_SET_INTERRUPT__READ 0x00000003U +#define AT_DMA_CHAN3_SET_INTERRUPT__WRITE 0x00000003U +#define AT_DMA_CHAN3_SET_INTERRUPT__PRESERVED 0x00000000U +#define AT_DMA_CHAN3_SET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN3_SET_INTERRUPT_MACRO__ */ + +/** @} end of chan3_set_interrupt */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan3_reset_interrupt */ +/** + * @defgroup at_ahb_dma_regs_core_chan3_reset_interrupt chan3_reset_interrupt + * @brief Contains register fields associated with chan3_reset_interrupt. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN3_RESET_INTERRUPT_MACRO__ +#define __AT_DMA_CHAN3_RESET_INTERRUPT_MACRO__ + +/* macros for field intrpt_reset */ +/** + * @defgroup at_ahb_dma_regs_core_intrpt_reset_field intrpt_reset_field + * @brief macros for field intrpt_reset + * @details if nth bit set, the nth interrupt is reset; HW clears all bits the next cycle. + * @{ + */ +#define AT_DMA_CHAN3_RESET_INTERRUPT__INTRPT_RESET__SHIFT 0 +#define AT_DMA_CHAN3_RESET_INTERRUPT__INTRPT_RESET__WIDTH 2 +#define AT_DMA_CHAN3_RESET_INTERRUPT__INTRPT_RESET__MASK 0x00000003U +#define AT_DMA_CHAN3_RESET_INTERRUPT__INTRPT_RESET__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN3_RESET_INTERRUPT__INTRPT_RESET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define AT_DMA_CHAN3_RESET_INTERRUPT__INTRPT_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_CHAN3_RESET_INTERRUPT__INTRPT_RESET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_CHAN3_RESET_INTERRUPT__INTRPT_RESET__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_CHAN3_RESET_INTERRUPT__TYPE uint32_t +#define AT_DMA_CHAN3_RESET_INTERRUPT__READ 0x00000003U +#define AT_DMA_CHAN3_RESET_INTERRUPT__WRITE 0x00000003U +#define AT_DMA_CHAN3_RESET_INTERRUPT__PRESERVED 0x00000000U +#define AT_DMA_CHAN3_RESET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_CHAN3_RESET_INTERRUPT_MACRO__ */ + +/** @} end of chan3_reset_interrupt */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_chan3_cfg_hnonsec */ +/** + * @defgroup at_ahb_dma_regs_core_chan3_cfg_hnonsec chan3_cfg_hnonsec + * @brief Contains register fields associated with chan3_cfg_hnonsec. definitions. + * @{ + */ +#ifndef __AT_DMA_CHAN3_CFG_HNONSEC_MACRO__ +#define __AT_DMA_CHAN3_CFG_HNONSEC_MACRO__ + +/* macros for field cfg_hnonsec */ +/** + * @defgroup at_ahb_dma_regs_core_cfg_hnonsec_field cfg_hnonsec_field + * @brief macros for field cfg_hnonsec + * @details control HNONSEC output signal of this channel. This register is only Write-able by Secure program. + * @{ + */ +#define AT_DMA_CHAN3_CFG_HNONSEC__CFG_HNONSEC__SHIFT 0 +#define AT_DMA_CHAN3_CFG_HNONSEC__CFG_HNONSEC__WIDTH 1 +#define AT_DMA_CHAN3_CFG_HNONSEC__CFG_HNONSEC__MASK 0x00000001U +#define AT_DMA_CHAN3_CFG_HNONSEC__CFG_HNONSEC__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN3_CFG_HNONSEC__CFG_HNONSEC__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_CHAN3_CFG_HNONSEC__CFG_HNONSEC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AT_DMA_CHAN3_CFG_HNONSEC__CFG_HNONSEC__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AT_DMA_CHAN3_CFG_HNONSEC__CFG_HNONSEC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_CHAN3_CFG_HNONSEC__CFG_HNONSEC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_CHAN3_CFG_HNONSEC__CFG_HNONSEC__RESET_VALUE 0x00000001U +/** @} */ +#define AT_DMA_CHAN3_CFG_HNONSEC__TYPE uint32_t +#define AT_DMA_CHAN3_CFG_HNONSEC__READ 0x00000001U +#define AT_DMA_CHAN3_CFG_HNONSEC__WRITE 0x00000001U +#define AT_DMA_CHAN3_CFG_HNONSEC__PRESERVED 0x00000000U +#define AT_DMA_CHAN3_CFG_HNONSEC__RESET_VALUE 0x00000001U + +#endif /* __AT_DMA_CHAN3_CFG_HNONSEC_MACRO__ */ + +/** @} end of chan3_cfg_hnonsec */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_err_interrupt_dly */ +/** + * @defgroup at_ahb_dma_regs_core_err_interrupt_dly err_interrupt_dly + * @brief err interrupt delayed in cycles definitions. + * @{ + */ +#ifndef __AT_DMA_ERR_INTERRUPT_DLY_MACRO__ +#define __AT_DMA_ERR_INTERRUPT_DLY_MACRO__ + +/* macros for field delay_amnt */ +/** + * @defgroup at_ahb_dma_regs_core_delay_amnt_field delay_amnt_field + * @brief macros for field delay_amnt + * @details number of cycles to delay the error interrupt event. Without this delay the interrupt may come up immediately after the go trigger leaving CPU no time to go into WFI. + * @{ + */ +#define AT_DMA_ERR_INTERRUPT_DLY__DELAY_AMNT__SHIFT 0 +#define AT_DMA_ERR_INTERRUPT_DLY__DELAY_AMNT__WIDTH 8 +#define AT_DMA_ERR_INTERRUPT_DLY__DELAY_AMNT__MASK 0x000000ffU +#define AT_DMA_ERR_INTERRUPT_DLY__DELAY_AMNT__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define AT_DMA_ERR_INTERRUPT_DLY__DELAY_AMNT__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define AT_DMA_ERR_INTERRUPT_DLY__DELAY_AMNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define AT_DMA_ERR_INTERRUPT_DLY__DELAY_AMNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define AT_DMA_ERR_INTERRUPT_DLY__DELAY_AMNT__RESET_VALUE 0x0000000aU +/** @} */ +#define AT_DMA_ERR_INTERRUPT_DLY__TYPE uint32_t +#define AT_DMA_ERR_INTERRUPT_DLY__READ 0x000000ffU +#define AT_DMA_ERR_INTERRUPT_DLY__WRITE 0x000000ffU +#define AT_DMA_ERR_INTERRUPT_DLY__PRESERVED 0x00000000U +#define AT_DMA_ERR_INTERRUPT_DLY__RESET_VALUE 0x0000000aU + +#endif /* __AT_DMA_ERR_INTERRUPT_DLY_MACRO__ */ + +/** @} end of err_interrupt_dly */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_arbiter_ctrl */ +/** + * @defgroup at_ahb_dma_regs_core_arbiter_ctrl arbiter_ctrl + * @brief Contains register fields associated with arbiter_ctrl. definitions. + * @{ + */ +#ifndef __AT_DMA_ARBITER_CTRL_MACRO__ +#define __AT_DMA_ARBITER_CTRL_MACRO__ + +/* macros for field priority_en */ +/** + * @defgroup at_ahb_dma_regs_core_priority_en_field priority_en_field + * @brief macros for field priority_en + * @details 0= no priority 1=lower numbered channel has higher priority when the bus owernership is relinquished. + * @{ + */ +#define AT_DMA_ARBITER_CTRL__PRIORITY_EN__SHIFT 0 +#define AT_DMA_ARBITER_CTRL__PRIORITY_EN__WIDTH 1 +#define AT_DMA_ARBITER_CTRL__PRIORITY_EN__MASK 0x00000001U +#define AT_DMA_ARBITER_CTRL__PRIORITY_EN__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_ARBITER_CTRL__PRIORITY_EN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_DMA_ARBITER_CTRL__PRIORITY_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AT_DMA_ARBITER_CTRL__PRIORITY_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AT_DMA_ARBITER_CTRL__PRIORITY_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_DMA_ARBITER_CTRL__PRIORITY_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_DMA_ARBITER_CTRL__PRIORITY_EN__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_ARBITER_CTRL__TYPE uint32_t +#define AT_DMA_ARBITER_CTRL__READ 0x00000001U +#define AT_DMA_ARBITER_CTRL__WRITE 0x00000001U +#define AT_DMA_ARBITER_CTRL__PRESERVED 0x00000000U +#define AT_DMA_ARBITER_CTRL__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_ARBITER_CTRL_MACRO__ */ + +/** @} end of arbiter_ctrl */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_arbiter_grant_stat */ +/** + * @defgroup at_ahb_dma_regs_core_arbiter_grant_stat arbiter_grant_stat + * @brief Contains register fields associated with arbiter_grant_stat. definitions. + * @{ + */ +#ifndef __AT_DMA_ARBITER_GRANT_STAT_MACRO__ +#define __AT_DMA_ARBITER_GRANT_STAT_MACRO__ + +/* macros for field chanx_bus_granted */ +/** + * @defgroup at_ahb_dma_regs_core_chanx_bus_granted_field chanx_bus_granted_field + * @brief macros for field chanx_bus_granted + * @details one-hot signal indicating channel with AHB bus ownership. + * @{ + */ +#define AT_DMA_ARBITER_GRANT_STAT__CHANX_BUS_GRANTED__SHIFT 0 +#define AT_DMA_ARBITER_GRANT_STAT__CHANX_BUS_GRANTED__WIDTH 4 +#define AT_DMA_ARBITER_GRANT_STAT__CHANX_BUS_GRANTED__MASK 0x0000000fU +#define AT_DMA_ARBITER_GRANT_STAT__CHANX_BUS_GRANTED__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define AT_DMA_ARBITER_GRANT_STAT__CHANX_BUS_GRANTED__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_ARBITER_GRANT_STAT__TYPE uint32_t +#define AT_DMA_ARBITER_GRANT_STAT__READ 0x0000000fU +#define AT_DMA_ARBITER_GRANT_STAT__PRESERVED 0x00000000U +#define AT_DMA_ARBITER_GRANT_STAT__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_ARBITER_GRANT_STAT_MACRO__ */ + +/** @} end of arbiter_grant_stat */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_diagcntl */ +/** + * @defgroup at_ahb_dma_regs_core_diagcntl diagcntl + * @brief Contains register fields associated with diagcntl. definitions. + * @{ + */ +#ifndef __AT_DMA_DIAGCNTL_MACRO__ +#define __AT_DMA_DIAGCNTL_MACRO__ + +/* macros for field diag3 */ +/** + * @defgroup at_ahb_dma_regs_core_diag3_field diag3_field + * @brief macros for field diag3 + * @details selects a group of signal to drive dbg[7:0]. + * @{ + */ +#define AT_DMA_DIAGCNTL__DIAG3__SHIFT 0 +#define AT_DMA_DIAGCNTL__DIAG3__WIDTH 2 +#define AT_DMA_DIAGCNTL__DIAG3__MASK 0x00000003U +#define AT_DMA_DIAGCNTL__DIAG3__READ(src) ((uint32_t)(src) & 0x00000003U) +#define AT_DMA_DIAGCNTL__DIAG3__WRITE(src) ((uint32_t)(src) & 0x00000003U) +#define AT_DMA_DIAGCNTL__DIAG3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define AT_DMA_DIAGCNTL__DIAG3__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define AT_DMA_DIAGCNTL__DIAG3__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field diag2 */ +/** + * @defgroup at_ahb_dma_regs_core_diag2_field diag2_field + * @brief macros for field diag2 + * @details selects a group of signal to drive dbg[15:8]. + * @{ + */ +#define AT_DMA_DIAGCNTL__DIAG2__SHIFT 8 +#define AT_DMA_DIAGCNTL__DIAG2__WIDTH 2 +#define AT_DMA_DIAGCNTL__DIAG2__MASK 0x00000300U +#define AT_DMA_DIAGCNTL__DIAG2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000300U) >> 8) +#define AT_DMA_DIAGCNTL__DIAG2__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000300U) +#define AT_DMA_DIAGCNTL__DIAG2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((uint32_t)(src) <<\ + 8) & 0x00000300U) +#define AT_DMA_DIAGCNTL__DIAG2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000300U))) +#define AT_DMA_DIAGCNTL__DIAG2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field diag1 */ +/** + * @defgroup at_ahb_dma_regs_core_diag1_field diag1_field + * @brief macros for field diag1 + * @details selects a group of signal to drive dbg[23:16]. + * @{ + */ +#define AT_DMA_DIAGCNTL__DIAG1__SHIFT 16 +#define AT_DMA_DIAGCNTL__DIAG1__WIDTH 2 +#define AT_DMA_DIAGCNTL__DIAG1__MASK 0x00030000U +#define AT_DMA_DIAGCNTL__DIAG1__READ(src) \ + (((uint32_t)(src)\ + & 0x00030000U) >> 16) +#define AT_DMA_DIAGCNTL__DIAG1__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00030000U) +#define AT_DMA_DIAGCNTL__DIAG1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00030000U) | (((uint32_t)(src) <<\ + 16) & 0x00030000U) +#define AT_DMA_DIAGCNTL__DIAG1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00030000U))) +#define AT_DMA_DIAGCNTL__DIAG1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field diag0 */ +/** + * @defgroup at_ahb_dma_regs_core_diag0_field diag0_field + * @brief macros for field diag0 + * @details selects a group of signal to drive dbg[31:24]. + * @{ + */ +#define AT_DMA_DIAGCNTL__DIAG0__SHIFT 24 +#define AT_DMA_DIAGCNTL__DIAG0__WIDTH 2 +#define AT_DMA_DIAGCNTL__DIAG0__MASK 0x03000000U +#define AT_DMA_DIAGCNTL__DIAG0__READ(src) \ + (((uint32_t)(src)\ + & 0x03000000U) >> 24) +#define AT_DMA_DIAGCNTL__DIAG0__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x03000000U) +#define AT_DMA_DIAGCNTL__DIAG0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((uint32_t)(src) <<\ + 24) & 0x03000000U) +#define AT_DMA_DIAGCNTL__DIAG0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x03000000U))) +#define AT_DMA_DIAGCNTL__DIAG0__RESET_VALUE 0x00000000U +/** @} */ +#define AT_DMA_DIAGCNTL__TYPE uint32_t +#define AT_DMA_DIAGCNTL__READ 0x03030303U +#define AT_DMA_DIAGCNTL__WRITE 0x03030303U +#define AT_DMA_DIAGCNTL__PRESERVED 0x00000000U +#define AT_DMA_DIAGCNTL__RESET_VALUE 0x00000000U + +#endif /* __AT_DMA_DIAGCNTL_MACRO__ */ + +/** @} end of diagcntl */ + +/* macros for BlueprintGlobalNameSpace::AT_DMA_id */ +/** + * @defgroup at_ahb_dma_regs_core_id id + * @brief Contains register fields associated with id. definitions. + * @{ + */ +#ifndef __AT_DMA_ID_MACRO__ +#define __AT_DMA_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_ahb_dma_regs_core_id_field id_field + * @brief macros for field id + * @details 'DMA ' + * @{ + */ +#define AT_DMA_ID__ID__SHIFT 0 +#define AT_DMA_ID__ID__WIDTH 32 +#define AT_DMA_ID__ID__MASK 0xffffffffU +#define AT_DMA_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_DMA_ID__ID__RESET_VALUE 0x444d4120U +/** @} */ +#define AT_DMA_ID__TYPE uint32_t +#define AT_DMA_ID__READ 0xffffffffU +#define AT_DMA_ID__PRESERVED 0x00000000U +#define AT_DMA_ID__RESET_VALUE 0x444d4120U + +#endif /* __AT_DMA_ID_MACRO__ */ + +/** @} end of id */ + +/** @} end of AT_AHB_DMA_REGS_CORE */ +#endif /* __REG_AT_AHB_DMA_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_ahb_prrf_regs_core_macro.h b/ATM33xx-5/include/reg/at_ahb_prrf_regs_core_macro.h new file mode 100644 index 0000000..1f1bcea --- /dev/null +++ b/ATM33xx-5/include/reg/at_ahb_prrf_regs_core_macro.h @@ -0,0 +1,3446 @@ +/* */ +/* File: at_ahb_prrf_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_ahb_prrf_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_AHB_PRRF_REGS_CORE_H__ +#define __REG_AT_AHB_PRRF_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_AHB_PRRF_REGS_CORE at_ahb_prrf_regs_core + * @ingroup AT_REG + * @brief at_ahb_prrf_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch_tag0 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch_tag0 patch_tag0 + * @brief Contains register fields associated with patch_tag0. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH_TAG0_MACRO__ +#define __AT_PRRF_PATCH_TAG0_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_ahb_prrf_regs_core_addr_field addr_field + * @brief macros for field addr + * @{ + */ +#define AT_PRRF_PATCH_TAG0__ADDR__SHIFT 0 +#define AT_PRRF_PATCH_TAG0__ADDR__WIDTH 22 +#define AT_PRRF_PATCH_TAG0__ADDR__MASK 0x003fffffU +#define AT_PRRF_PATCH_TAG0__ADDR__READ(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG0__ADDR__WRITE(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG0__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((uint32_t)(src) &\ + 0x003fffffU) +#define AT_PRRF_PATCH_TAG0__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x003fffffU))) +#define AT_PRRF_PATCH_TAG0__ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nword */ +/** + * @defgroup at_ahb_prrf_regs_core_nword_field nword_field + * @brief macros for field nword + * @{ + */ +#define AT_PRRF_PATCH_TAG0__NWORD__SHIFT 30 +#define AT_PRRF_PATCH_TAG0__NWORD__WIDTH 2 +#define AT_PRRF_PATCH_TAG0__NWORD__MASK 0xc0000000U +#define AT_PRRF_PATCH_TAG0__NWORD__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define AT_PRRF_PATCH_TAG0__NWORD__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG0__NWORD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG0__NWORD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define AT_PRRF_PATCH_TAG0__NWORD__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH_TAG0__TYPE uint32_t +#define AT_PRRF_PATCH_TAG0__READ 0xc03fffffU +#define AT_PRRF_PATCH_TAG0__WRITE 0xc03fffffU +#define AT_PRRF_PATCH_TAG0__PRESERVED 0x00000000U +#define AT_PRRF_PATCH_TAG0__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH_TAG0_MACRO__ */ + +/** @} end of patch_tag0 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch_tag1 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch_tag1 patch_tag1 + * @brief Contains register fields associated with patch_tag1. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH_TAG1_MACRO__ +#define __AT_PRRF_PATCH_TAG1_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_ahb_prrf_regs_core_addr_field addr_field + * @brief macros for field addr + * @{ + */ +#define AT_PRRF_PATCH_TAG1__ADDR__SHIFT 0 +#define AT_PRRF_PATCH_TAG1__ADDR__WIDTH 22 +#define AT_PRRF_PATCH_TAG1__ADDR__MASK 0x003fffffU +#define AT_PRRF_PATCH_TAG1__ADDR__READ(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG1__ADDR__WRITE(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG1__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((uint32_t)(src) &\ + 0x003fffffU) +#define AT_PRRF_PATCH_TAG1__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x003fffffU))) +#define AT_PRRF_PATCH_TAG1__ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nword */ +/** + * @defgroup at_ahb_prrf_regs_core_nword_field nword_field + * @brief macros for field nword + * @{ + */ +#define AT_PRRF_PATCH_TAG1__NWORD__SHIFT 30 +#define AT_PRRF_PATCH_TAG1__NWORD__WIDTH 2 +#define AT_PRRF_PATCH_TAG1__NWORD__MASK 0xc0000000U +#define AT_PRRF_PATCH_TAG1__NWORD__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define AT_PRRF_PATCH_TAG1__NWORD__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG1__NWORD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG1__NWORD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define AT_PRRF_PATCH_TAG1__NWORD__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH_TAG1__TYPE uint32_t +#define AT_PRRF_PATCH_TAG1__READ 0xc03fffffU +#define AT_PRRF_PATCH_TAG1__WRITE 0xc03fffffU +#define AT_PRRF_PATCH_TAG1__PRESERVED 0x00000000U +#define AT_PRRF_PATCH_TAG1__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH_TAG1_MACRO__ */ + +/** @} end of patch_tag1 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch_tag2 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch_tag2 patch_tag2 + * @brief Contains register fields associated with patch_tag2. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH_TAG2_MACRO__ +#define __AT_PRRF_PATCH_TAG2_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_ahb_prrf_regs_core_addr_field addr_field + * @brief macros for field addr + * @{ + */ +#define AT_PRRF_PATCH_TAG2__ADDR__SHIFT 0 +#define AT_PRRF_PATCH_TAG2__ADDR__WIDTH 22 +#define AT_PRRF_PATCH_TAG2__ADDR__MASK 0x003fffffU +#define AT_PRRF_PATCH_TAG2__ADDR__READ(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG2__ADDR__WRITE(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG2__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((uint32_t)(src) &\ + 0x003fffffU) +#define AT_PRRF_PATCH_TAG2__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x003fffffU))) +#define AT_PRRF_PATCH_TAG2__ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nword */ +/** + * @defgroup at_ahb_prrf_regs_core_nword_field nword_field + * @brief macros for field nword + * @{ + */ +#define AT_PRRF_PATCH_TAG2__NWORD__SHIFT 30 +#define AT_PRRF_PATCH_TAG2__NWORD__WIDTH 2 +#define AT_PRRF_PATCH_TAG2__NWORD__MASK 0xc0000000U +#define AT_PRRF_PATCH_TAG2__NWORD__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define AT_PRRF_PATCH_TAG2__NWORD__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG2__NWORD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG2__NWORD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define AT_PRRF_PATCH_TAG2__NWORD__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH_TAG2__TYPE uint32_t +#define AT_PRRF_PATCH_TAG2__READ 0xc03fffffU +#define AT_PRRF_PATCH_TAG2__WRITE 0xc03fffffU +#define AT_PRRF_PATCH_TAG2__PRESERVED 0x00000000U +#define AT_PRRF_PATCH_TAG2__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH_TAG2_MACRO__ */ + +/** @} end of patch_tag2 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch_tag3 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch_tag3 patch_tag3 + * @brief Contains register fields associated with patch_tag3. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH_TAG3_MACRO__ +#define __AT_PRRF_PATCH_TAG3_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_ahb_prrf_regs_core_addr_field addr_field + * @brief macros for field addr + * @{ + */ +#define AT_PRRF_PATCH_TAG3__ADDR__SHIFT 0 +#define AT_PRRF_PATCH_TAG3__ADDR__WIDTH 22 +#define AT_PRRF_PATCH_TAG3__ADDR__MASK 0x003fffffU +#define AT_PRRF_PATCH_TAG3__ADDR__READ(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG3__ADDR__WRITE(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG3__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((uint32_t)(src) &\ + 0x003fffffU) +#define AT_PRRF_PATCH_TAG3__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x003fffffU))) +#define AT_PRRF_PATCH_TAG3__ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nword */ +/** + * @defgroup at_ahb_prrf_regs_core_nword_field nword_field + * @brief macros for field nword + * @{ + */ +#define AT_PRRF_PATCH_TAG3__NWORD__SHIFT 30 +#define AT_PRRF_PATCH_TAG3__NWORD__WIDTH 2 +#define AT_PRRF_PATCH_TAG3__NWORD__MASK 0xc0000000U +#define AT_PRRF_PATCH_TAG3__NWORD__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define AT_PRRF_PATCH_TAG3__NWORD__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG3__NWORD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG3__NWORD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define AT_PRRF_PATCH_TAG3__NWORD__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH_TAG3__TYPE uint32_t +#define AT_PRRF_PATCH_TAG3__READ 0xc03fffffU +#define AT_PRRF_PATCH_TAG3__WRITE 0xc03fffffU +#define AT_PRRF_PATCH_TAG3__PRESERVED 0x00000000U +#define AT_PRRF_PATCH_TAG3__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH_TAG3_MACRO__ */ + +/** @} end of patch_tag3 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch_tag4 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch_tag4 patch_tag4 + * @brief Contains register fields associated with patch_tag4. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH_TAG4_MACRO__ +#define __AT_PRRF_PATCH_TAG4_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_ahb_prrf_regs_core_addr_field addr_field + * @brief macros for field addr + * @{ + */ +#define AT_PRRF_PATCH_TAG4__ADDR__SHIFT 0 +#define AT_PRRF_PATCH_TAG4__ADDR__WIDTH 22 +#define AT_PRRF_PATCH_TAG4__ADDR__MASK 0x003fffffU +#define AT_PRRF_PATCH_TAG4__ADDR__READ(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG4__ADDR__WRITE(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG4__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((uint32_t)(src) &\ + 0x003fffffU) +#define AT_PRRF_PATCH_TAG4__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x003fffffU))) +#define AT_PRRF_PATCH_TAG4__ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nword */ +/** + * @defgroup at_ahb_prrf_regs_core_nword_field nword_field + * @brief macros for field nword + * @{ + */ +#define AT_PRRF_PATCH_TAG4__NWORD__SHIFT 30 +#define AT_PRRF_PATCH_TAG4__NWORD__WIDTH 2 +#define AT_PRRF_PATCH_TAG4__NWORD__MASK 0xc0000000U +#define AT_PRRF_PATCH_TAG4__NWORD__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define AT_PRRF_PATCH_TAG4__NWORD__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG4__NWORD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG4__NWORD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define AT_PRRF_PATCH_TAG4__NWORD__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH_TAG4__TYPE uint32_t +#define AT_PRRF_PATCH_TAG4__READ 0xc03fffffU +#define AT_PRRF_PATCH_TAG4__WRITE 0xc03fffffU +#define AT_PRRF_PATCH_TAG4__PRESERVED 0x00000000U +#define AT_PRRF_PATCH_TAG4__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH_TAG4_MACRO__ */ + +/** @} end of patch_tag4 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch_tag5 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch_tag5 patch_tag5 + * @brief Contains register fields associated with patch_tag5. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH_TAG5_MACRO__ +#define __AT_PRRF_PATCH_TAG5_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_ahb_prrf_regs_core_addr_field addr_field + * @brief macros for field addr + * @{ + */ +#define AT_PRRF_PATCH_TAG5__ADDR__SHIFT 0 +#define AT_PRRF_PATCH_TAG5__ADDR__WIDTH 22 +#define AT_PRRF_PATCH_TAG5__ADDR__MASK 0x003fffffU +#define AT_PRRF_PATCH_TAG5__ADDR__READ(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG5__ADDR__WRITE(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG5__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((uint32_t)(src) &\ + 0x003fffffU) +#define AT_PRRF_PATCH_TAG5__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x003fffffU))) +#define AT_PRRF_PATCH_TAG5__ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nword */ +/** + * @defgroup at_ahb_prrf_regs_core_nword_field nword_field + * @brief macros for field nword + * @{ + */ +#define AT_PRRF_PATCH_TAG5__NWORD__SHIFT 30 +#define AT_PRRF_PATCH_TAG5__NWORD__WIDTH 2 +#define AT_PRRF_PATCH_TAG5__NWORD__MASK 0xc0000000U +#define AT_PRRF_PATCH_TAG5__NWORD__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define AT_PRRF_PATCH_TAG5__NWORD__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG5__NWORD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG5__NWORD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define AT_PRRF_PATCH_TAG5__NWORD__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH_TAG5__TYPE uint32_t +#define AT_PRRF_PATCH_TAG5__READ 0xc03fffffU +#define AT_PRRF_PATCH_TAG5__WRITE 0xc03fffffU +#define AT_PRRF_PATCH_TAG5__PRESERVED 0x00000000U +#define AT_PRRF_PATCH_TAG5__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH_TAG5_MACRO__ */ + +/** @} end of patch_tag5 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch_tag6 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch_tag6 patch_tag6 + * @brief Contains register fields associated with patch_tag6. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH_TAG6_MACRO__ +#define __AT_PRRF_PATCH_TAG6_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_ahb_prrf_regs_core_addr_field addr_field + * @brief macros for field addr + * @{ + */ +#define AT_PRRF_PATCH_TAG6__ADDR__SHIFT 0 +#define AT_PRRF_PATCH_TAG6__ADDR__WIDTH 22 +#define AT_PRRF_PATCH_TAG6__ADDR__MASK 0x003fffffU +#define AT_PRRF_PATCH_TAG6__ADDR__READ(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG6__ADDR__WRITE(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG6__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((uint32_t)(src) &\ + 0x003fffffU) +#define AT_PRRF_PATCH_TAG6__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x003fffffU))) +#define AT_PRRF_PATCH_TAG6__ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nword */ +/** + * @defgroup at_ahb_prrf_regs_core_nword_field nword_field + * @brief macros for field nword + * @{ + */ +#define AT_PRRF_PATCH_TAG6__NWORD__SHIFT 30 +#define AT_PRRF_PATCH_TAG6__NWORD__WIDTH 2 +#define AT_PRRF_PATCH_TAG6__NWORD__MASK 0xc0000000U +#define AT_PRRF_PATCH_TAG6__NWORD__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define AT_PRRF_PATCH_TAG6__NWORD__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG6__NWORD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG6__NWORD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define AT_PRRF_PATCH_TAG6__NWORD__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH_TAG6__TYPE uint32_t +#define AT_PRRF_PATCH_TAG6__READ 0xc03fffffU +#define AT_PRRF_PATCH_TAG6__WRITE 0xc03fffffU +#define AT_PRRF_PATCH_TAG6__PRESERVED 0x00000000U +#define AT_PRRF_PATCH_TAG6__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH_TAG6_MACRO__ */ + +/** @} end of patch_tag6 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch_tag7 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch_tag7 patch_tag7 + * @brief Contains register fields associated with patch_tag7. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH_TAG7_MACRO__ +#define __AT_PRRF_PATCH_TAG7_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_ahb_prrf_regs_core_addr_field addr_field + * @brief macros for field addr + * @{ + */ +#define AT_PRRF_PATCH_TAG7__ADDR__SHIFT 0 +#define AT_PRRF_PATCH_TAG7__ADDR__WIDTH 22 +#define AT_PRRF_PATCH_TAG7__ADDR__MASK 0x003fffffU +#define AT_PRRF_PATCH_TAG7__ADDR__READ(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG7__ADDR__WRITE(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG7__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((uint32_t)(src) &\ + 0x003fffffU) +#define AT_PRRF_PATCH_TAG7__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x003fffffU))) +#define AT_PRRF_PATCH_TAG7__ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nword */ +/** + * @defgroup at_ahb_prrf_regs_core_nword_field nword_field + * @brief macros for field nword + * @{ + */ +#define AT_PRRF_PATCH_TAG7__NWORD__SHIFT 30 +#define AT_PRRF_PATCH_TAG7__NWORD__WIDTH 2 +#define AT_PRRF_PATCH_TAG7__NWORD__MASK 0xc0000000U +#define AT_PRRF_PATCH_TAG7__NWORD__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define AT_PRRF_PATCH_TAG7__NWORD__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG7__NWORD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG7__NWORD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define AT_PRRF_PATCH_TAG7__NWORD__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH_TAG7__TYPE uint32_t +#define AT_PRRF_PATCH_TAG7__READ 0xc03fffffU +#define AT_PRRF_PATCH_TAG7__WRITE 0xc03fffffU +#define AT_PRRF_PATCH_TAG7__PRESERVED 0x00000000U +#define AT_PRRF_PATCH_TAG7__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH_TAG7_MACRO__ */ + +/** @} end of patch_tag7 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch_tag8 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch_tag8 patch_tag8 + * @brief Contains register fields associated with patch_tag8. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH_TAG8_MACRO__ +#define __AT_PRRF_PATCH_TAG8_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_ahb_prrf_regs_core_addr_field addr_field + * @brief macros for field addr + * @{ + */ +#define AT_PRRF_PATCH_TAG8__ADDR__SHIFT 0 +#define AT_PRRF_PATCH_TAG8__ADDR__WIDTH 22 +#define AT_PRRF_PATCH_TAG8__ADDR__MASK 0x003fffffU +#define AT_PRRF_PATCH_TAG8__ADDR__READ(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG8__ADDR__WRITE(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG8__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((uint32_t)(src) &\ + 0x003fffffU) +#define AT_PRRF_PATCH_TAG8__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x003fffffU))) +#define AT_PRRF_PATCH_TAG8__ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nword */ +/** + * @defgroup at_ahb_prrf_regs_core_nword_field nword_field + * @brief macros for field nword + * @{ + */ +#define AT_PRRF_PATCH_TAG8__NWORD__SHIFT 30 +#define AT_PRRF_PATCH_TAG8__NWORD__WIDTH 2 +#define AT_PRRF_PATCH_TAG8__NWORD__MASK 0xc0000000U +#define AT_PRRF_PATCH_TAG8__NWORD__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define AT_PRRF_PATCH_TAG8__NWORD__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG8__NWORD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG8__NWORD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define AT_PRRF_PATCH_TAG8__NWORD__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH_TAG8__TYPE uint32_t +#define AT_PRRF_PATCH_TAG8__READ 0xc03fffffU +#define AT_PRRF_PATCH_TAG8__WRITE 0xc03fffffU +#define AT_PRRF_PATCH_TAG8__PRESERVED 0x00000000U +#define AT_PRRF_PATCH_TAG8__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH_TAG8_MACRO__ */ + +/** @} end of patch_tag8 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch_tag9 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch_tag9 patch_tag9 + * @brief Contains register fields associated with patch_tag9. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH_TAG9_MACRO__ +#define __AT_PRRF_PATCH_TAG9_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_ahb_prrf_regs_core_addr_field addr_field + * @brief macros for field addr + * @{ + */ +#define AT_PRRF_PATCH_TAG9__ADDR__SHIFT 0 +#define AT_PRRF_PATCH_TAG9__ADDR__WIDTH 22 +#define AT_PRRF_PATCH_TAG9__ADDR__MASK 0x003fffffU +#define AT_PRRF_PATCH_TAG9__ADDR__READ(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG9__ADDR__WRITE(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG9__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((uint32_t)(src) &\ + 0x003fffffU) +#define AT_PRRF_PATCH_TAG9__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x003fffffU))) +#define AT_PRRF_PATCH_TAG9__ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nword */ +/** + * @defgroup at_ahb_prrf_regs_core_nword_field nword_field + * @brief macros for field nword + * @{ + */ +#define AT_PRRF_PATCH_TAG9__NWORD__SHIFT 30 +#define AT_PRRF_PATCH_TAG9__NWORD__WIDTH 2 +#define AT_PRRF_PATCH_TAG9__NWORD__MASK 0xc0000000U +#define AT_PRRF_PATCH_TAG9__NWORD__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define AT_PRRF_PATCH_TAG9__NWORD__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG9__NWORD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG9__NWORD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define AT_PRRF_PATCH_TAG9__NWORD__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH_TAG9__TYPE uint32_t +#define AT_PRRF_PATCH_TAG9__READ 0xc03fffffU +#define AT_PRRF_PATCH_TAG9__WRITE 0xc03fffffU +#define AT_PRRF_PATCH_TAG9__PRESERVED 0x00000000U +#define AT_PRRF_PATCH_TAG9__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH_TAG9_MACRO__ */ + +/** @} end of patch_tag9 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch_tag10 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch_tag10 patch_tag10 + * @brief Contains register fields associated with patch_tag10. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH_TAG10_MACRO__ +#define __AT_PRRF_PATCH_TAG10_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_ahb_prrf_regs_core_addr_field addr_field + * @brief macros for field addr + * @{ + */ +#define AT_PRRF_PATCH_TAG10__ADDR__SHIFT 0 +#define AT_PRRF_PATCH_TAG10__ADDR__WIDTH 22 +#define AT_PRRF_PATCH_TAG10__ADDR__MASK 0x003fffffU +#define AT_PRRF_PATCH_TAG10__ADDR__READ(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG10__ADDR__WRITE(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG10__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((uint32_t)(src) &\ + 0x003fffffU) +#define AT_PRRF_PATCH_TAG10__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x003fffffU))) +#define AT_PRRF_PATCH_TAG10__ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nword */ +/** + * @defgroup at_ahb_prrf_regs_core_nword_field nword_field + * @brief macros for field nword + * @{ + */ +#define AT_PRRF_PATCH_TAG10__NWORD__SHIFT 30 +#define AT_PRRF_PATCH_TAG10__NWORD__WIDTH 2 +#define AT_PRRF_PATCH_TAG10__NWORD__MASK 0xc0000000U +#define AT_PRRF_PATCH_TAG10__NWORD__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define AT_PRRF_PATCH_TAG10__NWORD__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG10__NWORD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG10__NWORD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define AT_PRRF_PATCH_TAG10__NWORD__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH_TAG10__TYPE uint32_t +#define AT_PRRF_PATCH_TAG10__READ 0xc03fffffU +#define AT_PRRF_PATCH_TAG10__WRITE 0xc03fffffU +#define AT_PRRF_PATCH_TAG10__PRESERVED 0x00000000U +#define AT_PRRF_PATCH_TAG10__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH_TAG10_MACRO__ */ + +/** @} end of patch_tag10 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch_tag11 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch_tag11 patch_tag11 + * @brief Contains register fields associated with patch_tag11. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH_TAG11_MACRO__ +#define __AT_PRRF_PATCH_TAG11_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_ahb_prrf_regs_core_addr_field addr_field + * @brief macros for field addr + * @{ + */ +#define AT_PRRF_PATCH_TAG11__ADDR__SHIFT 0 +#define AT_PRRF_PATCH_TAG11__ADDR__WIDTH 22 +#define AT_PRRF_PATCH_TAG11__ADDR__MASK 0x003fffffU +#define AT_PRRF_PATCH_TAG11__ADDR__READ(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG11__ADDR__WRITE(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG11__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((uint32_t)(src) &\ + 0x003fffffU) +#define AT_PRRF_PATCH_TAG11__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x003fffffU))) +#define AT_PRRF_PATCH_TAG11__ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nword */ +/** + * @defgroup at_ahb_prrf_regs_core_nword_field nword_field + * @brief macros for field nword + * @{ + */ +#define AT_PRRF_PATCH_TAG11__NWORD__SHIFT 30 +#define AT_PRRF_PATCH_TAG11__NWORD__WIDTH 2 +#define AT_PRRF_PATCH_TAG11__NWORD__MASK 0xc0000000U +#define AT_PRRF_PATCH_TAG11__NWORD__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define AT_PRRF_PATCH_TAG11__NWORD__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG11__NWORD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG11__NWORD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define AT_PRRF_PATCH_TAG11__NWORD__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH_TAG11__TYPE uint32_t +#define AT_PRRF_PATCH_TAG11__READ 0xc03fffffU +#define AT_PRRF_PATCH_TAG11__WRITE 0xc03fffffU +#define AT_PRRF_PATCH_TAG11__PRESERVED 0x00000000U +#define AT_PRRF_PATCH_TAG11__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH_TAG11_MACRO__ */ + +/** @} end of patch_tag11 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch_tag12 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch_tag12 patch_tag12 + * @brief Contains register fields associated with patch_tag12. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH_TAG12_MACRO__ +#define __AT_PRRF_PATCH_TAG12_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_ahb_prrf_regs_core_addr_field addr_field + * @brief macros for field addr + * @{ + */ +#define AT_PRRF_PATCH_TAG12__ADDR__SHIFT 0 +#define AT_PRRF_PATCH_TAG12__ADDR__WIDTH 22 +#define AT_PRRF_PATCH_TAG12__ADDR__MASK 0x003fffffU +#define AT_PRRF_PATCH_TAG12__ADDR__READ(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG12__ADDR__WRITE(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG12__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((uint32_t)(src) &\ + 0x003fffffU) +#define AT_PRRF_PATCH_TAG12__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x003fffffU))) +#define AT_PRRF_PATCH_TAG12__ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nword */ +/** + * @defgroup at_ahb_prrf_regs_core_nword_field nword_field + * @brief macros for field nword + * @{ + */ +#define AT_PRRF_PATCH_TAG12__NWORD__SHIFT 30 +#define AT_PRRF_PATCH_TAG12__NWORD__WIDTH 2 +#define AT_PRRF_PATCH_TAG12__NWORD__MASK 0xc0000000U +#define AT_PRRF_PATCH_TAG12__NWORD__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define AT_PRRF_PATCH_TAG12__NWORD__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG12__NWORD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG12__NWORD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define AT_PRRF_PATCH_TAG12__NWORD__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH_TAG12__TYPE uint32_t +#define AT_PRRF_PATCH_TAG12__READ 0xc03fffffU +#define AT_PRRF_PATCH_TAG12__WRITE 0xc03fffffU +#define AT_PRRF_PATCH_TAG12__PRESERVED 0x00000000U +#define AT_PRRF_PATCH_TAG12__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH_TAG12_MACRO__ */ + +/** @} end of patch_tag12 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch_tag13 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch_tag13 patch_tag13 + * @brief Contains register fields associated with patch_tag13. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH_TAG13_MACRO__ +#define __AT_PRRF_PATCH_TAG13_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_ahb_prrf_regs_core_addr_field addr_field + * @brief macros for field addr + * @{ + */ +#define AT_PRRF_PATCH_TAG13__ADDR__SHIFT 0 +#define AT_PRRF_PATCH_TAG13__ADDR__WIDTH 22 +#define AT_PRRF_PATCH_TAG13__ADDR__MASK 0x003fffffU +#define AT_PRRF_PATCH_TAG13__ADDR__READ(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG13__ADDR__WRITE(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG13__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((uint32_t)(src) &\ + 0x003fffffU) +#define AT_PRRF_PATCH_TAG13__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x003fffffU))) +#define AT_PRRF_PATCH_TAG13__ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nword */ +/** + * @defgroup at_ahb_prrf_regs_core_nword_field nword_field + * @brief macros for field nword + * @{ + */ +#define AT_PRRF_PATCH_TAG13__NWORD__SHIFT 30 +#define AT_PRRF_PATCH_TAG13__NWORD__WIDTH 2 +#define AT_PRRF_PATCH_TAG13__NWORD__MASK 0xc0000000U +#define AT_PRRF_PATCH_TAG13__NWORD__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define AT_PRRF_PATCH_TAG13__NWORD__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG13__NWORD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG13__NWORD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define AT_PRRF_PATCH_TAG13__NWORD__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH_TAG13__TYPE uint32_t +#define AT_PRRF_PATCH_TAG13__READ 0xc03fffffU +#define AT_PRRF_PATCH_TAG13__WRITE 0xc03fffffU +#define AT_PRRF_PATCH_TAG13__PRESERVED 0x00000000U +#define AT_PRRF_PATCH_TAG13__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH_TAG13_MACRO__ */ + +/** @} end of patch_tag13 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch_tag14 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch_tag14 patch_tag14 + * @brief Contains register fields associated with patch_tag14. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH_TAG14_MACRO__ +#define __AT_PRRF_PATCH_TAG14_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_ahb_prrf_regs_core_addr_field addr_field + * @brief macros for field addr + * @{ + */ +#define AT_PRRF_PATCH_TAG14__ADDR__SHIFT 0 +#define AT_PRRF_PATCH_TAG14__ADDR__WIDTH 22 +#define AT_PRRF_PATCH_TAG14__ADDR__MASK 0x003fffffU +#define AT_PRRF_PATCH_TAG14__ADDR__READ(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG14__ADDR__WRITE(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG14__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((uint32_t)(src) &\ + 0x003fffffU) +#define AT_PRRF_PATCH_TAG14__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x003fffffU))) +#define AT_PRRF_PATCH_TAG14__ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nword */ +/** + * @defgroup at_ahb_prrf_regs_core_nword_field nword_field + * @brief macros for field nword + * @{ + */ +#define AT_PRRF_PATCH_TAG14__NWORD__SHIFT 30 +#define AT_PRRF_PATCH_TAG14__NWORD__WIDTH 2 +#define AT_PRRF_PATCH_TAG14__NWORD__MASK 0xc0000000U +#define AT_PRRF_PATCH_TAG14__NWORD__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define AT_PRRF_PATCH_TAG14__NWORD__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG14__NWORD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG14__NWORD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define AT_PRRF_PATCH_TAG14__NWORD__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH_TAG14__TYPE uint32_t +#define AT_PRRF_PATCH_TAG14__READ 0xc03fffffU +#define AT_PRRF_PATCH_TAG14__WRITE 0xc03fffffU +#define AT_PRRF_PATCH_TAG14__PRESERVED 0x00000000U +#define AT_PRRF_PATCH_TAG14__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH_TAG14_MACRO__ */ + +/** @} end of patch_tag14 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch_tag15 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch_tag15 patch_tag15 + * @brief Contains register fields associated with patch_tag15. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH_TAG15_MACRO__ +#define __AT_PRRF_PATCH_TAG15_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_ahb_prrf_regs_core_addr_field addr_field + * @brief macros for field addr + * @{ + */ +#define AT_PRRF_PATCH_TAG15__ADDR__SHIFT 0 +#define AT_PRRF_PATCH_TAG15__ADDR__WIDTH 22 +#define AT_PRRF_PATCH_TAG15__ADDR__MASK 0x003fffffU +#define AT_PRRF_PATCH_TAG15__ADDR__READ(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG15__ADDR__WRITE(src) ((uint32_t)(src) & 0x003fffffU) +#define AT_PRRF_PATCH_TAG15__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((uint32_t)(src) &\ + 0x003fffffU) +#define AT_PRRF_PATCH_TAG15__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x003fffffU))) +#define AT_PRRF_PATCH_TAG15__ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nword */ +/** + * @defgroup at_ahb_prrf_regs_core_nword_field nword_field + * @brief macros for field nword + * @{ + */ +#define AT_PRRF_PATCH_TAG15__NWORD__SHIFT 30 +#define AT_PRRF_PATCH_TAG15__NWORD__WIDTH 2 +#define AT_PRRF_PATCH_TAG15__NWORD__MASK 0xc0000000U +#define AT_PRRF_PATCH_TAG15__NWORD__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define AT_PRRF_PATCH_TAG15__NWORD__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG15__NWORD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define AT_PRRF_PATCH_TAG15__NWORD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define AT_PRRF_PATCH_TAG15__NWORD__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH_TAG15__TYPE uint32_t +#define AT_PRRF_PATCH_TAG15__READ 0xc03fffffU +#define AT_PRRF_PATCH_TAG15__WRITE 0xc03fffffU +#define AT_PRRF_PATCH_TAG15__PRESERVED 0x00000000U +#define AT_PRRF_PATCH_TAG15__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH_TAG15_MACRO__ */ + +/** @} end of patch_tag15 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch0 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch0 patch0 + * @brief Contains register fields associated with patch0. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH0_MACRO__ +#define __AT_PRRF_PATCH0_MACRO__ + +/* macros for field patch0 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch0_field patch0_field + * @brief macros for field patch0 + * @{ + */ +#define AT_PRRF_PATCH0__PATCH0__SHIFT 0 +#define AT_PRRF_PATCH0__PATCH0__WIDTH 32 +#define AT_PRRF_PATCH0__PATCH0__MASK 0xffffffffU +#define AT_PRRF_PATCH0__PATCH0__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH0__PATCH0__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH0__PATCH0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH0__PATCH0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH0__PATCH0__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH0__TYPE uint32_t +#define AT_PRRF_PATCH0__READ 0xffffffffU +#define AT_PRRF_PATCH0__WRITE 0xffffffffU +#define AT_PRRF_PATCH0__PRESERVED 0x00000000U +#define AT_PRRF_PATCH0__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH0_MACRO__ */ + +/** @} end of patch0 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch1 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch1 patch1 + * @brief Contains register fields associated with patch1. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH1_MACRO__ +#define __AT_PRRF_PATCH1_MACRO__ + +/* macros for field patch1 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch1_field patch1_field + * @brief macros for field patch1 + * @{ + */ +#define AT_PRRF_PATCH1__PATCH1__SHIFT 0 +#define AT_PRRF_PATCH1__PATCH1__WIDTH 32 +#define AT_PRRF_PATCH1__PATCH1__MASK 0xffffffffU +#define AT_PRRF_PATCH1__PATCH1__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH1__PATCH1__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH1__PATCH1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH1__PATCH1__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH1__PATCH1__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH1__TYPE uint32_t +#define AT_PRRF_PATCH1__READ 0xffffffffU +#define AT_PRRF_PATCH1__WRITE 0xffffffffU +#define AT_PRRF_PATCH1__PRESERVED 0x00000000U +#define AT_PRRF_PATCH1__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH1_MACRO__ */ + +/** @} end of patch1 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch2 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch2 patch2 + * @brief Contains register fields associated with patch2. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH2_MACRO__ +#define __AT_PRRF_PATCH2_MACRO__ + +/* macros for field patch2 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch2_field patch2_field + * @brief macros for field patch2 + * @{ + */ +#define AT_PRRF_PATCH2__PATCH2__SHIFT 0 +#define AT_PRRF_PATCH2__PATCH2__WIDTH 32 +#define AT_PRRF_PATCH2__PATCH2__MASK 0xffffffffU +#define AT_PRRF_PATCH2__PATCH2__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH2__PATCH2__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH2__PATCH2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH2__PATCH2__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH2__PATCH2__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH2__TYPE uint32_t +#define AT_PRRF_PATCH2__READ 0xffffffffU +#define AT_PRRF_PATCH2__WRITE 0xffffffffU +#define AT_PRRF_PATCH2__PRESERVED 0x00000000U +#define AT_PRRF_PATCH2__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH2_MACRO__ */ + +/** @} end of patch2 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch3 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch3 patch3 + * @brief Contains register fields associated with patch3. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH3_MACRO__ +#define __AT_PRRF_PATCH3_MACRO__ + +/* macros for field patch3 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch3_field patch3_field + * @brief macros for field patch3 + * @{ + */ +#define AT_PRRF_PATCH3__PATCH3__SHIFT 0 +#define AT_PRRF_PATCH3__PATCH3__WIDTH 32 +#define AT_PRRF_PATCH3__PATCH3__MASK 0xffffffffU +#define AT_PRRF_PATCH3__PATCH3__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH3__PATCH3__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH3__PATCH3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH3__PATCH3__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH3__PATCH3__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH3__TYPE uint32_t +#define AT_PRRF_PATCH3__READ 0xffffffffU +#define AT_PRRF_PATCH3__WRITE 0xffffffffU +#define AT_PRRF_PATCH3__PRESERVED 0x00000000U +#define AT_PRRF_PATCH3__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH3_MACRO__ */ + +/** @} end of patch3 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch4 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch4 patch4 + * @brief Contains register fields associated with patch4. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH4_MACRO__ +#define __AT_PRRF_PATCH4_MACRO__ + +/* macros for field patch4 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch4_field patch4_field + * @brief macros for field patch4 + * @{ + */ +#define AT_PRRF_PATCH4__PATCH4__SHIFT 0 +#define AT_PRRF_PATCH4__PATCH4__WIDTH 32 +#define AT_PRRF_PATCH4__PATCH4__MASK 0xffffffffU +#define AT_PRRF_PATCH4__PATCH4__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH4__PATCH4__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH4__PATCH4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH4__PATCH4__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH4__PATCH4__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH4__TYPE uint32_t +#define AT_PRRF_PATCH4__READ 0xffffffffU +#define AT_PRRF_PATCH4__WRITE 0xffffffffU +#define AT_PRRF_PATCH4__PRESERVED 0x00000000U +#define AT_PRRF_PATCH4__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH4_MACRO__ */ + +/** @} end of patch4 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch5 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch5 patch5 + * @brief Contains register fields associated with patch5. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH5_MACRO__ +#define __AT_PRRF_PATCH5_MACRO__ + +/* macros for field patch5 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch5_field patch5_field + * @brief macros for field patch5 + * @{ + */ +#define AT_PRRF_PATCH5__PATCH5__SHIFT 0 +#define AT_PRRF_PATCH5__PATCH5__WIDTH 32 +#define AT_PRRF_PATCH5__PATCH5__MASK 0xffffffffU +#define AT_PRRF_PATCH5__PATCH5__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH5__PATCH5__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH5__PATCH5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH5__PATCH5__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH5__PATCH5__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH5__TYPE uint32_t +#define AT_PRRF_PATCH5__READ 0xffffffffU +#define AT_PRRF_PATCH5__WRITE 0xffffffffU +#define AT_PRRF_PATCH5__PRESERVED 0x00000000U +#define AT_PRRF_PATCH5__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH5_MACRO__ */ + +/** @} end of patch5 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch6 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch6 patch6 + * @brief Contains register fields associated with patch6. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH6_MACRO__ +#define __AT_PRRF_PATCH6_MACRO__ + +/* macros for field patch6 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch6_field patch6_field + * @brief macros for field patch6 + * @{ + */ +#define AT_PRRF_PATCH6__PATCH6__SHIFT 0 +#define AT_PRRF_PATCH6__PATCH6__WIDTH 32 +#define AT_PRRF_PATCH6__PATCH6__MASK 0xffffffffU +#define AT_PRRF_PATCH6__PATCH6__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH6__PATCH6__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH6__PATCH6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH6__PATCH6__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH6__PATCH6__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH6__TYPE uint32_t +#define AT_PRRF_PATCH6__READ 0xffffffffU +#define AT_PRRF_PATCH6__WRITE 0xffffffffU +#define AT_PRRF_PATCH6__PRESERVED 0x00000000U +#define AT_PRRF_PATCH6__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH6_MACRO__ */ + +/** @} end of patch6 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch7 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch7 patch7 + * @brief Contains register fields associated with patch7. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH7_MACRO__ +#define __AT_PRRF_PATCH7_MACRO__ + +/* macros for field patch7 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch7_field patch7_field + * @brief macros for field patch7 + * @{ + */ +#define AT_PRRF_PATCH7__PATCH7__SHIFT 0 +#define AT_PRRF_PATCH7__PATCH7__WIDTH 32 +#define AT_PRRF_PATCH7__PATCH7__MASK 0xffffffffU +#define AT_PRRF_PATCH7__PATCH7__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH7__PATCH7__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH7__PATCH7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH7__PATCH7__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH7__PATCH7__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH7__TYPE uint32_t +#define AT_PRRF_PATCH7__READ 0xffffffffU +#define AT_PRRF_PATCH7__WRITE 0xffffffffU +#define AT_PRRF_PATCH7__PRESERVED 0x00000000U +#define AT_PRRF_PATCH7__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH7_MACRO__ */ + +/** @} end of patch7 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch8 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch8 patch8 + * @brief Contains register fields associated with patch8. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH8_MACRO__ +#define __AT_PRRF_PATCH8_MACRO__ + +/* macros for field patch8 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch8_field patch8_field + * @brief macros for field patch8 + * @{ + */ +#define AT_PRRF_PATCH8__PATCH8__SHIFT 0 +#define AT_PRRF_PATCH8__PATCH8__WIDTH 32 +#define AT_PRRF_PATCH8__PATCH8__MASK 0xffffffffU +#define AT_PRRF_PATCH8__PATCH8__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH8__PATCH8__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH8__PATCH8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH8__PATCH8__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH8__PATCH8__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH8__TYPE uint32_t +#define AT_PRRF_PATCH8__READ 0xffffffffU +#define AT_PRRF_PATCH8__WRITE 0xffffffffU +#define AT_PRRF_PATCH8__PRESERVED 0x00000000U +#define AT_PRRF_PATCH8__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH8_MACRO__ */ + +/** @} end of patch8 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch9 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch9 patch9 + * @brief Contains register fields associated with patch9. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH9_MACRO__ +#define __AT_PRRF_PATCH9_MACRO__ + +/* macros for field patch9 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch9_field patch9_field + * @brief macros for field patch9 + * @{ + */ +#define AT_PRRF_PATCH9__PATCH9__SHIFT 0 +#define AT_PRRF_PATCH9__PATCH9__WIDTH 32 +#define AT_PRRF_PATCH9__PATCH9__MASK 0xffffffffU +#define AT_PRRF_PATCH9__PATCH9__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH9__PATCH9__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH9__PATCH9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH9__PATCH9__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH9__PATCH9__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH9__TYPE uint32_t +#define AT_PRRF_PATCH9__READ 0xffffffffU +#define AT_PRRF_PATCH9__WRITE 0xffffffffU +#define AT_PRRF_PATCH9__PRESERVED 0x00000000U +#define AT_PRRF_PATCH9__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH9_MACRO__ */ + +/** @} end of patch9 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch10 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch10 patch10 + * @brief Contains register fields associated with patch10. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH10_MACRO__ +#define __AT_PRRF_PATCH10_MACRO__ + +/* macros for field patch10 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch10_field patch10_field + * @brief macros for field patch10 + * @{ + */ +#define AT_PRRF_PATCH10__PATCH10__SHIFT 0 +#define AT_PRRF_PATCH10__PATCH10__WIDTH 32 +#define AT_PRRF_PATCH10__PATCH10__MASK 0xffffffffU +#define AT_PRRF_PATCH10__PATCH10__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH10__PATCH10__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH10__PATCH10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH10__PATCH10__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH10__PATCH10__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH10__TYPE uint32_t +#define AT_PRRF_PATCH10__READ 0xffffffffU +#define AT_PRRF_PATCH10__WRITE 0xffffffffU +#define AT_PRRF_PATCH10__PRESERVED 0x00000000U +#define AT_PRRF_PATCH10__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH10_MACRO__ */ + +/** @} end of patch10 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch11 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch11 patch11 + * @brief Contains register fields associated with patch11. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH11_MACRO__ +#define __AT_PRRF_PATCH11_MACRO__ + +/* macros for field patch11 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch11_field patch11_field + * @brief macros for field patch11 + * @{ + */ +#define AT_PRRF_PATCH11__PATCH11__SHIFT 0 +#define AT_PRRF_PATCH11__PATCH11__WIDTH 32 +#define AT_PRRF_PATCH11__PATCH11__MASK 0xffffffffU +#define AT_PRRF_PATCH11__PATCH11__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH11__PATCH11__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH11__PATCH11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH11__PATCH11__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH11__PATCH11__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH11__TYPE uint32_t +#define AT_PRRF_PATCH11__READ 0xffffffffU +#define AT_PRRF_PATCH11__WRITE 0xffffffffU +#define AT_PRRF_PATCH11__PRESERVED 0x00000000U +#define AT_PRRF_PATCH11__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH11_MACRO__ */ + +/** @} end of patch11 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch12 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch12 patch12 + * @brief Contains register fields associated with patch12. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH12_MACRO__ +#define __AT_PRRF_PATCH12_MACRO__ + +/* macros for field patch12 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch12_field patch12_field + * @brief macros for field patch12 + * @{ + */ +#define AT_PRRF_PATCH12__PATCH12__SHIFT 0 +#define AT_PRRF_PATCH12__PATCH12__WIDTH 32 +#define AT_PRRF_PATCH12__PATCH12__MASK 0xffffffffU +#define AT_PRRF_PATCH12__PATCH12__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH12__PATCH12__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH12__PATCH12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH12__PATCH12__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH12__PATCH12__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH12__TYPE uint32_t +#define AT_PRRF_PATCH12__READ 0xffffffffU +#define AT_PRRF_PATCH12__WRITE 0xffffffffU +#define AT_PRRF_PATCH12__PRESERVED 0x00000000U +#define AT_PRRF_PATCH12__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH12_MACRO__ */ + +/** @} end of patch12 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch13 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch13 patch13 + * @brief Contains register fields associated with patch13. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH13_MACRO__ +#define __AT_PRRF_PATCH13_MACRO__ + +/* macros for field patch13 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch13_field patch13_field + * @brief macros for field patch13 + * @{ + */ +#define AT_PRRF_PATCH13__PATCH13__SHIFT 0 +#define AT_PRRF_PATCH13__PATCH13__WIDTH 32 +#define AT_PRRF_PATCH13__PATCH13__MASK 0xffffffffU +#define AT_PRRF_PATCH13__PATCH13__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH13__PATCH13__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH13__PATCH13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH13__PATCH13__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH13__PATCH13__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH13__TYPE uint32_t +#define AT_PRRF_PATCH13__READ 0xffffffffU +#define AT_PRRF_PATCH13__WRITE 0xffffffffU +#define AT_PRRF_PATCH13__PRESERVED 0x00000000U +#define AT_PRRF_PATCH13__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH13_MACRO__ */ + +/** @} end of patch13 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch14 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch14 patch14 + * @brief Contains register fields associated with patch14. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH14_MACRO__ +#define __AT_PRRF_PATCH14_MACRO__ + +/* macros for field patch14 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch14_field patch14_field + * @brief macros for field patch14 + * @{ + */ +#define AT_PRRF_PATCH14__PATCH14__SHIFT 0 +#define AT_PRRF_PATCH14__PATCH14__WIDTH 32 +#define AT_PRRF_PATCH14__PATCH14__MASK 0xffffffffU +#define AT_PRRF_PATCH14__PATCH14__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH14__PATCH14__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH14__PATCH14__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH14__PATCH14__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH14__PATCH14__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH14__TYPE uint32_t +#define AT_PRRF_PATCH14__READ 0xffffffffU +#define AT_PRRF_PATCH14__WRITE 0xffffffffU +#define AT_PRRF_PATCH14__PRESERVED 0x00000000U +#define AT_PRRF_PATCH14__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH14_MACRO__ */ + +/** @} end of patch14 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch15 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch15 patch15 + * @brief Contains register fields associated with patch15. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH15_MACRO__ +#define __AT_PRRF_PATCH15_MACRO__ + +/* macros for field patch15 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch15_field patch15_field + * @brief macros for field patch15 + * @{ + */ +#define AT_PRRF_PATCH15__PATCH15__SHIFT 0 +#define AT_PRRF_PATCH15__PATCH15__WIDTH 32 +#define AT_PRRF_PATCH15__PATCH15__MASK 0xffffffffU +#define AT_PRRF_PATCH15__PATCH15__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH15__PATCH15__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH15__PATCH15__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH15__PATCH15__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH15__PATCH15__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH15__TYPE uint32_t +#define AT_PRRF_PATCH15__READ 0xffffffffU +#define AT_PRRF_PATCH15__WRITE 0xffffffffU +#define AT_PRRF_PATCH15__PRESERVED 0x00000000U +#define AT_PRRF_PATCH15__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH15_MACRO__ */ + +/** @} end of patch15 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch16 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch16 patch16 + * @brief Contains register fields associated with patch16. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH16_MACRO__ +#define __AT_PRRF_PATCH16_MACRO__ + +/* macros for field patch16 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch16_field patch16_field + * @brief macros for field patch16 + * @{ + */ +#define AT_PRRF_PATCH16__PATCH16__SHIFT 0 +#define AT_PRRF_PATCH16__PATCH16__WIDTH 32 +#define AT_PRRF_PATCH16__PATCH16__MASK 0xffffffffU +#define AT_PRRF_PATCH16__PATCH16__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH16__PATCH16__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH16__PATCH16__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH16__PATCH16__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH16__PATCH16__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH16__TYPE uint32_t +#define AT_PRRF_PATCH16__READ 0xffffffffU +#define AT_PRRF_PATCH16__WRITE 0xffffffffU +#define AT_PRRF_PATCH16__PRESERVED 0x00000000U +#define AT_PRRF_PATCH16__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH16_MACRO__ */ + +/** @} end of patch16 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch17 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch17 patch17 + * @brief Contains register fields associated with patch17. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH17_MACRO__ +#define __AT_PRRF_PATCH17_MACRO__ + +/* macros for field patch17 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch17_field patch17_field + * @brief macros for field patch17 + * @{ + */ +#define AT_PRRF_PATCH17__PATCH17__SHIFT 0 +#define AT_PRRF_PATCH17__PATCH17__WIDTH 32 +#define AT_PRRF_PATCH17__PATCH17__MASK 0xffffffffU +#define AT_PRRF_PATCH17__PATCH17__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH17__PATCH17__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH17__PATCH17__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH17__PATCH17__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH17__PATCH17__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH17__TYPE uint32_t +#define AT_PRRF_PATCH17__READ 0xffffffffU +#define AT_PRRF_PATCH17__WRITE 0xffffffffU +#define AT_PRRF_PATCH17__PRESERVED 0x00000000U +#define AT_PRRF_PATCH17__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH17_MACRO__ */ + +/** @} end of patch17 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch18 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch18 patch18 + * @brief Contains register fields associated with patch18. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH18_MACRO__ +#define __AT_PRRF_PATCH18_MACRO__ + +/* macros for field patch18 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch18_field patch18_field + * @brief macros for field patch18 + * @{ + */ +#define AT_PRRF_PATCH18__PATCH18__SHIFT 0 +#define AT_PRRF_PATCH18__PATCH18__WIDTH 32 +#define AT_PRRF_PATCH18__PATCH18__MASK 0xffffffffU +#define AT_PRRF_PATCH18__PATCH18__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH18__PATCH18__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH18__PATCH18__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH18__PATCH18__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH18__PATCH18__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH18__TYPE uint32_t +#define AT_PRRF_PATCH18__READ 0xffffffffU +#define AT_PRRF_PATCH18__WRITE 0xffffffffU +#define AT_PRRF_PATCH18__PRESERVED 0x00000000U +#define AT_PRRF_PATCH18__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH18_MACRO__ */ + +/** @} end of patch18 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch19 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch19 patch19 + * @brief Contains register fields associated with patch19. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH19_MACRO__ +#define __AT_PRRF_PATCH19_MACRO__ + +/* macros for field patch19 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch19_field patch19_field + * @brief macros for field patch19 + * @{ + */ +#define AT_PRRF_PATCH19__PATCH19__SHIFT 0 +#define AT_PRRF_PATCH19__PATCH19__WIDTH 32 +#define AT_PRRF_PATCH19__PATCH19__MASK 0xffffffffU +#define AT_PRRF_PATCH19__PATCH19__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH19__PATCH19__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH19__PATCH19__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH19__PATCH19__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH19__PATCH19__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH19__TYPE uint32_t +#define AT_PRRF_PATCH19__READ 0xffffffffU +#define AT_PRRF_PATCH19__WRITE 0xffffffffU +#define AT_PRRF_PATCH19__PRESERVED 0x00000000U +#define AT_PRRF_PATCH19__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH19_MACRO__ */ + +/** @} end of patch19 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch20 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch20 patch20 + * @brief Contains register fields associated with patch20. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH20_MACRO__ +#define __AT_PRRF_PATCH20_MACRO__ + +/* macros for field patch20 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch20_field patch20_field + * @brief macros for field patch20 + * @{ + */ +#define AT_PRRF_PATCH20__PATCH20__SHIFT 0 +#define AT_PRRF_PATCH20__PATCH20__WIDTH 32 +#define AT_PRRF_PATCH20__PATCH20__MASK 0xffffffffU +#define AT_PRRF_PATCH20__PATCH20__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH20__PATCH20__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH20__PATCH20__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH20__PATCH20__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH20__PATCH20__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH20__TYPE uint32_t +#define AT_PRRF_PATCH20__READ 0xffffffffU +#define AT_PRRF_PATCH20__WRITE 0xffffffffU +#define AT_PRRF_PATCH20__PRESERVED 0x00000000U +#define AT_PRRF_PATCH20__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH20_MACRO__ */ + +/** @} end of patch20 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch21 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch21 patch21 + * @brief Contains register fields associated with patch21. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH21_MACRO__ +#define __AT_PRRF_PATCH21_MACRO__ + +/* macros for field patch21 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch21_field patch21_field + * @brief macros for field patch21 + * @{ + */ +#define AT_PRRF_PATCH21__PATCH21__SHIFT 0 +#define AT_PRRF_PATCH21__PATCH21__WIDTH 32 +#define AT_PRRF_PATCH21__PATCH21__MASK 0xffffffffU +#define AT_PRRF_PATCH21__PATCH21__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH21__PATCH21__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH21__PATCH21__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH21__PATCH21__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH21__PATCH21__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH21__TYPE uint32_t +#define AT_PRRF_PATCH21__READ 0xffffffffU +#define AT_PRRF_PATCH21__WRITE 0xffffffffU +#define AT_PRRF_PATCH21__PRESERVED 0x00000000U +#define AT_PRRF_PATCH21__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH21_MACRO__ */ + +/** @} end of patch21 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch22 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch22 patch22 + * @brief Contains register fields associated with patch22. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH22_MACRO__ +#define __AT_PRRF_PATCH22_MACRO__ + +/* macros for field patch22 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch22_field patch22_field + * @brief macros for field patch22 + * @{ + */ +#define AT_PRRF_PATCH22__PATCH22__SHIFT 0 +#define AT_PRRF_PATCH22__PATCH22__WIDTH 32 +#define AT_PRRF_PATCH22__PATCH22__MASK 0xffffffffU +#define AT_PRRF_PATCH22__PATCH22__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH22__PATCH22__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH22__PATCH22__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH22__PATCH22__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH22__PATCH22__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH22__TYPE uint32_t +#define AT_PRRF_PATCH22__READ 0xffffffffU +#define AT_PRRF_PATCH22__WRITE 0xffffffffU +#define AT_PRRF_PATCH22__PRESERVED 0x00000000U +#define AT_PRRF_PATCH22__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH22_MACRO__ */ + +/** @} end of patch22 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch23 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch23 patch23 + * @brief Contains register fields associated with patch23. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH23_MACRO__ +#define __AT_PRRF_PATCH23_MACRO__ + +/* macros for field patch23 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch23_field patch23_field + * @brief macros for field patch23 + * @{ + */ +#define AT_PRRF_PATCH23__PATCH23__SHIFT 0 +#define AT_PRRF_PATCH23__PATCH23__WIDTH 32 +#define AT_PRRF_PATCH23__PATCH23__MASK 0xffffffffU +#define AT_PRRF_PATCH23__PATCH23__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH23__PATCH23__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH23__PATCH23__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH23__PATCH23__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH23__PATCH23__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH23__TYPE uint32_t +#define AT_PRRF_PATCH23__READ 0xffffffffU +#define AT_PRRF_PATCH23__WRITE 0xffffffffU +#define AT_PRRF_PATCH23__PRESERVED 0x00000000U +#define AT_PRRF_PATCH23__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH23_MACRO__ */ + +/** @} end of patch23 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch24 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch24 patch24 + * @brief Contains register fields associated with patch24. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH24_MACRO__ +#define __AT_PRRF_PATCH24_MACRO__ + +/* macros for field patch24 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch24_field patch24_field + * @brief macros for field patch24 + * @{ + */ +#define AT_PRRF_PATCH24__PATCH24__SHIFT 0 +#define AT_PRRF_PATCH24__PATCH24__WIDTH 32 +#define AT_PRRF_PATCH24__PATCH24__MASK 0xffffffffU +#define AT_PRRF_PATCH24__PATCH24__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH24__PATCH24__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH24__PATCH24__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH24__PATCH24__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH24__PATCH24__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH24__TYPE uint32_t +#define AT_PRRF_PATCH24__READ 0xffffffffU +#define AT_PRRF_PATCH24__WRITE 0xffffffffU +#define AT_PRRF_PATCH24__PRESERVED 0x00000000U +#define AT_PRRF_PATCH24__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH24_MACRO__ */ + +/** @} end of patch24 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch25 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch25 patch25 + * @brief Contains register fields associated with patch25. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH25_MACRO__ +#define __AT_PRRF_PATCH25_MACRO__ + +/* macros for field patch25 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch25_field patch25_field + * @brief macros for field patch25 + * @{ + */ +#define AT_PRRF_PATCH25__PATCH25__SHIFT 0 +#define AT_PRRF_PATCH25__PATCH25__WIDTH 32 +#define AT_PRRF_PATCH25__PATCH25__MASK 0xffffffffU +#define AT_PRRF_PATCH25__PATCH25__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH25__PATCH25__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH25__PATCH25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH25__PATCH25__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH25__PATCH25__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH25__TYPE uint32_t +#define AT_PRRF_PATCH25__READ 0xffffffffU +#define AT_PRRF_PATCH25__WRITE 0xffffffffU +#define AT_PRRF_PATCH25__PRESERVED 0x00000000U +#define AT_PRRF_PATCH25__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH25_MACRO__ */ + +/** @} end of patch25 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch26 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch26 patch26 + * @brief Contains register fields associated with patch26. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH26_MACRO__ +#define __AT_PRRF_PATCH26_MACRO__ + +/* macros for field patch26 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch26_field patch26_field + * @brief macros for field patch26 + * @{ + */ +#define AT_PRRF_PATCH26__PATCH26__SHIFT 0 +#define AT_PRRF_PATCH26__PATCH26__WIDTH 32 +#define AT_PRRF_PATCH26__PATCH26__MASK 0xffffffffU +#define AT_PRRF_PATCH26__PATCH26__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH26__PATCH26__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH26__PATCH26__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH26__PATCH26__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH26__PATCH26__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH26__TYPE uint32_t +#define AT_PRRF_PATCH26__READ 0xffffffffU +#define AT_PRRF_PATCH26__WRITE 0xffffffffU +#define AT_PRRF_PATCH26__PRESERVED 0x00000000U +#define AT_PRRF_PATCH26__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH26_MACRO__ */ + +/** @} end of patch26 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch27 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch27 patch27 + * @brief Contains register fields associated with patch27. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH27_MACRO__ +#define __AT_PRRF_PATCH27_MACRO__ + +/* macros for field patch27 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch27_field patch27_field + * @brief macros for field patch27 + * @{ + */ +#define AT_PRRF_PATCH27__PATCH27__SHIFT 0 +#define AT_PRRF_PATCH27__PATCH27__WIDTH 32 +#define AT_PRRF_PATCH27__PATCH27__MASK 0xffffffffU +#define AT_PRRF_PATCH27__PATCH27__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH27__PATCH27__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH27__PATCH27__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH27__PATCH27__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH27__PATCH27__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH27__TYPE uint32_t +#define AT_PRRF_PATCH27__READ 0xffffffffU +#define AT_PRRF_PATCH27__WRITE 0xffffffffU +#define AT_PRRF_PATCH27__PRESERVED 0x00000000U +#define AT_PRRF_PATCH27__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH27_MACRO__ */ + +/** @} end of patch27 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch28 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch28 patch28 + * @brief Contains register fields associated with patch28. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH28_MACRO__ +#define __AT_PRRF_PATCH28_MACRO__ + +/* macros for field patch28 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch28_field patch28_field + * @brief macros for field patch28 + * @{ + */ +#define AT_PRRF_PATCH28__PATCH28__SHIFT 0 +#define AT_PRRF_PATCH28__PATCH28__WIDTH 32 +#define AT_PRRF_PATCH28__PATCH28__MASK 0xffffffffU +#define AT_PRRF_PATCH28__PATCH28__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH28__PATCH28__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH28__PATCH28__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH28__PATCH28__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH28__PATCH28__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH28__TYPE uint32_t +#define AT_PRRF_PATCH28__READ 0xffffffffU +#define AT_PRRF_PATCH28__WRITE 0xffffffffU +#define AT_PRRF_PATCH28__PRESERVED 0x00000000U +#define AT_PRRF_PATCH28__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH28_MACRO__ */ + +/** @} end of patch28 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch29 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch29 patch29 + * @brief Contains register fields associated with patch29. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH29_MACRO__ +#define __AT_PRRF_PATCH29_MACRO__ + +/* macros for field patch29 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch29_field patch29_field + * @brief macros for field patch29 + * @{ + */ +#define AT_PRRF_PATCH29__PATCH29__SHIFT 0 +#define AT_PRRF_PATCH29__PATCH29__WIDTH 32 +#define AT_PRRF_PATCH29__PATCH29__MASK 0xffffffffU +#define AT_PRRF_PATCH29__PATCH29__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH29__PATCH29__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH29__PATCH29__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH29__PATCH29__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH29__PATCH29__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH29__TYPE uint32_t +#define AT_PRRF_PATCH29__READ 0xffffffffU +#define AT_PRRF_PATCH29__WRITE 0xffffffffU +#define AT_PRRF_PATCH29__PRESERVED 0x00000000U +#define AT_PRRF_PATCH29__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH29_MACRO__ */ + +/** @} end of patch29 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch30 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch30 patch30 + * @brief Contains register fields associated with patch30. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH30_MACRO__ +#define __AT_PRRF_PATCH30_MACRO__ + +/* macros for field patch30 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch30_field patch30_field + * @brief macros for field patch30 + * @{ + */ +#define AT_PRRF_PATCH30__PATCH30__SHIFT 0 +#define AT_PRRF_PATCH30__PATCH30__WIDTH 32 +#define AT_PRRF_PATCH30__PATCH30__MASK 0xffffffffU +#define AT_PRRF_PATCH30__PATCH30__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH30__PATCH30__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH30__PATCH30__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH30__PATCH30__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH30__PATCH30__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH30__TYPE uint32_t +#define AT_PRRF_PATCH30__READ 0xffffffffU +#define AT_PRRF_PATCH30__WRITE 0xffffffffU +#define AT_PRRF_PATCH30__PRESERVED 0x00000000U +#define AT_PRRF_PATCH30__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH30_MACRO__ */ + +/** @} end of patch30 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch31 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch31 patch31 + * @brief Contains register fields associated with patch31. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH31_MACRO__ +#define __AT_PRRF_PATCH31_MACRO__ + +/* macros for field patch31 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch31_field patch31_field + * @brief macros for field patch31 + * @{ + */ +#define AT_PRRF_PATCH31__PATCH31__SHIFT 0 +#define AT_PRRF_PATCH31__PATCH31__WIDTH 32 +#define AT_PRRF_PATCH31__PATCH31__MASK 0xffffffffU +#define AT_PRRF_PATCH31__PATCH31__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH31__PATCH31__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH31__PATCH31__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH31__PATCH31__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH31__PATCH31__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH31__TYPE uint32_t +#define AT_PRRF_PATCH31__READ 0xffffffffU +#define AT_PRRF_PATCH31__WRITE 0xffffffffU +#define AT_PRRF_PATCH31__PRESERVED 0x00000000U +#define AT_PRRF_PATCH31__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH31_MACRO__ */ + +/** @} end of patch31 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch32 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch32 patch32 + * @brief Contains register fields associated with patch32. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH32_MACRO__ +#define __AT_PRRF_PATCH32_MACRO__ + +/* macros for field patch32 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch32_field patch32_field + * @brief macros for field patch32 + * @{ + */ +#define AT_PRRF_PATCH32__PATCH32__SHIFT 0 +#define AT_PRRF_PATCH32__PATCH32__WIDTH 32 +#define AT_PRRF_PATCH32__PATCH32__MASK 0xffffffffU +#define AT_PRRF_PATCH32__PATCH32__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH32__PATCH32__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH32__PATCH32__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH32__PATCH32__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH32__PATCH32__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH32__TYPE uint32_t +#define AT_PRRF_PATCH32__READ 0xffffffffU +#define AT_PRRF_PATCH32__WRITE 0xffffffffU +#define AT_PRRF_PATCH32__PRESERVED 0x00000000U +#define AT_PRRF_PATCH32__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH32_MACRO__ */ + +/** @} end of patch32 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch33 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch33 patch33 + * @brief Contains register fields associated with patch33. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH33_MACRO__ +#define __AT_PRRF_PATCH33_MACRO__ + +/* macros for field patch33 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch33_field patch33_field + * @brief macros for field patch33 + * @{ + */ +#define AT_PRRF_PATCH33__PATCH33__SHIFT 0 +#define AT_PRRF_PATCH33__PATCH33__WIDTH 32 +#define AT_PRRF_PATCH33__PATCH33__MASK 0xffffffffU +#define AT_PRRF_PATCH33__PATCH33__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH33__PATCH33__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH33__PATCH33__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH33__PATCH33__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH33__PATCH33__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH33__TYPE uint32_t +#define AT_PRRF_PATCH33__READ 0xffffffffU +#define AT_PRRF_PATCH33__WRITE 0xffffffffU +#define AT_PRRF_PATCH33__PRESERVED 0x00000000U +#define AT_PRRF_PATCH33__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH33_MACRO__ */ + +/** @} end of patch33 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch34 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch34 patch34 + * @brief Contains register fields associated with patch34. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH34_MACRO__ +#define __AT_PRRF_PATCH34_MACRO__ + +/* macros for field patch34 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch34_field patch34_field + * @brief macros for field patch34 + * @{ + */ +#define AT_PRRF_PATCH34__PATCH34__SHIFT 0 +#define AT_PRRF_PATCH34__PATCH34__WIDTH 32 +#define AT_PRRF_PATCH34__PATCH34__MASK 0xffffffffU +#define AT_PRRF_PATCH34__PATCH34__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH34__PATCH34__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH34__PATCH34__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH34__PATCH34__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH34__PATCH34__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH34__TYPE uint32_t +#define AT_PRRF_PATCH34__READ 0xffffffffU +#define AT_PRRF_PATCH34__WRITE 0xffffffffU +#define AT_PRRF_PATCH34__PRESERVED 0x00000000U +#define AT_PRRF_PATCH34__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH34_MACRO__ */ + +/** @} end of patch34 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch35 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch35 patch35 + * @brief Contains register fields associated with patch35. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH35_MACRO__ +#define __AT_PRRF_PATCH35_MACRO__ + +/* macros for field patch35 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch35_field patch35_field + * @brief macros for field patch35 + * @{ + */ +#define AT_PRRF_PATCH35__PATCH35__SHIFT 0 +#define AT_PRRF_PATCH35__PATCH35__WIDTH 32 +#define AT_PRRF_PATCH35__PATCH35__MASK 0xffffffffU +#define AT_PRRF_PATCH35__PATCH35__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH35__PATCH35__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH35__PATCH35__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH35__PATCH35__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH35__PATCH35__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH35__TYPE uint32_t +#define AT_PRRF_PATCH35__READ 0xffffffffU +#define AT_PRRF_PATCH35__WRITE 0xffffffffU +#define AT_PRRF_PATCH35__PRESERVED 0x00000000U +#define AT_PRRF_PATCH35__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH35_MACRO__ */ + +/** @} end of patch35 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch36 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch36 patch36 + * @brief Contains register fields associated with patch36. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH36_MACRO__ +#define __AT_PRRF_PATCH36_MACRO__ + +/* macros for field patch36 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch36_field patch36_field + * @brief macros for field patch36 + * @{ + */ +#define AT_PRRF_PATCH36__PATCH36__SHIFT 0 +#define AT_PRRF_PATCH36__PATCH36__WIDTH 32 +#define AT_PRRF_PATCH36__PATCH36__MASK 0xffffffffU +#define AT_PRRF_PATCH36__PATCH36__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH36__PATCH36__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH36__PATCH36__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH36__PATCH36__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH36__PATCH36__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH36__TYPE uint32_t +#define AT_PRRF_PATCH36__READ 0xffffffffU +#define AT_PRRF_PATCH36__WRITE 0xffffffffU +#define AT_PRRF_PATCH36__PRESERVED 0x00000000U +#define AT_PRRF_PATCH36__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH36_MACRO__ */ + +/** @} end of patch36 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch37 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch37 patch37 + * @brief Contains register fields associated with patch37. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH37_MACRO__ +#define __AT_PRRF_PATCH37_MACRO__ + +/* macros for field patch37 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch37_field patch37_field + * @brief macros for field patch37 + * @{ + */ +#define AT_PRRF_PATCH37__PATCH37__SHIFT 0 +#define AT_PRRF_PATCH37__PATCH37__WIDTH 32 +#define AT_PRRF_PATCH37__PATCH37__MASK 0xffffffffU +#define AT_PRRF_PATCH37__PATCH37__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH37__PATCH37__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH37__PATCH37__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH37__PATCH37__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH37__PATCH37__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH37__TYPE uint32_t +#define AT_PRRF_PATCH37__READ 0xffffffffU +#define AT_PRRF_PATCH37__WRITE 0xffffffffU +#define AT_PRRF_PATCH37__PRESERVED 0x00000000U +#define AT_PRRF_PATCH37__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH37_MACRO__ */ + +/** @} end of patch37 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch38 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch38 patch38 + * @brief Contains register fields associated with patch38. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH38_MACRO__ +#define __AT_PRRF_PATCH38_MACRO__ + +/* macros for field patch38 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch38_field patch38_field + * @brief macros for field patch38 + * @{ + */ +#define AT_PRRF_PATCH38__PATCH38__SHIFT 0 +#define AT_PRRF_PATCH38__PATCH38__WIDTH 32 +#define AT_PRRF_PATCH38__PATCH38__MASK 0xffffffffU +#define AT_PRRF_PATCH38__PATCH38__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH38__PATCH38__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH38__PATCH38__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH38__PATCH38__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH38__PATCH38__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH38__TYPE uint32_t +#define AT_PRRF_PATCH38__READ 0xffffffffU +#define AT_PRRF_PATCH38__WRITE 0xffffffffU +#define AT_PRRF_PATCH38__PRESERVED 0x00000000U +#define AT_PRRF_PATCH38__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH38_MACRO__ */ + +/** @} end of patch38 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch39 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch39 patch39 + * @brief Contains register fields associated with patch39. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH39_MACRO__ +#define __AT_PRRF_PATCH39_MACRO__ + +/* macros for field patch39 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch39_field patch39_field + * @brief macros for field patch39 + * @{ + */ +#define AT_PRRF_PATCH39__PATCH39__SHIFT 0 +#define AT_PRRF_PATCH39__PATCH39__WIDTH 32 +#define AT_PRRF_PATCH39__PATCH39__MASK 0xffffffffU +#define AT_PRRF_PATCH39__PATCH39__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH39__PATCH39__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH39__PATCH39__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH39__PATCH39__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH39__PATCH39__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH39__TYPE uint32_t +#define AT_PRRF_PATCH39__READ 0xffffffffU +#define AT_PRRF_PATCH39__WRITE 0xffffffffU +#define AT_PRRF_PATCH39__PRESERVED 0x00000000U +#define AT_PRRF_PATCH39__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH39_MACRO__ */ + +/** @} end of patch39 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch40 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch40 patch40 + * @brief Contains register fields associated with patch40. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH40_MACRO__ +#define __AT_PRRF_PATCH40_MACRO__ + +/* macros for field patch40 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch40_field patch40_field + * @brief macros for field patch40 + * @{ + */ +#define AT_PRRF_PATCH40__PATCH40__SHIFT 0 +#define AT_PRRF_PATCH40__PATCH40__WIDTH 32 +#define AT_PRRF_PATCH40__PATCH40__MASK 0xffffffffU +#define AT_PRRF_PATCH40__PATCH40__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH40__PATCH40__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH40__PATCH40__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH40__PATCH40__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH40__PATCH40__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH40__TYPE uint32_t +#define AT_PRRF_PATCH40__READ 0xffffffffU +#define AT_PRRF_PATCH40__WRITE 0xffffffffU +#define AT_PRRF_PATCH40__PRESERVED 0x00000000U +#define AT_PRRF_PATCH40__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH40_MACRO__ */ + +/** @} end of patch40 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch41 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch41 patch41 + * @brief Contains register fields associated with patch41. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH41_MACRO__ +#define __AT_PRRF_PATCH41_MACRO__ + +/* macros for field patch41 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch41_field patch41_field + * @brief macros for field patch41 + * @{ + */ +#define AT_PRRF_PATCH41__PATCH41__SHIFT 0 +#define AT_PRRF_PATCH41__PATCH41__WIDTH 32 +#define AT_PRRF_PATCH41__PATCH41__MASK 0xffffffffU +#define AT_PRRF_PATCH41__PATCH41__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH41__PATCH41__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH41__PATCH41__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH41__PATCH41__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH41__PATCH41__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH41__TYPE uint32_t +#define AT_PRRF_PATCH41__READ 0xffffffffU +#define AT_PRRF_PATCH41__WRITE 0xffffffffU +#define AT_PRRF_PATCH41__PRESERVED 0x00000000U +#define AT_PRRF_PATCH41__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH41_MACRO__ */ + +/** @} end of patch41 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch42 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch42 patch42 + * @brief Contains register fields associated with patch42. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH42_MACRO__ +#define __AT_PRRF_PATCH42_MACRO__ + +/* macros for field patch42 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch42_field patch42_field + * @brief macros for field patch42 + * @{ + */ +#define AT_PRRF_PATCH42__PATCH42__SHIFT 0 +#define AT_PRRF_PATCH42__PATCH42__WIDTH 32 +#define AT_PRRF_PATCH42__PATCH42__MASK 0xffffffffU +#define AT_PRRF_PATCH42__PATCH42__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH42__PATCH42__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH42__PATCH42__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH42__PATCH42__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH42__PATCH42__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH42__TYPE uint32_t +#define AT_PRRF_PATCH42__READ 0xffffffffU +#define AT_PRRF_PATCH42__WRITE 0xffffffffU +#define AT_PRRF_PATCH42__PRESERVED 0x00000000U +#define AT_PRRF_PATCH42__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH42_MACRO__ */ + +/** @} end of patch42 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch43 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch43 patch43 + * @brief Contains register fields associated with patch43. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH43_MACRO__ +#define __AT_PRRF_PATCH43_MACRO__ + +/* macros for field patch43 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch43_field patch43_field + * @brief macros for field patch43 + * @{ + */ +#define AT_PRRF_PATCH43__PATCH43__SHIFT 0 +#define AT_PRRF_PATCH43__PATCH43__WIDTH 32 +#define AT_PRRF_PATCH43__PATCH43__MASK 0xffffffffU +#define AT_PRRF_PATCH43__PATCH43__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH43__PATCH43__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH43__PATCH43__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH43__PATCH43__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH43__PATCH43__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH43__TYPE uint32_t +#define AT_PRRF_PATCH43__READ 0xffffffffU +#define AT_PRRF_PATCH43__WRITE 0xffffffffU +#define AT_PRRF_PATCH43__PRESERVED 0x00000000U +#define AT_PRRF_PATCH43__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH43_MACRO__ */ + +/** @} end of patch43 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch44 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch44 patch44 + * @brief Contains register fields associated with patch44. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH44_MACRO__ +#define __AT_PRRF_PATCH44_MACRO__ + +/* macros for field patch44 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch44_field patch44_field + * @brief macros for field patch44 + * @{ + */ +#define AT_PRRF_PATCH44__PATCH44__SHIFT 0 +#define AT_PRRF_PATCH44__PATCH44__WIDTH 32 +#define AT_PRRF_PATCH44__PATCH44__MASK 0xffffffffU +#define AT_PRRF_PATCH44__PATCH44__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH44__PATCH44__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH44__PATCH44__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH44__PATCH44__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH44__PATCH44__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH44__TYPE uint32_t +#define AT_PRRF_PATCH44__READ 0xffffffffU +#define AT_PRRF_PATCH44__WRITE 0xffffffffU +#define AT_PRRF_PATCH44__PRESERVED 0x00000000U +#define AT_PRRF_PATCH44__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH44_MACRO__ */ + +/** @} end of patch44 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch45 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch45 patch45 + * @brief Contains register fields associated with patch45. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH45_MACRO__ +#define __AT_PRRF_PATCH45_MACRO__ + +/* macros for field patch45 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch45_field patch45_field + * @brief macros for field patch45 + * @{ + */ +#define AT_PRRF_PATCH45__PATCH45__SHIFT 0 +#define AT_PRRF_PATCH45__PATCH45__WIDTH 32 +#define AT_PRRF_PATCH45__PATCH45__MASK 0xffffffffU +#define AT_PRRF_PATCH45__PATCH45__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH45__PATCH45__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH45__PATCH45__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH45__PATCH45__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH45__PATCH45__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH45__TYPE uint32_t +#define AT_PRRF_PATCH45__READ 0xffffffffU +#define AT_PRRF_PATCH45__WRITE 0xffffffffU +#define AT_PRRF_PATCH45__PRESERVED 0x00000000U +#define AT_PRRF_PATCH45__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH45_MACRO__ */ + +/** @} end of patch45 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch46 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch46 patch46 + * @brief Contains register fields associated with patch46. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH46_MACRO__ +#define __AT_PRRF_PATCH46_MACRO__ + +/* macros for field patch46 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch46_field patch46_field + * @brief macros for field patch46 + * @{ + */ +#define AT_PRRF_PATCH46__PATCH46__SHIFT 0 +#define AT_PRRF_PATCH46__PATCH46__WIDTH 32 +#define AT_PRRF_PATCH46__PATCH46__MASK 0xffffffffU +#define AT_PRRF_PATCH46__PATCH46__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH46__PATCH46__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH46__PATCH46__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH46__PATCH46__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH46__PATCH46__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH46__TYPE uint32_t +#define AT_PRRF_PATCH46__READ 0xffffffffU +#define AT_PRRF_PATCH46__WRITE 0xffffffffU +#define AT_PRRF_PATCH46__PRESERVED 0x00000000U +#define AT_PRRF_PATCH46__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH46_MACRO__ */ + +/** @} end of patch46 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_patch47 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch47 patch47 + * @brief Contains register fields associated with patch47. definitions. + * @{ + */ +#ifndef __AT_PRRF_PATCH47_MACRO__ +#define __AT_PRRF_PATCH47_MACRO__ + +/* macros for field patch47 */ +/** + * @defgroup at_ahb_prrf_regs_core_patch47_field patch47_field + * @brief macros for field patch47 + * @{ + */ +#define AT_PRRF_PATCH47__PATCH47__SHIFT 0 +#define AT_PRRF_PATCH47__PATCH47__WIDTH 32 +#define AT_PRRF_PATCH47__PATCH47__MASK 0xffffffffU +#define AT_PRRF_PATCH47__PATCH47__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH47__PATCH47__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_PRRF_PATCH47__PATCH47__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_PATCH47__PATCH47__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_PATCH47__PATCH47__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_PATCH47__TYPE uint32_t +#define AT_PRRF_PATCH47__READ 0xffffffffU +#define AT_PRRF_PATCH47__WRITE 0xffffffffU +#define AT_PRRF_PATCH47__PRESERVED 0x00000000U +#define AT_PRRF_PATCH47__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_PATCH47_MACRO__ */ + +/** @} end of patch47 */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_rram_wrt_config_lo */ +/** + * @defgroup at_ahb_prrf_regs_core_rram_wrt_config_lo rram_wrt_config_lo + * @brief Contains register fields associated with rram_wrt_config_lo. definitions. + * @{ + */ +#ifndef __AT_PRRF_RRAM_WRT_CONFIG_LO_MACRO__ +#define __AT_PRRF_RRAM_WRT_CONFIG_LO_MACRO__ + +/* macros for field din */ +/** + * @defgroup at_ahb_prrf_regs_core_din_field din_field + * @brief macros for field din + * @{ + */ +#define AT_PRRF_RRAM_WRT_CONFIG_LO__DIN__SHIFT 0 +#define AT_PRRF_RRAM_WRT_CONFIG_LO__DIN__WIDTH 32 +#define AT_PRRF_RRAM_WRT_CONFIG_LO__DIN__MASK 0xffffffffU +#define AT_PRRF_RRAM_WRT_CONFIG_LO__DIN__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_PRRF_RRAM_WRT_CONFIG_LO__DIN__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_PRRF_RRAM_WRT_CONFIG_LO__DIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_RRAM_WRT_CONFIG_LO__DIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_RRAM_WRT_CONFIG_LO__DIN__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_RRAM_WRT_CONFIG_LO__TYPE uint32_t +#define AT_PRRF_RRAM_WRT_CONFIG_LO__READ 0xffffffffU +#define AT_PRRF_RRAM_WRT_CONFIG_LO__WRITE 0xffffffffU +#define AT_PRRF_RRAM_WRT_CONFIG_LO__PRESERVED 0x00000000U +#define AT_PRRF_RRAM_WRT_CONFIG_LO__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_RRAM_WRT_CONFIG_LO_MACRO__ */ + +/** @} end of rram_wrt_config_lo */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_rram_wrt_config_hi */ +/** + * @defgroup at_ahb_prrf_regs_core_rram_wrt_config_hi rram_wrt_config_hi + * @brief Contains register fields associated with rram_wrt_config_hi. definitions. + * @{ + */ +#ifndef __AT_PRRF_RRAM_WRT_CONFIG_HI_MACRO__ +#define __AT_PRRF_RRAM_WRT_CONFIG_HI_MACRO__ + +/* macros for field din */ +/** + * @defgroup at_ahb_prrf_regs_core_din_field din_field + * @brief macros for field din + * @{ + */ +#define AT_PRRF_RRAM_WRT_CONFIG_HI__DIN__SHIFT 0 +#define AT_PRRF_RRAM_WRT_CONFIG_HI__DIN__WIDTH 32 +#define AT_PRRF_RRAM_WRT_CONFIG_HI__DIN__MASK 0xffffffffU +#define AT_PRRF_RRAM_WRT_CONFIG_HI__DIN__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_PRRF_RRAM_WRT_CONFIG_HI__DIN__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_PRRF_RRAM_WRT_CONFIG_HI__DIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_PRRF_RRAM_WRT_CONFIG_HI__DIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_PRRF_RRAM_WRT_CONFIG_HI__DIN__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_RRAM_WRT_CONFIG_HI__TYPE uint32_t +#define AT_PRRF_RRAM_WRT_CONFIG_HI__READ 0xffffffffU +#define AT_PRRF_RRAM_WRT_CONFIG_HI__WRITE 0xffffffffU +#define AT_PRRF_RRAM_WRT_CONFIG_HI__PRESERVED 0x00000000U +#define AT_PRRF_RRAM_WRT_CONFIG_HI__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_RRAM_WRT_CONFIG_HI_MACRO__ */ + +/** @} end of rram_wrt_config_hi */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_rram_read_config_lo */ +/** + * @defgroup at_ahb_prrf_regs_core_rram_read_config_lo rram_read_config_lo + * @brief Contains register fields associated with rram_read_config_lo. definitions. + * @{ + */ +#ifndef __AT_PRRF_RRAM_READ_CONFIG_LO_MACRO__ +#define __AT_PRRF_RRAM_READ_CONFIG_LO_MACRO__ + +/* macros for field dout */ +/** + * @defgroup at_ahb_prrf_regs_core_dout_field dout_field + * @brief macros for field dout + * @{ + */ +#define AT_PRRF_RRAM_READ_CONFIG_LO__DOUT__SHIFT 0 +#define AT_PRRF_RRAM_READ_CONFIG_LO__DOUT__WIDTH 32 +#define AT_PRRF_RRAM_READ_CONFIG_LO__DOUT__MASK 0xffffffffU +#define AT_PRRF_RRAM_READ_CONFIG_LO__DOUT__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_PRRF_RRAM_READ_CONFIG_LO__DOUT__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_RRAM_READ_CONFIG_LO__TYPE uint32_t +#define AT_PRRF_RRAM_READ_CONFIG_LO__READ 0xffffffffU +#define AT_PRRF_RRAM_READ_CONFIG_LO__PRESERVED 0x00000000U +#define AT_PRRF_RRAM_READ_CONFIG_LO__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_RRAM_READ_CONFIG_LO_MACRO__ */ + +/** @} end of rram_read_config_lo */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_rram_read_config_hi */ +/** + * @defgroup at_ahb_prrf_regs_core_rram_read_config_hi rram_read_config_hi + * @brief Contains register fields associated with rram_read_config_hi. definitions. + * @{ + */ +#ifndef __AT_PRRF_RRAM_READ_CONFIG_HI_MACRO__ +#define __AT_PRRF_RRAM_READ_CONFIG_HI_MACRO__ + +/* macros for field dout */ +/** + * @defgroup at_ahb_prrf_regs_core_dout_field dout_field + * @brief macros for field dout + * @{ + */ +#define AT_PRRF_RRAM_READ_CONFIG_HI__DOUT__SHIFT 0 +#define AT_PRRF_RRAM_READ_CONFIG_HI__DOUT__WIDTH 32 +#define AT_PRRF_RRAM_READ_CONFIG_HI__DOUT__MASK 0xffffffffU +#define AT_PRRF_RRAM_READ_CONFIG_HI__DOUT__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_PRRF_RRAM_READ_CONFIG_HI__DOUT__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_RRAM_READ_CONFIG_HI__TYPE uint32_t +#define AT_PRRF_RRAM_READ_CONFIG_HI__READ 0xffffffffU +#define AT_PRRF_RRAM_READ_CONFIG_HI__PRESERVED 0x00000000U +#define AT_PRRF_RRAM_READ_CONFIG_HI__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_RRAM_READ_CONFIG_HI_MACRO__ */ + +/** @} end of rram_read_config_hi */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_rram_cache_config */ +/** + * @defgroup at_ahb_prrf_regs_core_rram_cache_config rram_cache_config + * @brief Contains register fields associated with rram_cache_config. definitions. + * @{ + */ +#ifndef __AT_PRRF_RRAM_CACHE_CONFIG_MACRO__ +#define __AT_PRRF_RRAM_CACHE_CONFIG_MACRO__ + +/* macros for field cache_mode */ +/** + * @defgroup at_ahb_prrf_regs_core_cache_mode_field cache_mode_field + * @brief macros for field cache_mode + * @{ + */ +#define AT_PRRF_RRAM_CACHE_CONFIG__CACHE_MODE__SHIFT 0 +#define AT_PRRF_RRAM_CACHE_CONFIG__CACHE_MODE__WIDTH 1 +#define AT_PRRF_RRAM_CACHE_CONFIG__CACHE_MODE__MASK 0x00000001U +#define AT_PRRF_RRAM_CACHE_CONFIG__CACHE_MODE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_PRRF_RRAM_CACHE_CONFIG__CACHE_MODE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_PRRF_RRAM_CACHE_CONFIG__CACHE_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AT_PRRF_RRAM_CACHE_CONFIG__CACHE_MODE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AT_PRRF_RRAM_CACHE_CONFIG__CACHE_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_PRRF_RRAM_CACHE_CONFIG__CACHE_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_PRRF_RRAM_CACHE_CONFIG__CACHE_MODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enable_cache */ +/** + * @defgroup at_ahb_prrf_regs_core_enable_cache_field enable_cache_field + * @brief macros for field enable_cache + * @{ + */ +#define AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_CACHE__SHIFT 1 +#define AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_CACHE__WIDTH 1 +#define AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_CACHE__MASK 0x00000002U +#define AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_CACHE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_CACHE__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_CACHE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_CACHE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_CACHE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_CACHE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_CACHE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field invalidate_cache */ +/** + * @defgroup at_ahb_prrf_regs_core_invalidate_cache_field invalidate_cache_field + * @brief macros for field invalidate_cache + * @{ + */ +#define AT_PRRF_RRAM_CACHE_CONFIG__INVALIDATE_CACHE__SHIFT 2 +#define AT_PRRF_RRAM_CACHE_CONFIG__INVALIDATE_CACHE__WIDTH 1 +#define AT_PRRF_RRAM_CACHE_CONFIG__INVALIDATE_CACHE__MASK 0x00000004U +#define AT_PRRF_RRAM_CACHE_CONFIG__INVALIDATE_CACHE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define AT_PRRF_RRAM_CACHE_CONFIG__INVALIDATE_CACHE__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define AT_PRRF_RRAM_CACHE_CONFIG__INVALIDATE_CACHE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define AT_PRRF_RRAM_CACHE_CONFIG__INVALIDATE_CACHE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define AT_PRRF_RRAM_CACHE_CONFIG__INVALIDATE_CACHE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define AT_PRRF_RRAM_CACHE_CONFIG__INVALIDATE_CACHE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define AT_PRRF_RRAM_CACHE_CONFIG__INVALIDATE_CACHE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enable_fine_clock_gating */ +/** + * @defgroup at_ahb_prrf_regs_core_enable_fine_clock_gating_field enable_fine_clock_gating_field + * @brief macros for field enable_fine_clock_gating + * @details secondary clock gating control (enable_cache is primary). 1=rram_cache clock is enabled only when access falls in rram region. 0=always-on. + * @{ + */ +#define AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_FINE_CLOCK_GATING__SHIFT 3 +#define AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_FINE_CLOCK_GATING__WIDTH 1 +#define AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_FINE_CLOCK_GATING__MASK 0x00000008U +#define AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_FINE_CLOCK_GATING__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_FINE_CLOCK_GATING__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_FINE_CLOCK_GATING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_FINE_CLOCK_GATING__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_FINE_CLOCK_GATING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_FINE_CLOCK_GATING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_FINE_CLOCK_GATING__RESET_VALUE \ + 0x00000000U +/** @} */ +#define AT_PRRF_RRAM_CACHE_CONFIG__TYPE uint32_t +#define AT_PRRF_RRAM_CACHE_CONFIG__READ 0x0000000fU +#define AT_PRRF_RRAM_CACHE_CONFIG__WRITE 0x0000000fU +#define AT_PRRF_RRAM_CACHE_CONFIG__PRESERVED 0x00000000U +#define AT_PRRF_RRAM_CACHE_CONFIG__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_RRAM_CACHE_CONFIG_MACRO__ */ + +/** @} end of rram_cache_config */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_rram_mem_config */ +/** + * @defgroup at_ahb_prrf_regs_core_rram_mem_config rram_mem_config + * @brief Contains register fields associated with rram_mem_config. definitions. + * @{ + */ +#ifndef __AT_PRRF_RRAM_MEM_CONFIG_MACRO__ +#define __AT_PRRF_RRAM_MEM_CONFIG_MACRO__ + +/* macros for field rram_speedup_b */ +/** + * @defgroup at_ahb_prrf_regs_core_rram_speedup_b_field rram_speedup_b_field + * @brief macros for field rram_speedup_b + * @{ + */ +#define AT_PRRF_RRAM_MEM_CONFIG__RRAM_SPEEDUP_B__SHIFT 0 +#define AT_PRRF_RRAM_MEM_CONFIG__RRAM_SPEEDUP_B__WIDTH 1 +#define AT_PRRF_RRAM_MEM_CONFIG__RRAM_SPEEDUP_B__MASK 0x00000001U +#define AT_PRRF_RRAM_MEM_CONFIG__RRAM_SPEEDUP_B__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_PRRF_RRAM_MEM_CONFIG__RRAM_SPEEDUP_B__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_PRRF_RRAM_MEM_CONFIG__RRAM_SPEEDUP_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AT_PRRF_RRAM_MEM_CONFIG__RRAM_SPEEDUP_B__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AT_PRRF_RRAM_MEM_CONFIG__RRAM_SPEEDUP_B__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_PRRF_RRAM_MEM_CONFIG__RRAM_SPEEDUP_B__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_PRRF_RRAM_MEM_CONFIG__RRAM_SPEEDUP_B__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field trc_info */ +/** + * @defgroup at_ahb_prrf_regs_core_trc_info_field trc_info_field + * @brief macros for field trc_info + * @{ + */ +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_INFO__SHIFT 1 +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_INFO__WIDTH 1 +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_INFO__MASK 0x00000002U +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_INFO__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_INFO__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_INFO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_INFO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_INFO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_INFO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_INFO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field trc_lven */ +/** + * @defgroup at_ahb_prrf_regs_core_trc_lven_field trc_lven_field + * @brief macros for field trc_lven + * @{ + */ +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_LVEN__SHIFT 2 +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_LVEN__WIDTH 1 +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_LVEN__MASK 0x00000004U +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_LVEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_LVEN__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_LVEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_LVEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_LVEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_LVEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_LVEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field trc_tin */ +/** + * @defgroup at_ahb_prrf_regs_core_trc_tin_field trc_tin_field + * @brief macros for field trc_tin + * @{ + */ +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_TIN__SHIFT 3 +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_TIN__WIDTH 15 +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_TIN__MASK 0x0003fff8U +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_TIN__READ(src) \ + (((uint32_t)(src)\ + & 0x0003fff8U) >> 3) +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_TIN__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x0003fff8U) +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_TIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fff8U) | (((uint32_t)(src) <<\ + 3) & 0x0003fff8U) +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_TIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x0003fff8U))) +#define AT_PRRF_RRAM_MEM_CONFIG__TRC_TIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_fine_ckg */ +/** + * @defgroup at_ahb_prrf_regs_core_en_fine_ckg_field en_fine_ckg_field + * @brief macros for field en_fine_ckg + * @details enable fine clock gating to the rram macro + * @{ + */ +#define AT_PRRF_RRAM_MEM_CONFIG__EN_FINE_CKG__SHIFT 18 +#define AT_PRRF_RRAM_MEM_CONFIG__EN_FINE_CKG__WIDTH 1 +#define AT_PRRF_RRAM_MEM_CONFIG__EN_FINE_CKG__MASK 0x00040000U +#define AT_PRRF_RRAM_MEM_CONFIG__EN_FINE_CKG__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define AT_PRRF_RRAM_MEM_CONFIG__EN_FINE_CKG__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define AT_PRRF_RRAM_MEM_CONFIG__EN_FINE_CKG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define AT_PRRF_RRAM_MEM_CONFIG__EN_FINE_CKG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define AT_PRRF_RRAM_MEM_CONFIG__EN_FINE_CKG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define AT_PRRF_RRAM_MEM_CONFIG__EN_FINE_CKG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define AT_PRRF_RRAM_MEM_CONFIG__EN_FINE_CKG__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_RRAM_MEM_CONFIG__TYPE uint32_t +#define AT_PRRF_RRAM_MEM_CONFIG__READ 0x0007ffffU +#define AT_PRRF_RRAM_MEM_CONFIG__WRITE 0x0007ffffU +#define AT_PRRF_RRAM_MEM_CONFIG__PRESERVED 0x00000000U +#define AT_PRRF_RRAM_MEM_CONFIG__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_RRAM_MEM_CONFIG_MACRO__ */ + +/** @} end of rram_mem_config */ + +/* macros for BlueprintGlobalNameSpace::AT_PRRF_rram_status */ +/** + * @defgroup at_ahb_prrf_regs_core_rram_status rram_status + * @brief Contains register fields associated with rram_status. definitions. + * @{ + */ +#ifndef __AT_PRRF_RRAM_STATUS_MACRO__ +#define __AT_PRRF_RRAM_STATUS_MACRO__ + +/* macros for field busy */ +/** + * @defgroup at_ahb_prrf_regs_core_busy_field busy_field + * @brief macros for field busy + * @{ + */ +#define AT_PRRF_RRAM_STATUS__BUSY__SHIFT 0 +#define AT_PRRF_RRAM_STATUS__BUSY__WIDTH 1 +#define AT_PRRF_RRAM_STATUS__BUSY__MASK 0x00000001U +#define AT_PRRF_RRAM_STATUS__BUSY__READ(src) ((uint32_t)(src) & 0x00000001U) +#define AT_PRRF_RRAM_STATUS__BUSY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_PRRF_RRAM_STATUS__BUSY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_PRRF_RRAM_STATUS__BUSY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field err */ +/** + * @defgroup at_ahb_prrf_regs_core_err_field err_field + * @brief macros for field err + * @{ + */ +#define AT_PRRF_RRAM_STATUS__ERR__SHIFT 1 +#define AT_PRRF_RRAM_STATUS__ERR__WIDTH 1 +#define AT_PRRF_RRAM_STATUS__ERR__MASK 0x00000002U +#define AT_PRRF_RRAM_STATUS__ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_PRRF_RRAM_STATUS__ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_PRRF_RRAM_STATUS__ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_PRRF_RRAM_STATUS__ERR__RESET_VALUE 0x00000000U +/** @} */ +#define AT_PRRF_RRAM_STATUS__TYPE uint32_t +#define AT_PRRF_RRAM_STATUS__READ 0x00000003U +#define AT_PRRF_RRAM_STATUS__PRESERVED 0x00000000U +#define AT_PRRF_RRAM_STATUS__RESET_VALUE 0x00000000U + +#endif /* __AT_PRRF_RRAM_STATUS_MACRO__ */ + +/** @} end of rram_status */ + +/** @} end of AT_AHB_PRRF_REGS_CORE */ +#endif /* __REG_AT_AHB_PRRF_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_ahb_sha2_regs_core_macro.h b/ATM33xx-5/include/reg/at_ahb_sha2_regs_core_macro.h new file mode 100644 index 0000000..84fdb57 --- /dev/null +++ b/ATM33xx-5/include/reg/at_ahb_sha2_regs_core_macro.h @@ -0,0 +1,1684 @@ +/* */ +/* File: at_ahb_sha2_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_ahb_sha2_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_AHB_SHA2_REGS_CORE_H__ +#define __REG_AT_AHB_SHA2_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_AHB_SHA2_REGS_CORE at_ahb_sha2_regs_core + * @ingroup AT_REG + * @brief at_ahb_sha2_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_control */ +/** + * @defgroup at_ahb_sha2_regs_core_control control + * @brief Contains register fields associated with control. definitions. + * @{ + */ +#ifndef __AT_SHA2_CONTROL_MACRO__ +#define __AT_SHA2_CONTROL_MACRO__ + +/* macros for field sha_en */ +/** + * @defgroup at_ahb_sha2_regs_core_sha_en_field sha_en_field + * @brief macros for field sha_en + * @details SHA256 enable. If 0, SHA engine won't initiate compression, this is used to stop operation of the SHA engine until configuration has been done. When the SHA engine is disabled the digest is cleared. + * @{ + */ +#define AT_SHA2_CONTROL__SHA_EN__SHIFT 0 +#define AT_SHA2_CONTROL__SHA_EN__WIDTH 1 +#define AT_SHA2_CONTROL__SHA_EN__MASK 0x00000001U +#define AT_SHA2_CONTROL__SHA_EN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define AT_SHA2_CONTROL__SHA_EN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define AT_SHA2_CONTROL__SHA_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AT_SHA2_CONTROL__SHA_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AT_SHA2_CONTROL__SHA_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_SHA2_CONTROL__SHA_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_SHA2_CONTROL__SHA_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hmac_en */ +/** + * @defgroup at_ahb_sha2_regs_core_hmac_en_field hmac_en_field + * @brief macros for field hmac_en + * @details HMAC datapath enable. If this bit is 1, HMAC operates when hash_start toggles + * @{ + */ +#define AT_SHA2_CONTROL__HMAC_EN__SHIFT 1 +#define AT_SHA2_CONTROL__HMAC_EN__WIDTH 1 +#define AT_SHA2_CONTROL__HMAC_EN__MASK 0x00000002U +#define AT_SHA2_CONTROL__HMAC_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_SHA2_CONTROL__HMAC_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define AT_SHA2_CONTROL__HMAC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define AT_SHA2_CONTROL__HMAC_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define AT_SHA2_CONTROL__HMAC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_SHA2_CONTROL__HMAC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_SHA2_CONTROL__HMAC_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_swizzle */ +/** + * @defgroup at_ahb_sha2_regs_core_byte_swizzle_field byte_swizzle_field + * @brief macros for field byte_swizzle + * @details message word byte swizzle + * @{ + */ +#define AT_SHA2_CONTROL__BYTE_SWIZZLE__SHIFT 2 +#define AT_SHA2_CONTROL__BYTE_SWIZZLE__WIDTH 1 +#define AT_SHA2_CONTROL__BYTE_SWIZZLE__MASK 0x00000004U +#define AT_SHA2_CONTROL__BYTE_SWIZZLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define AT_SHA2_CONTROL__BYTE_SWIZZLE__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define AT_SHA2_CONTROL__BYTE_SWIZZLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define AT_SHA2_CONTROL__BYTE_SWIZZLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define AT_SHA2_CONTROL__BYTE_SWIZZLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define AT_SHA2_CONTROL__BYTE_SWIZZLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define AT_SHA2_CONTROL__BYTE_SWIZZLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field digest_swizzle */ +/** + * @defgroup at_ahb_sha2_regs_core_digest_swizzle_field digest_swizzle_field + * @brief macros for field digest_swizzle + * @details digest word's byte swizzle + * @{ + */ +#define AT_SHA2_CONTROL__DIGEST_SWIZZLE__SHIFT 3 +#define AT_SHA2_CONTROL__DIGEST_SWIZZLE__WIDTH 1 +#define AT_SHA2_CONTROL__DIGEST_SWIZZLE__MASK 0x00000008U +#define AT_SHA2_CONTROL__DIGEST_SWIZZLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define AT_SHA2_CONTROL__DIGEST_SWIZZLE__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define AT_SHA2_CONTROL__DIGEST_SWIZZLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define AT_SHA2_CONTROL__DIGEST_SWIZZLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define AT_SHA2_CONTROL__DIGEST_SWIZZLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define AT_SHA2_CONTROL__DIGEST_SWIZZLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define AT_SHA2_CONTROL__DIGEST_SWIZZLE__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_CONTROL__TYPE uint32_t +#define AT_SHA2_CONTROL__READ 0x0000000fU +#define AT_SHA2_CONTROL__WRITE 0x0000000fU +#define AT_SHA2_CONTROL__PRESERVED 0x00000000U +#define AT_SHA2_CONTROL__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_CONTROL_MACRO__ */ + +/** @} end of control */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_sideload_ctrl */ +/** + * @defgroup at_ahb_sha2_regs_core_sideload_ctrl sideload_ctrl + * @brief Contains register fields associated with sideload_ctrl. definitions. + * @{ + */ +#ifndef __AT_SHA2_SIDELOAD_CTRL_MACRO__ +#define __AT_SHA2_SIDELOAD_CTRL_MACRO__ + +/* macros for field sideload_ptr_clr */ +/** + * @defgroup at_ahb_sha2_regs_core_sideload_ptr_clr_field sideload_ptr_clr_field + * @brief macros for field sideload_ptr_clr + * @details write 1 to clear the write pointer. Not Self-clearing. + * @{ + */ +#define AT_SHA2_SIDELOAD_CTRL__SIDELOAD_PTR_CLR__SHIFT 0 +#define AT_SHA2_SIDELOAD_CTRL__SIDELOAD_PTR_CLR__WIDTH 1 +#define AT_SHA2_SIDELOAD_CTRL__SIDELOAD_PTR_CLR__MASK 0x00000001U +#define AT_SHA2_SIDELOAD_CTRL__SIDELOAD_PTR_CLR__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_SHA2_SIDELOAD_CTRL__SIDELOAD_PTR_CLR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_SHA2_SIDELOAD_CTRL__SIDELOAD_PTR_CLR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AT_SHA2_SIDELOAD_CTRL__SIDELOAD_PTR_CLR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AT_SHA2_SIDELOAD_CTRL__SIDELOAD_PTR_CLR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_SHA2_SIDELOAD_CTRL__SIDELOAD_PTR_CLR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_SHA2_SIDELOAD_CTRL__SIDELOAD_PTR_CLR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sideload_update_en */ +/** + * @defgroup at_ahb_sha2_regs_core_sideload_update_en_field sideload_update_en_field + * @brief macros for field sideload_update_en + * @details write 1 to enable sideload buffer push. + * @{ + */ +#define AT_SHA2_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__SHIFT 1 +#define AT_SHA2_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__WIDTH 1 +#define AT_SHA2_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__MASK 0x00000002U +#define AT_SHA2_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_SHA2_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define AT_SHA2_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define AT_SHA2_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define AT_SHA2_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_SHA2_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_SHA2_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_SIDELOAD_CTRL__TYPE uint32_t +#define AT_SHA2_SIDELOAD_CTRL__READ 0x00000003U +#define AT_SHA2_SIDELOAD_CTRL__WRITE 0x00000003U +#define AT_SHA2_SIDELOAD_CTRL__PRESERVED 0x00000000U +#define AT_SHA2_SIDELOAD_CTRL__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_SIDELOAD_CTRL_MACRO__ */ + +/** @} end of sideload_ctrl */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_cmd */ +/** + * @defgroup at_ahb_sha2_regs_core_cmd cmd + * @brief Contains register fields associated with cmd. definitions. + * @{ + */ +#ifndef __AT_SHA2_CMD_MACRO__ +#define __AT_SHA2_CMD_MACRO__ + +/* macros for field hash_start */ +/** + * @defgroup at_ahb_sha2_regs_core_hash_start_field hash_start_field + * @brief macros for field hash_start + * @details Write 1 to start the SHA256 or HMAC operation. CPU should configure relative information first, such as message_length, secret_key. + * @{ + */ +#define AT_SHA2_CMD__HASH_START__SHIFT 0 +#define AT_SHA2_CMD__HASH_START__WIDTH 1 +#define AT_SHA2_CMD__HASH_START__MASK 0x00000001U +#define AT_SHA2_CMD__HASH_START__READ(src) ((uint32_t)(src) & 0x00000001U) +#define AT_SHA2_CMD__HASH_START__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define AT_SHA2_CMD__HASH_START__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AT_SHA2_CMD__HASH_START__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AT_SHA2_CMD__HASH_START__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_SHA2_CMD__HASH_START__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_SHA2_CMD__HASH_START__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hash_process */ +/** + * @defgroup at_ahb_sha2_regs_core_hash_process_field hash_process_field + * @brief macros for field hash_process + * @details Write 1 to process the final SHA256 digest or calculate the HMAC message hash. + * @{ + */ +#define AT_SHA2_CMD__HASH_PROCESS__SHIFT 1 +#define AT_SHA2_CMD__HASH_PROCESS__WIDTH 1 +#define AT_SHA2_CMD__HASH_PROCESS__MASK 0x00000002U +#define AT_SHA2_CMD__HASH_PROCESS__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_SHA2_CMD__HASH_PROCESS__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define AT_SHA2_CMD__HASH_PROCESS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define AT_SHA2_CMD__HASH_PROCESS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define AT_SHA2_CMD__HASH_PROCESS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_SHA2_CMD__HASH_PROCESS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_SHA2_CMD__HASH_PROCESS__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_CMD__TYPE uint32_t +#define AT_SHA2_CMD__READ 0x00000003U +#define AT_SHA2_CMD__WRITE 0x00000003U +#define AT_SHA2_CMD__PRESERVED 0x00000000U +#define AT_SHA2_CMD__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_CMD_MACRO__ */ + +/** @} end of cmd */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_message_length_lo */ +/** + * @defgroup at_ahb_sha2_regs_core_message_length_lo message_length_lo + * @brief Contains register fields associated with message_length_lo. definitions. + * @{ + */ +#ifndef __AT_SHA2_MESSAGE_LENGTH_LO_MACRO__ +#define __AT_SHA2_MESSAGE_LENGTH_LO_MACRO__ + +/* macros for field length_lo */ +/** + * @defgroup at_ahb_sha2_regs_core_length_lo_field length_lo_field + * @brief macros for field length_lo + * @details Received Message Length calculated by the HMAC in bits [31:0] Message is byte granularity. lower 3bits [2:0] are ignored. + * @{ + */ +#define AT_SHA2_MESSAGE_LENGTH_LO__LENGTH_LO__SHIFT 0 +#define AT_SHA2_MESSAGE_LENGTH_LO__LENGTH_LO__WIDTH 32 +#define AT_SHA2_MESSAGE_LENGTH_LO__LENGTH_LO__MASK 0xffffffffU +#define AT_SHA2_MESSAGE_LENGTH_LO__LENGTH_LO__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_SHA2_MESSAGE_LENGTH_LO__LENGTH_LO__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_MESSAGE_LENGTH_LO__TYPE uint32_t +#define AT_SHA2_MESSAGE_LENGTH_LO__READ 0xffffffffU +#define AT_SHA2_MESSAGE_LENGTH_LO__PRESERVED 0x00000000U +#define AT_SHA2_MESSAGE_LENGTH_LO__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_MESSAGE_LENGTH_LO_MACRO__ */ + +/** @} end of message_length_lo */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_message_length_hi */ +/** + * @defgroup at_ahb_sha2_regs_core_message_length_hi message_length_hi + * @brief Contains register fields associated with message_length_hi. definitions. + * @{ + */ +#ifndef __AT_SHA2_MESSAGE_LENGTH_HI_MACRO__ +#define __AT_SHA2_MESSAGE_LENGTH_HI_MACRO__ + +/* macros for field length_hi */ +/** + * @defgroup at_ahb_sha2_regs_core_length_hi_field length_hi_field + * @brief macros for field length_hi + * @details Received Message Length calculated by the HMAC in bits [63:32] Message is byte granularity. lower 3bits [2:0] are ignored. + * @{ + */ +#define AT_SHA2_MESSAGE_LENGTH_HI__LENGTH_HI__SHIFT 0 +#define AT_SHA2_MESSAGE_LENGTH_HI__LENGTH_HI__WIDTH 32 +#define AT_SHA2_MESSAGE_LENGTH_HI__LENGTH_HI__MASK 0xffffffffU +#define AT_SHA2_MESSAGE_LENGTH_HI__LENGTH_HI__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AT_SHA2_MESSAGE_LENGTH_HI__LENGTH_HI__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_MESSAGE_LENGTH_HI__TYPE uint32_t +#define AT_SHA2_MESSAGE_LENGTH_HI__READ 0xffffffffU +#define AT_SHA2_MESSAGE_LENGTH_HI__PRESERVED 0x00000000U +#define AT_SHA2_MESSAGE_LENGTH_HI__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_MESSAGE_LENGTH_HI_MACRO__ */ + +/** @} end of message_length_hi */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_wipe_v */ +/** + * @defgroup at_ahb_sha2_regs_core_wipe_v wipe_v + * @brief Contains register fields associated with wipe_v. definitions. + * @{ + */ +#ifndef __AT_SHA2_WIPE_V_MACRO__ +#define __AT_SHA2_WIPE_V_MACRO__ + +/* macros for field wipe_v */ +/** + * @defgroup at_ahb_sha2_regs_core_wipe_v_field wipe_v_field + * @brief macros for field wipe_v + * @details a write to this register triggers a wipe_secret action. + * @{ + */ +#define AT_SHA2_WIPE_V__WIPE_V__SHIFT 0 +#define AT_SHA2_WIPE_V__WIPE_V__WIDTH 32 +#define AT_SHA2_WIPE_V__WIPE_V__MASK 0xffffffffU +#define AT_SHA2_WIPE_V__WIPE_V__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_WIPE_V__WIPE_V__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_WIPE_V__WIPE_V__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_SHA2_WIPE_V__WIPE_V__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_SHA2_WIPE_V__WIPE_V__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_WIPE_V__TYPE uint32_t +#define AT_SHA2_WIPE_V__READ 0xffffffffU +#define AT_SHA2_WIPE_V__WRITE 0xffffffffU +#define AT_SHA2_WIPE_V__PRESERVED 0x00000000U +#define AT_SHA2_WIPE_V__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_WIPE_V_MACRO__ */ + +/** @} end of wipe_v */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_fifo_push */ +/** + * @defgroup at_ahb_sha2_regs_core_fifo_push fifo_push + * @brief Contains register fields associated with fifo_push. definitions. + * @{ + */ +#ifndef __AT_SHA2_FIFO_PUSH_MACRO__ +#define __AT_SHA2_FIFO_PUSH_MACRO__ + +/* macros for field wdata */ +/** + * @defgroup at_ahb_sha2_regs_core_wdata_field wdata_field + * @brief macros for field wdata + * @details Message FIFO input port. Byte writes are supported + * @{ + */ +#define AT_SHA2_FIFO_PUSH__WDATA__SHIFT 0 +#define AT_SHA2_FIFO_PUSH__WDATA__WIDTH 32 +#define AT_SHA2_FIFO_PUSH__WDATA__MASK 0xffffffffU +#define AT_SHA2_FIFO_PUSH__WDATA__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_FIFO_PUSH__WDATA__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_FIFO_PUSH__WDATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_SHA2_FIFO_PUSH__WDATA__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AT_SHA2_FIFO_PUSH__WDATA__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_FIFO_PUSH__TYPE uint32_t +#define AT_SHA2_FIFO_PUSH__READ 0xffffffffU +#define AT_SHA2_FIFO_PUSH__WRITE 0xffffffffU +#define AT_SHA2_FIFO_PUSH__PRESERVED 0x00000000U +#define AT_SHA2_FIFO_PUSH__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_FIFO_PUSH_MACRO__ */ + +/** @} end of fifo_push */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_digest0 */ +/** + * @defgroup at_ahb_sha2_regs_core_digest0 digest0 + * @brief Contains register fields associated with digest0. definitions. + * @{ + */ +#ifndef __AT_SHA2_DIGEST0_MACRO__ +#define __AT_SHA2_DIGEST0_MACRO__ + +/* macros for field digest0 */ +/** + * @defgroup at_ahb_sha2_regs_core_digest0_field digest0_field + * @brief macros for field digest0 + * @details Digest output. If HMAC is disabled, the register shows result of SHA256 Order of the digest is: digest[255:0] = {DIGEST0, DIGEST1, DIGEST2, ... , DIGEST7}; + * @{ + */ +#define AT_SHA2_DIGEST0__DIGEST0__SHIFT 0 +#define AT_SHA2_DIGEST0__DIGEST0__WIDTH 32 +#define AT_SHA2_DIGEST0__DIGEST0__MASK 0xffffffffU +#define AT_SHA2_DIGEST0__DIGEST0__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_DIGEST0__DIGEST0__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_DIGEST0__TYPE uint32_t +#define AT_SHA2_DIGEST0__READ 0xffffffffU +#define AT_SHA2_DIGEST0__PRESERVED 0x00000000U +#define AT_SHA2_DIGEST0__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_DIGEST0_MACRO__ */ + +/** @} end of digest0 */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_digest1 */ +/** + * @defgroup at_ahb_sha2_regs_core_digest1 digest1 + * @brief Contains register fields associated with digest1. definitions. + * @{ + */ +#ifndef __AT_SHA2_DIGEST1_MACRO__ +#define __AT_SHA2_DIGEST1_MACRO__ + +/* macros for field digest1 */ +/** + * @defgroup at_ahb_sha2_regs_core_digest1_field digest1_field + * @brief macros for field digest1 + * @details Digest output. If HMAC is disabled, the register shows result of SHA256 Order of the digest is: digest[255:0] = {DIGEST0, DIGEST1, DIGEST2, ... , DIGEST7}; + * @{ + */ +#define AT_SHA2_DIGEST1__DIGEST1__SHIFT 0 +#define AT_SHA2_DIGEST1__DIGEST1__WIDTH 32 +#define AT_SHA2_DIGEST1__DIGEST1__MASK 0xffffffffU +#define AT_SHA2_DIGEST1__DIGEST1__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_DIGEST1__DIGEST1__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_DIGEST1__TYPE uint32_t +#define AT_SHA2_DIGEST1__READ 0xffffffffU +#define AT_SHA2_DIGEST1__PRESERVED 0x00000000U +#define AT_SHA2_DIGEST1__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_DIGEST1_MACRO__ */ + +/** @} end of digest1 */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_digest2 */ +/** + * @defgroup at_ahb_sha2_regs_core_digest2 digest2 + * @brief Contains register fields associated with digest2. definitions. + * @{ + */ +#ifndef __AT_SHA2_DIGEST2_MACRO__ +#define __AT_SHA2_DIGEST2_MACRO__ + +/* macros for field digest2 */ +/** + * @defgroup at_ahb_sha2_regs_core_digest2_field digest2_field + * @brief macros for field digest2 + * @details Digest output. If HMAC is disabled, the register shows result of SHA256 Order of the digest is: digest[255:0] = {DIGEST0, DIGEST1, DIGEST2, ... , DIGEST7}; + * @{ + */ +#define AT_SHA2_DIGEST2__DIGEST2__SHIFT 0 +#define AT_SHA2_DIGEST2__DIGEST2__WIDTH 32 +#define AT_SHA2_DIGEST2__DIGEST2__MASK 0xffffffffU +#define AT_SHA2_DIGEST2__DIGEST2__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_DIGEST2__DIGEST2__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_DIGEST2__TYPE uint32_t +#define AT_SHA2_DIGEST2__READ 0xffffffffU +#define AT_SHA2_DIGEST2__PRESERVED 0x00000000U +#define AT_SHA2_DIGEST2__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_DIGEST2_MACRO__ */ + +/** @} end of digest2 */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_digest3 */ +/** + * @defgroup at_ahb_sha2_regs_core_digest3 digest3 + * @brief Contains register fields associated with digest3. definitions. + * @{ + */ +#ifndef __AT_SHA2_DIGEST3_MACRO__ +#define __AT_SHA2_DIGEST3_MACRO__ + +/* macros for field digest3 */ +/** + * @defgroup at_ahb_sha2_regs_core_digest3_field digest3_field + * @brief macros for field digest3 + * @details Digest output. If HMAC is disabled, the register shows result of SHA256 Order of the digest is: digest[255:0] = {DIGEST0, DIGEST1, DIGEST2, ... , DIGEST7}; + * @{ + */ +#define AT_SHA2_DIGEST3__DIGEST3__SHIFT 0 +#define AT_SHA2_DIGEST3__DIGEST3__WIDTH 32 +#define AT_SHA2_DIGEST3__DIGEST3__MASK 0xffffffffU +#define AT_SHA2_DIGEST3__DIGEST3__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_DIGEST3__DIGEST3__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_DIGEST3__TYPE uint32_t +#define AT_SHA2_DIGEST3__READ 0xffffffffU +#define AT_SHA2_DIGEST3__PRESERVED 0x00000000U +#define AT_SHA2_DIGEST3__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_DIGEST3_MACRO__ */ + +/** @} end of digest3 */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_digest4 */ +/** + * @defgroup at_ahb_sha2_regs_core_digest4 digest4 + * @brief Contains register fields associated with digest4. definitions. + * @{ + */ +#ifndef __AT_SHA2_DIGEST4_MACRO__ +#define __AT_SHA2_DIGEST4_MACRO__ + +/* macros for field digest4 */ +/** + * @defgroup at_ahb_sha2_regs_core_digest4_field digest4_field + * @brief macros for field digest4 + * @details Digest output. If HMAC is disabled, the register shows result of SHA256 Order of the digest is: digest[255:0] = {DIGEST0, DIGEST1, DIGEST2, ... , DIGEST7}; + * @{ + */ +#define AT_SHA2_DIGEST4__DIGEST4__SHIFT 0 +#define AT_SHA2_DIGEST4__DIGEST4__WIDTH 32 +#define AT_SHA2_DIGEST4__DIGEST4__MASK 0xffffffffU +#define AT_SHA2_DIGEST4__DIGEST4__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_DIGEST4__DIGEST4__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_DIGEST4__TYPE uint32_t +#define AT_SHA2_DIGEST4__READ 0xffffffffU +#define AT_SHA2_DIGEST4__PRESERVED 0x00000000U +#define AT_SHA2_DIGEST4__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_DIGEST4_MACRO__ */ + +/** @} end of digest4 */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_digest5 */ +/** + * @defgroup at_ahb_sha2_regs_core_digest5 digest5 + * @brief Contains register fields associated with digest5. definitions. + * @{ + */ +#ifndef __AT_SHA2_DIGEST5_MACRO__ +#define __AT_SHA2_DIGEST5_MACRO__ + +/* macros for field digest5 */ +/** + * @defgroup at_ahb_sha2_regs_core_digest5_field digest5_field + * @brief macros for field digest5 + * @details Digest output. If HMAC is disabled, the register shows result of SHA256 Order of the digest is: digest[255:0] = {DIGEST0, DIGEST1, DIGEST2, ... , DIGEST7}; + * @{ + */ +#define AT_SHA2_DIGEST5__DIGEST5__SHIFT 0 +#define AT_SHA2_DIGEST5__DIGEST5__WIDTH 32 +#define AT_SHA2_DIGEST5__DIGEST5__MASK 0xffffffffU +#define AT_SHA2_DIGEST5__DIGEST5__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_DIGEST5__DIGEST5__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_DIGEST5__TYPE uint32_t +#define AT_SHA2_DIGEST5__READ 0xffffffffU +#define AT_SHA2_DIGEST5__PRESERVED 0x00000000U +#define AT_SHA2_DIGEST5__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_DIGEST5_MACRO__ */ + +/** @} end of digest5 */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_digest6 */ +/** + * @defgroup at_ahb_sha2_regs_core_digest6 digest6 + * @brief Contains register fields associated with digest6. definitions. + * @{ + */ +#ifndef __AT_SHA2_DIGEST6_MACRO__ +#define __AT_SHA2_DIGEST6_MACRO__ + +/* macros for field digest6 */ +/** + * @defgroup at_ahb_sha2_regs_core_digest6_field digest6_field + * @brief macros for field digest6 + * @details Digest output. If HMAC is disabled, the register shows result of SHA256 Order of the digest is: digest[255:0] = {DIGEST0, DIGEST1, DIGEST2, ... , DIGEST7}; + * @{ + */ +#define AT_SHA2_DIGEST6__DIGEST6__SHIFT 0 +#define AT_SHA2_DIGEST6__DIGEST6__WIDTH 32 +#define AT_SHA2_DIGEST6__DIGEST6__MASK 0xffffffffU +#define AT_SHA2_DIGEST6__DIGEST6__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_DIGEST6__DIGEST6__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_DIGEST6__TYPE uint32_t +#define AT_SHA2_DIGEST6__READ 0xffffffffU +#define AT_SHA2_DIGEST6__PRESERVED 0x00000000U +#define AT_SHA2_DIGEST6__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_DIGEST6_MACRO__ */ + +/** @} end of digest6 */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_digest7 */ +/** + * @defgroup at_ahb_sha2_regs_core_digest7 digest7 + * @brief Contains register fields associated with digest7. definitions. + * @{ + */ +#ifndef __AT_SHA2_DIGEST7_MACRO__ +#define __AT_SHA2_DIGEST7_MACRO__ + +/* macros for field digest7 */ +/** + * @defgroup at_ahb_sha2_regs_core_digest7_field digest7_field + * @brief macros for field digest7 + * @details Digest output. If HMAC is disabled, the register shows result of SHA256 Order of the digest is: digest[255:0] = {DIGEST0, DIGEST1, DIGEST2, ... , DIGEST7}; + * @{ + */ +#define AT_SHA2_DIGEST7__DIGEST7__SHIFT 0 +#define AT_SHA2_DIGEST7__DIGEST7__WIDTH 32 +#define AT_SHA2_DIGEST7__DIGEST7__MASK 0xffffffffU +#define AT_SHA2_DIGEST7__DIGEST7__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_DIGEST7__DIGEST7__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_DIGEST7__TYPE uint32_t +#define AT_SHA2_DIGEST7__READ 0xffffffffU +#define AT_SHA2_DIGEST7__PRESERVED 0x00000000U +#define AT_SHA2_DIGEST7__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_DIGEST7_MACRO__ */ + +/** @} end of digest7 */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_key_0 */ +/** + * @defgroup at_ahb_sha2_regs_core_key_0 key_0 + * @brief SHA256 assumes secret key is hashed 256bit key. Order of the secret key is: key[255:0] = {KEY0, KEY1, KEY2, ... , KEY7}; definitions. + * @{ + */ +#ifndef __AT_SHA2_KEY_0_MACRO__ +#define __AT_SHA2_KEY_0_MACRO__ + +/* macros for field key_0 */ +/** + * @defgroup at_ahb_sha2_regs_core_key_0_field key_0_field + * @brief macros for field key_0 + * @details 32-bit chunk of 256-bit Secret Key. + * @{ + */ +#define AT_SHA2_KEY_0__KEY_0__SHIFT 0 +#define AT_SHA2_KEY_0__KEY_0__WIDTH 32 +#define AT_SHA2_KEY_0__KEY_0__MASK 0xffffffffU +#define AT_SHA2_KEY_0__KEY_0__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_KEY_0__KEY_0__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_KEY_0__KEY_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_SHA2_KEY_0__KEY_0__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define AT_SHA2_KEY_0__KEY_0__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_KEY_0__TYPE uint32_t +#define AT_SHA2_KEY_0__READ 0xffffffffU +#define AT_SHA2_KEY_0__WRITE 0xffffffffU +#define AT_SHA2_KEY_0__PRESERVED 0x00000000U +#define AT_SHA2_KEY_0__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_KEY_0_MACRO__ */ + +/** @} end of key_0 */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_key_1 */ +/** + * @defgroup at_ahb_sha2_regs_core_key_1 key_1 + * @brief SHA256 assumes secret key is hashed 256bit key. Order of the secret key is: key[255:0] = {KEY0, KEY1, KEY2, ... , KEY7}; definitions. + * @{ + */ +#ifndef __AT_SHA2_KEY_1_MACRO__ +#define __AT_SHA2_KEY_1_MACRO__ + +/* macros for field key_1 */ +/** + * @defgroup at_ahb_sha2_regs_core_key_1_field key_1_field + * @brief macros for field key_1 + * @details 32-bit chunk of 256-bit Secret Key. + * @{ + */ +#define AT_SHA2_KEY_1__KEY_1__SHIFT 0 +#define AT_SHA2_KEY_1__KEY_1__WIDTH 32 +#define AT_SHA2_KEY_1__KEY_1__MASK 0xffffffffU +#define AT_SHA2_KEY_1__KEY_1__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_KEY_1__KEY_1__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_KEY_1__KEY_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_SHA2_KEY_1__KEY_1__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define AT_SHA2_KEY_1__KEY_1__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_KEY_1__TYPE uint32_t +#define AT_SHA2_KEY_1__READ 0xffffffffU +#define AT_SHA2_KEY_1__WRITE 0xffffffffU +#define AT_SHA2_KEY_1__PRESERVED 0x00000000U +#define AT_SHA2_KEY_1__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_KEY_1_MACRO__ */ + +/** @} end of key_1 */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_key_2 */ +/** + * @defgroup at_ahb_sha2_regs_core_key_2 key_2 + * @brief SHA256 assumes secret key is hashed 256bit key. Order of the secret key is: key[255:0] = {KEY0, KEY1, KEY2, ... , KEY7}; definitions. + * @{ + */ +#ifndef __AT_SHA2_KEY_2_MACRO__ +#define __AT_SHA2_KEY_2_MACRO__ + +/* macros for field key_2 */ +/** + * @defgroup at_ahb_sha2_regs_core_key_2_field key_2_field + * @brief macros for field key_2 + * @details 32-bit chunk of 256-bit Secret Key. + * @{ + */ +#define AT_SHA2_KEY_2__KEY_2__SHIFT 0 +#define AT_SHA2_KEY_2__KEY_2__WIDTH 32 +#define AT_SHA2_KEY_2__KEY_2__MASK 0xffffffffU +#define AT_SHA2_KEY_2__KEY_2__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_KEY_2__KEY_2__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_KEY_2__KEY_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_SHA2_KEY_2__KEY_2__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define AT_SHA2_KEY_2__KEY_2__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_KEY_2__TYPE uint32_t +#define AT_SHA2_KEY_2__READ 0xffffffffU +#define AT_SHA2_KEY_2__WRITE 0xffffffffU +#define AT_SHA2_KEY_2__PRESERVED 0x00000000U +#define AT_SHA2_KEY_2__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_KEY_2_MACRO__ */ + +/** @} end of key_2 */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_key_3 */ +/** + * @defgroup at_ahb_sha2_regs_core_key_3 key_3 + * @brief SHA256 assumes secret key is hashed 256bit key. Order of the secret key is: key[255:0] = {KEY0, KEY1, KEY2, ... , KEY7}; definitions. + * @{ + */ +#ifndef __AT_SHA2_KEY_3_MACRO__ +#define __AT_SHA2_KEY_3_MACRO__ + +/* macros for field key_3 */ +/** + * @defgroup at_ahb_sha2_regs_core_key_3_field key_3_field + * @brief macros for field key_3 + * @details 32-bit chunk of 256-bit Secret Key. + * @{ + */ +#define AT_SHA2_KEY_3__KEY_3__SHIFT 0 +#define AT_SHA2_KEY_3__KEY_3__WIDTH 32 +#define AT_SHA2_KEY_3__KEY_3__MASK 0xffffffffU +#define AT_SHA2_KEY_3__KEY_3__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_KEY_3__KEY_3__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_KEY_3__KEY_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_SHA2_KEY_3__KEY_3__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define AT_SHA2_KEY_3__KEY_3__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_KEY_3__TYPE uint32_t +#define AT_SHA2_KEY_3__READ 0xffffffffU +#define AT_SHA2_KEY_3__WRITE 0xffffffffU +#define AT_SHA2_KEY_3__PRESERVED 0x00000000U +#define AT_SHA2_KEY_3__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_KEY_3_MACRO__ */ + +/** @} end of key_3 */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_key_4 */ +/** + * @defgroup at_ahb_sha2_regs_core_key_4 key_4 + * @brief SHA256 assumes secret key is hashed 256bit key. Order of the secret key is: key[255:0] = {KEY0, KEY1, KEY2, ... , KEY7}; definitions. + * @{ + */ +#ifndef __AT_SHA2_KEY_4_MACRO__ +#define __AT_SHA2_KEY_4_MACRO__ + +/* macros for field key_4 */ +/** + * @defgroup at_ahb_sha2_regs_core_key_4_field key_4_field + * @brief macros for field key_4 + * @details 32-bit chunk of 256-bit Secret Key. + * @{ + */ +#define AT_SHA2_KEY_4__KEY_4__SHIFT 0 +#define AT_SHA2_KEY_4__KEY_4__WIDTH 32 +#define AT_SHA2_KEY_4__KEY_4__MASK 0xffffffffU +#define AT_SHA2_KEY_4__KEY_4__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_KEY_4__KEY_4__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_KEY_4__KEY_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_SHA2_KEY_4__KEY_4__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define AT_SHA2_KEY_4__KEY_4__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_KEY_4__TYPE uint32_t +#define AT_SHA2_KEY_4__READ 0xffffffffU +#define AT_SHA2_KEY_4__WRITE 0xffffffffU +#define AT_SHA2_KEY_4__PRESERVED 0x00000000U +#define AT_SHA2_KEY_4__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_KEY_4_MACRO__ */ + +/** @} end of key_4 */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_key_5 */ +/** + * @defgroup at_ahb_sha2_regs_core_key_5 key_5 + * @brief SHA256 assumes secret key is hashed 256bit key. Order of the secret key is: key[255:0] = {KEY0, KEY1, KEY2, ... , KEY7}; definitions. + * @{ + */ +#ifndef __AT_SHA2_KEY_5_MACRO__ +#define __AT_SHA2_KEY_5_MACRO__ + +/* macros for field key_5 */ +/** + * @defgroup at_ahb_sha2_regs_core_key_5_field key_5_field + * @brief macros for field key_5 + * @details 32-bit chunk of 256-bit Secret Key. + * @{ + */ +#define AT_SHA2_KEY_5__KEY_5__SHIFT 0 +#define AT_SHA2_KEY_5__KEY_5__WIDTH 32 +#define AT_SHA2_KEY_5__KEY_5__MASK 0xffffffffU +#define AT_SHA2_KEY_5__KEY_5__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_KEY_5__KEY_5__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_KEY_5__KEY_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_SHA2_KEY_5__KEY_5__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define AT_SHA2_KEY_5__KEY_5__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_KEY_5__TYPE uint32_t +#define AT_SHA2_KEY_5__READ 0xffffffffU +#define AT_SHA2_KEY_5__WRITE 0xffffffffU +#define AT_SHA2_KEY_5__PRESERVED 0x00000000U +#define AT_SHA2_KEY_5__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_KEY_5_MACRO__ */ + +/** @} end of key_5 */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_key_6 */ +/** + * @defgroup at_ahb_sha2_regs_core_key_6 key_6 + * @brief SHA256 assumes secret key is hashed 256bit key. Order of the secret key is: key[255:0] = {KEY0, KEY1, KEY2, ... , KEY7}; definitions. + * @{ + */ +#ifndef __AT_SHA2_KEY_6_MACRO__ +#define __AT_SHA2_KEY_6_MACRO__ + +/* macros for field key_6 */ +/** + * @defgroup at_ahb_sha2_regs_core_key_6_field key_6_field + * @brief macros for field key_6 + * @details 32-bit chunk of 256-bit Secret Key. + * @{ + */ +#define AT_SHA2_KEY_6__KEY_6__SHIFT 0 +#define AT_SHA2_KEY_6__KEY_6__WIDTH 32 +#define AT_SHA2_KEY_6__KEY_6__MASK 0xffffffffU +#define AT_SHA2_KEY_6__KEY_6__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_KEY_6__KEY_6__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_KEY_6__KEY_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_SHA2_KEY_6__KEY_6__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define AT_SHA2_KEY_6__KEY_6__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_KEY_6__TYPE uint32_t +#define AT_SHA2_KEY_6__READ 0xffffffffU +#define AT_SHA2_KEY_6__WRITE 0xffffffffU +#define AT_SHA2_KEY_6__PRESERVED 0x00000000U +#define AT_SHA2_KEY_6__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_KEY_6_MACRO__ */ + +/** @} end of key_6 */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_key_7 */ +/** + * @defgroup at_ahb_sha2_regs_core_key_7 key_7 + * @brief SHA256 assumes secret key is hashed 256bit key. Order of the secret key is: key[255:0] = {KEY0, KEY1, KEY2, ... , KEY7}; definitions. + * @{ + */ +#ifndef __AT_SHA2_KEY_7_MACRO__ +#define __AT_SHA2_KEY_7_MACRO__ + +/* macros for field key_7 */ +/** + * @defgroup at_ahb_sha2_regs_core_key_7_field key_7_field + * @brief macros for field key_7 + * @details 32-bit chunk of 256-bit Secret Key. + * @{ + */ +#define AT_SHA2_KEY_7__KEY_7__SHIFT 0 +#define AT_SHA2_KEY_7__KEY_7__WIDTH 32 +#define AT_SHA2_KEY_7__KEY_7__MASK 0xffffffffU +#define AT_SHA2_KEY_7__KEY_7__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_KEY_7__KEY_7__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_KEY_7__KEY_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AT_SHA2_KEY_7__KEY_7__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define AT_SHA2_KEY_7__KEY_7__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_KEY_7__TYPE uint32_t +#define AT_SHA2_KEY_7__READ 0xffffffffU +#define AT_SHA2_KEY_7__WRITE 0xffffffffU +#define AT_SHA2_KEY_7__PRESERVED 0x00000000U +#define AT_SHA2_KEY_7__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_KEY_7_MACRO__ */ + +/** @} end of key_7 */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_status */ +/** + * @defgroup at_ahb_sha2_regs_core_status status + * @brief Contains register fields associated with status. definitions. + * @{ + */ +#ifndef __AT_SHA2_STATUS_MACRO__ +#define __AT_SHA2_STATUS_MACRO__ + +/* macros for field fifo_empty */ +/** + * @defgroup at_ahb_sha2_regs_core_fifo_empty_field fifo_empty_field + * @brief macros for field fifo_empty + * @details FIFO empty + * @{ + */ +#define AT_SHA2_STATUS__FIFO_EMPTY__SHIFT 0 +#define AT_SHA2_STATUS__FIFO_EMPTY__WIDTH 1 +#define AT_SHA2_STATUS__FIFO_EMPTY__MASK 0x00000001U +#define AT_SHA2_STATUS__FIFO_EMPTY__READ(src) ((uint32_t)(src) & 0x00000001U) +#define AT_SHA2_STATUS__FIFO_EMPTY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_SHA2_STATUS__FIFO_EMPTY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_SHA2_STATUS__FIFO_EMPTY__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field fifo_full */ +/** + * @defgroup at_ahb_sha2_regs_core_fifo_full_field fifo_full_field + * @brief macros for field fifo_full + * @details FIFO full. Data written to the FIFO whilst it is full will cause back-pressure on the interconnect + * @{ + */ +#define AT_SHA2_STATUS__FIFO_FULL__SHIFT 1 +#define AT_SHA2_STATUS__FIFO_FULL__WIDTH 1 +#define AT_SHA2_STATUS__FIFO_FULL__MASK 0x00000002U +#define AT_SHA2_STATUS__FIFO_FULL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_SHA2_STATUS__FIFO_FULL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_SHA2_STATUS__FIFO_FULL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_SHA2_STATUS__FIFO_FULL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reserved */ +/** + * @defgroup at_ahb_sha2_regs_core_reserved_field reserved_field + * @brief macros for field reserved + * @{ + */ +#define AT_SHA2_STATUS__RESERVED__SHIFT 2 +#define AT_SHA2_STATUS__RESERVED__WIDTH 2 +#define AT_SHA2_STATUS__RESERVED__MASK 0x0000000cU +#define AT_SHA2_STATUS__RESERVED__READ(src) \ + (((uint32_t)(src)\ + & 0x0000000cU) >> 2) +#define AT_SHA2_STATUS__RESERVED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fifo_depth */ +/** + * @defgroup at_ahb_sha2_regs_core_fifo_depth_field fifo_depth_field + * @brief macros for field fifo_depth + * @details FIFO entry count + * @{ + */ +#define AT_SHA2_STATUS__FIFO_DEPTH__SHIFT 4 +#define AT_SHA2_STATUS__FIFO_DEPTH__WIDTH 5 +#define AT_SHA2_STATUS__FIFO_DEPTH__MASK 0x000001f0U +#define AT_SHA2_STATUS__FIFO_DEPTH__READ(src) \ + (((uint32_t)(src)\ + & 0x000001f0U) >> 4) +#define AT_SHA2_STATUS__FIFO_DEPTH__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_STATUS__TYPE uint32_t +#define AT_SHA2_STATUS__READ 0x000001ffU +#define AT_SHA2_STATUS__PRESERVED 0x00000000U +#define AT_SHA2_STATUS__RESET_VALUE 0x00000001U + +#endif /* __AT_SHA2_STATUS_MACRO__ */ + +/** @} end of status */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_interrupt_status */ +/** + * @defgroup at_ahb_sha2_regs_core_interrupt_status interrupt_status + * @brief Contains register fields associated with interrupt_status. definitions. + * @{ + */ +#ifndef __AT_SHA2_INTERRUPT_STATUS_MACRO__ +#define __AT_SHA2_INTERRUPT_STATUS_MACRO__ + +/* macros for field fifo_empty */ +/** + * @defgroup at_ahb_sha2_regs_core_fifo_empty_field fifo_empty_field + * @brief macros for field fifo_empty + * @details Message FIFO empty condition + * @{ + */ +#define AT_SHA2_INTERRUPT_STATUS__FIFO_EMPTY__SHIFT 0 +#define AT_SHA2_INTERRUPT_STATUS__FIFO_EMPTY__WIDTH 1 +#define AT_SHA2_INTERRUPT_STATUS__FIFO_EMPTY__MASK 0x00000001U +#define AT_SHA2_INTERRUPT_STATUS__FIFO_EMPTY__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_SHA2_INTERRUPT_STATUS__FIFO_EMPTY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_SHA2_INTERRUPT_STATUS__FIFO_EMPTY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_SHA2_INTERRUPT_STATUS__FIFO_EMPTY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fifo_full */ +/** + * @defgroup at_ahb_sha2_regs_core_fifo_full_field fifo_full_field + * @brief macros for field fifo_full + * @details Message FIFO full condition + * @{ + */ +#define AT_SHA2_INTERRUPT_STATUS__FIFO_FULL__SHIFT 1 +#define AT_SHA2_INTERRUPT_STATUS__FIFO_FULL__WIDTH 1 +#define AT_SHA2_INTERRUPT_STATUS__FIFO_FULL__MASK 0x00000002U +#define AT_SHA2_INTERRUPT_STATUS__FIFO_FULL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_SHA2_INTERRUPT_STATUS__FIFO_FULL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_SHA2_INTERRUPT_STATUS__FIFO_FULL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_SHA2_INTERRUPT_STATUS__FIFO_FULL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field chunk_done */ +/** + * @defgroup at_ahb_sha2_regs_core_chunk_done_field chunk_done_field + * @brief macros for field chunk_done + * @details one chunk of message done. (512 bits of message and padded bits) + * @{ + */ +#define AT_SHA2_INTERRUPT_STATUS__CHUNK_DONE__SHIFT 2 +#define AT_SHA2_INTERRUPT_STATUS__CHUNK_DONE__WIDTH 1 +#define AT_SHA2_INTERRUPT_STATUS__CHUNK_DONE__MASK 0x00000004U +#define AT_SHA2_INTERRUPT_STATUS__CHUNK_DONE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define AT_SHA2_INTERRUPT_STATUS__CHUNK_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define AT_SHA2_INTERRUPT_STATUS__CHUNK_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define AT_SHA2_INTERRUPT_STATUS__CHUNK_DONE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hmac_done */ +/** + * @defgroup at_ahb_sha2_regs_core_hmac_done_field hmac_done_field + * @brief macros for field hmac_done + * @details HMAC-256 completes a message with key + * @{ + */ +#define AT_SHA2_INTERRUPT_STATUS__HMAC_DONE__SHIFT 3 +#define AT_SHA2_INTERRUPT_STATUS__HMAC_DONE__WIDTH 1 +#define AT_SHA2_INTERRUPT_STATUS__HMAC_DONE__MASK 0x00000008U +#define AT_SHA2_INTERRUPT_STATUS__HMAC_DONE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define AT_SHA2_INTERRUPT_STATUS__HMAC_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define AT_SHA2_INTERRUPT_STATUS__HMAC_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define AT_SHA2_INTERRUPT_STATUS__HMAC_DONE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field push_when_full */ +/** + * @defgroup at_ahb_sha2_regs_core_push_when_full_field push_when_full_field + * @brief macros for field push_when_full + * @details push when Message FIFO empty condition + * @{ + */ +#define AT_SHA2_INTERRUPT_STATUS__PUSH_WHEN_FULL__SHIFT 4 +#define AT_SHA2_INTERRUPT_STATUS__PUSH_WHEN_FULL__WIDTH 1 +#define AT_SHA2_INTERRUPT_STATUS__PUSH_WHEN_FULL__MASK 0x00000010U +#define AT_SHA2_INTERRUPT_STATUS__PUSH_WHEN_FULL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define AT_SHA2_INTERRUPT_STATUS__PUSH_WHEN_FULL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define AT_SHA2_INTERRUPT_STATUS__PUSH_WHEN_FULL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define AT_SHA2_INTERRUPT_STATUS__PUSH_WHEN_FULL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pop_when_empty */ +/** + * @defgroup at_ahb_sha2_regs_core_pop_when_empty_field pop_when_empty_field + * @brief macros for field pop_when_empty + * @details pop when Message FIFO is full condition + * @{ + */ +#define AT_SHA2_INTERRUPT_STATUS__POP_WHEN_EMPTY__SHIFT 5 +#define AT_SHA2_INTERRUPT_STATUS__POP_WHEN_EMPTY__WIDTH 1 +#define AT_SHA2_INTERRUPT_STATUS__POP_WHEN_EMPTY__MASK 0x00000020U +#define AT_SHA2_INTERRUPT_STATUS__POP_WHEN_EMPTY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define AT_SHA2_INTERRUPT_STATUS__POP_WHEN_EMPTY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define AT_SHA2_INTERRUPT_STATUS__POP_WHEN_EMPTY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define AT_SHA2_INTERRUPT_STATUS__POP_WHEN_EMPTY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hmac_err */ +/** + * @defgroup at_ahb_sha2_regs_core_hmac_err_field hmac_err_field + * @brief macros for field hmac_err + * @details HMAC error occurred. ERR_CODE register shows which error occurred + * @{ + */ +#define AT_SHA2_INTERRUPT_STATUS__HMAC_ERR__SHIFT 6 +#define AT_SHA2_INTERRUPT_STATUS__HMAC_ERR__WIDTH 1 +#define AT_SHA2_INTERRUPT_STATUS__HMAC_ERR__MASK 0x00000040U +#define AT_SHA2_INTERRUPT_STATUS__HMAC_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define AT_SHA2_INTERRUPT_STATUS__HMAC_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define AT_SHA2_INTERRUPT_STATUS__HMAC_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define AT_SHA2_INTERRUPT_STATUS__HMAC_ERR__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_INTERRUPT_STATUS__TYPE uint32_t +#define AT_SHA2_INTERRUPT_STATUS__READ 0x0000007fU +#define AT_SHA2_INTERRUPT_STATUS__PRESERVED 0x00000000U +#define AT_SHA2_INTERRUPT_STATUS__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_INTERRUPT_STATUS_MACRO__ */ + +/** @} end of interrupt_status */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_interrupt_mask */ +/** + * @defgroup at_ahb_sha2_regs_core_interrupt_mask interrupt_mask + * @brief Contains register fields associated with interrupt_mask. definitions. + * @{ + */ +#ifndef __AT_SHA2_INTERRUPT_MASK_MACRO__ +#define __AT_SHA2_INTERRUPT_MASK_MACRO__ + +/* macros for field fifo_empty */ +/** + * @defgroup at_ahb_sha2_regs_core_fifo_empty_field fifo_empty_field + * @brief macros for field fifo_empty + * @details interrupt mask bit + * @{ + */ +#define AT_SHA2_INTERRUPT_MASK__FIFO_EMPTY__SHIFT 0 +#define AT_SHA2_INTERRUPT_MASK__FIFO_EMPTY__WIDTH 1 +#define AT_SHA2_INTERRUPT_MASK__FIFO_EMPTY__MASK 0x00000001U +#define AT_SHA2_INTERRUPT_MASK__FIFO_EMPTY__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_SHA2_INTERRUPT_MASK__FIFO_EMPTY__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AT_SHA2_INTERRUPT_MASK__FIFO_EMPTY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AT_SHA2_INTERRUPT_MASK__FIFO_EMPTY__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AT_SHA2_INTERRUPT_MASK__FIFO_EMPTY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AT_SHA2_INTERRUPT_MASK__FIFO_EMPTY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AT_SHA2_INTERRUPT_MASK__FIFO_EMPTY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fifo_full */ +/** + * @defgroup at_ahb_sha2_regs_core_fifo_full_field fifo_full_field + * @brief macros for field fifo_full + * @details interrupt mask bit + * @{ + */ +#define AT_SHA2_INTERRUPT_MASK__FIFO_FULL__SHIFT 1 +#define AT_SHA2_INTERRUPT_MASK__FIFO_FULL__WIDTH 1 +#define AT_SHA2_INTERRUPT_MASK__FIFO_FULL__MASK 0x00000002U +#define AT_SHA2_INTERRUPT_MASK__FIFO_FULL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AT_SHA2_INTERRUPT_MASK__FIFO_FULL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define AT_SHA2_INTERRUPT_MASK__FIFO_FULL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define AT_SHA2_INTERRUPT_MASK__FIFO_FULL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define AT_SHA2_INTERRUPT_MASK__FIFO_FULL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AT_SHA2_INTERRUPT_MASK__FIFO_FULL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AT_SHA2_INTERRUPT_MASK__FIFO_FULL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field chunk_done */ +/** + * @defgroup at_ahb_sha2_regs_core_chunk_done_field chunk_done_field + * @brief macros for field chunk_done + * @details interrupt mask bit + * @{ + */ +#define AT_SHA2_INTERRUPT_MASK__CHUNK_DONE__SHIFT 2 +#define AT_SHA2_INTERRUPT_MASK__CHUNK_DONE__WIDTH 1 +#define AT_SHA2_INTERRUPT_MASK__CHUNK_DONE__MASK 0x00000004U +#define AT_SHA2_INTERRUPT_MASK__CHUNK_DONE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define AT_SHA2_INTERRUPT_MASK__CHUNK_DONE__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define AT_SHA2_INTERRUPT_MASK__CHUNK_DONE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define AT_SHA2_INTERRUPT_MASK__CHUNK_DONE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define AT_SHA2_INTERRUPT_MASK__CHUNK_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define AT_SHA2_INTERRUPT_MASK__CHUNK_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define AT_SHA2_INTERRUPT_MASK__CHUNK_DONE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hmac_done */ +/** + * @defgroup at_ahb_sha2_regs_core_hmac_done_field hmac_done_field + * @brief macros for field hmac_done + * @details interrupt mask bit + * @{ + */ +#define AT_SHA2_INTERRUPT_MASK__HMAC_DONE__SHIFT 3 +#define AT_SHA2_INTERRUPT_MASK__HMAC_DONE__WIDTH 1 +#define AT_SHA2_INTERRUPT_MASK__HMAC_DONE__MASK 0x00000008U +#define AT_SHA2_INTERRUPT_MASK__HMAC_DONE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define AT_SHA2_INTERRUPT_MASK__HMAC_DONE__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define AT_SHA2_INTERRUPT_MASK__HMAC_DONE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define AT_SHA2_INTERRUPT_MASK__HMAC_DONE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define AT_SHA2_INTERRUPT_MASK__HMAC_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define AT_SHA2_INTERRUPT_MASK__HMAC_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define AT_SHA2_INTERRUPT_MASK__HMAC_DONE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field push_when_full */ +/** + * @defgroup at_ahb_sha2_regs_core_push_when_full_field push_when_full_field + * @brief macros for field push_when_full + * @details interrupt mask bit + * @{ + */ +#define AT_SHA2_INTERRUPT_MASK__PUSH_WHEN_FULL__SHIFT 4 +#define AT_SHA2_INTERRUPT_MASK__PUSH_WHEN_FULL__WIDTH 1 +#define AT_SHA2_INTERRUPT_MASK__PUSH_WHEN_FULL__MASK 0x00000010U +#define AT_SHA2_INTERRUPT_MASK__PUSH_WHEN_FULL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define AT_SHA2_INTERRUPT_MASK__PUSH_WHEN_FULL__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define AT_SHA2_INTERRUPT_MASK__PUSH_WHEN_FULL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define AT_SHA2_INTERRUPT_MASK__PUSH_WHEN_FULL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define AT_SHA2_INTERRUPT_MASK__PUSH_WHEN_FULL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define AT_SHA2_INTERRUPT_MASK__PUSH_WHEN_FULL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define AT_SHA2_INTERRUPT_MASK__PUSH_WHEN_FULL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pop_when_empty */ +/** + * @defgroup at_ahb_sha2_regs_core_pop_when_empty_field pop_when_empty_field + * @brief macros for field pop_when_empty + * @details interrupt mask bit + * @{ + */ +#define AT_SHA2_INTERRUPT_MASK__POP_WHEN_EMPTY__SHIFT 5 +#define AT_SHA2_INTERRUPT_MASK__POP_WHEN_EMPTY__WIDTH 1 +#define AT_SHA2_INTERRUPT_MASK__POP_WHEN_EMPTY__MASK 0x00000020U +#define AT_SHA2_INTERRUPT_MASK__POP_WHEN_EMPTY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define AT_SHA2_INTERRUPT_MASK__POP_WHEN_EMPTY__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define AT_SHA2_INTERRUPT_MASK__POP_WHEN_EMPTY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define AT_SHA2_INTERRUPT_MASK__POP_WHEN_EMPTY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define AT_SHA2_INTERRUPT_MASK__POP_WHEN_EMPTY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define AT_SHA2_INTERRUPT_MASK__POP_WHEN_EMPTY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define AT_SHA2_INTERRUPT_MASK__POP_WHEN_EMPTY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hmac_err */ +/** + * @defgroup at_ahb_sha2_regs_core_hmac_err_field hmac_err_field + * @brief macros for field hmac_err + * @details interrupt mask bit + * @{ + */ +#define AT_SHA2_INTERRUPT_MASK__HMAC_ERR__SHIFT 6 +#define AT_SHA2_INTERRUPT_MASK__HMAC_ERR__WIDTH 1 +#define AT_SHA2_INTERRUPT_MASK__HMAC_ERR__MASK 0x00000040U +#define AT_SHA2_INTERRUPT_MASK__HMAC_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define AT_SHA2_INTERRUPT_MASK__HMAC_ERR__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define AT_SHA2_INTERRUPT_MASK__HMAC_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define AT_SHA2_INTERRUPT_MASK__HMAC_ERR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define AT_SHA2_INTERRUPT_MASK__HMAC_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define AT_SHA2_INTERRUPT_MASK__HMAC_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define AT_SHA2_INTERRUPT_MASK__HMAC_ERR__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_INTERRUPT_MASK__TYPE uint32_t +#define AT_SHA2_INTERRUPT_MASK__READ 0x0000007fU +#define AT_SHA2_INTERRUPT_MASK__WRITE 0x0000007fU +#define AT_SHA2_INTERRUPT_MASK__PRESERVED 0x00000000U +#define AT_SHA2_INTERRUPT_MASK__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_INTERRUPT_MASK_MACRO__ */ + +/** @} end of interrupt_mask */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_set_interrupt */ +/** + * @defgroup at_ahb_sha2_regs_core_set_interrupt set_interrupt + * @brief Contains register fields associated with set_interrupt. definitions. + * @{ + */ +#ifndef __AT_SHA2_SET_INTERRUPT_MACRO__ +#define __AT_SHA2_SET_INTERRUPT_MACRO__ + +/* macros for field intrpt_set */ +/** + * @defgroup at_ahb_sha2_regs_core_intrpt_set_field intrpt_set_field + * @brief macros for field intrpt_set + * @details if nth bit set, the nth interrupt is set; + * @{ + */ +#define AT_SHA2_SET_INTERRUPT__INTRPT_SET__SHIFT 0 +#define AT_SHA2_SET_INTERRUPT__INTRPT_SET__WIDTH 7 +#define AT_SHA2_SET_INTERRUPT__INTRPT_SET__MASK 0x0000007fU +#define AT_SHA2_SET_INTERRUPT__INTRPT_SET__READ(src) \ + ((uint32_t)(src)\ + & 0x0000007fU) +#define AT_SHA2_SET_INTERRUPT__INTRPT_SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000007fU) +#define AT_SHA2_SET_INTERRUPT__INTRPT_SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define AT_SHA2_SET_INTERRUPT__INTRPT_SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000007fU))) +#define AT_SHA2_SET_INTERRUPT__INTRPT_SET__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_SET_INTERRUPT__TYPE uint32_t +#define AT_SHA2_SET_INTERRUPT__READ 0x0000007fU +#define AT_SHA2_SET_INTERRUPT__WRITE 0x0000007fU +#define AT_SHA2_SET_INTERRUPT__PRESERVED 0x00000000U +#define AT_SHA2_SET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_SET_INTERRUPT_MACRO__ */ + +/** @} end of set_interrupt */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_reset_interrupt */ +/** + * @defgroup at_ahb_sha2_regs_core_reset_interrupt reset_interrupt + * @brief Contains register fields associated with reset_interrupt. definitions. + * @{ + */ +#ifndef __AT_SHA2_RESET_INTERRUPT_MACRO__ +#define __AT_SHA2_RESET_INTERRUPT_MACRO__ + +/* macros for field intrpt_reset */ +/** + * @defgroup at_ahb_sha2_regs_core_intrpt_reset_field intrpt_reset_field + * @brief macros for field intrpt_reset + * @details if nth bit set, the nth interrupt is reset; + * @{ + */ +#define AT_SHA2_RESET_INTERRUPT__INTRPT_RESET__SHIFT 0 +#define AT_SHA2_RESET_INTERRUPT__INTRPT_RESET__WIDTH 7 +#define AT_SHA2_RESET_INTERRUPT__INTRPT_RESET__MASK 0x0000007fU +#define AT_SHA2_RESET_INTERRUPT__INTRPT_RESET__READ(src) \ + ((uint32_t)(src)\ + & 0x0000007fU) +#define AT_SHA2_RESET_INTERRUPT__INTRPT_RESET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000007fU) +#define AT_SHA2_RESET_INTERRUPT__INTRPT_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define AT_SHA2_RESET_INTERRUPT__INTRPT_RESET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000007fU))) +#define AT_SHA2_RESET_INTERRUPT__INTRPT_RESET__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_RESET_INTERRUPT__TYPE uint32_t +#define AT_SHA2_RESET_INTERRUPT__READ 0x0000007fU +#define AT_SHA2_RESET_INTERRUPT__WRITE 0x0000007fU +#define AT_SHA2_RESET_INTERRUPT__PRESERVED 0x00000000U +#define AT_SHA2_RESET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_RESET_INTERRUPT_MACRO__ */ + +/** @} end of reset_interrupt */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_err_code */ +/** + * @defgroup at_ahb_sha2_regs_core_err_code err_code + * @brief Contains register fields associated with err_code. definitions. + * @{ + */ +#ifndef __AT_SHA2_ERR_CODE_MACRO__ +#define __AT_SHA2_ERR_CODE_MACRO__ + +/* macros for field err_code */ +/** + * @defgroup at_ahb_sha2_regs_core_err_code_field err_code_field + * @brief macros for field err_code + * @details NoError = 32'h 0000_0000, SwPushMsgWhenShaDisabled = 32'h 0000_0001, SwHashStartWhenShaDisabled = 32'h 0000_0002, SwUpdateSecretKeyInProcess = 32'h 0000_0003, SwHashStartWhenActive = 32'h 0000_0004, SwPushMsgWhenDisallowed = 32'h 0000_0005 + * @{ + */ +#define AT_SHA2_ERR_CODE__ERR_CODE__SHIFT 0 +#define AT_SHA2_ERR_CODE__ERR_CODE__WIDTH 32 +#define AT_SHA2_ERR_CODE__ERR_CODE__MASK 0xffffffffU +#define AT_SHA2_ERR_CODE__ERR_CODE__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_ERR_CODE__ERR_CODE__RESET_VALUE 0x00000000U +/** @} */ +#define AT_SHA2_ERR_CODE__TYPE uint32_t +#define AT_SHA2_ERR_CODE__READ 0xffffffffU +#define AT_SHA2_ERR_CODE__PRESERVED 0x00000000U +#define AT_SHA2_ERR_CODE__RESET_VALUE 0x00000000U + +#endif /* __AT_SHA2_ERR_CODE_MACRO__ */ + +/** @} end of err_code */ + +/* macros for BlueprintGlobalNameSpace::AT_SHA2_id */ +/** + * @defgroup at_ahb_sha2_regs_core_id id + * @brief Contains register fields associated with id. definitions. + * @{ + */ +#ifndef __AT_SHA2_ID_MACRO__ +#define __AT_SHA2_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_ahb_sha2_regs_core_id_field id_field + * @brief macros for field id + * @details 'SHA2' + * @{ + */ +#define AT_SHA2_ID__ID__SHIFT 0 +#define AT_SHA2_ID__ID__WIDTH 32 +#define AT_SHA2_ID__ID__MASK 0xffffffffU +#define AT_SHA2_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AT_SHA2_ID__ID__RESET_VALUE 0x53484132U +/** @} */ +#define AT_SHA2_ID__TYPE uint32_t +#define AT_SHA2_ID__READ 0xffffffffU +#define AT_SHA2_ID__PRESERVED 0x00000000U +#define AT_SHA2_ID__RESET_VALUE 0x53484132U + +#endif /* __AT_SHA2_ID_MACRO__ */ + +/** @} end of id */ + +/** @} end of AT_AHB_SHA2_REGS_CORE */ +#endif /* __REG_AT_AHB_SHA2_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_apb_aes_regs_core_macro.h b/ATM33xx-5/include/reg/at_apb_aes_regs_core_macro.h new file mode 100644 index 0000000..386bd5d --- /dev/null +++ b/ATM33xx-5/include/reg/at_apb_aes_regs_core_macro.h @@ -0,0 +1,1918 @@ +/* */ +/* File: at_apb_aes_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_apb_aes_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_APB_AES_REGS_CORE_H__ +#define __REG_AT_APB_AES_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_APB_AES_REGS_CORE at_apb_aes_regs_core + * @ingroup AT_REG + * @brief at_apb_aes_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::AES_alert_test */ +/** + * @defgroup at_apb_aes_regs_core_alert_test alert_test + * @brief control signals for all aes subcores definitions. + * @{ + */ +#ifndef __AES_ALERT_TEST_MACRO__ +#define __AES_ALERT_TEST_MACRO__ + +/* macros for field fatal_fault */ +/** + * @defgroup at_apb_aes_regs_core_fatal_fault_field fatal_fault_field + * @brief macros for field fatal_fault + * @details Write 1 to trigger one alert event of this kind + * @{ + */ +#define AES_ALERT_TEST__FATAL_FAULT__SHIFT 0 +#define AES_ALERT_TEST__FATAL_FAULT__WIDTH 1 +#define AES_ALERT_TEST__FATAL_FAULT__MASK 0x00000001U +#define AES_ALERT_TEST__FATAL_FAULT__READ(src) ((uint32_t)(src) & 0x00000001U) +#define AES_ALERT_TEST__FATAL_FAULT__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define AES_ALERT_TEST__FATAL_FAULT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AES_ALERT_TEST__FATAL_FAULT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AES_ALERT_TEST__FATAL_FAULT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AES_ALERT_TEST__FATAL_FAULT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AES_ALERT_TEST__FATAL_FAULT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field recov_ctrl_update_err */ +/** + * @defgroup at_apb_aes_regs_core_recov_ctrl_update_err_field recov_ctrl_update_err_field + * @brief macros for field recov_ctrl_update_err + * @details Write 1 to trigger one alert event of this kind + * @{ + */ +#define AES_ALERT_TEST__RECOV_CTRL_UPDATE_ERR__SHIFT 1 +#define AES_ALERT_TEST__RECOV_CTRL_UPDATE_ERR__WIDTH 1 +#define AES_ALERT_TEST__RECOV_CTRL_UPDATE_ERR__MASK 0x00000002U +#define AES_ALERT_TEST__RECOV_CTRL_UPDATE_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AES_ALERT_TEST__RECOV_CTRL_UPDATE_ERR__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define AES_ALERT_TEST__RECOV_CTRL_UPDATE_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define AES_ALERT_TEST__RECOV_CTRL_UPDATE_ERR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define AES_ALERT_TEST__RECOV_CTRL_UPDATE_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AES_ALERT_TEST__RECOV_CTRL_UPDATE_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AES_ALERT_TEST__RECOV_CTRL_UPDATE_ERR__RESET_VALUE 0x00000000U +/** @} */ +#define AES_ALERT_TEST__TYPE uint32_t +#define AES_ALERT_TEST__READ 0x00000003U +#define AES_ALERT_TEST__WRITE 0x00000003U +#define AES_ALERT_TEST__PRESERVED 0x00000000U +#define AES_ALERT_TEST__RESET_VALUE 0x00000000U + +#endif /* __AES_ALERT_TEST_MACRO__ */ + +/** @} end of alert_test */ + +/* macros for BlueprintGlobalNameSpace::AES_KEY_SHARE0_0 */ +/** + * @defgroup at_apb_aes_regs_core_KEY_SHARE0_0 KEY_SHARE0_0 + * @brief Initial Key Registers Share 0. The actual initial key corresponds to Initial Key Registers Share 0 XORed with Initial Key Registers Share 1. Loaded into the internal Full Key register upon starting encryption/decryption of the next block. All key registers (Share 0 and Share 1) must be written at least once when the key is changed, regardless of key length (write random data for unused bits). The order in which the registers are updated does not matter. Can only be updated when the AES unit is idle. If the AES unit is non-idle, writes to these registers are ignored. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_KEY_SHARE0_0_MACRO__ +#define __AES_KEY_SHARE0_0_MACRO__ + +/* macros for field key_share0_0 */ +/** + * @defgroup at_apb_aes_regs_core_key_share0_0_field key_share0_0_field + * @brief macros for field key_share0_0 + * @details initial Key Share 0 + * @{ + */ +#define AES_KEY_SHARE0_0__KEY_SHARE0_0__SHIFT 0 +#define AES_KEY_SHARE0_0__KEY_SHARE0_0__WIDTH 32 +#define AES_KEY_SHARE0_0__KEY_SHARE0_0__MASK 0xffffffffU +#define AES_KEY_SHARE0_0__KEY_SHARE0_0__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE0_0__KEY_SHARE0_0__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE0_0__KEY_SHARE0_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_KEY_SHARE0_0__KEY_SHARE0_0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AES_KEY_SHARE0_0__KEY_SHARE0_0__RESET_VALUE 0x00000000U +/** @} */ +#define AES_KEY_SHARE0_0__TYPE uint32_t +#define AES_KEY_SHARE0_0__READ 0xffffffffU +#define AES_KEY_SHARE0_0__WRITE 0xffffffffU +#define AES_KEY_SHARE0_0__PRESERVED 0x00000000U +#define AES_KEY_SHARE0_0__RESET_VALUE 0x00000000U + +#endif /* __AES_KEY_SHARE0_0_MACRO__ */ + +/** @} end of KEY_SHARE0_0 */ + +/* macros for BlueprintGlobalNameSpace::AES_KEY_SHARE0_1 */ +/** + * @defgroup at_apb_aes_regs_core_KEY_SHARE0_1 KEY_SHARE0_1 + * @brief Initial Key Registers Share 0. The actual initial key corresponds to Initial Key Registers Share 0 XORed with Initial Key Registers Share 1. Loaded into the internal Full Key register upon starting encryption/decryption of the next block. All key registers (Share 0 and Share 1) must be written at least once when the key is changed, regardless of key length (write random data for unused bits). The order in which the registers are updated does not matter. Can only be updated when the AES unit is idle. If the AES unit is non-idle, writes to these registers are ignored. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_KEY_SHARE0_1_MACRO__ +#define __AES_KEY_SHARE0_1_MACRO__ + +/* macros for field key_share0_1 */ +/** + * @defgroup at_apb_aes_regs_core_key_share0_1_field key_share0_1_field + * @brief macros for field key_share0_1 + * @details For KEY_SHARE01 + * @{ + */ +#define AES_KEY_SHARE0_1__KEY_SHARE0_1__SHIFT 0 +#define AES_KEY_SHARE0_1__KEY_SHARE0_1__WIDTH 32 +#define AES_KEY_SHARE0_1__KEY_SHARE0_1__MASK 0xffffffffU +#define AES_KEY_SHARE0_1__KEY_SHARE0_1__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE0_1__KEY_SHARE0_1__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE0_1__KEY_SHARE0_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_KEY_SHARE0_1__KEY_SHARE0_1__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AES_KEY_SHARE0_1__KEY_SHARE0_1__RESET_VALUE 0x00000000U +/** @} */ +#define AES_KEY_SHARE0_1__TYPE uint32_t +#define AES_KEY_SHARE0_1__READ 0xffffffffU +#define AES_KEY_SHARE0_1__WRITE 0xffffffffU +#define AES_KEY_SHARE0_1__PRESERVED 0x00000000U +#define AES_KEY_SHARE0_1__RESET_VALUE 0x00000000U + +#endif /* __AES_KEY_SHARE0_1_MACRO__ */ + +/** @} end of KEY_SHARE0_1 */ + +/* macros for BlueprintGlobalNameSpace::AES_KEY_SHARE0_2 */ +/** + * @defgroup at_apb_aes_regs_core_KEY_SHARE0_2 KEY_SHARE0_2 + * @brief Initial Key Registers Share 0. The actual initial key corresponds to Initial Key Registers Share 0 XORed with Initial Key Registers Share 1. Loaded into the internal Full Key register upon starting encryption/decryption of the next block. All key registers (Share 0 and Share 1) must be written at least once when the key is changed, regardless of key length (write random data for unused bits). The order in which the registers are updated does not matter. Can only be updated when the AES unit is idle. If the AES unit is non-idle, writes to these registers are ignored. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_KEY_SHARE0_2_MACRO__ +#define __AES_KEY_SHARE0_2_MACRO__ + +/* macros for field key_share0_2 */ +/** + * @defgroup at_apb_aes_regs_core_key_share0_2_field key_share0_2_field + * @brief macros for field key_share0_2 + * @details For KEY_SHARE02 + * @{ + */ +#define AES_KEY_SHARE0_2__KEY_SHARE0_2__SHIFT 0 +#define AES_KEY_SHARE0_2__KEY_SHARE0_2__WIDTH 32 +#define AES_KEY_SHARE0_2__KEY_SHARE0_2__MASK 0xffffffffU +#define AES_KEY_SHARE0_2__KEY_SHARE0_2__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE0_2__KEY_SHARE0_2__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE0_2__KEY_SHARE0_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_KEY_SHARE0_2__KEY_SHARE0_2__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AES_KEY_SHARE0_2__KEY_SHARE0_2__RESET_VALUE 0x00000000U +/** @} */ +#define AES_KEY_SHARE0_2__TYPE uint32_t +#define AES_KEY_SHARE0_2__READ 0xffffffffU +#define AES_KEY_SHARE0_2__WRITE 0xffffffffU +#define AES_KEY_SHARE0_2__PRESERVED 0x00000000U +#define AES_KEY_SHARE0_2__RESET_VALUE 0x00000000U + +#endif /* __AES_KEY_SHARE0_2_MACRO__ */ + +/** @} end of KEY_SHARE0_2 */ + +/* macros for BlueprintGlobalNameSpace::AES_KEY_SHARE0_3 */ +/** + * @defgroup at_apb_aes_regs_core_KEY_SHARE0_3 KEY_SHARE0_3 + * @brief Initial Key Registers Share 0. The actual initial key corresponds to Initial Key Registers Share 0 XORed with Initial Key Registers Share 1. Loaded into the internal Full Key register upon starting encryption/decryption of the next block. All key registers (Share 0 and Share 1) must be written at least once when the key is changed, regardless of key length (write random data for unused bits). The order in which the registers are updated does not matter. Can only be updated when the AES unit is idle. If the AES unit is non-idle, writes to these registers are ignored. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_KEY_SHARE0_3_MACRO__ +#define __AES_KEY_SHARE0_3_MACRO__ + +/* macros for field key_share0_3 */ +/** + * @defgroup at_apb_aes_regs_core_key_share0_3_field key_share0_3_field + * @brief macros for field key_share0_3 + * @details For KEY_SHARE03 + * @{ + */ +#define AES_KEY_SHARE0_3__KEY_SHARE0_3__SHIFT 0 +#define AES_KEY_SHARE0_3__KEY_SHARE0_3__WIDTH 32 +#define AES_KEY_SHARE0_3__KEY_SHARE0_3__MASK 0xffffffffU +#define AES_KEY_SHARE0_3__KEY_SHARE0_3__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE0_3__KEY_SHARE0_3__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE0_3__KEY_SHARE0_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_KEY_SHARE0_3__KEY_SHARE0_3__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AES_KEY_SHARE0_3__KEY_SHARE0_3__RESET_VALUE 0x00000000U +/** @} */ +#define AES_KEY_SHARE0_3__TYPE uint32_t +#define AES_KEY_SHARE0_3__READ 0xffffffffU +#define AES_KEY_SHARE0_3__WRITE 0xffffffffU +#define AES_KEY_SHARE0_3__PRESERVED 0x00000000U +#define AES_KEY_SHARE0_3__RESET_VALUE 0x00000000U + +#endif /* __AES_KEY_SHARE0_3_MACRO__ */ + +/** @} end of KEY_SHARE0_3 */ + +/* macros for BlueprintGlobalNameSpace::AES_KEY_SHARE0_4 */ +/** + * @defgroup at_apb_aes_regs_core_KEY_SHARE0_4 KEY_SHARE0_4 + * @brief Initial Key Registers Share 0. The actual initial key corresponds to Initial Key Registers Share 0 XORed with Initial Key Registers Share 1. Loaded into the internal Full Key register upon starting encryption/decryption of the next block. All key registers (Share 0 and Share 1) must be written at least once when the key is changed, regardless of key length (write random data for unused bits). The order in which the registers are updated does not matter. Can only be updated when the AES unit is idle. If the AES unit is non-idle, writes to these registers are ignored. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_KEY_SHARE0_4_MACRO__ +#define __AES_KEY_SHARE0_4_MACRO__ + +/* macros for field key_share0_4 */ +/** + * @defgroup at_apb_aes_regs_core_key_share0_4_field key_share0_4_field + * @brief macros for field key_share0_4 + * @details For KEY_SHARE04 + * @{ + */ +#define AES_KEY_SHARE0_4__KEY_SHARE0_4__SHIFT 0 +#define AES_KEY_SHARE0_4__KEY_SHARE0_4__WIDTH 32 +#define AES_KEY_SHARE0_4__KEY_SHARE0_4__MASK 0xffffffffU +#define AES_KEY_SHARE0_4__KEY_SHARE0_4__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE0_4__KEY_SHARE0_4__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE0_4__KEY_SHARE0_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_KEY_SHARE0_4__KEY_SHARE0_4__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AES_KEY_SHARE0_4__KEY_SHARE0_4__RESET_VALUE 0x00000000U +/** @} */ +#define AES_KEY_SHARE0_4__TYPE uint32_t +#define AES_KEY_SHARE0_4__READ 0xffffffffU +#define AES_KEY_SHARE0_4__WRITE 0xffffffffU +#define AES_KEY_SHARE0_4__PRESERVED 0x00000000U +#define AES_KEY_SHARE0_4__RESET_VALUE 0x00000000U + +#endif /* __AES_KEY_SHARE0_4_MACRO__ */ + +/** @} end of KEY_SHARE0_4 */ + +/* macros for BlueprintGlobalNameSpace::AES_KEY_SHARE0_5 */ +/** + * @defgroup at_apb_aes_regs_core_KEY_SHARE0_5 KEY_SHARE0_5 + * @brief Initial Key Registers Share 0. The actual initial key corresponds to Initial Key Registers Share 0 XORed with Initial Key Registers Share 1. Loaded into the internal Full Key register upon starting encryption/decryption of the next block. All key registers (Share 0 and Share 1) must be written at least once when the key is changed, regardless of key length (write random data for unused bits). The order in which the registers are updated does not matter. Can only be updated when the AES unit is idle. If the AES unit is non-idle, writes to these registers are ignored. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_KEY_SHARE0_5_MACRO__ +#define __AES_KEY_SHARE0_5_MACRO__ + +/* macros for field key_share0_5 */ +/** + * @defgroup at_apb_aes_regs_core_key_share0_5_field key_share0_5_field + * @brief macros for field key_share0_5 + * @details For KEY_SHARE05 + * @{ + */ +#define AES_KEY_SHARE0_5__KEY_SHARE0_5__SHIFT 0 +#define AES_KEY_SHARE0_5__KEY_SHARE0_5__WIDTH 32 +#define AES_KEY_SHARE0_5__KEY_SHARE0_5__MASK 0xffffffffU +#define AES_KEY_SHARE0_5__KEY_SHARE0_5__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE0_5__KEY_SHARE0_5__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE0_5__KEY_SHARE0_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_KEY_SHARE0_5__KEY_SHARE0_5__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AES_KEY_SHARE0_5__KEY_SHARE0_5__RESET_VALUE 0x00000000U +/** @} */ +#define AES_KEY_SHARE0_5__TYPE uint32_t +#define AES_KEY_SHARE0_5__READ 0xffffffffU +#define AES_KEY_SHARE0_5__WRITE 0xffffffffU +#define AES_KEY_SHARE0_5__PRESERVED 0x00000000U +#define AES_KEY_SHARE0_5__RESET_VALUE 0x00000000U + +#endif /* __AES_KEY_SHARE0_5_MACRO__ */ + +/** @} end of KEY_SHARE0_5 */ + +/* macros for BlueprintGlobalNameSpace::AES_KEY_SHARE0_6 */ +/** + * @defgroup at_apb_aes_regs_core_KEY_SHARE0_6 KEY_SHARE0_6 + * @brief Initial Key Registers Share 0. The actual initial key corresponds to Initial Key Registers Share 0 XORed with Initial Key Registers Share 1. Loaded into the internal Full Key register upon starting encryption/decryption of the next block. All key registers (Share 0 and Share 1) must be written at least once when the key is changed, regardless of key length (write random data for unused bits). The order in which the registers are updated does not matter. Can only be updated when the AES unit is idle. If the AES unit is non-idle, writes to these registers are ignored. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_KEY_SHARE0_6_MACRO__ +#define __AES_KEY_SHARE0_6_MACRO__ + +/* macros for field key_share0_6 */ +/** + * @defgroup at_apb_aes_regs_core_key_share0_6_field key_share0_6_field + * @brief macros for field key_share0_6 + * @details For KEY_SHARE06 + * @{ + */ +#define AES_KEY_SHARE0_6__KEY_SHARE0_6__SHIFT 0 +#define AES_KEY_SHARE0_6__KEY_SHARE0_6__WIDTH 32 +#define AES_KEY_SHARE0_6__KEY_SHARE0_6__MASK 0xffffffffU +#define AES_KEY_SHARE0_6__KEY_SHARE0_6__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE0_6__KEY_SHARE0_6__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE0_6__KEY_SHARE0_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_KEY_SHARE0_6__KEY_SHARE0_6__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AES_KEY_SHARE0_6__KEY_SHARE0_6__RESET_VALUE 0x00000000U +/** @} */ +#define AES_KEY_SHARE0_6__TYPE uint32_t +#define AES_KEY_SHARE0_6__READ 0xffffffffU +#define AES_KEY_SHARE0_6__WRITE 0xffffffffU +#define AES_KEY_SHARE0_6__PRESERVED 0x00000000U +#define AES_KEY_SHARE0_6__RESET_VALUE 0x00000000U + +#endif /* __AES_KEY_SHARE0_6_MACRO__ */ + +/** @} end of KEY_SHARE0_6 */ + +/* macros for BlueprintGlobalNameSpace::AES_KEY_SHARE0_7 */ +/** + * @defgroup at_apb_aes_regs_core_KEY_SHARE0_7 KEY_SHARE0_7 + * @brief Initial Key Registers Share 0. The actual initial key corresponds to Initial Key Registers Share 0 XORed with Initial Key Registers Share 1. Loaded into the internal Full Key register upon starting encryption/decryption of the next block. All key registers (Share 0 and Share 1) must be written at least once when the key is changed, regardless of key length (write random data for unused bits). The order in which the registers are updated does not matter. Can only be updated when the AES unit is idle. If the AES unit is non-idle, writes to these registers are ignored. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_KEY_SHARE0_7_MACRO__ +#define __AES_KEY_SHARE0_7_MACRO__ + +/* macros for field key_share0_7 */ +/** + * @defgroup at_apb_aes_regs_core_key_share0_7_field key_share0_7_field + * @brief macros for field key_share0_7 + * @details For KEY_SHARE07 + * @{ + */ +#define AES_KEY_SHARE0_7__KEY_SHARE0_7__SHIFT 0 +#define AES_KEY_SHARE0_7__KEY_SHARE0_7__WIDTH 32 +#define AES_KEY_SHARE0_7__KEY_SHARE0_7__MASK 0xffffffffU +#define AES_KEY_SHARE0_7__KEY_SHARE0_7__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE0_7__KEY_SHARE0_7__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE0_7__KEY_SHARE0_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_KEY_SHARE0_7__KEY_SHARE0_7__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AES_KEY_SHARE0_7__KEY_SHARE0_7__RESET_VALUE 0x00000000U +/** @} */ +#define AES_KEY_SHARE0_7__TYPE uint32_t +#define AES_KEY_SHARE0_7__READ 0xffffffffU +#define AES_KEY_SHARE0_7__WRITE 0xffffffffU +#define AES_KEY_SHARE0_7__PRESERVED 0x00000000U +#define AES_KEY_SHARE0_7__RESET_VALUE 0x00000000U + +#endif /* __AES_KEY_SHARE0_7_MACRO__ */ + +/** @} end of KEY_SHARE0_7 */ + +/* macros for BlueprintGlobalNameSpace::AES_KEY_SHARE1_0 */ +/** + * @defgroup at_apb_aes_regs_core_KEY_SHARE1_0 KEY_SHARE1_0 + * @brief Initial Key Registers Share 1. The actual initial key corresponds to Initial Key Registers Share 1 XORed with Initial Key Registers Share 0. Loaded into the internal Full Key register upon starting encryption/decryption of the next block. All key registers (Share 0 and Share 1) must be written at least once when the key is changed, regardless of key length (write random data for unused bits). The order in which the registers are updated does not matter. Can only be updated when the AES unit is idle. If the AES unit is non-idle, writes to these registers are ignored. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_KEY_SHARE1_0_MACRO__ +#define __AES_KEY_SHARE1_0_MACRO__ + +/* macros for field key_share1_0 */ +/** + * @defgroup at_apb_aes_regs_core_key_share1_0_field key_share1_0_field + * @brief macros for field key_share1_0 + * @details initial Key Share 1 + * @{ + */ +#define AES_KEY_SHARE1_0__KEY_SHARE1_0__SHIFT 0 +#define AES_KEY_SHARE1_0__KEY_SHARE1_0__WIDTH 32 +#define AES_KEY_SHARE1_0__KEY_SHARE1_0__MASK 0xffffffffU +#define AES_KEY_SHARE1_0__KEY_SHARE1_0__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE1_0__KEY_SHARE1_0__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE1_0__KEY_SHARE1_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_KEY_SHARE1_0__KEY_SHARE1_0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AES_KEY_SHARE1_0__KEY_SHARE1_0__RESET_VALUE 0x00000000U +/** @} */ +#define AES_KEY_SHARE1_0__TYPE uint32_t +#define AES_KEY_SHARE1_0__READ 0xffffffffU +#define AES_KEY_SHARE1_0__WRITE 0xffffffffU +#define AES_KEY_SHARE1_0__PRESERVED 0x00000000U +#define AES_KEY_SHARE1_0__RESET_VALUE 0x00000000U + +#endif /* __AES_KEY_SHARE1_0_MACRO__ */ + +/** @} end of KEY_SHARE1_0 */ + +/* macros for BlueprintGlobalNameSpace::AES_KEY_SHARE1_1 */ +/** + * @defgroup at_apb_aes_regs_core_KEY_SHARE1_1 KEY_SHARE1_1 + * @brief Initial Key Registers Share 1. The actual initial key corresponds to Initial Key Registers Share 1 XORed with Initial Key Registers Share 0. Loaded into the internal Full Key register upon starting encryption/decryption of the next block. All key registers (Share 0 and Share 1) must be written at least once when the key is changed, regardless of key length (write random data for unused bits). The order in which the registers are updated does not matter. Can only be updated when the AES unit is idle. If the AES unit is non-idle, writes to these registers are ignored. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_KEY_SHARE1_1_MACRO__ +#define __AES_KEY_SHARE1_1_MACRO__ + +/* macros for field key_share1_1 */ +/** + * @defgroup at_apb_aes_regs_core_key_share1_1_field key_share1_1_field + * @brief macros for field key_share1_1 + * @details For KEY_SHARE11 + * @{ + */ +#define AES_KEY_SHARE1_1__KEY_SHARE1_1__SHIFT 0 +#define AES_KEY_SHARE1_1__KEY_SHARE1_1__WIDTH 32 +#define AES_KEY_SHARE1_1__KEY_SHARE1_1__MASK 0xffffffffU +#define AES_KEY_SHARE1_1__KEY_SHARE1_1__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE1_1__KEY_SHARE1_1__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE1_1__KEY_SHARE1_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_KEY_SHARE1_1__KEY_SHARE1_1__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AES_KEY_SHARE1_1__KEY_SHARE1_1__RESET_VALUE 0x00000000U +/** @} */ +#define AES_KEY_SHARE1_1__TYPE uint32_t +#define AES_KEY_SHARE1_1__READ 0xffffffffU +#define AES_KEY_SHARE1_1__WRITE 0xffffffffU +#define AES_KEY_SHARE1_1__PRESERVED 0x00000000U +#define AES_KEY_SHARE1_1__RESET_VALUE 0x00000000U + +#endif /* __AES_KEY_SHARE1_1_MACRO__ */ + +/** @} end of KEY_SHARE1_1 */ + +/* macros for BlueprintGlobalNameSpace::AES_KEY_SHARE1_2 */ +/** + * @defgroup at_apb_aes_regs_core_KEY_SHARE1_2 KEY_SHARE1_2 + * @brief Initial Key Registers Share 1. The actual initial key corresponds to Initial Key Registers Share 1 XORed with Initial Key Registers Share 0. Loaded into the internal Full Key register upon starting encryption/decryption of the next block. All key registers (Share 0 and Share 1) must be written at least once when the key is changed, regardless of key length (write random data for unused bits). The order in which the registers are updated does not matter. Can only be updated when the AES unit is idle. If the AES unit is non-idle, writes to these registers are ignored. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_KEY_SHARE1_2_MACRO__ +#define __AES_KEY_SHARE1_2_MACRO__ + +/* macros for field key_share1_2 */ +/** + * @defgroup at_apb_aes_regs_core_key_share1_2_field key_share1_2_field + * @brief macros for field key_share1_2 + * @details For KEY_SHARE12 + * @{ + */ +#define AES_KEY_SHARE1_2__KEY_SHARE1_2__SHIFT 0 +#define AES_KEY_SHARE1_2__KEY_SHARE1_2__WIDTH 32 +#define AES_KEY_SHARE1_2__KEY_SHARE1_2__MASK 0xffffffffU +#define AES_KEY_SHARE1_2__KEY_SHARE1_2__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE1_2__KEY_SHARE1_2__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE1_2__KEY_SHARE1_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_KEY_SHARE1_2__KEY_SHARE1_2__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AES_KEY_SHARE1_2__KEY_SHARE1_2__RESET_VALUE 0x00000000U +/** @} */ +#define AES_KEY_SHARE1_2__TYPE uint32_t +#define AES_KEY_SHARE1_2__READ 0xffffffffU +#define AES_KEY_SHARE1_2__WRITE 0xffffffffU +#define AES_KEY_SHARE1_2__PRESERVED 0x00000000U +#define AES_KEY_SHARE1_2__RESET_VALUE 0x00000000U + +#endif /* __AES_KEY_SHARE1_2_MACRO__ */ + +/** @} end of KEY_SHARE1_2 */ + +/* macros for BlueprintGlobalNameSpace::AES_KEY_SHARE1_3 */ +/** + * @defgroup at_apb_aes_regs_core_KEY_SHARE1_3 KEY_SHARE1_3 + * @brief Initial Key Registers Share 1. The actual initial key corresponds to Initial Key Registers Share 1 XORed with Initial Key Registers Share 0. Loaded into the internal Full Key register upon starting encryption/decryption of the next block. All key registers (Share 0 and Share 1) must be written at least once when the key is changed, regardless of key length (write random data for unused bits). The order in which the registers are updated does not matter. Can only be updated when the AES unit is idle. If the AES unit is non-idle, writes to these registers are ignored. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_KEY_SHARE1_3_MACRO__ +#define __AES_KEY_SHARE1_3_MACRO__ + +/* macros for field key_share1_3 */ +/** + * @defgroup at_apb_aes_regs_core_key_share1_3_field key_share1_3_field + * @brief macros for field key_share1_3 + * @details For KEY_SHARE13 + * @{ + */ +#define AES_KEY_SHARE1_3__KEY_SHARE1_3__SHIFT 0 +#define AES_KEY_SHARE1_3__KEY_SHARE1_3__WIDTH 32 +#define AES_KEY_SHARE1_3__KEY_SHARE1_3__MASK 0xffffffffU +#define AES_KEY_SHARE1_3__KEY_SHARE1_3__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE1_3__KEY_SHARE1_3__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE1_3__KEY_SHARE1_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_KEY_SHARE1_3__KEY_SHARE1_3__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AES_KEY_SHARE1_3__KEY_SHARE1_3__RESET_VALUE 0x00000000U +/** @} */ +#define AES_KEY_SHARE1_3__TYPE uint32_t +#define AES_KEY_SHARE1_3__READ 0xffffffffU +#define AES_KEY_SHARE1_3__WRITE 0xffffffffU +#define AES_KEY_SHARE1_3__PRESERVED 0x00000000U +#define AES_KEY_SHARE1_3__RESET_VALUE 0x00000000U + +#endif /* __AES_KEY_SHARE1_3_MACRO__ */ + +/** @} end of KEY_SHARE1_3 */ + +/* macros for BlueprintGlobalNameSpace::AES_KEY_SHARE1_4 */ +/** + * @defgroup at_apb_aes_regs_core_KEY_SHARE1_4 KEY_SHARE1_4 + * @brief Initial Key Registers Share 1. The actual initial key corresponds to Initial Key Registers Share 1 XORed with Initial Key Registers Share 0. Loaded into the internal Full Key register upon starting encryption/decryption of the next block. All key registers (Share 0 and Share 1) must be written at least once when the key is changed, regardless of key length (write random data for unused bits). The order in which the registers are updated does not matter. Can only be updated when the AES unit is idle. If the AES unit is non-idle, writes to these registers are ignored. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_KEY_SHARE1_4_MACRO__ +#define __AES_KEY_SHARE1_4_MACRO__ + +/* macros for field key_share1_4 */ +/** + * @defgroup at_apb_aes_regs_core_key_share1_4_field key_share1_4_field + * @brief macros for field key_share1_4 + * @details For KEY_SHARE14 + * @{ + */ +#define AES_KEY_SHARE1_4__KEY_SHARE1_4__SHIFT 0 +#define AES_KEY_SHARE1_4__KEY_SHARE1_4__WIDTH 32 +#define AES_KEY_SHARE1_4__KEY_SHARE1_4__MASK 0xffffffffU +#define AES_KEY_SHARE1_4__KEY_SHARE1_4__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE1_4__KEY_SHARE1_4__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE1_4__KEY_SHARE1_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_KEY_SHARE1_4__KEY_SHARE1_4__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AES_KEY_SHARE1_4__KEY_SHARE1_4__RESET_VALUE 0x00000000U +/** @} */ +#define AES_KEY_SHARE1_4__TYPE uint32_t +#define AES_KEY_SHARE1_4__READ 0xffffffffU +#define AES_KEY_SHARE1_4__WRITE 0xffffffffU +#define AES_KEY_SHARE1_4__PRESERVED 0x00000000U +#define AES_KEY_SHARE1_4__RESET_VALUE 0x00000000U + +#endif /* __AES_KEY_SHARE1_4_MACRO__ */ + +/** @} end of KEY_SHARE1_4 */ + +/* macros for BlueprintGlobalNameSpace::AES_KEY_SHARE1_5 */ +/** + * @defgroup at_apb_aes_regs_core_KEY_SHARE1_5 KEY_SHARE1_5 + * @brief Initial Key Registers Share 1. The actual initial key corresponds to Initial Key Registers Share 1 XORed with Initial Key Registers Share 0. Loaded into the internal Full Key register upon starting encryption/decryption of the next block. All key registers (Share 0 and Share 1) must be written at least once when the key is changed, regardless of key length (write random data for unused bits). The order in which the registers are updated does not matter. Can only be updated when the AES unit is idle. If the AES unit is non-idle, writes to these registers are ignored. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_KEY_SHARE1_5_MACRO__ +#define __AES_KEY_SHARE1_5_MACRO__ + +/* macros for field key_share1_5 */ +/** + * @defgroup at_apb_aes_regs_core_key_share1_5_field key_share1_5_field + * @brief macros for field key_share1_5 + * @details For KEY_SHARE15 + * @{ + */ +#define AES_KEY_SHARE1_5__KEY_SHARE1_5__SHIFT 0 +#define AES_KEY_SHARE1_5__KEY_SHARE1_5__WIDTH 32 +#define AES_KEY_SHARE1_5__KEY_SHARE1_5__MASK 0xffffffffU +#define AES_KEY_SHARE1_5__KEY_SHARE1_5__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE1_5__KEY_SHARE1_5__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE1_5__KEY_SHARE1_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_KEY_SHARE1_5__KEY_SHARE1_5__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AES_KEY_SHARE1_5__KEY_SHARE1_5__RESET_VALUE 0x00000000U +/** @} */ +#define AES_KEY_SHARE1_5__TYPE uint32_t +#define AES_KEY_SHARE1_5__READ 0xffffffffU +#define AES_KEY_SHARE1_5__WRITE 0xffffffffU +#define AES_KEY_SHARE1_5__PRESERVED 0x00000000U +#define AES_KEY_SHARE1_5__RESET_VALUE 0x00000000U + +#endif /* __AES_KEY_SHARE1_5_MACRO__ */ + +/** @} end of KEY_SHARE1_5 */ + +/* macros for BlueprintGlobalNameSpace::AES_KEY_SHARE1_6 */ +/** + * @defgroup at_apb_aes_regs_core_KEY_SHARE1_6 KEY_SHARE1_6 + * @brief Initial Key Registers Share 1. The actual initial key corresponds to Initial Key Registers Share 1 XORed with Initial Key Registers Share 0. Loaded into the internal Full Key register upon starting encryption/decryption of the next block. All key registers (Share 0 and Share 1) must be written at least once when the key is changed, regardless of key length (write random data for unused bits). The order in which the registers are updated does not matter. Can only be updated when the AES unit is idle. If the AES unit is non-idle, writes to these registers are ignored. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_KEY_SHARE1_6_MACRO__ +#define __AES_KEY_SHARE1_6_MACRO__ + +/* macros for field key_share1_6 */ +/** + * @defgroup at_apb_aes_regs_core_key_share1_6_field key_share1_6_field + * @brief macros for field key_share1_6 + * @details For KEY_SHARE16 + * @{ + */ +#define AES_KEY_SHARE1_6__KEY_SHARE1_6__SHIFT 0 +#define AES_KEY_SHARE1_6__KEY_SHARE1_6__WIDTH 32 +#define AES_KEY_SHARE1_6__KEY_SHARE1_6__MASK 0xffffffffU +#define AES_KEY_SHARE1_6__KEY_SHARE1_6__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE1_6__KEY_SHARE1_6__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE1_6__KEY_SHARE1_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_KEY_SHARE1_6__KEY_SHARE1_6__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AES_KEY_SHARE1_6__KEY_SHARE1_6__RESET_VALUE 0x00000000U +/** @} */ +#define AES_KEY_SHARE1_6__TYPE uint32_t +#define AES_KEY_SHARE1_6__READ 0xffffffffU +#define AES_KEY_SHARE1_6__WRITE 0xffffffffU +#define AES_KEY_SHARE1_6__PRESERVED 0x00000000U +#define AES_KEY_SHARE1_6__RESET_VALUE 0x00000000U + +#endif /* __AES_KEY_SHARE1_6_MACRO__ */ + +/** @} end of KEY_SHARE1_6 */ + +/* macros for BlueprintGlobalNameSpace::AES_KEY_SHARE1_7 */ +/** + * @defgroup at_apb_aes_regs_core_KEY_SHARE1_7 KEY_SHARE1_7 + * @brief Initial Key Registers Share 1. The actual initial key corresponds to Initial Key Registers Share 1 XORed with Initial Key Registers Share 0. Loaded into the internal Full Key register upon starting encryption/decryption of the next block. All key registers (Share 0 and Share 1) must be written at least once when the key is changed, regardless of key length (write random data for unused bits). The order in which the registers are updated does not matter. Can only be updated when the AES unit is idle. If the AES unit is non-idle, writes to these registers are ignored. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_KEY_SHARE1_7_MACRO__ +#define __AES_KEY_SHARE1_7_MACRO__ + +/* macros for field key_share1_7 */ +/** + * @defgroup at_apb_aes_regs_core_key_share1_7_field key_share1_7_field + * @brief macros for field key_share1_7 + * @details For KEY_SHARE17 + * @{ + */ +#define AES_KEY_SHARE1_7__KEY_SHARE1_7__SHIFT 0 +#define AES_KEY_SHARE1_7__KEY_SHARE1_7__WIDTH 32 +#define AES_KEY_SHARE1_7__KEY_SHARE1_7__MASK 0xffffffffU +#define AES_KEY_SHARE1_7__KEY_SHARE1_7__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE1_7__KEY_SHARE1_7__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define AES_KEY_SHARE1_7__KEY_SHARE1_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_KEY_SHARE1_7__KEY_SHARE1_7__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AES_KEY_SHARE1_7__KEY_SHARE1_7__RESET_VALUE 0x00000000U +/** @} */ +#define AES_KEY_SHARE1_7__TYPE uint32_t +#define AES_KEY_SHARE1_7__READ 0xffffffffU +#define AES_KEY_SHARE1_7__WRITE 0xffffffffU +#define AES_KEY_SHARE1_7__PRESERVED 0x00000000U +#define AES_KEY_SHARE1_7__RESET_VALUE 0x00000000U + +#endif /* __AES_KEY_SHARE1_7_MACRO__ */ + +/** @} end of KEY_SHARE1_7 */ + +/* macros for BlueprintGlobalNameSpace::AES_IV_0 */ +/** + * @defgroup at_apb_aes_regs_core_IV_0 IV_0 + * @brief Initialization Vector Registers. The initialization vector (IV) or initial counter value must be written to these registers when starting a new message in CBC or CTR mode (see Control Register), respectively. In CBC and CTR modes, the AES unit does not start encryption/decryption with a partially updated IV. Each register has to be written at least once. The order in which the registers are written does not matter. If the AES unit is non-idle, writes to these registers are ignored. Whenever starting a new message, the corresponding IV value must be provided by the processor. Once started, the AES unit automatically updates the contents of these registers. In ECB mode, the IV registers are not used and do not need to be configured. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_IV_0_MACRO__ +#define __AES_IV_0_MACRO__ + +/* macros for field iv_0 */ +/** + * @defgroup at_apb_aes_regs_core_iv_0_field iv_0_field + * @brief macros for field iv_0 + * @details Initialization Vector + * @{ + */ +#define AES_IV_0__IV_0__SHIFT 0 +#define AES_IV_0__IV_0__WIDTH 32 +#define AES_IV_0__IV_0__MASK 0xffffffffU +#define AES_IV_0__IV_0__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_IV_0__IV_0__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_IV_0__IV_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_IV_0__IV_0__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define AES_IV_0__IV_0__RESET_VALUE 0x00000000U +/** @} */ +#define AES_IV_0__TYPE uint32_t +#define AES_IV_0__READ 0xffffffffU +#define AES_IV_0__WRITE 0xffffffffU +#define AES_IV_0__PRESERVED 0x00000000U +#define AES_IV_0__RESET_VALUE 0x00000000U + +#endif /* __AES_IV_0_MACRO__ */ + +/** @} end of IV_0 */ + +/* macros for BlueprintGlobalNameSpace::AES_IV_1 */ +/** + * @defgroup at_apb_aes_regs_core_IV_1 IV_1 + * @brief Initialization Vector Registers. The initialization vector (IV) or initial counter value must be written to these registers when starting a new message in CBC or CTR mode (see Control Register), respectively. In CBC and CTR modes, the AES unit does not start encryption/decryption with a partially updated IV. Each register has to be written at least once. The order in which the registers are written does not matter. If the AES unit is non-idle, writes to these registers are ignored. Whenever starting a new message, the corresponding IV value must be provided by the processor. Once started, the AES unit automatically updates the contents of these registers. In ECB mode, the IV registers are not used and do not need to be configured. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_IV_1_MACRO__ +#define __AES_IV_1_MACRO__ + +/* macros for field iv_1 */ +/** + * @defgroup at_apb_aes_regs_core_iv_1_field iv_1_field + * @brief macros for field iv_1 + * @details For IV1 + * @{ + */ +#define AES_IV_1__IV_1__SHIFT 0 +#define AES_IV_1__IV_1__WIDTH 32 +#define AES_IV_1__IV_1__MASK 0xffffffffU +#define AES_IV_1__IV_1__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_IV_1__IV_1__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_IV_1__IV_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_IV_1__IV_1__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define AES_IV_1__IV_1__RESET_VALUE 0x00000000U +/** @} */ +#define AES_IV_1__TYPE uint32_t +#define AES_IV_1__READ 0xffffffffU +#define AES_IV_1__WRITE 0xffffffffU +#define AES_IV_1__PRESERVED 0x00000000U +#define AES_IV_1__RESET_VALUE 0x00000000U + +#endif /* __AES_IV_1_MACRO__ */ + +/** @} end of IV_1 */ + +/* macros for BlueprintGlobalNameSpace::AES_IV_2 */ +/** + * @defgroup at_apb_aes_regs_core_IV_2 IV_2 + * @brief Initialization Vector Registers. The initialization vector (IV) or initial counter value must be written to these registers when starting a new message in CBC or CTR mode (see Control Register), respectively. In CBC and CTR modes, the AES unit does not start encryption/decryption with a partially updated IV. Each register has to be written at least once. The order in which the registers are written does not matter. If the AES unit is non-idle, writes to these registers are ignored. Whenever starting a new message, the corresponding IV value must be provided by the processor. Once started, the AES unit automatically updates the contents of these registers. In ECB mode, the IV registers are not used and do not need to be configured. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_IV_2_MACRO__ +#define __AES_IV_2_MACRO__ + +/* macros for field iv_2 */ +/** + * @defgroup at_apb_aes_regs_core_iv_2_field iv_2_field + * @brief macros for field iv_2 + * @details For IV2 + * @{ + */ +#define AES_IV_2__IV_2__SHIFT 0 +#define AES_IV_2__IV_2__WIDTH 32 +#define AES_IV_2__IV_2__MASK 0xffffffffU +#define AES_IV_2__IV_2__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_IV_2__IV_2__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_IV_2__IV_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_IV_2__IV_2__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define AES_IV_2__IV_2__RESET_VALUE 0x00000000U +/** @} */ +#define AES_IV_2__TYPE uint32_t +#define AES_IV_2__READ 0xffffffffU +#define AES_IV_2__WRITE 0xffffffffU +#define AES_IV_2__PRESERVED 0x00000000U +#define AES_IV_2__RESET_VALUE 0x00000000U + +#endif /* __AES_IV_2_MACRO__ */ + +/** @} end of IV_2 */ + +/* macros for BlueprintGlobalNameSpace::AES_IV_3 */ +/** + * @defgroup at_apb_aes_regs_core_IV_3 IV_3 + * @brief Initialization Vector Registers. The initialization vector (IV) or initial counter value must be written to these registers when starting a new message in CBC or CTR mode (see Control Register), respectively. In CBC and CTR modes, the AES unit does not start encryption/decryption with a partially updated IV. Each register has to be written at least once. The order in which the registers are written does not matter. If the AES unit is non-idle, writes to these registers are ignored. Whenever starting a new message, the corresponding IV value must be provided by the processor. Once started, the AES unit automatically updates the contents of these registers. In ECB mode, the IV registers are not used and do not need to be configured. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_IV_3_MACRO__ +#define __AES_IV_3_MACRO__ + +/* macros for field iv_3 */ +/** + * @defgroup at_apb_aes_regs_core_iv_3_field iv_3_field + * @brief macros for field iv_3 + * @details For IV3 + * @{ + */ +#define AES_IV_3__IV_3__SHIFT 0 +#define AES_IV_3__IV_3__WIDTH 32 +#define AES_IV_3__IV_3__MASK 0xffffffffU +#define AES_IV_3__IV_3__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_IV_3__IV_3__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_IV_3__IV_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_IV_3__IV_3__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define AES_IV_3__IV_3__RESET_VALUE 0x00000000U +/** @} */ +#define AES_IV_3__TYPE uint32_t +#define AES_IV_3__READ 0xffffffffU +#define AES_IV_3__WRITE 0xffffffffU +#define AES_IV_3__PRESERVED 0x00000000U +#define AES_IV_3__RESET_VALUE 0x00000000U + +#endif /* __AES_IV_3_MACRO__ */ + +/** @} end of IV_3 */ + +/* macros for BlueprintGlobalNameSpace::AES_DATA_IN_0 */ +/** + * @defgroup at_apb_aes_regs_core_DATA_IN_0 DATA_IN_0 + * @brief Input Data Registers. If MANUAL_OPERATION=0 (see Control Register), the AES unit automatically starts encryption/decryption after all Input Data registers have been written. Each register has to be written at least once. The order in which the registers are written does not matter. Loaded into the internal State register upon starting encryption/decryption of the next block. After that, the processor can update the Input Data registers (See INPUT_READY field of Status Register). Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_DATA_IN_0_MACRO__ +#define __AES_DATA_IN_0_MACRO__ + +/* macros for field data_in_0 */ +/** + * @defgroup at_apb_aes_regs_core_data_in_0_field data_in_0_field + * @brief macros for field data_in_0 + * @details Input Data + * @{ + */ +#define AES_DATA_IN_0__DATA_IN_0__SHIFT 0 +#define AES_DATA_IN_0__DATA_IN_0__WIDTH 32 +#define AES_DATA_IN_0__DATA_IN_0__MASK 0xffffffffU +#define AES_DATA_IN_0__DATA_IN_0__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_DATA_IN_0__DATA_IN_0__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_DATA_IN_0__DATA_IN_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_DATA_IN_0__DATA_IN_0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AES_DATA_IN_0__DATA_IN_0__RESET_VALUE 0x00000000U +/** @} */ +#define AES_DATA_IN_0__TYPE uint32_t +#define AES_DATA_IN_0__READ 0xffffffffU +#define AES_DATA_IN_0__WRITE 0xffffffffU +#define AES_DATA_IN_0__PRESERVED 0x00000000U +#define AES_DATA_IN_0__RESET_VALUE 0x00000000U + +#endif /* __AES_DATA_IN_0_MACRO__ */ + +/** @} end of DATA_IN_0 */ + +/* macros for BlueprintGlobalNameSpace::AES_DATA_IN_1 */ +/** + * @defgroup at_apb_aes_regs_core_DATA_IN_1 DATA_IN_1 + * @brief Input Data Registers. If MANUAL_OPERATION=0 (see Control Register), the AES unit automatically starts encryption/decryption after all Input Data registers have been written. Each register has to be written at least once. The order in which the registers are written does not matter. Loaded into the internal State register upon starting encryption/decryption of the next block. After that, the processor can update the Input Data registers (See INPUT_READY field of Status Register). Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_DATA_IN_1_MACRO__ +#define __AES_DATA_IN_1_MACRO__ + +/* macros for field data_in_1 */ +/** + * @defgroup at_apb_aes_regs_core_data_in_1_field data_in_1_field + * @brief macros for field data_in_1 + * @details For DATA_IN1 + * @{ + */ +#define AES_DATA_IN_1__DATA_IN_1__SHIFT 0 +#define AES_DATA_IN_1__DATA_IN_1__WIDTH 32 +#define AES_DATA_IN_1__DATA_IN_1__MASK 0xffffffffU +#define AES_DATA_IN_1__DATA_IN_1__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_DATA_IN_1__DATA_IN_1__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_DATA_IN_1__DATA_IN_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_DATA_IN_1__DATA_IN_1__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AES_DATA_IN_1__DATA_IN_1__RESET_VALUE 0x00000000U +/** @} */ +#define AES_DATA_IN_1__TYPE uint32_t +#define AES_DATA_IN_1__READ 0xffffffffU +#define AES_DATA_IN_1__WRITE 0xffffffffU +#define AES_DATA_IN_1__PRESERVED 0x00000000U +#define AES_DATA_IN_1__RESET_VALUE 0x00000000U + +#endif /* __AES_DATA_IN_1_MACRO__ */ + +/** @} end of DATA_IN_1 */ + +/* macros for BlueprintGlobalNameSpace::AES_DATA_IN_2 */ +/** + * @defgroup at_apb_aes_regs_core_DATA_IN_2 DATA_IN_2 + * @brief Input Data Registers. If MANUAL_OPERATION=0 (see Control Register), the AES unit automatically starts encryption/decryption after all Input Data registers have been written. Each register has to be written at least once. The order in which the registers are written does not matter. Loaded into the internal State register upon starting encryption/decryption of the next block. After that, the processor can update the Input Data registers (See INPUT_READY field of Status Register). Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_DATA_IN_2_MACRO__ +#define __AES_DATA_IN_2_MACRO__ + +/* macros for field data_in_2 */ +/** + * @defgroup at_apb_aes_regs_core_data_in_2_field data_in_2_field + * @brief macros for field data_in_2 + * @details For DATA_IN2 + * @{ + */ +#define AES_DATA_IN_2__DATA_IN_2__SHIFT 0 +#define AES_DATA_IN_2__DATA_IN_2__WIDTH 32 +#define AES_DATA_IN_2__DATA_IN_2__MASK 0xffffffffU +#define AES_DATA_IN_2__DATA_IN_2__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_DATA_IN_2__DATA_IN_2__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_DATA_IN_2__DATA_IN_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_DATA_IN_2__DATA_IN_2__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AES_DATA_IN_2__DATA_IN_2__RESET_VALUE 0x00000000U +/** @} */ +#define AES_DATA_IN_2__TYPE uint32_t +#define AES_DATA_IN_2__READ 0xffffffffU +#define AES_DATA_IN_2__WRITE 0xffffffffU +#define AES_DATA_IN_2__PRESERVED 0x00000000U +#define AES_DATA_IN_2__RESET_VALUE 0x00000000U + +#endif /* __AES_DATA_IN_2_MACRO__ */ + +/** @} end of DATA_IN_2 */ + +/* macros for BlueprintGlobalNameSpace::AES_DATA_IN_3 */ +/** + * @defgroup at_apb_aes_regs_core_DATA_IN_3 DATA_IN_3 + * @brief Input Data Registers. If MANUAL_OPERATION=0 (see Control Register), the AES unit automatically starts encryption/decryption after all Input Data registers have been written. Each register has to be written at least once. The order in which the registers are written does not matter. Loaded into the internal State register upon starting encryption/decryption of the next block. After that, the processor can update the Input Data registers (See INPUT_READY field of Status Register). Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_DATA_IN_3_MACRO__ +#define __AES_DATA_IN_3_MACRO__ + +/* macros for field data_in_3 */ +/** + * @defgroup at_apb_aes_regs_core_data_in_3_field data_in_3_field + * @brief macros for field data_in_3 + * @details For DATA_IN3 + * @{ + */ +#define AES_DATA_IN_3__DATA_IN_3__SHIFT 0 +#define AES_DATA_IN_3__DATA_IN_3__WIDTH 32 +#define AES_DATA_IN_3__DATA_IN_3__MASK 0xffffffffU +#define AES_DATA_IN_3__DATA_IN_3__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_DATA_IN_3__DATA_IN_3__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_DATA_IN_3__DATA_IN_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define AES_DATA_IN_3__DATA_IN_3__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define AES_DATA_IN_3__DATA_IN_3__RESET_VALUE 0x00000000U +/** @} */ +#define AES_DATA_IN_3__TYPE uint32_t +#define AES_DATA_IN_3__READ 0xffffffffU +#define AES_DATA_IN_3__WRITE 0xffffffffU +#define AES_DATA_IN_3__PRESERVED 0x00000000U +#define AES_DATA_IN_3__RESET_VALUE 0x00000000U + +#endif /* __AES_DATA_IN_3_MACRO__ */ + +/** @} end of DATA_IN_3 */ + +/* macros for BlueprintGlobalNameSpace::AES_DATA_OUT_0 */ +/** + * @defgroup at_apb_aes_regs_core_DATA_OUT_0 DATA_OUT_0 + * @brief Output Data Register. Holds the output data produced by the AES unit during the last encryption/decryption operation. If MANUAL_OPERATION=0 (see Control Register), the AES unit is stalled when the previous output data has not yet been read and is about to be overwritten. Each register has to be read at least once. The order in which the registers are read does not matter. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_DATA_OUT_0_MACRO__ +#define __AES_DATA_OUT_0_MACRO__ + +/* macros for field data_out_0 */ +/** + * @defgroup at_apb_aes_regs_core_data_out_0_field data_out_0_field + * @brief macros for field data_out_0 + * @details Output Data + * @{ + */ +#define AES_DATA_OUT_0__DATA_OUT_0__SHIFT 0 +#define AES_DATA_OUT_0__DATA_OUT_0__WIDTH 32 +#define AES_DATA_OUT_0__DATA_OUT_0__MASK 0xffffffffU +#define AES_DATA_OUT_0__DATA_OUT_0__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_DATA_OUT_0__DATA_OUT_0__RESET_VALUE 0x00000000U +/** @} */ +#define AES_DATA_OUT_0__TYPE uint32_t +#define AES_DATA_OUT_0__READ 0xffffffffU +#define AES_DATA_OUT_0__PRESERVED 0x00000000U +#define AES_DATA_OUT_0__RESET_VALUE 0x00000000U + +#endif /* __AES_DATA_OUT_0_MACRO__ */ + +/** @} end of DATA_OUT_0 */ + +/* macros for BlueprintGlobalNameSpace::AES_DATA_OUT_1 */ +/** + * @defgroup at_apb_aes_regs_core_DATA_OUT_1 DATA_OUT_1 + * @brief Output Data Register. Holds the output data produced by the AES unit during the last encryption/decryption operation. If MANUAL_OPERATION=0 (see Control Register), the AES unit is stalled when the previous output data has not yet been read and is about to be overwritten. Each register has to be read at least once. The order in which the registers are read does not matter. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_DATA_OUT_1_MACRO__ +#define __AES_DATA_OUT_1_MACRO__ + +/* macros for field data_out_1 */ +/** + * @defgroup at_apb_aes_regs_core_data_out_1_field data_out_1_field + * @brief macros for field data_out_1 + * @details For DATA_OUT1 + * @{ + */ +#define AES_DATA_OUT_1__DATA_OUT_1__SHIFT 0 +#define AES_DATA_OUT_1__DATA_OUT_1__WIDTH 32 +#define AES_DATA_OUT_1__DATA_OUT_1__MASK 0xffffffffU +#define AES_DATA_OUT_1__DATA_OUT_1__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_DATA_OUT_1__DATA_OUT_1__RESET_VALUE 0x00000000U +/** @} */ +#define AES_DATA_OUT_1__TYPE uint32_t +#define AES_DATA_OUT_1__READ 0xffffffffU +#define AES_DATA_OUT_1__PRESERVED 0x00000000U +#define AES_DATA_OUT_1__RESET_VALUE 0x00000000U + +#endif /* __AES_DATA_OUT_1_MACRO__ */ + +/** @} end of DATA_OUT_1 */ + +/* macros for BlueprintGlobalNameSpace::AES_DATA_OUT_2 */ +/** + * @defgroup at_apb_aes_regs_core_DATA_OUT_2 DATA_OUT_2 + * @brief Output Data Register. Holds the output data produced by the AES unit during the last encryption/decryption operation. If MANUAL_OPERATION=0 (see Control Register), the AES unit is stalled when the previous output data has not yet been read and is about to be overwritten. Each register has to be read at least once. The order in which the registers are read does not matter. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_DATA_OUT_2_MACRO__ +#define __AES_DATA_OUT_2_MACRO__ + +/* macros for field data_out_2 */ +/** + * @defgroup at_apb_aes_regs_core_data_out_2_field data_out_2_field + * @brief macros for field data_out_2 + * @details For DATA_OUT2 + * @{ + */ +#define AES_DATA_OUT_2__DATA_OUT_2__SHIFT 0 +#define AES_DATA_OUT_2__DATA_OUT_2__WIDTH 32 +#define AES_DATA_OUT_2__DATA_OUT_2__MASK 0xffffffffU +#define AES_DATA_OUT_2__DATA_OUT_2__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_DATA_OUT_2__DATA_OUT_2__RESET_VALUE 0x00000000U +/** @} */ +#define AES_DATA_OUT_2__TYPE uint32_t +#define AES_DATA_OUT_2__READ 0xffffffffU +#define AES_DATA_OUT_2__PRESERVED 0x00000000U +#define AES_DATA_OUT_2__RESET_VALUE 0x00000000U + +#endif /* __AES_DATA_OUT_2_MACRO__ */ + +/** @} end of DATA_OUT_2 */ + +/* macros for BlueprintGlobalNameSpace::AES_DATA_OUT_3 */ +/** + * @defgroup at_apb_aes_regs_core_DATA_OUT_3 DATA_OUT_3 + * @brief Output Data Register. Holds the output data produced by the AES unit during the last encryption/decryption operation. If MANUAL_OPERATION=0 (see Control Register), the AES unit is stalled when the previous output data has not yet been read and is about to be overwritten. Each register has to be read at least once. The order in which the registers are read does not matter. Upon reset, these registers are cleared with pseudo-random data. definitions. + * @{ + */ +#ifndef __AES_DATA_OUT_3_MACRO__ +#define __AES_DATA_OUT_3_MACRO__ + +/* macros for field data_out_3 */ +/** + * @defgroup at_apb_aes_regs_core_data_out_3_field data_out_3_field + * @brief macros for field data_out_3 + * @details For DATA_OUT3 + * @{ + */ +#define AES_DATA_OUT_3__DATA_OUT_3__SHIFT 0 +#define AES_DATA_OUT_3__DATA_OUT_3__WIDTH 32 +#define AES_DATA_OUT_3__DATA_OUT_3__MASK 0xffffffffU +#define AES_DATA_OUT_3__DATA_OUT_3__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_DATA_OUT_3__DATA_OUT_3__RESET_VALUE 0x00000000U +/** @} */ +#define AES_DATA_OUT_3__TYPE uint32_t +#define AES_DATA_OUT_3__READ 0xffffffffU +#define AES_DATA_OUT_3__PRESERVED 0x00000000U +#define AES_DATA_OUT_3__RESET_VALUE 0x00000000U + +#endif /* __AES_DATA_OUT_3_MACRO__ */ + +/** @} end of DATA_OUT_3 */ + +/* macros for BlueprintGlobalNameSpace::AES_CTRL_SHADOWED */ +/** + * @defgroup at_apb_aes_regs_core_CTRL_SHADOWED CTRL_SHADOWED + * @brief Control Register. Can only be updated when the AES unit is idle. If the AES unit is non-idle, writes to this register are ignored. This register is shadowed, meaning two subsequent write operations are required to change its content. If the two write operations try to set a different value, a recoverable alert is triggered (See Status Register). A read operation clears the internal phase tracking: The next write operation is always considered a first write operation of an update sequence. Any write operation to this register will clear the status tracking required for automatic mode (See MANUAL_OPERATION field). A write to the Control Register is considered the start of a new message. Hence, software needs to provide new key, IV and input data afterwards. definitions. + * @{ + */ +#ifndef __AES_CTRL_SHADOWED_MACRO__ +#define __AES_CTRL_SHADOWED_MACRO__ + +/* macros for field OPERATION */ +/** + * @defgroup at_apb_aes_regs_core_OPERATION_field OPERATION_field + * @brief macros for field OPERATION + * @details Select encryption(0) or decryption(1) operation of AES unit. + * @{ + */ +#define AES_CTRL_SHADOWED__OPERATION__SHIFT 0 +#define AES_CTRL_SHADOWED__OPERATION__WIDTH 1 +#define AES_CTRL_SHADOWED__OPERATION__MASK 0x00000001U +#define AES_CTRL_SHADOWED__OPERATION__READ(src) ((uint32_t)(src) & 0x00000001U) +#define AES_CTRL_SHADOWED__OPERATION__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AES_CTRL_SHADOWED__OPERATION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AES_CTRL_SHADOWED__OPERATION__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AES_CTRL_SHADOWED__OPERATION__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AES_CTRL_SHADOWED__OPERATION__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AES_CTRL_SHADOWED__OPERATION__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field MODE */ +/** + * @defgroup at_apb_aes_regs_core_MODE_field MODE_field + * @brief macros for field MODE + * @details 6-bit one-hot field to select AES block cipher mode. Invalid input values, i.e., values with multiple bits set and value 6'b00_0000, are mapped to AES_NONE (6'b10_0000). 1 AES_ECB 6'b00_0001: Electronic Codebook (ECB) mode. 2 AES_CBC 6'b00_0010: Cipher Block Chaining (CBC) mode. 4 AES_CFB 6'b00_0100: Cipher Feedback (CFB) mode. 8 AES_OFB 6'b00_1000: Output Feedback (OFB) mode. 16 AES_CTR 6'b01_0000: Counter (CTR) mode. 32 AES_NONE 6'b10_0000: Invalid input values, i.e., value with multiple bits set and value 6'b00_0000, are mapped to AES_NONE. Other values are reserved. + * @{ + */ +#define AES_CTRL_SHADOWED__MODE__SHIFT 1 +#define AES_CTRL_SHADOWED__MODE__WIDTH 6 +#define AES_CTRL_SHADOWED__MODE__MASK 0x0000007eU +#define AES_CTRL_SHADOWED__MODE__READ(src) \ + (((uint32_t)(src)\ + & 0x0000007eU) >> 1) +#define AES_CTRL_SHADOWED__MODE__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x0000007eU) +#define AES_CTRL_SHADOWED__MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007eU) | (((uint32_t)(src) <<\ + 1) & 0x0000007eU) +#define AES_CTRL_SHADOWED__MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x0000007eU))) +#define AES_CTRL_SHADOWED__MODE__RESET_VALUE 0x00000020U +/** @} */ + +/* macros for field KEY_LEN */ +/** + * @defgroup at_apb_aes_regs_core_KEY_LEN_field KEY_LEN_field + * @brief macros for field KEY_LEN + * @details 3-bit one-hot field to select AES key length. Invalid input values, i.e., values with multiple bits set, value 3'b000, and value 3'b010 in case 192-bit keys are not supported (because disabled at compile time) are mapped to AES_256 (3'b100). 1 AES_128 3'b001 128-bit key length. 2 AES_192 3'b010 192-bit key length. In case support for 192-bit keys has been disabled at compile time, setting this value results in configuring AES_256 (3'b100). 4 AES_256 3'b100 256-bit key length. Invalid input values, i.e., values with multiple bits set, value 3'b000, and value 3'b010 in case 192-bit keys are not supported (because disabled at compile time) are mapped to AES_256. + * @{ + */ +#define AES_CTRL_SHADOWED__KEY_LEN__SHIFT 7 +#define AES_CTRL_SHADOWED__KEY_LEN__WIDTH 3 +#define AES_CTRL_SHADOWED__KEY_LEN__MASK 0x00000380U +#define AES_CTRL_SHADOWED__KEY_LEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000380U) >> 7) +#define AES_CTRL_SHADOWED__KEY_LEN__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000380U) +#define AES_CTRL_SHADOWED__KEY_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000380U) | (((uint32_t)(src) <<\ + 7) & 0x00000380U) +#define AES_CTRL_SHADOWED__KEY_LEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000380U))) +#define AES_CTRL_SHADOWED__KEY_LEN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field SIDELOAD */ +/** + * @defgroup at_apb_aes_regs_core_SIDELOAD_field SIDELOAD_field + * @brief macros for field SIDELOAD + * @details Controls whether the AES unit uses the key provided by the key manager via key sideload interface (1) or the key provided by software via Initial Key Registers KEY_SHARE1_0 - KEY_SHARE1_7 (0). + * @{ + */ +#define AES_CTRL_SHADOWED__SIDELOAD__SHIFT 10 +#define AES_CTRL_SHADOWED__SIDELOAD__WIDTH 1 +#define AES_CTRL_SHADOWED__SIDELOAD__MASK 0x00000400U +#define AES_CTRL_SHADOWED__SIDELOAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define AES_CTRL_SHADOWED__SIDELOAD__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define AES_CTRL_SHADOWED__SIDELOAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define AES_CTRL_SHADOWED__SIDELOAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define AES_CTRL_SHADOWED__SIDELOAD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define AES_CTRL_SHADOWED__SIDELOAD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define AES_CTRL_SHADOWED__SIDELOAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field MANUAL_OPERATION */ +/** + * @defgroup at_apb_aes_regs_core_MANUAL_OPERATION_field MANUAL_OPERATION_field + * @brief macros for field MANUAL_OPERATION + * @details Controls whether the AES unit is operated in normal/automatic mode (0) or fully manual mode (1). In automatic mode (0), the AES unit automatically i) starts to encrypt/decrypt when it receives new input data, and ii) stalls during the last encryption/decryption cycle if the previous output data has not yet been read. This is the most efficient mode to operate in. Note that the corresponding status tracking is automatically cleared upon a write to the Control Register. In manual mode (1), the AES unit i) only starts to encrypt/decrypt after receiving a start trigger (see Trigger Register), and ii) overwrites previous output data irrespective of whether it has been read out or not. This mode is useful if software needs full control over the AES unit. + * @{ + */ +#define AES_CTRL_SHADOWED__MANUAL_OPERATION__SHIFT 11 +#define AES_CTRL_SHADOWED__MANUAL_OPERATION__WIDTH 1 +#define AES_CTRL_SHADOWED__MANUAL_OPERATION__MASK 0x00000800U +#define AES_CTRL_SHADOWED__MANUAL_OPERATION__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define AES_CTRL_SHADOWED__MANUAL_OPERATION__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define AES_CTRL_SHADOWED__MANUAL_OPERATION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define AES_CTRL_SHADOWED__MANUAL_OPERATION__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define AES_CTRL_SHADOWED__MANUAL_OPERATION__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define AES_CTRL_SHADOWED__MANUAL_OPERATION__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define AES_CTRL_SHADOWED__MANUAL_OPERATION__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field FORCE_ZERO_MASKS */ +/** + * @defgroup at_apb_aes_regs_core_FORCE_ZERO_MASKS_field FORCE_ZERO_MASKS_field + * @brief macros for field FORCE_ZERO_MASKS + * @details Use masks generated by internal masking PRNG (0) or force all masks constantly to zero (1). Setting all masks to constant zero can be useful when performing SCA. To completely disable the masking, the second key share (KEY_SHARE1_0 - KEY_SHARE1_7) must be zero as well. Only applicable if both the Masking parameter and the SecAllowForcingMasks parameter are set to one. + * @{ + */ +#define AES_CTRL_SHADOWED__FORCE_ZERO_MASKS__SHIFT 12 +#define AES_CTRL_SHADOWED__FORCE_ZERO_MASKS__WIDTH 1 +#define AES_CTRL_SHADOWED__FORCE_ZERO_MASKS__MASK 0x00001000U +#define AES_CTRL_SHADOWED__FORCE_ZERO_MASKS__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define AES_CTRL_SHADOWED__FORCE_ZERO_MASKS__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define AES_CTRL_SHADOWED__FORCE_ZERO_MASKS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define AES_CTRL_SHADOWED__FORCE_ZERO_MASKS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define AES_CTRL_SHADOWED__FORCE_ZERO_MASKS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define AES_CTRL_SHADOWED__FORCE_ZERO_MASKS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define AES_CTRL_SHADOWED__FORCE_ZERO_MASKS__RESET_VALUE 0x00000000U +/** @} */ +#define AES_CTRL_SHADOWED__TYPE uint32_t +#define AES_CTRL_SHADOWED__READ 0x00001fffU +#define AES_CTRL_SHADOWED__WRITE 0x00001fffU +#define AES_CTRL_SHADOWED__PRESERVED 0x00000000U +#define AES_CTRL_SHADOWED__RESET_VALUE 0x000000c0U + +#endif /* __AES_CTRL_SHADOWED_MACRO__ */ + +/** @} end of CTRL_SHADOWED */ + +/* macros for BlueprintGlobalNameSpace::AES_TRIGGER */ +/** + * @defgroup at_apb_aes_regs_core_TRIGGER TRIGGER + * @brief Trigger Register. Each bit is individually cleared to zero when executing the corresponding trigger. While executing any of the triggered operations, the AES unit will set the IDLE bit in the Status Register to zero. The processor must check the Status Register before triggering further actions. For example, writes to Initial Key and IV Registers are ignored while the AES unit is busy. Writes to the Input Data Registers are not ignored but the data will be cleared if a KEY_IV_DATA_IN_CLEAR operation is pending. definitions. + * @{ + */ +#ifndef __AES_TRIGGER_MACRO__ +#define __AES_TRIGGER_MACRO__ + +/* macros for field START */ +/** + * @defgroup at_apb_aes_regs_core_START_field START_field + * @brief macros for field START + * @details Keep AES unit paused (0) or trigger the encryption/decryption of one data block (1). This trigger is ignored if MANUAL_OPERATION=0 (see Control Register). + * @{ + */ +#define AES_TRIGGER__START__SHIFT 0 +#define AES_TRIGGER__START__WIDTH 1 +#define AES_TRIGGER__START__MASK 0x00000001U +#define AES_TRIGGER__START__READ(src) ((uint32_t)(src) & 0x00000001U) +#define AES_TRIGGER__START__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define AES_TRIGGER__START__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AES_TRIGGER__START__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define AES_TRIGGER__START__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AES_TRIGGER__START__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AES_TRIGGER__START__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field KEY_IV_DATA_IN_CLEAR */ +/** + * @defgroup at_apb_aes_regs_core_KEY_IV_DATA_IN_CLEAR_field KEY_IV_DATA_IN_CLEAR_field + * @brief macros for field KEY_IV_DATA_IN_CLEAR + * @details Keep current values in Initial Key, internal Full Key and Decryption Key registers, IV registers and Input Data registers (0) or clear all those registers with pseudo-random data (1). + * @{ + */ +#define AES_TRIGGER__KEY_IV_DATA_IN_CLEAR__SHIFT 1 +#define AES_TRIGGER__KEY_IV_DATA_IN_CLEAR__WIDTH 1 +#define AES_TRIGGER__KEY_IV_DATA_IN_CLEAR__MASK 0x00000002U +#define AES_TRIGGER__KEY_IV_DATA_IN_CLEAR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AES_TRIGGER__KEY_IV_DATA_IN_CLEAR__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define AES_TRIGGER__KEY_IV_DATA_IN_CLEAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define AES_TRIGGER__KEY_IV_DATA_IN_CLEAR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define AES_TRIGGER__KEY_IV_DATA_IN_CLEAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AES_TRIGGER__KEY_IV_DATA_IN_CLEAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AES_TRIGGER__KEY_IV_DATA_IN_CLEAR__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field DATA_OUT_CLEAR */ +/** + * @defgroup at_apb_aes_regs_core_DATA_OUT_CLEAR_field DATA_OUT_CLEAR_field + * @brief macros for field DATA_OUT_CLEAR + * @details Keep current values in Output Data registers (0) or clear those registers with pseudo-random data (1). + * @{ + */ +#define AES_TRIGGER__DATA_OUT_CLEAR__SHIFT 2 +#define AES_TRIGGER__DATA_OUT_CLEAR__WIDTH 1 +#define AES_TRIGGER__DATA_OUT_CLEAR__MASK 0x00000004U +#define AES_TRIGGER__DATA_OUT_CLEAR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define AES_TRIGGER__DATA_OUT_CLEAR__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define AES_TRIGGER__DATA_OUT_CLEAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define AES_TRIGGER__DATA_OUT_CLEAR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define AES_TRIGGER__DATA_OUT_CLEAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define AES_TRIGGER__DATA_OUT_CLEAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define AES_TRIGGER__DATA_OUT_CLEAR__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field PRNG_RESEED */ +/** + * @defgroup at_apb_aes_regs_core_PRNG_RESEED_field PRNG_RESEED_field + * @brief macros for field PRNG_RESEED + * @details Keep continuing with the current internal state of the internal pseudo-random number generator used for register clearing (0) or perform a reseed of the internal state from the connected entropy source (1). + * @{ + */ +#define AES_TRIGGER__PRNG_RESEED__SHIFT 3 +#define AES_TRIGGER__PRNG_RESEED__WIDTH 1 +#define AES_TRIGGER__PRNG_RESEED__MASK 0x00000008U +#define AES_TRIGGER__PRNG_RESEED__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define AES_TRIGGER__PRNG_RESEED__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define AES_TRIGGER__PRNG_RESEED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define AES_TRIGGER__PRNG_RESEED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define AES_TRIGGER__PRNG_RESEED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define AES_TRIGGER__PRNG_RESEED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define AES_TRIGGER__PRNG_RESEED__RESET_VALUE 0x00000001U +/** @} */ +#define AES_TRIGGER__TYPE uint32_t +#define AES_TRIGGER__READ 0x0000000fU +#define AES_TRIGGER__WRITE 0x0000000fU +#define AES_TRIGGER__PRESERVED 0x00000000U +#define AES_TRIGGER__RESET_VALUE 0x0000000eU + +#endif /* __AES_TRIGGER_MACRO__ */ + +/** @} end of TRIGGER */ + +/* macros for BlueprintGlobalNameSpace::AES_STATUS */ +/** + * @defgroup at_apb_aes_regs_core_STATUS STATUS + * @brief Status Register definitions. + * @{ + */ +#ifndef __AES_STATUS_MACRO__ +#define __AES_STATUS_MACRO__ + +/* macros for field IDLE */ +/** + * @defgroup at_apb_aes_regs_core_IDLE_field IDLE_field + * @brief macros for field IDLE + * @details The AES unit is idle (1) or busy (0). This flag is 0 if one of the following operations is currently running: i) encryption/decryption, ii) register clearing or iii) PRNG reseeding. This flag is also 0 if an encryption/decryption is running but the AES unit is stalled. + * @{ + */ +#define AES_STATUS__IDLE__SHIFT 0 +#define AES_STATUS__IDLE__WIDTH 1 +#define AES_STATUS__IDLE__MASK 0x00000001U +#define AES_STATUS__IDLE__READ(src) ((uint32_t)(src) & 0x00000001U) +#define AES_STATUS__IDLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AES_STATUS__IDLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AES_STATUS__IDLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field STALL */ +/** + * @defgroup at_apb_aes_regs_core_STALL_field STALL_field + * @brief macros for field STALL + * @details The AES unit is not stalled (0) or stalled (1) because there is previous output data that must be read by the processor before the AES unit can overwrite this data. This flag is not meaningful if MANUAL_OPERATION=1 (see Control Register). + * @{ + */ +#define AES_STATUS__STALL__SHIFT 1 +#define AES_STATUS__STALL__WIDTH 1 +#define AES_STATUS__STALL__MASK 0x00000002U +#define AES_STATUS__STALL__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define AES_STATUS__STALL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AES_STATUS__STALL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AES_STATUS__STALL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field OUTPUT_LOST */ +/** + * @defgroup at_apb_aes_regs_core_OUTPUT_LOST_field OUTPUT_LOST_field + * @brief macros for field OUTPUT_LOST + * @details All previous output data has been fully read by the processor (0) or at least one previous output data block has been lost (1). It has been overwritten by the AES unit before the processor could fully read it. Once set to 1, this flag remains set until AES operation is restarted by re-writing the Control Register. The primary use of this flag is for design verification. This flag is not meaningful if MANUAL_OPERATION=0 (see Control Register). + * @{ + */ +#define AES_STATUS__OUTPUT_LOST__SHIFT 2 +#define AES_STATUS__OUTPUT_LOST__WIDTH 1 +#define AES_STATUS__OUTPUT_LOST__MASK 0x00000004U +#define AES_STATUS__OUTPUT_LOST__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define AES_STATUS__OUTPUT_LOST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define AES_STATUS__OUTPUT_LOST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define AES_STATUS__OUTPUT_LOST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field OUTPUT_VALID */ +/** + * @defgroup at_apb_aes_regs_core_OUTPUT_VALID_field OUTPUT_VALID_field + * @brief macros for field OUTPUT_VALID + * @details The AES unit has no valid output (0) or has valid output data (1). + * @{ + */ +#define AES_STATUS__OUTPUT_VALID__SHIFT 3 +#define AES_STATUS__OUTPUT_VALID__WIDTH 1 +#define AES_STATUS__OUTPUT_VALID__MASK 0x00000008U +#define AES_STATUS__OUTPUT_VALID__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define AES_STATUS__OUTPUT_VALID__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define AES_STATUS__OUTPUT_VALID__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define AES_STATUS__OUTPUT_VALID__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field INPUT_READY */ +/** + * @defgroup at_apb_aes_regs_core_INPUT_READY_field INPUT_READY_field + * @brief macros for field INPUT_READY + * @details The AES unit is ready (1) or not ready (0) to receive new data input via the DATA_IN registers. If the present values in the DATA_IN registers have not yet been loaded into the module this flag is 0 (not ready). + * @{ + */ +#define AES_STATUS__INPUT_READY__SHIFT 4 +#define AES_STATUS__INPUT_READY__WIDTH 1 +#define AES_STATUS__INPUT_READY__MASK 0x00000010U +#define AES_STATUS__INPUT_READY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define AES_STATUS__INPUT_READY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define AES_STATUS__INPUT_READY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define AES_STATUS__INPUT_READY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ALERT_RECOV_CTRL_UPDATE_ERR */ +/** + * @defgroup at_apb_aes_regs_core_ALERT_RECOV_CTRL_UPDATE_ERR_field ALERT_RECOV_CTRL_UPDATE_ERR_field + * @brief macros for field ALERT_RECOV_CTRL_UPDATE_ERR + * @details An update error has not occurred (0) or has occurred (1) in the shadowed Control Register. AES operation needs to be restarted by re-writing the Control Register. + * @{ + */ +#define AES_STATUS__ALERT_RECOV_CTRL_UPDATE_ERR__SHIFT 5 +#define AES_STATUS__ALERT_RECOV_CTRL_UPDATE_ERR__WIDTH 1 +#define AES_STATUS__ALERT_RECOV_CTRL_UPDATE_ERR__MASK 0x00000020U +#define AES_STATUS__ALERT_RECOV_CTRL_UPDATE_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define AES_STATUS__ALERT_RECOV_CTRL_UPDATE_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define AES_STATUS__ALERT_RECOV_CTRL_UPDATE_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define AES_STATUS__ALERT_RECOV_CTRL_UPDATE_ERR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ALERT_FATAL_FAULT */ +/** + * @defgroup at_apb_aes_regs_core_ALERT_FATAL_FAULT_field ALERT_FATAL_FAULT_field + * @brief macros for field ALERT_FATAL_FAULT + * @details No fatal fault has occurred inside the AES unit (0). A fatal fault has occurred and the AES unit needs to be reset (1). Examples for fatal faults include i) storage errors in the Control Register, ii) if any internal FSM enters an invalid state, iii) if any sparsely encoded signal takes on an invalid value, iv) errors in the internal round counter, v) escalations triggered by the life cycle controller, and vi) fatal integrity failures on the TL-UL bus. + * @{ + */ +#define AES_STATUS__ALERT_FATAL_FAULT__SHIFT 6 +#define AES_STATUS__ALERT_FATAL_FAULT__WIDTH 1 +#define AES_STATUS__ALERT_FATAL_FAULT__MASK 0x00000040U +#define AES_STATUS__ALERT_FATAL_FAULT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define AES_STATUS__ALERT_FATAL_FAULT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define AES_STATUS__ALERT_FATAL_FAULT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define AES_STATUS__ALERT_FATAL_FAULT__RESET_VALUE 0x00000000U +/** @} */ +#define AES_STATUS__TYPE uint32_t +#define AES_STATUS__READ 0x0000007fU +#define AES_STATUS__PRESERVED 0x00000000U +#define AES_STATUS__RESET_VALUE 0x00000000U + +#endif /* __AES_STATUS_MACRO__ */ + +/** @} end of STATUS */ + +/* macros for BlueprintGlobalNameSpace::AES_status1 */ +/** + * @defgroup at_apb_aes_regs_core_status1 status1 + * @brief Status Register definitions. + * @{ + */ +#ifndef __AES_STATUS1_MACRO__ +#define __AES_STATUS1_MACRO__ + +/* macros for field sideload_wptr */ +/** + * @defgroup at_apb_aes_regs_core_sideload_wptr_field sideload_wptr_field + * @brief macros for field sideload_wptr + * @details The current value of the sideload key write pointer. This pointer shows the next slot the new word will be stored. + * @{ + */ +#define AES_STATUS1__SIDELOAD_WPTR__SHIFT 0 +#define AES_STATUS1__SIDELOAD_WPTR__WIDTH 3 +#define AES_STATUS1__SIDELOAD_WPTR__MASK 0x00000007U +#define AES_STATUS1__SIDELOAD_WPTR__READ(src) ((uint32_t)(src) & 0x00000007U) +#define AES_STATUS1__SIDELOAD_WPTR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field key_len_err */ +/** + * @defgroup at_apb_aes_regs_core_key_len_err_field key_len_err_field + * @brief macros for field key_len_err + * @details indicates meta key size error. Asserted by HW when sideload_val is written 1 while the meta key size does not match operation key size. cleared by core reset. + * @{ + */ +#define AES_STATUS1__KEY_LEN_ERR__SHIFT 31 +#define AES_STATUS1__KEY_LEN_ERR__WIDTH 1 +#define AES_STATUS1__KEY_LEN_ERR__MASK 0x80000000U +#define AES_STATUS1__KEY_LEN_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define AES_STATUS1__KEY_LEN_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define AES_STATUS1__KEY_LEN_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define AES_STATUS1__KEY_LEN_ERR__RESET_VALUE 0x00000000U +/** @} */ +#define AES_STATUS1__TYPE uint32_t +#define AES_STATUS1__READ 0x80000007U +#define AES_STATUS1__PRESERVED 0x00000000U +#define AES_STATUS1__RESET_VALUE 0x00000000U + +#endif /* __AES_STATUS1_MACRO__ */ + +/** @} end of status1 */ + +/* macros for BlueprintGlobalNameSpace::AES_sideload_ctrl */ +/** + * @defgroup at_apb_aes_regs_core_sideload_ctrl sideload_ctrl + * @brief Contains register fields associated with sideload_ctrl. definitions. + * @{ + */ +#ifndef __AES_SIDELOAD_CTRL_MACRO__ +#define __AES_SIDELOAD_CTRL_MACRO__ + +/* macros for field sideload_val */ +/** + * @defgroup at_apb_aes_regs_core_sideload_val_field sideload_val_field + * @brief macros for field sideload_val + * @details write 1 to assert that sideload key is valid. Write 0 to invalidate. Write 1 will also clear the sideload key write pointer. The sideload key is composed of 8 words, which are stored in a fifo like buffer. A write pointer points to the next slot in the buffer in which a new word will be stored. + * @{ + */ +#define AES_SIDELOAD_CTRL__SIDELOAD_VAL__SHIFT 0 +#define AES_SIDELOAD_CTRL__SIDELOAD_VAL__WIDTH 1 +#define AES_SIDELOAD_CTRL__SIDELOAD_VAL__MASK 0x00000001U +#define AES_SIDELOAD_CTRL__SIDELOAD_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AES_SIDELOAD_CTRL__SIDELOAD_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define AES_SIDELOAD_CTRL__SIDELOAD_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define AES_SIDELOAD_CTRL__SIDELOAD_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define AES_SIDELOAD_CTRL__SIDELOAD_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define AES_SIDELOAD_CTRL__SIDELOAD_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define AES_SIDELOAD_CTRL__SIDELOAD_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sideload_update_en */ +/** + * @defgroup at_apb_aes_regs_core_sideload_update_en_field sideload_update_en_field + * @brief macros for field sideload_update_en + * @details write 1 to enable sideload buffer push. + * @{ + */ +#define AES_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__SHIFT 1 +#define AES_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__WIDTH 1 +#define AES_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__MASK 0x00000002U +#define AES_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define AES_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define AES_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define AES_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define AES_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define AES_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define AES_SIDELOAD_CTRL__SIDELOAD_UPDATE_EN__RESET_VALUE 0x00000001U +/** @} */ +#define AES_SIDELOAD_CTRL__TYPE uint32_t +#define AES_SIDELOAD_CTRL__READ 0x00000003U +#define AES_SIDELOAD_CTRL__WRITE 0x00000003U +#define AES_SIDELOAD_CTRL__PRESERVED 0x00000000U +#define AES_SIDELOAD_CTRL__RESET_VALUE 0x00000002U + +#endif /* __AES_SIDELOAD_CTRL_MACRO__ */ + +/** @} end of sideload_ctrl */ + +/* macros for BlueprintGlobalNameSpace::AES_id */ +/** + * @defgroup at_apb_aes_regs_core_id id + * @brief Contains register fields associated with id. definitions. + * @{ + */ +#ifndef __AES_ID_MACRO__ +#define __AES_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_aes_regs_core_id_field id_field + * @brief macros for field id + * @details AES in ASCII + * @{ + */ +#define AES_ID__ID__SHIFT 0 +#define AES_ID__ID__WIDTH 32 +#define AES_ID__ID__MASK 0xffffffffU +#define AES_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define AES_ID__ID__RESET_VALUE 0x00414553U +/** @} */ +#define AES_ID__TYPE uint32_t +#define AES_ID__READ 0xffffffffU +#define AES_ID__PRESERVED 0x00000000U +#define AES_ID__RESET_VALUE 0x00414553U + +#endif /* __AES_ID_MACRO__ */ + +/** @} end of id */ + +/** @} end of AT_APB_AES_REGS_CORE */ +#endif /* __REG_AT_APB_AES_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_apb_clkrstgen_regs_core_macro.h b/ATM33xx-5/include/reg/at_apb_clkrstgen_regs_core_macro.h new file mode 100644 index 0000000..3b4e4a5 --- /dev/null +++ b/ATM33xx-5/include/reg/at_apb_clkrstgen_regs_core_macro.h @@ -0,0 +1,1382 @@ +/* */ +/* File: at_apb_clkrstgen_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_apb_clkrstgen_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_APB_CLKRSTGEN_REGS_CORE_H__ +#define __REG_AT_APB_CLKRSTGEN_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_APB_CLKRSTGEN_REGS_CORE at_apb_clkrstgen_regs_core + * @ingroup AT_REG + * @brief at_apb_clkrstgen_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::CLKRSTGEN_clk_bp_ctrl */ +/** + * @defgroup at_apb_clkrstgen_regs_core_clk_bp_ctrl clk_bp_ctrl + * @brief Contains register fields associated with clk_bp_ctrl. definitions. + * @{ + */ +#ifndef __CLKRSTGEN_CLK_BP_CTRL_MACRO__ +#define __CLKRSTGEN_CLK_BP_CTRL_MACRO__ + +/* macros for field pll_cluster_sel */ +/** + * @defgroup at_apb_clkrstgen_regs_core_pll_cluster_sel_field pll_cluster_sel_field + * @brief macros for field pll_cluster_sel + * @details selects which clock is output by this cluster 0 = 16MHz 1 = selected pll frequency always leave this cluster in 16MHz (0 setting) before leaving it + * @{ + */ +#define CLKRSTGEN_CLK_BP_CTRL__PLL_CLUSTER_SEL__SHIFT 0 +#define CLKRSTGEN_CLK_BP_CTRL__PLL_CLUSTER_SEL__WIDTH 1 +#define CLKRSTGEN_CLK_BP_CTRL__PLL_CLUSTER_SEL__MASK 0x00000001U +#define CLKRSTGEN_CLK_BP_CTRL__PLL_CLUSTER_SEL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CLKRSTGEN_CLK_BP_CTRL__PLL_CLUSTER_SEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CLKRSTGEN_CLK_BP_CTRL__PLL_CLUSTER_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define CLKRSTGEN_CLK_BP_CTRL__PLL_CLUSTER_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define CLKRSTGEN_CLK_BP_CTRL__PLL_CLUSTER_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define CLKRSTGEN_CLK_BP_CTRL__PLL_CLUSTER_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define CLKRSTGEN_CLK_BP_CTRL__PLL_CLUSTER_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pll_div2_cluster_sel */ +/** + * @defgroup at_apb_clkrstgen_regs_core_pll_div2_cluster_sel_field pll_div2_cluster_sel_field + * @brief macros for field pll_div2_cluster_sel + * @details selects which clock is output by this cluster 0 = 16MHz 1 = (selected pll frequency)/2 always leave this cluster in 16MHz (0 setting) before leaving it + * @{ + */ +#define CLKRSTGEN_CLK_BP_CTRL__PLL_DIV2_CLUSTER_SEL__SHIFT 1 +#define CLKRSTGEN_CLK_BP_CTRL__PLL_DIV2_CLUSTER_SEL__WIDTH 1 +#define CLKRSTGEN_CLK_BP_CTRL__PLL_DIV2_CLUSTER_SEL__MASK 0x00000002U +#define CLKRSTGEN_CLK_BP_CTRL__PLL_DIV2_CLUSTER_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define CLKRSTGEN_CLK_BP_CTRL__PLL_DIV2_CLUSTER_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define CLKRSTGEN_CLK_BP_CTRL__PLL_DIV2_CLUSTER_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define CLKRSTGEN_CLK_BP_CTRL__PLL_DIV2_CLUSTER_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define CLKRSTGEN_CLK_BP_CTRL__PLL_DIV2_CLUSTER_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define CLKRSTGEN_CLK_BP_CTRL__PLL_DIV2_CLUSTER_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define CLKRSTGEN_CLK_BP_CTRL__PLL_DIV2_CLUSTER_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field doubler_cluster_sel */ +/** + * @defgroup at_apb_clkrstgen_regs_core_doubler_cluster_sel_field doubler_cluster_sel_field + * @brief macros for field doubler_cluster_sel + * @details selects which clock is output by this cluster 0 = 16MHz 1 = 32MHz always leave this cluster in 16MHz (0 setting) before leaving it + * @{ + */ +#define CLKRSTGEN_CLK_BP_CTRL__DOUBLER_CLUSTER_SEL__SHIFT 2 +#define CLKRSTGEN_CLK_BP_CTRL__DOUBLER_CLUSTER_SEL__WIDTH 1 +#define CLKRSTGEN_CLK_BP_CTRL__DOUBLER_CLUSTER_SEL__MASK 0x00000004U +#define CLKRSTGEN_CLK_BP_CTRL__DOUBLER_CLUSTER_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define CLKRSTGEN_CLK_BP_CTRL__DOUBLER_CLUSTER_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define CLKRSTGEN_CLK_BP_CTRL__DOUBLER_CLUSTER_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define CLKRSTGEN_CLK_BP_CTRL__DOUBLER_CLUSTER_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define CLKRSTGEN_CLK_BP_CTRL__DOUBLER_CLUSTER_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define CLKRSTGEN_CLK_BP_CTRL__DOUBLER_CLUSTER_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define CLKRSTGEN_CLK_BP_CTRL__DOUBLER_CLUSTER_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field slow_cluster_sel */ +/** + * @defgroup at_apb_clkrstgen_regs_core_slow_cluster_sel_field slow_cluster_sel_field + * @brief macros for field slow_cluster_sel + * @details selects which clock is output by this cluster 0 = 16MHz 1 = 8MHz 3 = 4MHz 2 = 2MHz 6 = 1MHz 7 = 500kHz notice the gray encoding; only change one bit per write always leave this cluster in 16MHz (0 setting) before leaving it + * @{ + */ +#define CLKRSTGEN_CLK_BP_CTRL__SLOW_CLUSTER_SEL__SHIFT 3 +#define CLKRSTGEN_CLK_BP_CTRL__SLOW_CLUSTER_SEL__WIDTH 3 +#define CLKRSTGEN_CLK_BP_CTRL__SLOW_CLUSTER_SEL__MASK 0x00000038U +#define CLKRSTGEN_CLK_BP_CTRL__SLOW_CLUSTER_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define CLKRSTGEN_CLK_BP_CTRL__SLOW_CLUSTER_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define CLKRSTGEN_CLK_BP_CTRL__SLOW_CLUSTER_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define CLKRSTGEN_CLK_BP_CTRL__SLOW_CLUSTER_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define CLKRSTGEN_CLK_BP_CTRL__SLOW_CLUSTER_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cluster_sel */ +/** + * @defgroup at_apb_clkrstgen_regs_core_cluster_sel_field cluster_sel_field + * @brief macros for field cluster_sel + * @details selects which cluster is to drive the backplane clock 0 = clk16x 1 = slow clocks 2 = doubler cluster 4 = pll cluster 8 = pll div2 cluster always cycle through 0 so that only one bits changes per write + * @{ + */ +#define CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__SHIFT 6 +#define CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__WIDTH 4 +#define CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__MASK 0x000003c0U +#define CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x000003c0U) >> 6) +#define CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000003c0U) +#define CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003c0U) | (((uint32_t)(src) <<\ + 6) & 0x000003c0U) +#define CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000003c0U))) +#define CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define CLKRSTGEN_CLK_BP_CTRL__TYPE uint32_t +#define CLKRSTGEN_CLK_BP_CTRL__READ 0x000003ffU +#define CLKRSTGEN_CLK_BP_CTRL__WRITE 0x000003ffU +#define CLKRSTGEN_CLK_BP_CTRL__PRESERVED 0x00000000U +#define CLKRSTGEN_CLK_BP_CTRL__RESET_VALUE 0x00000000U + +#endif /* __CLKRSTGEN_CLK_BP_CTRL_MACRO__ */ + +/** @} end of clk_bp_ctrl */ + +/* macros for BlueprintGlobalNameSpace::CLKRSTGEN_clk_bp_ctrl_stat */ +/** + * @defgroup at_apb_clkrstgen_regs_core_clk_bp_ctrl_stat clk_bp_ctrl_stat + * @brief status of clk_bp_ctrl. definitions. + * @{ + */ +#ifndef __CLKRSTGEN_CLK_BP_CTRL_STAT_MACRO__ +#define __CLKRSTGEN_CLK_BP_CTRL_STAT_MACRO__ + +/* macros for field pll_cluster_sel_stat */ +/** + * @defgroup at_apb_clkrstgen_regs_core_pll_cluster_sel_stat_field pll_cluster_sel_stat_field + * @brief macros for field pll_cluster_sel_stat + * @details status of pll_cluster_sel + * @{ + */ +#define CLKRSTGEN_CLK_BP_CTRL_STAT__PLL_CLUSTER_SEL_STAT__SHIFT 0 +#define CLKRSTGEN_CLK_BP_CTRL_STAT__PLL_CLUSTER_SEL_STAT__WIDTH 1 +#define CLKRSTGEN_CLK_BP_CTRL_STAT__PLL_CLUSTER_SEL_STAT__MASK 0x00000001U +#define CLKRSTGEN_CLK_BP_CTRL_STAT__PLL_CLUSTER_SEL_STAT__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CLKRSTGEN_CLK_BP_CTRL_STAT__PLL_CLUSTER_SEL_STAT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define CLKRSTGEN_CLK_BP_CTRL_STAT__PLL_CLUSTER_SEL_STAT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define CLKRSTGEN_CLK_BP_CTRL_STAT__PLL_CLUSTER_SEL_STAT__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field pll_div2_cluster_sel_stat */ +/** + * @defgroup at_apb_clkrstgen_regs_core_pll_div2_cluster_sel_stat_field pll_div2_cluster_sel_stat_field + * @brief macros for field pll_div2_cluster_sel_stat + * @details status of pll_div2_cluster_sel + * @{ + */ +#define CLKRSTGEN_CLK_BP_CTRL_STAT__PLL_DIV2_CLUSTER_SEL_STAT__SHIFT 1 +#define CLKRSTGEN_CLK_BP_CTRL_STAT__PLL_DIV2_CLUSTER_SEL_STAT__WIDTH 1 +#define CLKRSTGEN_CLK_BP_CTRL_STAT__PLL_DIV2_CLUSTER_SEL_STAT__MASK 0x00000002U +#define CLKRSTGEN_CLK_BP_CTRL_STAT__PLL_DIV2_CLUSTER_SEL_STAT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define CLKRSTGEN_CLK_BP_CTRL_STAT__PLL_DIV2_CLUSTER_SEL_STAT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define CLKRSTGEN_CLK_BP_CTRL_STAT__PLL_DIV2_CLUSTER_SEL_STAT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define CLKRSTGEN_CLK_BP_CTRL_STAT__PLL_DIV2_CLUSTER_SEL_STAT__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field doubler_cluster_sel_stat */ +/** + * @defgroup at_apb_clkrstgen_regs_core_doubler_cluster_sel_stat_field doubler_cluster_sel_stat_field + * @brief macros for field doubler_cluster_sel_stat + * @details status of doubler_cluster_sel + * @{ + */ +#define CLKRSTGEN_CLK_BP_CTRL_STAT__DOUBLER_CLUSTER_SEL_STAT__SHIFT 2 +#define CLKRSTGEN_CLK_BP_CTRL_STAT__DOUBLER_CLUSTER_SEL_STAT__WIDTH 1 +#define CLKRSTGEN_CLK_BP_CTRL_STAT__DOUBLER_CLUSTER_SEL_STAT__MASK 0x00000004U +#define CLKRSTGEN_CLK_BP_CTRL_STAT__DOUBLER_CLUSTER_SEL_STAT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define CLKRSTGEN_CLK_BP_CTRL_STAT__DOUBLER_CLUSTER_SEL_STAT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define CLKRSTGEN_CLK_BP_CTRL_STAT__DOUBLER_CLUSTER_SEL_STAT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define CLKRSTGEN_CLK_BP_CTRL_STAT__DOUBLER_CLUSTER_SEL_STAT__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field slow_cluster_sel_stat */ +/** + * @defgroup at_apb_clkrstgen_regs_core_slow_cluster_sel_stat_field slow_cluster_sel_stat_field + * @brief macros for field slow_cluster_sel_stat + * @details status of slow_cluster_sel + * @{ + */ +#define CLKRSTGEN_CLK_BP_CTRL_STAT__SLOW_CLUSTER_SEL_STAT__SHIFT 3 +#define CLKRSTGEN_CLK_BP_CTRL_STAT__SLOW_CLUSTER_SEL_STAT__WIDTH 3 +#define CLKRSTGEN_CLK_BP_CTRL_STAT__SLOW_CLUSTER_SEL_STAT__MASK 0x00000038U +#define CLKRSTGEN_CLK_BP_CTRL_STAT__SLOW_CLUSTER_SEL_STAT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define CLKRSTGEN_CLK_BP_CTRL_STAT__SLOW_CLUSTER_SEL_STAT__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field cluster_sel_stat */ +/** + * @defgroup at_apb_clkrstgen_regs_core_cluster_sel_stat_field cluster_sel_stat_field + * @brief macros for field cluster_sel_stat + * @details status of cluster_sel + * @{ + */ +#define CLKRSTGEN_CLK_BP_CTRL_STAT__CLUSTER_SEL_STAT__SHIFT 6 +#define CLKRSTGEN_CLK_BP_CTRL_STAT__CLUSTER_SEL_STAT__WIDTH 4 +#define CLKRSTGEN_CLK_BP_CTRL_STAT__CLUSTER_SEL_STAT__MASK 0x000003c0U +#define CLKRSTGEN_CLK_BP_CTRL_STAT__CLUSTER_SEL_STAT__READ(src) \ + (((uint32_t)(src)\ + & 0x000003c0U) >> 6) +#define CLKRSTGEN_CLK_BP_CTRL_STAT__CLUSTER_SEL_STAT__RESET_VALUE 0x00000000U +/** @} */ +#define CLKRSTGEN_CLK_BP_CTRL_STAT__TYPE uint32_t +#define CLKRSTGEN_CLK_BP_CTRL_STAT__READ 0x000003ffU +#define CLKRSTGEN_CLK_BP_CTRL_STAT__PRESERVED 0x00000000U +#define CLKRSTGEN_CLK_BP_CTRL_STAT__RESET_VALUE 0x00000000U + +#endif /* __CLKRSTGEN_CLK_BP_CTRL_STAT_MACRO__ */ + +/** @} end of clk_bp_ctrl_stat */ + +/* macros for BlueprintGlobalNameSpace::CLKRSTGEN_clk_aud_ctrl */ +/** + * @defgroup at_apb_clkrstgen_regs_core_clk_aud_ctrl clk_aud_ctrl + * @brief Contains register fields associated with clk_aud_ctrl. definitions. + * @{ + */ +#ifndef __CLKRSTGEN_CLK_AUD_CTRL_MACRO__ +#define __CLKRSTGEN_CLK_AUD_CTRL_MACRO__ + +/* macros for field pdm_sel */ +/** + * @defgroup at_apb_clkrstgen_regs_core_pdm_sel_field pdm_sel_field + * @brief macros for field pdm_sel + * @details selects the pdm clock source 0 = i2s clock divided by 1 1 = i2s clock divided by 2 + * @{ + */ +#define CLKRSTGEN_CLK_AUD_CTRL__PDM_SEL__SHIFT 0 +#define CLKRSTGEN_CLK_AUD_CTRL__PDM_SEL__WIDTH 1 +#define CLKRSTGEN_CLK_AUD_CTRL__PDM_SEL__MASK 0x00000001U +#define CLKRSTGEN_CLK_AUD_CTRL__PDM_SEL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CLKRSTGEN_CLK_AUD_CTRL__PDM_SEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CLKRSTGEN_CLK_AUD_CTRL__PDM_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define CLKRSTGEN_CLK_AUD_CTRL__PDM_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define CLKRSTGEN_CLK_AUD_CTRL__PDM_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define CLKRSTGEN_CLK_AUD_CTRL__PDM_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define CLKRSTGEN_CLK_AUD_CTRL__PDM_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pdm_clk_enable */ +/** + * @defgroup at_apb_clkrstgen_regs_core_pdm_clk_enable_field pdm_clk_enable_field + * @brief macros for field pdm_clk_enable + * @details enable pdm clock; make frequency selection (pdm_sel) only when disabled + * @{ + */ +#define CLKRSTGEN_CLK_AUD_CTRL__PDM_CLK_ENABLE__SHIFT 4 +#define CLKRSTGEN_CLK_AUD_CTRL__PDM_CLK_ENABLE__WIDTH 1 +#define CLKRSTGEN_CLK_AUD_CTRL__PDM_CLK_ENABLE__MASK 0x00000010U +#define CLKRSTGEN_CLK_AUD_CTRL__PDM_CLK_ENABLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define CLKRSTGEN_CLK_AUD_CTRL__PDM_CLK_ENABLE__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define CLKRSTGEN_CLK_AUD_CTRL__PDM_CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define CLKRSTGEN_CLK_AUD_CTRL__PDM_CLK_ENABLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define CLKRSTGEN_CLK_AUD_CTRL__PDM_CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define CLKRSTGEN_CLK_AUD_CTRL__PDM_CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define CLKRSTGEN_CLK_AUD_CTRL__PDM_CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field i2s_sel */ +/** + * @defgroup at_apb_clkrstgen_regs_core_i2s_sel_field i2s_sel_field + * @brief macros for field i2s_sel + * @details selects the i2s clock source 0 = 16MHz 1 = 32MHz 2 = (pll frequency/1) 3 = (pll frequency/2) 4 = (pll frequency/3) 5 = (pll frequency/4) 6 = (pll frequency/5) 7 = (pll frequency/6) 8 = (pll frequency/7) 9 = (pll frequency/8) + * @{ + */ +#define CLKRSTGEN_CLK_AUD_CTRL__I2S_SEL__SHIFT 5 +#define CLKRSTGEN_CLK_AUD_CTRL__I2S_SEL__WIDTH 4 +#define CLKRSTGEN_CLK_AUD_CTRL__I2S_SEL__MASK 0x000001e0U +#define CLKRSTGEN_CLK_AUD_CTRL__I2S_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x000001e0U) >> 5) +#define CLKRSTGEN_CLK_AUD_CTRL__I2S_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x000001e0U) +#define CLKRSTGEN_CLK_AUD_CTRL__I2S_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001e0U) | (((uint32_t)(src) <<\ + 5) & 0x000001e0U) +#define CLKRSTGEN_CLK_AUD_CTRL__I2S_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000001e0U))) +#define CLKRSTGEN_CLK_AUD_CTRL__I2S_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field i2s_clk_enable */ +/** + * @defgroup at_apb_clkrstgen_regs_core_i2s_clk_enable_field i2s_clk_enable_field + * @brief macros for field i2s_clk_enable + * @details enable i2s clock; make frequency selection (i2s_sel) only when disabled + * @{ + */ +#define CLKRSTGEN_CLK_AUD_CTRL__I2S_CLK_ENABLE__SHIFT 9 +#define CLKRSTGEN_CLK_AUD_CTRL__I2S_CLK_ENABLE__WIDTH 1 +#define CLKRSTGEN_CLK_AUD_CTRL__I2S_CLK_ENABLE__MASK 0x00000200U +#define CLKRSTGEN_CLK_AUD_CTRL__I2S_CLK_ENABLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define CLKRSTGEN_CLK_AUD_CTRL__I2S_CLK_ENABLE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define CLKRSTGEN_CLK_AUD_CTRL__I2S_CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define CLKRSTGEN_CLK_AUD_CTRL__I2S_CLK_ENABLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define CLKRSTGEN_CLK_AUD_CTRL__I2S_CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define CLKRSTGEN_CLK_AUD_CTRL__I2S_CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define CLKRSTGEN_CLK_AUD_CTRL__I2S_CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ +#define CLKRSTGEN_CLK_AUD_CTRL__TYPE uint32_t +#define CLKRSTGEN_CLK_AUD_CTRL__READ 0x000003f1U +#define CLKRSTGEN_CLK_AUD_CTRL__WRITE 0x000003f1U +#define CLKRSTGEN_CLK_AUD_CTRL__PRESERVED 0x00000000U +#define CLKRSTGEN_CLK_AUD_CTRL__RESET_VALUE 0x00000000U + +#endif /* __CLKRSTGEN_CLK_AUD_CTRL_MACRO__ */ + +/** @} end of clk_aud_ctrl */ + +/* macros for BlueprintGlobalNameSpace::CLKRSTGEN_pll_ctrl */ +/** + * @defgroup at_apb_clkrstgen_regs_core_pll_ctrl pll_ctrl + * @brief Contains register fields associated with pll_ctrl. definitions. + * @{ + */ +#ifndef __CLKRSTGEN_PLL_CTRL_MACRO__ +#define __CLKRSTGEN_PLL_CTRL_MACRO__ + +/* macros for field pll_freq_sel */ +/** + * @defgroup at_apb_clkrstgen_regs_core_pll_freq_sel_field pll_freq_sel_field + * @brief macros for field pll_freq_sel + * @details 0 = 48 MHz 1 = 56 MHz / reserved / don't use 2 = 64 MHz 3 = 72 MHz / reserved / don't use 4 = 80 MHz 5 = 88 MHz / reserved / don't use 6 = 96 MHz + * @{ + */ +#define CLKRSTGEN_PLL_CTRL__PLL_FREQ_SEL__SHIFT 0 +#define CLKRSTGEN_PLL_CTRL__PLL_FREQ_SEL__WIDTH 4 +#define CLKRSTGEN_PLL_CTRL__PLL_FREQ_SEL__MASK 0x0000000fU +#define CLKRSTGEN_PLL_CTRL__PLL_FREQ_SEL__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define CLKRSTGEN_PLL_CTRL__PLL_FREQ_SEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define CLKRSTGEN_PLL_CTRL__PLL_FREQ_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define CLKRSTGEN_PLL_CTRL__PLL_FREQ_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define CLKRSTGEN_PLL_CTRL__PLL_FREQ_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pll_enable */ +/** + * @defgroup at_apb_clkrstgen_regs_core_pll_enable_field pll_enable_field + * @brief macros for field pll_enable + * @{ + */ +#define CLKRSTGEN_PLL_CTRL__PLL_ENABLE__SHIFT 4 +#define CLKRSTGEN_PLL_CTRL__PLL_ENABLE__WIDTH 1 +#define CLKRSTGEN_PLL_CTRL__PLL_ENABLE__MASK 0x00000010U +#define CLKRSTGEN_PLL_CTRL__PLL_ENABLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define CLKRSTGEN_PLL_CTRL__PLL_ENABLE__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define CLKRSTGEN_PLL_CTRL__PLL_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define CLKRSTGEN_PLL_CTRL__PLL_ENABLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define CLKRSTGEN_PLL_CTRL__PLL_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define CLKRSTGEN_PLL_CTRL__PLL_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define CLKRSTGEN_PLL_CTRL__PLL_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pll_update */ +/** + * @defgroup at_apb_clkrstgen_regs_core_pll_update_field pll_update_field + * @brief macros for field pll_update + * @{ + */ +#define CLKRSTGEN_PLL_CTRL__PLL_UPDATE__SHIFT 5 +#define CLKRSTGEN_PLL_CTRL__PLL_UPDATE__WIDTH 1 +#define CLKRSTGEN_PLL_CTRL__PLL_UPDATE__MASK 0x00000020U +#define CLKRSTGEN_PLL_CTRL__PLL_UPDATE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define CLKRSTGEN_PLL_CTRL__PLL_UPDATE__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define CLKRSTGEN_PLL_CTRL__PLL_UPDATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define CLKRSTGEN_PLL_CTRL__PLL_UPDATE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define CLKRSTGEN_PLL_CTRL__PLL_UPDATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define CLKRSTGEN_PLL_CTRL__PLL_UPDATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define CLKRSTGEN_PLL_CTRL__PLL_UPDATE__RESET_VALUE 0x00000000U +/** @} */ +#define CLKRSTGEN_PLL_CTRL__TYPE uint32_t +#define CLKRSTGEN_PLL_CTRL__READ 0x0000003fU +#define CLKRSTGEN_PLL_CTRL__WRITE 0x0000003fU +#define CLKRSTGEN_PLL_CTRL__PRESERVED 0x00000000U +#define CLKRSTGEN_PLL_CTRL__RESET_VALUE 0x00000000U + +#endif /* __CLKRSTGEN_PLL_CTRL_MACRO__ */ + +/** @} end of pll_ctrl */ + +/* macros for BlueprintGlobalNameSpace::CLKRSTGEN_user_resets */ +/** + * @defgroup at_apb_clkrstgen_regs_core_user_resets user_resets + * @brief Contains register fields associated with user_resets. definitions. + * @{ + */ +#ifndef __CLKRSTGEN_USER_RESETS_MACRO__ +#define __CLKRSTGEN_USER_RESETS_MACRO__ + +/* macros for field ble_core */ +/** + * @defgroup at_apb_clkrstgen_regs_core_ble_core_field ble_core_field + * @brief macros for field ble_core + * @{ + */ +#define CLKRSTGEN_USER_RESETS__BLE_CORE__SHIFT 0 +#define CLKRSTGEN_USER_RESETS__BLE_CORE__WIDTH 1 +#define CLKRSTGEN_USER_RESETS__BLE_CORE__MASK 0x00000001U +#define CLKRSTGEN_USER_RESETS__BLE_CORE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CLKRSTGEN_USER_RESETS__BLE_CORE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CLKRSTGEN_USER_RESETS__BLE_CORE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define CLKRSTGEN_USER_RESETS__BLE_CORE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define CLKRSTGEN_USER_RESETS__BLE_CORE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define CLKRSTGEN_USER_RESETS__BLE_CORE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define CLKRSTGEN_USER_RESETS__BLE_CORE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ble_intf */ +/** + * @defgroup at_apb_clkrstgen_regs_core_ble_intf_field ble_intf_field + * @brief macros for field ble_intf + * @{ + */ +#define CLKRSTGEN_USER_RESETS__BLE_INTF__SHIFT 1 +#define CLKRSTGEN_USER_RESETS__BLE_INTF__WIDTH 1 +#define CLKRSTGEN_USER_RESETS__BLE_INTF__MASK 0x00000002U +#define CLKRSTGEN_USER_RESETS__BLE_INTF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define CLKRSTGEN_USER_RESETS__BLE_INTF__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define CLKRSTGEN_USER_RESETS__BLE_INTF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define CLKRSTGEN_USER_RESETS__BLE_INTF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define CLKRSTGEN_USER_RESETS__BLE_INTF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define CLKRSTGEN_USER_RESETS__BLE_INTF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define CLKRSTGEN_USER_RESETS__BLE_INTF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ble_lowp */ +/** + * @defgroup at_apb_clkrstgen_regs_core_ble_lowp_field ble_lowp_field + * @brief macros for field ble_lowp + * @{ + */ +#define CLKRSTGEN_USER_RESETS__BLE_LOWP__SHIFT 2 +#define CLKRSTGEN_USER_RESETS__BLE_LOWP__WIDTH 1 +#define CLKRSTGEN_USER_RESETS__BLE_LOWP__MASK 0x00000004U +#define CLKRSTGEN_USER_RESETS__BLE_LOWP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define CLKRSTGEN_USER_RESETS__BLE_LOWP__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define CLKRSTGEN_USER_RESETS__BLE_LOWP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define CLKRSTGEN_USER_RESETS__BLE_LOWP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define CLKRSTGEN_USER_RESETS__BLE_LOWP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define CLKRSTGEN_USER_RESETS__BLE_LOWP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define CLKRSTGEN_USER_RESETS__BLE_LOWP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mdm_rif */ +/** + * @defgroup at_apb_clkrstgen_regs_core_mdm_rif_field mdm_rif_field + * @brief macros for field mdm_rif + * @details forces a reset into both mdm and rif cores + * @{ + */ +#define CLKRSTGEN_USER_RESETS__MDM_RIF__SHIFT 3 +#define CLKRSTGEN_USER_RESETS__MDM_RIF__WIDTH 1 +#define CLKRSTGEN_USER_RESETS__MDM_RIF__MASK 0x00000008U +#define CLKRSTGEN_USER_RESETS__MDM_RIF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define CLKRSTGEN_USER_RESETS__MDM_RIF__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define CLKRSTGEN_USER_RESETS__MDM_RIF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define CLKRSTGEN_USER_RESETS__MDM_RIF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define CLKRSTGEN_USER_RESETS__MDM_RIF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define CLKRSTGEN_USER_RESETS__MDM_RIF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define CLKRSTGEN_USER_RESETS__MDM_RIF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field use_arm_clkdivs */ +/** + * @defgroup at_apb_clkrstgen_regs_core_use_arm_clkdivs_field use_arm_clkdivs_field + * @brief macros for field use_arm_clkdivs + * @{ + */ +#define CLKRSTGEN_USER_RESETS__USE_ARM_CLKDIVS__SHIFT 31 +#define CLKRSTGEN_USER_RESETS__USE_ARM_CLKDIVS__WIDTH 1 +#define CLKRSTGEN_USER_RESETS__USE_ARM_CLKDIVS__MASK 0x80000000U +#define CLKRSTGEN_USER_RESETS__USE_ARM_CLKDIVS__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define CLKRSTGEN_USER_RESETS__USE_ARM_CLKDIVS__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define CLKRSTGEN_USER_RESETS__USE_ARM_CLKDIVS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define CLKRSTGEN_USER_RESETS__USE_ARM_CLKDIVS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define CLKRSTGEN_USER_RESETS__USE_ARM_CLKDIVS__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define CLKRSTGEN_USER_RESETS__USE_ARM_CLKDIVS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define CLKRSTGEN_USER_RESETS__USE_ARM_CLKDIVS__RESET_VALUE 0x00000000U +/** @} */ +#define CLKRSTGEN_USER_RESETS__TYPE uint32_t +#define CLKRSTGEN_USER_RESETS__READ 0x8000000fU +#define CLKRSTGEN_USER_RESETS__WRITE 0x8000000fU +#define CLKRSTGEN_USER_RESETS__PRESERVED 0x00000000U +#define CLKRSTGEN_USER_RESETS__RESET_VALUE 0x00000000U + +#endif /* __CLKRSTGEN_USER_RESETS_MACRO__ */ + +/** @} end of user_resets */ + +/* macros for BlueprintGlobalNameSpace::CLKRSTGEN_user_clk_disables */ +/** + * @defgroup at_apb_clkrstgen_regs_core_user_clk_disables user_clk_disables + * @brief Contains register fields associated with user_clk_disables. definitions. + * @{ + */ +#ifndef __CLKRSTGEN_USER_CLK_DISABLES_MACRO__ +#define __CLKRSTGEN_USER_CLK_DISABLES_MACRO__ + +/* macros for field mdm_rif */ +/** + * @defgroup at_apb_clkrstgen_regs_core_mdm_rif_field mdm_rif_field + * @brief macros for field mdm_rif + * @details turns off 8MHz and 16MHz clocks going to mdm and rif cores + * @{ + */ +#define CLKRSTGEN_USER_CLK_DISABLES__MDM_RIF__SHIFT 0 +#define CLKRSTGEN_USER_CLK_DISABLES__MDM_RIF__WIDTH 1 +#define CLKRSTGEN_USER_CLK_DISABLES__MDM_RIF__MASK 0x00000001U +#define CLKRSTGEN_USER_CLK_DISABLES__MDM_RIF__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CLKRSTGEN_USER_CLK_DISABLES__MDM_RIF__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CLKRSTGEN_USER_CLK_DISABLES__MDM_RIF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define CLKRSTGEN_USER_CLK_DISABLES__MDM_RIF__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define CLKRSTGEN_USER_CLK_DISABLES__MDM_RIF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define CLKRSTGEN_USER_CLK_DISABLES__MDM_RIF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define CLKRSTGEN_USER_CLK_DISABLES__MDM_RIF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pdm */ +/** + * @defgroup at_apb_clkrstgen_regs_core_pdm_field pdm_field + * @brief macros for field pdm + * @{ + */ +#define CLKRSTGEN_USER_CLK_DISABLES__PDM__SHIFT 1 +#define CLKRSTGEN_USER_CLK_DISABLES__PDM__WIDTH 1 +#define CLKRSTGEN_USER_CLK_DISABLES__PDM__MASK 0x00000002U +#define CLKRSTGEN_USER_CLK_DISABLES__PDM__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define CLKRSTGEN_USER_CLK_DISABLES__PDM__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define CLKRSTGEN_USER_CLK_DISABLES__PDM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define CLKRSTGEN_USER_CLK_DISABLES__PDM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define CLKRSTGEN_USER_CLK_DISABLES__PDM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define CLKRSTGEN_USER_CLK_DISABLES__PDM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define CLKRSTGEN_USER_CLK_DISABLES__PDM__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field i2s */ +/** + * @defgroup at_apb_clkrstgen_regs_core_i2s_field i2s_field + * @brief macros for field i2s + * @{ + */ +#define CLKRSTGEN_USER_CLK_DISABLES__I2S__SHIFT 2 +#define CLKRSTGEN_USER_CLK_DISABLES__I2S__WIDTH 1 +#define CLKRSTGEN_USER_CLK_DISABLES__I2S__MASK 0x00000004U +#define CLKRSTGEN_USER_CLK_DISABLES__I2S__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define CLKRSTGEN_USER_CLK_DISABLES__I2S__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define CLKRSTGEN_USER_CLK_DISABLES__I2S__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define CLKRSTGEN_USER_CLK_DISABLES__I2S__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define CLKRSTGEN_USER_CLK_DISABLES__I2S__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define CLKRSTGEN_USER_CLK_DISABLES__I2S__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define CLKRSTGEN_USER_CLK_DISABLES__I2S__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cpu_lpc */ +/** + * @defgroup at_apb_clkrstgen_regs_core_cpu_lpc_field cpu_lpc_field + * @brief macros for field cpu_lpc + * @{ + */ +#define CLKRSTGEN_USER_CLK_DISABLES__CPU_LPC__SHIFT 3 +#define CLKRSTGEN_USER_CLK_DISABLES__CPU_LPC__WIDTH 1 +#define CLKRSTGEN_USER_CLK_DISABLES__CPU_LPC__MASK 0x00000008U +#define CLKRSTGEN_USER_CLK_DISABLES__CPU_LPC__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define CLKRSTGEN_USER_CLK_DISABLES__CPU_LPC__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define CLKRSTGEN_USER_CLK_DISABLES__CPU_LPC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define CLKRSTGEN_USER_CLK_DISABLES__CPU_LPC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define CLKRSTGEN_USER_CLK_DISABLES__CPU_LPC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define CLKRSTGEN_USER_CLK_DISABLES__CPU_LPC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define CLKRSTGEN_USER_CLK_DISABLES__CPU_LPC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hyper */ +/** + * @defgroup at_apb_clkrstgen_regs_core_hyper_field hyper_field + * @brief macros for field hyper + * @{ + */ +#define CLKRSTGEN_USER_CLK_DISABLES__HYPER__SHIFT 4 +#define CLKRSTGEN_USER_CLK_DISABLES__HYPER__WIDTH 1 +#define CLKRSTGEN_USER_CLK_DISABLES__HYPER__MASK 0x00000010U +#define CLKRSTGEN_USER_CLK_DISABLES__HYPER__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define CLKRSTGEN_USER_CLK_DISABLES__HYPER__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define CLKRSTGEN_USER_CLK_DISABLES__HYPER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define CLKRSTGEN_USER_CLK_DISABLES__HYPER__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define CLKRSTGEN_USER_CLK_DISABLES__HYPER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define CLKRSTGEN_USER_CLK_DISABLES__HYPER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define CLKRSTGEN_USER_CLK_DISABLES__HYPER__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cal */ +/** + * @defgroup at_apb_clkrstgen_regs_core_cal_field cal_field + * @brief macros for field cal + * @details radio.calfc_out + * @{ + */ +#define CLKRSTGEN_USER_CLK_DISABLES__CAL__SHIFT 5 +#define CLKRSTGEN_USER_CLK_DISABLES__CAL__WIDTH 1 +#define CLKRSTGEN_USER_CLK_DISABLES__CAL__MASK 0x00000020U +#define CLKRSTGEN_USER_CLK_DISABLES__CAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define CLKRSTGEN_USER_CLK_DISABLES__CAL__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define CLKRSTGEN_USER_CLK_DISABLES__CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define CLKRSTGEN_USER_CLK_DISABLES__CAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define CLKRSTGEN_USER_CLK_DISABLES__CAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define CLKRSTGEN_USER_CLK_DISABLES__CAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define CLKRSTGEN_USER_CLK_DISABLES__CAL__RESET_VALUE 0x00000001U +/** @} */ +#define CLKRSTGEN_USER_CLK_DISABLES__TYPE uint32_t +#define CLKRSTGEN_USER_CLK_DISABLES__READ 0x0000003fU +#define CLKRSTGEN_USER_CLK_DISABLES__WRITE 0x0000003fU +#define CLKRSTGEN_USER_CLK_DISABLES__PRESERVED 0x00000000U +#define CLKRSTGEN_USER_CLK_DISABLES__RESET_VALUE 0x00000020U + +#endif /* __CLKRSTGEN_USER_CLK_DISABLES_MACRO__ */ + +/** @} end of user_clk_disables */ + +/* macros for BlueprintGlobalNameSpace::CLKRSTGEN_user_clk_gate_force_on */ +/** + * @defgroup at_apb_clkrstgen_regs_core_user_clk_gate_force_on user_clk_gate_force_on + * @brief Contains register fields associated with user_clk_gate_force_on. definitions. + * @{ + */ +#ifndef __CLKRSTGEN_USER_CLK_GATE_FORCE_ON_MACRO__ +#define __CLKRSTGEN_USER_CLK_GATE_FORCE_ON_MACRO__ + +/* macros for field ble52_hgclk */ +/** + * @defgroup at_apb_clkrstgen_regs_core_ble52_hgclk_field ble52_hgclk_field + * @brief macros for field ble52_hgclk + * @details The hgclk port of ble52 is normally clock gated by the ble52 core itself. If you want this clock to always run (for instance, for debug) then assert this signal. + * @{ + */ +#define CLKRSTGEN_USER_CLK_GATE_FORCE_ON__BLE52_HGCLK__SHIFT 0 +#define CLKRSTGEN_USER_CLK_GATE_FORCE_ON__BLE52_HGCLK__WIDTH 1 +#define CLKRSTGEN_USER_CLK_GATE_FORCE_ON__BLE52_HGCLK__MASK 0x00000001U +#define CLKRSTGEN_USER_CLK_GATE_FORCE_ON__BLE52_HGCLK__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CLKRSTGEN_USER_CLK_GATE_FORCE_ON__BLE52_HGCLK__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CLKRSTGEN_USER_CLK_GATE_FORCE_ON__BLE52_HGCLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define CLKRSTGEN_USER_CLK_GATE_FORCE_ON__BLE52_HGCLK__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define CLKRSTGEN_USER_CLK_GATE_FORCE_ON__BLE52_HGCLK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define CLKRSTGEN_USER_CLK_GATE_FORCE_ON__BLE52_HGCLK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define CLKRSTGEN_USER_CLK_GATE_FORCE_ON__BLE52_HGCLK__RESET_VALUE 0x00000001U +/** @} */ +#define CLKRSTGEN_USER_CLK_GATE_FORCE_ON__TYPE uint32_t +#define CLKRSTGEN_USER_CLK_GATE_FORCE_ON__READ 0x00000001U +#define CLKRSTGEN_USER_CLK_GATE_FORCE_ON__WRITE 0x00000001U +#define CLKRSTGEN_USER_CLK_GATE_FORCE_ON__PRESERVED 0x00000000U +#define CLKRSTGEN_USER_CLK_GATE_FORCE_ON__RESET_VALUE 0x00000001U + +#endif /* __CLKRSTGEN_USER_CLK_GATE_FORCE_ON_MACRO__ */ + +/** @} end of user_clk_gate_force_on */ + +/* macros for BlueprintGlobalNameSpace::CLKRSTGEN_user_clk_gate_ctrl */ +/** + * @defgroup at_apb_clkrstgen_regs_core_user_clk_gate_ctrl user_clk_gate_ctrl + * @brief Contains register fields associated with user_clk_gate_ctrl. definitions. + * @{ + */ +#ifndef __CLKRSTGEN_USER_CLK_GATE_CTRL_MACRO__ +#define __CLKRSTGEN_USER_CLK_GATE_CTRL_MACRO__ + +/* macros for field apb0_hclk */ +/** + * @defgroup at_apb_clkrstgen_regs_core_apb0_hclk_field apb0_hclk_field + * @brief macros for field apb0_hclk + * @details 0,3=normal; 1=forced on; 2=forced off + * @{ + */ +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB0_HCLK__SHIFT 0 +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB0_HCLK__WIDTH 2 +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB0_HCLK__MASK 0x00000003U +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB0_HCLK__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB0_HCLK__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB0_HCLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB0_HCLK__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB0_HCLK__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field apb1_hclk */ +/** + * @defgroup at_apb_clkrstgen_regs_core_apb1_hclk_field apb1_hclk_field + * @brief macros for field apb1_hclk + * @details 0,3=normal; 1=forced on; 2=forced off + * @{ + */ +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB1_HCLK__SHIFT 2 +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB1_HCLK__WIDTH 2 +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB1_HCLK__MASK 0x0000000cU +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB1_HCLK__READ(src) \ + (((uint32_t)(src)\ + & 0x0000000cU) >> 2) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB1_HCLK__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000000cU) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB1_HCLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((uint32_t)(src) <<\ + 2) & 0x0000000cU) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB1_HCLK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000000cU))) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB1_HCLK__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field apb2_hclk */ +/** + * @defgroup at_apb_clkrstgen_regs_core_apb2_hclk_field apb2_hclk_field + * @brief macros for field apb2_hclk + * @details 0,3=normal; 1=forced on; 2=forced off + * @{ + */ +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB2_HCLK__SHIFT 4 +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB2_HCLK__WIDTH 2 +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB2_HCLK__MASK 0x00000030U +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB2_HCLK__READ(src) \ + (((uint32_t)(src)\ + & 0x00000030U) >> 4) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB2_HCLK__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000030U) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB2_HCLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((uint32_t)(src) <<\ + 4) & 0x00000030U) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB2_HCLK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000030U))) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__APB2_HCLK__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field dma_hclk */ +/** + * @defgroup at_apb_clkrstgen_regs_core_dma_hclk_field dma_hclk_field + * @brief macros for field dma_hclk + * @details 0,3=normal; 1=forced on; 2=forced off + * @{ + */ +#define CLKRSTGEN_USER_CLK_GATE_CTRL__DMA_HCLK__SHIFT 6 +#define CLKRSTGEN_USER_CLK_GATE_CTRL__DMA_HCLK__WIDTH 2 +#define CLKRSTGEN_USER_CLK_GATE_CTRL__DMA_HCLK__MASK 0x000000c0U +#define CLKRSTGEN_USER_CLK_GATE_CTRL__DMA_HCLK__READ(src) \ + (((uint32_t)(src)\ + & 0x000000c0U) >> 6) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__DMA_HCLK__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000000c0U) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__DMA_HCLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((uint32_t)(src) <<\ + 6) & 0x000000c0U) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__DMA_HCLK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000000c0U))) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__DMA_HCLK__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field sha_hclk */ +/** + * @defgroup at_apb_clkrstgen_regs_core_sha_hclk_field sha_hclk_field + * @brief macros for field sha_hclk + * @details 0,3=normal; 1=forced on; 2=forced off + * @{ + */ +#define CLKRSTGEN_USER_CLK_GATE_CTRL__SHA_HCLK__SHIFT 8 +#define CLKRSTGEN_USER_CLK_GATE_CTRL__SHA_HCLK__WIDTH 2 +#define CLKRSTGEN_USER_CLK_GATE_CTRL__SHA_HCLK__MASK 0x00000300U +#define CLKRSTGEN_USER_CLK_GATE_CTRL__SHA_HCLK__READ(src) \ + (((uint32_t)(src)\ + & 0x00000300U) >> 8) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__SHA_HCLK__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000300U) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__SHA_HCLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((uint32_t)(src) <<\ + 8) & 0x00000300U) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__SHA_HCLK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000300U))) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__SHA_HCLK__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field romc_hclk */ +/** + * @defgroup at_apb_clkrstgen_regs_core_romc_hclk_field romc_hclk_field + * @brief macros for field romc_hclk + * @details 0,3=normal; 1=forced on; 2=forced off + * @{ + */ +#define CLKRSTGEN_USER_CLK_GATE_CTRL__ROMC_HCLK__SHIFT 10 +#define CLKRSTGEN_USER_CLK_GATE_CTRL__ROMC_HCLK__WIDTH 2 +#define CLKRSTGEN_USER_CLK_GATE_CTRL__ROMC_HCLK__MASK 0x00000c00U +#define CLKRSTGEN_USER_CLK_GATE_CTRL__ROMC_HCLK__READ(src) \ + (((uint32_t)(src)\ + & 0x00000c00U) >> 10) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__ROMC_HCLK__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000c00U) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__ROMC_HCLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000c00U) | (((uint32_t)(src) <<\ + 10) & 0x00000c00U) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__ROMC_HCLK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000c00U))) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__ROMC_HCLK__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ble_hclk */ +/** + * @defgroup at_apb_clkrstgen_regs_core_ble_hclk_field ble_hclk_field + * @brief macros for field ble_hclk + * @details 0,3=normal; 1=forced on; 2=forced off + * @{ + */ +#define CLKRSTGEN_USER_CLK_GATE_CTRL__BLE_HCLK__SHIFT 12 +#define CLKRSTGEN_USER_CLK_GATE_CTRL__BLE_HCLK__WIDTH 2 +#define CLKRSTGEN_USER_CLK_GATE_CTRL__BLE_HCLK__MASK 0x00003000U +#define CLKRSTGEN_USER_CLK_GATE_CTRL__BLE_HCLK__READ(src) \ + (((uint32_t)(src)\ + & 0x00003000U) >> 12) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__BLE_HCLK__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00003000U) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__BLE_HCLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((uint32_t)(src) <<\ + 12) & 0x00003000U) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__BLE_HCLK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00003000U))) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__BLE_HCLK__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field sticky_clk */ +/** + * @defgroup at_apb_clkrstgen_regs_core_sticky_clk_field sticky_clk_field + * @brief macros for field sticky_clk + * @details 0=forced off; 1=forced on; clock enable signal to sticky bits. + * @{ + */ +#define CLKRSTGEN_USER_CLK_GATE_CTRL__STICKY_CLK__SHIFT 14 +#define CLKRSTGEN_USER_CLK_GATE_CTRL__STICKY_CLK__WIDTH 1 +#define CLKRSTGEN_USER_CLK_GATE_CTRL__STICKY_CLK__MASK 0x00004000U +#define CLKRSTGEN_USER_CLK_GATE_CTRL__STICKY_CLK__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__STICKY_CLK__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__STICKY_CLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__STICKY_CLK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__STICKY_CLK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__STICKY_CLK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define CLKRSTGEN_USER_CLK_GATE_CTRL__STICKY_CLK__RESET_VALUE 0x00000000U +/** @} */ +#define CLKRSTGEN_USER_CLK_GATE_CTRL__TYPE uint32_t +#define CLKRSTGEN_USER_CLK_GATE_CTRL__READ 0x00007fffU +#define CLKRSTGEN_USER_CLK_GATE_CTRL__WRITE 0x00007fffU +#define CLKRSTGEN_USER_CLK_GATE_CTRL__PRESERVED 0x00000000U +#define CLKRSTGEN_USER_CLK_GATE_CTRL__RESET_VALUE 0x00001655U + +#endif /* __CLKRSTGEN_USER_CLK_GATE_CTRL_MACRO__ */ + +/** @} end of user_clk_gate_ctrl */ + +/* macros for BlueprintGlobalNameSpace::CLKRSTGEN_configuration */ +/** + * @defgroup at_apb_clkrstgen_regs_core_configuration configuration + * @brief Contains register fields associated with configuration. definitions. + * @{ + */ +#ifndef __CLKRSTGEN_CONFIGURATION_MACRO__ +#define __CLKRSTGEN_CONFIGURATION_MACRO__ + +/* macros for field index */ +/** + * @defgroup at_apb_clkrstgen_regs_core_index_field index_field + * @brief macros for field index + * @details which fpga configuration? + * @{ + */ +#define CLKRSTGEN_CONFIGURATION__INDEX__SHIFT 0 +#define CLKRSTGEN_CONFIGURATION__INDEX__WIDTH 8 +#define CLKRSTGEN_CONFIGURATION__INDEX__MASK 0x000000ffU +#define CLKRSTGEN_CONFIGURATION__INDEX__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define CLKRSTGEN_CONFIGURATION__INDEX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pll_ready */ +/** + * @defgroup at_apb_clkrstgen_regs_core_pll_ready_field pll_ready_field + * @brief macros for field pll_ready + * @details indicates when PLL output is no longer being gated and PLL clock is available + * @{ + */ +#define CLKRSTGEN_CONFIGURATION__PLL_READY__SHIFT 8 +#define CLKRSTGEN_CONFIGURATION__PLL_READY__WIDTH 1 +#define CLKRSTGEN_CONFIGURATION__PLL_READY__MASK 0x00000100U +#define CLKRSTGEN_CONFIGURATION__PLL_READY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define CLKRSTGEN_CONFIGURATION__PLL_READY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define CLKRSTGEN_CONFIGURATION__PLL_READY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define CLKRSTGEN_CONFIGURATION__PLL_READY__RESET_VALUE 0x00000000U +/** @} */ +#define CLKRSTGEN_CONFIGURATION__TYPE uint32_t +#define CLKRSTGEN_CONFIGURATION__READ 0x000001ffU +#define CLKRSTGEN_CONFIGURATION__PRESERVED 0x00000000U +#define CLKRSTGEN_CONFIGURATION__RESET_VALUE 0x00000000U + +#endif /* __CLKRSTGEN_CONFIGURATION_MACRO__ */ + +/** @} end of configuration */ + +/* macros for BlueprintGlobalNameSpace::CLKRSTGEN_clksync */ +/** + * @defgroup at_apb_clkrstgen_regs_core_clksync clksync + * @brief Contains register fields associated with clksync. definitions. + * @{ + */ +#ifndef __CLKRSTGEN_CLKSYNC_MACRO__ +#define __CLKRSTGEN_CLKSYNC_MACRO__ + +/* macros for field div_val */ +/** + * @defgroup at_apb_clkrstgen_regs_core_div_val_field div_val_field + * @brief macros for field div_val + * @details how much to divide the pll to get 16 MHz? + * @{ + */ +#define CLKRSTGEN_CLKSYNC__DIV_VAL__SHIFT 0 +#define CLKRSTGEN_CLKSYNC__DIV_VAL__WIDTH 4 +#define CLKRSTGEN_CLKSYNC__DIV_VAL__MASK 0x0000000fU +#define CLKRSTGEN_CLKSYNC__DIV_VAL__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define CLKRSTGEN_CLKSYNC__DIV_VAL__WRITE(src) ((uint32_t)(src) & 0x0000000fU) +#define CLKRSTGEN_CLKSYNC__DIV_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define CLKRSTGEN_CLKSYNC__DIV_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define CLKRSTGEN_CLKSYNC__DIV_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clk16_src */ +/** + * @defgroup at_apb_clkrstgen_regs_core_clk16_src_field clk16_src_field + * @brief macros for field clk16_src + * @details selects the source of the 16 MHz clock domain 0 = crystal 1 = divided down pll + * @{ + */ +#define CLKRSTGEN_CLKSYNC__CLK16_SRC__SHIFT 4 +#define CLKRSTGEN_CLKSYNC__CLK16_SRC__WIDTH 1 +#define CLKRSTGEN_CLKSYNC__CLK16_SRC__MASK 0x00000010U +#define CLKRSTGEN_CLKSYNC__CLK16_SRC__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define CLKRSTGEN_CLKSYNC__CLK16_SRC__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define CLKRSTGEN_CLKSYNC__CLK16_SRC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define CLKRSTGEN_CLKSYNC__CLK16_SRC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define CLKRSTGEN_CLKSYNC__CLK16_SRC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define CLKRSTGEN_CLKSYNC__CLK16_SRC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define CLKRSTGEN_CLKSYNC__CLK16_SRC__RESET_VALUE 0x00000000U +/** @} */ +#define CLKRSTGEN_CLKSYNC__TYPE uint32_t +#define CLKRSTGEN_CLKSYNC__READ 0x0000001fU +#define CLKRSTGEN_CLKSYNC__WRITE 0x0000001fU +#define CLKRSTGEN_CLKSYNC__PRESERVED 0x00000000U +#define CLKRSTGEN_CLKSYNC__RESET_VALUE 0x00000000U + +#endif /* __CLKRSTGEN_CLKSYNC_MACRO__ */ + +/** @} end of clksync */ + +/* macros for BlueprintGlobalNameSpace::CLKRSTGEN_core_id */ +/** + * @defgroup at_apb_clkrstgen_regs_core_core_id core_id + * @brief core id definitions. + * @{ + */ +#ifndef __CLKRSTGEN_CORE_ID_MACRO__ +#define __CLKRSTGEN_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_clkrstgen_regs_core_id_field id_field + * @brief macros for field id + * @details CLKR in ASCII + * @{ + */ +#define CLKRSTGEN_CORE_ID__ID__SHIFT 0 +#define CLKRSTGEN_CORE_ID__ID__WIDTH 32 +#define CLKRSTGEN_CORE_ID__ID__MASK 0xffffffffU +#define CLKRSTGEN_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define CLKRSTGEN_CORE_ID__ID__RESET_VALUE 0x434c4b52U +/** @} */ +#define CLKRSTGEN_CORE_ID__TYPE uint32_t +#define CLKRSTGEN_CORE_ID__READ 0xffffffffU +#define CLKRSTGEN_CORE_ID__PRESERVED 0x00000000U +#define CLKRSTGEN_CORE_ID__RESET_VALUE 0x434c4b52U + +#endif /* __CLKRSTGEN_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of AT_APB_CLKRSTGEN_REGS_CORE */ +#endif /* __REG_AT_APB_CLKRSTGEN_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_apb_gadc_regs_core_macro.h b/ATM33xx-5/include/reg/at_apb_gadc_regs_core_macro.h new file mode 100644 index 0000000..68aa140 --- /dev/null +++ b/ATM33xx-5/include/reg/at_apb_gadc_regs_core_macro.h @@ -0,0 +1,2285 @@ +/* */ +/* File: at_apb_gadc_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_apb_gadc_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_APB_GADC_REGS_CORE_H__ +#define __REG_AT_APB_GADC_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_APB_GADC_REGS_CORE at_apb_gadc_regs_core + * @ingroup AT_REG + * @brief at_apb_gadc_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::DGADC_ctrl */ +/** + * @defgroup at_apb_gadc_regs_core_ctrl ctrl + * @brief control signals definitions. + * @{ + */ +#ifndef __DGADC_CTRL_MACRO__ +#define __DGADC_CTRL_MACRO__ + +/* macros for field enable_dp */ +/** + * @defgroup at_apb_gadc_regs_core_enable_dp_field enable_dp_field + * @brief macros for field enable_dp + * @details Enables digital datapath. + * @{ + */ +#define DGADC_CTRL__ENABLE_DP__SHIFT 0 +#define DGADC_CTRL__ENABLE_DP__WIDTH 1 +#define DGADC_CTRL__ENABLE_DP__MASK 0x00000001U +#define DGADC_CTRL__ENABLE_DP__READ(src) ((uint32_t)(src) & 0x00000001U) +#define DGADC_CTRL__ENABLE_DP__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define DGADC_CTRL__ENABLE_DP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define DGADC_CTRL__ENABLE_DP__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define DGADC_CTRL__ENABLE_DP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define DGADC_CTRL__ENABLE_DP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define DGADC_CTRL__ENABLE_DP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mode */ +/** + * @defgroup at_apb_gadc_regs_core_mode_field mode_field + * @brief macros for field mode + * @details What is the mode of operation? 0 = continuous 1 = one-shot + * @{ + */ +#define DGADC_CTRL__MODE__SHIFT 1 +#define DGADC_CTRL__MODE__WIDTH 1 +#define DGADC_CTRL__MODE__MASK 0x00000002U +#define DGADC_CTRL__MODE__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define DGADC_CTRL__MODE__WRITE(src) (((uint32_t)(src) << 1) & 0x00000002U) +#define DGADC_CTRL__MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define DGADC_CTRL__MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define DGADC_CTRL__MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define DGADC_CTRL__MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define DGADC_CTRL__MODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field warmup */ +/** + * @defgroup at_apb_gadc_regs_core_warmup_field warmup_field + * @brief macros for field warmup + * @details Do 8 clocks cycle of warmup at beginning of round. No data sampled during this period. + * @{ + */ +#define DGADC_CTRL__WARMUP__SHIFT 2 +#define DGADC_CTRL__WARMUP__WIDTH 1 +#define DGADC_CTRL__WARMUP__MASK 0x00000004U +#define DGADC_CTRL__WARMUP__READ(src) (((uint32_t)(src) & 0x00000004U) >> 2) +#define DGADC_CTRL__WARMUP__WRITE(src) (((uint32_t)(src) << 2) & 0x00000004U) +#define DGADC_CTRL__WARMUP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define DGADC_CTRL__WARMUP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define DGADC_CTRL__WARMUP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define DGADC_CTRL__WARMUP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define DGADC_CTRL__WARMUP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field code */ +/** + * @defgroup at_apb_gadc_regs_core_code_field code_field + * @brief macros for field code + * @details Specifies ADC input data code bit representation. 0 = MSB of input gadc data is inverted 1 = MSB of input gadc data is not inverted Data in pedestal format is converted to 2's complement. + * @{ + */ +#define DGADC_CTRL__CODE__SHIFT 3 +#define DGADC_CTRL__CODE__WIDTH 1 +#define DGADC_CTRL__CODE__MASK 0x00000008U +#define DGADC_CTRL__CODE__READ(src) (((uint32_t)(src) & 0x00000008U) >> 3) +#define DGADC_CTRL__CODE__WRITE(src) (((uint32_t)(src) << 3) & 0x00000008U) +#define DGADC_CTRL__CODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define DGADC_CTRL__CODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define DGADC_CTRL__CODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define DGADC_CTRL__CODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define DGADC_CTRL__CODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clkdiv */ +/** + * @defgroup at_apb_gadc_regs_core_clkdiv_field clkdiv_field + * @brief macros for field clkdiv + * @details gadc clock frequency 0 = 2.00MHz 1 = 1.00MHz 2 = 0.50MHz 3 = 0.25MHz + * @{ + */ +#define DGADC_CTRL__CLKDIV__SHIFT 4 +#define DGADC_CTRL__CLKDIV__WIDTH 2 +#define DGADC_CTRL__CLKDIV__MASK 0x00000030U +#define DGADC_CTRL__CLKDIV__READ(src) (((uint32_t)(src) & 0x00000030U) >> 4) +#define DGADC_CTRL__CLKDIV__WRITE(src) (((uint32_t)(src) << 4) & 0x00000030U) +#define DGADC_CTRL__CLKDIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((uint32_t)(src) <<\ + 4) & 0x00000030U) +#define DGADC_CTRL__CLKDIV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000030U))) +#define DGADC_CTRL__CLKDIV__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wait_amount */ +/** + * @defgroup at_apb_gadc_regs_core_wait_amount_field wait_amount_field + * @brief macros for field wait_amount + * @details Specifies how many wait cycles in gadc clock cycles. + * @{ + */ +#define DGADC_CTRL__WAIT_AMOUNT__SHIFT 6 +#define DGADC_CTRL__WAIT_AMOUNT__WIDTH 7 +#define DGADC_CTRL__WAIT_AMOUNT__MASK 0x00001fc0U +#define DGADC_CTRL__WAIT_AMOUNT__READ(src) \ + (((uint32_t)(src)\ + & 0x00001fc0U) >> 6) +#define DGADC_CTRL__WAIT_AMOUNT__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00001fc0U) +#define DGADC_CTRL__WAIT_AMOUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fc0U) | (((uint32_t)(src) <<\ + 6) & 0x00001fc0U) +#define DGADC_CTRL__WAIT_AMOUNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00001fc0U))) +#define DGADC_CTRL__WAIT_AMOUNT__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field averaging_amount */ +/** + * @defgroup at_apb_gadc_regs_core_averaging_amount_field averaging_amount_field + * @brief macros for field averaging_amount + * @details average 2^averaging_amount samples + * @{ + */ +#define DGADC_CTRL__AVERAGING_AMOUNT__SHIFT 13 +#define DGADC_CTRL__AVERAGING_AMOUNT__WIDTH 3 +#define DGADC_CTRL__AVERAGING_AMOUNT__MASK 0x0000e000U +#define DGADC_CTRL__AVERAGING_AMOUNT__READ(src) \ + (((uint32_t)(src)\ + & 0x0000e000U) >> 13) +#define DGADC_CTRL__AVERAGING_AMOUNT__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0000e000U) +#define DGADC_CTRL__AVERAGING_AMOUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((uint32_t)(src) <<\ + 13) & 0x0000e000U) +#define DGADC_CTRL__AVERAGING_AMOUNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0000e000U))) +#define DGADC_CTRL__AVERAGING_AMOUNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_channels */ +/** + * @defgroup at_apb_gadc_regs_core_watch_channels_field watch_channels_field + * @brief macros for field watch_channels + * @details Which channels are active? bit 0 = Not Used bit 1 = Vbatt bit 2 = Vstor bit 3 = core supply bit 4 = temperature bit 5 = external port 1; differential bit 6 = external port 0; differential bit 7 = external port 1; single ended pos bit 8 = external port 1; single ended neg bit 9 = external port 0; single ended pos bit 10 = external port 0; single ended neg bit 11 = Vli-ion bit 12-14 = input short bit 15 = No-Connect + * @{ + */ +#define DGADC_CTRL__WATCH_CHANNELS__SHIFT 16 +#define DGADC_CTRL__WATCH_CHANNELS__WIDTH 16 +#define DGADC_CTRL__WATCH_CHANNELS__MASK 0xffff0000U +#define DGADC_CTRL__WATCH_CHANNELS__READ(src) \ + (((uint32_t)(src)\ + & 0xffff0000U) >> 16) +#define DGADC_CTRL__WATCH_CHANNELS__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0xffff0000U) +#define DGADC_CTRL__WATCH_CHANNELS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define DGADC_CTRL__WATCH_CHANNELS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define DGADC_CTRL__WATCH_CHANNELS__RESET_VALUE 0x00000000U +/** @} */ +#define DGADC_CTRL__TYPE uint32_t +#define DGADC_CTRL__READ 0xffffffffU +#define DGADC_CTRL__WRITE 0xffffffffU +#define DGADC_CTRL__PRESERVED 0x00000000U +#define DGADC_CTRL__RESET_VALUE 0x00000100U + +#endif /* __DGADC_CTRL_MACRO__ */ + +/** @} end of ctrl */ + +/* macros for BlueprintGlobalNameSpace::DGADC_ctrl1 */ +/** + * @defgroup at_apb_gadc_regs_core_ctrl1 ctrl1 + * @brief control signals definitions. + * @{ + */ +#ifndef __DGADC_CTRL1_MACRO__ +#define __DGADC_CTRL1_MACRO__ + +/* macros for field ch_sel_ovrd */ +/** + * @defgroup at_apb_gadc_regs_core_ch_sel_ovrd_field ch_sel_ovrd_field + * @brief macros for field ch_sel_ovrd + * @details when set overrides gadc channel select. + * @{ + */ +#define DGADC_CTRL1__CH_SEL_OVRD__SHIFT 0 +#define DGADC_CTRL1__CH_SEL_OVRD__WIDTH 1 +#define DGADC_CTRL1__CH_SEL_OVRD__MASK 0x00000001U +#define DGADC_CTRL1__CH_SEL_OVRD__READ(src) ((uint32_t)(src) & 0x00000001U) +#define DGADC_CTRL1__CH_SEL_OVRD__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define DGADC_CTRL1__CH_SEL_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define DGADC_CTRL1__CH_SEL_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define DGADC_CTRL1__CH_SEL_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define DGADC_CTRL1__CH_SEL_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define DGADC_CTRL1__CH_SEL_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch_sel_ovrd_val */ +/** + * @defgroup at_apb_gadc_regs_core_ch_sel_ovrd_val_field ch_sel_ovrd_val_field + * @brief macros for field ch_sel_ovrd_val + * @details when override is set, what's the gadc channel to select. + * @{ + */ +#define DGADC_CTRL1__CH_SEL_OVRD_VAL__SHIFT 1 +#define DGADC_CTRL1__CH_SEL_OVRD_VAL__WIDTH 4 +#define DGADC_CTRL1__CH_SEL_OVRD_VAL__MASK 0x0000001eU +#define DGADC_CTRL1__CH_SEL_OVRD_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x0000001eU) >> 1) +#define DGADC_CTRL1__CH_SEL_OVRD_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x0000001eU) +#define DGADC_CTRL1__CH_SEL_OVRD_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001eU) | (((uint32_t)(src) <<\ + 1) & 0x0000001eU) +#define DGADC_CTRL1__CH_SEL_OVRD_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x0000001eU))) +#define DGADC_CTRL1__CH_SEL_OVRD_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ddr_en */ +/** + * @defgroup at_apb_gadc_regs_core_ddr_en_field ddr_en_field + * @brief macros for field ddr_en + * @details for debug; brings out gadc_out as a 6b wide ddr bus + * @{ + */ +#define DGADC_CTRL1__DDR_EN__SHIFT 5 +#define DGADC_CTRL1__DDR_EN__WIDTH 1 +#define DGADC_CTRL1__DDR_EN__MASK 0x00000020U +#define DGADC_CTRL1__DDR_EN__READ(src) (((uint32_t)(src) & 0x00000020U) >> 5) +#define DGADC_CTRL1__DDR_EN__WRITE(src) (((uint32_t)(src) << 5) & 0x00000020U) +#define DGADC_CTRL1__DDR_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define DGADC_CTRL1__DDR_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define DGADC_CTRL1__DDR_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define DGADC_CTRL1__DDR_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define DGADC_CTRL1__DDR_EN__RESET_VALUE 0x00000000U +/** @} */ +#define DGADC_CTRL1__TYPE uint32_t +#define DGADC_CTRL1__READ 0x0000003fU +#define DGADC_CTRL1__WRITE 0x0000003fU +#define DGADC_CTRL1__PRESERVED 0x00000000U +#define DGADC_CTRL1__RESET_VALUE 0x00000000U + +#endif /* __DGADC_CTRL1_MACRO__ */ + +/** @} end of ctrl1 */ + +/* macros for BlueprintGlobalNameSpace::DGADC_ch1_datapath_config */ +/** + * @defgroup at_apb_gadc_regs_core_ch1_datapath_config ch1_datapath_config + * @brief channel-1 offset and gain datpath parameters definitions. + * @{ + */ +#ifndef __DGADC_CH1_DATAPATH_CONFIG_MACRO__ +#define __DGADC_CH1_DATAPATH_CONFIG_MACRO__ + +/* macros for field gain */ +/** + * @defgroup at_apb_gadc_regs_core_gain_field gain_field + * @brief macros for field gain + * @details Q<0,12> gain number + * @{ + */ +#define DGADC_CH1_DATAPATH_CONFIG__GAIN__SHIFT 0 +#define DGADC_CH1_DATAPATH_CONFIG__GAIN__WIDTH 13 +#define DGADC_CH1_DATAPATH_CONFIG__GAIN__MASK 0x00001fffU +#define DGADC_CH1_DATAPATH_CONFIG__GAIN__READ(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH1_DATAPATH_CONFIG__GAIN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH1_DATAPATH_CONFIG__GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fffU) | ((uint32_t)(src) &\ + 0x00001fffU) +#define DGADC_CH1_DATAPATH_CONFIG__GAIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00001fffU))) +#define DGADC_CH1_DATAPATH_CONFIG__GAIN__RESET_VALUE 0x00000800U +/** @} */ + +/* macros for field gain_exp */ +/** + * @defgroup at_apb_gadc_regs_core_gain_exp_field gain_exp_field + * @brief macros for field gain_exp + * @details Q<4,0> gain exponent + * @{ + */ +#define DGADC_CH1_DATAPATH_CONFIG__GAIN_EXP__SHIFT 13 +#define DGADC_CH1_DATAPATH_CONFIG__GAIN_EXP__WIDTH 5 +#define DGADC_CH1_DATAPATH_CONFIG__GAIN_EXP__MASK 0x0003e000U +#define DGADC_CH1_DATAPATH_CONFIG__GAIN_EXP__READ(src) \ + (((uint32_t)(src)\ + & 0x0003e000U) >> 13) +#define DGADC_CH1_DATAPATH_CONFIG__GAIN_EXP__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0003e000U) +#define DGADC_CH1_DATAPATH_CONFIG__GAIN_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003e000U) | (((uint32_t)(src) <<\ + 13) & 0x0003e000U) +#define DGADC_CH1_DATAPATH_CONFIG__GAIN_EXP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0003e000U))) +#define DGADC_CH1_DATAPATH_CONFIG__GAIN_EXP__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field offset */ +/** + * @defgroup at_apb_gadc_regs_core_offset_field offset_field + * @brief macros for field offset + * @details Q<9,4> offset + * @{ + */ +#define DGADC_CH1_DATAPATH_CONFIG__OFFSET__SHIFT 18 +#define DGADC_CH1_DATAPATH_CONFIG__OFFSET__WIDTH 14 +#define DGADC_CH1_DATAPATH_CONFIG__OFFSET__MASK 0xfffc0000U +#define DGADC_CH1_DATAPATH_CONFIG__OFFSET__READ(src) \ + (((uint32_t)(src)\ + & 0xfffc0000U) >> 18) +#define DGADC_CH1_DATAPATH_CONFIG__OFFSET__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0xfffc0000U) +#define DGADC_CH1_DATAPATH_CONFIG__OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffc0000U) | (((uint32_t)(src) <<\ + 18) & 0xfffc0000U) +#define DGADC_CH1_DATAPATH_CONFIG__OFFSET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0xfffc0000U))) +#define DGADC_CH1_DATAPATH_CONFIG__OFFSET__RESET_VALUE 0x00000000U +/** @} */ +#define DGADC_CH1_DATAPATH_CONFIG__TYPE uint32_t +#define DGADC_CH1_DATAPATH_CONFIG__READ 0xffffffffU +#define DGADC_CH1_DATAPATH_CONFIG__WRITE 0xffffffffU +#define DGADC_CH1_DATAPATH_CONFIG__PRESERVED 0x00000000U +#define DGADC_CH1_DATAPATH_CONFIG__RESET_VALUE 0x00002800U + +#endif /* __DGADC_CH1_DATAPATH_CONFIG_MACRO__ */ + +/** @} end of ch1_datapath_config */ + +/* macros for BlueprintGlobalNameSpace::DGADC_ch2_datapath_config */ +/** + * @defgroup at_apb_gadc_regs_core_ch2_datapath_config ch2_datapath_config + * @brief channel-2 offset and gain datpath parameters definitions. + * @{ + */ +#ifndef __DGADC_CH2_DATAPATH_CONFIG_MACRO__ +#define __DGADC_CH2_DATAPATH_CONFIG_MACRO__ + +/* macros for field gain */ +/** + * @defgroup at_apb_gadc_regs_core_gain_field gain_field + * @brief macros for field gain + * @details Q<0,12> gain number + * @{ + */ +#define DGADC_CH2_DATAPATH_CONFIG__GAIN__SHIFT 0 +#define DGADC_CH2_DATAPATH_CONFIG__GAIN__WIDTH 13 +#define DGADC_CH2_DATAPATH_CONFIG__GAIN__MASK 0x00001fffU +#define DGADC_CH2_DATAPATH_CONFIG__GAIN__READ(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH2_DATAPATH_CONFIG__GAIN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH2_DATAPATH_CONFIG__GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fffU) | ((uint32_t)(src) &\ + 0x00001fffU) +#define DGADC_CH2_DATAPATH_CONFIG__GAIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00001fffU))) +#define DGADC_CH2_DATAPATH_CONFIG__GAIN__RESET_VALUE 0x00000800U +/** @} */ + +/* macros for field gain_exp */ +/** + * @defgroup at_apb_gadc_regs_core_gain_exp_field gain_exp_field + * @brief macros for field gain_exp + * @details Q<4,0> gain exponent + * @{ + */ +#define DGADC_CH2_DATAPATH_CONFIG__GAIN_EXP__SHIFT 13 +#define DGADC_CH2_DATAPATH_CONFIG__GAIN_EXP__WIDTH 5 +#define DGADC_CH2_DATAPATH_CONFIG__GAIN_EXP__MASK 0x0003e000U +#define DGADC_CH2_DATAPATH_CONFIG__GAIN_EXP__READ(src) \ + (((uint32_t)(src)\ + & 0x0003e000U) >> 13) +#define DGADC_CH2_DATAPATH_CONFIG__GAIN_EXP__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0003e000U) +#define DGADC_CH2_DATAPATH_CONFIG__GAIN_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003e000U) | (((uint32_t)(src) <<\ + 13) & 0x0003e000U) +#define DGADC_CH2_DATAPATH_CONFIG__GAIN_EXP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0003e000U))) +#define DGADC_CH2_DATAPATH_CONFIG__GAIN_EXP__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field offset */ +/** + * @defgroup at_apb_gadc_regs_core_offset_field offset_field + * @brief macros for field offset + * @details Q<9,4> offset + * @{ + */ +#define DGADC_CH2_DATAPATH_CONFIG__OFFSET__SHIFT 18 +#define DGADC_CH2_DATAPATH_CONFIG__OFFSET__WIDTH 14 +#define DGADC_CH2_DATAPATH_CONFIG__OFFSET__MASK 0xfffc0000U +#define DGADC_CH2_DATAPATH_CONFIG__OFFSET__READ(src) \ + (((uint32_t)(src)\ + & 0xfffc0000U) >> 18) +#define DGADC_CH2_DATAPATH_CONFIG__OFFSET__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0xfffc0000U) +#define DGADC_CH2_DATAPATH_CONFIG__OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffc0000U) | (((uint32_t)(src) <<\ + 18) & 0xfffc0000U) +#define DGADC_CH2_DATAPATH_CONFIG__OFFSET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0xfffc0000U))) +#define DGADC_CH2_DATAPATH_CONFIG__OFFSET__RESET_VALUE 0x00000000U +/** @} */ +#define DGADC_CH2_DATAPATH_CONFIG__TYPE uint32_t +#define DGADC_CH2_DATAPATH_CONFIG__READ 0xffffffffU +#define DGADC_CH2_DATAPATH_CONFIG__WRITE 0xffffffffU +#define DGADC_CH2_DATAPATH_CONFIG__PRESERVED 0x00000000U +#define DGADC_CH2_DATAPATH_CONFIG__RESET_VALUE 0x00002800U + +#endif /* __DGADC_CH2_DATAPATH_CONFIG_MACRO__ */ + +/** @} end of ch2_datapath_config */ + +/* macros for BlueprintGlobalNameSpace::DGADC_ch3_datapath_config */ +/** + * @defgroup at_apb_gadc_regs_core_ch3_datapath_config ch3_datapath_config + * @brief channel-3 offset and gain datpath parameters definitions. + * @{ + */ +#ifndef __DGADC_CH3_DATAPATH_CONFIG_MACRO__ +#define __DGADC_CH3_DATAPATH_CONFIG_MACRO__ + +/* macros for field gain */ +/** + * @defgroup at_apb_gadc_regs_core_gain_field gain_field + * @brief macros for field gain + * @details Q<0,12> gain number + * @{ + */ +#define DGADC_CH3_DATAPATH_CONFIG__GAIN__SHIFT 0 +#define DGADC_CH3_DATAPATH_CONFIG__GAIN__WIDTH 13 +#define DGADC_CH3_DATAPATH_CONFIG__GAIN__MASK 0x00001fffU +#define DGADC_CH3_DATAPATH_CONFIG__GAIN__READ(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH3_DATAPATH_CONFIG__GAIN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH3_DATAPATH_CONFIG__GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fffU) | ((uint32_t)(src) &\ + 0x00001fffU) +#define DGADC_CH3_DATAPATH_CONFIG__GAIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00001fffU))) +#define DGADC_CH3_DATAPATH_CONFIG__GAIN__RESET_VALUE 0x00000800U +/** @} */ + +/* macros for field gain_exp */ +/** + * @defgroup at_apb_gadc_regs_core_gain_exp_field gain_exp_field + * @brief macros for field gain_exp + * @details Q<4,0> gain exponent + * @{ + */ +#define DGADC_CH3_DATAPATH_CONFIG__GAIN_EXP__SHIFT 13 +#define DGADC_CH3_DATAPATH_CONFIG__GAIN_EXP__WIDTH 5 +#define DGADC_CH3_DATAPATH_CONFIG__GAIN_EXP__MASK 0x0003e000U +#define DGADC_CH3_DATAPATH_CONFIG__GAIN_EXP__READ(src) \ + (((uint32_t)(src)\ + & 0x0003e000U) >> 13) +#define DGADC_CH3_DATAPATH_CONFIG__GAIN_EXP__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0003e000U) +#define DGADC_CH3_DATAPATH_CONFIG__GAIN_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003e000U) | (((uint32_t)(src) <<\ + 13) & 0x0003e000U) +#define DGADC_CH3_DATAPATH_CONFIG__GAIN_EXP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0003e000U))) +#define DGADC_CH3_DATAPATH_CONFIG__GAIN_EXP__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field offset */ +/** + * @defgroup at_apb_gadc_regs_core_offset_field offset_field + * @brief macros for field offset + * @details Q<9,4> offset + * @{ + */ +#define DGADC_CH3_DATAPATH_CONFIG__OFFSET__SHIFT 18 +#define DGADC_CH3_DATAPATH_CONFIG__OFFSET__WIDTH 14 +#define DGADC_CH3_DATAPATH_CONFIG__OFFSET__MASK 0xfffc0000U +#define DGADC_CH3_DATAPATH_CONFIG__OFFSET__READ(src) \ + (((uint32_t)(src)\ + & 0xfffc0000U) >> 18) +#define DGADC_CH3_DATAPATH_CONFIG__OFFSET__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0xfffc0000U) +#define DGADC_CH3_DATAPATH_CONFIG__OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffc0000U) | (((uint32_t)(src) <<\ + 18) & 0xfffc0000U) +#define DGADC_CH3_DATAPATH_CONFIG__OFFSET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0xfffc0000U))) +#define DGADC_CH3_DATAPATH_CONFIG__OFFSET__RESET_VALUE 0x00000000U +/** @} */ +#define DGADC_CH3_DATAPATH_CONFIG__TYPE uint32_t +#define DGADC_CH3_DATAPATH_CONFIG__READ 0xffffffffU +#define DGADC_CH3_DATAPATH_CONFIG__WRITE 0xffffffffU +#define DGADC_CH3_DATAPATH_CONFIG__PRESERVED 0x00000000U +#define DGADC_CH3_DATAPATH_CONFIG__RESET_VALUE 0x00002800U + +#endif /* __DGADC_CH3_DATAPATH_CONFIG_MACRO__ */ + +/** @} end of ch3_datapath_config */ + +/* macros for BlueprintGlobalNameSpace::DGADC_ch4_datapath_config */ +/** + * @defgroup at_apb_gadc_regs_core_ch4_datapath_config ch4_datapath_config + * @brief channel-4 offset and gain datpath parameters definitions. + * @{ + */ +#ifndef __DGADC_CH4_DATAPATH_CONFIG_MACRO__ +#define __DGADC_CH4_DATAPATH_CONFIG_MACRO__ + +/* macros for field gain */ +/** + * @defgroup at_apb_gadc_regs_core_gain_field gain_field + * @brief macros for field gain + * @details Q<0,12> gain number + * @{ + */ +#define DGADC_CH4_DATAPATH_CONFIG__GAIN__SHIFT 0 +#define DGADC_CH4_DATAPATH_CONFIG__GAIN__WIDTH 13 +#define DGADC_CH4_DATAPATH_CONFIG__GAIN__MASK 0x00001fffU +#define DGADC_CH4_DATAPATH_CONFIG__GAIN__READ(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH4_DATAPATH_CONFIG__GAIN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH4_DATAPATH_CONFIG__GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fffU) | ((uint32_t)(src) &\ + 0x00001fffU) +#define DGADC_CH4_DATAPATH_CONFIG__GAIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00001fffU))) +#define DGADC_CH4_DATAPATH_CONFIG__GAIN__RESET_VALUE 0x00000800U +/** @} */ + +/* macros for field gain_exp */ +/** + * @defgroup at_apb_gadc_regs_core_gain_exp_field gain_exp_field + * @brief macros for field gain_exp + * @details Q<4,0> gain exponent + * @{ + */ +#define DGADC_CH4_DATAPATH_CONFIG__GAIN_EXP__SHIFT 13 +#define DGADC_CH4_DATAPATH_CONFIG__GAIN_EXP__WIDTH 5 +#define DGADC_CH4_DATAPATH_CONFIG__GAIN_EXP__MASK 0x0003e000U +#define DGADC_CH4_DATAPATH_CONFIG__GAIN_EXP__READ(src) \ + (((uint32_t)(src)\ + & 0x0003e000U) >> 13) +#define DGADC_CH4_DATAPATH_CONFIG__GAIN_EXP__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0003e000U) +#define DGADC_CH4_DATAPATH_CONFIG__GAIN_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003e000U) | (((uint32_t)(src) <<\ + 13) & 0x0003e000U) +#define DGADC_CH4_DATAPATH_CONFIG__GAIN_EXP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0003e000U))) +#define DGADC_CH4_DATAPATH_CONFIG__GAIN_EXP__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field offset */ +/** + * @defgroup at_apb_gadc_regs_core_offset_field offset_field + * @brief macros for field offset + * @details Q<9,4> offset + * @{ + */ +#define DGADC_CH4_DATAPATH_CONFIG__OFFSET__SHIFT 18 +#define DGADC_CH4_DATAPATH_CONFIG__OFFSET__WIDTH 14 +#define DGADC_CH4_DATAPATH_CONFIG__OFFSET__MASK 0xfffc0000U +#define DGADC_CH4_DATAPATH_CONFIG__OFFSET__READ(src) \ + (((uint32_t)(src)\ + & 0xfffc0000U) >> 18) +#define DGADC_CH4_DATAPATH_CONFIG__OFFSET__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0xfffc0000U) +#define DGADC_CH4_DATAPATH_CONFIG__OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffc0000U) | (((uint32_t)(src) <<\ + 18) & 0xfffc0000U) +#define DGADC_CH4_DATAPATH_CONFIG__OFFSET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0xfffc0000U))) +#define DGADC_CH4_DATAPATH_CONFIG__OFFSET__RESET_VALUE 0x00000000U +/** @} */ +#define DGADC_CH4_DATAPATH_CONFIG__TYPE uint32_t +#define DGADC_CH4_DATAPATH_CONFIG__READ 0xffffffffU +#define DGADC_CH4_DATAPATH_CONFIG__WRITE 0xffffffffU +#define DGADC_CH4_DATAPATH_CONFIG__PRESERVED 0x00000000U +#define DGADC_CH4_DATAPATH_CONFIG__RESET_VALUE 0x00002800U + +#endif /* __DGADC_CH4_DATAPATH_CONFIG_MACRO__ */ + +/** @} end of ch4_datapath_config */ + +/* macros for BlueprintGlobalNameSpace::DGADC_ch5_datapath_config */ +/** + * @defgroup at_apb_gadc_regs_core_ch5_datapath_config ch5_datapath_config + * @brief channel-5 offset and gain datpath parameters definitions. + * @{ + */ +#ifndef __DGADC_CH5_DATAPATH_CONFIG_MACRO__ +#define __DGADC_CH5_DATAPATH_CONFIG_MACRO__ + +/* macros for field gain */ +/** + * @defgroup at_apb_gadc_regs_core_gain_field gain_field + * @brief macros for field gain + * @details Q<0,12> gain number + * @{ + */ +#define DGADC_CH5_DATAPATH_CONFIG__GAIN__SHIFT 0 +#define DGADC_CH5_DATAPATH_CONFIG__GAIN__WIDTH 13 +#define DGADC_CH5_DATAPATH_CONFIG__GAIN__MASK 0x00001fffU +#define DGADC_CH5_DATAPATH_CONFIG__GAIN__READ(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH5_DATAPATH_CONFIG__GAIN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH5_DATAPATH_CONFIG__GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fffU) | ((uint32_t)(src) &\ + 0x00001fffU) +#define DGADC_CH5_DATAPATH_CONFIG__GAIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00001fffU))) +#define DGADC_CH5_DATAPATH_CONFIG__GAIN__RESET_VALUE 0x00000800U +/** @} */ + +/* macros for field gain_exp */ +/** + * @defgroup at_apb_gadc_regs_core_gain_exp_field gain_exp_field + * @brief macros for field gain_exp + * @details Q<4,0> gain exponent + * @{ + */ +#define DGADC_CH5_DATAPATH_CONFIG__GAIN_EXP__SHIFT 13 +#define DGADC_CH5_DATAPATH_CONFIG__GAIN_EXP__WIDTH 5 +#define DGADC_CH5_DATAPATH_CONFIG__GAIN_EXP__MASK 0x0003e000U +#define DGADC_CH5_DATAPATH_CONFIG__GAIN_EXP__READ(src) \ + (((uint32_t)(src)\ + & 0x0003e000U) >> 13) +#define DGADC_CH5_DATAPATH_CONFIG__GAIN_EXP__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0003e000U) +#define DGADC_CH5_DATAPATH_CONFIG__GAIN_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003e000U) | (((uint32_t)(src) <<\ + 13) & 0x0003e000U) +#define DGADC_CH5_DATAPATH_CONFIG__GAIN_EXP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0003e000U))) +#define DGADC_CH5_DATAPATH_CONFIG__GAIN_EXP__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field offset */ +/** + * @defgroup at_apb_gadc_regs_core_offset_field offset_field + * @brief macros for field offset + * @details Q<9,4> offset + * @{ + */ +#define DGADC_CH5_DATAPATH_CONFIG__OFFSET__SHIFT 18 +#define DGADC_CH5_DATAPATH_CONFIG__OFFSET__WIDTH 14 +#define DGADC_CH5_DATAPATH_CONFIG__OFFSET__MASK 0xfffc0000U +#define DGADC_CH5_DATAPATH_CONFIG__OFFSET__READ(src) \ + (((uint32_t)(src)\ + & 0xfffc0000U) >> 18) +#define DGADC_CH5_DATAPATH_CONFIG__OFFSET__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0xfffc0000U) +#define DGADC_CH5_DATAPATH_CONFIG__OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffc0000U) | (((uint32_t)(src) <<\ + 18) & 0xfffc0000U) +#define DGADC_CH5_DATAPATH_CONFIG__OFFSET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0xfffc0000U))) +#define DGADC_CH5_DATAPATH_CONFIG__OFFSET__RESET_VALUE 0x00000000U +/** @} */ +#define DGADC_CH5_DATAPATH_CONFIG__TYPE uint32_t +#define DGADC_CH5_DATAPATH_CONFIG__READ 0xffffffffU +#define DGADC_CH5_DATAPATH_CONFIG__WRITE 0xffffffffU +#define DGADC_CH5_DATAPATH_CONFIG__PRESERVED 0x00000000U +#define DGADC_CH5_DATAPATH_CONFIG__RESET_VALUE 0x00002800U + +#endif /* __DGADC_CH5_DATAPATH_CONFIG_MACRO__ */ + +/** @} end of ch5_datapath_config */ + +/* macros for BlueprintGlobalNameSpace::DGADC_ch6_datapath_config */ +/** + * @defgroup at_apb_gadc_regs_core_ch6_datapath_config ch6_datapath_config + * @brief channel-6 offset and gain datpath parameters definitions. + * @{ + */ +#ifndef __DGADC_CH6_DATAPATH_CONFIG_MACRO__ +#define __DGADC_CH6_DATAPATH_CONFIG_MACRO__ + +/* macros for field gain */ +/** + * @defgroup at_apb_gadc_regs_core_gain_field gain_field + * @brief macros for field gain + * @details Q<0,12> gain number + * @{ + */ +#define DGADC_CH6_DATAPATH_CONFIG__GAIN__SHIFT 0 +#define DGADC_CH6_DATAPATH_CONFIG__GAIN__WIDTH 13 +#define DGADC_CH6_DATAPATH_CONFIG__GAIN__MASK 0x00001fffU +#define DGADC_CH6_DATAPATH_CONFIG__GAIN__READ(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH6_DATAPATH_CONFIG__GAIN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH6_DATAPATH_CONFIG__GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fffU) | ((uint32_t)(src) &\ + 0x00001fffU) +#define DGADC_CH6_DATAPATH_CONFIG__GAIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00001fffU))) +#define DGADC_CH6_DATAPATH_CONFIG__GAIN__RESET_VALUE 0x00000800U +/** @} */ + +/* macros for field gain_exp */ +/** + * @defgroup at_apb_gadc_regs_core_gain_exp_field gain_exp_field + * @brief macros for field gain_exp + * @details Q<4,0> gain exponent + * @{ + */ +#define DGADC_CH6_DATAPATH_CONFIG__GAIN_EXP__SHIFT 13 +#define DGADC_CH6_DATAPATH_CONFIG__GAIN_EXP__WIDTH 5 +#define DGADC_CH6_DATAPATH_CONFIG__GAIN_EXP__MASK 0x0003e000U +#define DGADC_CH6_DATAPATH_CONFIG__GAIN_EXP__READ(src) \ + (((uint32_t)(src)\ + & 0x0003e000U) >> 13) +#define DGADC_CH6_DATAPATH_CONFIG__GAIN_EXP__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0003e000U) +#define DGADC_CH6_DATAPATH_CONFIG__GAIN_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003e000U) | (((uint32_t)(src) <<\ + 13) & 0x0003e000U) +#define DGADC_CH6_DATAPATH_CONFIG__GAIN_EXP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0003e000U))) +#define DGADC_CH6_DATAPATH_CONFIG__GAIN_EXP__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field offset */ +/** + * @defgroup at_apb_gadc_regs_core_offset_field offset_field + * @brief macros for field offset + * @details Q<9,4> offset + * @{ + */ +#define DGADC_CH6_DATAPATH_CONFIG__OFFSET__SHIFT 18 +#define DGADC_CH6_DATAPATH_CONFIG__OFFSET__WIDTH 14 +#define DGADC_CH6_DATAPATH_CONFIG__OFFSET__MASK 0xfffc0000U +#define DGADC_CH6_DATAPATH_CONFIG__OFFSET__READ(src) \ + (((uint32_t)(src)\ + & 0xfffc0000U) >> 18) +#define DGADC_CH6_DATAPATH_CONFIG__OFFSET__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0xfffc0000U) +#define DGADC_CH6_DATAPATH_CONFIG__OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffc0000U) | (((uint32_t)(src) <<\ + 18) & 0xfffc0000U) +#define DGADC_CH6_DATAPATH_CONFIG__OFFSET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0xfffc0000U))) +#define DGADC_CH6_DATAPATH_CONFIG__OFFSET__RESET_VALUE 0x00000000U +/** @} */ +#define DGADC_CH6_DATAPATH_CONFIG__TYPE uint32_t +#define DGADC_CH6_DATAPATH_CONFIG__READ 0xffffffffU +#define DGADC_CH6_DATAPATH_CONFIG__WRITE 0xffffffffU +#define DGADC_CH6_DATAPATH_CONFIG__PRESERVED 0x00000000U +#define DGADC_CH6_DATAPATH_CONFIG__RESET_VALUE 0x00002800U + +#endif /* __DGADC_CH6_DATAPATH_CONFIG_MACRO__ */ + +/** @} end of ch6_datapath_config */ + +/* macros for BlueprintGlobalNameSpace::DGADC_ch7_datapath_config */ +/** + * @defgroup at_apb_gadc_regs_core_ch7_datapath_config ch7_datapath_config + * @brief channel-7 offset and gain datpath parameters definitions. + * @{ + */ +#ifndef __DGADC_CH7_DATAPATH_CONFIG_MACRO__ +#define __DGADC_CH7_DATAPATH_CONFIG_MACRO__ + +/* macros for field gain */ +/** + * @defgroup at_apb_gadc_regs_core_gain_field gain_field + * @brief macros for field gain + * @details Q<0,12> gain number + * @{ + */ +#define DGADC_CH7_DATAPATH_CONFIG__GAIN__SHIFT 0 +#define DGADC_CH7_DATAPATH_CONFIG__GAIN__WIDTH 13 +#define DGADC_CH7_DATAPATH_CONFIG__GAIN__MASK 0x00001fffU +#define DGADC_CH7_DATAPATH_CONFIG__GAIN__READ(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH7_DATAPATH_CONFIG__GAIN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH7_DATAPATH_CONFIG__GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fffU) | ((uint32_t)(src) &\ + 0x00001fffU) +#define DGADC_CH7_DATAPATH_CONFIG__GAIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00001fffU))) +#define DGADC_CH7_DATAPATH_CONFIG__GAIN__RESET_VALUE 0x00000800U +/** @} */ + +/* macros for field gain_exp */ +/** + * @defgroup at_apb_gadc_regs_core_gain_exp_field gain_exp_field + * @brief macros for field gain_exp + * @details Q<4,0> gain exponent + * @{ + */ +#define DGADC_CH7_DATAPATH_CONFIG__GAIN_EXP__SHIFT 13 +#define DGADC_CH7_DATAPATH_CONFIG__GAIN_EXP__WIDTH 5 +#define DGADC_CH7_DATAPATH_CONFIG__GAIN_EXP__MASK 0x0003e000U +#define DGADC_CH7_DATAPATH_CONFIG__GAIN_EXP__READ(src) \ + (((uint32_t)(src)\ + & 0x0003e000U) >> 13) +#define DGADC_CH7_DATAPATH_CONFIG__GAIN_EXP__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0003e000U) +#define DGADC_CH7_DATAPATH_CONFIG__GAIN_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003e000U) | (((uint32_t)(src) <<\ + 13) & 0x0003e000U) +#define DGADC_CH7_DATAPATH_CONFIG__GAIN_EXP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0003e000U))) +#define DGADC_CH7_DATAPATH_CONFIG__GAIN_EXP__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field offset */ +/** + * @defgroup at_apb_gadc_regs_core_offset_field offset_field + * @brief macros for field offset + * @details Q<9,4> offset + * @{ + */ +#define DGADC_CH7_DATAPATH_CONFIG__OFFSET__SHIFT 18 +#define DGADC_CH7_DATAPATH_CONFIG__OFFSET__WIDTH 14 +#define DGADC_CH7_DATAPATH_CONFIG__OFFSET__MASK 0xfffc0000U +#define DGADC_CH7_DATAPATH_CONFIG__OFFSET__READ(src) \ + (((uint32_t)(src)\ + & 0xfffc0000U) >> 18) +#define DGADC_CH7_DATAPATH_CONFIG__OFFSET__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0xfffc0000U) +#define DGADC_CH7_DATAPATH_CONFIG__OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffc0000U) | (((uint32_t)(src) <<\ + 18) & 0xfffc0000U) +#define DGADC_CH7_DATAPATH_CONFIG__OFFSET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0xfffc0000U))) +#define DGADC_CH7_DATAPATH_CONFIG__OFFSET__RESET_VALUE 0x00000000U +/** @} */ +#define DGADC_CH7_DATAPATH_CONFIG__TYPE uint32_t +#define DGADC_CH7_DATAPATH_CONFIG__READ 0xffffffffU +#define DGADC_CH7_DATAPATH_CONFIG__WRITE 0xffffffffU +#define DGADC_CH7_DATAPATH_CONFIG__PRESERVED 0x00000000U +#define DGADC_CH7_DATAPATH_CONFIG__RESET_VALUE 0x00002800U + +#endif /* __DGADC_CH7_DATAPATH_CONFIG_MACRO__ */ + +/** @} end of ch7_datapath_config */ + +/* macros for BlueprintGlobalNameSpace::DGADC_ch8_datapath_config */ +/** + * @defgroup at_apb_gadc_regs_core_ch8_datapath_config ch8_datapath_config + * @brief channel-8 offset and gain datpath parameters definitions. + * @{ + */ +#ifndef __DGADC_CH8_DATAPATH_CONFIG_MACRO__ +#define __DGADC_CH8_DATAPATH_CONFIG_MACRO__ + +/* macros for field gain */ +/** + * @defgroup at_apb_gadc_regs_core_gain_field gain_field + * @brief macros for field gain + * @details Q<0,12> gain number + * @{ + */ +#define DGADC_CH8_DATAPATH_CONFIG__GAIN__SHIFT 0 +#define DGADC_CH8_DATAPATH_CONFIG__GAIN__WIDTH 13 +#define DGADC_CH8_DATAPATH_CONFIG__GAIN__MASK 0x00001fffU +#define DGADC_CH8_DATAPATH_CONFIG__GAIN__READ(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH8_DATAPATH_CONFIG__GAIN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH8_DATAPATH_CONFIG__GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fffU) | ((uint32_t)(src) &\ + 0x00001fffU) +#define DGADC_CH8_DATAPATH_CONFIG__GAIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00001fffU))) +#define DGADC_CH8_DATAPATH_CONFIG__GAIN__RESET_VALUE 0x00000800U +/** @} */ + +/* macros for field gain_exp */ +/** + * @defgroup at_apb_gadc_regs_core_gain_exp_field gain_exp_field + * @brief macros for field gain_exp + * @details Q<4,0> gain exponent + * @{ + */ +#define DGADC_CH8_DATAPATH_CONFIG__GAIN_EXP__SHIFT 13 +#define DGADC_CH8_DATAPATH_CONFIG__GAIN_EXP__WIDTH 5 +#define DGADC_CH8_DATAPATH_CONFIG__GAIN_EXP__MASK 0x0003e000U +#define DGADC_CH8_DATAPATH_CONFIG__GAIN_EXP__READ(src) \ + (((uint32_t)(src)\ + & 0x0003e000U) >> 13) +#define DGADC_CH8_DATAPATH_CONFIG__GAIN_EXP__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0003e000U) +#define DGADC_CH8_DATAPATH_CONFIG__GAIN_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003e000U) | (((uint32_t)(src) <<\ + 13) & 0x0003e000U) +#define DGADC_CH8_DATAPATH_CONFIG__GAIN_EXP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0003e000U))) +#define DGADC_CH8_DATAPATH_CONFIG__GAIN_EXP__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field offset */ +/** + * @defgroup at_apb_gadc_regs_core_offset_field offset_field + * @brief macros for field offset + * @details Q<9,4> offset + * @{ + */ +#define DGADC_CH8_DATAPATH_CONFIG__OFFSET__SHIFT 18 +#define DGADC_CH8_DATAPATH_CONFIG__OFFSET__WIDTH 14 +#define DGADC_CH8_DATAPATH_CONFIG__OFFSET__MASK 0xfffc0000U +#define DGADC_CH8_DATAPATH_CONFIG__OFFSET__READ(src) \ + (((uint32_t)(src)\ + & 0xfffc0000U) >> 18) +#define DGADC_CH8_DATAPATH_CONFIG__OFFSET__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0xfffc0000U) +#define DGADC_CH8_DATAPATH_CONFIG__OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffc0000U) | (((uint32_t)(src) <<\ + 18) & 0xfffc0000U) +#define DGADC_CH8_DATAPATH_CONFIG__OFFSET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0xfffc0000U))) +#define DGADC_CH8_DATAPATH_CONFIG__OFFSET__RESET_VALUE 0x00000000U +/** @} */ +#define DGADC_CH8_DATAPATH_CONFIG__TYPE uint32_t +#define DGADC_CH8_DATAPATH_CONFIG__READ 0xffffffffU +#define DGADC_CH8_DATAPATH_CONFIG__WRITE 0xffffffffU +#define DGADC_CH8_DATAPATH_CONFIG__PRESERVED 0x00000000U +#define DGADC_CH8_DATAPATH_CONFIG__RESET_VALUE 0x00002800U + +#endif /* __DGADC_CH8_DATAPATH_CONFIG_MACRO__ */ + +/** @} end of ch8_datapath_config */ + +/* macros for BlueprintGlobalNameSpace::DGADC_ch9_datapath_config */ +/** + * @defgroup at_apb_gadc_regs_core_ch9_datapath_config ch9_datapath_config + * @brief channel-9 offset and gain datpath parameters definitions. + * @{ + */ +#ifndef __DGADC_CH9_DATAPATH_CONFIG_MACRO__ +#define __DGADC_CH9_DATAPATH_CONFIG_MACRO__ + +/* macros for field gain */ +/** + * @defgroup at_apb_gadc_regs_core_gain_field gain_field + * @brief macros for field gain + * @details Q<0,12> gain number + * @{ + */ +#define DGADC_CH9_DATAPATH_CONFIG__GAIN__SHIFT 0 +#define DGADC_CH9_DATAPATH_CONFIG__GAIN__WIDTH 13 +#define DGADC_CH9_DATAPATH_CONFIG__GAIN__MASK 0x00001fffU +#define DGADC_CH9_DATAPATH_CONFIG__GAIN__READ(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH9_DATAPATH_CONFIG__GAIN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH9_DATAPATH_CONFIG__GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fffU) | ((uint32_t)(src) &\ + 0x00001fffU) +#define DGADC_CH9_DATAPATH_CONFIG__GAIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00001fffU))) +#define DGADC_CH9_DATAPATH_CONFIG__GAIN__RESET_VALUE 0x00000800U +/** @} */ + +/* macros for field gain_exp */ +/** + * @defgroup at_apb_gadc_regs_core_gain_exp_field gain_exp_field + * @brief macros for field gain_exp + * @details Q<4,0> gain exponent + * @{ + */ +#define DGADC_CH9_DATAPATH_CONFIG__GAIN_EXP__SHIFT 13 +#define DGADC_CH9_DATAPATH_CONFIG__GAIN_EXP__WIDTH 5 +#define DGADC_CH9_DATAPATH_CONFIG__GAIN_EXP__MASK 0x0003e000U +#define DGADC_CH9_DATAPATH_CONFIG__GAIN_EXP__READ(src) \ + (((uint32_t)(src)\ + & 0x0003e000U) >> 13) +#define DGADC_CH9_DATAPATH_CONFIG__GAIN_EXP__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0003e000U) +#define DGADC_CH9_DATAPATH_CONFIG__GAIN_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003e000U) | (((uint32_t)(src) <<\ + 13) & 0x0003e000U) +#define DGADC_CH9_DATAPATH_CONFIG__GAIN_EXP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0003e000U))) +#define DGADC_CH9_DATAPATH_CONFIG__GAIN_EXP__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field offset */ +/** + * @defgroup at_apb_gadc_regs_core_offset_field offset_field + * @brief macros for field offset + * @details Q<9,4> offset + * @{ + */ +#define DGADC_CH9_DATAPATH_CONFIG__OFFSET__SHIFT 18 +#define DGADC_CH9_DATAPATH_CONFIG__OFFSET__WIDTH 14 +#define DGADC_CH9_DATAPATH_CONFIG__OFFSET__MASK 0xfffc0000U +#define DGADC_CH9_DATAPATH_CONFIG__OFFSET__READ(src) \ + (((uint32_t)(src)\ + & 0xfffc0000U) >> 18) +#define DGADC_CH9_DATAPATH_CONFIG__OFFSET__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0xfffc0000U) +#define DGADC_CH9_DATAPATH_CONFIG__OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffc0000U) | (((uint32_t)(src) <<\ + 18) & 0xfffc0000U) +#define DGADC_CH9_DATAPATH_CONFIG__OFFSET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0xfffc0000U))) +#define DGADC_CH9_DATAPATH_CONFIG__OFFSET__RESET_VALUE 0x00000000U +/** @} */ +#define DGADC_CH9_DATAPATH_CONFIG__TYPE uint32_t +#define DGADC_CH9_DATAPATH_CONFIG__READ 0xffffffffU +#define DGADC_CH9_DATAPATH_CONFIG__WRITE 0xffffffffU +#define DGADC_CH9_DATAPATH_CONFIG__PRESERVED 0x00000000U +#define DGADC_CH9_DATAPATH_CONFIG__RESET_VALUE 0x00002800U + +#endif /* __DGADC_CH9_DATAPATH_CONFIG_MACRO__ */ + +/** @} end of ch9_datapath_config */ + +/* macros for BlueprintGlobalNameSpace::DGADC_ch10_datapath_config */ +/** + * @defgroup at_apb_gadc_regs_core_ch10_datapath_config ch10_datapath_config + * @brief channel-10 offset and gain datpath parameters definitions. + * @{ + */ +#ifndef __DGADC_CH10_DATAPATH_CONFIG_MACRO__ +#define __DGADC_CH10_DATAPATH_CONFIG_MACRO__ + +/* macros for field gain */ +/** + * @defgroup at_apb_gadc_regs_core_gain_field gain_field + * @brief macros for field gain + * @details Q<0,12> gain number + * @{ + */ +#define DGADC_CH10_DATAPATH_CONFIG__GAIN__SHIFT 0 +#define DGADC_CH10_DATAPATH_CONFIG__GAIN__WIDTH 13 +#define DGADC_CH10_DATAPATH_CONFIG__GAIN__MASK 0x00001fffU +#define DGADC_CH10_DATAPATH_CONFIG__GAIN__READ(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH10_DATAPATH_CONFIG__GAIN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH10_DATAPATH_CONFIG__GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fffU) | ((uint32_t)(src) &\ + 0x00001fffU) +#define DGADC_CH10_DATAPATH_CONFIG__GAIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00001fffU))) +#define DGADC_CH10_DATAPATH_CONFIG__GAIN__RESET_VALUE 0x00000800U +/** @} */ + +/* macros for field gain_exp */ +/** + * @defgroup at_apb_gadc_regs_core_gain_exp_field gain_exp_field + * @brief macros for field gain_exp + * @details Q<4,0> gain exponent + * @{ + */ +#define DGADC_CH10_DATAPATH_CONFIG__GAIN_EXP__SHIFT 13 +#define DGADC_CH10_DATAPATH_CONFIG__GAIN_EXP__WIDTH 5 +#define DGADC_CH10_DATAPATH_CONFIG__GAIN_EXP__MASK 0x0003e000U +#define DGADC_CH10_DATAPATH_CONFIG__GAIN_EXP__READ(src) \ + (((uint32_t)(src)\ + & 0x0003e000U) >> 13) +#define DGADC_CH10_DATAPATH_CONFIG__GAIN_EXP__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0003e000U) +#define DGADC_CH10_DATAPATH_CONFIG__GAIN_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003e000U) | (((uint32_t)(src) <<\ + 13) & 0x0003e000U) +#define DGADC_CH10_DATAPATH_CONFIG__GAIN_EXP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0003e000U))) +#define DGADC_CH10_DATAPATH_CONFIG__GAIN_EXP__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field offset */ +/** + * @defgroup at_apb_gadc_regs_core_offset_field offset_field + * @brief macros for field offset + * @details Q<9,4> offset + * @{ + */ +#define DGADC_CH10_DATAPATH_CONFIG__OFFSET__SHIFT 18 +#define DGADC_CH10_DATAPATH_CONFIG__OFFSET__WIDTH 14 +#define DGADC_CH10_DATAPATH_CONFIG__OFFSET__MASK 0xfffc0000U +#define DGADC_CH10_DATAPATH_CONFIG__OFFSET__READ(src) \ + (((uint32_t)(src)\ + & 0xfffc0000U) >> 18) +#define DGADC_CH10_DATAPATH_CONFIG__OFFSET__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0xfffc0000U) +#define DGADC_CH10_DATAPATH_CONFIG__OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffc0000U) | (((uint32_t)(src) <<\ + 18) & 0xfffc0000U) +#define DGADC_CH10_DATAPATH_CONFIG__OFFSET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0xfffc0000U))) +#define DGADC_CH10_DATAPATH_CONFIG__OFFSET__RESET_VALUE 0x00000000U +/** @} */ +#define DGADC_CH10_DATAPATH_CONFIG__TYPE uint32_t +#define DGADC_CH10_DATAPATH_CONFIG__READ 0xffffffffU +#define DGADC_CH10_DATAPATH_CONFIG__WRITE 0xffffffffU +#define DGADC_CH10_DATAPATH_CONFIG__PRESERVED 0x00000000U +#define DGADC_CH10_DATAPATH_CONFIG__RESET_VALUE 0x00002800U + +#endif /* __DGADC_CH10_DATAPATH_CONFIG_MACRO__ */ + +/** @} end of ch10_datapath_config */ + +/* macros for BlueprintGlobalNameSpace::DGADC_ch11_datapath_config */ +/** + * @defgroup at_apb_gadc_regs_core_ch11_datapath_config ch11_datapath_config + * @brief channel-11 offset and gain datpath parameters definitions. + * @{ + */ +#ifndef __DGADC_CH11_DATAPATH_CONFIG_MACRO__ +#define __DGADC_CH11_DATAPATH_CONFIG_MACRO__ + +/* macros for field gain */ +/** + * @defgroup at_apb_gadc_regs_core_gain_field gain_field + * @brief macros for field gain + * @details Q<0,12> gain number + * @{ + */ +#define DGADC_CH11_DATAPATH_CONFIG__GAIN__SHIFT 0 +#define DGADC_CH11_DATAPATH_CONFIG__GAIN__WIDTH 13 +#define DGADC_CH11_DATAPATH_CONFIG__GAIN__MASK 0x00001fffU +#define DGADC_CH11_DATAPATH_CONFIG__GAIN__READ(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH11_DATAPATH_CONFIG__GAIN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH11_DATAPATH_CONFIG__GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fffU) | ((uint32_t)(src) &\ + 0x00001fffU) +#define DGADC_CH11_DATAPATH_CONFIG__GAIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00001fffU))) +#define DGADC_CH11_DATAPATH_CONFIG__GAIN__RESET_VALUE 0x00000800U +/** @} */ + +/* macros for field gain_exp */ +/** + * @defgroup at_apb_gadc_regs_core_gain_exp_field gain_exp_field + * @brief macros for field gain_exp + * @details Q<4,0> gain exponent + * @{ + */ +#define DGADC_CH11_DATAPATH_CONFIG__GAIN_EXP__SHIFT 13 +#define DGADC_CH11_DATAPATH_CONFIG__GAIN_EXP__WIDTH 5 +#define DGADC_CH11_DATAPATH_CONFIG__GAIN_EXP__MASK 0x0003e000U +#define DGADC_CH11_DATAPATH_CONFIG__GAIN_EXP__READ(src) \ + (((uint32_t)(src)\ + & 0x0003e000U) >> 13) +#define DGADC_CH11_DATAPATH_CONFIG__GAIN_EXP__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0003e000U) +#define DGADC_CH11_DATAPATH_CONFIG__GAIN_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003e000U) | (((uint32_t)(src) <<\ + 13) & 0x0003e000U) +#define DGADC_CH11_DATAPATH_CONFIG__GAIN_EXP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0003e000U))) +#define DGADC_CH11_DATAPATH_CONFIG__GAIN_EXP__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field offset */ +/** + * @defgroup at_apb_gadc_regs_core_offset_field offset_field + * @brief macros for field offset + * @details Q<9,4> offset + * @{ + */ +#define DGADC_CH11_DATAPATH_CONFIG__OFFSET__SHIFT 18 +#define DGADC_CH11_DATAPATH_CONFIG__OFFSET__WIDTH 14 +#define DGADC_CH11_DATAPATH_CONFIG__OFFSET__MASK 0xfffc0000U +#define DGADC_CH11_DATAPATH_CONFIG__OFFSET__READ(src) \ + (((uint32_t)(src)\ + & 0xfffc0000U) >> 18) +#define DGADC_CH11_DATAPATH_CONFIG__OFFSET__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0xfffc0000U) +#define DGADC_CH11_DATAPATH_CONFIG__OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffc0000U) | (((uint32_t)(src) <<\ + 18) & 0xfffc0000U) +#define DGADC_CH11_DATAPATH_CONFIG__OFFSET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0xfffc0000U))) +#define DGADC_CH11_DATAPATH_CONFIG__OFFSET__RESET_VALUE 0x00000000U +/** @} */ +#define DGADC_CH11_DATAPATH_CONFIG__TYPE uint32_t +#define DGADC_CH11_DATAPATH_CONFIG__READ 0xffffffffU +#define DGADC_CH11_DATAPATH_CONFIG__WRITE 0xffffffffU +#define DGADC_CH11_DATAPATH_CONFIG__PRESERVED 0x00000000U +#define DGADC_CH11_DATAPATH_CONFIG__RESET_VALUE 0x00002800U + +#endif /* __DGADC_CH11_DATAPATH_CONFIG_MACRO__ */ + +/** @} end of ch11_datapath_config */ + +/* macros for BlueprintGlobalNameSpace::DGADC_ch12_datapath_config */ +/** + * @defgroup at_apb_gadc_regs_core_ch12_datapath_config ch12_datapath_config + * @brief channel-12 offset and gain datpath parameters applied to unused channels 0,13,14 by defaults definitions. + * @{ + */ +#ifndef __DGADC_CH12_DATAPATH_CONFIG_MACRO__ +#define __DGADC_CH12_DATAPATH_CONFIG_MACRO__ + +/* macros for field gain */ +/** + * @defgroup at_apb_gadc_regs_core_gain_field gain_field + * @brief macros for field gain + * @details Q<0,12> gain number + * @{ + */ +#define DGADC_CH12_DATAPATH_CONFIG__GAIN__SHIFT 0 +#define DGADC_CH12_DATAPATH_CONFIG__GAIN__WIDTH 13 +#define DGADC_CH12_DATAPATH_CONFIG__GAIN__MASK 0x00001fffU +#define DGADC_CH12_DATAPATH_CONFIG__GAIN__READ(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH12_DATAPATH_CONFIG__GAIN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define DGADC_CH12_DATAPATH_CONFIG__GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fffU) | ((uint32_t)(src) &\ + 0x00001fffU) +#define DGADC_CH12_DATAPATH_CONFIG__GAIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00001fffU))) +#define DGADC_CH12_DATAPATH_CONFIG__GAIN__RESET_VALUE 0x00000800U +/** @} */ + +/* macros for field gain_exp */ +/** + * @defgroup at_apb_gadc_regs_core_gain_exp_field gain_exp_field + * @brief macros for field gain_exp + * @details Q<4,0> gain exponent + * @{ + */ +#define DGADC_CH12_DATAPATH_CONFIG__GAIN_EXP__SHIFT 13 +#define DGADC_CH12_DATAPATH_CONFIG__GAIN_EXP__WIDTH 5 +#define DGADC_CH12_DATAPATH_CONFIG__GAIN_EXP__MASK 0x0003e000U +#define DGADC_CH12_DATAPATH_CONFIG__GAIN_EXP__READ(src) \ + (((uint32_t)(src)\ + & 0x0003e000U) >> 13) +#define DGADC_CH12_DATAPATH_CONFIG__GAIN_EXP__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0003e000U) +#define DGADC_CH12_DATAPATH_CONFIG__GAIN_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003e000U) | (((uint32_t)(src) <<\ + 13) & 0x0003e000U) +#define DGADC_CH12_DATAPATH_CONFIG__GAIN_EXP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0003e000U))) +#define DGADC_CH12_DATAPATH_CONFIG__GAIN_EXP__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field offset */ +/** + * @defgroup at_apb_gadc_regs_core_offset_field offset_field + * @brief macros for field offset + * @details Q<9,4> offset + * @{ + */ +#define DGADC_CH12_DATAPATH_CONFIG__OFFSET__SHIFT 18 +#define DGADC_CH12_DATAPATH_CONFIG__OFFSET__WIDTH 14 +#define DGADC_CH12_DATAPATH_CONFIG__OFFSET__MASK 0xfffc0000U +#define DGADC_CH12_DATAPATH_CONFIG__OFFSET__READ(src) \ + (((uint32_t)(src)\ + & 0xfffc0000U) >> 18) +#define DGADC_CH12_DATAPATH_CONFIG__OFFSET__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0xfffc0000U) +#define DGADC_CH12_DATAPATH_CONFIG__OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffc0000U) | (((uint32_t)(src) <<\ + 18) & 0xfffc0000U) +#define DGADC_CH12_DATAPATH_CONFIG__OFFSET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0xfffc0000U))) +#define DGADC_CH12_DATAPATH_CONFIG__OFFSET__RESET_VALUE 0x00000000U +/** @} */ +#define DGADC_CH12_DATAPATH_CONFIG__TYPE uint32_t +#define DGADC_CH12_DATAPATH_CONFIG__READ 0xffffffffU +#define DGADC_CH12_DATAPATH_CONFIG__WRITE 0xffffffffU +#define DGADC_CH12_DATAPATH_CONFIG__PRESERVED 0x00000000U +#define DGADC_CH12_DATAPATH_CONFIG__RESET_VALUE 0x00002800U + +#endif /* __DGADC_CH12_DATAPATH_CONFIG_MACRO__ */ + +/** @} end of ch12_datapath_config */ + +/* macros for BlueprintGlobalNameSpace::DGADC_gain_config0 */ +/** + * @defgroup at_apb_gadc_regs_core_gain_config0 gain_config0 + * @brief channels 1-10 gain settings selection definitions. + * @{ + */ +#ifndef __DGADC_GAIN_CONFIG0_MACRO__ +#define __DGADC_GAIN_CONFIG0_MACRO__ + +/* macros for field ch1_gain_sel */ +/** + * @defgroup at_apb_gadc_regs_core_ch1_gain_sel_field ch1_gain_sel_field + * @brief macros for field ch1_gain_sel + * @details channel-1 gain settings + * @{ + */ +#define DGADC_GAIN_CONFIG0__CH1_GAIN_SEL__SHIFT 0 +#define DGADC_GAIN_CONFIG0__CH1_GAIN_SEL__WIDTH 3 +#define DGADC_GAIN_CONFIG0__CH1_GAIN_SEL__MASK 0x00000007U +#define DGADC_GAIN_CONFIG0__CH1_GAIN_SEL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define DGADC_GAIN_CONFIG0__CH1_GAIN_SEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define DGADC_GAIN_CONFIG0__CH1_GAIN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define DGADC_GAIN_CONFIG0__CH1_GAIN_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define DGADC_GAIN_CONFIG0__CH1_GAIN_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch2_gain_sel */ +/** + * @defgroup at_apb_gadc_regs_core_ch2_gain_sel_field ch2_gain_sel_field + * @brief macros for field ch2_gain_sel + * @details channel-2 gain settings + * @{ + */ +#define DGADC_GAIN_CONFIG0__CH2_GAIN_SEL__SHIFT 3 +#define DGADC_GAIN_CONFIG0__CH2_GAIN_SEL__WIDTH 3 +#define DGADC_GAIN_CONFIG0__CH2_GAIN_SEL__MASK 0x00000038U +#define DGADC_GAIN_CONFIG0__CH2_GAIN_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define DGADC_GAIN_CONFIG0__CH2_GAIN_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define DGADC_GAIN_CONFIG0__CH2_GAIN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define DGADC_GAIN_CONFIG0__CH2_GAIN_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define DGADC_GAIN_CONFIG0__CH2_GAIN_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch3_gain_sel */ +/** + * @defgroup at_apb_gadc_regs_core_ch3_gain_sel_field ch3_gain_sel_field + * @brief macros for field ch3_gain_sel + * @details channel-3 gain settings + * @{ + */ +#define DGADC_GAIN_CONFIG0__CH3_GAIN_SEL__SHIFT 6 +#define DGADC_GAIN_CONFIG0__CH3_GAIN_SEL__WIDTH 3 +#define DGADC_GAIN_CONFIG0__CH3_GAIN_SEL__MASK 0x000001c0U +#define DGADC_GAIN_CONFIG0__CH3_GAIN_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x000001c0U) >> 6) +#define DGADC_GAIN_CONFIG0__CH3_GAIN_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000001c0U) +#define DGADC_GAIN_CONFIG0__CH3_GAIN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((uint32_t)(src) <<\ + 6) & 0x000001c0U) +#define DGADC_GAIN_CONFIG0__CH3_GAIN_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000001c0U))) +#define DGADC_GAIN_CONFIG0__CH3_GAIN_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch4_gain_sel */ +/** + * @defgroup at_apb_gadc_regs_core_ch4_gain_sel_field ch4_gain_sel_field + * @brief macros for field ch4_gain_sel + * @details channel-4 gain settings + * @{ + */ +#define DGADC_GAIN_CONFIG0__CH4_GAIN_SEL__SHIFT 9 +#define DGADC_GAIN_CONFIG0__CH4_GAIN_SEL__WIDTH 3 +#define DGADC_GAIN_CONFIG0__CH4_GAIN_SEL__MASK 0x00000e00U +#define DGADC_GAIN_CONFIG0__CH4_GAIN_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000e00U) >> 9) +#define DGADC_GAIN_CONFIG0__CH4_GAIN_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000e00U) +#define DGADC_GAIN_CONFIG0__CH4_GAIN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((uint32_t)(src) <<\ + 9) & 0x00000e00U) +#define DGADC_GAIN_CONFIG0__CH4_GAIN_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000e00U))) +#define DGADC_GAIN_CONFIG0__CH4_GAIN_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch5_gain_sel */ +/** + * @defgroup at_apb_gadc_regs_core_ch5_gain_sel_field ch5_gain_sel_field + * @brief macros for field ch5_gain_sel + * @details channel-5 gain settings + * @{ + */ +#define DGADC_GAIN_CONFIG0__CH5_GAIN_SEL__SHIFT 12 +#define DGADC_GAIN_CONFIG0__CH5_GAIN_SEL__WIDTH 3 +#define DGADC_GAIN_CONFIG0__CH5_GAIN_SEL__MASK 0x00007000U +#define DGADC_GAIN_CONFIG0__CH5_GAIN_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00007000U) >> 12) +#define DGADC_GAIN_CONFIG0__CH5_GAIN_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00007000U) +#define DGADC_GAIN_CONFIG0__CH5_GAIN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((uint32_t)(src) <<\ + 12) & 0x00007000U) +#define DGADC_GAIN_CONFIG0__CH5_GAIN_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00007000U))) +#define DGADC_GAIN_CONFIG0__CH5_GAIN_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch6_gain_sel */ +/** + * @defgroup at_apb_gadc_regs_core_ch6_gain_sel_field ch6_gain_sel_field + * @brief macros for field ch6_gain_sel + * @details channel-6 gain settings + * @{ + */ +#define DGADC_GAIN_CONFIG0__CH6_GAIN_SEL__SHIFT 15 +#define DGADC_GAIN_CONFIG0__CH6_GAIN_SEL__WIDTH 3 +#define DGADC_GAIN_CONFIG0__CH6_GAIN_SEL__MASK 0x00038000U +#define DGADC_GAIN_CONFIG0__CH6_GAIN_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00038000U) >> 15) +#define DGADC_GAIN_CONFIG0__CH6_GAIN_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00038000U) +#define DGADC_GAIN_CONFIG0__CH6_GAIN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((uint32_t)(src) <<\ + 15) & 0x00038000U) +#define DGADC_GAIN_CONFIG0__CH6_GAIN_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00038000U))) +#define DGADC_GAIN_CONFIG0__CH6_GAIN_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch7_gain_sel */ +/** + * @defgroup at_apb_gadc_regs_core_ch7_gain_sel_field ch7_gain_sel_field + * @brief macros for field ch7_gain_sel + * @details channel-7 gain settings + * @{ + */ +#define DGADC_GAIN_CONFIG0__CH7_GAIN_SEL__SHIFT 18 +#define DGADC_GAIN_CONFIG0__CH7_GAIN_SEL__WIDTH 3 +#define DGADC_GAIN_CONFIG0__CH7_GAIN_SEL__MASK 0x001c0000U +#define DGADC_GAIN_CONFIG0__CH7_GAIN_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x001c0000U) >> 18) +#define DGADC_GAIN_CONFIG0__CH7_GAIN_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x001c0000U) +#define DGADC_GAIN_CONFIG0__CH7_GAIN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((uint32_t)(src) <<\ + 18) & 0x001c0000U) +#define DGADC_GAIN_CONFIG0__CH7_GAIN_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x001c0000U))) +#define DGADC_GAIN_CONFIG0__CH7_GAIN_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch8_gain_sel */ +/** + * @defgroup at_apb_gadc_regs_core_ch8_gain_sel_field ch8_gain_sel_field + * @brief macros for field ch8_gain_sel + * @details channel-8 gain settings + * @{ + */ +#define DGADC_GAIN_CONFIG0__CH8_GAIN_SEL__SHIFT 21 +#define DGADC_GAIN_CONFIG0__CH8_GAIN_SEL__WIDTH 3 +#define DGADC_GAIN_CONFIG0__CH8_GAIN_SEL__MASK 0x00e00000U +#define DGADC_GAIN_CONFIG0__CH8_GAIN_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00e00000U) >> 21) +#define DGADC_GAIN_CONFIG0__CH8_GAIN_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00e00000U) +#define DGADC_GAIN_CONFIG0__CH8_GAIN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((uint32_t)(src) <<\ + 21) & 0x00e00000U) +#define DGADC_GAIN_CONFIG0__CH8_GAIN_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00e00000U))) +#define DGADC_GAIN_CONFIG0__CH8_GAIN_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch9_gain_sel */ +/** + * @defgroup at_apb_gadc_regs_core_ch9_gain_sel_field ch9_gain_sel_field + * @brief macros for field ch9_gain_sel + * @details channel-9 gain settings + * @{ + */ +#define DGADC_GAIN_CONFIG0__CH9_GAIN_SEL__SHIFT 24 +#define DGADC_GAIN_CONFIG0__CH9_GAIN_SEL__WIDTH 3 +#define DGADC_GAIN_CONFIG0__CH9_GAIN_SEL__MASK 0x07000000U +#define DGADC_GAIN_CONFIG0__CH9_GAIN_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x07000000U) >> 24) +#define DGADC_GAIN_CONFIG0__CH9_GAIN_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x07000000U) +#define DGADC_GAIN_CONFIG0__CH9_GAIN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((uint32_t)(src) <<\ + 24) & 0x07000000U) +#define DGADC_GAIN_CONFIG0__CH9_GAIN_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x07000000U))) +#define DGADC_GAIN_CONFIG0__CH9_GAIN_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch10_gain_sel */ +/** + * @defgroup at_apb_gadc_regs_core_ch10_gain_sel_field ch10_gain_sel_field + * @brief macros for field ch10_gain_sel + * @details channel-10 gain settings + * @{ + */ +#define DGADC_GAIN_CONFIG0__CH10_GAIN_SEL__SHIFT 27 +#define DGADC_GAIN_CONFIG0__CH10_GAIN_SEL__WIDTH 3 +#define DGADC_GAIN_CONFIG0__CH10_GAIN_SEL__MASK 0x38000000U +#define DGADC_GAIN_CONFIG0__CH10_GAIN_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x38000000U) >> 27) +#define DGADC_GAIN_CONFIG0__CH10_GAIN_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x38000000U) +#define DGADC_GAIN_CONFIG0__CH10_GAIN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x38000000U) | (((uint32_t)(src) <<\ + 27) & 0x38000000U) +#define DGADC_GAIN_CONFIG0__CH10_GAIN_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x38000000U))) +#define DGADC_GAIN_CONFIG0__CH10_GAIN_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define DGADC_GAIN_CONFIG0__TYPE uint32_t +#define DGADC_GAIN_CONFIG0__READ 0x3fffffffU +#define DGADC_GAIN_CONFIG0__WRITE 0x3fffffffU +#define DGADC_GAIN_CONFIG0__PRESERVED 0x00000000U +#define DGADC_GAIN_CONFIG0__RESET_VALUE 0x00000000U + +#endif /* __DGADC_GAIN_CONFIG0_MACRO__ */ + +/** @} end of gain_config0 */ + +/* macros for BlueprintGlobalNameSpace::DGADC_gain_config1 */ +/** + * @defgroup at_apb_gadc_regs_core_gain_config1 gain_config1 + * @brief channels 11-15 gain settings selection definitions. + * @{ + */ +#ifndef __DGADC_GAIN_CONFIG1_MACRO__ +#define __DGADC_GAIN_CONFIG1_MACRO__ + +/* macros for field ch11_gain_sel */ +/** + * @defgroup at_apb_gadc_regs_core_ch11_gain_sel_field ch11_gain_sel_field + * @brief macros for field ch11_gain_sel + * @details channel-11 gain settings + * @{ + */ +#define DGADC_GAIN_CONFIG1__CH11_GAIN_SEL__SHIFT 0 +#define DGADC_GAIN_CONFIG1__CH11_GAIN_SEL__WIDTH 3 +#define DGADC_GAIN_CONFIG1__CH11_GAIN_SEL__MASK 0x00000007U +#define DGADC_GAIN_CONFIG1__CH11_GAIN_SEL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define DGADC_GAIN_CONFIG1__CH11_GAIN_SEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define DGADC_GAIN_CONFIG1__CH11_GAIN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define DGADC_GAIN_CONFIG1__CH11_GAIN_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define DGADC_GAIN_CONFIG1__CH11_GAIN_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch12_gain_sel */ +/** + * @defgroup at_apb_gadc_regs_core_ch12_gain_sel_field ch12_gain_sel_field + * @brief macros for field ch12_gain_sel + * @details channel-12 gain settings + * @{ + */ +#define DGADC_GAIN_CONFIG1__CH12_GAIN_SEL__SHIFT 3 +#define DGADC_GAIN_CONFIG1__CH12_GAIN_SEL__WIDTH 3 +#define DGADC_GAIN_CONFIG1__CH12_GAIN_SEL__MASK 0x00000038U +#define DGADC_GAIN_CONFIG1__CH12_GAIN_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define DGADC_GAIN_CONFIG1__CH12_GAIN_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define DGADC_GAIN_CONFIG1__CH12_GAIN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define DGADC_GAIN_CONFIG1__CH12_GAIN_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define DGADC_GAIN_CONFIG1__CH12_GAIN_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define DGADC_GAIN_CONFIG1__TYPE uint32_t +#define DGADC_GAIN_CONFIG1__READ 0x0000003fU +#define DGADC_GAIN_CONFIG1__WRITE 0x0000003fU +#define DGADC_GAIN_CONFIG1__PRESERVED 0x00000000U +#define DGADC_GAIN_CONFIG1__RESET_VALUE 0x00000000U + +#endif /* __DGADC_GAIN_CONFIG1_MACRO__ */ + +/** @} end of gain_config1 */ + +/* macros for BlueprintGlobalNameSpace::DGADC_datapath_output */ +/** + * @defgroup at_apb_gadc_regs_core_datapath_output datapath_output + * @brief a read of this register pops the data FIFO definitions. + * @{ + */ +#ifndef __DGADC_DATAPATH_OUTPUT_MACRO__ +#define __DGADC_DATAPATH_OUTPUT_MACRO__ + +/* macros for field data */ +/** + * @defgroup at_apb_gadc_regs_core_data_field data_field + * @brief macros for field data + * @details {4b channel id, 12b processed ADC sample Q<10,1>, 5b exponent} + * @{ + */ +#define DGADC_DATAPATH_OUTPUT__DATA__SHIFT 0 +#define DGADC_DATAPATH_OUTPUT__DATA__WIDTH 21 +#define DGADC_DATAPATH_OUTPUT__DATA__MASK 0x001fffffU +#define DGADC_DATAPATH_OUTPUT__DATA__READ(src) ((uint32_t)(src) & 0x001fffffU) +#define DGADC_DATAPATH_OUTPUT__DATA__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field empty */ +/** + * @defgroup at_apb_gadc_regs_core_empty_field empty_field + * @brief macros for field empty + * @details if 1, ignore data sample because fifo has been drained + * @{ + */ +#define DGADC_DATAPATH_OUTPUT__EMPTY__SHIFT 31 +#define DGADC_DATAPATH_OUTPUT__EMPTY__WIDTH 1 +#define DGADC_DATAPATH_OUTPUT__EMPTY__MASK 0x80000000U +#define DGADC_DATAPATH_OUTPUT__EMPTY__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define DGADC_DATAPATH_OUTPUT__EMPTY__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define DGADC_DATAPATH_OUTPUT__EMPTY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define DGADC_DATAPATH_OUTPUT__EMPTY__RESET_VALUE 0x00000000U +/** @} */ +#define DGADC_DATAPATH_OUTPUT__TYPE uint32_t +#define DGADC_DATAPATH_OUTPUT__READ 0x801fffffU +#define DGADC_DATAPATH_OUTPUT__PRESERVED 0x00000000U +#define DGADC_DATAPATH_OUTPUT__RESET_VALUE 0x00000000U + +#endif /* __DGADC_DATAPATH_OUTPUT_MACRO__ */ + +/** @} end of datapath_output */ + +/* macros for BlueprintGlobalNameSpace::DGADC_interrupts */ +/** + * @defgroup at_apb_gadc_regs_core_interrupts interrupts + * @brief interrupt status definitions. + * @{ + */ +#ifndef __DGADC_INTERRUPTS_MACRO__ +#define __DGADC_INTERRUPTS_MACRO__ + +/* macros for field intrpt0 */ +/** + * @defgroup at_apb_gadc_regs_core_intrpt0_field intrpt0_field + * @brief macros for field intrpt0 + * @details hardware written to fifo + * @{ + */ +#define DGADC_INTERRUPTS__INTRPT0__SHIFT 0 +#define DGADC_INTERRUPTS__INTRPT0__WIDTH 1 +#define DGADC_INTERRUPTS__INTRPT0__MASK 0x00000001U +#define DGADC_INTERRUPTS__INTRPT0__READ(src) ((uint32_t)(src) & 0x00000001U) +#define DGADC_INTERRUPTS__INTRPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define DGADC_INTERRUPTS__INTRPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define DGADC_INTERRUPTS__INTRPT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrpt1 */ +/** + * @defgroup at_apb_gadc_regs_core_intrpt1_field intrpt1_field + * @brief macros for field intrpt1 + * @details fifo overran + * @{ + */ +#define DGADC_INTERRUPTS__INTRPT1__SHIFT 1 +#define DGADC_INTERRUPTS__INTRPT1__WIDTH 1 +#define DGADC_INTERRUPTS__INTRPT1__MASK 0x00000002U +#define DGADC_INTERRUPTS__INTRPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define DGADC_INTERRUPTS__INTRPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define DGADC_INTERRUPTS__INTRPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define DGADC_INTERRUPTS__INTRPT1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrpt2 */ +/** + * @defgroup at_apb_gadc_regs_core_intrpt2_field intrpt2_field + * @brief macros for field intrpt2 + * @details one shot or one round of continuous mode has completed + * @{ + */ +#define DGADC_INTERRUPTS__INTRPT2__SHIFT 2 +#define DGADC_INTERRUPTS__INTRPT2__WIDTH 1 +#define DGADC_INTERRUPTS__INTRPT2__MASK 0x00000004U +#define DGADC_INTERRUPTS__INTRPT2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define DGADC_INTERRUPTS__INTRPT2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define DGADC_INTERRUPTS__INTRPT2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define DGADC_INTERRUPTS__INTRPT2__RESET_VALUE 0x00000000U +/** @} */ +#define DGADC_INTERRUPTS__TYPE uint32_t +#define DGADC_INTERRUPTS__READ 0x00000007U +#define DGADC_INTERRUPTS__PRESERVED 0x00000000U +#define DGADC_INTERRUPTS__RESET_VALUE 0x00000000U + +#endif /* __DGADC_INTERRUPTS_MACRO__ */ + +/** @} end of interrupts */ + +/* macros for BlueprintGlobalNameSpace::DGADC_interrupt_mask */ +/** + * @defgroup at_apb_gadc_regs_core_interrupt_mask interrupt_mask + * @brief interrupt masking definitions. + * @{ + */ +#ifndef __DGADC_INTERRUPT_MASK_MACRO__ +#define __DGADC_INTERRUPT_MASK_MACRO__ + +/* macros for field mask_intrpt0 */ +/** + * @defgroup at_apb_gadc_regs_core_mask_intrpt0_field mask_intrpt0_field + * @brief macros for field mask_intrpt0 + * @details allow intrpt0 to propogate to core's single output interrupt + * @{ + */ +#define DGADC_INTERRUPT_MASK__MASK_INTRPT0__SHIFT 0 +#define DGADC_INTERRUPT_MASK__MASK_INTRPT0__WIDTH 1 +#define DGADC_INTERRUPT_MASK__MASK_INTRPT0__MASK 0x00000001U +#define DGADC_INTERRUPT_MASK__MASK_INTRPT0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define DGADC_INTERRUPT_MASK__MASK_INTRPT0__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define DGADC_INTERRUPT_MASK__MASK_INTRPT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define DGADC_INTERRUPT_MASK__MASK_INTRPT0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define DGADC_INTERRUPT_MASK__MASK_INTRPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define DGADC_INTERRUPT_MASK__MASK_INTRPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define DGADC_INTERRUPT_MASK__MASK_INTRPT0__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field mask_intrpt1 */ +/** + * @defgroup at_apb_gadc_regs_core_mask_intrpt1_field mask_intrpt1_field + * @brief macros for field mask_intrpt1 + * @details allow intrpt1 to propogate to core's single output interrupt + * @{ + */ +#define DGADC_INTERRUPT_MASK__MASK_INTRPT1__SHIFT 1 +#define DGADC_INTERRUPT_MASK__MASK_INTRPT1__WIDTH 1 +#define DGADC_INTERRUPT_MASK__MASK_INTRPT1__MASK 0x00000002U +#define DGADC_INTERRUPT_MASK__MASK_INTRPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define DGADC_INTERRUPT_MASK__MASK_INTRPT1__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define DGADC_INTERRUPT_MASK__MASK_INTRPT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define DGADC_INTERRUPT_MASK__MASK_INTRPT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define DGADC_INTERRUPT_MASK__MASK_INTRPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define DGADC_INTERRUPT_MASK__MASK_INTRPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define DGADC_INTERRUPT_MASK__MASK_INTRPT1__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field mask_intrpt2 */ +/** + * @defgroup at_apb_gadc_regs_core_mask_intrpt2_field mask_intrpt2_field + * @brief macros for field mask_intrpt2 + * @details allow intrpt2 to propogate to core's single output interrupt + * @{ + */ +#define DGADC_INTERRUPT_MASK__MASK_INTRPT2__SHIFT 2 +#define DGADC_INTERRUPT_MASK__MASK_INTRPT2__WIDTH 1 +#define DGADC_INTERRUPT_MASK__MASK_INTRPT2__MASK 0x00000004U +#define DGADC_INTERRUPT_MASK__MASK_INTRPT2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define DGADC_INTERRUPT_MASK__MASK_INTRPT2__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define DGADC_INTERRUPT_MASK__MASK_INTRPT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define DGADC_INTERRUPT_MASK__MASK_INTRPT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define DGADC_INTERRUPT_MASK__MASK_INTRPT2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define DGADC_INTERRUPT_MASK__MASK_INTRPT2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define DGADC_INTERRUPT_MASK__MASK_INTRPT2__RESET_VALUE 0x00000001U +/** @} */ +#define DGADC_INTERRUPT_MASK__TYPE uint32_t +#define DGADC_INTERRUPT_MASK__READ 0x00000007U +#define DGADC_INTERRUPT_MASK__WRITE 0x00000007U +#define DGADC_INTERRUPT_MASK__PRESERVED 0x00000000U +#define DGADC_INTERRUPT_MASK__RESET_VALUE 0x00000007U + +#endif /* __DGADC_INTERRUPT_MASK_MACRO__ */ + +/** @} end of interrupt_mask */ + +/* macros for BlueprintGlobalNameSpace::DGADC_interrupt_clear */ +/** + * @defgroup at_apb_gadc_regs_core_interrupt_clear interrupt_clear + * @brief clear interrupts definitions. + * @{ + */ +#ifndef __DGADC_INTERRUPT_CLEAR_MACRO__ +#define __DGADC_INTERRUPT_CLEAR_MACRO__ + +/* macros for field clear_intrpt0 */ +/** + * @defgroup at_apb_gadc_regs_core_clear_intrpt0_field clear_intrpt0_field + * @brief macros for field clear_intrpt0 + * @details clear interrupt 0; not self reseting + * @{ + */ +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT0__SHIFT 0 +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT0__WIDTH 1 +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT0__MASK 0x00000001U +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT0__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_intrpt1 */ +/** + * @defgroup at_apb_gadc_regs_core_clear_intrpt1_field clear_intrpt1_field + * @brief macros for field clear_intrpt1 + * @details clear interrupt 1; not self reseting + * @{ + */ +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT1__SHIFT 1 +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT1__WIDTH 1 +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT1__MASK 0x00000002U +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT1__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_intrpt2 */ +/** + * @defgroup at_apb_gadc_regs_core_clear_intrpt2_field clear_intrpt2_field + * @brief macros for field clear_intrpt2 + * @details clear interrupt 2; not self reseting + * @{ + */ +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT2__SHIFT 2 +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT2__WIDTH 1 +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT2__MASK 0x00000004U +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT2__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define DGADC_INTERRUPT_CLEAR__CLEAR_INTRPT2__RESET_VALUE 0x00000000U +/** @} */ +#define DGADC_INTERRUPT_CLEAR__TYPE uint32_t +#define DGADC_INTERRUPT_CLEAR__READ 0x00000007U +#define DGADC_INTERRUPT_CLEAR__WRITE 0x00000007U +#define DGADC_INTERRUPT_CLEAR__PRESERVED 0x00000000U +#define DGADC_INTERRUPT_CLEAR__RESET_VALUE 0x00000000U + +#endif /* __DGADC_INTERRUPT_CLEAR_MACRO__ */ + +/** @} end of interrupt_clear */ + +/* macros for BlueprintGlobalNameSpace::DGADC_fifo_dbg */ +/** + * @defgroup at_apb_gadc_regs_core_fifo_dbg fifo_dbg + * @brief FIFO debug definitions. + * @{ + */ +#ifndef __DGADC_FIFO_DBG_MACRO__ +#define __DGADC_FIFO_DBG_MACRO__ + +/* macros for field status */ +/** + * @defgroup at_apb_gadc_regs_core_status_field status_field + * @brief macros for field status + * @details FIFO debug status + * @{ + */ +#define DGADC_FIFO_DBG__STATUS__SHIFT 0 +#define DGADC_FIFO_DBG__STATUS__WIDTH 16 +#define DGADC_FIFO_DBG__STATUS__MASK 0x0000ffffU +#define DGADC_FIFO_DBG__STATUS__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define DGADC_FIFO_DBG__STATUS__RESET_VALUE 0x00000000U +/** @} */ +#define DGADC_FIFO_DBG__TYPE uint32_t +#define DGADC_FIFO_DBG__READ 0x0000ffffU +#define DGADC_FIFO_DBG__PRESERVED 0x00000000U +#define DGADC_FIFO_DBG__RESET_VALUE 0x00000000U + +#endif /* __DGADC_FIFO_DBG_MACRO__ */ + +/** @} end of fifo_dbg */ + +/* macros for BlueprintGlobalNameSpace::DGADC_core_id */ +/** + * @defgroup at_apb_gadc_regs_core_core_id core_id + * @brief core ID definitions. + * @{ + */ +#ifndef __DGADC_CORE_ID_MACRO__ +#define __DGADC_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_gadc_regs_core_id_field id_field + * @brief macros for field id + * @details GADC in ASCII + * @{ + */ +#define DGADC_CORE_ID__ID__SHIFT 0 +#define DGADC_CORE_ID__ID__WIDTH 32 +#define DGADC_CORE_ID__ID__MASK 0xffffffffU +#define DGADC_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define DGADC_CORE_ID__ID__RESET_VALUE 0x47414443U +/** @} */ +#define DGADC_CORE_ID__TYPE uint32_t +#define DGADC_CORE_ID__READ 0xffffffffU +#define DGADC_CORE_ID__PRESERVED 0x00000000U +#define DGADC_CORE_ID__RESET_VALUE 0x47414443U + +#endif /* __DGADC_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of AT_APB_GADC_REGS_CORE */ +#endif /* __REG_AT_APB_GADC_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_apb_i2c_regs_core_macro.h b/ATM33xx-5/include/reg/at_apb_i2c_regs_core_macro.h new file mode 100644 index 0000000..8a31ebe --- /dev/null +++ b/ATM33xx-5/include/reg/at_apb_i2c_regs_core_macro.h @@ -0,0 +1,1079 @@ +/* */ +/* File: at_apb_i2c_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_apb_i2c_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_APB_I2C_REGS_CORE_H__ +#define __REG_AT_APB_I2C_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_APB_I2C_REGS_CORE at_apb_i2c_regs_core + * @ingroup AT_REG + * @brief at_apb_i2c_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::I2C_transaction_setup */ +/** + * @defgroup at_apb_i2c_regs_core_transaction_setup transaction_setup + * @brief Contains register fields associated with transaction_setup. definitions. + * @{ + */ +#ifndef __I2C_TRANSACTION_SETUP_MACRO__ +#define __I2C_TRANSACTION_SETUP_MACRO__ + +/* macros for field head */ +/** + * @defgroup at_apb_i2c_regs_core_head_field head_field + * @brief macros for field head + * @details - 0=start - 1=stall + * @{ + */ +#define I2C_TRANSACTION_SETUP__HEAD__SHIFT 0 +#define I2C_TRANSACTION_SETUP__HEAD__WIDTH 2 +#define I2C_TRANSACTION_SETUP__HEAD__MASK 0x00000003U +#define I2C_TRANSACTION_SETUP__HEAD__READ(src) ((uint32_t)(src) & 0x00000003U) +#define I2C_TRANSACTION_SETUP__HEAD__WRITE(src) ((uint32_t)(src) & 0x00000003U) +#define I2C_TRANSACTION_SETUP__HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define I2C_TRANSACTION_SETUP__HEAD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define I2C_TRANSACTION_SETUP__HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tail */ +/** + * @defgroup at_apb_i2c_regs_core_tail_field tail_field + * @brief macros for field tail + * @details - 0=stop - 1=stall - 2=restart + * @{ + */ +#define I2C_TRANSACTION_SETUP__TAIL__SHIFT 4 +#define I2C_TRANSACTION_SETUP__TAIL__WIDTH 2 +#define I2C_TRANSACTION_SETUP__TAIL__MASK 0x00000030U +#define I2C_TRANSACTION_SETUP__TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000030U) >> 4) +#define I2C_TRANSACTION_SETUP__TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000030U) +#define I2C_TRANSACTION_SETUP__TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((uint32_t)(src) <<\ + 4) & 0x00000030U) +#define I2C_TRANSACTION_SETUP__TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000030U))) +#define I2C_TRANSACTION_SETUP__TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field master_drives_ack */ +/** + * @defgroup at_apb_i2c_regs_core_master_drives_ack_field master_drives_ack_field + * @brief macros for field master_drives_ack + * @{ + */ +#define I2C_TRANSACTION_SETUP__MASTER_DRIVES_ACK__SHIFT 16 +#define I2C_TRANSACTION_SETUP__MASTER_DRIVES_ACK__WIDTH 1 +#define I2C_TRANSACTION_SETUP__MASTER_DRIVES_ACK__MASK 0x00010000U +#define I2C_TRANSACTION_SETUP__MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define I2C_TRANSACTION_SETUP__MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define I2C_TRANSACTION_SETUP__MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define I2C_TRANSACTION_SETUP__MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define I2C_TRANSACTION_SETUP__MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define I2C_TRANSACTION_SETUP__MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define I2C_TRANSACTION_SETUP__MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ack_value_to_drive */ +/** + * @defgroup at_apb_i2c_regs_core_ack_value_to_drive_field ack_value_to_drive_field + * @brief macros for field ack_value_to_drive + * @{ + */ +#define I2C_TRANSACTION_SETUP__ACK_VALUE_TO_DRIVE__SHIFT 17 +#define I2C_TRANSACTION_SETUP__ACK_VALUE_TO_DRIVE__WIDTH 1 +#define I2C_TRANSACTION_SETUP__ACK_VALUE_TO_DRIVE__MASK 0x00020000U +#define I2C_TRANSACTION_SETUP__ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define I2C_TRANSACTION_SETUP__ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define I2C_TRANSACTION_SETUP__ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define I2C_TRANSACTION_SETUP__ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define I2C_TRANSACTION_SETUP__ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define I2C_TRANSACTION_SETUP__ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define I2C_TRANSACTION_SETUP__ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field go */ +/** + * @defgroup at_apb_i2c_regs_core_go_field go_field + * @brief macros for field go + * @details transaction lauches on rising edge; not self reseting + * @{ + */ +#define I2C_TRANSACTION_SETUP__GO__SHIFT 20 +#define I2C_TRANSACTION_SETUP__GO__WIDTH 1 +#define I2C_TRANSACTION_SETUP__GO__MASK 0x00100000U +#define I2C_TRANSACTION_SETUP__GO__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define I2C_TRANSACTION_SETUP__GO__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define I2C_TRANSACTION_SETUP__GO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define I2C_TRANSACTION_SETUP__GO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define I2C_TRANSACTION_SETUP__GO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define I2C_TRANSACTION_SETUP__GO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define I2C_TRANSACTION_SETUP__GO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mstr */ +/** + * @defgroup at_apb_i2c_regs_core_mstr_field mstr_field + * @brief macros for field mstr + * @details - 1=master interface - 0=slave interface + * @{ + */ +#define I2C_TRANSACTION_SETUP__MSTR__SHIFT 21 +#define I2C_TRANSACTION_SETUP__MSTR__WIDTH 1 +#define I2C_TRANSACTION_SETUP__MSTR__MASK 0x00200000U +#define I2C_TRANSACTION_SETUP__MSTR__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define I2C_TRANSACTION_SETUP__MSTR__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define I2C_TRANSACTION_SETUP__MSTR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define I2C_TRANSACTION_SETUP__MSTR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define I2C_TRANSACTION_SETUP__MSTR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define I2C_TRANSACTION_SETUP__MSTR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define I2C_TRANSACTION_SETUP__MSTR__RESET_VALUE 0x00000001U +/** @} */ +#define I2C_TRANSACTION_SETUP__TYPE uint32_t +#define I2C_TRANSACTION_SETUP__READ 0x00330033U +#define I2C_TRANSACTION_SETUP__WRITE 0x00330033U +#define I2C_TRANSACTION_SETUP__PRESERVED 0x00000000U +#define I2C_TRANSACTION_SETUP__RESET_VALUE 0x00200000U + +#endif /* __I2C_TRANSACTION_SETUP_MACRO__ */ + +/** @} end of transaction_setup */ + +/* macros for BlueprintGlobalNameSpace::I2C_clock_control */ +/** + * @defgroup at_apb_i2c_regs_core_clock_control clock_control + * @brief Contains register fields associated with clock_control. definitions. + * @{ + */ +#ifndef __I2C_CLOCK_CONTROL_MACRO__ +#define __I2C_CLOCK_CONTROL_MACRO__ + +/* macros for field clkdiv */ +/** + * @defgroup at_apb_i2c_regs_core_clkdiv_field clkdiv_field + * @brief macros for field clkdiv + * @details freq_sclk = f_pclk/(4*(clkdiv+1)) + * @{ + */ +#define I2C_CLOCK_CONTROL__CLKDIV__SHIFT 0 +#define I2C_CLOCK_CONTROL__CLKDIV__WIDTH 10 +#define I2C_CLOCK_CONTROL__CLKDIV__MASK 0x000003ffU +#define I2C_CLOCK_CONTROL__CLKDIV__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define I2C_CLOCK_CONTROL__CLKDIV__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define I2C_CLOCK_CONTROL__CLKDIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define I2C_CLOCK_CONTROL__CLKDIV__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define I2C_CLOCK_CONTROL__CLKDIV__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field clk_pu */ +/** + * @defgroup at_apb_i2c_regs_core_clk_pu_field clk_pu_field + * @brief macros for field clk_pu + * @details scl pin pullup enable + * @{ + */ +#define I2C_CLOCK_CONTROL__CLK_PU__SHIFT 10 +#define I2C_CLOCK_CONTROL__CLK_PU__WIDTH 1 +#define I2C_CLOCK_CONTROL__CLK_PU__MASK 0x00000400U +#define I2C_CLOCK_CONTROL__CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define I2C_CLOCK_CONTROL__CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define I2C_CLOCK_CONTROL__CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define I2C_CLOCK_CONTROL__CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define I2C_CLOCK_CONTROL__CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define I2C_CLOCK_CONTROL__CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define I2C_CLOCK_CONTROL__CLK_PU__RESET_VALUE 0x00000000U +/** @} */ +#define I2C_CLOCK_CONTROL__TYPE uint32_t +#define I2C_CLOCK_CONTROL__READ 0x000007ffU +#define I2C_CLOCK_CONTROL__WRITE 0x000007ffU +#define I2C_CLOCK_CONTROL__PRESERVED 0x00000000U +#define I2C_CLOCK_CONTROL__RESET_VALUE 0x00000007U + +#endif /* __I2C_CLOCK_CONTROL_MACRO__ */ + +/** @} end of clock_control */ + +/* macros for BlueprintGlobalNameSpace::I2C_outgoing_data */ +/** + * @defgroup at_apb_i2c_regs_core_outgoing_data outgoing_data + * @brief Contains register fields associated with outgoing_data. definitions. + * @{ + */ +#ifndef __I2C_OUTGOING_DATA_MACRO__ +#define __I2C_OUTGOING_DATA_MACRO__ + +/* macros for field data_o */ +/** + * @defgroup at_apb_i2c_regs_core_data_o_field data_o_field + * @brief macros for field data_o + * @details can be device id, address within device, or write data; if it's device id, the LSB is the R/Wb indicator + * @{ + */ +#define I2C_OUTGOING_DATA__DATA_O__SHIFT 0 +#define I2C_OUTGOING_DATA__DATA_O__WIDTH 8 +#define I2C_OUTGOING_DATA__DATA_O__MASK 0x000000ffU +#define I2C_OUTGOING_DATA__DATA_O__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define I2C_OUTGOING_DATA__DATA_O__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define I2C_OUTGOING_DATA__DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define I2C_OUTGOING_DATA__DATA_O__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define I2C_OUTGOING_DATA__DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field data_oe */ +/** + * @defgroup at_apb_i2c_regs_core_data_oe_field data_oe_field + * @brief macros for field data_oe + * @{ + */ +#define I2C_OUTGOING_DATA__DATA_OE__SHIFT 8 +#define I2C_OUTGOING_DATA__DATA_OE__WIDTH 8 +#define I2C_OUTGOING_DATA__DATA_OE__MASK 0x0000ff00U +#define I2C_OUTGOING_DATA__DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define I2C_OUTGOING_DATA__DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define I2C_OUTGOING_DATA__DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define I2C_OUTGOING_DATA__DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define I2C_OUTGOING_DATA__DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field data_pu */ +/** + * @defgroup at_apb_i2c_regs_core_data_pu_field data_pu_field + * @brief macros for field data_pu + * @details sda pin pullup enable + * @{ + */ +#define I2C_OUTGOING_DATA__DATA_PU__SHIFT 16 +#define I2C_OUTGOING_DATA__DATA_PU__WIDTH 1 +#define I2C_OUTGOING_DATA__DATA_PU__MASK 0x00010000U +#define I2C_OUTGOING_DATA__DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define I2C_OUTGOING_DATA__DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define I2C_OUTGOING_DATA__DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define I2C_OUTGOING_DATA__DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define I2C_OUTGOING_DATA__DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define I2C_OUTGOING_DATA__DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define I2C_OUTGOING_DATA__DATA_PU__RESET_VALUE 0x00000000U +/** @} */ +#define I2C_OUTGOING_DATA__TYPE uint32_t +#define I2C_OUTGOING_DATA__READ 0x0001ffffU +#define I2C_OUTGOING_DATA__WRITE 0x0001ffffU +#define I2C_OUTGOING_DATA__PRESERVED 0x00000000U +#define I2C_OUTGOING_DATA__RESET_VALUE 0x0000ff00U + +#endif /* __I2C_OUTGOING_DATA_MACRO__ */ + +/** @} end of outgoing_data */ + +/* macros for BlueprintGlobalNameSpace::I2C_outgoing_data1 */ +/** + * @defgroup at_apb_i2c_regs_core_outgoing_data1 outgoing_data1 + * @brief stores outgoing read data definitions. + * @{ + */ +#ifndef __I2C_OUTGOING_DATA1_MACRO__ +#define __I2C_OUTGOING_DATA1_MACRO__ + +/* macros for field data1_o */ +/** + * @defgroup at_apb_i2c_regs_core_data1_o_field data1_o_field + * @brief macros for field data1_o + * @details slave: stores outgoing read data + * @{ + */ +#define I2C_OUTGOING_DATA1__DATA1_O__SHIFT 0 +#define I2C_OUTGOING_DATA1__DATA1_O__WIDTH 32 +#define I2C_OUTGOING_DATA1__DATA1_O__MASK 0xffffffffU +#define I2C_OUTGOING_DATA1__DATA1_O__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define I2C_OUTGOING_DATA1__DATA1_O__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define I2C_OUTGOING_DATA1__DATA1_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define I2C_OUTGOING_DATA1__DATA1_O__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define I2C_OUTGOING_DATA1__DATA1_O__RESET_VALUE 0x00000000U +/** @} */ +#define I2C_OUTGOING_DATA1__TYPE uint32_t +#define I2C_OUTGOING_DATA1__READ 0xffffffffU +#define I2C_OUTGOING_DATA1__WRITE 0xffffffffU +#define I2C_OUTGOING_DATA1__PRESERVED 0x00000000U +#define I2C_OUTGOING_DATA1__RESET_VALUE 0x00000000U + +#endif /* __I2C_OUTGOING_DATA1_MACRO__ */ + +/** @} end of outgoing_data1 */ + +/* macros for BlueprintGlobalNameSpace::I2C_io_ctrl */ +/** + * @defgroup at_apb_i2c_regs_core_io_ctrl io_ctrl + * @brief Contains register fields associated with io_ctrl. definitions. + * @{ + */ +#ifndef __I2C_IO_CTRL_MACRO__ +#define __I2C_IO_CTRL_MACRO__ + +/* macros for field data_ie_ovrd */ +/** + * @defgroup at_apb_i2c_regs_core_data_ie_ovrd_field data_ie_ovrd_field + * @brief macros for field data_ie_ovrd + * @details - 1= ie is high - 0= ie is ~oe + * @{ + */ +#define I2C_IO_CTRL__DATA_IE_OVRD__SHIFT 0 +#define I2C_IO_CTRL__DATA_IE_OVRD__WIDTH 1 +#define I2C_IO_CTRL__DATA_IE_OVRD__MASK 0x00000001U +#define I2C_IO_CTRL__DATA_IE_OVRD__READ(src) ((uint32_t)(src) & 0x00000001U) +#define I2C_IO_CTRL__DATA_IE_OVRD__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define I2C_IO_CTRL__DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define I2C_IO_CTRL__DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define I2C_IO_CTRL__DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define I2C_IO_CTRL__DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define I2C_IO_CTRL__DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ +#define I2C_IO_CTRL__TYPE uint32_t +#define I2C_IO_CTRL__READ 0x00000001U +#define I2C_IO_CTRL__WRITE 0x00000001U +#define I2C_IO_CTRL__PRESERVED 0x00000000U +#define I2C_IO_CTRL__RESET_VALUE 0x00000000U + +#endif /* __I2C_IO_CTRL_MACRO__ */ + +/** @} end of io_ctrl */ + +/* macros for BlueprintGlobalNameSpace::I2C_incoming_data */ +/** + * @defgroup at_apb_i2c_regs_core_incoming_data incoming_data + * @brief stores incoming write data definitions. + * @{ + */ +#ifndef __I2C_INCOMING_DATA_MACRO__ +#define __I2C_INCOMING_DATA_MACRO__ + +/* macros for field data_i */ +/** + * @defgroup at_apb_i2c_regs_core_data_i_field data_i_field + * @brief macros for field data_i + * @details master: only lsb byte used slave: all 4 bytes can be used + * @{ + */ +#define I2C_INCOMING_DATA__DATA_I__SHIFT 0 +#define I2C_INCOMING_DATA__DATA_I__WIDTH 32 +#define I2C_INCOMING_DATA__DATA_I__MASK 0xffffffffU +#define I2C_INCOMING_DATA__DATA_I__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define I2C_INCOMING_DATA__DATA_I__RESET_VALUE 0x00000000U +/** @} */ +#define I2C_INCOMING_DATA__TYPE uint32_t +#define I2C_INCOMING_DATA__READ 0xffffffffU +#define I2C_INCOMING_DATA__PRESERVED 0x00000000U +#define I2C_INCOMING_DATA__RESET_VALUE 0x00000000U + +#endif /* __I2C_INCOMING_DATA_MACRO__ */ + +/** @} end of incoming_data */ + +/* macros for BlueprintGlobalNameSpace::I2C_incoming_data1 */ +/** + * @defgroup at_apb_i2c_regs_core_incoming_data1 incoming_data1 + * @brief stores read/write address definitions. + * @{ + */ +#ifndef __I2C_INCOMING_DATA1_MACRO__ +#define __I2C_INCOMING_DATA1_MACRO__ + +/* macros for field data1_i */ +/** + * @defgroup at_apb_i2c_regs_core_data1_i_field data1_i_field + * @brief macros for field data1_i + * @details slave: stores read/write address + * @{ + */ +#define I2C_INCOMING_DATA1__DATA1_I__SHIFT 0 +#define I2C_INCOMING_DATA1__DATA1_I__WIDTH 32 +#define I2C_INCOMING_DATA1__DATA1_I__MASK 0xffffffffU +#define I2C_INCOMING_DATA1__DATA1_I__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define I2C_INCOMING_DATA1__DATA1_I__RESET_VALUE 0x00000000U +/** @} */ +#define I2C_INCOMING_DATA1__TYPE uint32_t +#define I2C_INCOMING_DATA1__READ 0xffffffffU +#define I2C_INCOMING_DATA1__PRESERVED 0x00000000U +#define I2C_INCOMING_DATA1__RESET_VALUE 0x00000000U + +#endif /* __I2C_INCOMING_DATA1_MACRO__ */ + +/** @} end of incoming_data1 */ + +/* macros for BlueprintGlobalNameSpace::I2C_transaction_status */ +/** + * @defgroup at_apb_i2c_regs_core_transaction_status transaction_status + * @brief Contains register fields associated with transaction_status. definitions. + * @{ + */ +#ifndef __I2C_TRANSACTION_STATUS_MACRO__ +#define __I2C_TRANSACTION_STATUS_MACRO__ + +/* macros for field ack_value */ +/** + * @defgroup at_apb_i2c_regs_core_ack_value_field ack_value_field + * @brief macros for field ack_value + * @details useless if mast_drives_ack is set + * @{ + */ +#define I2C_TRANSACTION_STATUS__ACK_VALUE__SHIFT 0 +#define I2C_TRANSACTION_STATUS__ACK_VALUE__WIDTH 1 +#define I2C_TRANSACTION_STATUS__ACK_VALUE__MASK 0x00000001U +#define I2C_TRANSACTION_STATUS__ACK_VALUE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define I2C_TRANSACTION_STATUS__ACK_VALUE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define I2C_TRANSACTION_STATUS__ACK_VALUE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define I2C_TRANSACTION_STATUS__ACK_VALUE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field running */ +/** + * @defgroup at_apb_i2c_regs_core_running_field running_field + * @brief macros for field running + * @details 1=indicate master or slave running based on which interface selected by 'mstr' bit + * @{ + */ +#define I2C_TRANSACTION_STATUS__RUNNING__SHIFT 1 +#define I2C_TRANSACTION_STATUS__RUNNING__WIDTH 1 +#define I2C_TRANSACTION_STATUS__RUNNING__MASK 0x00000002U +#define I2C_TRANSACTION_STATUS__RUNNING__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define I2C_TRANSACTION_STATUS__RUNNING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define I2C_TRANSACTION_STATUS__RUNNING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define I2C_TRANSACTION_STATUS__RUNNING__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field s_rwb */ +/** + * @defgroup at_apb_i2c_regs_core_s_rwb_field s_rwb_field + * @brief macros for field s_rwb + * @details slave read/write status bit - 0=write - 1=read + * @{ + */ +#define I2C_TRANSACTION_STATUS__S_RWB__SHIFT 2 +#define I2C_TRANSACTION_STATUS__S_RWB__WIDTH 1 +#define I2C_TRANSACTION_STATUS__S_RWB__MASK 0x00000004U +#define I2C_TRANSACTION_STATUS__S_RWB__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define I2C_TRANSACTION_STATUS__S_RWB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define I2C_TRANSACTION_STATUS__S_RWB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define I2C_TRANSACTION_STATUS__S_RWB__RESET_VALUE 0x00000000U +/** @} */ +#define I2C_TRANSACTION_STATUS__TYPE uint32_t +#define I2C_TRANSACTION_STATUS__READ 0x00000007U +#define I2C_TRANSACTION_STATUS__PRESERVED 0x00000000U +#define I2C_TRANSACTION_STATUS__RESET_VALUE 0x00000000U + +#endif /* __I2C_TRANSACTION_STATUS_MACRO__ */ + +/** @} end of transaction_status */ + +/* macros for BlueprintGlobalNameSpace::I2C_interrupt_mask */ +/** + * @defgroup at_apb_i2c_regs_core_interrupt_mask interrupt_mask + * @brief Contains register fields associated with interrupt_mask. definitions. + * @{ + */ +#ifndef __I2C_INTERRUPT_MASK_MACRO__ +#define __I2C_INTERRUPT_MASK_MACRO__ + +/* macros for field passthru0 */ +/** + * @defgroup at_apb_i2c_regs_core_passthru0_field passthru0_field + * @brief macros for field passthru0 + * @details 1=allow interrupt0 to be OR'ed into core interrupt + * @{ + */ +#define I2C_INTERRUPT_MASK__PASSTHRU0__SHIFT 0 +#define I2C_INTERRUPT_MASK__PASSTHRU0__WIDTH 1 +#define I2C_INTERRUPT_MASK__PASSTHRU0__MASK 0x00000001U +#define I2C_INTERRUPT_MASK__PASSTHRU0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define I2C_INTERRUPT_MASK__PASSTHRU0__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define I2C_INTERRUPT_MASK__PASSTHRU0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define I2C_INTERRUPT_MASK__PASSTHRU0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define I2C_INTERRUPT_MASK__PASSTHRU0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define I2C_INTERRUPT_MASK__PASSTHRU0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define I2C_INTERRUPT_MASK__PASSTHRU0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field passthru1 */ +/** + * @defgroup at_apb_i2c_regs_core_passthru1_field passthru1_field + * @brief macros for field passthru1 + * @details 1=allow interrupt1 to be OR'ed into core interrupt + * @{ + */ +#define I2C_INTERRUPT_MASK__PASSTHRU1__SHIFT 1 +#define I2C_INTERRUPT_MASK__PASSTHRU1__WIDTH 1 +#define I2C_INTERRUPT_MASK__PASSTHRU1__MASK 0x00000002U +#define I2C_INTERRUPT_MASK__PASSTHRU1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define I2C_INTERRUPT_MASK__PASSTHRU1__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define I2C_INTERRUPT_MASK__PASSTHRU1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define I2C_INTERRUPT_MASK__PASSTHRU1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define I2C_INTERRUPT_MASK__PASSTHRU1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define I2C_INTERRUPT_MASK__PASSTHRU1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define I2C_INTERRUPT_MASK__PASSTHRU1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field passthru2 */ +/** + * @defgroup at_apb_i2c_regs_core_passthru2_field passthru2_field + * @brief macros for field passthru2 + * @details 1=allow interrupt2 to be OR'ed into core interrupt + * @{ + */ +#define I2C_INTERRUPT_MASK__PASSTHRU2__SHIFT 2 +#define I2C_INTERRUPT_MASK__PASSTHRU2__WIDTH 1 +#define I2C_INTERRUPT_MASK__PASSTHRU2__MASK 0x00000004U +#define I2C_INTERRUPT_MASK__PASSTHRU2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define I2C_INTERRUPT_MASK__PASSTHRU2__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define I2C_INTERRUPT_MASK__PASSTHRU2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define I2C_INTERRUPT_MASK__PASSTHRU2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define I2C_INTERRUPT_MASK__PASSTHRU2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define I2C_INTERRUPT_MASK__PASSTHRU2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define I2C_INTERRUPT_MASK__PASSTHRU2__RESET_VALUE 0x00000000U +/** @} */ +#define I2C_INTERRUPT_MASK__TYPE uint32_t +#define I2C_INTERRUPT_MASK__READ 0x00000007U +#define I2C_INTERRUPT_MASK__WRITE 0x00000007U +#define I2C_INTERRUPT_MASK__PRESERVED 0x00000000U +#define I2C_INTERRUPT_MASK__RESET_VALUE 0x00000000U + +#endif /* __I2C_INTERRUPT_MASK_MACRO__ */ + +/** @} end of interrupt_mask */ + +/* macros for BlueprintGlobalNameSpace::I2C_interrupt_status */ +/** + * @defgroup at_apb_i2c_regs_core_interrupt_status interrupt_status + * @brief Contains register fields associated with interrupt_status. definitions. + * @{ + */ +#ifndef __I2C_INTERRUPT_STATUS_MACRO__ +#define __I2C_INTERRUPT_STATUS_MACRO__ + +/* macros for field interrupt0 */ +/** + * @defgroup at_apb_i2c_regs_core_interrupt0_field interrupt0_field + * @brief macros for field interrupt0 + * @details from master, rising edge on done; independent of mask + * @{ + */ +#define I2C_INTERRUPT_STATUS__INTERRUPT0__SHIFT 0 +#define I2C_INTERRUPT_STATUS__INTERRUPT0__WIDTH 1 +#define I2C_INTERRUPT_STATUS__INTERRUPT0__MASK 0x00000001U +#define I2C_INTERRUPT_STATUS__INTERRUPT0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define I2C_INTERRUPT_STATUS__INTERRUPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define I2C_INTERRUPT_STATUS__INTERRUPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define I2C_INTERRUPT_STATUS__INTERRUPT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field interrupt1 */ +/** + * @defgroup at_apb_i2c_regs_core_interrupt1_field interrupt1_field + * @brief macros for field interrupt1 + * @details from slave, rising edge on done transaction capture; independent of mask + * @{ + */ +#define I2C_INTERRUPT_STATUS__INTERRUPT1__SHIFT 1 +#define I2C_INTERRUPT_STATUS__INTERRUPT1__WIDTH 1 +#define I2C_INTERRUPT_STATUS__INTERRUPT1__MASK 0x00000002U +#define I2C_INTERRUPT_STATUS__INTERRUPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define I2C_INTERRUPT_STATUS__INTERRUPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define I2C_INTERRUPT_STATUS__INTERRUPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define I2C_INTERRUPT_STATUS__INTERRUPT1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field interrupt2 */ +/** + * @defgroup at_apb_i2c_regs_core_interrupt2_field interrupt2_field + * @brief macros for field interrupt2 + * @details from slave, rising edge on read data valid error; independent of mask + * @{ + */ +#define I2C_INTERRUPT_STATUS__INTERRUPT2__SHIFT 2 +#define I2C_INTERRUPT_STATUS__INTERRUPT2__WIDTH 1 +#define I2C_INTERRUPT_STATUS__INTERRUPT2__MASK 0x00000004U +#define I2C_INTERRUPT_STATUS__INTERRUPT2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define I2C_INTERRUPT_STATUS__INTERRUPT2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define I2C_INTERRUPT_STATUS__INTERRUPT2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define I2C_INTERRUPT_STATUS__INTERRUPT2__RESET_VALUE 0x00000000U +/** @} */ +#define I2C_INTERRUPT_STATUS__TYPE uint32_t +#define I2C_INTERRUPT_STATUS__READ 0x00000007U +#define I2C_INTERRUPT_STATUS__PRESERVED 0x00000000U +#define I2C_INTERRUPT_STATUS__RESET_VALUE 0x00000000U + +#endif /* __I2C_INTERRUPT_STATUS_MACRO__ */ + +/** @} end of interrupt_status */ + +/* macros for BlueprintGlobalNameSpace::I2C_set_interrupt */ +/** + * @defgroup at_apb_i2c_regs_core_set_interrupt set_interrupt + * @brief not auto cleared definitions. + * @{ + */ +#ifndef __I2C_SET_INTERRUPT_MACRO__ +#define __I2C_SET_INTERRUPT_MACRO__ + +/* macros for field set_interrupt0 */ +/** + * @defgroup at_apb_i2c_regs_core_set_interrupt0_field set_interrupt0_field + * @brief macros for field set_interrupt0 + * @details set interrupt0; not auto cleared + * @{ + */ +#define I2C_SET_INTERRUPT__SET_INTERRUPT0__SHIFT 0 +#define I2C_SET_INTERRUPT__SET_INTERRUPT0__WIDTH 1 +#define I2C_SET_INTERRUPT__SET_INTERRUPT0__MASK 0x00000001U +#define I2C_SET_INTERRUPT__SET_INTERRUPT0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define I2C_SET_INTERRUPT__SET_INTERRUPT0__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define I2C_SET_INTERRUPT__SET_INTERRUPT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define I2C_SET_INTERRUPT__SET_INTERRUPT0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define I2C_SET_INTERRUPT__SET_INTERRUPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define I2C_SET_INTERRUPT__SET_INTERRUPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define I2C_SET_INTERRUPT__SET_INTERRUPT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field set_interrupt1 */ +/** + * @defgroup at_apb_i2c_regs_core_set_interrupt1_field set_interrupt1_field + * @brief macros for field set_interrupt1 + * @details set interrupt1; not auto cleared + * @{ + */ +#define I2C_SET_INTERRUPT__SET_INTERRUPT1__SHIFT 1 +#define I2C_SET_INTERRUPT__SET_INTERRUPT1__WIDTH 1 +#define I2C_SET_INTERRUPT__SET_INTERRUPT1__MASK 0x00000002U +#define I2C_SET_INTERRUPT__SET_INTERRUPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define I2C_SET_INTERRUPT__SET_INTERRUPT1__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define I2C_SET_INTERRUPT__SET_INTERRUPT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define I2C_SET_INTERRUPT__SET_INTERRUPT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define I2C_SET_INTERRUPT__SET_INTERRUPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define I2C_SET_INTERRUPT__SET_INTERRUPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define I2C_SET_INTERRUPT__SET_INTERRUPT1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field set_interrupt2 */ +/** + * @defgroup at_apb_i2c_regs_core_set_interrupt2_field set_interrupt2_field + * @brief macros for field set_interrupt2 + * @details set interrupt2; not auto cleared + * @{ + */ +#define I2C_SET_INTERRUPT__SET_INTERRUPT2__SHIFT 2 +#define I2C_SET_INTERRUPT__SET_INTERRUPT2__WIDTH 1 +#define I2C_SET_INTERRUPT__SET_INTERRUPT2__MASK 0x00000004U +#define I2C_SET_INTERRUPT__SET_INTERRUPT2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define I2C_SET_INTERRUPT__SET_INTERRUPT2__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define I2C_SET_INTERRUPT__SET_INTERRUPT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define I2C_SET_INTERRUPT__SET_INTERRUPT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define I2C_SET_INTERRUPT__SET_INTERRUPT2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define I2C_SET_INTERRUPT__SET_INTERRUPT2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define I2C_SET_INTERRUPT__SET_INTERRUPT2__RESET_VALUE 0x00000000U +/** @} */ +#define I2C_SET_INTERRUPT__TYPE uint32_t +#define I2C_SET_INTERRUPT__READ 0x00000007U +#define I2C_SET_INTERRUPT__WRITE 0x00000007U +#define I2C_SET_INTERRUPT__PRESERVED 0x00000000U +#define I2C_SET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __I2C_SET_INTERRUPT_MACRO__ */ + +/** @} end of set_interrupt */ + +/* macros for BlueprintGlobalNameSpace::I2C_reset_interrupt */ +/** + * @defgroup at_apb_i2c_regs_core_reset_interrupt reset_interrupt + * @brief not auto cleared definitions. + * @{ + */ +#ifndef __I2C_RESET_INTERRUPT_MACRO__ +#define __I2C_RESET_INTERRUPT_MACRO__ + +/* macros for field reset_interrupt0 */ +/** + * @defgroup at_apb_i2c_regs_core_reset_interrupt0_field reset_interrupt0_field + * @brief macros for field reset_interrupt0 + * @details clear interrupt0; not auto cleared + * @{ + */ +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT0__SHIFT 0 +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT0__WIDTH 1 +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT0__MASK 0x00000001U +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT0__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reset_interrupt1 */ +/** + * @defgroup at_apb_i2c_regs_core_reset_interrupt1_field reset_interrupt1_field + * @brief macros for field reset_interrupt1 + * @details clear interrupt1; not auto cleared + * @{ + */ +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT1__SHIFT 1 +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT1__WIDTH 1 +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT1__MASK 0x00000002U +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT1__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reset_interrupt2 */ +/** + * @defgroup at_apb_i2c_regs_core_reset_interrupt2_field reset_interrupt2_field + * @brief macros for field reset_interrupt2 + * @details clear interrupt2; not auto cleared + * @{ + */ +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT2__SHIFT 2 +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT2__WIDTH 1 +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT2__MASK 0x00000004U +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT2__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define I2C_RESET_INTERRUPT__RESET_INTERRUPT2__RESET_VALUE 0x00000000U +/** @} */ +#define I2C_RESET_INTERRUPT__TYPE uint32_t +#define I2C_RESET_INTERRUPT__READ 0x00000007U +#define I2C_RESET_INTERRUPT__WRITE 0x00000007U +#define I2C_RESET_INTERRUPT__PRESERVED 0x00000000U +#define I2C_RESET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __I2C_RESET_INTERRUPT_MACRO__ */ + +/** @} end of reset_interrupt */ + +/* macros for BlueprintGlobalNameSpace::I2C_id */ +/** + * @defgroup at_apb_i2c_regs_core_id id + * @brief Contains register fields associated with id. definitions. + * @{ + */ +#ifndef __I2C_ID_MACRO__ +#define __I2C_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_i2c_regs_core_id_field id_field + * @brief macros for field id + * @details I2C in ASCII + * @{ + */ +#define I2C_ID__ID__SHIFT 0 +#define I2C_ID__ID__WIDTH 32 +#define I2C_ID__ID__MASK 0xffffffffU +#define I2C_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define I2C_ID__ID__RESET_VALUE 0x49324320U +/** @} */ +#define I2C_ID__TYPE uint32_t +#define I2C_ID__READ 0xffffffffU +#define I2C_ID__PRESERVED 0x00000000U +#define I2C_ID__RESET_VALUE 0x49324320U + +#endif /* __I2C_ID_MACRO__ */ + +/** @} end of id */ + +/** @} end of AT_APB_I2C_REGS_CORE */ +#endif /* __REG_AT_APB_I2C_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_apb_ksm_regs_core_macro.h b/ATM33xx-5/include/reg/at_apb_ksm_regs_core_macro.h new file mode 100644 index 0000000..d76fe8b --- /dev/null +++ b/ATM33xx-5/include/reg/at_apb_ksm_regs_core_macro.h @@ -0,0 +1,1112 @@ +/* */ +/* File: at_apb_ksm_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_apb_ksm_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_APB_KSM_REGS_CORE_H__ +#define __REG_AT_APB_KSM_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_APB_KSM_REGS_CORE at_apb_ksm_regs_core + * @ingroup AT_REG + * @brief at_apb_ksm_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::KSM_ctrl0 */ +/** + * @defgroup at_apb_ksm_regs_core_ctrl0 ctrl0 + * @brief Contains register fields associated with ctrl0. definitions. + * @{ + */ +#ifndef __KSM_CTRL0_MACRO__ +#define __KSM_CTRL0_MACRO__ + +/* macros for field go */ +/** + * @defgroup at_apb_ksm_regs_core_go_field go_field + * @brief macros for field go + * @details start the keyboard scanning; will scan while go is high; not self reseting + * @{ + */ +#define KSM_CTRL0__GO__SHIFT 0 +#define KSM_CTRL0__GO__WIDTH 1 +#define KSM_CTRL0__GO__MASK 0x00000001U +#define KSM_CTRL0__GO__READ(src) ((uint32_t)(src) & 0x00000001U) +#define KSM_CTRL0__GO__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define KSM_CTRL0__GO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define KSM_CTRL0__GO__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define KSM_CTRL0__GO__SET(dst) (dst) = ((dst) & ~0x00000001U) | (uint32_t)(1) +#define KSM_CTRL0__GO__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (uint32_t)(0) +#define KSM_CTRL0__GO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field loopback */ +/** + * @defgroup at_apb_ksm_regs_core_loopback_field loopback_field + * @brief macros for field loopback + * @details enable lpback_ksi (see below) + * @{ + */ +#define KSM_CTRL0__LOOPBACK__SHIFT 1 +#define KSM_CTRL0__LOOPBACK__WIDTH 1 +#define KSM_CTRL0__LOOPBACK__MASK 0x00000002U +#define KSM_CTRL0__LOOPBACK__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define KSM_CTRL0__LOOPBACK__WRITE(src) (((uint32_t)(src) << 1) & 0x00000002U) +#define KSM_CTRL0__LOOPBACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define KSM_CTRL0__LOOPBACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define KSM_CTRL0__LOOPBACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define KSM_CTRL0__LOOPBACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define KSM_CTRL0__LOOPBACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pop */ +/** + * @defgroup at_apb_ksm_regs_core_pop_field pop_field + * @brief macros for field pop + * @details read from keyboard event fifo; not self reseting + * @{ + */ +#define KSM_CTRL0__POP__SHIFT 2 +#define KSM_CTRL0__POP__WIDTH 1 +#define KSM_CTRL0__POP__MASK 0x00000004U +#define KSM_CTRL0__POP__READ(src) (((uint32_t)(src) & 0x00000004U) >> 2) +#define KSM_CTRL0__POP__WRITE(src) (((uint32_t)(src) << 2) & 0x00000004U) +#define KSM_CTRL0__POP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define KSM_CTRL0__POP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define KSM_CTRL0__POP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define KSM_CTRL0__POP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define KSM_CTRL0__POP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field flush */ +/** + * @defgroup at_apb_ksm_regs_core_flush_field flush_field + * @brief macros for field flush + * @details flushes the key packet fifo + * @{ + */ +#define KSM_CTRL0__FLUSH__SHIFT 3 +#define KSM_CTRL0__FLUSH__WIDTH 1 +#define KSM_CTRL0__FLUSH__MASK 0x00000008U +#define KSM_CTRL0__FLUSH__READ(src) (((uint32_t)(src) & 0x00000008U) >> 3) +#define KSM_CTRL0__FLUSH__WRITE(src) (((uint32_t)(src) << 3) & 0x00000008U) +#define KSM_CTRL0__FLUSH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define KSM_CTRL0__FLUSH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define KSM_CTRL0__FLUSH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define KSM_CTRL0__FLUSH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define KSM_CTRL0__FLUSH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field consecscan */ +/** + * @defgroup at_apb_ksm_regs_core_consecscan_field consecscan_field + * @brief macros for field consecscan + * @details how many consecutive scans are needed before key press or key release event? (0 is INVALID) + * @{ + */ +#define KSM_CTRL0__CONSECSCAN__SHIFT 8 +#define KSM_CTRL0__CONSECSCAN__WIDTH 4 +#define KSM_CTRL0__CONSECSCAN__MASK 0x00000f00U +#define KSM_CTRL0__CONSECSCAN__READ(src) (((uint32_t)(src) & 0x00000f00U) >> 8) +#define KSM_CTRL0__CONSECSCAN__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000f00U) +#define KSM_CTRL0__CONSECSCAN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((uint32_t)(src) <<\ + 8) & 0x00000f00U) +#define KSM_CTRL0__CONSECSCAN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000f00U))) +#define KSM_CTRL0__CONSECSCAN__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field ksm_not_empty_to_intrpt */ +/** + * @defgroup at_apb_ksm_regs_core_ksm_not_empty_to_intrpt_field ksm_not_empty_to_intrpt_field + * @brief macros for field ksm_not_empty_to_intrpt + * @details in addition to fifo_write, /not empty/ signal will also feed into setting intrpt[0] + * @{ + */ +#define KSM_CTRL0__KSM_NOT_EMPTY_TO_INTRPT__SHIFT 12 +#define KSM_CTRL0__KSM_NOT_EMPTY_TO_INTRPT__WIDTH 1 +#define KSM_CTRL0__KSM_NOT_EMPTY_TO_INTRPT__MASK 0x00001000U +#define KSM_CTRL0__KSM_NOT_EMPTY_TO_INTRPT__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define KSM_CTRL0__KSM_NOT_EMPTY_TO_INTRPT__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define KSM_CTRL0__KSM_NOT_EMPTY_TO_INTRPT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define KSM_CTRL0__KSM_NOT_EMPTY_TO_INTRPT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define KSM_CTRL0__KSM_NOT_EMPTY_TO_INTRPT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define KSM_CTRL0__KSM_NOT_EMPTY_TO_INTRPT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define KSM_CTRL0__KSM_NOT_EMPTY_TO_INTRPT__RESET_VALUE 0x00000000U +/** @} */ +#define KSM_CTRL0__TYPE uint32_t +#define KSM_CTRL0__READ 0x00001f0fU +#define KSM_CTRL0__WRITE 0x00001f0fU +#define KSM_CTRL0__PRESERVED 0x00000000U +#define KSM_CTRL0__RESET_VALUE 0x00000800U + +#endif /* __KSM_CTRL0_MACRO__ */ + +/** @} end of ctrl0 */ + +/* macros for BlueprintGlobalNameSpace::KSM_time_param0 */ +/** + * @defgroup at_apb_ksm_regs_core_time_param0 time_param0 + * @brief Contains register fields associated with time_param0. definitions. + * @{ + */ +#ifndef __KSM_TIME_PARAM0_MACRO__ +#define __KSM_TIME_PARAM0_MACRO__ + +/* macros for field t2 */ +/** + * @defgroup at_apb_ksm_regs_core_t2_field t2_field + * @brief macros for field t2 + * @details from sampling last row to col rising + * @{ + */ +#define KSM_TIME_PARAM0__T2__SHIFT 0 +#define KSM_TIME_PARAM0__T2__WIDTH 16 +#define KSM_TIME_PARAM0__T2__MASK 0x0000ffffU +#define KSM_TIME_PARAM0__T2__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define KSM_TIME_PARAM0__T2__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define KSM_TIME_PARAM0__T2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define KSM_TIME_PARAM0__T2__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define KSM_TIME_PARAM0__T2__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field t1 */ +/** + * @defgroup at_apb_ksm_regs_core_t1_field t1_field + * @brief macros for field t1 + * @details from col falling to sampling first row + * @{ + */ +#define KSM_TIME_PARAM0__T1__SHIFT 16 +#define KSM_TIME_PARAM0__T1__WIDTH 16 +#define KSM_TIME_PARAM0__T1__MASK 0xffff0000U +#define KSM_TIME_PARAM0__T1__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define KSM_TIME_PARAM0__T1__WRITE(src) (((uint32_t)(src) << 16) & 0xffff0000U) +#define KSM_TIME_PARAM0__T1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define KSM_TIME_PARAM0__T1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define KSM_TIME_PARAM0__T1__RESET_VALUE 0x00000010U +/** @} */ +#define KSM_TIME_PARAM0__TYPE uint32_t +#define KSM_TIME_PARAM0__READ 0xffffffffU +#define KSM_TIME_PARAM0__WRITE 0xffffffffU +#define KSM_TIME_PARAM0__PRESERVED 0x00000000U +#define KSM_TIME_PARAM0__RESET_VALUE 0x00100010U + +#endif /* __KSM_TIME_PARAM0_MACRO__ */ + +/** @} end of time_param0 */ + +/* macros for BlueprintGlobalNameSpace::KSM_time_param1 */ +/** + * @defgroup at_apb_ksm_regs_core_time_param1 time_param1 + * @brief Contains register fields associated with time_param1. definitions. + * @{ + */ +#ifndef __KSM_TIME_PARAM1_MACRO__ +#define __KSM_TIME_PARAM1_MACRO__ + +/* macros for field t4 */ +/** + * @defgroup at_apb_ksm_regs_core_t4_field t4_field + * @brief macros for field t4 + * @details gap between col rising and next col falling + * @{ + */ +#define KSM_TIME_PARAM1__T4__SHIFT 0 +#define KSM_TIME_PARAM1__T4__WIDTH 16 +#define KSM_TIME_PARAM1__T4__MASK 0x0000ffffU +#define KSM_TIME_PARAM1__T4__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define KSM_TIME_PARAM1__T4__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define KSM_TIME_PARAM1__T4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define KSM_TIME_PARAM1__T4__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define KSM_TIME_PARAM1__T4__RESET_VALUE 0x00000040U +/** @} */ + +/* macros for field t3 */ +/** + * @defgroup at_apb_ksm_regs_core_t3_field t3_field + * @brief macros for field t3 + * @details gap between adjacent row samplings + * @{ + */ +#define KSM_TIME_PARAM1__T3__SHIFT 16 +#define KSM_TIME_PARAM1__T3__WIDTH 16 +#define KSM_TIME_PARAM1__T3__MASK 0xffff0000U +#define KSM_TIME_PARAM1__T3__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define KSM_TIME_PARAM1__T3__WRITE(src) (((uint32_t)(src) << 16) & 0xffff0000U) +#define KSM_TIME_PARAM1__T3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define KSM_TIME_PARAM1__T3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define KSM_TIME_PARAM1__T3__RESET_VALUE 0x00000008U +/** @} */ +#define KSM_TIME_PARAM1__TYPE uint32_t +#define KSM_TIME_PARAM1__READ 0xffffffffU +#define KSM_TIME_PARAM1__WRITE 0xffffffffU +#define KSM_TIME_PARAM1__PRESERVED 0x00000000U +#define KSM_TIME_PARAM1__RESET_VALUE 0x00080040U + +#endif /* __KSM_TIME_PARAM1_MACRO__ */ + +/** @} end of time_param1 */ + +/* macros for BlueprintGlobalNameSpace::KSM_matrix_size */ +/** + * @defgroup at_apb_ksm_regs_core_matrix_size matrix_size + * @brief Contains register fields associated with matrix_size. definitions. + * @{ + */ +#ifndef __KSM_MATRIX_SIZE_MACRO__ +#define __KSM_MATRIX_SIZE_MACRO__ + +/* macros for field num_col */ +/** + * @defgroup at_apb_ksm_regs_core_num_col_field num_col_field + * @brief macros for field num_col + * @details the actual number of cols is num_col + 1 + * @{ + */ +#define KSM_MATRIX_SIZE__NUM_COL__SHIFT 0 +#define KSM_MATRIX_SIZE__NUM_COL__WIDTH 5 +#define KSM_MATRIX_SIZE__NUM_COL__MASK 0x0000001fU +#define KSM_MATRIX_SIZE__NUM_COL__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define KSM_MATRIX_SIZE__NUM_COL__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define KSM_MATRIX_SIZE__NUM_COL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define KSM_MATRIX_SIZE__NUM_COL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define KSM_MATRIX_SIZE__NUM_COL__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field num_row */ +/** + * @defgroup at_apb_ksm_regs_core_num_row_field num_row_field + * @brief macros for field num_row + * @details the actual number of rows is num_row + 1 + * @{ + */ +#define KSM_MATRIX_SIZE__NUM_ROW__SHIFT 8 +#define KSM_MATRIX_SIZE__NUM_ROW__WIDTH 5 +#define KSM_MATRIX_SIZE__NUM_ROW__MASK 0x00001f00U +#define KSM_MATRIX_SIZE__NUM_ROW__READ(src) \ + (((uint32_t)(src)\ + & 0x00001f00U) >> 8) +#define KSM_MATRIX_SIZE__NUM_ROW__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00001f00U) +#define KSM_MATRIX_SIZE__NUM_ROW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((uint32_t)(src) <<\ + 8) & 0x00001f00U) +#define KSM_MATRIX_SIZE__NUM_ROW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00001f00U))) +#define KSM_MATRIX_SIZE__NUM_ROW__RESET_VALUE 0x00000013U +/** @} */ +#define KSM_MATRIX_SIZE__TYPE uint32_t +#define KSM_MATRIX_SIZE__READ 0x00001f1fU +#define KSM_MATRIX_SIZE__WRITE 0x00001f1fU +#define KSM_MATRIX_SIZE__PRESERVED 0x00000000U +#define KSM_MATRIX_SIZE__RESET_VALUE 0x00001307U + +#endif /* __KSM_MATRIX_SIZE_MACRO__ */ + +/** @} end of matrix_size */ + +/* macros for BlueprintGlobalNameSpace::KSM_keyboard_packet */ +/** + * @defgroup at_apb_ksm_regs_core_keyboard_packet keyboard_packet + * @brief Contains register fields associated with keyboard_packet. definitions. + * @{ + */ +#ifndef __KSM_KEYBOARD_PACKET_MACRO__ +#define __KSM_KEYBOARD_PACKET_MACRO__ + +/* macros for field row */ +/** + * @defgroup at_apb_ksm_regs_core_row_field row_field + * @brief macros for field row + * @details the row of the pressed or released key; 0-indexed + * @{ + */ +#define KSM_KEYBOARD_PACKET__ROW__SHIFT 0 +#define KSM_KEYBOARD_PACKET__ROW__WIDTH 5 +#define KSM_KEYBOARD_PACKET__ROW__MASK 0x0000001fU +#define KSM_KEYBOARD_PACKET__ROW__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define KSM_KEYBOARD_PACKET__ROW__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field col */ +/** + * @defgroup at_apb_ksm_regs_core_col_field col_field + * @brief macros for field col + * @details the column of the pressed or released key; 0-indexed + * @{ + */ +#define KSM_KEYBOARD_PACKET__COL__SHIFT 5 +#define KSM_KEYBOARD_PACKET__COL__WIDTH 5 +#define KSM_KEYBOARD_PACKET__COL__MASK 0x000003e0U +#define KSM_KEYBOARD_PACKET__COL__READ(src) \ + (((uint32_t)(src)\ + & 0x000003e0U) >> 5) +#define KSM_KEYBOARD_PACKET__COL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pressed_released_n */ +/** + * @defgroup at_apb_ksm_regs_core_pressed_released_n_field pressed_released_n_field + * @brief macros for field pressed_released_n + * @details 1=pressed 0=released + * @{ + */ +#define KSM_KEYBOARD_PACKET__PRESSED_RELEASED_N__SHIFT 10 +#define KSM_KEYBOARD_PACKET__PRESSED_RELEASED_N__WIDTH 1 +#define KSM_KEYBOARD_PACKET__PRESSED_RELEASED_N__MASK 0x00000400U +#define KSM_KEYBOARD_PACKET__PRESSED_RELEASED_N__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define KSM_KEYBOARD_PACKET__PRESSED_RELEASED_N__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define KSM_KEYBOARD_PACKET__PRESSED_RELEASED_N__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define KSM_KEYBOARD_PACKET__PRESSED_RELEASED_N__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field empty */ +/** + * @defgroup at_apb_ksm_regs_core_empty_field empty_field + * @brief macros for field empty + * @details if 1, ignore this pack et + * @{ + */ +#define KSM_KEYBOARD_PACKET__EMPTY__SHIFT 11 +#define KSM_KEYBOARD_PACKET__EMPTY__WIDTH 1 +#define KSM_KEYBOARD_PACKET__EMPTY__MASK 0x00000800U +#define KSM_KEYBOARD_PACKET__EMPTY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define KSM_KEYBOARD_PACKET__EMPTY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define KSM_KEYBOARD_PACKET__EMPTY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define KSM_KEYBOARD_PACKET__EMPTY__RESET_VALUE 0x00000000U +/** @} */ +#define KSM_KEYBOARD_PACKET__TYPE uint32_t +#define KSM_KEYBOARD_PACKET__READ 0x00000fffU +#define KSM_KEYBOARD_PACKET__PRESERVED 0x00000000U +#define KSM_KEYBOARD_PACKET__RESET_VALUE 0x00000000U + +#endif /* __KSM_KEYBOARD_PACKET_MACRO__ */ + +/** @} end of keyboard_packet */ + +/* macros for BlueprintGlobalNameSpace::KSM_low_power */ +/** + * @defgroup at_apb_ksm_regs_core_low_power low_power + * @brief Contains register fields associated with low_power. definitions. + * @{ + */ +#ifndef __KSM_LOW_POWER_MACRO__ +#define __KSM_LOW_POWER_MACRO__ + +/* macros for field key */ +/** + * @defgroup at_apb_ksm_regs_core_key_field key_field + * @brief macros for field key + * @details this is the key press or release that woke the device + * @{ + */ +#define KSM_LOW_POWER__KEY__SHIFT 0 +#define KSM_LOW_POWER__KEY__WIDTH 11 +#define KSM_LOW_POWER__KEY__MASK 0x000007ffU +#define KSM_LOW_POWER__KEY__READ(src) ((uint32_t)(src) & 0x000007ffU) +#define KSM_LOW_POWER__KEY__RESET_VALUE 0x00000000U +/** @} */ +#define KSM_LOW_POWER__TYPE uint32_t +#define KSM_LOW_POWER__READ 0x000007ffU +#define KSM_LOW_POWER__PRESERVED 0x00000000U +#define KSM_LOW_POWER__RESET_VALUE 0x00000000U + +#endif /* __KSM_LOW_POWER_MACRO__ */ + +/** @} end of low_power */ + +/* macros for BlueprintGlobalNameSpace::KSM_lpback_ksi */ +/** + * @defgroup at_apb_ksm_regs_core_lpback_ksi lpback_ksi + * @brief Contains register fields associated with lpback_ksi. definitions. + * @{ + */ +#ifndef __KSM_LPBACK_KSI_MACRO__ +#define __KSM_LPBACK_KSI_MACRO__ + +/* macros for field lpback_ksi */ +/** + * @defgroup at_apb_ksm_regs_core_lpback_ksi_field lpback_ksi_field + * @brief macros for field lpback_ksi + * @details the values to be driven on each of the ksi lines (while in loopback) + * @{ + */ +#define KSM_LPBACK_KSI__LPBACK_KSI__SHIFT 0 +#define KSM_LPBACK_KSI__LPBACK_KSI__WIDTH 20 +#define KSM_LPBACK_KSI__LPBACK_KSI__MASK 0x000fffffU +#define KSM_LPBACK_KSI__LPBACK_KSI__READ(src) ((uint32_t)(src) & 0x000fffffU) +#define KSM_LPBACK_KSI__LPBACK_KSI__WRITE(src) ((uint32_t)(src) & 0x000fffffU) +#define KSM_LPBACK_KSI__LPBACK_KSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fffffU) | ((uint32_t)(src) &\ + 0x000fffffU) +#define KSM_LPBACK_KSI__LPBACK_KSI__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000fffffU))) +#define KSM_LPBACK_KSI__LPBACK_KSI__RESET_VALUE 0x000fffffU +/** @} */ +#define KSM_LPBACK_KSI__TYPE uint32_t +#define KSM_LPBACK_KSI__READ 0x000fffffU +#define KSM_LPBACK_KSI__WRITE 0x000fffffU +#define KSM_LPBACK_KSI__PRESERVED 0x00000000U +#define KSM_LPBACK_KSI__RESET_VALUE 0x000fffffU + +#endif /* __KSM_LPBACK_KSI_MACRO__ */ + +/** @} end of lpback_ksi */ + +/* macros for BlueprintGlobalNameSpace::KSM_status */ +/** + * @defgroup at_apb_ksm_regs_core_status status + * @brief Contains register fields associated with status. definitions. + * @{ + */ +#ifndef __KSM_STATUS_MACRO__ +#define __KSM_STATUS_MACRO__ + +/* macros for field command_taken */ +/** + * @defgroup at_apb_ksm_regs_core_command_taken_field command_taken_field + * @brief macros for field command_taken + * @details fsm in on 32kHz clock; it takes two 32kHz cycles for the command to be picked up + * @{ + */ +#define KSM_STATUS__COMMAND_TAKEN__SHIFT 0 +#define KSM_STATUS__COMMAND_TAKEN__WIDTH 1 +#define KSM_STATUS__COMMAND_TAKEN__MASK 0x00000001U +#define KSM_STATUS__COMMAND_TAKEN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define KSM_STATUS__COMMAND_TAKEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define KSM_STATUS__COMMAND_TAKEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define KSM_STATUS__COMMAND_TAKEN__RESET_VALUE 0x00000000U +/** @} */ +#define KSM_STATUS__TYPE uint32_t +#define KSM_STATUS__READ 0x00000001U +#define KSM_STATUS__PRESERVED 0x00000000U +#define KSM_STATUS__RESET_VALUE 0x00000000U + +#endif /* __KSM_STATUS_MACRO__ */ + +/** @} end of status */ + +/* macros for BlueprintGlobalNameSpace::KSM_interrupts */ +/** + * @defgroup at_apb_ksm_regs_core_interrupts interrupts + * @brief Contains register fields associated with interrupts. definitions. + * @{ + */ +#ifndef __KSM_INTERRUPTS_MACRO__ +#define __KSM_INTERRUPTS_MACRO__ + +/* macros for field intrpt0 */ +/** + * @defgroup at_apb_ksm_regs_core_intrpt0_field intrpt0_field + * @brief macros for field intrpt0 + * @details hardware wrote packet to keyboard event fifo + * @{ + */ +#define KSM_INTERRUPTS__INTRPT0__SHIFT 0 +#define KSM_INTERRUPTS__INTRPT0__WIDTH 1 +#define KSM_INTERRUPTS__INTRPT0__MASK 0x00000001U +#define KSM_INTERRUPTS__INTRPT0__READ(src) ((uint32_t)(src) & 0x00000001U) +#define KSM_INTERRUPTS__INTRPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define KSM_INTERRUPTS__INTRPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define KSM_INTERRUPTS__INTRPT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrpt1 */ +/** + * @defgroup at_apb_ksm_regs_core_intrpt1_field intrpt1_field + * @brief macros for field intrpt1 + * @details keyboard event fifo overran + * @{ + */ +#define KSM_INTERRUPTS__INTRPT1__SHIFT 1 +#define KSM_INTERRUPTS__INTRPT1__WIDTH 1 +#define KSM_INTERRUPTS__INTRPT1__MASK 0x00000002U +#define KSM_INTERRUPTS__INTRPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define KSM_INTERRUPTS__INTRPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define KSM_INTERRUPTS__INTRPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define KSM_INTERRUPTS__INTRPT1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrpt2 */ +/** + * @defgroup at_apb_ksm_regs_core_intrpt2_field intrpt2_field + * @brief macros for field intrpt2 + * @details pop read is done + * @{ + */ +#define KSM_INTERRUPTS__INTRPT2__SHIFT 2 +#define KSM_INTERRUPTS__INTRPT2__WIDTH 1 +#define KSM_INTERRUPTS__INTRPT2__MASK 0x00000004U +#define KSM_INTERRUPTS__INTRPT2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define KSM_INTERRUPTS__INTRPT2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define KSM_INTERRUPTS__INTRPT2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define KSM_INTERRUPTS__INTRPT2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrpt3 */ +/** + * @defgroup at_apb_ksm_regs_core_intrpt3_field intrpt3_field + * @brief macros for field intrpt3 + * @details flush read is done + * @{ + */ +#define KSM_INTERRUPTS__INTRPT3__SHIFT 3 +#define KSM_INTERRUPTS__INTRPT3__WIDTH 1 +#define KSM_INTERRUPTS__INTRPT3__MASK 0x00000008U +#define KSM_INTERRUPTS__INTRPT3__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define KSM_INTERRUPTS__INTRPT3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define KSM_INTERRUPTS__INTRPT3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define KSM_INTERRUPTS__INTRPT3__RESET_VALUE 0x00000000U +/** @} */ +#define KSM_INTERRUPTS__TYPE uint32_t +#define KSM_INTERRUPTS__READ 0x0000000fU +#define KSM_INTERRUPTS__PRESERVED 0x00000000U +#define KSM_INTERRUPTS__RESET_VALUE 0x00000000U + +#endif /* __KSM_INTERRUPTS_MACRO__ */ + +/** @} end of interrupts */ + +/* macros for BlueprintGlobalNameSpace::KSM_interrupt_mask */ +/** + * @defgroup at_apb_ksm_regs_core_interrupt_mask interrupt_mask + * @brief Contains register fields associated with interrupt_mask. definitions. + * @{ + */ +#ifndef __KSM_INTERRUPT_MASK_MACRO__ +#define __KSM_INTERRUPT_MASK_MACRO__ + +/* macros for field mask_intrpt0 */ +/** + * @defgroup at_apb_ksm_regs_core_mask_intrpt0_field mask_intrpt0_field + * @brief macros for field mask_intrpt0 + * @details allow intrpt0 to propogate to core's single output interrupt + * @{ + */ +#define KSM_INTERRUPT_MASK__MASK_INTRPT0__SHIFT 0 +#define KSM_INTERRUPT_MASK__MASK_INTRPT0__WIDTH 1 +#define KSM_INTERRUPT_MASK__MASK_INTRPT0__MASK 0x00000001U +#define KSM_INTERRUPT_MASK__MASK_INTRPT0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define KSM_INTERRUPT_MASK__MASK_INTRPT0__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define KSM_INTERRUPT_MASK__MASK_INTRPT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define KSM_INTERRUPT_MASK__MASK_INTRPT0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define KSM_INTERRUPT_MASK__MASK_INTRPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define KSM_INTERRUPT_MASK__MASK_INTRPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define KSM_INTERRUPT_MASK__MASK_INTRPT0__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field mask_intrpt1 */ +/** + * @defgroup at_apb_ksm_regs_core_mask_intrpt1_field mask_intrpt1_field + * @brief macros for field mask_intrpt1 + * @details allow intrpt1 to propogate to core's single output interrupt + * @{ + */ +#define KSM_INTERRUPT_MASK__MASK_INTRPT1__SHIFT 1 +#define KSM_INTERRUPT_MASK__MASK_INTRPT1__WIDTH 1 +#define KSM_INTERRUPT_MASK__MASK_INTRPT1__MASK 0x00000002U +#define KSM_INTERRUPT_MASK__MASK_INTRPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define KSM_INTERRUPT_MASK__MASK_INTRPT1__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define KSM_INTERRUPT_MASK__MASK_INTRPT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define KSM_INTERRUPT_MASK__MASK_INTRPT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define KSM_INTERRUPT_MASK__MASK_INTRPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define KSM_INTERRUPT_MASK__MASK_INTRPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define KSM_INTERRUPT_MASK__MASK_INTRPT1__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field mask_intrpt2 */ +/** + * @defgroup at_apb_ksm_regs_core_mask_intrpt2_field mask_intrpt2_field + * @brief macros for field mask_intrpt2 + * @details allow intrpt2 to propogate to core's single output interrupt + * @{ + */ +#define KSM_INTERRUPT_MASK__MASK_INTRPT2__SHIFT 2 +#define KSM_INTERRUPT_MASK__MASK_INTRPT2__WIDTH 1 +#define KSM_INTERRUPT_MASK__MASK_INTRPT2__MASK 0x00000004U +#define KSM_INTERRUPT_MASK__MASK_INTRPT2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define KSM_INTERRUPT_MASK__MASK_INTRPT2__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define KSM_INTERRUPT_MASK__MASK_INTRPT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define KSM_INTERRUPT_MASK__MASK_INTRPT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define KSM_INTERRUPT_MASK__MASK_INTRPT2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define KSM_INTERRUPT_MASK__MASK_INTRPT2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define KSM_INTERRUPT_MASK__MASK_INTRPT2__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field mask_intrpt3 */ +/** + * @defgroup at_apb_ksm_regs_core_mask_intrpt3_field mask_intrpt3_field + * @brief macros for field mask_intrpt3 + * @details allow intrpt3 to propogate to core's single output interrupt + * @{ + */ +#define KSM_INTERRUPT_MASK__MASK_INTRPT3__SHIFT 3 +#define KSM_INTERRUPT_MASK__MASK_INTRPT3__WIDTH 1 +#define KSM_INTERRUPT_MASK__MASK_INTRPT3__MASK 0x00000008U +#define KSM_INTERRUPT_MASK__MASK_INTRPT3__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define KSM_INTERRUPT_MASK__MASK_INTRPT3__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define KSM_INTERRUPT_MASK__MASK_INTRPT3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define KSM_INTERRUPT_MASK__MASK_INTRPT3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define KSM_INTERRUPT_MASK__MASK_INTRPT3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define KSM_INTERRUPT_MASK__MASK_INTRPT3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define KSM_INTERRUPT_MASK__MASK_INTRPT3__RESET_VALUE 0x00000001U +/** @} */ +#define KSM_INTERRUPT_MASK__TYPE uint32_t +#define KSM_INTERRUPT_MASK__READ 0x0000000fU +#define KSM_INTERRUPT_MASK__WRITE 0x0000000fU +#define KSM_INTERRUPT_MASK__PRESERVED 0x00000000U +#define KSM_INTERRUPT_MASK__RESET_VALUE 0x0000000fU + +#endif /* __KSM_INTERRUPT_MASK_MACRO__ */ + +/** @} end of interrupt_mask */ + +/* macros for BlueprintGlobalNameSpace::KSM_interrupt_clear */ +/** + * @defgroup at_apb_ksm_regs_core_interrupt_clear interrupt_clear + * @brief Contains register fields associated with interrupt_clear. definitions. + * @{ + */ +#ifndef __KSM_INTERRUPT_CLEAR_MACRO__ +#define __KSM_INTERRUPT_CLEAR_MACRO__ + +/* macros for field clear_intrpt0 */ +/** + * @defgroup at_apb_ksm_regs_core_clear_intrpt0_field clear_intrpt0_field + * @brief macros for field clear_intrpt0 + * @details clear interrupt 0; not self reseting + * @{ + */ +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT0__SHIFT 0 +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT0__WIDTH 1 +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT0__MASK 0x00000001U +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT0__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_intrpt1 */ +/** + * @defgroup at_apb_ksm_regs_core_clear_intrpt1_field clear_intrpt1_field + * @brief macros for field clear_intrpt1 + * @details clear interrupt 1; not self reseting + * @{ + */ +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT1__SHIFT 1 +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT1__WIDTH 1 +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT1__MASK 0x00000002U +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT1__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_intrpt2 */ +/** + * @defgroup at_apb_ksm_regs_core_clear_intrpt2_field clear_intrpt2_field + * @brief macros for field clear_intrpt2 + * @details clear interrupt 2; not self reseting + * @{ + */ +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT2__SHIFT 2 +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT2__WIDTH 1 +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT2__MASK 0x00000004U +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT2__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_intrpt3 */ +/** + * @defgroup at_apb_ksm_regs_core_clear_intrpt3_field clear_intrpt3_field + * @brief macros for field clear_intrpt3 + * @details clear interrupt 3; not self reseting + * @{ + */ +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT3__SHIFT 3 +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT3__WIDTH 1 +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT3__MASK 0x00000008U +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT3__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT3__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define KSM_INTERRUPT_CLEAR__CLEAR_INTRPT3__RESET_VALUE 0x00000000U +/** @} */ +#define KSM_INTERRUPT_CLEAR__TYPE uint32_t +#define KSM_INTERRUPT_CLEAR__READ 0x0000000fU +#define KSM_INTERRUPT_CLEAR__WRITE 0x0000000fU +#define KSM_INTERRUPT_CLEAR__PRESERVED 0x00000000U +#define KSM_INTERRUPT_CLEAR__RESET_VALUE 0x00000000U + +#endif /* __KSM_INTERRUPT_CLEAR_MACRO__ */ + +/** @} end of interrupt_clear */ + +/* macros for BlueprintGlobalNameSpace::KSM_debug */ +/** + * @defgroup at_apb_ksm_regs_core_debug debug + * @brief Contains register fields associated with debug. definitions. + * @{ + */ +#ifndef __KSM_DEBUG_MACRO__ +#define __KSM_DEBUG_MACRO__ + +/* macros for field kb */ +/** + * @defgroup at_apb_ksm_regs_core_kb_field kb_field + * @brief macros for field kb + * @details {4'b0, debounce_available(array of booleans; 12b)} + * @{ + */ +#define KSM_DEBUG__KB__SHIFT 0 +#define KSM_DEBUG__KB__WIDTH 16 +#define KSM_DEBUG__KB__MASK 0x0000ffffU +#define KSM_DEBUG__KB__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define KSM_DEBUG__KB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fifo */ +/** + * @defgroup at_apb_ksm_regs_core_fifo_field fifo_field + * @brief macros for field fifo + * @details {overrun, underrun, full, empty, 4'd0, rdaddr(unsigned int; 4b), wraddr(unsigned int; 4b)} + * @{ + */ +#define KSM_DEBUG__FIFO__SHIFT 16 +#define KSM_DEBUG__FIFO__WIDTH 16 +#define KSM_DEBUG__FIFO__MASK 0xffff0000U +#define KSM_DEBUG__FIFO__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define KSM_DEBUG__FIFO__RESET_VALUE 0x00000000U +/** @} */ +#define KSM_DEBUG__TYPE uint32_t +#define KSM_DEBUG__READ 0xffffffffU +#define KSM_DEBUG__PRESERVED 0x00000000U +#define KSM_DEBUG__RESET_VALUE 0x00000000U + +#endif /* __KSM_DEBUG_MACRO__ */ + +/** @} end of debug */ + +/* macros for BlueprintGlobalNameSpace::KSM_debug2 */ +/** + * @defgroup at_apb_ksm_regs_core_debug2 debug2 + * @brief Contains register fields associated with debug2. definitions. + * @{ + */ +#ifndef __KSM_DEBUG2_MACRO__ +#define __KSM_DEBUG2_MACRO__ + +/* macros for field kr */ +/** + * @defgroup at_apb_ksm_regs_core_kr_field kr_field + * @brief macros for field kr + * @details how many keys have been released? + * @{ + */ +#define KSM_DEBUG2__KR__SHIFT 0 +#define KSM_DEBUG2__KR__WIDTH 16 +#define KSM_DEBUG2__KR__MASK 0x0000ffffU +#define KSM_DEBUG2__KR__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define KSM_DEBUG2__KR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field kp */ +/** + * @defgroup at_apb_ksm_regs_core_kp_field kp_field + * @brief macros for field kp + * @details how many keys have been pressed? + * @{ + */ +#define KSM_DEBUG2__KP__SHIFT 16 +#define KSM_DEBUG2__KP__WIDTH 16 +#define KSM_DEBUG2__KP__MASK 0xffff0000U +#define KSM_DEBUG2__KP__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define KSM_DEBUG2__KP__RESET_VALUE 0x00000000U +/** @} */ +#define KSM_DEBUG2__TYPE uint32_t +#define KSM_DEBUG2__READ 0xffffffffU +#define KSM_DEBUG2__PRESERVED 0x00000000U +#define KSM_DEBUG2__RESET_VALUE 0x00000000U + +#endif /* __KSM_DEBUG2_MACRO__ */ + +/** @} end of debug2 */ + +/* macros for BlueprintGlobalNameSpace::KSM_core_id */ +/** + * @defgroup at_apb_ksm_regs_core_core_id core_id + * @brief Contains register fields associated with core_id. definitions. + * @{ + */ +#ifndef __KSM_CORE_ID_MACRO__ +#define __KSM_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_ksm_regs_core_id_field id_field + * @brief macros for field id + * @details KSM in ASCII + * @{ + */ +#define KSM_CORE_ID__ID__SHIFT 0 +#define KSM_CORE_ID__ID__WIDTH 32 +#define KSM_CORE_ID__ID__MASK 0xffffffffU +#define KSM_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define KSM_CORE_ID__ID__RESET_VALUE 0x4b534d20U +/** @} */ +#define KSM_CORE_ID__TYPE uint32_t +#define KSM_CORE_ID__READ 0xffffffffU +#define KSM_CORE_ID__PRESERVED 0x00000000U +#define KSM_CORE_ID__RESET_VALUE 0x4b534d20U + +#endif /* __KSM_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of AT_APB_KSM_REGS_CORE */ +#endif /* __REG_AT_APB_KSM_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_apb_pdm_regs_core_macro.h b/ATM33xx-5/include/reg/at_apb_pdm_regs_core_macro.h new file mode 100644 index 0000000..813a25b --- /dev/null +++ b/ATM33xx-5/include/reg/at_apb_pdm_regs_core_macro.h @@ -0,0 +1,2159 @@ +/* */ +/* File: at_apb_pdm_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_apb_pdm_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_APB_PDM_REGS_CORE_H__ +#define __REG_AT_APB_PDM_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_APB_PDM_REGS_CORE at_apb_pdm_regs_core + * @ingroup AT_REG + * @brief at_apb_pdm_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::PDM_control */ +/** + * @defgroup at_apb_pdm_regs_core_control control + * @brief Contains register fields associated with control. definitions. + * @{ + */ +#ifndef __PDM_CONTROL_MACRO__ +#define __PDM_CONTROL_MACRO__ + +/* macros for field enable_dp */ +/** + * @defgroup at_apb_pdm_regs_core_enable_dp_field enable_dp_field + * @brief macros for field enable_dp + * @details enable the datapath + * @{ + */ +#define PDM_CONTROL__ENABLE_DP__SHIFT 0 +#define PDM_CONTROL__ENABLE_DP__WIDTH 1 +#define PDM_CONTROL__ENABLE_DP__MASK 0x00000001U +#define PDM_CONTROL__ENABLE_DP__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PDM_CONTROL__ENABLE_DP__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PDM_CONTROL__ENABLE_DP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PDM_CONTROL__ENABLE_DP__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PDM_CONTROL__ENABLE_DP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PDM_CONTROL__ENABLE_DP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PDM_CONTROL__ENABLE_DP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field capture_on_rising */ +/** + * @defgroup at_apb_pdm_regs_core_capture_on_rising_field capture_on_rising_field + * @brief macros for field capture_on_rising + * @details selects edge of pdm clock to capture pdm data 0= pdm data sampled on falling edge of pdm clock (i.e. pdm data transitions on rising edge of pdm clock) 1= pdm data sampled on rising edge of pdm clock (i.e. pdm data transitions on falling edge of pdm clock) + * @{ + */ +#define PDM_CONTROL__CAPTURE_ON_RISING__SHIFT 1 +#define PDM_CONTROL__CAPTURE_ON_RISING__WIDTH 1 +#define PDM_CONTROL__CAPTURE_ON_RISING__MASK 0x00000002U +#define PDM_CONTROL__CAPTURE_ON_RISING__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PDM_CONTROL__CAPTURE_ON_RISING__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PDM_CONTROL__CAPTURE_ON_RISING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PDM_CONTROL__CAPTURE_ON_RISING__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PDM_CONTROL__CAPTURE_ON_RISING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PDM_CONTROL__CAPTURE_ON_RISING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PDM_CONTROL__CAPTURE_ON_RISING__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field swap_samples */ +/** + * @defgroup at_apb_pdm_regs_core_swap_samples_field swap_samples_field + * @brief macros for field swap_samples + * @details swap packed samples in pingpong buffer location default: former samples uses lsb bits and later samples uses msb bits applies to 16bit samples only + * @{ + */ +#define PDM_CONTROL__SWAP_SAMPLES__SHIFT 2 +#define PDM_CONTROL__SWAP_SAMPLES__WIDTH 1 +#define PDM_CONTROL__SWAP_SAMPLES__MASK 0x00000004U +#define PDM_CONTROL__SWAP_SAMPLES__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PDM_CONTROL__SWAP_SAMPLES__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PDM_CONTROL__SWAP_SAMPLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PDM_CONTROL__SWAP_SAMPLES__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PDM_CONTROL__SWAP_SAMPLES__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PDM_CONTROL__SWAP_SAMPLES__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PDM_CONTROL__SWAP_SAMPLES__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pack_samples */ +/** + * @defgroup at_apb_pdm_regs_core_pack_samples_field pack_samples_field + * @brief macros for field pack_samples + * @details pack samples in ping-pong buffer default: samples are stored unpacked applies to 20/24 bit samples only + * @{ + */ +#define PDM_CONTROL__PACK_SAMPLES__SHIFT 3 +#define PDM_CONTROL__PACK_SAMPLES__WIDTH 1 +#define PDM_CONTROL__PACK_SAMPLES__MASK 0x00000008U +#define PDM_CONTROL__PACK_SAMPLES__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PDM_CONTROL__PACK_SAMPLES__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PDM_CONTROL__PACK_SAMPLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PDM_CONTROL__PACK_SAMPLES__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PDM_CONTROL__PACK_SAMPLES__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PDM_CONTROL__PACK_SAMPLES__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PDM_CONTROL__PACK_SAMPLES__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pdm_clk_sel */ +/** + * @defgroup at_apb_pdm_regs_core_pdm_clk_sel_field pdm_clk_sel_field + * @brief macros for field pdm_clk_sel + * @details pdm clock frequency = f_pclk/(pdm_clk_sel+1) valid range: 3 to 31 possible rates when pcm_rate_sel[0]=1: 31= 500KHz 15= 1MHz 7= 2MHz possible rates when pcm_rate_sel[0]=0: 23= 500KHz 11= 1MHz 5= 2MHz + * @{ + */ +#define PDM_CONTROL__PDM_CLK_SEL__SHIFT 4 +#define PDM_CONTROL__PDM_CLK_SEL__WIDTH 5 +#define PDM_CONTROL__PDM_CLK_SEL__MASK 0x000001f0U +#define PDM_CONTROL__PDM_CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x000001f0U) >> 4) +#define PDM_CONTROL__PDM_CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x000001f0U) +#define PDM_CONTROL__PDM_CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001f0U) | (((uint32_t)(src) <<\ + 4) & 0x000001f0U) +#define PDM_CONTROL__PDM_CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000001f0U))) +#define PDM_CONTROL__PDM_CLK_SEL__RESET_VALUE 0x0000000fU +/** @} */ + +/* macros for field pcm_rate_sel */ +/** + * @defgroup at_apb_pdm_regs_core_pcm_rate_sel_field pcm_rate_sel_field + * @brief macros for field pcm_rate_sel + * @details pcm output rate selection if msb bit3=1 it's in pcm_rate override mode 0= 6KHz 1= 8KHz 2= 12KHz 3= 16KHz 4= 24KHz 5= 32KHz 6= 48KHz 7= 64KHz + * @{ + */ +#define PDM_CONTROL__PCM_RATE_SEL__SHIFT 9 +#define PDM_CONTROL__PCM_RATE_SEL__WIDTH 4 +#define PDM_CONTROL__PCM_RATE_SEL__MASK 0x00001e00U +#define PDM_CONTROL__PCM_RATE_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00001e00U) >> 9) +#define PDM_CONTROL__PCM_RATE_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00001e00U) +#define PDM_CONTROL__PCM_RATE_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001e00U) | (((uint32_t)(src) <<\ + 9) & 0x00001e00U) +#define PDM_CONTROL__PCM_RATE_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00001e00U))) +#define PDM_CONTROL__PCM_RATE_SEL__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field pcm_bit_width */ +/** + * @defgroup at_apb_pdm_regs_core_pcm_bit_width_field pcm_bit_width_field + * @brief macros for field pcm_bit_width + * @details pcm output sample bit width 0= 16bit 1= 20bit 2/3= 24bit + * @{ + */ +#define PDM_CONTROL__PCM_BIT_WIDTH__SHIFT 13 +#define PDM_CONTROL__PCM_BIT_WIDTH__WIDTH 2 +#define PDM_CONTROL__PCM_BIT_WIDTH__MASK 0x00006000U +#define PDM_CONTROL__PCM_BIT_WIDTH__READ(src) \ + (((uint32_t)(src)\ + & 0x00006000U) >> 13) +#define PDM_CONTROL__PCM_BIT_WIDTH__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00006000U) +#define PDM_CONTROL__PCM_BIT_WIDTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00006000U) | (((uint32_t)(src) <<\ + 13) & 0x00006000U) +#define PDM_CONTROL__PCM_BIT_WIDTH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00006000U))) +#define PDM_CONTROL__PCM_BIT_WIDTH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pdm_in_dbg */ +/** + * @defgroup at_apb_pdm_regs_core_pdm_in_dbg_field pdm_in_dbg_field + * @brief macros for field pdm_in_dbg + * @details if 1, bypass pdm bitstream and send in dc value 1 + * @{ + */ +#define PDM_CONTROL__PDM_IN_DBG__SHIFT 15 +#define PDM_CONTROL__PDM_IN_DBG__WIDTH 1 +#define PDM_CONTROL__PDM_IN_DBG__MASK 0x00008000U +#define PDM_CONTROL__PDM_IN_DBG__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define PDM_CONTROL__PDM_IN_DBG__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define PDM_CONTROL__PDM_IN_DBG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define PDM_CONTROL__PDM_IN_DBG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define PDM_CONTROL__PDM_IN_DBG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PDM_CONTROL__PDM_IN_DBG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PDM_CONTROL__PDM_IN_DBG__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field stereo_mode */ +/** + * @defgroup at_apb_pdm_regs_core_stereo_mode_field stereo_mode_field + * @brief macros for field stereo_mode + * @details selects between stereo and mono mode of operation 1= stereo mode; act as datapath enable for other stereo datapath pair. When this bit is set along with enable_dp, it enables stereo datapath pair concurrently to avoid pdm data capture synchronization issues. At that time, corresponding bits for the other datapath pair shouldn't be set. 0= mono mode; use enable_dp bit to enable each datapath. + * @{ + */ +#define PDM_CONTROL__STEREO_MODE__SHIFT 16 +#define PDM_CONTROL__STEREO_MODE__WIDTH 1 +#define PDM_CONTROL__STEREO_MODE__MASK 0x00010000U +#define PDM_CONTROL__STEREO_MODE__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define PDM_CONTROL__STEREO_MODE__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define PDM_CONTROL__STEREO_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define PDM_CONTROL__STEREO_MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define PDM_CONTROL__STEREO_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PDM_CONTROL__STEREO_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PDM_CONTROL__STEREO_MODE__RESET_VALUE 0x00000000U +/** @} */ +#define PDM_CONTROL__TYPE uint32_t +#define PDM_CONTROL__READ 0x0001ffffU +#define PDM_CONTROL__WRITE 0x0001ffffU +#define PDM_CONTROL__PRESERVED 0x00000000U +#define PDM_CONTROL__RESET_VALUE 0x000006f0U + +#endif /* __PDM_CONTROL_MACRO__ */ + +/** @} end of control */ + +/* macros for BlueprintGlobalNameSpace::PDM_filter_config */ +/** + * @defgroup at_apb_pdm_regs_core_filter_config filter_config + * @brief Contains register fields associated with filter_config. definitions. + * @{ + */ +#ifndef __PDM_FILTER_CONFIG_MACRO__ +#define __PDM_FILTER_CONFIG_MACRO__ + +/* macros for field cic_ord */ +/** + * @defgroup at_apb_pdm_regs_core_cic_ord_field cic_ord_field + * @brief macros for field cic_ord + * @details cic order 0= 3rd order 1= 4th order 2/3= unused + * @{ + */ +#define PDM_FILTER_CONFIG__CIC_ORD__SHIFT 0 +#define PDM_FILTER_CONFIG__CIC_ORD__WIDTH 2 +#define PDM_FILTER_CONFIG__CIC_ORD__MASK 0x00000003U +#define PDM_FILTER_CONFIG__CIC_ORD__READ(src) ((uint32_t)(src) & 0x00000003U) +#define PDM_FILTER_CONFIG__CIC_ORD__WRITE(src) ((uint32_t)(src) & 0x00000003U) +#define PDM_FILTER_CONFIG__CIC_ORD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define PDM_FILTER_CONFIG__CIC_ORD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define PDM_FILTER_CONFIG__CIC_ORD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hpf_ord */ +/** + * @defgroup at_apb_pdm_regs_core_hpf_ord_field hpf_ord_field + * @brief macros for field hpf_ord + * @details hpf order 0= 1st order 1= 2nd order 2/3= 3rd order + * @{ + */ +#define PDM_FILTER_CONFIG__HPF_ORD__SHIFT 2 +#define PDM_FILTER_CONFIG__HPF_ORD__WIDTH 2 +#define PDM_FILTER_CONFIG__HPF_ORD__MASK 0x0000000cU +#define PDM_FILTER_CONFIG__HPF_ORD__READ(src) \ + (((uint32_t)(src)\ + & 0x0000000cU) >> 2) +#define PDM_FILTER_CONFIG__HPF_ORD__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000000cU) +#define PDM_FILTER_CONFIG__HPF_ORD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((uint32_t)(src) <<\ + 2) & 0x0000000cU) +#define PDM_FILTER_CONFIG__HPF_ORD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000000cU))) +#define PDM_FILTER_CONFIG__HPF_ORD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hpf_bw */ +/** + * @defgroup at_apb_pdm_regs_core_hpf_bw_field hpf_bw_field + * @brief macros for field hpf_bw + * @details hpf bandwidth selection when hpf_ord=0, bandwidth will be (Hz): 0= 10, 1= 20, 2= 40, 3= 80, 4= 161, 5= 324, 6= 658, 7= 1359 when hpf_ord=1, bandwidth will be (Hz): 0= 9, 1= 19, 2= 37, 3= 75, 4= 151, 5= 304, 6= 616, 7= 1269 when hpf_ord=2, bandwidth will be (Hz): 0= 15, 1= 30, 2= 60, 3= 120, 4= 242, 5= 487, 6= 989, 7= 2036 + * @{ + */ +#define PDM_FILTER_CONFIG__HPF_BW__SHIFT 4 +#define PDM_FILTER_CONFIG__HPF_BW__WIDTH 4 +#define PDM_FILTER_CONFIG__HPF_BW__MASK 0x000000f0U +#define PDM_FILTER_CONFIG__HPF_BW__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define PDM_FILTER_CONFIG__HPF_BW__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x000000f0U) +#define PDM_FILTER_CONFIG__HPF_BW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define PDM_FILTER_CONFIG__HPF_BW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define PDM_FILTER_CONFIG__HPF_BW__RESET_VALUE 0x00000005U +/** @} */ + +/* macros for field hpf_bypass */ +/** + * @defgroup at_apb_pdm_regs_core_hpf_bypass_field hpf_bypass_field + * @brief macros for field hpf_bypass + * @details 1= bypass hpf + * @{ + */ +#define PDM_FILTER_CONFIG__HPF_BYPASS__SHIFT 8 +#define PDM_FILTER_CONFIG__HPF_BYPASS__WIDTH 1 +#define PDM_FILTER_CONFIG__HPF_BYPASS__MASK 0x00000100U +#define PDM_FILTER_CONFIG__HPF_BYPASS__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define PDM_FILTER_CONFIG__HPF_BYPASS__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define PDM_FILTER_CONFIG__HPF_BYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define PDM_FILTER_CONFIG__HPF_BYPASS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define PDM_FILTER_CONFIG__HPF_BYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PDM_FILTER_CONFIG__HPF_BYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PDM_FILTER_CONFIG__HPF_BYPASS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hpf_init_enable */ +/** + * @defgroup at_apb_pdm_regs_core_hpf_init_enable_field hpf_init_enable_field + * @brief macros for field hpf_init_enable + * @details 1= enable hpf initialization + * @{ + */ +#define PDM_FILTER_CONFIG__HPF_INIT_ENABLE__SHIFT 9 +#define PDM_FILTER_CONFIG__HPF_INIT_ENABLE__WIDTH 1 +#define PDM_FILTER_CONFIG__HPF_INIT_ENABLE__MASK 0x00000200U +#define PDM_FILTER_CONFIG__HPF_INIT_ENABLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PDM_FILTER_CONFIG__HPF_INIT_ENABLE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define PDM_FILTER_CONFIG__HPF_INIT_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define PDM_FILTER_CONFIG__HPF_INIT_ENABLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define PDM_FILTER_CONFIG__HPF_INIT_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PDM_FILTER_CONFIG__HPF_INIT_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PDM_FILTER_CONFIG__HPF_INIT_ENABLE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field hpf1_init_shift */ +/** + * @defgroup at_apb_pdm_regs_core_hpf1_init_shift_field hpf1_init_shift_field + * @brief macros for field hpf1_init_shift + * @details hpf1 initialization shift amount, max=10 for values > max, operation is same as max + * @{ + */ +#define PDM_FILTER_CONFIG__HPF1_INIT_SHIFT__SHIFT 10 +#define PDM_FILTER_CONFIG__HPF1_INIT_SHIFT__WIDTH 4 +#define PDM_FILTER_CONFIG__HPF1_INIT_SHIFT__MASK 0x00003c00U +#define PDM_FILTER_CONFIG__HPF1_INIT_SHIFT__READ(src) \ + (((uint32_t)(src)\ + & 0x00003c00U) >> 10) +#define PDM_FILTER_CONFIG__HPF1_INIT_SHIFT__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00003c00U) +#define PDM_FILTER_CONFIG__HPF1_INIT_SHIFT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003c00U) | (((uint32_t)(src) <<\ + 10) & 0x00003c00U) +#define PDM_FILTER_CONFIG__HPF1_INIT_SHIFT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00003c00U))) +#define PDM_FILTER_CONFIG__HPF1_INIT_SHIFT__RESET_VALUE 0x0000000aU +/** @} */ + +/* macros for field hpf2_init_shift */ +/** + * @defgroup at_apb_pdm_regs_core_hpf2_init_shift_field hpf2_init_shift_field + * @brief macros for field hpf2_init_shift + * @details hpf2 initialization shift amount, max=24 for values > max, operation is same as max + * @{ + */ +#define PDM_FILTER_CONFIG__HPF2_INIT_SHIFT__SHIFT 14 +#define PDM_FILTER_CONFIG__HPF2_INIT_SHIFT__WIDTH 5 +#define PDM_FILTER_CONFIG__HPF2_INIT_SHIFT__MASK 0x0007c000U +#define PDM_FILTER_CONFIG__HPF2_INIT_SHIFT__READ(src) \ + (((uint32_t)(src)\ + & 0x0007c000U) >> 14) +#define PDM_FILTER_CONFIG__HPF2_INIT_SHIFT__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0007c000U) +#define PDM_FILTER_CONFIG__HPF2_INIT_SHIFT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007c000U) | (((uint32_t)(src) <<\ + 14) & 0x0007c000U) +#define PDM_FILTER_CONFIG__HPF2_INIT_SHIFT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0007c000U))) +#define PDM_FILTER_CONFIG__HPF2_INIT_SHIFT__RESET_VALUE 0x00000018U +/** @} */ + +/* macros for field hbf_bypass_ovrd_val */ +/** + * @defgroup at_apb_pdm_regs_core_hbf_bypass_ovrd_val_field hbf_bypass_ovrd_val_field + * @brief macros for field hbf_bypass_ovrd_val + * @details hbf bypass override value used only during pcm_rate override mode: 0= enable hbf 1= bypass hbf; output rate=input rate + * @{ + */ +#define PDM_FILTER_CONFIG__HBF_BYPASS_OVRD_VAL__SHIFT 19 +#define PDM_FILTER_CONFIG__HBF_BYPASS_OVRD_VAL__WIDTH 1 +#define PDM_FILTER_CONFIG__HBF_BYPASS_OVRD_VAL__MASK 0x00080000U +#define PDM_FILTER_CONFIG__HBF_BYPASS_OVRD_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define PDM_FILTER_CONFIG__HBF_BYPASS_OVRD_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define PDM_FILTER_CONFIG__HBF_BYPASS_OVRD_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define PDM_FILTER_CONFIG__HBF_BYPASS_OVRD_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define PDM_FILTER_CONFIG__HBF_BYPASS_OVRD_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define PDM_FILTER_CONFIG__HBF_BYPASS_OVRD_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define PDM_FILTER_CONFIG__HBF_BYPASS_OVRD_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field lpf_bw */ +/** + * @defgroup at_apb_pdm_regs_core_lpf_bw_field lpf_bw_field + * @brief macros for field lpf_bw + * @details lpf bandwidth override selection used only during pcm_rate override mode: if pcm_rate_sel[0]=1, bandwidth will be (KHz): 0= 4 1= 6 2= 8 3= 10 4= 12 5= 14 6/7= 15.5 if pcm_rate_sel[0]=0, bandwidth will be (KHz): 0= 3 1= 4.5 2= 6 3= 7.5 4= 9 5= 10 6/7= 11.5 + * @{ + */ +#define PDM_FILTER_CONFIG__LPF_BW__SHIFT 20 +#define PDM_FILTER_CONFIG__LPF_BW__WIDTH 3 +#define PDM_FILTER_CONFIG__LPF_BW__MASK 0x00700000U +#define PDM_FILTER_CONFIG__LPF_BW__READ(src) \ + (((uint32_t)(src)\ + & 0x00700000U) >> 20) +#define PDM_FILTER_CONFIG__LPF_BW__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00700000U) +#define PDM_FILTER_CONFIG__LPF_BW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((uint32_t)(src) <<\ + 20) & 0x00700000U) +#define PDM_FILTER_CONFIG__LPF_BW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00700000U))) +#define PDM_FILTER_CONFIG__LPF_BW__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field lpf_bypass_ovrd_val */ +/** + * @defgroup at_apb_pdm_regs_core_lpf_bypass_ovrd_val_field lpf_bypass_ovrd_val_field + * @brief macros for field lpf_bypass_ovrd_val + * @details lpf bypass override value used only during pcm_rate override mode: 0= enable lpf 1= bypass lpf; output rate=input rate + * @{ + */ +#define PDM_FILTER_CONFIG__LPF_BYPASS_OVRD_VAL__SHIFT 23 +#define PDM_FILTER_CONFIG__LPF_BYPASS_OVRD_VAL__WIDTH 1 +#define PDM_FILTER_CONFIG__LPF_BYPASS_OVRD_VAL__MASK 0x00800000U +#define PDM_FILTER_CONFIG__LPF_BYPASS_OVRD_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PDM_FILTER_CONFIG__LPF_BYPASS_OVRD_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define PDM_FILTER_CONFIG__LPF_BYPASS_OVRD_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define PDM_FILTER_CONFIG__LPF_BYPASS_OVRD_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define PDM_FILTER_CONFIG__LPF_BYPASS_OVRD_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PDM_FILTER_CONFIG__LPF_BYPASS_OVRD_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PDM_FILTER_CONFIG__LPF_BYPASS_OVRD_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field downsample_ratio */ +/** + * @defgroup at_apb_pdm_regs_core_downsample_ratio_field downsample_ratio_field + * @brief macros for field downsample_ratio + * @details downsample override used only during pcm_rate override mode: downsampling by 1/(1+downsample_ratio) + * @{ + */ +#define PDM_FILTER_CONFIG__DOWNSAMPLE_RATIO__SHIFT 24 +#define PDM_FILTER_CONFIG__DOWNSAMPLE_RATIO__WIDTH 2 +#define PDM_FILTER_CONFIG__DOWNSAMPLE_RATIO__MASK 0x03000000U +#define PDM_FILTER_CONFIG__DOWNSAMPLE_RATIO__READ(src) \ + (((uint32_t)(src)\ + & 0x03000000U) >> 24) +#define PDM_FILTER_CONFIG__DOWNSAMPLE_RATIO__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x03000000U) +#define PDM_FILTER_CONFIG__DOWNSAMPLE_RATIO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((uint32_t)(src) <<\ + 24) & 0x03000000U) +#define PDM_FILTER_CONFIG__DOWNSAMPLE_RATIO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x03000000U))) +#define PDM_FILTER_CONFIG__DOWNSAMPLE_RATIO__RESET_VALUE 0x00000000U +/** @} */ +#define PDM_FILTER_CONFIG__TYPE uint32_t +#define PDM_FILTER_CONFIG__READ 0x03ffffffU +#define PDM_FILTER_CONFIG__WRITE 0x03ffffffU +#define PDM_FILTER_CONFIG__PRESERVED 0x00000000U +#define PDM_FILTER_CONFIG__RESET_VALUE 0x00062a50U + +#endif /* __PDM_FILTER_CONFIG_MACRO__ */ + +/** @} end of filter_config */ + +/* macros for BlueprintGlobalNameSpace::PDM_filter_config1 */ +/** + * @defgroup at_apb_pdm_regs_core_filter_config1 filter_config1 + * @brief Contains register fields associated with filter_config1. definitions. + * @{ + */ +#ifndef __PDM_FILTER_CONFIG1_MACRO__ +#define __PDM_FILTER_CONFIG1_MACRO__ + +/* macros for field interp_bypass */ +/** + * @defgroup at_apb_pdm_regs_core_interp_bypass_field interp_bypass_field + * @brief macros for field interp_bypass + * @details 1= bypass interpolator, also resets the fir filter taps + * @{ + */ +#define PDM_FILTER_CONFIG1__INTERP_BYPASS__SHIFT 0 +#define PDM_FILTER_CONFIG1__INTERP_BYPASS__WIDTH 1 +#define PDM_FILTER_CONFIG1__INTERP_BYPASS__MASK 0x00000001U +#define PDM_FILTER_CONFIG1__INTERP_BYPASS__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PDM_FILTER_CONFIG1__INTERP_BYPASS__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PDM_FILTER_CONFIG1__INTERP_BYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PDM_FILTER_CONFIG1__INTERP_BYPASS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PDM_FILTER_CONFIG1__INTERP_BYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PDM_FILTER_CONFIG1__INTERP_BYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PDM_FILTER_CONFIG1__INTERP_BYPASS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field interp_skp_sample */ +/** + * @defgroup at_apb_pdm_regs_core_interp_skp_sample_field interp_skp_sample_field + * @brief macros for field interp_skp_sample + * @details skip one sample to accomodate cfo frequency drift, auto-clear + * @{ + */ +#define PDM_FILTER_CONFIG1__INTERP_SKP_SAMPLE__SHIFT 1 +#define PDM_FILTER_CONFIG1__INTERP_SKP_SAMPLE__WIDTH 1 +#define PDM_FILTER_CONFIG1__INTERP_SKP_SAMPLE__MASK 0x00000002U +#define PDM_FILTER_CONFIG1__INTERP_SKP_SAMPLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PDM_FILTER_CONFIG1__INTERP_SKP_SAMPLE__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PDM_FILTER_CONFIG1__INTERP_SKP_SAMPLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PDM_FILTER_CONFIG1__INTERP_SKP_SAMPLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PDM_FILTER_CONFIG1__INTERP_SKP_SAMPLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PDM_FILTER_CONFIG1__INTERP_SKP_SAMPLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PDM_FILTER_CONFIG1__INTERP_SKP_SAMPLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field interp_add_sample */ +/** + * @defgroup at_apb_pdm_regs_core_interp_add_sample_field interp_add_sample_field + * @brief macros for field interp_add_sample + * @details add one sample to accomodate cfo frequency drift, auto-clear + * @{ + */ +#define PDM_FILTER_CONFIG1__INTERP_ADD_SAMPLE__SHIFT 2 +#define PDM_FILTER_CONFIG1__INTERP_ADD_SAMPLE__WIDTH 1 +#define PDM_FILTER_CONFIG1__INTERP_ADD_SAMPLE__MASK 0x00000004U +#define PDM_FILTER_CONFIG1__INTERP_ADD_SAMPLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PDM_FILTER_CONFIG1__INTERP_ADD_SAMPLE__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PDM_FILTER_CONFIG1__INTERP_ADD_SAMPLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PDM_FILTER_CONFIG1__INTERP_ADD_SAMPLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PDM_FILTER_CONFIG1__INTERP_ADD_SAMPLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PDM_FILTER_CONFIG1__INTERP_ADD_SAMPLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PDM_FILTER_CONFIG1__INTERP_ADD_SAMPLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field interp_ph_idx0 */ +/** + * @defgroup at_apb_pdm_regs_core_interp_ph_idx0_field interp_ph_idx0_field + * @brief macros for field interp_ph_idx0 + * @details index-0 into interpolator coefficient table + * @{ + */ +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX0__SHIFT 3 +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX0__WIDTH 8 +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX0__MASK 0x000007f8U +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX0__READ(src) \ + (((uint32_t)(src)\ + & 0x000007f8U) >> 3) +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX0__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x000007f8U) +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007f8U) | (((uint32_t)(src) <<\ + 3) & 0x000007f8U) +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x000007f8U))) +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX0__RESET_VALUE 0x0000007fU +/** @} */ + +/* macros for field interp_ph_idx1 */ +/** + * @defgroup at_apb_pdm_regs_core_interp_ph_idx1_field interp_ph_idx1_field + * @brief macros for field interp_ph_idx1 + * @details index-1 into interpolator coefficient table; for use only when add sample + * @{ + */ +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX1__SHIFT 11 +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX1__WIDTH 8 +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX1__MASK 0x0007f800U +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX1__READ(src) \ + (((uint32_t)(src)\ + & 0x0007f800U) >> 11) +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX1__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x0007f800U) +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007f800U) | (((uint32_t)(src) <<\ + 11) & 0x0007f800U) +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x0007f800U))) +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field interp_ph_idx_updt */ +/** + * @defgroup at_apb_pdm_regs_core_interp_ph_idx_updt_field interp_ph_idx_updt_field + * @brief macros for field interp_ph_idx_updt + * @details interpolator phase indices update indicator for HW to capture, auto-clear + * @{ + */ +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX_UPDT__SHIFT 19 +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX_UPDT__WIDTH 1 +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX_UPDT__MASK 0x00080000U +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX_UPDT__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX_UPDT__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX_UPDT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX_UPDT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX_UPDT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX_UPDT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define PDM_FILTER_CONFIG1__INTERP_PH_IDX_UPDT__RESET_VALUE 0x00000000U +/** @} */ +#define PDM_FILTER_CONFIG1__TYPE uint32_t +#define PDM_FILTER_CONFIG1__READ 0x000fffffU +#define PDM_FILTER_CONFIG1__WRITE 0x000fffffU +#define PDM_FILTER_CONFIG1__PRESERVED 0x00000000U +#define PDM_FILTER_CONFIG1__RESET_VALUE 0x000003f8U + +#endif /* __PDM_FILTER_CONFIG1_MACRO__ */ + +/** @} end of filter_config1 */ + +/* macros for BlueprintGlobalNameSpace::PDM_gain_control_config */ +/** + * @defgroup at_apb_pdm_regs_core_gain_control_config gain_control_config + * @brief Contains register fields associated with gain_control_config. definitions. + * @{ + */ +#ifndef __PDM_GAIN_CONTROL_CONFIG_MACRO__ +#define __PDM_GAIN_CONTROL_CONFIG_MACRO__ + +/* macros for field code */ +/** + * @defgroup at_apb_pdm_regs_core_code_field code_field + * @brief macros for field code + * @details gain code for LUT + * @{ + */ +#define PDM_GAIN_CONTROL_CONFIG__CODE__SHIFT 0 +#define PDM_GAIN_CONTROL_CONFIG__CODE__WIDTH 7 +#define PDM_GAIN_CONTROL_CONFIG__CODE__MASK 0x0000007fU +#define PDM_GAIN_CONTROL_CONFIG__CODE__READ(src) \ + ((uint32_t)(src)\ + & 0x0000007fU) +#define PDM_GAIN_CONTROL_CONFIG__CODE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000007fU) +#define PDM_GAIN_CONTROL_CONFIG__CODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define PDM_GAIN_CONTROL_CONFIG__CODE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000007fU))) +#define PDM_GAIN_CONTROL_CONFIG__CODE__RESET_VALUE 0x00000040U +/** @} */ + +/* macros for field cic_gain_sel */ +/** + * @defgroup at_apb_pdm_regs_core_cic_gain_sel_field cic_gain_sel_field + * @brief macros for field cic_gain_sel + * @details allow gain-scaling at the output of cic through bit shifting zero-padding for left shift; rounding, dropping lsbs for right shift. 0= no scaling 1-4= up scaling; zero-padding +1 to +4 respectively 5-7= down scaling; dropping lsbs -1 to -3 respectively + * @{ + */ +#define PDM_GAIN_CONTROL_CONFIG__CIC_GAIN_SEL__SHIFT 7 +#define PDM_GAIN_CONTROL_CONFIG__CIC_GAIN_SEL__WIDTH 3 +#define PDM_GAIN_CONTROL_CONFIG__CIC_GAIN_SEL__MASK 0x00000380U +#define PDM_GAIN_CONTROL_CONFIG__CIC_GAIN_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000380U) >> 7) +#define PDM_GAIN_CONTROL_CONFIG__CIC_GAIN_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000380U) +#define PDM_GAIN_CONTROL_CONFIG__CIC_GAIN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000380U) | (((uint32_t)(src) <<\ + 7) & 0x00000380U) +#define PDM_GAIN_CONTROL_CONFIG__CIC_GAIN_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000380U))) +#define PDM_GAIN_CONTROL_CONFIG__CIC_GAIN_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hpf_gain_sel */ +/** + * @defgroup at_apb_pdm_regs_core_hpf_gain_sel_field hpf_gain_sel_field + * @brief macros for field hpf_gain_sel + * @details allow gain-scaling at the output of hpf through bit shifting zero-padding for left shift; rounding, dropping lsbs for right shift. 0= no scaling 1-4= up scaling; zero-padding +1 to +4 respectively 5-7= down scaling; dropping lsbs -1 to -3 respectively + * @{ + */ +#define PDM_GAIN_CONTROL_CONFIG__HPF_GAIN_SEL__SHIFT 10 +#define PDM_GAIN_CONTROL_CONFIG__HPF_GAIN_SEL__WIDTH 3 +#define PDM_GAIN_CONTROL_CONFIG__HPF_GAIN_SEL__MASK 0x00001c00U +#define PDM_GAIN_CONTROL_CONFIG__HPF_GAIN_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00001c00U) >> 10) +#define PDM_GAIN_CONTROL_CONFIG__HPF_GAIN_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00001c00U) +#define PDM_GAIN_CONTROL_CONFIG__HPF_GAIN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001c00U) | (((uint32_t)(src) <<\ + 10) & 0x00001c00U) +#define PDM_GAIN_CONTROL_CONFIG__HPF_GAIN_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00001c00U))) +#define PDM_GAIN_CONTROL_CONFIG__HPF_GAIN_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hbf_gain_sel */ +/** + * @defgroup at_apb_pdm_regs_core_hbf_gain_sel_field hbf_gain_sel_field + * @brief macros for field hbf_gain_sel + * @details allow gain-scaling at the output of hbf through bit shifting zero-padding for left shift; rounding, dropping lsbs for right shift. 0= no scaling 1-4= up scaling; zero-padding +1 to +4 respectively 5-7= down scaling; dropping lsbs -1 to -3 respectively + * @{ + */ +#define PDM_GAIN_CONTROL_CONFIG__HBF_GAIN_SEL__SHIFT 13 +#define PDM_GAIN_CONTROL_CONFIG__HBF_GAIN_SEL__WIDTH 3 +#define PDM_GAIN_CONTROL_CONFIG__HBF_GAIN_SEL__MASK 0x0000e000U +#define PDM_GAIN_CONTROL_CONFIG__HBF_GAIN_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x0000e000U) >> 13) +#define PDM_GAIN_CONTROL_CONFIG__HBF_GAIN_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0000e000U) +#define PDM_GAIN_CONTROL_CONFIG__HBF_GAIN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((uint32_t)(src) <<\ + 13) & 0x0000e000U) +#define PDM_GAIN_CONTROL_CONFIG__HBF_GAIN_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0000e000U))) +#define PDM_GAIN_CONTROL_CONFIG__HBF_GAIN_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define PDM_GAIN_CONTROL_CONFIG__TYPE uint32_t +#define PDM_GAIN_CONTROL_CONFIG__READ 0x0000ffffU +#define PDM_GAIN_CONTROL_CONFIG__WRITE 0x0000ffffU +#define PDM_GAIN_CONTROL_CONFIG__PRESERVED 0x00000000U +#define PDM_GAIN_CONTROL_CONFIG__RESET_VALUE 0x00000040U + +#endif /* __PDM_GAIN_CONTROL_CONFIG_MACRO__ */ + +/** @} end of gain_control_config */ + +/* macros for BlueprintGlobalNameSpace::PDM_pcm_sample */ +/** + * @defgroup at_apb_pdm_regs_core_pcm_sample pcm_sample + * @brief A read of this register pops data FIFO definitions. + * @{ + */ +#ifndef __PDM_PCM_SAMPLE_MACRO__ +#define __PDM_PCM_SAMPLE_MACRO__ + +/* macros for field data */ +/** + * @defgroup at_apb_pdm_regs_core_data_field data_field + * @brief macros for field data + * @details signed, twos complement + * @{ + */ +#define PDM_PCM_SAMPLE__DATA__SHIFT 0 +#define PDM_PCM_SAMPLE__DATA__WIDTH 24 +#define PDM_PCM_SAMPLE__DATA__MASK 0x00ffffffU +#define PDM_PCM_SAMPLE__DATA__READ(src) ((uint32_t)(src) & 0x00ffffffU) +#define PDM_PCM_SAMPLE__DATA__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field empty */ +/** + * @defgroup at_apb_pdm_regs_core_empty_field empty_field + * @brief macros for field empty + * @details if 1, ignore data sample because fifo has been drained + * @{ + */ +#define PDM_PCM_SAMPLE__EMPTY__SHIFT 31 +#define PDM_PCM_SAMPLE__EMPTY__WIDTH 1 +#define PDM_PCM_SAMPLE__EMPTY__MASK 0x80000000U +#define PDM_PCM_SAMPLE__EMPTY__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define PDM_PCM_SAMPLE__EMPTY__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PDM_PCM_SAMPLE__EMPTY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PDM_PCM_SAMPLE__EMPTY__RESET_VALUE 0x00000000U +/** @} */ +#define PDM_PCM_SAMPLE__TYPE uint32_t +#define PDM_PCM_SAMPLE__READ 0x80ffffffU +#define PDM_PCM_SAMPLE__PRESERVED 0x00000000U +#define PDM_PCM_SAMPLE__RESET_VALUE 0x00000000U + +#endif /* __PDM_PCM_SAMPLE_MACRO__ */ + +/** @} end of pcm_sample */ + +/* macros for BlueprintGlobalNameSpace::PDM_fifo_debug */ +/** + * @defgroup at_apb_pdm_regs_core_fifo_debug fifo_debug + * @brief Contains register fields associated with fifo_debug. definitions. + * @{ + */ +#ifndef __PDM_FIFO_DEBUG_MACRO__ +#define __PDM_FIFO_DEBUG_MACRO__ + +/* macros for field status */ +/** + * @defgroup at_apb_pdm_regs_core_status_field status_field + * @brief macros for field status + * @details {overrun, underrun, full, empty, 4'd0, rdaddr(unsigned int; 4b), wraddr(unsigned int; 4b)} + * @{ + */ +#define PDM_FIFO_DEBUG__STATUS__SHIFT 0 +#define PDM_FIFO_DEBUG__STATUS__WIDTH 16 +#define PDM_FIFO_DEBUG__STATUS__MASK 0x0000ffffU +#define PDM_FIFO_DEBUG__STATUS__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define PDM_FIFO_DEBUG__STATUS__RESET_VALUE 0x00000000U +/** @} */ +#define PDM_FIFO_DEBUG__TYPE uint32_t +#define PDM_FIFO_DEBUG__READ 0x0000ffffU +#define PDM_FIFO_DEBUG__PRESERVED 0x00000000U +#define PDM_FIFO_DEBUG__RESET_VALUE 0x00000000U + +#endif /* __PDM_FIFO_DEBUG_MACRO__ */ + +/** @} end of fifo_debug */ + +/* macros for BlueprintGlobalNameSpace::PDM_interrupts */ +/** + * @defgroup at_apb_pdm_regs_core_interrupts interrupts + * @brief Contains register fields associated with interrupts. definitions. + * @{ + */ +#ifndef __PDM_INTERRUPTS_MACRO__ +#define __PDM_INTERRUPTS_MACRO__ + +/* macros for field intrpt0 */ +/** + * @defgroup at_apb_pdm_regs_core_intrpt0_field intrpt0_field + * @brief macros for field intrpt0 + * @details interpolator done processing current pcm sample + * @{ + */ +#define PDM_INTERRUPTS__INTRPT0__SHIFT 0 +#define PDM_INTERRUPTS__INTRPT0__WIDTH 1 +#define PDM_INTERRUPTS__INTRPT0__MASK 0x00000001U +#define PDM_INTERRUPTS__INTRPT0__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PDM_INTERRUPTS__INTRPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PDM_INTERRUPTS__INTRPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PDM_INTERRUPTS__INTRPT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrpt1 */ +/** + * @defgroup at_apb_pdm_regs_core_intrpt1_field intrpt1_field + * @brief macros for field intrpt1 + * @details hw wrote to ping pong buffer + * @{ + */ +#define PDM_INTERRUPTS__INTRPT1__SHIFT 1 +#define PDM_INTERRUPTS__INTRPT1__WIDTH 1 +#define PDM_INTERRUPTS__INTRPT1__MASK 0x00000002U +#define PDM_INTERRUPTS__INTRPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PDM_INTERRUPTS__INTRPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PDM_INTERRUPTS__INTRPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PDM_INTERRUPTS__INTRPT1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrpt2 */ +/** + * @defgroup at_apb_pdm_regs_core_intrpt2_field intrpt2_field + * @brief macros for field intrpt2 + * @details ping pong buffer A is locked and needs to be emptied + * @{ + */ +#define PDM_INTERRUPTS__INTRPT2__SHIFT 2 +#define PDM_INTERRUPTS__INTRPT2__WIDTH 1 +#define PDM_INTERRUPTS__INTRPT2__MASK 0x00000004U +#define PDM_INTERRUPTS__INTRPT2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PDM_INTERRUPTS__INTRPT2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PDM_INTERRUPTS__INTRPT2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PDM_INTERRUPTS__INTRPT2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrpt3 */ +/** + * @defgroup at_apb_pdm_regs_core_intrpt3_field intrpt3_field + * @brief macros for field intrpt3 + * @details ping pong buffer B is locked and needs to be emptied + * @{ + */ +#define PDM_INTERRUPTS__INTRPT3__SHIFT 3 +#define PDM_INTERRUPTS__INTRPT3__WIDTH 1 +#define PDM_INTERRUPTS__INTRPT3__MASK 0x00000008U +#define PDM_INTERRUPTS__INTRPT3__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PDM_INTERRUPTS__INTRPT3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PDM_INTERRUPTS__INTRPT3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PDM_INTERRUPTS__INTRPT3__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrpt4 */ +/** + * @defgroup at_apb_pdm_regs_core_intrpt4_field intrpt4_field + * @brief macros for field intrpt4 + * @details error in buffer A; hw wants to write to buffer but lock hasn't been released by sw + * @{ + */ +#define PDM_INTERRUPTS__INTRPT4__SHIFT 4 +#define PDM_INTERRUPTS__INTRPT4__WIDTH 1 +#define PDM_INTERRUPTS__INTRPT4__MASK 0x00000010U +#define PDM_INTERRUPTS__INTRPT4__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PDM_INTERRUPTS__INTRPT4__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PDM_INTERRUPTS__INTRPT4__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PDM_INTERRUPTS__INTRPT4__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrpt5 */ +/** + * @defgroup at_apb_pdm_regs_core_intrpt5_field intrpt5_field + * @brief macros for field intrpt5 + * @details error in buffer B; hw wants to write to buffer but lock hasn't been released by sw + * @{ + */ +#define PDM_INTERRUPTS__INTRPT5__SHIFT 5 +#define PDM_INTERRUPTS__INTRPT5__WIDTH 1 +#define PDM_INTERRUPTS__INTRPT5__MASK 0x00000020U +#define PDM_INTERRUPTS__INTRPT5__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PDM_INTERRUPTS__INTRPT5__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PDM_INTERRUPTS__INTRPT5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PDM_INTERRUPTS__INTRPT5__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrpt6 */ +/** + * @defgroup at_apb_pdm_regs_core_intrpt6_field intrpt6_field + * @brief macros for field intrpt6 + * @details ping pong buffer C is locked and needs to be emptied + * @{ + */ +#define PDM_INTERRUPTS__INTRPT6__SHIFT 6 +#define PDM_INTERRUPTS__INTRPT6__WIDTH 1 +#define PDM_INTERRUPTS__INTRPT6__MASK 0x00000040U +#define PDM_INTERRUPTS__INTRPT6__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define PDM_INTERRUPTS__INTRPT6__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PDM_INTERRUPTS__INTRPT6__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PDM_INTERRUPTS__INTRPT6__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrpt7 */ +/** + * @defgroup at_apb_pdm_regs_core_intrpt7_field intrpt7_field + * @brief macros for field intrpt7 + * @details ping pong buffer D is locked and needs to be emptied + * @{ + */ +#define PDM_INTERRUPTS__INTRPT7__SHIFT 7 +#define PDM_INTERRUPTS__INTRPT7__WIDTH 1 +#define PDM_INTERRUPTS__INTRPT7__MASK 0x00000080U +#define PDM_INTERRUPTS__INTRPT7__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define PDM_INTERRUPTS__INTRPT7__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define PDM_INTERRUPTS__INTRPT7__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define PDM_INTERRUPTS__INTRPT7__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrpt8 */ +/** + * @defgroup at_apb_pdm_regs_core_intrpt8_field intrpt8_field + * @brief macros for field intrpt8 + * @details error in buffer C; hw wants to write to buffer but lock hasn't been released by sw + * @{ + */ +#define PDM_INTERRUPTS__INTRPT8__SHIFT 8 +#define PDM_INTERRUPTS__INTRPT8__WIDTH 1 +#define PDM_INTERRUPTS__INTRPT8__MASK 0x00000100U +#define PDM_INTERRUPTS__INTRPT8__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define PDM_INTERRUPTS__INTRPT8__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PDM_INTERRUPTS__INTRPT8__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PDM_INTERRUPTS__INTRPT8__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrpt9 */ +/** + * @defgroup at_apb_pdm_regs_core_intrpt9_field intrpt9_field + * @brief macros for field intrpt9 + * @details error in buffer D; hw wants to write to buffer but lock hasn't been released by sw + * @{ + */ +#define PDM_INTERRUPTS__INTRPT9__SHIFT 9 +#define PDM_INTERRUPTS__INTRPT9__WIDTH 1 +#define PDM_INTERRUPTS__INTRPT9__MASK 0x00000200U +#define PDM_INTERRUPTS__INTRPT9__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PDM_INTERRUPTS__INTRPT9__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PDM_INTERRUPTS__INTRPT9__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PDM_INTERRUPTS__INTRPT9__RESET_VALUE 0x00000000U +/** @} */ +#define PDM_INTERRUPTS__TYPE uint32_t +#define PDM_INTERRUPTS__READ 0x000003ffU +#define PDM_INTERRUPTS__PRESERVED 0x00000000U +#define PDM_INTERRUPTS__RESET_VALUE 0x00000000U + +#endif /* __PDM_INTERRUPTS_MACRO__ */ + +/** @} end of interrupts */ + +/* macros for BlueprintGlobalNameSpace::PDM_interrupt_mask */ +/** + * @defgroup at_apb_pdm_regs_core_interrupt_mask interrupt_mask + * @brief Contains register fields associated with interrupt_mask. definitions. + * @{ + */ +#ifndef __PDM_INTERRUPT_MASK_MACRO__ +#define __PDM_INTERRUPT_MASK_MACRO__ + +/* macros for field mask_intrpt0 */ +/** + * @defgroup at_apb_pdm_regs_core_mask_intrpt0_field mask_intrpt0_field + * @brief macros for field mask_intrpt0 + * @details allow intrpt0 to propogate to core's single output interrupt + * @{ + */ +#define PDM_INTERRUPT_MASK__MASK_INTRPT0__SHIFT 0 +#define PDM_INTERRUPT_MASK__MASK_INTRPT0__WIDTH 1 +#define PDM_INTERRUPT_MASK__MASK_INTRPT0__MASK 0x00000001U +#define PDM_INTERRUPT_MASK__MASK_INTRPT0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT0__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PDM_INTERRUPT_MASK__MASK_INTRPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PDM_INTERRUPT_MASK__MASK_INTRPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PDM_INTERRUPT_MASK__MASK_INTRPT0__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field mask_intrpt1 */ +/** + * @defgroup at_apb_pdm_regs_core_mask_intrpt1_field mask_intrpt1_field + * @brief macros for field mask_intrpt1 + * @details allow intrpt1 to propogate to core's single output interrupt + * @{ + */ +#define PDM_INTERRUPT_MASK__MASK_INTRPT1__SHIFT 1 +#define PDM_INTERRUPT_MASK__MASK_INTRPT1__WIDTH 1 +#define PDM_INTERRUPT_MASK__MASK_INTRPT1__MASK 0x00000002U +#define PDM_INTERRUPT_MASK__MASK_INTRPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PDM_INTERRUPT_MASK__MASK_INTRPT1__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PDM_INTERRUPT_MASK__MASK_INTRPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PDM_INTERRUPT_MASK__MASK_INTRPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PDM_INTERRUPT_MASK__MASK_INTRPT1__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field mask_intrpt2 */ +/** + * @defgroup at_apb_pdm_regs_core_mask_intrpt2_field mask_intrpt2_field + * @brief macros for field mask_intrpt2 + * @details allow intrpt2 to propogate to core's single output interrupt + * @{ + */ +#define PDM_INTERRUPT_MASK__MASK_INTRPT2__SHIFT 2 +#define PDM_INTERRUPT_MASK__MASK_INTRPT2__WIDTH 1 +#define PDM_INTERRUPT_MASK__MASK_INTRPT2__MASK 0x00000004U +#define PDM_INTERRUPT_MASK__MASK_INTRPT2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PDM_INTERRUPT_MASK__MASK_INTRPT2__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PDM_INTERRUPT_MASK__MASK_INTRPT2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PDM_INTERRUPT_MASK__MASK_INTRPT2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PDM_INTERRUPT_MASK__MASK_INTRPT2__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field mask_intrpt3 */ +/** + * @defgroup at_apb_pdm_regs_core_mask_intrpt3_field mask_intrpt3_field + * @brief macros for field mask_intrpt3 + * @details allow intrpt3 to propogate to core's single output interrupt + * @{ + */ +#define PDM_INTERRUPT_MASK__MASK_INTRPT3__SHIFT 3 +#define PDM_INTERRUPT_MASK__MASK_INTRPT3__WIDTH 1 +#define PDM_INTERRUPT_MASK__MASK_INTRPT3__MASK 0x00000008U +#define PDM_INTERRUPT_MASK__MASK_INTRPT3__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PDM_INTERRUPT_MASK__MASK_INTRPT3__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PDM_INTERRUPT_MASK__MASK_INTRPT3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PDM_INTERRUPT_MASK__MASK_INTRPT3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PDM_INTERRUPT_MASK__MASK_INTRPT3__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field mask_intrpt4 */ +/** + * @defgroup at_apb_pdm_regs_core_mask_intrpt4_field mask_intrpt4_field + * @brief macros for field mask_intrpt4 + * @details allow intrpt4 to propogate to core's single output interrupt + * @{ + */ +#define PDM_INTERRUPT_MASK__MASK_INTRPT4__SHIFT 4 +#define PDM_INTERRUPT_MASK__MASK_INTRPT4__WIDTH 1 +#define PDM_INTERRUPT_MASK__MASK_INTRPT4__MASK 0x00000010U +#define PDM_INTERRUPT_MASK__MASK_INTRPT4__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PDM_INTERRUPT_MASK__MASK_INTRPT4__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT4__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PDM_INTERRUPT_MASK__MASK_INTRPT4__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PDM_INTERRUPT_MASK__MASK_INTRPT4__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PDM_INTERRUPT_MASK__MASK_INTRPT4__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field mask_intrpt5 */ +/** + * @defgroup at_apb_pdm_regs_core_mask_intrpt5_field mask_intrpt5_field + * @brief macros for field mask_intrpt5 + * @details allow intrpt5 to propogate to core's single output interrupt + * @{ + */ +#define PDM_INTERRUPT_MASK__MASK_INTRPT5__SHIFT 5 +#define PDM_INTERRUPT_MASK__MASK_INTRPT5__WIDTH 1 +#define PDM_INTERRUPT_MASK__MASK_INTRPT5__MASK 0x00000020U +#define PDM_INTERRUPT_MASK__MASK_INTRPT5__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PDM_INTERRUPT_MASK__MASK_INTRPT5__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT5__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define PDM_INTERRUPT_MASK__MASK_INTRPT5__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PDM_INTERRUPT_MASK__MASK_INTRPT5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PDM_INTERRUPT_MASK__MASK_INTRPT5__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field mask_intrpt6 */ +/** + * @defgroup at_apb_pdm_regs_core_mask_intrpt6_field mask_intrpt6_field + * @brief macros for field mask_intrpt6 + * @details allow intrpt6 to propogate to core's single output interrupt + * @{ + */ +#define PDM_INTERRUPT_MASK__MASK_INTRPT6__SHIFT 6 +#define PDM_INTERRUPT_MASK__MASK_INTRPT6__WIDTH 1 +#define PDM_INTERRUPT_MASK__MASK_INTRPT6__MASK 0x00000040U +#define PDM_INTERRUPT_MASK__MASK_INTRPT6__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define PDM_INTERRUPT_MASK__MASK_INTRPT6__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT6__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PDM_INTERRUPT_MASK__MASK_INTRPT6__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PDM_INTERRUPT_MASK__MASK_INTRPT6__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PDM_INTERRUPT_MASK__MASK_INTRPT6__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field mask_intrpt7 */ +/** + * @defgroup at_apb_pdm_regs_core_mask_intrpt7_field mask_intrpt7_field + * @brief macros for field mask_intrpt7 + * @details allow intrpt7 to propogate to core's single output interrupt + * @{ + */ +#define PDM_INTERRUPT_MASK__MASK_INTRPT7__SHIFT 7 +#define PDM_INTERRUPT_MASK__MASK_INTRPT7__WIDTH 1 +#define PDM_INTERRUPT_MASK__MASK_INTRPT7__MASK 0x00000080U +#define PDM_INTERRUPT_MASK__MASK_INTRPT7__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define PDM_INTERRUPT_MASK__MASK_INTRPT7__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT7__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define PDM_INTERRUPT_MASK__MASK_INTRPT7__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define PDM_INTERRUPT_MASK__MASK_INTRPT7__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define PDM_INTERRUPT_MASK__MASK_INTRPT7__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field mask_intrpt8 */ +/** + * @defgroup at_apb_pdm_regs_core_mask_intrpt8_field mask_intrpt8_field + * @brief macros for field mask_intrpt8 + * @details allow intrpt8 to propogate to core's single output interrupt + * @{ + */ +#define PDM_INTERRUPT_MASK__MASK_INTRPT8__SHIFT 8 +#define PDM_INTERRUPT_MASK__MASK_INTRPT8__WIDTH 1 +#define PDM_INTERRUPT_MASK__MASK_INTRPT8__MASK 0x00000100U +#define PDM_INTERRUPT_MASK__MASK_INTRPT8__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define PDM_INTERRUPT_MASK__MASK_INTRPT8__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT8__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define PDM_INTERRUPT_MASK__MASK_INTRPT8__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PDM_INTERRUPT_MASK__MASK_INTRPT8__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PDM_INTERRUPT_MASK__MASK_INTRPT8__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field mask_intrpt9 */ +/** + * @defgroup at_apb_pdm_regs_core_mask_intrpt9_field mask_intrpt9_field + * @brief macros for field mask_intrpt9 + * @details allow intrpt9 to propogate to core's single output interrupt + * @{ + */ +#define PDM_INTERRUPT_MASK__MASK_INTRPT9__SHIFT 9 +#define PDM_INTERRUPT_MASK__MASK_INTRPT9__WIDTH 1 +#define PDM_INTERRUPT_MASK__MASK_INTRPT9__MASK 0x00000200U +#define PDM_INTERRUPT_MASK__MASK_INTRPT9__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PDM_INTERRUPT_MASK__MASK_INTRPT9__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define PDM_INTERRUPT_MASK__MASK_INTRPT9__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define PDM_INTERRUPT_MASK__MASK_INTRPT9__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PDM_INTERRUPT_MASK__MASK_INTRPT9__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PDM_INTERRUPT_MASK__MASK_INTRPT9__RESET_VALUE 0x00000001U +/** @} */ +#define PDM_INTERRUPT_MASK__TYPE uint32_t +#define PDM_INTERRUPT_MASK__READ 0x000003ffU +#define PDM_INTERRUPT_MASK__WRITE 0x000003ffU +#define PDM_INTERRUPT_MASK__PRESERVED 0x00000000U +#define PDM_INTERRUPT_MASK__RESET_VALUE 0x000003ffU + +#endif /* __PDM_INTERRUPT_MASK_MACRO__ */ + +/** @} end of interrupt_mask */ + +/* macros for BlueprintGlobalNameSpace::PDM_interrupt_clear */ +/** + * @defgroup at_apb_pdm_regs_core_interrupt_clear interrupt_clear + * @brief Contains register fields associated with interrupt_clear. definitions. + * @{ + */ +#ifndef __PDM_INTERRUPT_CLEAR_MACRO__ +#define __PDM_INTERRUPT_CLEAR_MACRO__ + +/* macros for field clear_intrpt0 */ +/** + * @defgroup at_apb_pdm_regs_core_clear_intrpt0_field clear_intrpt0_field + * @brief macros for field clear_intrpt0 + * @details clear interrupt 0; not self reseting + * @{ + */ +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT0__SHIFT 0 +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT0__WIDTH 1 +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT0__MASK 0x00000001U +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT0__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_intrpt1 */ +/** + * @defgroup at_apb_pdm_regs_core_clear_intrpt1_field clear_intrpt1_field + * @brief macros for field clear_intrpt1 + * @details clear interrupt 1; not self reseting + * @{ + */ +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT1__SHIFT 1 +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT1__WIDTH 1 +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT1__MASK 0x00000002U +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT1__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_intrpt2 */ +/** + * @defgroup at_apb_pdm_regs_core_clear_intrpt2_field clear_intrpt2_field + * @brief macros for field clear_intrpt2 + * @details clear interrupt 2; not self reseting + * @{ + */ +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT2__SHIFT 2 +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT2__WIDTH 1 +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT2__MASK 0x00000004U +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT2__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_intrpt3 */ +/** + * @defgroup at_apb_pdm_regs_core_clear_intrpt3_field clear_intrpt3_field + * @brief macros for field clear_intrpt3 + * @details clear interrupt 3; not self reseting + * @{ + */ +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT3__SHIFT 3 +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT3__WIDTH 1 +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT3__MASK 0x00000008U +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT3__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT3__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT3__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_intrpt4 */ +/** + * @defgroup at_apb_pdm_regs_core_clear_intrpt4_field clear_intrpt4_field + * @brief macros for field clear_intrpt4 + * @details clear interrupt 4; not self reseting + * @{ + */ +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT4__SHIFT 4 +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT4__WIDTH 1 +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT4__MASK 0x00000010U +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT4__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT4__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT4__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT4__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT4__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT4__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_intrpt5 */ +/** + * @defgroup at_apb_pdm_regs_core_clear_intrpt5_field clear_intrpt5_field + * @brief macros for field clear_intrpt5 + * @details clear interrupt 5; not self reseting + * @{ + */ +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT5__SHIFT 5 +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT5__WIDTH 1 +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT5__MASK 0x00000020U +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT5__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT5__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT5__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT5__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT5__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_intrpt6 */ +/** + * @defgroup at_apb_pdm_regs_core_clear_intrpt6_field clear_intrpt6_field + * @brief macros for field clear_intrpt6 + * @details clear interrupt 6; not self reseting + * @{ + */ +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT6__SHIFT 6 +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT6__WIDTH 1 +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT6__MASK 0x00000040U +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT6__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT6__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT6__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT6__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT6__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT6__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_intrpt7 */ +/** + * @defgroup at_apb_pdm_regs_core_clear_intrpt7_field clear_intrpt7_field + * @brief macros for field clear_intrpt7 + * @details clear interrupt 7; not self reseting + * @{ + */ +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT7__SHIFT 7 +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT7__WIDTH 1 +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT7__MASK 0x00000080U +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT7__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT7__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT7__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT7__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT7__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT7__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_intrpt8 */ +/** + * @defgroup at_apb_pdm_regs_core_clear_intrpt8_field clear_intrpt8_field + * @brief macros for field clear_intrpt8 + * @details clear interrupt 8; not self reseting + * @{ + */ +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT8__SHIFT 8 +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT8__WIDTH 1 +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT8__MASK 0x00000100U +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT8__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT8__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT8__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT8__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT8__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT8__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_intrpt9 */ +/** + * @defgroup at_apb_pdm_regs_core_clear_intrpt9_field clear_intrpt9_field + * @brief macros for field clear_intrpt9 + * @details clear interrupt 9; not self reseting + * @{ + */ +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT9__SHIFT 9 +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT9__WIDTH 1 +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT9__MASK 0x00000200U +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT9__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT9__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT9__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT9__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT9__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PDM_INTERRUPT_CLEAR__CLEAR_INTRPT9__RESET_VALUE 0x00000000U +/** @} */ +#define PDM_INTERRUPT_CLEAR__TYPE uint32_t +#define PDM_INTERRUPT_CLEAR__READ 0x000003ffU +#define PDM_INTERRUPT_CLEAR__WRITE 0x000003ffU +#define PDM_INTERRUPT_CLEAR__PRESERVED 0x00000000U +#define PDM_INTERRUPT_CLEAR__RESET_VALUE 0x00000000U + +#endif /* __PDM_INTERRUPT_CLEAR_MACRO__ */ + +/** @} end of interrupt_clear */ + +/* macros for BlueprintGlobalNameSpace::PDM_buffer_access_mode */ +/** + * @defgroup at_apb_pdm_regs_core_buffer_access_mode buffer_access_mode + * @brief Contains register fields associated with buffer_access_mode. definitions. + * @{ + */ +#ifndef __PDM_BUFFER_ACCESS_MODE_MACRO__ +#define __PDM_BUFFER_ACCESS_MODE_MACRO__ + +/* macros for field dma_mode */ +/** + * @defgroup at_apb_pdm_regs_core_dma_mode_field dma_mode_field + * @brief macros for field dma_mode + * @details 1= pingpong buffer has fifo-like interface. read address is auto-incremented from base address of buffer A by an internal counter, counting from 0 to 63 and wraps around. buffer full interrupt is cleared by HW at the end of the last read of the buffer. The auto-increment counter is cleared when fifo_mode is 0. + * @{ + */ +#define PDM_BUFFER_ACCESS_MODE__DMA_MODE__SHIFT 0 +#define PDM_BUFFER_ACCESS_MODE__DMA_MODE__WIDTH 1 +#define PDM_BUFFER_ACCESS_MODE__DMA_MODE__MASK 0x00000001U +#define PDM_BUFFER_ACCESS_MODE__DMA_MODE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PDM_BUFFER_ACCESS_MODE__DMA_MODE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PDM_BUFFER_ACCESS_MODE__DMA_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PDM_BUFFER_ACCESS_MODE__DMA_MODE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PDM_BUFFER_ACCESS_MODE__DMA_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PDM_BUFFER_ACCESS_MODE__DMA_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PDM_BUFFER_ACCESS_MODE__DMA_MODE__RESET_VALUE 0x00000000U +/** @} */ +#define PDM_BUFFER_ACCESS_MODE__TYPE uint32_t +#define PDM_BUFFER_ACCESS_MODE__READ 0x00000001U +#define PDM_BUFFER_ACCESS_MODE__WRITE 0x00000001U +#define PDM_BUFFER_ACCESS_MODE__PRESERVED 0x00000000U +#define PDM_BUFFER_ACCESS_MODE__RESET_VALUE 0x00000000U + +#endif /* __PDM_BUFFER_ACCESS_MODE_MACRO__ */ + +/** @} end of buffer_access_mode */ + +/* macros for BlueprintGlobalNameSpace::PDM_auto_counter */ +/** + * @defgroup at_apb_pdm_regs_core_auto_counter auto_counter + * @brief Contains register fields associated with auto_counter. definitions. + * @{ + */ +#ifndef __PDM_AUTO_COUNTER_MACRO__ +#define __PDM_AUTO_COUNTER_MACRO__ + +/* macros for field count */ +/** + * @defgroup at_apb_pdm_regs_core_count_field count_field + * @brief macros for field count + * @details current value of the auto increment counter. + * @{ + */ +#define PDM_AUTO_COUNTER__COUNT__SHIFT 0 +#define PDM_AUTO_COUNTER__COUNT__WIDTH 6 +#define PDM_AUTO_COUNTER__COUNT__MASK 0x0000003fU +#define PDM_AUTO_COUNTER__COUNT__READ(src) ((uint32_t)(src) & 0x0000003fU) +#define PDM_AUTO_COUNTER__COUNT__RESET_VALUE 0x00000000U +/** @} */ +#define PDM_AUTO_COUNTER__TYPE uint32_t +#define PDM_AUTO_COUNTER__READ 0x0000003fU +#define PDM_AUTO_COUNTER__PRESERVED 0x00000000U +#define PDM_AUTO_COUNTER__RESET_VALUE 0x00000000U + +#endif /* __PDM_AUTO_COUNTER_MACRO__ */ + +/** @} end of auto_counter */ + +/* macros for BlueprintGlobalNameSpace::PDM_buffer_depth */ +/** + * @defgroup at_apb_pdm_regs_core_buffer_depth buffer_depth + * @brief Contains register fields associated with buffer_depth. definitions. + * @{ + */ +#ifndef __PDM_BUFFER_DEPTH_MACRO__ +#define __PDM_BUFFER_DEPTH_MACRO__ + +/* macros for field depth */ +/** + * @defgroup at_apb_pdm_regs_core_depth_field depth_field + * @brief macros for field depth + * @details one buffer depth + * @{ + */ +#define PDM_BUFFER_DEPTH__DEPTH__SHIFT 0 +#define PDM_BUFFER_DEPTH__DEPTH__WIDTH 5 +#define PDM_BUFFER_DEPTH__DEPTH__MASK 0x0000001fU +#define PDM_BUFFER_DEPTH__DEPTH__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define PDM_BUFFER_DEPTH__DEPTH__RESET_VALUE 0x00000010U +/** @} */ +#define PDM_BUFFER_DEPTH__TYPE uint32_t +#define PDM_BUFFER_DEPTH__READ 0x0000001fU +#define PDM_BUFFER_DEPTH__PRESERVED 0x00000000U +#define PDM_BUFFER_DEPTH__RESET_VALUE 0x00000010U + +#endif /* __PDM_BUFFER_DEPTH_MACRO__ */ + +/** @} end of buffer_depth */ + +/* macros for BlueprintGlobalNameSpace::PDM_core_id */ +/** + * @defgroup at_apb_pdm_regs_core_core_id core_id + * @brief Contains register fields associated with core_id. definitions. + * @{ + */ +#ifndef __PDM_CORE_ID_MACRO__ +#define __PDM_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_pdm_regs_core_id_field id_field + * @brief macros for field id + * @details 'PDM ' in ASCII + * @{ + */ +#define PDM_CORE_ID__ID__SHIFT 0 +#define PDM_CORE_ID__ID__WIDTH 32 +#define PDM_CORE_ID__ID__MASK 0xffffffffU +#define PDM_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PDM_CORE_ID__ID__RESET_VALUE 0x50444d20U +/** @} */ +#define PDM_CORE_ID__TYPE uint32_t +#define PDM_CORE_ID__READ 0xffffffffU +#define PDM_CORE_ID__PRESERVED 0x00000000U +#define PDM_CORE_ID__RESET_VALUE 0x50444d20U + +#endif /* __PDM_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/* macros for BlueprintGlobalNameSpace::PDM_rev_hash */ +/** + * @defgroup at_apb_pdm_regs_core_rev_hash rev_hash + * @brief Contains register fields associated with rev_hash. definitions. + * @{ + */ +#ifndef __PDM_REV_HASH_MACRO__ +#define __PDM_REV_HASH_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_pdm_regs_core_id_field id_field + * @brief macros for field id + * @details crc32 of this document; don't change value to anything other than 32'h00000000; scripts will fill it out in the verilog + * @{ + */ +#define PDM_REV_HASH__ID__SHIFT 0 +#define PDM_REV_HASH__ID__WIDTH 32 +#define PDM_REV_HASH__ID__MASK 0xffffffffU +#define PDM_REV_HASH__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PDM_REV_HASH__ID__RESET_VALUE 0x00000000U +/** @} */ +#define PDM_REV_HASH__TYPE uint32_t +#define PDM_REV_HASH__READ 0xffffffffU +#define PDM_REV_HASH__PRESERVED 0x00000000U +#define PDM_REV_HASH__RESET_VALUE 0x00000000U + +#endif /* __PDM_REV_HASH_MACRO__ */ + +/** @} end of rev_hash */ + +/* macros for BlueprintGlobalNameSpace::PDM_rev_key */ +/** + * @defgroup at_apb_pdm_regs_core_rev_key rev_key + * @brief Contains register fields associated with rev_key. definitions. + * @{ + */ +#ifndef __PDM_REV_KEY_MACRO__ +#define __PDM_REV_KEY_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_pdm_regs_core_id_field id_field + * @brief macros for field id + * @details REV in ASCII + * @{ + */ +#define PDM_REV_KEY__ID__SHIFT 0 +#define PDM_REV_KEY__ID__WIDTH 32 +#define PDM_REV_KEY__ID__MASK 0xffffffffU +#define PDM_REV_KEY__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PDM_REV_KEY__ID__RESET_VALUE 0x52455620U +/** @} */ +#define PDM_REV_KEY__TYPE uint32_t +#define PDM_REV_KEY__READ 0xffffffffU +#define PDM_REV_KEY__PRESERVED 0x00000000U +#define PDM_REV_KEY__RESET_VALUE 0x52455620U + +#endif /* __PDM_REV_KEY_MACRO__ */ + +/** @} end of rev_key */ + +/** @} end of AT_APB_PDM_REGS_CORE */ +#endif /* __REG_AT_APB_PDM_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_apb_pseq_regs_core_macro.h b/ATM33xx-5/include/reg/at_apb_pseq_regs_core_macro.h new file mode 100644 index 0000000..f1bfc71 --- /dev/null +++ b/ATM33xx-5/include/reg/at_apb_pseq_regs_core_macro.h @@ -0,0 +1,14423 @@ +/* */ +/* File: at_apb_pseq_paris_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_apb_pseq_paris_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_APB_PSEQ_PARIS_REGS_CORE_H__ +#define __REG_AT_APB_PSEQ_PARIS_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_APB_PSEQ_PARIS_REGS_CORE at_apb_pseq_paris_regs_core + * @ingroup AT_REG + * @brief at_apb_pseq_paris_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_ctrl0 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_ctrl0 ctrl0 + * @brief signals to prepare for and to request low power state definitions. + * @{ + */ +#ifndef __PSEQ_CTRL0_MACRO__ +#define __PSEQ_CTRL0_MACRO__ + +/* macros for field manage_xtal */ +/** + * @defgroup at_apb_pseq_paris_regs_core_manage_xtal_field manage_xtal_field + * @brief macros for field manage_xtal + * @details If set, permits SOC to power down clk_mpc crystal circuit during low power mode. + * @{ + */ +#define PSEQ_CTRL0__MANAGE_XTAL__SHIFT 0 +#define PSEQ_CTRL0__MANAGE_XTAL__WIDTH 1 +#define PSEQ_CTRL0__MANAGE_XTAL__MASK 0x00000001U +#define PSEQ_CTRL0__MANAGE_XTAL__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PSEQ_CTRL0__MANAGE_XTAL__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PSEQ_CTRL0__MANAGE_XTAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_CTRL0__MANAGE_XTAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_CTRL0__MANAGE_XTAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_CTRL0__MANAGE_XTAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_CTRL0__MANAGE_XTAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field req_ble_only_lp_state */ +/** + * @defgroup at_apb_pseq_paris_regs_core_req_ble_only_lp_state_field req_ble_only_lp_state_field + * @brief macros for field req_ble_only_lp_state + * @details If set, requests SOC to go to BLE Only low power state. + * @{ + */ +#define PSEQ_CTRL0__REQ_BLE_ONLY_LP_STATE__SHIFT 1 +#define PSEQ_CTRL0__REQ_BLE_ONLY_LP_STATE__WIDTH 1 +#define PSEQ_CTRL0__REQ_BLE_ONLY_LP_STATE__MASK 0x00000002U +#define PSEQ_CTRL0__REQ_BLE_ONLY_LP_STATE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_CTRL0__REQ_BLE_ONLY_LP_STATE__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PSEQ_CTRL0__REQ_BLE_ONLY_LP_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PSEQ_CTRL0__REQ_BLE_ONLY_LP_STATE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PSEQ_CTRL0__REQ_BLE_ONLY_LP_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_CTRL0__REQ_BLE_ONLY_LP_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_CTRL0__REQ_BLE_ONLY_LP_STATE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field req_retain_all_state */ +/** + * @defgroup at_apb_pseq_paris_regs_core_req_retain_all_state_field req_retain_all_state_field + * @brief macros for field req_retain_all_state + * @details If set, requests SOC to go to Retain All low power state. + * @{ + */ +#define PSEQ_CTRL0__REQ_RETAIN_ALL_STATE__SHIFT 2 +#define PSEQ_CTRL0__REQ_RETAIN_ALL_STATE__WIDTH 1 +#define PSEQ_CTRL0__REQ_RETAIN_ALL_STATE__MASK 0x00000004U +#define PSEQ_CTRL0__REQ_RETAIN_ALL_STATE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PSEQ_CTRL0__REQ_RETAIN_ALL_STATE__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PSEQ_CTRL0__REQ_RETAIN_ALL_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PSEQ_CTRL0__REQ_RETAIN_ALL_STATE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PSEQ_CTRL0__REQ_RETAIN_ALL_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PSEQ_CTRL0__REQ_RETAIN_ALL_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PSEQ_CTRL0__REQ_RETAIN_ALL_STATE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field req_hibernate_state */ +/** + * @defgroup at_apb_pseq_paris_regs_core_req_hibernate_state_field req_hibernate_state_field + * @brief macros for field req_hibernate_state + * @details If set, requests SOC to go to Hibernate low power state. + * @{ + */ +#define PSEQ_CTRL0__REQ_HIBERNATE_STATE__SHIFT 3 +#define PSEQ_CTRL0__REQ_HIBERNATE_STATE__WIDTH 1 +#define PSEQ_CTRL0__REQ_HIBERNATE_STATE__MASK 0x00000008U +#define PSEQ_CTRL0__REQ_HIBERNATE_STATE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PSEQ_CTRL0__REQ_HIBERNATE_STATE__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PSEQ_CTRL0__REQ_HIBERNATE_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PSEQ_CTRL0__REQ_HIBERNATE_STATE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PSEQ_CTRL0__REQ_HIBERNATE_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PSEQ_CTRL0__REQ_HIBERNATE_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PSEQ_CTRL0__REQ_HIBERNATE_STATE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enable_debug_bus */ +/** + * @defgroup at_apb_pseq_paris_regs_core_enable_debug_bus_field enable_debug_bus_field + * @brief macros for field enable_debug_bus + * @details If set, pseq debug bus will be enabled (e.g. allowed to start toggling at pinmux input). + * @{ + */ +#define PSEQ_CTRL0__ENABLE_DEBUG_BUS__SHIFT 4 +#define PSEQ_CTRL0__ENABLE_DEBUG_BUS__WIDTH 1 +#define PSEQ_CTRL0__ENABLE_DEBUG_BUS__MASK 0x00000010U +#define PSEQ_CTRL0__ENABLE_DEBUG_BUS__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PSEQ_CTRL0__ENABLE_DEBUG_BUS__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PSEQ_CTRL0__ENABLE_DEBUG_BUS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PSEQ_CTRL0__ENABLE_DEBUG_BUS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PSEQ_CTRL0__ENABLE_DEBUG_BUS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PSEQ_CTRL0__ENABLE_DEBUG_BUS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PSEQ_CTRL0__ENABLE_DEBUG_BUS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field req_ble_to_boot */ +/** + * @defgroup at_apb_pseq_paris_regs_core_req_ble_to_boot_field req_ble_to_boot_field + * @brief macros for field req_ble_to_boot + * @details If set, requests that ble powers up. + * @{ + */ +#define PSEQ_CTRL0__REQ_BLE_TO_BOOT__SHIFT 5 +#define PSEQ_CTRL0__REQ_BLE_TO_BOOT__WIDTH 1 +#define PSEQ_CTRL0__REQ_BLE_TO_BOOT__MASK 0x00000020U +#define PSEQ_CTRL0__REQ_BLE_TO_BOOT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PSEQ_CTRL0__REQ_BLE_TO_BOOT__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define PSEQ_CTRL0__REQ_BLE_TO_BOOT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define PSEQ_CTRL0__REQ_BLE_TO_BOOT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define PSEQ_CTRL0__REQ_BLE_TO_BOOT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PSEQ_CTRL0__REQ_BLE_TO_BOOT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PSEQ_CTRL0__REQ_BLE_TO_BOOT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pwm_latch_open */ +/** + * @defgroup at_apb_pseq_paris_regs_core_pwm_latch_open_field pwm_latch_open_field + * @brief macros for field pwm_latch_open + * @details If set, opens all latches on pwm output prior to entering low power to hold pwm. + * @{ + */ +#define PSEQ_CTRL0__PWM_LATCH_OPEN__SHIFT 6 +#define PSEQ_CTRL0__PWM_LATCH_OPEN__WIDTH 1 +#define PSEQ_CTRL0__PWM_LATCH_OPEN__MASK 0x00000040U +#define PSEQ_CTRL0__PWM_LATCH_OPEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define PSEQ_CTRL0__PWM_LATCH_OPEN__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define PSEQ_CTRL0__PWM_LATCH_OPEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PSEQ_CTRL0__PWM_LATCH_OPEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PSEQ_CTRL0__PWM_LATCH_OPEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PSEQ_CTRL0__PWM_LATCH_OPEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PSEQ_CTRL0__PWM_LATCH_OPEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field xtal_waits_for_retv */ +/** + * @defgroup at_apb_pseq_paris_regs_core_xtal_waits_for_retv_field xtal_waits_for_retv_field + * @brief macros for field xtal_waits_for_retv + * @details If set, xtal will not be enabled until the retention voltage has been boosted back up to nominal value. + * @{ + */ +#define PSEQ_CTRL0__XTAL_WAITS_FOR_RETV__SHIFT 16 +#define PSEQ_CTRL0__XTAL_WAITS_FOR_RETV__WIDTH 1 +#define PSEQ_CTRL0__XTAL_WAITS_FOR_RETV__MASK 0x00010000U +#define PSEQ_CTRL0__XTAL_WAITS_FOR_RETV__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define PSEQ_CTRL0__XTAL_WAITS_FOR_RETV__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define PSEQ_CTRL0__XTAL_WAITS_FOR_RETV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define PSEQ_CTRL0__XTAL_WAITS_FOR_RETV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define PSEQ_CTRL0__XTAL_WAITS_FOR_RETV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PSEQ_CTRL0__XTAL_WAITS_FOR_RETV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PSEQ_CTRL0__XTAL_WAITS_FOR_RETV__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ble_boosts_retv */ +/** + * @defgroup at_apb_pseq_paris_regs_core_ble_boosts_retv_field ble_boosts_retv_field + * @brief macros for field ble_boosts_retv + * @details If set, any time ble requests the clk_mpc oscillator, the retention voltage is boosted back up to nominal value. + * @{ + */ +#define PSEQ_CTRL0__BLE_BOOSTS_RETV__SHIFT 17 +#define PSEQ_CTRL0__BLE_BOOSTS_RETV__WIDTH 1 +#define PSEQ_CTRL0__BLE_BOOSTS_RETV__MASK 0x00020000U +#define PSEQ_CTRL0__BLE_BOOSTS_RETV__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define PSEQ_CTRL0__BLE_BOOSTS_RETV__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define PSEQ_CTRL0__BLE_BOOSTS_RETV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define PSEQ_CTRL0__BLE_BOOSTS_RETV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define PSEQ_CTRL0__BLE_BOOSTS_RETV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define PSEQ_CTRL0__BLE_BOOSTS_RETV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define PSEQ_CTRL0__BLE_BOOSTS_RETV__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field block_dbg_wake */ +/** + * @defgroup at_apb_pseq_paris_regs_core_block_dbg_wake_field block_dbg_wake_field + * @brief macros for field block_dbg_wake + * @details If set, debugger cannot wake chip from low power state. + * @{ + */ +#define PSEQ_CTRL0__BLOCK_DBG_WAKE__SHIFT 18 +#define PSEQ_CTRL0__BLOCK_DBG_WAKE__WIDTH 1 +#define PSEQ_CTRL0__BLOCK_DBG_WAKE__MASK 0x00040000U +#define PSEQ_CTRL0__BLOCK_DBG_WAKE__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define PSEQ_CTRL0__BLOCK_DBG_WAKE__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define PSEQ_CTRL0__BLOCK_DBG_WAKE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define PSEQ_CTRL0__BLOCK_DBG_WAKE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define PSEQ_CTRL0__BLOCK_DBG_WAKE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define PSEQ_CTRL0__BLOCK_DBG_WAKE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define PSEQ_CTRL0__BLOCK_DBG_WAKE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wurx_det0_sel */ +/** + * @defgroup at_apb_pseq_paris_regs_core_wurx_det0_sel_field wurx_det0_sel_field + * @brief macros for field wurx_det0_sel + * @details Is wurx0 detect level or edge? 0=level 1=rising 2,3=falling + * @{ + */ +#define PSEQ_CTRL0__WURX_DET0_SEL__SHIFT 19 +#define PSEQ_CTRL0__WURX_DET0_SEL__WIDTH 2 +#define PSEQ_CTRL0__WURX_DET0_SEL__MASK 0x00180000U +#define PSEQ_CTRL0__WURX_DET0_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define PSEQ_CTRL0__WURX_DET0_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define PSEQ_CTRL0__WURX_DET0_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define PSEQ_CTRL0__WURX_DET0_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define PSEQ_CTRL0__WURX_DET0_SEL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field wurx_det1_sel */ +/** + * @defgroup at_apb_pseq_paris_regs_core_wurx_det1_sel_field wurx_det1_sel_field + * @brief macros for field wurx_det1_sel + * @details Is wurx1 detect level or edge? 0=level 1=rising 2,3=falling + * @{ + */ +#define PSEQ_CTRL0__WURX_DET1_SEL__SHIFT 21 +#define PSEQ_CTRL0__WURX_DET1_SEL__WIDTH 2 +#define PSEQ_CTRL0__WURX_DET1_SEL__MASK 0x00600000U +#define PSEQ_CTRL0__WURX_DET1_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define PSEQ_CTRL0__WURX_DET1_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define PSEQ_CTRL0__WURX_DET1_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define PSEQ_CTRL0__WURX_DET1_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define PSEQ_CTRL0__WURX_DET1_SEL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field radio_en_i_src */ +/** + * @defgroup at_apb_pseq_paris_regs_core_radio_en_i_src_field radio_en_i_src_field + * @brief macros for field radio_en_i_src + * @details Source of radio enable request signal. 0=direct/rw_cm_timing_gen_lp 1=indirect/rif + * @{ + */ +#define PSEQ_CTRL0__RADIO_EN_I_SRC__SHIFT 23 +#define PSEQ_CTRL0__RADIO_EN_I_SRC__WIDTH 1 +#define PSEQ_CTRL0__RADIO_EN_I_SRC__MASK 0x00800000U +#define PSEQ_CTRL0__RADIO_EN_I_SRC__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PSEQ_CTRL0__RADIO_EN_I_SRC__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define PSEQ_CTRL0__RADIO_EN_I_SRC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define PSEQ_CTRL0__RADIO_EN_I_SRC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define PSEQ_CTRL0__RADIO_EN_I_SRC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PSEQ_CTRL0__RADIO_EN_I_SRC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PSEQ_CTRL0__RADIO_EN_I_SRC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pinsel_latch_open */ +/** + * @defgroup at_apb_pseq_paris_regs_core_pinsel_latch_open_field pinsel_latch_open_field + * @brief macros for field pinsel_latch_open + * @details If set, opens all latches all pin select signals. + * @{ + */ +#define PSEQ_CTRL0__PINSEL_LATCH_OPEN__SHIFT 24 +#define PSEQ_CTRL0__PINSEL_LATCH_OPEN__WIDTH 1 +#define PSEQ_CTRL0__PINSEL_LATCH_OPEN__MASK 0x01000000U +#define PSEQ_CTRL0__PINSEL_LATCH_OPEN__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define PSEQ_CTRL0__PINSEL_LATCH_OPEN__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define PSEQ_CTRL0__PINSEL_LATCH_OPEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define PSEQ_CTRL0__PINSEL_LATCH_OPEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define PSEQ_CTRL0__PINSEL_LATCH_OPEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define PSEQ_CTRL0__PINSEL_LATCH_OPEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define PSEQ_CTRL0__PINSEL_LATCH_OPEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ksm_latch_open */ +/** + * @defgroup at_apb_pseq_paris_regs_core_ksm_latch_open_field ksm_latch_open_field + * @brief macros for field ksm_latch_open + * @details If set, opens all latches on ksm control signals. + * @{ + */ +#define PSEQ_CTRL0__KSM_LATCH_OPEN__SHIFT 25 +#define PSEQ_CTRL0__KSM_LATCH_OPEN__WIDTH 1 +#define PSEQ_CTRL0__KSM_LATCH_OPEN__MASK 0x02000000U +#define PSEQ_CTRL0__KSM_LATCH_OPEN__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define PSEQ_CTRL0__KSM_LATCH_OPEN__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define PSEQ_CTRL0__KSM_LATCH_OPEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define PSEQ_CTRL0__KSM_LATCH_OPEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define PSEQ_CTRL0__KSM_LATCH_OPEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define PSEQ_CTRL0__KSM_LATCH_OPEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define PSEQ_CTRL0__KSM_LATCH_OPEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field gpio_latch_open */ +/** + * @defgroup at_apb_pseq_paris_regs_core_gpio_latch_open_field gpio_latch_open_field + * @brief macros for field gpio_latch_open + * @details If set, opens all latches on gpio control signals. + * @{ + */ +#define PSEQ_CTRL0__GPIO_LATCH_OPEN__SHIFT 26 +#define PSEQ_CTRL0__GPIO_LATCH_OPEN__WIDTH 1 +#define PSEQ_CTRL0__GPIO_LATCH_OPEN__MASK 0x04000000U +#define PSEQ_CTRL0__GPIO_LATCH_OPEN__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define PSEQ_CTRL0__GPIO_LATCH_OPEN__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define PSEQ_CTRL0__GPIO_LATCH_OPEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define PSEQ_CTRL0__GPIO_LATCH_OPEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define PSEQ_CTRL0__GPIO_LATCH_OPEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define PSEQ_CTRL0__GPIO_LATCH_OPEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define PSEQ_CTRL0__GPIO_LATCH_OPEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field req_soc_off */ +/** + * @defgroup at_apb_pseq_paris_regs_core_req_soc_off_field req_soc_off_field + * @brief macros for field req_soc_off + * @details If set, requests SOC to go SOC Off state. + * @{ + */ +#define PSEQ_CTRL0__REQ_SOC_OFF__SHIFT 27 +#define PSEQ_CTRL0__REQ_SOC_OFF__WIDTH 1 +#define PSEQ_CTRL0__REQ_SOC_OFF__MASK 0x08000000U +#define PSEQ_CTRL0__REQ_SOC_OFF__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define PSEQ_CTRL0__REQ_SOC_OFF__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define PSEQ_CTRL0__REQ_SOC_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define PSEQ_CTRL0__REQ_SOC_OFF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define PSEQ_CTRL0__REQ_SOC_OFF__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define PSEQ_CTRL0__REQ_SOC_OFF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define PSEQ_CTRL0__REQ_SOC_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pinpu_latch_open */ +/** + * @defgroup at_apb_pseq_paris_regs_core_pinpu_latch_open_field pinpu_latch_open_field + * @brief macros for field pinpu_latch_open + * @details If set, opens all latches on all pin pu signals. + * @{ + */ +#define PSEQ_CTRL0__PINPU_LATCH_OPEN__SHIFT 28 +#define PSEQ_CTRL0__PINPU_LATCH_OPEN__WIDTH 1 +#define PSEQ_CTRL0__PINPU_LATCH_OPEN__MASK 0x10000000U +#define PSEQ_CTRL0__PINPU_LATCH_OPEN__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define PSEQ_CTRL0__PINPU_LATCH_OPEN__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define PSEQ_CTRL0__PINPU_LATCH_OPEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define PSEQ_CTRL0__PINPU_LATCH_OPEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define PSEQ_CTRL0__PINPU_LATCH_OPEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define PSEQ_CTRL0__PINPU_LATCH_OPEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define PSEQ_CTRL0__PINPU_LATCH_OPEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field i2c_latch_open */ +/** + * @defgroup at_apb_pseq_paris_regs_core_i2c_latch_open_field i2c_latch_open_field + * @brief macros for field i2c_latch_open + * @details If set, opens all latches on i2c 0/1 sck/sda pu signals. + * @{ + */ +#define PSEQ_CTRL0__I2C_LATCH_OPEN__SHIFT 29 +#define PSEQ_CTRL0__I2C_LATCH_OPEN__WIDTH 1 +#define PSEQ_CTRL0__I2C_LATCH_OPEN__MASK 0x20000000U +#define PSEQ_CTRL0__I2C_LATCH_OPEN__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define PSEQ_CTRL0__I2C_LATCH_OPEN__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define PSEQ_CTRL0__I2C_LATCH_OPEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define PSEQ_CTRL0__I2C_LATCH_OPEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define PSEQ_CTRL0__I2C_LATCH_OPEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define PSEQ_CTRL0__I2C_LATCH_OPEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define PSEQ_CTRL0__I2C_LATCH_OPEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field spi_latch_open */ +/** + * @defgroup at_apb_pseq_paris_regs_core_spi_latch_open_field spi_latch_open_field + * @brief macros for field spi_latch_open + * @details If set, opens all latches on spi0 slave control signals. + * @{ + */ +#define PSEQ_CTRL0__SPI_LATCH_OPEN__SHIFT 30 +#define PSEQ_CTRL0__SPI_LATCH_OPEN__WIDTH 1 +#define PSEQ_CTRL0__SPI_LATCH_OPEN__MASK 0x40000000U +#define PSEQ_CTRL0__SPI_LATCH_OPEN__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define PSEQ_CTRL0__SPI_LATCH_OPEN__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define PSEQ_CTRL0__SPI_LATCH_OPEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define PSEQ_CTRL0__SPI_LATCH_OPEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define PSEQ_CTRL0__SPI_LATCH_OPEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define PSEQ_CTRL0__SPI_LATCH_OPEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define PSEQ_CTRL0__SPI_LATCH_OPEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field req_shub_adv */ +/** + * @defgroup at_apb_pseq_paris_regs_core_req_shub_adv_field req_shub_adv_field + * @brief macros for field req_shub_adv + * @details If set, requests SOC to go to do CPU-less adv. + * @{ + */ +#define PSEQ_CTRL0__REQ_SHUB_ADV__SHIFT 31 +#define PSEQ_CTRL0__REQ_SHUB_ADV__WIDTH 1 +#define PSEQ_CTRL0__REQ_SHUB_ADV__MASK 0x80000000U +#define PSEQ_CTRL0__REQ_SHUB_ADV__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define PSEQ_CTRL0__REQ_SHUB_ADV__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define PSEQ_CTRL0__REQ_SHUB_ADV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define PSEQ_CTRL0__REQ_SHUB_ADV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define PSEQ_CTRL0__REQ_SHUB_ADV__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PSEQ_CTRL0__REQ_SHUB_ADV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PSEQ_CTRL0__REQ_SHUB_ADV__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_CTRL0__TYPE uint32_t +#define PSEQ_CTRL0__READ 0xffff007fU +#define PSEQ_CTRL0__WRITE 0xffff007fU +#define PSEQ_CTRL0__PRESERVED 0x00000000U +#define PSEQ_CTRL0__RESET_VALUE 0x002a0000U + +#endif /* __PSEQ_CTRL0_MACRO__ */ + +/** @} end of ctrl0 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_ctrl1 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_ctrl1 ctrl1 + * @brief signals to prepare for and to request low power state definitions. + * @{ + */ +#ifndef __PSEQ_CTRL1_MACRO__ +#define __PSEQ_CTRL1_MACRO__ + +/* macros for field energy4CPU_sel */ +/** + * @defgroup at_apb_pseq_paris_regs_core_energy4CPU_sel_field energy4CPU_sel_field + * @brief macros for field energy4CPU_sel + * @details Is energy4CPU level or edge? 0=level 1=rising 2=falling 3=negate level + * @{ + */ +#define PSEQ_CTRL1__ENERGY4CPU_SEL__SHIFT 0 +#define PSEQ_CTRL1__ENERGY4CPU_SEL__WIDTH 2 +#define PSEQ_CTRL1__ENERGY4CPU_SEL__MASK 0x00000003U +#define PSEQ_CTRL1__ENERGY4CPU_SEL__READ(src) ((uint32_t)(src) & 0x00000003U) +#define PSEQ_CTRL1__ENERGY4CPU_SEL__WRITE(src) ((uint32_t)(src) & 0x00000003U) +#define PSEQ_CTRL1__ENERGY4CPU_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define PSEQ_CTRL1__ENERGY4CPU_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define PSEQ_CTRL1__ENERGY4CPU_SEL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field energy4TX_sel */ +/** + * @defgroup at_apb_pseq_paris_regs_core_energy4TX_sel_field energy4TX_sel_field + * @brief macros for field energy4TX_sel + * @details Is energy4TX level or edge? 0=level 1=rising 2=falling 3=negate level + * @{ + */ +#define PSEQ_CTRL1__ENERGY4TX_SEL__SHIFT 2 +#define PSEQ_CTRL1__ENERGY4TX_SEL__WIDTH 2 +#define PSEQ_CTRL1__ENERGY4TX_SEL__MASK 0x0000000cU +#define PSEQ_CTRL1__ENERGY4TX_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x0000000cU) >> 2) +#define PSEQ_CTRL1__ENERGY4TX_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000000cU) +#define PSEQ_CTRL1__ENERGY4TX_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((uint32_t)(src) <<\ + 2) & 0x0000000cU) +#define PSEQ_CTRL1__ENERGY4TX_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000000cU))) +#define PSEQ_CTRL1__ENERGY4TX_SEL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field endoflife_sel */ +/** + * @defgroup at_apb_pseq_paris_regs_core_endoflife_sel_field endoflife_sel_field + * @brief macros for field endoflife_sel + * @details Is endoflife level or edge? 0=level 1=rising 2=falling 3=negate level + * @{ + */ +#define PSEQ_CTRL1__ENDOFLIFE_SEL__SHIFT 4 +#define PSEQ_CTRL1__ENDOFLIFE_SEL__WIDTH 2 +#define PSEQ_CTRL1__ENDOFLIFE_SEL__MASK 0x00000030U +#define PSEQ_CTRL1__ENDOFLIFE_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000030U) >> 4) +#define PSEQ_CTRL1__ENDOFLIFE_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000030U) +#define PSEQ_CTRL1__ENDOFLIFE_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((uint32_t)(src) <<\ + 4) & 0x00000030U) +#define PSEQ_CTRL1__ENDOFLIFE_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000030U))) +#define PSEQ_CTRL1__ENDOFLIFE_SEL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field brownout_sel */ +/** + * @defgroup at_apb_pseq_paris_regs_core_brownout_sel_field brownout_sel_field + * @brief macros for field brownout_sel + * @details Is brownout level or edge? 0=level 1=rising 2=falling 3=negate level + * @{ + */ +#define PSEQ_CTRL1__BROWNOUT_SEL__SHIFT 6 +#define PSEQ_CTRL1__BROWNOUT_SEL__WIDTH 2 +#define PSEQ_CTRL1__BROWNOUT_SEL__MASK 0x000000c0U +#define PSEQ_CTRL1__BROWNOUT_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x000000c0U) >> 6) +#define PSEQ_CTRL1__BROWNOUT_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000000c0U) +#define PSEQ_CTRL1__BROWNOUT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((uint32_t)(src) <<\ + 6) & 0x000000c0U) +#define PSEQ_CTRL1__BROWNOUT_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000000c0U))) +#define PSEQ_CTRL1__BROWNOUT_SEL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field reset_wurx_spi_regs */ +/** + * @defgroup at_apb_pseq_paris_regs_core_reset_wurx_spi_regs_field reset_wurx_spi_regs_field + * @brief macros for field reset_wurx_spi_regs + * @{ + */ +#define PSEQ_CTRL1__RESET_WURX_SPI_REGS__SHIFT 8 +#define PSEQ_CTRL1__RESET_WURX_SPI_REGS__WIDTH 1 +#define PSEQ_CTRL1__RESET_WURX_SPI_REGS__MASK 0x00000100U +#define PSEQ_CTRL1__RESET_WURX_SPI_REGS__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define PSEQ_CTRL1__RESET_WURX_SPI_REGS__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define PSEQ_CTRL1__RESET_WURX_SPI_REGS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define PSEQ_CTRL1__RESET_WURX_SPI_REGS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define PSEQ_CTRL1__RESET_WURX_SPI_REGS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PSEQ_CTRL1__RESET_WURX_SPI_REGS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PSEQ_CTRL1__RESET_WURX_SPI_REGS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reset_radio_spi_regs */ +/** + * @defgroup at_apb_pseq_paris_regs_core_reset_radio_spi_regs_field reset_radio_spi_regs_field + * @brief macros for field reset_radio_spi_regs + * @{ + */ +#define PSEQ_CTRL1__RESET_RADIO_SPI_REGS__SHIFT 9 +#define PSEQ_CTRL1__RESET_RADIO_SPI_REGS__WIDTH 1 +#define PSEQ_CTRL1__RESET_RADIO_SPI_REGS__MASK 0x00000200U +#define PSEQ_CTRL1__RESET_RADIO_SPI_REGS__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PSEQ_CTRL1__RESET_RADIO_SPI_REGS__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define PSEQ_CTRL1__RESET_RADIO_SPI_REGS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define PSEQ_CTRL1__RESET_RADIO_SPI_REGS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define PSEQ_CTRL1__RESET_RADIO_SPI_REGS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PSEQ_CTRL1__RESET_RADIO_SPI_REGS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PSEQ_CTRL1__RESET_RADIO_SPI_REGS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reset_pmu_spi_regs */ +/** + * @defgroup at_apb_pseq_paris_regs_core_reset_pmu_spi_regs_field reset_pmu_spi_regs_field + * @brief macros for field reset_pmu_spi_regs + * @{ + */ +#define PSEQ_CTRL1__RESET_PMU_SPI_REGS__SHIFT 10 +#define PSEQ_CTRL1__RESET_PMU_SPI_REGS__WIDTH 1 +#define PSEQ_CTRL1__RESET_PMU_SPI_REGS__MASK 0x00000400U +#define PSEQ_CTRL1__RESET_PMU_SPI_REGS__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define PSEQ_CTRL1__RESET_PMU_SPI_REGS__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define PSEQ_CTRL1__RESET_PMU_SPI_REGS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define PSEQ_CTRL1__RESET_PMU_SPI_REGS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define PSEQ_CTRL1__RESET_PMU_SPI_REGS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define PSEQ_CTRL1__RESET_PMU_SPI_REGS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define PSEQ_CTRL1__RESET_PMU_SPI_REGS__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_CTRL1__TYPE uint32_t +#define PSEQ_CTRL1__READ 0x000007ffU +#define PSEQ_CTRL1__WRITE 0x000007ffU +#define PSEQ_CTRL1__PRESERVED 0x00000000U +#define PSEQ_CTRL1__RESET_VALUE 0x00000055U + +#endif /* __PSEQ_CTRL1_MACRO__ */ + +/** @} end of ctrl1 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_retain_all_wake_mask */ +/** + * @defgroup at_apb_pseq_paris_regs_core_retain_all_wake_mask retain_all_wake_mask + * @brief signals to select which events can generate a wake event while in Retain All definitions. + * @{ + */ +#ifndef __PSEQ_RETAIN_ALL_WAKE_MASK_MACRO__ +#define __PSEQ_RETAIN_ALL_WAKE_MASK_MACRO__ + +/* macros for field watch_gpio */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_gpio_field watch_gpio_field + * @brief macros for field watch_gpio + * @details valid to wake on gpio activity + * @{ + */ +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_GPIO__SHIFT 0 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_GPIO__WIDTH 1 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_GPIO__MASK 0x00000001U +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_GPIO__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_GPIO__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_GPIO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_GPIO__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_GPIO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_GPIO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_GPIO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_cntdown */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_cntdown_field watch_cntdown_field + * @brief macros for field watch_cntdown + * @details valid to wake on count down timer expiring + * @{ + */ +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_CNTDOWN__SHIFT 1 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_CNTDOWN__WIDTH 1 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_CNTDOWN__MASK 0x00000002U +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_CNTDOWN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_CNTDOWN__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_CNTDOWN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_CNTDOWN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_CNTDOWN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_CNTDOWN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_CNTDOWN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_wurx0 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_wurx0_field watch_wurx0_field + * @brief macros for field watch_wurx0 + * @details valid to wake on wurx0 detect + * @{ + */ +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX0__SHIFT 2 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX0__WIDTH 1 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX0__MASK 0x00000004U +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX0__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX0__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_wurx1 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_wurx1_field watch_wurx1_field + * @brief macros for field watch_wurx1 + * @details valid to wake on wurx1 detect + * @{ + */ +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX1__SHIFT 3 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX1__WIDTH 1 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX1__MASK 0x00000008U +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX1__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_qdec */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_qdec_field watch_qdec_field + * @brief macros for field watch_qdec + * @details valid to wake on qdec activity + * @{ + */ +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_QDEC__SHIFT 4 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_QDEC__WIDTH 1 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_QDEC__MASK 0x00000010U +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_QDEC__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_QDEC__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_QDEC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_QDEC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_QDEC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_QDEC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_QDEC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_ksm */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_ksm_field watch_ksm_field + * @brief macros for field watch_ksm + * @details valid to wake on keyboard activity + * @{ + */ +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_KSM__SHIFT 5 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_KSM__WIDTH 1 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_KSM__MASK 0x00000020U +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_KSM__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_KSM__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_KSM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_KSM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_KSM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_KSM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_KSM__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_shub */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_shub_field watch_shub_field + * @brief macros for field watch_shub + * @details valid to wake on sensor hub trigger + * @{ + */ +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_SHUB__SHIFT 6 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_SHUB__WIDTH 1 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_SHUB__MASK 0x00000040U +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_SHUB__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_SHUB__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_SHUB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_SHUB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_SHUB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_SHUB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_SHUB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_spi */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_spi_field watch_spi_field + * @brief macros for field watch_spi + * @details valid to wake on spi slave activity + * @{ + */ +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_SPI__SHIFT 7 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_SPI__WIDTH 1 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_SPI__MASK 0x00000080U +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_SPI__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_SPI__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_SPI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_SPI__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_SPI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_SPI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_SPI__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_i2c */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_i2c_field watch_i2c_field + * @brief macros for field watch_i2c + * @details valid to wake on i2c slave activity + * @{ + */ +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_I2C__SHIFT 8 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_I2C__WIDTH 1 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_I2C__MASK 0x00000100U +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_I2C__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_I2C__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_I2C__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_I2C__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_I2C__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_I2C__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_I2C__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_pmu_lpcomp */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_pmu_lpcomp_field watch_pmu_lpcomp_field + * @brief macros for field watch_pmu_lpcomp + * @details valid to wake on pmu lpcomp threshold crossing + * @{ + */ +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_PMU_LPCOMP__SHIFT 9 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_PMU_LPCOMP__WIDTH 1 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_PMU_LPCOMP__MASK 0x00000200U +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_PMU_LPCOMP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_PMU_LPCOMP__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_PMU_LPCOMP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_PMU_LPCOMP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_PMU_LPCOMP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_PMU_LPCOMP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_PMU_LPCOMP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_pmu_timer */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_pmu_timer_field watch_pmu_timer_field + * @brief macros for field watch_pmu_timer + * @details valid to wake on pmu timer expiring + * @{ + */ +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_PMU_TIMER__SHIFT 10 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_PMU_TIMER__WIDTH 1 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_PMU_TIMER__MASK 0x00000400U +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_PMU_TIMER__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_PMU_TIMER__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_PMU_TIMER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_PMU_TIMER__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_PMU_TIMER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_PMU_TIMER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_PMU_TIMER__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_energy4CPU */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_energy4CPU_field watch_energy4CPU_field + * @brief macros for field watch_energy4CPU + * @details valid to wake on pmu asserting energy4CPU + * @{ + */ +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENERGY4CPU__SHIFT 11 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENERGY4CPU__WIDTH 1 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENERGY4CPU__MASK 0x00000800U +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENERGY4CPU__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENERGY4CPU__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENERGY4CPU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENERGY4CPU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENERGY4CPU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENERGY4CPU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENERGY4CPU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_energy4TX */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_energy4TX_field watch_energy4TX_field + * @brief macros for field watch_energy4TX + * @details valid to wake on pmu asserting energy4TX + * @{ + */ +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENERGY4TX__SHIFT 12 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENERGY4TX__WIDTH 1 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENERGY4TX__MASK 0x00001000U +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENERGY4TX__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENERGY4TX__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENERGY4TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENERGY4TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENERGY4TX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENERGY4TX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENERGY4TX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_endoflife */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_endoflife_field watch_endoflife_field + * @brief macros for field watch_endoflife + * @details valid to wake on pmu asserting endoflife + * @{ + */ +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENDOFLIFE__SHIFT 13 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENDOFLIFE__WIDTH 1 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENDOFLIFE__MASK 0x00002000U +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENDOFLIFE__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENDOFLIFE__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENDOFLIFE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENDOFLIFE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENDOFLIFE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENDOFLIFE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_ENDOFLIFE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_brownout */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_brownout_field watch_brownout_field + * @brief macros for field watch_brownout + * @details valid to wake on pmu asserting brownout + * @{ + */ +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_BROWNOUT__SHIFT 14 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_BROWNOUT__WIDTH 1 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_BROWNOUT__MASK 0x00004000U +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_BROWNOUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_BROWNOUT__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_BROWNOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_BROWNOUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_BROWNOUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_BROWNOUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_BROWNOUT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_wurx */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_wurx_field watch_wurx_field + * @brief macros for field watch_wurx + * @details valid to wake on multiple wurx detects in certain amount of time + * @{ + */ +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX__SHIFT 15 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX__WIDTH 1 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX__MASK 0x00008000U +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_WURX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_ble_osc_on */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_ble_osc_on_field watch_ble_osc_on_field + * @brief macros for field watch_ble_osc_on + * @{ + */ +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_BLE_OSC_ON__SHIFT 16 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_BLE_OSC_ON__WIDTH 1 +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_BLE_OSC_ON__MASK 0x00010000U +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_BLE_OSC_ON__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_BLE_OSC_ON__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_BLE_OSC_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_BLE_OSC_ON__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_BLE_OSC_ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_BLE_OSC_ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PSEQ_RETAIN_ALL_WAKE_MASK__WATCH_BLE_OSC_ON__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field qualify_on_energy4TX */ +/** + * @defgroup at_apb_pseq_paris_regs_core_qualify_on_energy4TX_field qualify_on_energy4TX_field + * @brief macros for field qualify_on_energy4TX + * @{ + */ +#define PSEQ_RETAIN_ALL_WAKE_MASK__QUALIFY_ON_ENERGY4TX__SHIFT 30 +#define PSEQ_RETAIN_ALL_WAKE_MASK__QUALIFY_ON_ENERGY4TX__WIDTH 1 +#define PSEQ_RETAIN_ALL_WAKE_MASK__QUALIFY_ON_ENERGY4TX__MASK 0x40000000U +#define PSEQ_RETAIN_ALL_WAKE_MASK__QUALIFY_ON_ENERGY4TX__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define PSEQ_RETAIN_ALL_WAKE_MASK__QUALIFY_ON_ENERGY4TX__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__QUALIFY_ON_ENERGY4TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__QUALIFY_ON_ENERGY4TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define PSEQ_RETAIN_ALL_WAKE_MASK__QUALIFY_ON_ENERGY4TX__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define PSEQ_RETAIN_ALL_WAKE_MASK__QUALIFY_ON_ENERGY4TX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define PSEQ_RETAIN_ALL_WAKE_MASK__QUALIFY_ON_ENERGY4TX__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field qualify_on_energy4CPU */ +/** + * @defgroup at_apb_pseq_paris_regs_core_qualify_on_energy4CPU_field qualify_on_energy4CPU_field + * @brief macros for field qualify_on_energy4CPU + * @{ + */ +#define PSEQ_RETAIN_ALL_WAKE_MASK__QUALIFY_ON_ENERGY4CPU__SHIFT 31 +#define PSEQ_RETAIN_ALL_WAKE_MASK__QUALIFY_ON_ENERGY4CPU__WIDTH 1 +#define PSEQ_RETAIN_ALL_WAKE_MASK__QUALIFY_ON_ENERGY4CPU__MASK 0x80000000U +#define PSEQ_RETAIN_ALL_WAKE_MASK__QUALIFY_ON_ENERGY4CPU__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define PSEQ_RETAIN_ALL_WAKE_MASK__QUALIFY_ON_ENERGY4CPU__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__QUALIFY_ON_ENERGY4CPU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define PSEQ_RETAIN_ALL_WAKE_MASK__QUALIFY_ON_ENERGY4CPU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define PSEQ_RETAIN_ALL_WAKE_MASK__QUALIFY_ON_ENERGY4CPU__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PSEQ_RETAIN_ALL_WAKE_MASK__QUALIFY_ON_ENERGY4CPU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PSEQ_RETAIN_ALL_WAKE_MASK__QUALIFY_ON_ENERGY4CPU__RESET_VALUE \ + 0x00000000U +/** @} */ +#define PSEQ_RETAIN_ALL_WAKE_MASK__TYPE uint32_t +#define PSEQ_RETAIN_ALL_WAKE_MASK__READ 0xc001ffffU +#define PSEQ_RETAIN_ALL_WAKE_MASK__WRITE 0xc001ffffU +#define PSEQ_RETAIN_ALL_WAKE_MASK__PRESERVED 0x00000000U +#define PSEQ_RETAIN_ALL_WAKE_MASK__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_RETAIN_ALL_WAKE_MASK_MACRO__ */ + +/** @} end of retain_all_wake_mask */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_hib_wake_mask */ +/** + * @defgroup at_apb_pseq_paris_regs_core_hib_wake_mask hib_wake_mask + * @brief signals to select which events can generate a wake event while in Hiberbate definitions. + * @{ + */ +#ifndef __PSEQ_HIB_WAKE_MASK_MACRO__ +#define __PSEQ_HIB_WAKE_MASK_MACRO__ + +/* macros for field watch_gpio */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_gpio_field watch_gpio_field + * @brief macros for field watch_gpio + * @details valid to wake on gpio activity + * @{ + */ +#define PSEQ_HIB_WAKE_MASK__WATCH_GPIO__SHIFT 0 +#define PSEQ_HIB_WAKE_MASK__WATCH_GPIO__WIDTH 1 +#define PSEQ_HIB_WAKE_MASK__WATCH_GPIO__MASK 0x00000001U +#define PSEQ_HIB_WAKE_MASK__WATCH_GPIO__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_HIB_WAKE_MASK__WATCH_GPIO__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_HIB_WAKE_MASK__WATCH_GPIO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_HIB_WAKE_MASK__WATCH_GPIO__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_HIB_WAKE_MASK__WATCH_GPIO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_HIB_WAKE_MASK__WATCH_GPIO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_HIB_WAKE_MASK__WATCH_GPIO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_cntdown */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_cntdown_field watch_cntdown_field + * @brief macros for field watch_cntdown + * @details valid to wake on count down timer expiring + * @{ + */ +#define PSEQ_HIB_WAKE_MASK__WATCH_CNTDOWN__SHIFT 1 +#define PSEQ_HIB_WAKE_MASK__WATCH_CNTDOWN__WIDTH 1 +#define PSEQ_HIB_WAKE_MASK__WATCH_CNTDOWN__MASK 0x00000002U +#define PSEQ_HIB_WAKE_MASK__WATCH_CNTDOWN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_HIB_WAKE_MASK__WATCH_CNTDOWN__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PSEQ_HIB_WAKE_MASK__WATCH_CNTDOWN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PSEQ_HIB_WAKE_MASK__WATCH_CNTDOWN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PSEQ_HIB_WAKE_MASK__WATCH_CNTDOWN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_HIB_WAKE_MASK__WATCH_CNTDOWN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_HIB_WAKE_MASK__WATCH_CNTDOWN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_wurx0 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_wurx0_field watch_wurx0_field + * @brief macros for field watch_wurx0 + * @details valid to wake on wurx0 detect + * @{ + */ +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX0__SHIFT 2 +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX0__WIDTH 1 +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX0__MASK 0x00000004U +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX0__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX0__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_wurx1 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_wurx1_field watch_wurx1_field + * @brief macros for field watch_wurx1 + * @details valid to wake on wurx1 detect + * @{ + */ +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX1__SHIFT 3 +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX1__WIDTH 1 +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX1__MASK 0x00000008U +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX1__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_qdec */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_qdec_field watch_qdec_field + * @brief macros for field watch_qdec + * @details valid to wake on qdec activity + * @{ + */ +#define PSEQ_HIB_WAKE_MASK__WATCH_QDEC__SHIFT 4 +#define PSEQ_HIB_WAKE_MASK__WATCH_QDEC__WIDTH 1 +#define PSEQ_HIB_WAKE_MASK__WATCH_QDEC__MASK 0x00000010U +#define PSEQ_HIB_WAKE_MASK__WATCH_QDEC__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PSEQ_HIB_WAKE_MASK__WATCH_QDEC__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PSEQ_HIB_WAKE_MASK__WATCH_QDEC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PSEQ_HIB_WAKE_MASK__WATCH_QDEC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PSEQ_HIB_WAKE_MASK__WATCH_QDEC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PSEQ_HIB_WAKE_MASK__WATCH_QDEC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PSEQ_HIB_WAKE_MASK__WATCH_QDEC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_ksm */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_ksm_field watch_ksm_field + * @brief macros for field watch_ksm + * @details valid to wake on keyboard activity + * @{ + */ +#define PSEQ_HIB_WAKE_MASK__WATCH_KSM__SHIFT 5 +#define PSEQ_HIB_WAKE_MASK__WATCH_KSM__WIDTH 1 +#define PSEQ_HIB_WAKE_MASK__WATCH_KSM__MASK 0x00000020U +#define PSEQ_HIB_WAKE_MASK__WATCH_KSM__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PSEQ_HIB_WAKE_MASK__WATCH_KSM__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define PSEQ_HIB_WAKE_MASK__WATCH_KSM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define PSEQ_HIB_WAKE_MASK__WATCH_KSM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define PSEQ_HIB_WAKE_MASK__WATCH_KSM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PSEQ_HIB_WAKE_MASK__WATCH_KSM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PSEQ_HIB_WAKE_MASK__WATCH_KSM__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_shub */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_shub_field watch_shub_field + * @brief macros for field watch_shub + * @details valid to wake on sensor hub trigger + * @{ + */ +#define PSEQ_HIB_WAKE_MASK__WATCH_SHUB__SHIFT 6 +#define PSEQ_HIB_WAKE_MASK__WATCH_SHUB__WIDTH 1 +#define PSEQ_HIB_WAKE_MASK__WATCH_SHUB__MASK 0x00000040U +#define PSEQ_HIB_WAKE_MASK__WATCH_SHUB__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define PSEQ_HIB_WAKE_MASK__WATCH_SHUB__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define PSEQ_HIB_WAKE_MASK__WATCH_SHUB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PSEQ_HIB_WAKE_MASK__WATCH_SHUB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PSEQ_HIB_WAKE_MASK__WATCH_SHUB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PSEQ_HIB_WAKE_MASK__WATCH_SHUB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PSEQ_HIB_WAKE_MASK__WATCH_SHUB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_spi */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_spi_field watch_spi_field + * @brief macros for field watch_spi + * @details valid to wake on spi slave activity + * @{ + */ +#define PSEQ_HIB_WAKE_MASK__WATCH_SPI__SHIFT 7 +#define PSEQ_HIB_WAKE_MASK__WATCH_SPI__WIDTH 1 +#define PSEQ_HIB_WAKE_MASK__WATCH_SPI__MASK 0x00000080U +#define PSEQ_HIB_WAKE_MASK__WATCH_SPI__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define PSEQ_HIB_WAKE_MASK__WATCH_SPI__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define PSEQ_HIB_WAKE_MASK__WATCH_SPI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define PSEQ_HIB_WAKE_MASK__WATCH_SPI__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define PSEQ_HIB_WAKE_MASK__WATCH_SPI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define PSEQ_HIB_WAKE_MASK__WATCH_SPI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define PSEQ_HIB_WAKE_MASK__WATCH_SPI__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_i2c */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_i2c_field watch_i2c_field + * @brief macros for field watch_i2c + * @details valid to wake on i2c slave activity + * @{ + */ +#define PSEQ_HIB_WAKE_MASK__WATCH_I2C__SHIFT 8 +#define PSEQ_HIB_WAKE_MASK__WATCH_I2C__WIDTH 1 +#define PSEQ_HIB_WAKE_MASK__WATCH_I2C__MASK 0x00000100U +#define PSEQ_HIB_WAKE_MASK__WATCH_I2C__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define PSEQ_HIB_WAKE_MASK__WATCH_I2C__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define PSEQ_HIB_WAKE_MASK__WATCH_I2C__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define PSEQ_HIB_WAKE_MASK__WATCH_I2C__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define PSEQ_HIB_WAKE_MASK__WATCH_I2C__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PSEQ_HIB_WAKE_MASK__WATCH_I2C__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PSEQ_HIB_WAKE_MASK__WATCH_I2C__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_pmu_lpcomp */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_pmu_lpcomp_field watch_pmu_lpcomp_field + * @brief macros for field watch_pmu_lpcomp + * @details valid to wake on pmu lpcomp threshold crossing + * @{ + */ +#define PSEQ_HIB_WAKE_MASK__WATCH_PMU_LPCOMP__SHIFT 9 +#define PSEQ_HIB_WAKE_MASK__WATCH_PMU_LPCOMP__WIDTH 1 +#define PSEQ_HIB_WAKE_MASK__WATCH_PMU_LPCOMP__MASK 0x00000200U +#define PSEQ_HIB_WAKE_MASK__WATCH_PMU_LPCOMP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PSEQ_HIB_WAKE_MASK__WATCH_PMU_LPCOMP__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define PSEQ_HIB_WAKE_MASK__WATCH_PMU_LPCOMP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define PSEQ_HIB_WAKE_MASK__WATCH_PMU_LPCOMP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define PSEQ_HIB_WAKE_MASK__WATCH_PMU_LPCOMP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PSEQ_HIB_WAKE_MASK__WATCH_PMU_LPCOMP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PSEQ_HIB_WAKE_MASK__WATCH_PMU_LPCOMP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_pmu_timer */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_pmu_timer_field watch_pmu_timer_field + * @brief macros for field watch_pmu_timer + * @details valid to wake on pmu timer expiring + * @{ + */ +#define PSEQ_HIB_WAKE_MASK__WATCH_PMU_TIMER__SHIFT 10 +#define PSEQ_HIB_WAKE_MASK__WATCH_PMU_TIMER__WIDTH 1 +#define PSEQ_HIB_WAKE_MASK__WATCH_PMU_TIMER__MASK 0x00000400U +#define PSEQ_HIB_WAKE_MASK__WATCH_PMU_TIMER__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define PSEQ_HIB_WAKE_MASK__WATCH_PMU_TIMER__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define PSEQ_HIB_WAKE_MASK__WATCH_PMU_TIMER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define PSEQ_HIB_WAKE_MASK__WATCH_PMU_TIMER__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define PSEQ_HIB_WAKE_MASK__WATCH_PMU_TIMER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define PSEQ_HIB_WAKE_MASK__WATCH_PMU_TIMER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define PSEQ_HIB_WAKE_MASK__WATCH_PMU_TIMER__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_energy4CPU */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_energy4CPU_field watch_energy4CPU_field + * @brief macros for field watch_energy4CPU + * @details valid to wake on pmu asserting energy4CPU + * @{ + */ +#define PSEQ_HIB_WAKE_MASK__WATCH_ENERGY4CPU__SHIFT 11 +#define PSEQ_HIB_WAKE_MASK__WATCH_ENERGY4CPU__WIDTH 1 +#define PSEQ_HIB_WAKE_MASK__WATCH_ENERGY4CPU__MASK 0x00000800U +#define PSEQ_HIB_WAKE_MASK__WATCH_ENERGY4CPU__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define PSEQ_HIB_WAKE_MASK__WATCH_ENERGY4CPU__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define PSEQ_HIB_WAKE_MASK__WATCH_ENERGY4CPU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define PSEQ_HIB_WAKE_MASK__WATCH_ENERGY4CPU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define PSEQ_HIB_WAKE_MASK__WATCH_ENERGY4CPU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define PSEQ_HIB_WAKE_MASK__WATCH_ENERGY4CPU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define PSEQ_HIB_WAKE_MASK__WATCH_ENERGY4CPU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_energy4TX */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_energy4TX_field watch_energy4TX_field + * @brief macros for field watch_energy4TX + * @details valid to wake on pmu asserting energy4TX + * @{ + */ +#define PSEQ_HIB_WAKE_MASK__WATCH_ENERGY4TX__SHIFT 12 +#define PSEQ_HIB_WAKE_MASK__WATCH_ENERGY4TX__WIDTH 1 +#define PSEQ_HIB_WAKE_MASK__WATCH_ENERGY4TX__MASK 0x00001000U +#define PSEQ_HIB_WAKE_MASK__WATCH_ENERGY4TX__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define PSEQ_HIB_WAKE_MASK__WATCH_ENERGY4TX__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define PSEQ_HIB_WAKE_MASK__WATCH_ENERGY4TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define PSEQ_HIB_WAKE_MASK__WATCH_ENERGY4TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define PSEQ_HIB_WAKE_MASK__WATCH_ENERGY4TX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define PSEQ_HIB_WAKE_MASK__WATCH_ENERGY4TX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define PSEQ_HIB_WAKE_MASK__WATCH_ENERGY4TX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_endoflife */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_endoflife_field watch_endoflife_field + * @brief macros for field watch_endoflife + * @details valid to wake on pmu asserting endoflife + * @{ + */ +#define PSEQ_HIB_WAKE_MASK__WATCH_ENDOFLIFE__SHIFT 13 +#define PSEQ_HIB_WAKE_MASK__WATCH_ENDOFLIFE__WIDTH 1 +#define PSEQ_HIB_WAKE_MASK__WATCH_ENDOFLIFE__MASK 0x00002000U +#define PSEQ_HIB_WAKE_MASK__WATCH_ENDOFLIFE__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define PSEQ_HIB_WAKE_MASK__WATCH_ENDOFLIFE__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define PSEQ_HIB_WAKE_MASK__WATCH_ENDOFLIFE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define PSEQ_HIB_WAKE_MASK__WATCH_ENDOFLIFE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define PSEQ_HIB_WAKE_MASK__WATCH_ENDOFLIFE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define PSEQ_HIB_WAKE_MASK__WATCH_ENDOFLIFE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define PSEQ_HIB_WAKE_MASK__WATCH_ENDOFLIFE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_brownout */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_brownout_field watch_brownout_field + * @brief macros for field watch_brownout + * @details valid to wake on pmu asserting brownout + * @{ + */ +#define PSEQ_HIB_WAKE_MASK__WATCH_BROWNOUT__SHIFT 14 +#define PSEQ_HIB_WAKE_MASK__WATCH_BROWNOUT__WIDTH 1 +#define PSEQ_HIB_WAKE_MASK__WATCH_BROWNOUT__MASK 0x00004000U +#define PSEQ_HIB_WAKE_MASK__WATCH_BROWNOUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PSEQ_HIB_WAKE_MASK__WATCH_BROWNOUT__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define PSEQ_HIB_WAKE_MASK__WATCH_BROWNOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define PSEQ_HIB_WAKE_MASK__WATCH_BROWNOUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define PSEQ_HIB_WAKE_MASK__WATCH_BROWNOUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PSEQ_HIB_WAKE_MASK__WATCH_BROWNOUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PSEQ_HIB_WAKE_MASK__WATCH_BROWNOUT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_wurx */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_wurx_field watch_wurx_field + * @brief macros for field watch_wurx + * @details valid to wake on multiple wurx detects in certain amount of time + * @{ + */ +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX__SHIFT 15 +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX__WIDTH 1 +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX__MASK 0x00008000U +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PSEQ_HIB_WAKE_MASK__WATCH_WURX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_ble_osc_on */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_ble_osc_on_field watch_ble_osc_on_field + * @brief macros for field watch_ble_osc_on + * @{ + */ +#define PSEQ_HIB_WAKE_MASK__WATCH_BLE_OSC_ON__SHIFT 16 +#define PSEQ_HIB_WAKE_MASK__WATCH_BLE_OSC_ON__WIDTH 1 +#define PSEQ_HIB_WAKE_MASK__WATCH_BLE_OSC_ON__MASK 0x00010000U +#define PSEQ_HIB_WAKE_MASK__WATCH_BLE_OSC_ON__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define PSEQ_HIB_WAKE_MASK__WATCH_BLE_OSC_ON__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define PSEQ_HIB_WAKE_MASK__WATCH_BLE_OSC_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define PSEQ_HIB_WAKE_MASK__WATCH_BLE_OSC_ON__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define PSEQ_HIB_WAKE_MASK__WATCH_BLE_OSC_ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PSEQ_HIB_WAKE_MASK__WATCH_BLE_OSC_ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PSEQ_HIB_WAKE_MASK__WATCH_BLE_OSC_ON__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field qualify_on_energy4TX */ +/** + * @defgroup at_apb_pseq_paris_regs_core_qualify_on_energy4TX_field qualify_on_energy4TX_field + * @brief macros for field qualify_on_energy4TX + * @{ + */ +#define PSEQ_HIB_WAKE_MASK__QUALIFY_ON_ENERGY4TX__SHIFT 30 +#define PSEQ_HIB_WAKE_MASK__QUALIFY_ON_ENERGY4TX__WIDTH 1 +#define PSEQ_HIB_WAKE_MASK__QUALIFY_ON_ENERGY4TX__MASK 0x40000000U +#define PSEQ_HIB_WAKE_MASK__QUALIFY_ON_ENERGY4TX__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define PSEQ_HIB_WAKE_MASK__QUALIFY_ON_ENERGY4TX__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define PSEQ_HIB_WAKE_MASK__QUALIFY_ON_ENERGY4TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define PSEQ_HIB_WAKE_MASK__QUALIFY_ON_ENERGY4TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define PSEQ_HIB_WAKE_MASK__QUALIFY_ON_ENERGY4TX__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define PSEQ_HIB_WAKE_MASK__QUALIFY_ON_ENERGY4TX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define PSEQ_HIB_WAKE_MASK__QUALIFY_ON_ENERGY4TX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field qualify_on_energy4CPU */ +/** + * @defgroup at_apb_pseq_paris_regs_core_qualify_on_energy4CPU_field qualify_on_energy4CPU_field + * @brief macros for field qualify_on_energy4CPU + * @{ + */ +#define PSEQ_HIB_WAKE_MASK__QUALIFY_ON_ENERGY4CPU__SHIFT 31 +#define PSEQ_HIB_WAKE_MASK__QUALIFY_ON_ENERGY4CPU__WIDTH 1 +#define PSEQ_HIB_WAKE_MASK__QUALIFY_ON_ENERGY4CPU__MASK 0x80000000U +#define PSEQ_HIB_WAKE_MASK__QUALIFY_ON_ENERGY4CPU__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define PSEQ_HIB_WAKE_MASK__QUALIFY_ON_ENERGY4CPU__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define PSEQ_HIB_WAKE_MASK__QUALIFY_ON_ENERGY4CPU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define PSEQ_HIB_WAKE_MASK__QUALIFY_ON_ENERGY4CPU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define PSEQ_HIB_WAKE_MASK__QUALIFY_ON_ENERGY4CPU__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PSEQ_HIB_WAKE_MASK__QUALIFY_ON_ENERGY4CPU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PSEQ_HIB_WAKE_MASK__QUALIFY_ON_ENERGY4CPU__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_HIB_WAKE_MASK__TYPE uint32_t +#define PSEQ_HIB_WAKE_MASK__READ 0xc001ffffU +#define PSEQ_HIB_WAKE_MASK__WRITE 0xc001ffffU +#define PSEQ_HIB_WAKE_MASK__PRESERVED 0x00000000U +#define PSEQ_HIB_WAKE_MASK__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_HIB_WAKE_MASK_MACRO__ */ + +/** @} end of hib_wake_mask */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_ble_ret_to_ble_act_wake_mask */ +/** + * @defgroup at_apb_pseq_paris_regs_core_ble_ret_to_ble_act_wake_mask ble_ret_to_ble_act_wake_mask + * @brief signals to select which events can generate a wake event while in BLE Retain and go to BLE Act definitions. + * @{ + */ +#ifndef __PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK_MACRO__ +#define __PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK_MACRO__ + +/* macros for field watch_gpio */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_gpio_field watch_gpio_field + * @brief macros for field watch_gpio + * @details valid to wake on gpio activity + * @{ + */ +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_GPIO__SHIFT 0 +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_GPIO__WIDTH 1 +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_GPIO__MASK 0x00000001U +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_GPIO__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_GPIO__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_GPIO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_GPIO__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_GPIO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_GPIO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_GPIO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_cntdown */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_cntdown_field watch_cntdown_field + * @brief macros for field watch_cntdown + * @details valid to wake on count down timer expiring + * @{ + */ +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_CNTDOWN__SHIFT 1 +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_CNTDOWN__WIDTH 1 +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_CNTDOWN__MASK 0x00000002U +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_CNTDOWN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_CNTDOWN__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_CNTDOWN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_CNTDOWN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_CNTDOWN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_CNTDOWN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_CNTDOWN__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field watch_wurx0 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_wurx0_field watch_wurx0_field + * @brief macros for field watch_wurx0 + * @details valid to wake on wurx0 detect + * @{ + */ +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_WURX0__SHIFT 2 +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_WURX0__WIDTH 1 +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_WURX0__MASK 0x00000004U +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_WURX0__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_WURX0__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_WURX0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_WURX0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_WURX0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_WURX0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_WURX0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_wurx1 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_wurx1_field watch_wurx1_field + * @brief macros for field watch_wurx1 + * @details valid to wake on wurx1 detect + * @{ + */ +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_WURX1__SHIFT 3 +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_WURX1__WIDTH 1 +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_WURX1__MASK 0x00000008U +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_WURX1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_WURX1__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_WURX1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_WURX1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_WURX1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_WURX1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_WURX1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_qdec */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_qdec_field watch_qdec_field + * @brief macros for field watch_qdec + * @details valid to wake on qdec activity + * @{ + */ +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_QDEC__SHIFT 4 +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_QDEC__WIDTH 1 +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_QDEC__MASK 0x00000010U +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_QDEC__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_QDEC__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_QDEC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_QDEC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_QDEC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_QDEC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_QDEC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_ksm */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_ksm_field watch_ksm_field + * @brief macros for field watch_ksm + * @details valid to wake on keyboard activity + * @{ + */ +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_KSM__SHIFT 5 +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_KSM__WIDTH 1 +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_KSM__MASK 0x00000020U +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_KSM__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_KSM__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_KSM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_KSM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_KSM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_KSM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_KSM__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_shub */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_shub_field watch_shub_field + * @brief macros for field watch_shub + * @details valid to wake on sensor hub trigger + * @{ + */ +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_SHUB__SHIFT 6 +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_SHUB__WIDTH 1 +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_SHUB__MASK 0x00000040U +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_SHUB__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_SHUB__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_SHUB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_SHUB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_SHUB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_SHUB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WATCH_SHUB__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__TYPE uint32_t +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__READ 0x0000007fU +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__WRITE 0x0000007fU +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__PRESERVED 0x00000000U +#define PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_BLE_RET_TO_BLE_ACT_WAKE_MASK_MACRO__ */ + +/** @} end of ble_ret_to_ble_act_wake_mask */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_ble_ret_to_cpu_act_wake_mask */ +/** + * @defgroup at_apb_pseq_paris_regs_core_ble_ret_to_cpu_act_wake_mask ble_ret_to_cpu_act_wake_mask + * @brief signals to select which events can generate a wake event while in BLE Retain and go to CPU Act definitions. + * @{ + */ +#ifndef __PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK_MACRO__ +#define __PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK_MACRO__ + +/* macros for field watch_gpio */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_gpio_field watch_gpio_field + * @brief macros for field watch_gpio + * @details valid to wake on gpio activity + * @{ + */ +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_GPIO__SHIFT 0 +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_GPIO__WIDTH 1 +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_GPIO__MASK 0x00000001U +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_GPIO__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_GPIO__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_GPIO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_GPIO__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_GPIO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_GPIO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_GPIO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_cntdown */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_cntdown_field watch_cntdown_field + * @brief macros for field watch_cntdown + * @details valid to wake on count down timer expiring + * @{ + */ +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_CNTDOWN__SHIFT 1 +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_CNTDOWN__WIDTH 1 +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_CNTDOWN__MASK 0x00000002U +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_CNTDOWN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_CNTDOWN__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_CNTDOWN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_CNTDOWN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_CNTDOWN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_CNTDOWN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_CNTDOWN__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field watch_wurx0 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_wurx0_field watch_wurx0_field + * @brief macros for field watch_wurx0 + * @details valid to wake on wurx0 detect + * @{ + */ +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_WURX0__SHIFT 2 +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_WURX0__WIDTH 1 +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_WURX0__MASK 0x00000004U +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_WURX0__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_WURX0__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_WURX0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_WURX0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_WURX0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_WURX0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_WURX0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_wurx1 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_wurx1_field watch_wurx1_field + * @brief macros for field watch_wurx1 + * @details valid to wake on wurx1 detect + * @{ + */ +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_WURX1__SHIFT 3 +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_WURX1__WIDTH 1 +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_WURX1__MASK 0x00000008U +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_WURX1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_WURX1__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_WURX1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_WURX1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_WURX1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_WURX1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_WURX1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_qdec */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_qdec_field watch_qdec_field + * @brief macros for field watch_qdec + * @details valid to wake on qdec activity + * @{ + */ +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_QDEC__SHIFT 4 +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_QDEC__WIDTH 1 +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_QDEC__MASK 0x00000010U +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_QDEC__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_QDEC__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_QDEC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_QDEC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_QDEC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_QDEC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_QDEC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_ksm */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_ksm_field watch_ksm_field + * @brief macros for field watch_ksm + * @details valid to wake on keyboard activity + * @{ + */ +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_KSM__SHIFT 5 +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_KSM__WIDTH 1 +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_KSM__MASK 0x00000020U +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_KSM__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_KSM__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_KSM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_KSM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_KSM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_KSM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_KSM__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field watch_shub */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_shub_field watch_shub_field + * @brief macros for field watch_shub + * @details valid to wake on sensor hub trigger + * @{ + */ +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_SHUB__SHIFT 6 +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_SHUB__WIDTH 1 +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_SHUB__MASK 0x00000040U +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_SHUB__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_SHUB__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_SHUB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_SHUB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_SHUB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_SHUB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WATCH_SHUB__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__TYPE uint32_t +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__READ 0x0000007fU +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__WRITE 0x0000007fU +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__PRESERVED 0x00000000U +#define PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_BLE_RET_TO_CPU_ACT_WAKE_MASK_MACRO__ */ + +/** @} end of ble_ret_to_cpu_act_wake_mask */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_gpio_wake_mask */ +/** + * @defgroup at_apb_pseq_paris_regs_core_gpio_wake_mask gpio_wake_mask + * @brief mask function to specify which gpio's can generate a gpio event definitions. + * @{ + */ +#ifndef __PSEQ_GPIO_WAKE_MASK_MACRO__ +#define __PSEQ_GPIO_WAKE_MASK_MACRO__ + +/* macros for field lower */ +/** + * @defgroup at_apb_pseq_paris_regs_core_lower_field lower_field + * @brief macros for field lower + * @details lower 16 gpio's + * @{ + */ +#define PSEQ_GPIO_WAKE_MASK__LOWER__SHIFT 0 +#define PSEQ_GPIO_WAKE_MASK__LOWER__WIDTH 16 +#define PSEQ_GPIO_WAKE_MASK__LOWER__MASK 0x0000ffffU +#define PSEQ_GPIO_WAKE_MASK__LOWER__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define PSEQ_GPIO_WAKE_MASK__LOWER__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define PSEQ_GPIO_WAKE_MASK__LOWER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define PSEQ_GPIO_WAKE_MASK__LOWER__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000ffffU))) +#define PSEQ_GPIO_WAKE_MASK__LOWER__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field upper */ +/** + * @defgroup at_apb_pseq_paris_regs_core_upper_field upper_field + * @brief macros for field upper + * @details upper 16 gpio's + * @{ + */ +#define PSEQ_GPIO_WAKE_MASK__UPPER__SHIFT 16 +#define PSEQ_GPIO_WAKE_MASK__UPPER__WIDTH 16 +#define PSEQ_GPIO_WAKE_MASK__UPPER__MASK 0xffff0000U +#define PSEQ_GPIO_WAKE_MASK__UPPER__READ(src) \ + (((uint32_t)(src)\ + & 0xffff0000U) >> 16) +#define PSEQ_GPIO_WAKE_MASK__UPPER__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0xffff0000U) +#define PSEQ_GPIO_WAKE_MASK__UPPER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define PSEQ_GPIO_WAKE_MASK__UPPER__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define PSEQ_GPIO_WAKE_MASK__UPPER__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_GPIO_WAKE_MASK__TYPE uint32_t +#define PSEQ_GPIO_WAKE_MASK__READ 0xffffffffU +#define PSEQ_GPIO_WAKE_MASK__WRITE 0xffffffffU +#define PSEQ_GPIO_WAKE_MASK__PRESERVED 0x00000000U +#define PSEQ_GPIO_WAKE_MASK__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_GPIO_WAKE_MASK_MACRO__ */ + +/** @} end of gpio_wake_mask */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_gpio_wake_type */ +/** + * @defgroup at_apb_pseq_paris_regs_core_gpio_wake_type gpio_wake_type + * @brief specifies how a gpio generates an event definitions. + * @{ + */ +#ifndef __PSEQ_GPIO_WAKE_TYPE_MACRO__ +#define __PSEQ_GPIO_WAKE_TYPE_MACRO__ + +/* macros for field lower */ +/** + * @defgroup at_apb_pseq_paris_regs_core_lower_field lower_field + * @brief macros for field lower + * @details (per bit) 1 = edge sensitive , 0 = level + * @{ + */ +#define PSEQ_GPIO_WAKE_TYPE__LOWER__SHIFT 0 +#define PSEQ_GPIO_WAKE_TYPE__LOWER__WIDTH 16 +#define PSEQ_GPIO_WAKE_TYPE__LOWER__MASK 0x0000ffffU +#define PSEQ_GPIO_WAKE_TYPE__LOWER__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define PSEQ_GPIO_WAKE_TYPE__LOWER__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define PSEQ_GPIO_WAKE_TYPE__LOWER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define PSEQ_GPIO_WAKE_TYPE__LOWER__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000ffffU))) +#define PSEQ_GPIO_WAKE_TYPE__LOWER__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field upper */ +/** + * @defgroup at_apb_pseq_paris_regs_core_upper_field upper_field + * @brief macros for field upper + * @details (per bit) 1 = edge sensitive , 0 = level + * @{ + */ +#define PSEQ_GPIO_WAKE_TYPE__UPPER__SHIFT 16 +#define PSEQ_GPIO_WAKE_TYPE__UPPER__WIDTH 16 +#define PSEQ_GPIO_WAKE_TYPE__UPPER__MASK 0xffff0000U +#define PSEQ_GPIO_WAKE_TYPE__UPPER__READ(src) \ + (((uint32_t)(src)\ + & 0xffff0000U) >> 16) +#define PSEQ_GPIO_WAKE_TYPE__UPPER__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0xffff0000U) +#define PSEQ_GPIO_WAKE_TYPE__UPPER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define PSEQ_GPIO_WAKE_TYPE__UPPER__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define PSEQ_GPIO_WAKE_TYPE__UPPER__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_GPIO_WAKE_TYPE__TYPE uint32_t +#define PSEQ_GPIO_WAKE_TYPE__READ 0xffffffffU +#define PSEQ_GPIO_WAKE_TYPE__WRITE 0xffffffffU +#define PSEQ_GPIO_WAKE_TYPE__PRESERVED 0x00000000U +#define PSEQ_GPIO_WAKE_TYPE__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_GPIO_WAKE_TYPE_MACRO__ */ + +/** @} end of gpio_wake_type */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_gpio_wake_pol */ +/** + * @defgroup at_apb_pseq_paris_regs_core_gpio_wake_pol gpio_wake_pol + * @brief specifies how a gpio generates an event definitions. + * @{ + */ +#ifndef __PSEQ_GPIO_WAKE_POL_MACRO__ +#define __PSEQ_GPIO_WAKE_POL_MACRO__ + +/* macros for field lower */ +/** + * @defgroup at_apb_pseq_paris_regs_core_lower_field lower_field + * @brief macros for field lower + * @details (per bit) 1 = level high/rising edge , 0 = level low/falling edge + * @{ + */ +#define PSEQ_GPIO_WAKE_POL__LOWER__SHIFT 0 +#define PSEQ_GPIO_WAKE_POL__LOWER__WIDTH 16 +#define PSEQ_GPIO_WAKE_POL__LOWER__MASK 0x0000ffffU +#define PSEQ_GPIO_WAKE_POL__LOWER__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define PSEQ_GPIO_WAKE_POL__LOWER__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define PSEQ_GPIO_WAKE_POL__LOWER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define PSEQ_GPIO_WAKE_POL__LOWER__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000ffffU))) +#define PSEQ_GPIO_WAKE_POL__LOWER__RESET_VALUE 0x0000ffffU +/** @} */ + +/* macros for field upper */ +/** + * @defgroup at_apb_pseq_paris_regs_core_upper_field upper_field + * @brief macros for field upper + * @details (per bit) 1 = level high/rising edge , 0 = level low/falling edge + * @{ + */ +#define PSEQ_GPIO_WAKE_POL__UPPER__SHIFT 16 +#define PSEQ_GPIO_WAKE_POL__UPPER__WIDTH 16 +#define PSEQ_GPIO_WAKE_POL__UPPER__MASK 0xffff0000U +#define PSEQ_GPIO_WAKE_POL__UPPER__READ(src) \ + (((uint32_t)(src)\ + & 0xffff0000U) >> 16) +#define PSEQ_GPIO_WAKE_POL__UPPER__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0xffff0000U) +#define PSEQ_GPIO_WAKE_POL__UPPER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define PSEQ_GPIO_WAKE_POL__UPPER__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define PSEQ_GPIO_WAKE_POL__UPPER__RESET_VALUE 0x0000ffffU +/** @} */ +#define PSEQ_GPIO_WAKE_POL__TYPE uint32_t +#define PSEQ_GPIO_WAKE_POL__READ 0xffffffffU +#define PSEQ_GPIO_WAKE_POL__WRITE 0xffffffffU +#define PSEQ_GPIO_WAKE_POL__PRESERVED 0x00000000U +#define PSEQ_GPIO_WAKE_POL__RESET_VALUE 0xffffffffU + +#endif /* __PSEQ_GPIO_WAKE_POL_MACRO__ */ + +/** @} end of gpio_wake_pol */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_gpio_wake_both_edges */ +/** + * @defgroup at_apb_pseq_paris_regs_core_gpio_wake_both_edges gpio_wake_both_edges + * @brief specifies how a gpio generates an event definitions. + * @{ + */ +#ifndef __PSEQ_GPIO_WAKE_BOTH_EDGES_MACRO__ +#define __PSEQ_GPIO_WAKE_BOTH_EDGES_MACRO__ + +/* macros for field lower */ +/** + * @defgroup at_apb_pseq_paris_regs_core_lower_field lower_field + * @brief macros for field lower + * @details (per bit) 1 = either edge will wake; higher precedence than gpio_wake_type and gpio_wake_pol + * @{ + */ +#define PSEQ_GPIO_WAKE_BOTH_EDGES__LOWER__SHIFT 0 +#define PSEQ_GPIO_WAKE_BOTH_EDGES__LOWER__WIDTH 16 +#define PSEQ_GPIO_WAKE_BOTH_EDGES__LOWER__MASK 0x0000ffffU +#define PSEQ_GPIO_WAKE_BOTH_EDGES__LOWER__READ(src) \ + ((uint32_t)(src)\ + & 0x0000ffffU) +#define PSEQ_GPIO_WAKE_BOTH_EDGES__LOWER__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000ffffU) +#define PSEQ_GPIO_WAKE_BOTH_EDGES__LOWER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define PSEQ_GPIO_WAKE_BOTH_EDGES__LOWER__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000ffffU))) +#define PSEQ_GPIO_WAKE_BOTH_EDGES__LOWER__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field upper */ +/** + * @defgroup at_apb_pseq_paris_regs_core_upper_field upper_field + * @brief macros for field upper + * @details (per bit) 1 = either edge will wake; higher precedence than gpio_wake_type and gpio_wake_pol + * @{ + */ +#define PSEQ_GPIO_WAKE_BOTH_EDGES__UPPER__SHIFT 16 +#define PSEQ_GPIO_WAKE_BOTH_EDGES__UPPER__WIDTH 16 +#define PSEQ_GPIO_WAKE_BOTH_EDGES__UPPER__MASK 0xffff0000U +#define PSEQ_GPIO_WAKE_BOTH_EDGES__UPPER__READ(src) \ + (((uint32_t)(src)\ + & 0xffff0000U) >> 16) +#define PSEQ_GPIO_WAKE_BOTH_EDGES__UPPER__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0xffff0000U) +#define PSEQ_GPIO_WAKE_BOTH_EDGES__UPPER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define PSEQ_GPIO_WAKE_BOTH_EDGES__UPPER__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define PSEQ_GPIO_WAKE_BOTH_EDGES__UPPER__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_GPIO_WAKE_BOTH_EDGES__TYPE uint32_t +#define PSEQ_GPIO_WAKE_BOTH_EDGES__READ 0xffffffffU +#define PSEQ_GPIO_WAKE_BOTH_EDGES__WRITE 0xffffffffU +#define PSEQ_GPIO_WAKE_BOTH_EDGES__PRESERVED 0x00000000U +#define PSEQ_GPIO_WAKE_BOTH_EDGES__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_GPIO_WAKE_BOTH_EDGES_MACRO__ */ + +/** @} end of gpio_wake_both_edges */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_gpio_wake_status */ +/** + * @defgroup at_apb_pseq_paris_regs_core_gpio_wake_status gpio_wake_status + * @brief specifies which gpio caused the wake definitions. + * @{ + */ +#ifndef __PSEQ_GPIO_WAKE_STATUS_MACRO__ +#define __PSEQ_GPIO_WAKE_STATUS_MACRO__ + +/* macros for field lower */ +/** + * @defgroup at_apb_pseq_paris_regs_core_lower_field lower_field + * @brief macros for field lower + * @{ + */ +#define PSEQ_GPIO_WAKE_STATUS__LOWER__SHIFT 0 +#define PSEQ_GPIO_WAKE_STATUS__LOWER__WIDTH 16 +#define PSEQ_GPIO_WAKE_STATUS__LOWER__MASK 0x0000ffffU +#define PSEQ_GPIO_WAKE_STATUS__LOWER__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define PSEQ_GPIO_WAKE_STATUS__LOWER__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field upper */ +/** + * @defgroup at_apb_pseq_paris_regs_core_upper_field upper_field + * @brief macros for field upper + * @{ + */ +#define PSEQ_GPIO_WAKE_STATUS__UPPER__SHIFT 16 +#define PSEQ_GPIO_WAKE_STATUS__UPPER__WIDTH 16 +#define PSEQ_GPIO_WAKE_STATUS__UPPER__MASK 0xffff0000U +#define PSEQ_GPIO_WAKE_STATUS__UPPER__READ(src) \ + (((uint32_t)(src)\ + & 0xffff0000U) >> 16) +#define PSEQ_GPIO_WAKE_STATUS__UPPER__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_GPIO_WAKE_STATUS__TYPE uint32_t +#define PSEQ_GPIO_WAKE_STATUS__READ 0xffffffffU +#define PSEQ_GPIO_WAKE_STATUS__PRESERVED 0x00000000U +#define PSEQ_GPIO_WAKE_STATUS__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_GPIO_WAKE_STATUS_MACRO__ */ + +/** @} end of gpio_wake_status */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_wurx_config */ +/** + * @defgroup at_apb_pseq_paris_regs_core_wurx_config wurx_config + * @brief wurx configuration definitions. + * @{ + */ +#ifndef __PSEQ_WURX_CONFIG_MACRO__ +#define __PSEQ_WURX_CONFIG_MACRO__ + +/* macros for field wurx_en */ +/** + * @defgroup at_apb_pseq_paris_regs_core_wurx_en_field wurx_en_field + * @brief macros for field wurx_en + * @details if low, disables wurx datapath + * @{ + */ +#define PSEQ_WURX_CONFIG__WURX_EN__SHIFT 0 +#define PSEQ_WURX_CONFIG__WURX_EN__WIDTH 1 +#define PSEQ_WURX_CONFIG__WURX_EN__MASK 0x00000001U +#define PSEQ_WURX_CONFIG__WURX_EN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PSEQ_WURX_CONFIG__WURX_EN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PSEQ_WURX_CONFIG__WURX_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_WURX_CONFIG__WURX_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_WURX_CONFIG__WURX_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_WURX_CONFIG__WURX_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_WURX_CONFIG__WURX_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wurx_rstb */ +/** + * @defgroup at_apb_pseq_paris_regs_core_wurx_rstb_field wurx_rstb_field + * @brief macros for field wurx_rstb + * @details if low, holds wurx in reset + * @{ + */ +#define PSEQ_WURX_CONFIG__WURX_RSTB__SHIFT 1 +#define PSEQ_WURX_CONFIG__WURX_RSTB__WIDTH 1 +#define PSEQ_WURX_CONFIG__WURX_RSTB__MASK 0x00000002U +#define PSEQ_WURX_CONFIG__WURX_RSTB__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_WURX_CONFIG__WURX_RSTB__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PSEQ_WURX_CONFIG__WURX_RSTB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PSEQ_WURX_CONFIG__WURX_RSTB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PSEQ_WURX_CONFIG__WURX_RSTB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_WURX_CONFIG__WURX_RSTB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_WURX_CONFIG__WURX_RSTB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wurx_cutvdd_b */ +/** + * @defgroup at_apb_pseq_paris_regs_core_wurx_cutvdd_b_field wurx_cutvdd_b_field + * @brief macros for field wurx_cutvdd_b + * @details if low, removes power from wurx + * @{ + */ +#define PSEQ_WURX_CONFIG__WURX_CUTVDD_B__SHIFT 2 +#define PSEQ_WURX_CONFIG__WURX_CUTVDD_B__WIDTH 1 +#define PSEQ_WURX_CONFIG__WURX_CUTVDD_B__MASK 0x00000004U +#define PSEQ_WURX_CONFIG__WURX_CUTVDD_B__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PSEQ_WURX_CONFIG__WURX_CUTVDD_B__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PSEQ_WURX_CONFIG__WURX_CUTVDD_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PSEQ_WURX_CONFIG__WURX_CUTVDD_B__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PSEQ_WURX_CONFIG__WURX_CUTVDD_B__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PSEQ_WURX_CONFIG__WURX_CUTVDD_B__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PSEQ_WURX_CONFIG__WURX_CUTVDD_B__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_WURX_CONFIG__TYPE uint32_t +#define PSEQ_WURX_CONFIG__READ 0x00000007U +#define PSEQ_WURX_CONFIG__WRITE 0x00000007U +#define PSEQ_WURX_CONFIG__PRESERVED 0x00000000U +#define PSEQ_WURX_CONFIG__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_WURX_CONFIG_MACRO__ */ + +/** @} end of wurx_config */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_wurx_config1 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_wurx_config1 wurx_config1 + * @brief wurx configuration definitions. + * @{ + */ +#ifndef __PSEQ_WURX_CONFIG1_MACRO__ +#define __PSEQ_WURX_CONFIG1_MACRO__ + +/* macros for field wurx_src_sel */ +/** + * @defgroup at_apb_pseq_paris_regs_core_wurx_src_sel_field wurx_src_sel_field + * @brief macros for field wurx_src_sel + * @details which multiple wurx detect source to watch 0=wurx0 1=wurx1 2,3=wurx0 or wurx1 + * @{ + */ +#define PSEQ_WURX_CONFIG1__WURX_SRC_SEL__SHIFT 0 +#define PSEQ_WURX_CONFIG1__WURX_SRC_SEL__WIDTH 2 +#define PSEQ_WURX_CONFIG1__WURX_SRC_SEL__MASK 0x00000003U +#define PSEQ_WURX_CONFIG1__WURX_SRC_SEL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PSEQ_WURX_CONFIG1__WURX_SRC_SEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PSEQ_WURX_CONFIG1__WURX_SRC_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define PSEQ_WURX_CONFIG1__WURX_SRC_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define PSEQ_WURX_CONFIG1__WURX_SRC_SEL__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field num_wurx_event */ +/** + * @defgroup at_apb_pseq_paris_regs_core_num_wurx_event_field num_wurx_event_field + * @brief macros for field num_wurx_event + * @details Number of multiple wurx detect events to watch + * @{ + */ +#define PSEQ_WURX_CONFIG1__NUM_WURX_EVENT__SHIFT 2 +#define PSEQ_WURX_CONFIG1__NUM_WURX_EVENT__WIDTH 4 +#define PSEQ_WURX_CONFIG1__NUM_WURX_EVENT__MASK 0x0000003cU +#define PSEQ_WURX_CONFIG1__NUM_WURX_EVENT__READ(src) \ + (((uint32_t)(src)\ + & 0x0000003cU) >> 2) +#define PSEQ_WURX_CONFIG1__NUM_WURX_EVENT__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000003cU) +#define PSEQ_WURX_CONFIG1__NUM_WURX_EVENT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003cU) | (((uint32_t)(src) <<\ + 2) & 0x0000003cU) +#define PSEQ_WURX_CONFIG1__NUM_WURX_EVENT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000003cU))) +#define PSEQ_WURX_CONFIG1__NUM_WURX_EVENT__RESET_VALUE 0x00000008U +/** @} */ +#define PSEQ_WURX_CONFIG1__TYPE uint32_t +#define PSEQ_WURX_CONFIG1__READ 0x0000003fU +#define PSEQ_WURX_CONFIG1__WRITE 0x0000003fU +#define PSEQ_WURX_CONFIG1__PRESERVED 0x00000000U +#define PSEQ_WURX_CONFIG1__RESET_VALUE 0x00000022U + +#endif /* __PSEQ_WURX_CONFIG1_MACRO__ */ + +/** @} end of wurx_config1 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_wurx_config2 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_wurx_config2 wurx_config2 + * @brief wurx configuration definitions. + * @{ + */ +#ifndef __PSEQ_WURX_CONFIG2_MACRO__ +#define __PSEQ_WURX_CONFIG2_MACRO__ + +/* macros for field num_wurx_time0_cyc */ +/** + * @defgroup at_apb_pseq_paris_regs_core_num_wurx_time0_cyc_field num_wurx_time0_cyc_field + * @brief macros for field num_wurx_time0_cyc + * @details Full time window during multiple wurx detect events watching in 32KHz cycles, default 1sec window + * @{ + */ +#define PSEQ_WURX_CONFIG2__NUM_WURX_TIME0_CYC__SHIFT 0 +#define PSEQ_WURX_CONFIG2__NUM_WURX_TIME0_CYC__WIDTH 17 +#define PSEQ_WURX_CONFIG2__NUM_WURX_TIME0_CYC__MASK 0x0001ffffU +#define PSEQ_WURX_CONFIG2__NUM_WURX_TIME0_CYC__READ(src) \ + ((uint32_t)(src)\ + & 0x0001ffffU) +#define PSEQ_WURX_CONFIG2__NUM_WURX_TIME0_CYC__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0001ffffU) +#define PSEQ_WURX_CONFIG2__NUM_WURX_TIME0_CYC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001ffffU) | ((uint32_t)(src) &\ + 0x0001ffffU) +#define PSEQ_WURX_CONFIG2__NUM_WURX_TIME0_CYC__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0001ffffU))) +#define PSEQ_WURX_CONFIG2__NUM_WURX_TIME0_CYC__RESET_VALUE 0x00008000U +/** @} */ + +/* macros for field num_wurx_time1_cyc */ +/** + * @defgroup at_apb_pseq_paris_regs_core_num_wurx_time1_cyc_field num_wurx_time1_cyc_field + * @brief macros for field num_wurx_time1_cyc + * @details Max time window between two consecutive wurx detect events in 32KHz cycles, default 500msec window + * @{ + */ +#define PSEQ_WURX_CONFIG2__NUM_WURX_TIME1_CYC__SHIFT 17 +#define PSEQ_WURX_CONFIG2__NUM_WURX_TIME1_CYC__WIDTH 15 +#define PSEQ_WURX_CONFIG2__NUM_WURX_TIME1_CYC__MASK 0xfffe0000U +#define PSEQ_WURX_CONFIG2__NUM_WURX_TIME1_CYC__READ(src) \ + (((uint32_t)(src)\ + & 0xfffe0000U) >> 17) +#define PSEQ_WURX_CONFIG2__NUM_WURX_TIME1_CYC__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0xfffe0000U) +#define PSEQ_WURX_CONFIG2__NUM_WURX_TIME1_CYC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffe0000U) | (((uint32_t)(src) <<\ + 17) & 0xfffe0000U) +#define PSEQ_WURX_CONFIG2__NUM_WURX_TIME1_CYC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0xfffe0000U))) +#define PSEQ_WURX_CONFIG2__NUM_WURX_TIME1_CYC__RESET_VALUE 0x00004000U +/** @} */ +#define PSEQ_WURX_CONFIG2__TYPE uint32_t +#define PSEQ_WURX_CONFIG2__READ 0xffffffffU +#define PSEQ_WURX_CONFIG2__WRITE 0xffffffffU +#define PSEQ_WURX_CONFIG2__PRESERVED 0x00000000U +#define PSEQ_WURX_CONFIG2__RESET_VALUE 0x80008000U + +#endif /* __PSEQ_WURX_CONFIG2_MACRO__ */ + +/** @} end of wurx_config2 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_gadc_config */ +/** + * @defgroup at_apb_pseq_paris_regs_core_gadc_config gadc_config + * @brief gadc configuration definitions. + * @{ + */ +#ifndef __PSEQ_GADC_CONFIG_MACRO__ +#define __PSEQ_GADC_CONFIG_MACRO__ + +/* macros for field gadc_en */ +/** + * @defgroup at_apb_pseq_paris_regs_core_gadc_en_field gadc_en_field + * @brief macros for field gadc_en + * @details if low, disables gadc datapath + * @{ + */ +#define PSEQ_GADC_CONFIG__GADC_EN__SHIFT 0 +#define PSEQ_GADC_CONFIG__GADC_EN__WIDTH 1 +#define PSEQ_GADC_CONFIG__GADC_EN__MASK 0x00000001U +#define PSEQ_GADC_CONFIG__GADC_EN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PSEQ_GADC_CONFIG__GADC_EN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PSEQ_GADC_CONFIG__GADC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_GADC_CONFIG__GADC_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_GADC_CONFIG__GADC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_GADC_CONFIG__GADC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_GADC_CONFIG__GADC_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field gadc_rstb */ +/** + * @defgroup at_apb_pseq_paris_regs_core_gadc_rstb_field gadc_rstb_field + * @brief macros for field gadc_rstb + * @details if low, holds gadc in reset + * @{ + */ +#define PSEQ_GADC_CONFIG__GADC_RSTB__SHIFT 1 +#define PSEQ_GADC_CONFIG__GADC_RSTB__WIDTH 1 +#define PSEQ_GADC_CONFIG__GADC_RSTB__MASK 0x00000002U +#define PSEQ_GADC_CONFIG__GADC_RSTB__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_GADC_CONFIG__GADC_RSTB__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PSEQ_GADC_CONFIG__GADC_RSTB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PSEQ_GADC_CONFIG__GADC_RSTB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PSEQ_GADC_CONFIG__GADC_RSTB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_GADC_CONFIG__GADC_RSTB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_GADC_CONFIG__GADC_RSTB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field gadc_cutvdd_b */ +/** + * @defgroup at_apb_pseq_paris_regs_core_gadc_cutvdd_b_field gadc_cutvdd_b_field + * @brief macros for field gadc_cutvdd_b + * @details if low, removes power from gadc + * @{ + */ +#define PSEQ_GADC_CONFIG__GADC_CUTVDD_B__SHIFT 2 +#define PSEQ_GADC_CONFIG__GADC_CUTVDD_B__WIDTH 1 +#define PSEQ_GADC_CONFIG__GADC_CUTVDD_B__MASK 0x00000004U +#define PSEQ_GADC_CONFIG__GADC_CUTVDD_B__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PSEQ_GADC_CONFIG__GADC_CUTVDD_B__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PSEQ_GADC_CONFIG__GADC_CUTVDD_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PSEQ_GADC_CONFIG__GADC_CUTVDD_B__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PSEQ_GADC_CONFIG__GADC_CUTVDD_B__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PSEQ_GADC_CONFIG__GADC_CUTVDD_B__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PSEQ_GADC_CONFIG__GADC_CUTVDD_B__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_GADC_CONFIG__TYPE uint32_t +#define PSEQ_GADC_CONFIG__READ 0x00000007U +#define PSEQ_GADC_CONFIG__WRITE 0x00000007U +#define PSEQ_GADC_CONFIG__PRESERVED 0x00000000U +#define PSEQ_GADC_CONFIG__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_GADC_CONFIG_MACRO__ */ + +/** @} end of gadc_config */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_xtal_bits0 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_xtal_bits0 xtal_bits0 + * @brief control signals for clk_mpc crystal circuit definitions. + * @{ + */ +#ifndef __PSEQ_XTAL_BITS0_MACRO__ +#define __PSEQ_XTAL_BITS0_MACRO__ + +/* macros for field xtalfreq */ +/** + * @defgroup at_apb_pseq_paris_regs_core_xtalfreq_field xtalfreq_field + * @brief macros for field xtalfreq + * @details 0=16MHz 1=8MHz + * @{ + */ +#define PSEQ_XTAL_BITS0__XTALFREQ__SHIFT 0 +#define PSEQ_XTAL_BITS0__XTALFREQ__WIDTH 1 +#define PSEQ_XTAL_BITS0__XTALFREQ__MASK 0x00000001U +#define PSEQ_XTAL_BITS0__XTALFREQ__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PSEQ_XTAL_BITS0__XTALFREQ__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PSEQ_XTAL_BITS0__XTALFREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_XTAL_BITS0__XTALFREQ__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_XTAL_BITS0__XTALFREQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_XTAL_BITS0__XTALFREQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_XTAL_BITS0__XTALFREQ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field xocapin */ +/** + * @defgroup at_apb_pseq_paris_regs_core_xocapin_field xocapin_field + * @brief macros for field xocapin + * @details 16MHz crystal tuning cap on XTALI_16M pin, typically set to same value as xocapout + * @{ + */ +#define PSEQ_XTAL_BITS0__XOCAPIN__SHIFT 1 +#define PSEQ_XTAL_BITS0__XOCAPIN__WIDTH 8 +#define PSEQ_XTAL_BITS0__XOCAPIN__MASK 0x000001feU +#define PSEQ_XTAL_BITS0__XOCAPIN__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define PSEQ_XTAL_BITS0__XOCAPIN__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define PSEQ_XTAL_BITS0__XOCAPIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define PSEQ_XTAL_BITS0__XOCAPIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define PSEQ_XTAL_BITS0__XOCAPIN__RESET_VALUE 0x000000b3U +/** @} */ + +/* macros for field xocapout */ +/** + * @defgroup at_apb_pseq_paris_regs_core_xocapout_field xocapout_field + * @brief macros for field xocapout + * @details 16MHz crystal tuning cap on XTALO_16M pin, typically set to same value as xocapin + * @{ + */ +#define PSEQ_XTAL_BITS0__XOCAPOUT__SHIFT 9 +#define PSEQ_XTAL_BITS0__XOCAPOUT__WIDTH 8 +#define PSEQ_XTAL_BITS0__XOCAPOUT__MASK 0x0001fe00U +#define PSEQ_XTAL_BITS0__XOCAPOUT__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define PSEQ_XTAL_BITS0__XOCAPOUT__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define PSEQ_XTAL_BITS0__XOCAPOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define PSEQ_XTAL_BITS0__XOCAPOUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define PSEQ_XTAL_BITS0__XOCAPOUT__RESET_VALUE 0x000000b3U +/** @} */ + +/* macros for field xobufn */ +/** + * @defgroup at_apb_pseq_paris_regs_core_xobufn_field xobufn_field + * @brief macros for field xobufn + * @{ + */ +#define PSEQ_XTAL_BITS0__XOBUFN__SHIFT 17 +#define PSEQ_XTAL_BITS0__XOBUFN__WIDTH 2 +#define PSEQ_XTAL_BITS0__XOBUFN__MASK 0x00060000U +#define PSEQ_XTAL_BITS0__XOBUFN__READ(src) \ + (((uint32_t)(src)\ + & 0x00060000U) >> 17) +#define PSEQ_XTAL_BITS0__XOBUFN__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00060000U) +#define PSEQ_XTAL_BITS0__XOBUFN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00060000U) | (((uint32_t)(src) <<\ + 17) & 0x00060000U) +#define PSEQ_XTAL_BITS0__XOBUFN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00060000U))) +#define PSEQ_XTAL_BITS0__XOBUFN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field xobufp */ +/** + * @defgroup at_apb_pseq_paris_regs_core_xobufp_field xobufp_field + * @brief macros for field xobufp + * @{ + */ +#define PSEQ_XTAL_BITS0__XOBUFP__SHIFT 19 +#define PSEQ_XTAL_BITS0__XOBUFP__WIDTH 2 +#define PSEQ_XTAL_BITS0__XOBUFP__MASK 0x00180000U +#define PSEQ_XTAL_BITS0__XOBUFP__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define PSEQ_XTAL_BITS0__XOBUFP__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define PSEQ_XTAL_BITS0__XOBUFP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define PSEQ_XTAL_BITS0__XOBUFP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define PSEQ_XTAL_BITS0__XOBUFP__RESET_VALUE 0x00000001U +/** @} */ +#define PSEQ_XTAL_BITS0__TYPE uint32_t +#define PSEQ_XTAL_BITS0__READ 0x001fffffU +#define PSEQ_XTAL_BITS0__WRITE 0x001fffffU +#define PSEQ_XTAL_BITS0__PRESERVED 0x00000000U +#define PSEQ_XTAL_BITS0__RESET_VALUE 0x000b6766U + +#endif /* __PSEQ_XTAL_BITS0_MACRO__ */ + +/** @} end of xtal_bits0 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_xtal_bits1 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_xtal_bits1 xtal_bits1 + * @brief control signals for clk_mpc crystal circuit definitions. + * @{ + */ +#ifndef __PSEQ_XTAL_BITS1_MACRO__ +#define __PSEQ_XTAL_BITS1_MACRO__ + +/* macros for field xobias */ +/** + * @defgroup at_apb_pseq_paris_regs_core_xobias_field xobias_field + * @brief macros for field xobias + * @details 16MHz bias current setting or AGC target value when AGC enabled + * @{ + */ +#define PSEQ_XTAL_BITS1__XOBIAS__SHIFT 0 +#define PSEQ_XTAL_BITS1__XOBIAS__WIDTH 4 +#define PSEQ_XTAL_BITS1__XOBIAS__MASK 0x0000000fU +#define PSEQ_XTAL_BITS1__XOBIAS__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define PSEQ_XTAL_BITS1__XOBIAS__WRITE(src) ((uint32_t)(src) & 0x0000000fU) +#define PSEQ_XTAL_BITS1__XOBIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define PSEQ_XTAL_BITS1__XOBIAS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define PSEQ_XTAL_BITS1__XOBIAS__RESET_VALUE 0x0000000cU +/** @} */ + +/* macros for field xoagc_en */ +/** + * @defgroup at_apb_pseq_paris_regs_core_xoagc_en_field xoagc_en_field + * @brief macros for field xoagc_en + * @details Enable AGC for 16MHz xtal + * @{ + */ +#define PSEQ_XTAL_BITS1__XOAGC_EN__SHIFT 4 +#define PSEQ_XTAL_BITS1__XOAGC_EN__WIDTH 1 +#define PSEQ_XTAL_BITS1__XOAGC_EN__MASK 0x00000010U +#define PSEQ_XTAL_BITS1__XOAGC_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PSEQ_XTAL_BITS1__XOAGC_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PSEQ_XTAL_BITS1__XOAGC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PSEQ_XTAL_BITS1__XOAGC_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PSEQ_XTAL_BITS1__XOAGC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PSEQ_XTAL_BITS1__XOAGC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PSEQ_XTAL_BITS1__XOAGC_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field xofaststart */ +/** + * @defgroup at_apb_pseq_paris_regs_core_xofaststart_field xofaststart_field + * @brief macros for field xofaststart + * @details Speed up crystal settling, 7 - max + * @{ + */ +#define PSEQ_XTAL_BITS1__XOFASTSTART__SHIFT 5 +#define PSEQ_XTAL_BITS1__XOFASTSTART__WIDTH 3 +#define PSEQ_XTAL_BITS1__XOFASTSTART__MASK 0x000000e0U +#define PSEQ_XTAL_BITS1__XOFASTSTART__READ(src) \ + (((uint32_t)(src)\ + & 0x000000e0U) >> 5) +#define PSEQ_XTAL_BITS1__XOFASTSTART__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x000000e0U) +#define PSEQ_XTAL_BITS1__XOFASTSTART__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((uint32_t)(src) <<\ + 5) & 0x000000e0U) +#define PSEQ_XTAL_BITS1__XOFASTSTART__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000000e0U))) +#define PSEQ_XTAL_BITS1__XOFASTSTART__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field xosettle */ +/** + * @defgroup at_apb_pseq_paris_regs_core_xosettle_field xosettle_field + * @brief macros for field xosettle + * @details 16MHz xtal settling time after which clock source is switched to xtal, in 64us steps, min valid setting is 1, do not set to 0 + * @{ + */ +#define PSEQ_XTAL_BITS1__XOSETTLE__SHIFT 8 +#define PSEQ_XTAL_BITS1__XOSETTLE__WIDTH 6 +#define PSEQ_XTAL_BITS1__XOSETTLE__MASK 0x00003f00U +#define PSEQ_XTAL_BITS1__XOSETTLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00003f00U) >> 8) +#define PSEQ_XTAL_BITS1__XOSETTLE__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00003f00U) +#define PSEQ_XTAL_BITS1__XOSETTLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((uint32_t)(src) <<\ + 8) & 0x00003f00U) +#define PSEQ_XTAL_BITS1__XOSETTLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00003f00U))) +#define PSEQ_XTAL_BITS1__XOSETTLE__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field rcoscfreq */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rcoscfreq_field rcoscfreq_field + * @brief macros for field rcoscfreq + * @details 16MHz RC oscillator frequency tuning, 0 - slowest, 15 - fastest + * @{ + */ +#define PSEQ_XTAL_BITS1__RCOSCFREQ__SHIFT 14 +#define PSEQ_XTAL_BITS1__RCOSCFREQ__WIDTH 4 +#define PSEQ_XTAL_BITS1__RCOSCFREQ__MASK 0x0003c000U +#define PSEQ_XTAL_BITS1__RCOSCFREQ__READ(src) \ + (((uint32_t)(src)\ + & 0x0003c000U) >> 14) +#define PSEQ_XTAL_BITS1__RCOSCFREQ__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0003c000U) +#define PSEQ_XTAL_BITS1__RCOSCFREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003c000U) | (((uint32_t)(src) <<\ + 14) & 0x0003c000U) +#define PSEQ_XTAL_BITS1__RCOSCFREQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0003c000U))) +#define PSEQ_XTAL_BITS1__RCOSCFREQ__RESET_VALUE 0x00000009U +/** @} */ + +/* macros for field doublerdcc_en */ +/** + * @defgroup at_apb_pseq_paris_regs_core_doublerdcc_en_field doublerdcc_en_field + * @brief macros for field doublerdcc_en + * @details enable duty cycle correction for clock doubler + * @{ + */ +#define PSEQ_XTAL_BITS1__DOUBLERDCC_EN__SHIFT 18 +#define PSEQ_XTAL_BITS1__DOUBLERDCC_EN__WIDTH 1 +#define PSEQ_XTAL_BITS1__DOUBLERDCC_EN__MASK 0x00040000U +#define PSEQ_XTAL_BITS1__DOUBLERDCC_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define PSEQ_XTAL_BITS1__DOUBLERDCC_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define PSEQ_XTAL_BITS1__DOUBLERDCC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define PSEQ_XTAL_BITS1__DOUBLERDCC_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define PSEQ_XTAL_BITS1__DOUBLERDCC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define PSEQ_XTAL_BITS1__DOUBLERDCC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define PSEQ_XTAL_BITS1__DOUBLERDCC_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clkhpc_en */ +/** + * @defgroup at_apb_pseq_paris_regs_core_clkhpc_en_field clkhpc_en_field + * @brief macros for field clkhpc_en + * @details enable root clk_hpc buffer + * @{ + */ +#define PSEQ_XTAL_BITS1__CLKHPC_EN__SHIFT 19 +#define PSEQ_XTAL_BITS1__CLKHPC_EN__WIDTH 1 +#define PSEQ_XTAL_BITS1__CLKHPC_EN__MASK 0x00080000U +#define PSEQ_XTAL_BITS1__CLKHPC_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define PSEQ_XTAL_BITS1__CLKHPC_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define PSEQ_XTAL_BITS1__CLKHPC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define PSEQ_XTAL_BITS1__CLKHPC_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define PSEQ_XTAL_BITS1__CLKHPC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define PSEQ_XTAL_BITS1__CLKHPC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define PSEQ_XTAL_BITS1__CLKHPC_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clkmpc_en */ +/** + * @defgroup at_apb_pseq_paris_regs_core_clkmpc_en_field clkmpc_en_field + * @brief macros for field clkmpc_en + * @details enable root clk_mpc buffer; chip will not be operational if cleared + * @{ + */ +#define PSEQ_XTAL_BITS1__CLKMPC_EN__SHIFT 20 +#define PSEQ_XTAL_BITS1__CLKMPC_EN__WIDTH 1 +#define PSEQ_XTAL_BITS1__CLKMPC_EN__MASK 0x00100000U +#define PSEQ_XTAL_BITS1__CLKMPC_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define PSEQ_XTAL_BITS1__CLKMPC_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define PSEQ_XTAL_BITS1__CLKMPC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define PSEQ_XTAL_BITS1__CLKMPC_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define PSEQ_XTAL_BITS1__CLKMPC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define PSEQ_XTAL_BITS1__CLKMPC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define PSEQ_XTAL_BITS1__CLKMPC_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field extclk */ +/** + * @defgroup at_apb_pseq_paris_regs_core_extclk_field extclk_field + * @brief macros for field extclk + * @details Set to 1 if supplying external clock source on XTALI_16M pin + * @{ + */ +#define PSEQ_XTAL_BITS1__EXTCLK__SHIFT 21 +#define PSEQ_XTAL_BITS1__EXTCLK__WIDTH 1 +#define PSEQ_XTAL_BITS1__EXTCLK__MASK 0x00200000U +#define PSEQ_XTAL_BITS1__EXTCLK__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define PSEQ_XTAL_BITS1__EXTCLK__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define PSEQ_XTAL_BITS1__EXTCLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define PSEQ_XTAL_BITS1__EXTCLK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define PSEQ_XTAL_BITS1__EXTCLK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define PSEQ_XTAL_BITS1__EXTCLK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define PSEQ_XTAL_BITS1__EXTCLK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field xtal_spare */ +/** + * @defgroup at_apb_pseq_paris_regs_core_xtal_spare_field xtal_spare_field + * @brief macros for field xtal_spare + * @details unused spare bits + * @{ + */ +#define PSEQ_XTAL_BITS1__XTAL_SPARE__SHIFT 22 +#define PSEQ_XTAL_BITS1__XTAL_SPARE__WIDTH 6 +#define PSEQ_XTAL_BITS1__XTAL_SPARE__MASK 0x0fc00000U +#define PSEQ_XTAL_BITS1__XTAL_SPARE__READ(src) \ + (((uint32_t)(src)\ + & 0x0fc00000U) >> 22) +#define PSEQ_XTAL_BITS1__XTAL_SPARE__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x0fc00000U) +#define PSEQ_XTAL_BITS1__XTAL_SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fc00000U) | (((uint32_t)(src) <<\ + 22) & 0x0fc00000U) +#define PSEQ_XTAL_BITS1__XTAL_SPARE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x0fc00000U))) +#define PSEQ_XTAL_BITS1__XTAL_SPARE__RESET_VALUE 0x00000038U +/** @} */ +#define PSEQ_XTAL_BITS1__TYPE uint32_t +#define PSEQ_XTAL_BITS1__READ 0x0fffffffU +#define PSEQ_XTAL_BITS1__WRITE 0x0fffffffU +#define PSEQ_XTAL_BITS1__PRESERVED 0x00000000U +#define PSEQ_XTAL_BITS1__RESET_VALUE 0x0e1650fcU + +#endif /* __PSEQ_XTAL_BITS1_MACRO__ */ + +/** @} end of xtal_bits1 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_overrides */ +/** + * @defgroup at_apb_pseq_paris_regs_core_overrides overrides + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_OVERRIDES_MACRO__ +#define __PSEQ_OVERRIDES_MACRO__ + +/* macros for field force_precision_req */ +/** + * @defgroup at_apb_pseq_paris_regs_core_force_precision_req_field force_precision_req_field + * @brief macros for field force_precision_req + * @details force the type of precision when clk_mpc is requested + * @{ + */ +#define PSEQ_OVERRIDES__FORCE_PRECISION_REQ__SHIFT 0 +#define PSEQ_OVERRIDES__FORCE_PRECISION_REQ__WIDTH 1 +#define PSEQ_OVERRIDES__FORCE_PRECISION_REQ__MASK 0x00000001U +#define PSEQ_OVERRIDES__FORCE_PRECISION_REQ__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_OVERRIDES__FORCE_PRECISION_REQ__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_OVERRIDES__FORCE_PRECISION_REQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_OVERRIDES__FORCE_PRECISION_REQ__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_OVERRIDES__FORCE_PRECISION_REQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_OVERRIDES__FORCE_PRECISION_REQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_OVERRIDES__FORCE_PRECISION_REQ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field force_precision_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_force_precision_val_field force_precision_val_field + * @brief macros for field force_precision_val + * @details when type of precision for clk_mpc is forced, what should it be? 1=high/xtal 0=low/osc + * @{ + */ +#define PSEQ_OVERRIDES__FORCE_PRECISION_VAL__SHIFT 1 +#define PSEQ_OVERRIDES__FORCE_PRECISION_VAL__WIDTH 1 +#define PSEQ_OVERRIDES__FORCE_PRECISION_VAL__MASK 0x00000002U +#define PSEQ_OVERRIDES__FORCE_PRECISION_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_OVERRIDES__FORCE_PRECISION_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PSEQ_OVERRIDES__FORCE_PRECISION_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PSEQ_OVERRIDES__FORCE_PRECISION_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PSEQ_OVERRIDES__FORCE_PRECISION_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_OVERRIDES__FORCE_PRECISION_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_OVERRIDES__FORCE_PRECISION_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field force_osc_on_req */ +/** + * @defgroup at_apb_pseq_paris_regs_core_force_osc_on_req_field force_osc_on_req_field + * @brief macros for field force_osc_on_req + * @details force that clk_mpc oscillator request always be on + * @{ + */ +#define PSEQ_OVERRIDES__FORCE_OSC_ON_REQ__SHIFT 2 +#define PSEQ_OVERRIDES__FORCE_OSC_ON_REQ__WIDTH 1 +#define PSEQ_OVERRIDES__FORCE_OSC_ON_REQ__MASK 0x00000004U +#define PSEQ_OVERRIDES__FORCE_OSC_ON_REQ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PSEQ_OVERRIDES__FORCE_OSC_ON_REQ__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PSEQ_OVERRIDES__FORCE_OSC_ON_REQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PSEQ_OVERRIDES__FORCE_OSC_ON_REQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PSEQ_OVERRIDES__FORCE_OSC_ON_REQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PSEQ_OVERRIDES__FORCE_OSC_ON_REQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PSEQ_OVERRIDES__FORCE_OSC_ON_REQ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field block_ble_osc_on_req */ +/** + * @defgroup at_apb_pseq_paris_regs_core_block_ble_osc_on_req_field block_ble_osc_on_req_field + * @brief macros for field block_ble_osc_on_req + * @details if set, ble core cannot request clk_mpc oscillator to be enabled, mostly for debug and testing + * @{ + */ +#define PSEQ_OVERRIDES__BLOCK_BLE_OSC_ON_REQ__SHIFT 3 +#define PSEQ_OVERRIDES__BLOCK_BLE_OSC_ON_REQ__WIDTH 1 +#define PSEQ_OVERRIDES__BLOCK_BLE_OSC_ON_REQ__MASK 0x00000008U +#define PSEQ_OVERRIDES__BLOCK_BLE_OSC_ON_REQ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PSEQ_OVERRIDES__BLOCK_BLE_OSC_ON_REQ__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PSEQ_OVERRIDES__BLOCK_BLE_OSC_ON_REQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PSEQ_OVERRIDES__BLOCK_BLE_OSC_ON_REQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PSEQ_OVERRIDES__BLOCK_BLE_OSC_ON_REQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PSEQ_OVERRIDES__BLOCK_BLE_OSC_ON_REQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PSEQ_OVERRIDES__BLOCK_BLE_OSC_ON_REQ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field block_ble_high_precision_req */ +/** + * @defgroup at_apb_pseq_paris_regs_core_block_ble_high_precision_req_field block_ble_high_precision_req_field + * @brief macros for field block_ble_high_precision_req + * @details if set, ble core cannot request high precision clock, mostly for debug and testing + * @{ + */ +#define PSEQ_OVERRIDES__BLOCK_BLE_HIGH_PRECISION_REQ__SHIFT 4 +#define PSEQ_OVERRIDES__BLOCK_BLE_HIGH_PRECISION_REQ__WIDTH 1 +#define PSEQ_OVERRIDES__BLOCK_BLE_HIGH_PRECISION_REQ__MASK 0x00000010U +#define PSEQ_OVERRIDES__BLOCK_BLE_HIGH_PRECISION_REQ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PSEQ_OVERRIDES__BLOCK_BLE_HIGH_PRECISION_REQ__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PSEQ_OVERRIDES__BLOCK_BLE_HIGH_PRECISION_REQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PSEQ_OVERRIDES__BLOCK_BLE_HIGH_PRECISION_REQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PSEQ_OVERRIDES__BLOCK_BLE_HIGH_PRECISION_REQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PSEQ_OVERRIDES__BLOCK_BLE_HIGH_PRECISION_REQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PSEQ_OVERRIDES__BLOCK_BLE_HIGH_PRECISION_REQ__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_OVERRIDES__TYPE uint32_t +#define PSEQ_OVERRIDES__READ 0x0000001fU +#define PSEQ_OVERRIDES__WRITE 0x0000001fU +#define PSEQ_OVERRIDES__PRESERVED 0x00000000U +#define PSEQ_OVERRIDES__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_OVERRIDES_MACRO__ */ + +/** @} end of overrides */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_overrides2 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_overrides2 overrides2 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_OVERRIDES2_MACRO__ +#define __PSEQ_OVERRIDES2_MACRO__ + +/* macros for field block_sysrom_vddcut */ +/** + * @defgroup at_apb_pseq_paris_regs_core_block_sysrom_vddcut_field block_sysrom_vddcut_field + * @brief macros for field block_sysrom_vddcut + * @details if set, this core's FSM cannot power down the ROM macros + * @{ + */ +#define PSEQ_OVERRIDES2__BLOCK_SYSROM_VDDCUT__SHIFT 0 +#define PSEQ_OVERRIDES2__BLOCK_SYSROM_VDDCUT__WIDTH 1 +#define PSEQ_OVERRIDES2__BLOCK_SYSROM_VDDCUT__MASK 0x00000001U +#define PSEQ_OVERRIDES2__BLOCK_SYSROM_VDDCUT__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_OVERRIDES2__BLOCK_SYSROM_VDDCUT__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_OVERRIDES2__BLOCK_SYSROM_VDDCUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_OVERRIDES2__BLOCK_SYSROM_VDDCUT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_OVERRIDES2__BLOCK_SYSROM_VDDCUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_OVERRIDES2__BLOCK_SYSROM_VDDCUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_OVERRIDES2__BLOCK_SYSROM_VDDCUT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field block_rram_vddcut */ +/** + * @defgroup at_apb_pseq_paris_regs_core_block_rram_vddcut_field block_rram_vddcut_field + * @brief macros for field block_rram_vddcut + * @details if set, this core's FSM cannot power down the rram macros + * @{ + */ +#define PSEQ_OVERRIDES2__BLOCK_RRAM_VDDCUT__SHIFT 1 +#define PSEQ_OVERRIDES2__BLOCK_RRAM_VDDCUT__WIDTH 1 +#define PSEQ_OVERRIDES2__BLOCK_RRAM_VDDCUT__MASK 0x00000002U +#define PSEQ_OVERRIDES2__BLOCK_RRAM_VDDCUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_OVERRIDES2__BLOCK_RRAM_VDDCUT__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PSEQ_OVERRIDES2__BLOCK_RRAM_VDDCUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PSEQ_OVERRIDES2__BLOCK_RRAM_VDDCUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PSEQ_OVERRIDES2__BLOCK_RRAM_VDDCUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_OVERRIDES2__BLOCK_RRAM_VDDCUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_OVERRIDES2__BLOCK_RRAM_VDDCUT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field block_efuse_vddcut */ +/** + * @defgroup at_apb_pseq_paris_regs_core_block_efuse_vddcut_field block_efuse_vddcut_field + * @brief macros for field block_efuse_vddcut + * @details if set, this core's FSM cannot power down the e-fuse macros + * @{ + */ +#define PSEQ_OVERRIDES2__BLOCK_EFUSE_VDDCUT__SHIFT 2 +#define PSEQ_OVERRIDES2__BLOCK_EFUSE_VDDCUT__WIDTH 1 +#define PSEQ_OVERRIDES2__BLOCK_EFUSE_VDDCUT__MASK 0x00000004U +#define PSEQ_OVERRIDES2__BLOCK_EFUSE_VDDCUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PSEQ_OVERRIDES2__BLOCK_EFUSE_VDDCUT__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PSEQ_OVERRIDES2__BLOCK_EFUSE_VDDCUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PSEQ_OVERRIDES2__BLOCK_EFUSE_VDDCUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PSEQ_OVERRIDES2__BLOCK_EFUSE_VDDCUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PSEQ_OVERRIDES2__BLOCK_EFUSE_VDDCUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PSEQ_OVERRIDES2__BLOCK_EFUSE_VDDCUT__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_OVERRIDES2__TYPE uint32_t +#define PSEQ_OVERRIDES2__READ 0x00000007U +#define PSEQ_OVERRIDES2__WRITE 0x00000007U +#define PSEQ_OVERRIDES2__PRESERVED 0x00000000U +#define PSEQ_OVERRIDES2__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_OVERRIDES2_MACRO__ */ + +/** @} end of overrides2 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_overrides3 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_overrides3 overrides3 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_OVERRIDES3_MACRO__ +#define __PSEQ_OVERRIDES3_MACRO__ + +/* macros for field override_sysrom_clken_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_sysrom_clken_val_field override_sysrom_clken_val_field + * @brief macros for field override_sysrom_clken_val + * @details if override is set, what value should be driven onto rom clock enable pin? + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_CLKEN_VAL__SHIFT 0 +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_CLKEN_VAL__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_CLKEN_VAL__MASK 0x00000001U +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_CLKEN_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_CLKEN_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_CLKEN_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_CLKEN_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_CLKEN_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_CLKEN_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_CLKEN_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_sysrom_clken */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_sysrom_clken_field override_sysrom_clken_field + * @brief macros for field override_sysrom_clken + * @details if set, software now has direct control of the rom clock enable pin + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_CLKEN__SHIFT 1 +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_CLKEN__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_CLKEN__MASK 0x00000002U +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_CLKEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_CLKEN__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_CLKEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_CLKEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_CLKEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_CLKEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_CLKEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_sysrom_iso_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_sysrom_iso_val_field override_sysrom_iso_val_field + * @brief macros for field override_sysrom_iso_val + * @details if override is set, what value should be driven onto rom ISO pin? + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_ISO_VAL__SHIFT 2 +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_ISO_VAL__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_ISO_VAL__MASK 0x00000004U +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_ISO_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_ISO_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_ISO_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_ISO_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_ISO_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_ISO_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_ISO_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_sysrom_iso */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_sysrom_iso_field override_sysrom_iso_field + * @brief macros for field override_sysrom_iso + * @details if set, software now has direct control of the rom ISO pin + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_ISO__SHIFT 3 +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_ISO__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_ISO__MASK 0x00000008U +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_ISO__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_ISO__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_ISO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_ISO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_ISO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_ISO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_ISO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_sysrom_ls_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_sysrom_ls_val_field override_sysrom_ls_val_field + * @brief macros for field override_sysrom_ls_val + * @details if override is set, what value should be driven onto rom LS pin? + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_LS_VAL__SHIFT 4 +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_LS_VAL__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_LS_VAL__MASK 0x00000010U +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_LS_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_LS_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_LS_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_LS_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_LS_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_LS_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_LS_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_sysrom_ls */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_sysrom_ls_field override_sysrom_ls_field + * @brief macros for field override_sysrom_ls + * @details if set, software now has direct control of the rom LS pin + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_LS__SHIFT 5 +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_LS__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_LS__MASK 0x00000020U +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_LS__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_LS__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_LS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_LS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_LS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_LS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PSEQ_OVERRIDES3__OVERRIDE_SYSROM_LS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_rram_clken_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rram_clken_val_field override_rram_clken_val_field + * @brief macros for field override_rram_clken_val + * @details if override is set, what value should be driven onto rram clock enable pin? + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_CLKEN_VAL__SHIFT 6 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_CLKEN_VAL__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_CLKEN_VAL__MASK 0x00000040U +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_CLKEN_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_CLKEN_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_CLKEN_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_CLKEN_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_CLKEN_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_CLKEN_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_CLKEN_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_rram_clken */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rram_clken_field override_rram_clken_field + * @brief macros for field override_rram_clken + * @details if set, software now has direct control of the rram clock enable pin + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_CLKEN__SHIFT 7 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_CLKEN__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_CLKEN__MASK 0x00000080U +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_CLKEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_CLKEN__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_CLKEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_CLKEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_CLKEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_CLKEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_CLKEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_rram_iso_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rram_iso_val_field override_rram_iso_val_field + * @brief macros for field override_rram_iso_val + * @details if override is set, what value should be driven onto rram ISO pin? + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_ISO_VAL__SHIFT 8 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_ISO_VAL__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_ISO_VAL__MASK 0x00000100U +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_ISO_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_ISO_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_ISO_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_ISO_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_ISO_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_ISO_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_ISO_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_rram_iso */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rram_iso_field override_rram_iso_field + * @brief macros for field override_rram_iso + * @details if set, software now has direct control of the rram ISO pin + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_ISO__SHIFT 9 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_ISO__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_ISO__MASK 0x00000200U +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_ISO__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_ISO__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_ISO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_ISO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_ISO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_ISO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_ISO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_rram_nap_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rram_nap_val_field override_rram_nap_val_field + * @brief macros for field override_rram_nap_val + * @details if override is set, what value should be driven onto rram NAP pin? + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_NAP_VAL__SHIFT 10 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_NAP_VAL__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_NAP_VAL__MASK 0x00000400U +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_NAP_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_NAP_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_NAP_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_NAP_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_NAP_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_NAP_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_NAP_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_rram_nap */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rram_nap_field override_rram_nap_field + * @brief macros for field override_rram_nap + * @details if set, software now has direct control of the rram NAP pin + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_NAP__SHIFT 11 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_NAP__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_NAP__MASK 0x00000800U +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_NAP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_NAP__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_NAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_NAP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_NAP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_NAP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_NAP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_rram_poc_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rram_poc_val_field override_rram_poc_val_field + * @brief macros for field override_rram_poc_val + * @details if override is set, what value should be driven onto rram POC_H pin? + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC_VAL__SHIFT 12 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC_VAL__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC_VAL__MASK 0x00001000U +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_rram_poc */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rram_poc_field override_rram_poc_field + * @brief macros for field override_rram_poc + * @details if set, software now has direct control of the rram POC_H pin + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC__SHIFT 13 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC__MASK 0x00002000U +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_rram_rst_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rram_rst_val_field override_rram_rst_val_field + * @brief macros for field override_rram_rst_val + * @details if override is set, what value should be driven onto rram RST pin? + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_RST_VAL__SHIFT 14 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_RST_VAL__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_RST_VAL__MASK 0x00004000U +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_RST_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_RST_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_RST_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_RST_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_RST_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_RST_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_RST_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_rram_rst */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rram_rst_field override_rram_rst_field + * @brief macros for field override_rram_rst + * @details if set, software now has direct control of the rram RST pin + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_RST__SHIFT 15 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_RST__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_RST__MASK 0x00008000U +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_RST__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_RST__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_RST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_RST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_RST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_RST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_RST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_rram_vddcut_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rram_vddcut_val_field override_rram_vddcut_val_field + * @brief macros for field override_rram_vddcut_val + * @details if override is set, should head switch on romc be open or close? 1=open 0=close + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_VDDCUT_VAL__SHIFT 16 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_VDDCUT_VAL__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_VDDCUT_VAL__MASK 0x00010000U +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_VDDCUT_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_VDDCUT_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_VDDCUT_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_VDDCUT_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_VDDCUT_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_VDDCUT_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_VDDCUT_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_rram_vddcut */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rram_vddcut_field override_rram_vddcut_field + * @brief macros for field override_rram_vddcut + * @details if set, head switch on romc (rom,rram) is now software controllable + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_VDDCUT__SHIFT 17 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_VDDCUT__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_VDDCUT__MASK 0x00020000U +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_VDDCUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_VDDCUT__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_VDDCUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_VDDCUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_VDDCUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_VDDCUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define PSEQ_OVERRIDES3__OVERRIDE_RRAM_VDDCUT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_efuse_iso_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_efuse_iso_val_field override_efuse_iso_val_field + * @brief macros for field override_efuse_iso_val + * @details if override is set, what value should be driven onto e-fuse ISO pin? + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_ISO_VAL__SHIFT 18 +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_ISO_VAL__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_ISO_VAL__MASK 0x00040000U +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_ISO_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_ISO_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_ISO_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_ISO_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_ISO_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_ISO_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_ISO_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_efuse_iso */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_efuse_iso_field override_efuse_iso_field + * @brief macros for field override_efuse_iso + * @details if set, software now has direct control of the e-fuse ISO pin + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_ISO__SHIFT 19 +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_ISO__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_ISO__MASK 0x00080000U +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_ISO__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_ISO__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_ISO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_ISO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_ISO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_ISO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_ISO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_efuse_vddcut_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_efuse_vddcut_val_field override_efuse_vddcut_val_field + * @brief macros for field override_efuse_vddcut_val + * @details if override is set, should head switch on e-fuse be open or close? 1=open 0=close + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_VDDCUT_VAL__SHIFT 20 +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_VDDCUT_VAL__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_VDDCUT_VAL__MASK 0x00100000U +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_VDDCUT_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_VDDCUT_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_VDDCUT_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_VDDCUT_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_VDDCUT_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_VDDCUT_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_VDDCUT_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_efuse_vddcut */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_efuse_vddcut_field override_efuse_vddcut_field + * @brief macros for field override_efuse_vddcut + * @details if set, head switch on e-fuse is now software controllable + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_VDDCUT__SHIFT 21 +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_VDDCUT__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_VDDCUT__MASK 0x00200000U +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_VDDCUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_VDDCUT__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_VDDCUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_VDDCUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_VDDCUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_VDDCUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define PSEQ_OVERRIDES3__OVERRIDE_EFUSE_VDDCUT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_ram_iso_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_ram_iso_val_field override_ram_iso_val_field + * @brief macros for field override_ram_iso_val + * @details if override is set, what value should be driven onto pd_mem ISO pins? + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_RAM_ISO_VAL__SHIFT 22 +#define PSEQ_OVERRIDES3__OVERRIDE_RAM_ISO_VAL__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_RAM_ISO_VAL__MASK 0x00400000U +#define PSEQ_OVERRIDES3__OVERRIDE_RAM_ISO_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define PSEQ_OVERRIDES3__OVERRIDE_RAM_ISO_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define PSEQ_OVERRIDES3__OVERRIDE_RAM_ISO_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define PSEQ_OVERRIDES3__OVERRIDE_RAM_ISO_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define PSEQ_OVERRIDES3__OVERRIDE_RAM_ISO_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define PSEQ_OVERRIDES3__OVERRIDE_RAM_ISO_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define PSEQ_OVERRIDES3__OVERRIDE_RAM_ISO_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_ram_iso */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_ram_iso_field override_ram_iso_field + * @brief macros for field override_ram_iso + * @details if set, software now has direct control of the pd_mem ISO pins + * @{ + */ +#define PSEQ_OVERRIDES3__OVERRIDE_RAM_ISO__SHIFT 23 +#define PSEQ_OVERRIDES3__OVERRIDE_RAM_ISO__WIDTH 1 +#define PSEQ_OVERRIDES3__OVERRIDE_RAM_ISO__MASK 0x00800000U +#define PSEQ_OVERRIDES3__OVERRIDE_RAM_ISO__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PSEQ_OVERRIDES3__OVERRIDE_RAM_ISO__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define PSEQ_OVERRIDES3__OVERRIDE_RAM_ISO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define PSEQ_OVERRIDES3__OVERRIDE_RAM_ISO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define PSEQ_OVERRIDES3__OVERRIDE_RAM_ISO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PSEQ_OVERRIDES3__OVERRIDE_RAM_ISO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PSEQ_OVERRIDES3__OVERRIDE_RAM_ISO__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_OVERRIDES3__TYPE uint32_t +#define PSEQ_OVERRIDES3__READ 0x00ffffffU +#define PSEQ_OVERRIDES3__WRITE 0x00ffffffU +#define PSEQ_OVERRIDES3__PRESERVED 0x00000000U +#define PSEQ_OVERRIDES3__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_OVERRIDES3_MACRO__ */ + +/** @} end of overrides3 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_overrides4 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_overrides4 overrides4 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_OVERRIDES4_MACRO__ +#define __PSEQ_OVERRIDES4_MACRO__ + +/* macros for field override_ble_clken_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_ble_clken_val_field override_ble_clken_val_field + * @brief macros for field override_ble_clken_val + * @details if override is set, what value should be driven onto the ble domain's clock enable signal? + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_CLKEN_VAL__SHIFT 0 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_CLKEN_VAL__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_CLKEN_VAL__MASK 0x00000001U +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_CLKEN_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_CLKEN_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_CLKEN_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_CLKEN_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_CLKEN_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_CLKEN_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_CLKEN_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_ble_clken */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_ble_clken_field override_ble_clken_field + * @brief macros for field override_ble_clken + * @details if set, software now has direct control of the clock enable signal going to the ble domain + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_CLKEN__SHIFT 1 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_CLKEN__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_CLKEN__MASK 0x00000002U +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_CLKEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_CLKEN__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_CLKEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_CLKEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_CLKEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_CLKEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_CLKEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_ble_frst_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_ble_frst_val_field override_ble_frst_val_field + * @brief macros for field override_ble_frst_val + * @details if override is set, what value should be driven onto the ble domain's forced reset signal? + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_FRST_VAL__SHIFT 2 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_FRST_VAL__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_FRST_VAL__MASK 0x00000004U +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_FRST_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_FRST_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_FRST_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_FRST_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_FRST_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_FRST_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_FRST_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_ble_frst */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_ble_frst_field override_ble_frst_field + * @brief macros for field override_ble_frst + * @details if set, software now has direct control of the forced reset signal going to the ble domain + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_FRST__SHIFT 3 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_FRST__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_FRST__MASK 0x00000008U +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_FRST__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_FRST__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_FRST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_FRST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_FRST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_FRST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_FRST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_ble_iso_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_ble_iso_val_field override_ble_iso_val_field + * @brief macros for field override_ble_iso_val + * @details if override is set, what value should be driven onto the ble domain's iso signal? + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_ISO_VAL__SHIFT 4 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_ISO_VAL__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_ISO_VAL__MASK 0x00000010U +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_ISO_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_ISO_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_ISO_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_ISO_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_ISO_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_ISO_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_ISO_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_ble_iso */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_ble_iso_field override_ble_iso_field + * @brief macros for field override_ble_iso + * @details if set, software now has direct control of the iso signal going to the ble domain + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_ISO__SHIFT 5 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_ISO__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_ISO__MASK 0x00000020U +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_ISO__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_ISO__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_ISO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_ISO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_ISO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_ISO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_ISO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_ble_kill_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_ble_kill_val_field override_ble_kill_val_field + * @brief macros for field override_ble_kill_val + * @details if override is set, what value should be driven onto the ble domain's kill signal? + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_KILL_VAL__SHIFT 6 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_KILL_VAL__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_KILL_VAL__MASK 0x00000040U +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_KILL_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_KILL_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_KILL_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_KILL_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_KILL_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_KILL_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_KILL_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_ble_kill */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_ble_kill_field override_ble_kill_field + * @brief macros for field override_ble_kill + * @details if set, software now has direct control of the kill signal going to the ble domain + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_KILL__SHIFT 7 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_KILL__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_KILL__MASK 0x00000080U +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_KILL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_KILL__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_KILL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_KILL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_KILL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_KILL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_KILL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_ble_sleep_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_ble_sleep_val_field override_ble_sleep_val_field + * @brief macros for field override_ble_sleep_val + * @details if override is set, what value should be driven onto the ble domain's sleep signal? + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SLEEP_VAL__SHIFT 8 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SLEEP_VAL__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SLEEP_VAL__MASK 0x00000100U +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SLEEP_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SLEEP_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SLEEP_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SLEEP_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SLEEP_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SLEEP_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SLEEP_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_ble_sleep */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_ble_sleep_field override_ble_sleep_field + * @brief macros for field override_ble_sleep + * @details if set, software now has direct control of the sleep signal going to the ble domain + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SLEEP__SHIFT 9 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SLEEP__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SLEEP__MASK 0x00000200U +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SLEEP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SLEEP__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SLEEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SLEEP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SLEEP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SLEEP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SLEEP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_ble_nrestore_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_ble_nrestore_val_field override_ble_nrestore_val_field + * @brief macros for field override_ble_nrestore_val + * @details if override is set, what value should be driven onto the ble domain's NRESTORE signal? + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_NRESTORE_VAL__SHIFT 10 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_NRESTORE_VAL__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_NRESTORE_VAL__MASK 0x00000400U +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_NRESTORE_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_NRESTORE_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_NRESTORE_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_NRESTORE_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_NRESTORE_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_NRESTORE_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_NRESTORE_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_ble_nrestore */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_ble_nrestore_field override_ble_nrestore_field + * @brief macros for field override_ble_nrestore + * @details if set, software now has direct control of the NRESTORE signal going to the ble domain + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_NRESTORE__SHIFT 11 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_NRESTORE__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_NRESTORE__MASK 0x00000800U +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_NRESTORE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_NRESTORE__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_NRESTORE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_NRESTORE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_NRESTORE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_NRESTORE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_NRESTORE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_ble_save_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_ble_save_val_field override_ble_save_val_field + * @brief macros for field override_ble_save_val + * @details if override is set, what value should be driven onto the ble domain's SAVE signal? + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SAVE_VAL__SHIFT 12 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SAVE_VAL__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SAVE_VAL__MASK 0x00001000U +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SAVE_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SAVE_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SAVE_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SAVE_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SAVE_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SAVE_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SAVE_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_ble_save */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_ble_save_field override_ble_save_field + * @brief macros for field override_ble_save + * @details if set, software now has direct control of the SAVE signal going to the ble domain + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SAVE__SHIFT 13 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SAVE__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SAVE__MASK 0x00002000U +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SAVE__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SAVE__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SAVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SAVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SAVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SAVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define PSEQ_OVERRIDES4__OVERRIDE_BLE_SAVE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_pnr_clken_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_pnr_clken_val_field override_pnr_clken_val_field + * @brief macros for field override_pnr_clken_val + * @details if override is set, what value should be driven onto the cpu domain's clock enable signal? + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_CLKEN_VAL__SHIFT 14 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_CLKEN_VAL__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_CLKEN_VAL__MASK 0x00004000U +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_CLKEN_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_CLKEN_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_CLKEN_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_CLKEN_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_CLKEN_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_CLKEN_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_CLKEN_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_pnr_clken */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_pnr_clken_field override_pnr_clken_field + * @brief macros for field override_pnr_clken + * @details if set, software now has direct control of the clock enable signal going to the cpu domain + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_CLKEN__SHIFT 15 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_CLKEN__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_CLKEN__MASK 0x00008000U +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_CLKEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_CLKEN__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_CLKEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_CLKEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_CLKEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_CLKEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_CLKEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_pnr_frst_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_pnr_frst_val_field override_pnr_frst_val_field + * @brief macros for field override_pnr_frst_val + * @details if override is set, what value should be driven onto the cpu domain's forced reset signal? + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_FRST_VAL__SHIFT 16 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_FRST_VAL__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_FRST_VAL__MASK 0x00010000U +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_FRST_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_FRST_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_FRST_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_FRST_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_FRST_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_FRST_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_FRST_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_pnr_frst */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_pnr_frst_field override_pnr_frst_field + * @brief macros for field override_pnr_frst + * @details if set, software now has direct control of the forced reset signal going to the cpu domain + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_FRST__SHIFT 17 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_FRST__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_FRST__MASK 0x00020000U +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_FRST__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_FRST__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_FRST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_FRST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_FRST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_FRST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_FRST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_pnr_iso_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_pnr_iso_val_field override_pnr_iso_val_field + * @brief macros for field override_pnr_iso_val + * @details if override is set, what value should be driven onto the cpu domain's iso signal? + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO_VAL__SHIFT 18 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO_VAL__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO_VAL__MASK 0x00040000U +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_pnr_iso */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_pnr_iso_field override_pnr_iso_field + * @brief macros for field override_pnr_iso + * @details if set, software now has direct control of the iso signal going to the cpu domain + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO__SHIFT 19 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO__MASK 0x00080000U +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_pnr_kill_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_pnr_kill_val_field override_pnr_kill_val_field + * @brief macros for field override_pnr_kill_val + * @details if override is set, what value should be driven onto the cpu domain's kill signal? + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_KILL_VAL__SHIFT 20 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_KILL_VAL__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_KILL_VAL__MASK 0x00100000U +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_KILL_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_KILL_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_KILL_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_KILL_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_KILL_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_KILL_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_KILL_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_pnr_kill */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_pnr_kill_field override_pnr_kill_field + * @brief macros for field override_pnr_kill + * @details if set, software now has direct control of the kill signal going to the cpu domain + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_KILL__SHIFT 21 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_KILL__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_KILL__MASK 0x00200000U +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_KILL__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_KILL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_KILL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_KILL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_KILL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_KILL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_KILL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_pnr_sleep_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_pnr_sleep_val_field override_pnr_sleep_val_field + * @brief macros for field override_pnr_sleep_val + * @details if override is set, what value should be driven onto the cpu domain's sleep signal? + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SLEEP_VAL__SHIFT 22 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SLEEP_VAL__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SLEEP_VAL__MASK 0x00400000U +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SLEEP_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SLEEP_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SLEEP_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SLEEP_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SLEEP_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SLEEP_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SLEEP_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_pnr_sleep */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_pnr_sleep_field override_pnr_sleep_field + * @brief macros for field override_pnr_sleep + * @details if set, software now has direct control of the sleep signal going to the cpu domain + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SLEEP__SHIFT 23 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SLEEP__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SLEEP__MASK 0x00800000U +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SLEEP__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SLEEP__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SLEEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SLEEP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SLEEP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SLEEP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SLEEP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_pnr_restore_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_pnr_restore_val_field override_pnr_restore_val_field + * @brief macros for field override_pnr_restore_val + * @details if override is set, what value should be driven onto the cpu domain's RESTORE signal? + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_RESTORE_VAL__SHIFT 24 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_RESTORE_VAL__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_RESTORE_VAL__MASK 0x01000000U +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_RESTORE_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_RESTORE_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_RESTORE_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_RESTORE_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_RESTORE_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_RESTORE_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_RESTORE_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_pnr_restore */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_pnr_restore_field override_pnr_restore_field + * @brief macros for field override_pnr_restore + * @details if set, software now has direct control of the RESTORE signal going to the cpu domain + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_RESTORE__SHIFT 25 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_RESTORE__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_RESTORE__MASK 0x02000000U +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_RESTORE__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_RESTORE__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_RESTORE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_RESTORE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_RESTORE__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_RESTORE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_RESTORE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_pnr_save_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_pnr_save_val_field override_pnr_save_val_field + * @brief macros for field override_pnr_save_val + * @details if override is set, what value should be driven onto the cpu domain's SAVE signal? + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SAVE_VAL__SHIFT 26 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SAVE_VAL__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SAVE_VAL__MASK 0x04000000U +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SAVE_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SAVE_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SAVE_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SAVE_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SAVE_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SAVE_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SAVE_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_pnr_save */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_pnr_save_field override_pnr_save_field + * @brief macros for field override_pnr_save + * @details if set, software now has direct control of the SAVE signal going to the cpu domain + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SAVE__SHIFT 27 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SAVE__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SAVE__MASK 0x08000000U +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SAVE__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SAVE__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SAVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SAVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SAVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SAVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_SAVE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_pnr_iso1_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_pnr_iso1_val_field override_pnr_iso1_val_field + * @brief macros for field override_pnr_iso1_val + * @details if override is set, what value should be driven onto the cpu domain's iso1 signal? + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO1_VAL__SHIFT 28 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO1_VAL__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO1_VAL__MASK 0x10000000U +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO1_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO1_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO1_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO1_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO1_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO1_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO1_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_pnr_iso1 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_pnr_iso1_field override_pnr_iso1_field + * @brief macros for field override_pnr_iso1 + * @details if set, software now has direct control of the iso1 signal going to the cpu domain; for scan_outs only + * @{ + */ +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO1__SHIFT 29 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO1__WIDTH 1 +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO1__MASK 0x20000000U +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO1__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO1__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO1__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define PSEQ_OVERRIDES4__OVERRIDE_PNR_ISO1__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_OVERRIDES4__TYPE uint32_t +#define PSEQ_OVERRIDES4__READ 0x3fffffffU +#define PSEQ_OVERRIDES4__WRITE 0x3fffffffU +#define PSEQ_OVERRIDES4__PRESERVED 0x00000000U +#define PSEQ_OVERRIDES4__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_OVERRIDES4_MACRO__ */ + +/** @} end of overrides4 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_overrides5 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_overrides5 overrides5 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_OVERRIDES5_MACRO__ +#define __PSEQ_OVERRIDES5_MACRO__ + +/* macros for field override_pnr_frstdp_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_pnr_frstdp_val_field override_pnr_frstdp_val_field + * @brief macros for field override_pnr_frstdp_val + * @details If override is set, what value is the cpu domain's datapath forced reset. + * @{ + */ +#define PSEQ_OVERRIDES5__OVERRIDE_PNR_FRSTDP_VAL__SHIFT 14 +#define PSEQ_OVERRIDES5__OVERRIDE_PNR_FRSTDP_VAL__WIDTH 1 +#define PSEQ_OVERRIDES5__OVERRIDE_PNR_FRSTDP_VAL__MASK 0x00004000U +#define PSEQ_OVERRIDES5__OVERRIDE_PNR_FRSTDP_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PSEQ_OVERRIDES5__OVERRIDE_PNR_FRSTDP_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define PSEQ_OVERRIDES5__OVERRIDE_PNR_FRSTDP_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define PSEQ_OVERRIDES5__OVERRIDE_PNR_FRSTDP_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define PSEQ_OVERRIDES5__OVERRIDE_PNR_FRSTDP_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PSEQ_OVERRIDES5__OVERRIDE_PNR_FRSTDP_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PSEQ_OVERRIDES5__OVERRIDE_PNR_FRSTDP_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_pnr_frstdp */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_pnr_frstdp_field override_pnr_frstdp_field + * @brief macros for field override_pnr_frstdp + * @details If set, software now has direct control of cpu domain's datapath forced reset. Not all state is retained even in Retain All state. + * @{ + */ +#define PSEQ_OVERRIDES5__OVERRIDE_PNR_FRSTDP__SHIFT 15 +#define PSEQ_OVERRIDES5__OVERRIDE_PNR_FRSTDP__WIDTH 1 +#define PSEQ_OVERRIDES5__OVERRIDE_PNR_FRSTDP__MASK 0x00008000U +#define PSEQ_OVERRIDES5__OVERRIDE_PNR_FRSTDP__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define PSEQ_OVERRIDES5__OVERRIDE_PNR_FRSTDP__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define PSEQ_OVERRIDES5__OVERRIDE_PNR_FRSTDP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define PSEQ_OVERRIDES5__OVERRIDE_PNR_FRSTDP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define PSEQ_OVERRIDES5__OVERRIDE_PNR_FRSTDP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PSEQ_OVERRIDES5__OVERRIDE_PNR_FRSTDP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PSEQ_OVERRIDES5__OVERRIDE_PNR_FRSTDP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_ble_frstdp_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_ble_frstdp_val_field override_ble_frstdp_val_field + * @brief macros for field override_ble_frstdp_val + * @details If override is set, what value is the ble domain's datapath forced reset. + * @{ + */ +#define PSEQ_OVERRIDES5__OVERRIDE_BLE_FRSTDP_VAL__SHIFT 16 +#define PSEQ_OVERRIDES5__OVERRIDE_BLE_FRSTDP_VAL__WIDTH 1 +#define PSEQ_OVERRIDES5__OVERRIDE_BLE_FRSTDP_VAL__MASK 0x00010000U +#define PSEQ_OVERRIDES5__OVERRIDE_BLE_FRSTDP_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define PSEQ_OVERRIDES5__OVERRIDE_BLE_FRSTDP_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define PSEQ_OVERRIDES5__OVERRIDE_BLE_FRSTDP_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define PSEQ_OVERRIDES5__OVERRIDE_BLE_FRSTDP_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define PSEQ_OVERRIDES5__OVERRIDE_BLE_FRSTDP_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PSEQ_OVERRIDES5__OVERRIDE_BLE_FRSTDP_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PSEQ_OVERRIDES5__OVERRIDE_BLE_FRSTDP_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_ble_frstdp */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_ble_frstdp_field override_ble_frstdp_field + * @brief macros for field override_ble_frstdp + * @details If set, software now has direct control of ble domain's datapath forced reset. Not all state is retained even in Retain All state. + * @{ + */ +#define PSEQ_OVERRIDES5__OVERRIDE_BLE_FRSTDP__SHIFT 17 +#define PSEQ_OVERRIDES5__OVERRIDE_BLE_FRSTDP__WIDTH 1 +#define PSEQ_OVERRIDES5__OVERRIDE_BLE_FRSTDP__MASK 0x00020000U +#define PSEQ_OVERRIDES5__OVERRIDE_BLE_FRSTDP__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define PSEQ_OVERRIDES5__OVERRIDE_BLE_FRSTDP__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define PSEQ_OVERRIDES5__OVERRIDE_BLE_FRSTDP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define PSEQ_OVERRIDES5__OVERRIDE_BLE_FRSTDP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define PSEQ_OVERRIDES5__OVERRIDE_BLE_FRSTDP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define PSEQ_OVERRIDES5__OVERRIDE_BLE_FRSTDP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define PSEQ_OVERRIDES5__OVERRIDE_BLE_FRSTDP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_radio_iso_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_radio_iso_val_field override_radio_iso_val_field + * @brief macros for field override_radio_iso_val + * @details If override is set, what value is the radio isolation signal? + * @{ + */ +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_ISO_VAL__SHIFT 18 +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_ISO_VAL__WIDTH 1 +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_ISO_VAL__MASK 0x00040000U +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_ISO_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_ISO_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_ISO_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_ISO_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_ISO_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_ISO_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_ISO_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_radio_iso */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_radio_iso_field override_radio_iso_field + * @brief macros for field override_radio_iso + * @details If set, software now has direct control of radio isolation signal . + * @{ + */ +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_ISO__SHIFT 19 +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_ISO__WIDTH 1 +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_ISO__MASK 0x00080000U +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_ISO__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_ISO__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_ISO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_ISO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_ISO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_ISO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_ISO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_wreq_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_wreq_val_field override_wreq_val_field + * @brief macros for field override_wreq_val + * @details If override is set, what value is value of wake up request? Useful for debug/test of pseq interrupt. 0=no wake 1=wake + * @{ + */ +#define PSEQ_OVERRIDES5__OVERRIDE_WREQ_VAL__SHIFT 20 +#define PSEQ_OVERRIDES5__OVERRIDE_WREQ_VAL__WIDTH 1 +#define PSEQ_OVERRIDES5__OVERRIDE_WREQ_VAL__MASK 0x00100000U +#define PSEQ_OVERRIDES5__OVERRIDE_WREQ_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define PSEQ_OVERRIDES5__OVERRIDE_WREQ_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define PSEQ_OVERRIDES5__OVERRIDE_WREQ_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define PSEQ_OVERRIDES5__OVERRIDE_WREQ_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define PSEQ_OVERRIDES5__OVERRIDE_WREQ_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define PSEQ_OVERRIDES5__OVERRIDE_WREQ_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define PSEQ_OVERRIDES5__OVERRIDE_WREQ_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_wreq */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_wreq_field override_wreq_field + * @brief macros for field override_wreq + * @details If set, software now has direct control of wake up request. + * @{ + */ +#define PSEQ_OVERRIDES5__OVERRIDE_WREQ__SHIFT 21 +#define PSEQ_OVERRIDES5__OVERRIDE_WREQ__WIDTH 1 +#define PSEQ_OVERRIDES5__OVERRIDE_WREQ__MASK 0x00200000U +#define PSEQ_OVERRIDES5__OVERRIDE_WREQ__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define PSEQ_OVERRIDES5__OVERRIDE_WREQ__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define PSEQ_OVERRIDES5__OVERRIDE_WREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define PSEQ_OVERRIDES5__OVERRIDE_WREQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define PSEQ_OVERRIDES5__OVERRIDE_WREQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define PSEQ_OVERRIDES5__OVERRIDE_WREQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define PSEQ_OVERRIDES5__OVERRIDE_WREQ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_radio_frst_b_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_radio_frst_b_val_field override_radio_frst_b_val_field + * @brief macros for field override_radio_frst_b_val + * @details If override is set, what value is the radio forced reset? 0=forced reset is enabled 1=forced reset is disabled + * @{ + */ +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_FRST_B_VAL__SHIFT 22 +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_FRST_B_VAL__WIDTH 1 +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_FRST_B_VAL__MASK 0x00400000U +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_FRST_B_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_FRST_B_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_FRST_B_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_FRST_B_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_FRST_B_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_FRST_B_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_FRST_B_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_radio_frst_b */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_radio_frst_b_field override_radio_frst_b_field + * @brief macros for field override_radio_frst_b + * @details If set, software now has direct control of radio forced reset . + * @{ + */ +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_FRST_B__SHIFT 23 +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_FRST_B__WIDTH 1 +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_FRST_B__MASK 0x00800000U +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_FRST_B__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_FRST_B__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_FRST_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_FRST_B__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_FRST_B__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_FRST_B__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_FRST_B__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_cutvdd_b_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_cutvdd_b_val_field override_cutvdd_b_val_field + * @brief macros for field override_cutvdd_b_val + * @details If override is set, what value is the radio enable? 0=head switches are open 1=head switches are closed + * @{ + */ +#define PSEQ_OVERRIDES5__OVERRIDE_CUTVDD_B_VAL__SHIFT 24 +#define PSEQ_OVERRIDES5__OVERRIDE_CUTVDD_B_VAL__WIDTH 1 +#define PSEQ_OVERRIDES5__OVERRIDE_CUTVDD_B_VAL__MASK 0x01000000U +#define PSEQ_OVERRIDES5__OVERRIDE_CUTVDD_B_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define PSEQ_OVERRIDES5__OVERRIDE_CUTVDD_B_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define PSEQ_OVERRIDES5__OVERRIDE_CUTVDD_B_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define PSEQ_OVERRIDES5__OVERRIDE_CUTVDD_B_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define PSEQ_OVERRIDES5__OVERRIDE_CUTVDD_B_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define PSEQ_OVERRIDES5__OVERRIDE_CUTVDD_B_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define PSEQ_OVERRIDES5__OVERRIDE_CUTVDD_B_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_cutvdd_b */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_cutvdd_b_field override_cutvdd_b_field + * @brief macros for field override_cutvdd_b + * @details If set, software now has direct control of radio head switches. + * @{ + */ +#define PSEQ_OVERRIDES5__OVERRIDE_CUTVDD_B__SHIFT 25 +#define PSEQ_OVERRIDES5__OVERRIDE_CUTVDD_B__WIDTH 1 +#define PSEQ_OVERRIDES5__OVERRIDE_CUTVDD_B__MASK 0x02000000U +#define PSEQ_OVERRIDES5__OVERRIDE_CUTVDD_B__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define PSEQ_OVERRIDES5__OVERRIDE_CUTVDD_B__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define PSEQ_OVERRIDES5__OVERRIDE_CUTVDD_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define PSEQ_OVERRIDES5__OVERRIDE_CUTVDD_B__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define PSEQ_OVERRIDES5__OVERRIDE_CUTVDD_B__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define PSEQ_OVERRIDES5__OVERRIDE_CUTVDD_B__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define PSEQ_OVERRIDES5__OVERRIDE_CUTVDD_B__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_radio_en_o_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_radio_en_o_val_field override_radio_en_o_val_field + * @brief macros for field override_radio_en_o_val + * @details If override is set, what value is the radio enable? 0=off 1=on + * @{ + */ +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_EN_O_VAL__SHIFT 26 +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_EN_O_VAL__WIDTH 1 +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_EN_O_VAL__MASK 0x04000000U +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_EN_O_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_EN_O_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_EN_O_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_EN_O_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_EN_O_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_EN_O_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_EN_O_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_radio_en_o */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_radio_en_o_field override_radio_en_o_field + * @brief macros for field override_radio_en_o + * @details If set, software now has direct control of radio enable. + * @{ + */ +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_EN_O__SHIFT 27 +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_EN_O__WIDTH 1 +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_EN_O__MASK 0x08000000U +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_EN_O__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_EN_O__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_EN_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_EN_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_EN_O__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_EN_O__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define PSEQ_OVERRIDES5__OVERRIDE_RADIO_EN_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_retv_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_retv_val_field override_retv_val_field + * @brief macros for field override_retv_val + * @details If override is set, what value is the memory retention voltage? 0=nominal 1=ultra low + * @{ + */ +#define PSEQ_OVERRIDES5__OVERRIDE_RETV_VAL__SHIFT 28 +#define PSEQ_OVERRIDES5__OVERRIDE_RETV_VAL__WIDTH 1 +#define PSEQ_OVERRIDES5__OVERRIDE_RETV_VAL__MASK 0x10000000U +#define PSEQ_OVERRIDES5__OVERRIDE_RETV_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define PSEQ_OVERRIDES5__OVERRIDE_RETV_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define PSEQ_OVERRIDES5__OVERRIDE_RETV_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define PSEQ_OVERRIDES5__OVERRIDE_RETV_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define PSEQ_OVERRIDES5__OVERRIDE_RETV_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define PSEQ_OVERRIDES5__OVERRIDE_RETV_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define PSEQ_OVERRIDES5__OVERRIDE_RETV_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_retv */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_retv_field override_retv_field + * @brief macros for field override_retv + * @details If set, software now has direct control of the memory retention voltage. + * @{ + */ +#define PSEQ_OVERRIDES5__OVERRIDE_RETV__SHIFT 29 +#define PSEQ_OVERRIDES5__OVERRIDE_RETV__WIDTH 1 +#define PSEQ_OVERRIDES5__OVERRIDE_RETV__MASK 0x20000000U +#define PSEQ_OVERRIDES5__OVERRIDE_RETV__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define PSEQ_OVERRIDES5__OVERRIDE_RETV__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define PSEQ_OVERRIDES5__OVERRIDE_RETV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define PSEQ_OVERRIDES5__OVERRIDE_RETV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define PSEQ_OVERRIDES5__OVERRIDE_RETV__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define PSEQ_OVERRIDES5__OVERRIDE_RETV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define PSEQ_OVERRIDES5__OVERRIDE_RETV__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_xtal_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_xtal_val_field override_xtal_val_field + * @brief macros for field override_xtal_val + * @details If override is set, what value is clk_mpc's cystal circuit enable? 0=off 1=on + * @{ + */ +#define PSEQ_OVERRIDES5__OVERRIDE_XTAL_VAL__SHIFT 30 +#define PSEQ_OVERRIDES5__OVERRIDE_XTAL_VAL__WIDTH 1 +#define PSEQ_OVERRIDES5__OVERRIDE_XTAL_VAL__MASK 0x40000000U +#define PSEQ_OVERRIDES5__OVERRIDE_XTAL_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define PSEQ_OVERRIDES5__OVERRIDE_XTAL_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define PSEQ_OVERRIDES5__OVERRIDE_XTAL_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define PSEQ_OVERRIDES5__OVERRIDE_XTAL_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define PSEQ_OVERRIDES5__OVERRIDE_XTAL_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define PSEQ_OVERRIDES5__OVERRIDE_XTAL_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define PSEQ_OVERRIDES5__OVERRIDE_XTAL_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_xtal */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_xtal_field override_xtal_field + * @brief macros for field override_xtal + * @details If set, software now has direct control of clk_mpc's crystal circuit enable. + * @{ + */ +#define PSEQ_OVERRIDES5__OVERRIDE_XTAL__SHIFT 31 +#define PSEQ_OVERRIDES5__OVERRIDE_XTAL__WIDTH 1 +#define PSEQ_OVERRIDES5__OVERRIDE_XTAL__MASK 0x80000000U +#define PSEQ_OVERRIDES5__OVERRIDE_XTAL__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define PSEQ_OVERRIDES5__OVERRIDE_XTAL__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define PSEQ_OVERRIDES5__OVERRIDE_XTAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define PSEQ_OVERRIDES5__OVERRIDE_XTAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define PSEQ_OVERRIDES5__OVERRIDE_XTAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PSEQ_OVERRIDES5__OVERRIDE_XTAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PSEQ_OVERRIDES5__OVERRIDE_XTAL__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_OVERRIDES5__TYPE uint32_t +#define PSEQ_OVERRIDES5__READ 0xffffc000U +#define PSEQ_OVERRIDES5__WRITE 0xffffc000U +#define PSEQ_OVERRIDES5__PRESERVED 0x00000000U +#define PSEQ_OVERRIDES5__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_OVERRIDES5_MACRO__ */ + +/** @} end of overrides5 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_sysram_overrides */ +/** + * @defgroup at_apb_pseq_paris_regs_core_sysram_overrides sysram_overrides + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_SYSRAM_OVERRIDES_MACRO__ +#define __PSEQ_SYSRAM_OVERRIDES_MACRO__ + +/* macros for field override_sysram_vddcut_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_sysram_vddcut_val_field override_sysram_vddcut_val_field + * @brief macros for field override_sysram_vddcut_val + * @details If override is set, what is state of sysram's head switches? [11:8] reserved [7] 16kB macro at high address space; [1] head switch open [0] head switch close [6] 16kB macro; [1] head switch open [0] head switch close [5] 16kB macro; [1] head switch open [0] head switch close [4] 16kB macro; [1] head switch open [0] head switch close [3] 16kB macro; [1] head switch open [0] head switch close [2] 16kB macro; [1] head switch open [0] head switch close [1] 16kB macro; [1] head switch open [0] head switch close [0] 16kB macro at lowest address space; [1] head switch open [0] head switch close + * @{ + */ +#define PSEQ_SYSRAM_OVERRIDES__OVERRIDE_SYSRAM_VDDCUT_VAL__SHIFT 0 +#define PSEQ_SYSRAM_OVERRIDES__OVERRIDE_SYSRAM_VDDCUT_VAL__WIDTH 8 +#define PSEQ_SYSRAM_OVERRIDES__OVERRIDE_SYSRAM_VDDCUT_VAL__MASK 0x000000ffU +#define PSEQ_SYSRAM_OVERRIDES__OVERRIDE_SYSRAM_VDDCUT_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES__OVERRIDE_SYSRAM_VDDCUT_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES__OVERRIDE_SYSRAM_VDDCUT_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES__OVERRIDE_SYSRAM_VDDCUT_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define PSEQ_SYSRAM_OVERRIDES__OVERRIDE_SYSRAM_VDDCUT_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_sysram_vddcut */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_sysram_vddcut_field override_sysram_vddcut_field + * @brief macros for field override_sysram_vddcut + * @details If set, software now has direct control of sysram's head switches. [23:20] reserved [19] 16kB macro at high address space [18] 16kB macro [17] 16kB macro [16] 16kB macro [15] 16kB macro [14] 16kB macro [13] 16kB macro [12] 16kB macro at lowest address space + * @{ + */ +#define PSEQ_SYSRAM_OVERRIDES__OVERRIDE_SYSRAM_VDDCUT__SHIFT 12 +#define PSEQ_SYSRAM_OVERRIDES__OVERRIDE_SYSRAM_VDDCUT__WIDTH 8 +#define PSEQ_SYSRAM_OVERRIDES__OVERRIDE_SYSRAM_VDDCUT__MASK 0x000ff000U +#define PSEQ_SYSRAM_OVERRIDES__OVERRIDE_SYSRAM_VDDCUT__READ(src) \ + (((uint32_t)(src)\ + & 0x000ff000U) >> 12) +#define PSEQ_SYSRAM_OVERRIDES__OVERRIDE_SYSRAM_VDDCUT__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x000ff000U) +#define PSEQ_SYSRAM_OVERRIDES__OVERRIDE_SYSRAM_VDDCUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ff000U) | (((uint32_t)(src) <<\ + 12) & 0x000ff000U) +#define PSEQ_SYSRAM_OVERRIDES__OVERRIDE_SYSRAM_VDDCUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x000ff000U))) +#define PSEQ_SYSRAM_OVERRIDES__OVERRIDE_SYSRAM_VDDCUT__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_SYSRAM_OVERRIDES__TYPE uint32_t +#define PSEQ_SYSRAM_OVERRIDES__READ 0x000ff0ffU +#define PSEQ_SYSRAM_OVERRIDES__WRITE 0x000ff0ffU +#define PSEQ_SYSRAM_OVERRIDES__PRESERVED 0x00000000U +#define PSEQ_SYSRAM_OVERRIDES__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_SYSRAM_OVERRIDES_MACRO__ */ + +/** @} end of sysram_overrides */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_sysram_overrides2 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_sysram_overrides2 sysram_overrides2 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_SYSRAM_OVERRIDES2_MACRO__ +#define __PSEQ_SYSRAM_OVERRIDES2_MACRO__ + +/* macros for field override_sysram_clken_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_sysram_clken_val_field override_sysram_clken_val_field + * @brief macros for field override_sysram_clken_val + * @details If override is set, what is state of sysram's clock enable signals? [11:8] reserved [7] 16kB macro at high address space [6] 16kB macro [5] 16kB macro [4] 16kB macro [3] 16kB macro [2] 16kB macro [1] 16kB macro [0] 16kB macro at lowest address space + * @{ + */ +#define PSEQ_SYSRAM_OVERRIDES2__OVERRIDE_SYSRAM_CLKEN_VAL__SHIFT 0 +#define PSEQ_SYSRAM_OVERRIDES2__OVERRIDE_SYSRAM_CLKEN_VAL__WIDTH 8 +#define PSEQ_SYSRAM_OVERRIDES2__OVERRIDE_SYSRAM_CLKEN_VAL__MASK 0x000000ffU +#define PSEQ_SYSRAM_OVERRIDES2__OVERRIDE_SYSRAM_CLKEN_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES2__OVERRIDE_SYSRAM_CLKEN_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES2__OVERRIDE_SYSRAM_CLKEN_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES2__OVERRIDE_SYSRAM_CLKEN_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define PSEQ_SYSRAM_OVERRIDES2__OVERRIDE_SYSRAM_CLKEN_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_sysram_clken */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_sysram_clken_field override_sysram_clken_field + * @brief macros for field override_sysram_clken + * @details If set, software now has direct control of sysram's clock enable signals. [23:20] reserved [19] 16kB macro at high address space [18] 16kB macro [17] 16kB macro [16] 16kB macro [15] 16kB macro [14] 16kB macro [13] 16kB macro [12] 16kB macro at lowest address space + * @{ + */ +#define PSEQ_SYSRAM_OVERRIDES2__OVERRIDE_SYSRAM_CLKEN__SHIFT 12 +#define PSEQ_SYSRAM_OVERRIDES2__OVERRIDE_SYSRAM_CLKEN__WIDTH 8 +#define PSEQ_SYSRAM_OVERRIDES2__OVERRIDE_SYSRAM_CLKEN__MASK 0x000ff000U +#define PSEQ_SYSRAM_OVERRIDES2__OVERRIDE_SYSRAM_CLKEN__READ(src) \ + (((uint32_t)(src)\ + & 0x000ff000U) >> 12) +#define PSEQ_SYSRAM_OVERRIDES2__OVERRIDE_SYSRAM_CLKEN__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x000ff000U) +#define PSEQ_SYSRAM_OVERRIDES2__OVERRIDE_SYSRAM_CLKEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ff000U) | (((uint32_t)(src) <<\ + 12) & 0x000ff000U) +#define PSEQ_SYSRAM_OVERRIDES2__OVERRIDE_SYSRAM_CLKEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x000ff000U))) +#define PSEQ_SYSRAM_OVERRIDES2__OVERRIDE_SYSRAM_CLKEN__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_SYSRAM_OVERRIDES2__TYPE uint32_t +#define PSEQ_SYSRAM_OVERRIDES2__READ 0x000ff0ffU +#define PSEQ_SYSRAM_OVERRIDES2__WRITE 0x000ff0ffU +#define PSEQ_SYSRAM_OVERRIDES2__PRESERVED 0x00000000U +#define PSEQ_SYSRAM_OVERRIDES2__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_SYSRAM_OVERRIDES2_MACRO__ */ + +/** @} end of sysram_overrides2 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_sysram_overrides3 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_sysram_overrides3 sysram_overrides3 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_SYSRAM_OVERRIDES3_MACRO__ +#define __PSEQ_SYSRAM_OVERRIDES3_MACRO__ + +/* macros for field override_sysram_iso_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_sysram_iso_val_field override_sysram_iso_val_field + * @brief macros for field override_sysram_iso_val + * @details If override is set, what is state of sysram's isolation signals? [11:8] reserved [7] 16kB macro at high address space [6] 16kB macro [5] 16kB macro [4] 16kB macro [3] 16kB macro [2] 16kB macro [1] 16kB macro [0] 16kB macro at lowest address space + * @{ + */ +#define PSEQ_SYSRAM_OVERRIDES3__OVERRIDE_SYSRAM_ISO_VAL__SHIFT 0 +#define PSEQ_SYSRAM_OVERRIDES3__OVERRIDE_SYSRAM_ISO_VAL__WIDTH 8 +#define PSEQ_SYSRAM_OVERRIDES3__OVERRIDE_SYSRAM_ISO_VAL__MASK 0x000000ffU +#define PSEQ_SYSRAM_OVERRIDES3__OVERRIDE_SYSRAM_ISO_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES3__OVERRIDE_SYSRAM_ISO_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES3__OVERRIDE_SYSRAM_ISO_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES3__OVERRIDE_SYSRAM_ISO_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define PSEQ_SYSRAM_OVERRIDES3__OVERRIDE_SYSRAM_ISO_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_sysram_iso */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_sysram_iso_field override_sysram_iso_field + * @brief macros for field override_sysram_iso + * @details If set, software now has direct control of sysram's isolation signals. [23:20] reserved [19] 16kB macro at high address space [18] 16kB macro [17] 16kB macro [16] 16kB macro [15] 16kB macro [14] 16kB macro [13] 16kB macro [12] 16kB macro at lowest address space + * @{ + */ +#define PSEQ_SYSRAM_OVERRIDES3__OVERRIDE_SYSRAM_ISO__SHIFT 12 +#define PSEQ_SYSRAM_OVERRIDES3__OVERRIDE_SYSRAM_ISO__WIDTH 8 +#define PSEQ_SYSRAM_OVERRIDES3__OVERRIDE_SYSRAM_ISO__MASK 0x000ff000U +#define PSEQ_SYSRAM_OVERRIDES3__OVERRIDE_SYSRAM_ISO__READ(src) \ + (((uint32_t)(src)\ + & 0x000ff000U) >> 12) +#define PSEQ_SYSRAM_OVERRIDES3__OVERRIDE_SYSRAM_ISO__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x000ff000U) +#define PSEQ_SYSRAM_OVERRIDES3__OVERRIDE_SYSRAM_ISO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ff000U) | (((uint32_t)(src) <<\ + 12) & 0x000ff000U) +#define PSEQ_SYSRAM_OVERRIDES3__OVERRIDE_SYSRAM_ISO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x000ff000U))) +#define PSEQ_SYSRAM_OVERRIDES3__OVERRIDE_SYSRAM_ISO__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_SYSRAM_OVERRIDES3__TYPE uint32_t +#define PSEQ_SYSRAM_OVERRIDES3__READ 0x000ff0ffU +#define PSEQ_SYSRAM_OVERRIDES3__WRITE 0x000ff0ffU +#define PSEQ_SYSRAM_OVERRIDES3__PRESERVED 0x00000000U +#define PSEQ_SYSRAM_OVERRIDES3__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_SYSRAM_OVERRIDES3_MACRO__ */ + +/** @} end of sysram_overrides3 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_sysram_overrides4 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_sysram_overrides4 sysram_overrides4 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_SYSRAM_OVERRIDES4_MACRO__ +#define __PSEQ_SYSRAM_OVERRIDES4_MACRO__ + +/* macros for field override_sysram_ls_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_sysram_ls_val_field override_sysram_ls_val_field + * @brief macros for field override_sysram_ls_val + * @details If override is set, what is state of sysram's LS signals? [11:8] reserved [7] 16kB macro at high address space [6] 16kB macro [5] 16kB macro [4] 16kB macro [3] 16kB macro [2] 16kB macro [1] 16kB macro [0] 16kB macro at lowest address space + * @{ + */ +#define PSEQ_SYSRAM_OVERRIDES4__OVERRIDE_SYSRAM_LS_VAL__SHIFT 0 +#define PSEQ_SYSRAM_OVERRIDES4__OVERRIDE_SYSRAM_LS_VAL__WIDTH 8 +#define PSEQ_SYSRAM_OVERRIDES4__OVERRIDE_SYSRAM_LS_VAL__MASK 0x000000ffU +#define PSEQ_SYSRAM_OVERRIDES4__OVERRIDE_SYSRAM_LS_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES4__OVERRIDE_SYSRAM_LS_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES4__OVERRIDE_SYSRAM_LS_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES4__OVERRIDE_SYSRAM_LS_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define PSEQ_SYSRAM_OVERRIDES4__OVERRIDE_SYSRAM_LS_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_sysram_ls */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_sysram_ls_field override_sysram_ls_field + * @brief macros for field override_sysram_ls + * @details If set, software now has direct control of sysram's LS signals. [23:20] reserved [19] 16kB macro at high address space [18] 16kB macro [17] 16kB macro [16] 16kB macro [15] 16kB macro [14] 16kB macro [13] 16kB macro [12] 16kB macro at lowest address space + * @{ + */ +#define PSEQ_SYSRAM_OVERRIDES4__OVERRIDE_SYSRAM_LS__SHIFT 12 +#define PSEQ_SYSRAM_OVERRIDES4__OVERRIDE_SYSRAM_LS__WIDTH 8 +#define PSEQ_SYSRAM_OVERRIDES4__OVERRIDE_SYSRAM_LS__MASK 0x000ff000U +#define PSEQ_SYSRAM_OVERRIDES4__OVERRIDE_SYSRAM_LS__READ(src) \ + (((uint32_t)(src)\ + & 0x000ff000U) >> 12) +#define PSEQ_SYSRAM_OVERRIDES4__OVERRIDE_SYSRAM_LS__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x000ff000U) +#define PSEQ_SYSRAM_OVERRIDES4__OVERRIDE_SYSRAM_LS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ff000U) | (((uint32_t)(src) <<\ + 12) & 0x000ff000U) +#define PSEQ_SYSRAM_OVERRIDES4__OVERRIDE_SYSRAM_LS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x000ff000U))) +#define PSEQ_SYSRAM_OVERRIDES4__OVERRIDE_SYSRAM_LS__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_SYSRAM_OVERRIDES4__TYPE uint32_t +#define PSEQ_SYSRAM_OVERRIDES4__READ 0x000ff0ffU +#define PSEQ_SYSRAM_OVERRIDES4__WRITE 0x000ff0ffU +#define PSEQ_SYSRAM_OVERRIDES4__PRESERVED 0x00000000U +#define PSEQ_SYSRAM_OVERRIDES4__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_SYSRAM_OVERRIDES4_MACRO__ */ + +/** @} end of sysram_overrides4 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_sysram_overrides5 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_sysram_overrides5 sysram_overrides5 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_SYSRAM_OVERRIDES5_MACRO__ +#define __PSEQ_SYSRAM_OVERRIDES5_MACRO__ + +/* macros for field override_sysram_ds_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_sysram_ds_val_field override_sysram_ds_val_field + * @brief macros for field override_sysram_ds_val + * @details If override is set, what is state of sysram's DS signals? [11:8] reserved [7] 16kB macro at high address space [6] 16kB macro [5] 16kB macro [4] 16kB macro [3] 16kB macro [2] 16kB macro [1] 16kB macro [0] 16kB macro at lowest address space + * @{ + */ +#define PSEQ_SYSRAM_OVERRIDES5__OVERRIDE_SYSRAM_DS_VAL__SHIFT 0 +#define PSEQ_SYSRAM_OVERRIDES5__OVERRIDE_SYSRAM_DS_VAL__WIDTH 8 +#define PSEQ_SYSRAM_OVERRIDES5__OVERRIDE_SYSRAM_DS_VAL__MASK 0x000000ffU +#define PSEQ_SYSRAM_OVERRIDES5__OVERRIDE_SYSRAM_DS_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES5__OVERRIDE_SYSRAM_DS_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES5__OVERRIDE_SYSRAM_DS_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES5__OVERRIDE_SYSRAM_DS_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define PSEQ_SYSRAM_OVERRIDES5__OVERRIDE_SYSRAM_DS_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_sysram_ds */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_sysram_ds_field override_sysram_ds_field + * @brief macros for field override_sysram_ds + * @details If set, software now has direct control of sysram's DS signals. [23:20] reserved [19] 16kB macro at high address space [18] 16kB macro [17] 16kB macro [16] 16kB macro [15] 16kB macro [14] 16kB macro [13] 16kB macro [12] 16kB macro at lowest address space + * @{ + */ +#define PSEQ_SYSRAM_OVERRIDES5__OVERRIDE_SYSRAM_DS__SHIFT 12 +#define PSEQ_SYSRAM_OVERRIDES5__OVERRIDE_SYSRAM_DS__WIDTH 8 +#define PSEQ_SYSRAM_OVERRIDES5__OVERRIDE_SYSRAM_DS__MASK 0x000ff000U +#define PSEQ_SYSRAM_OVERRIDES5__OVERRIDE_SYSRAM_DS__READ(src) \ + (((uint32_t)(src)\ + & 0x000ff000U) >> 12) +#define PSEQ_SYSRAM_OVERRIDES5__OVERRIDE_SYSRAM_DS__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x000ff000U) +#define PSEQ_SYSRAM_OVERRIDES5__OVERRIDE_SYSRAM_DS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ff000U) | (((uint32_t)(src) <<\ + 12) & 0x000ff000U) +#define PSEQ_SYSRAM_OVERRIDES5__OVERRIDE_SYSRAM_DS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x000ff000U))) +#define PSEQ_SYSRAM_OVERRIDES5__OVERRIDE_SYSRAM_DS__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_SYSRAM_OVERRIDES5__TYPE uint32_t +#define PSEQ_SYSRAM_OVERRIDES5__READ 0x000ff0ffU +#define PSEQ_SYSRAM_OVERRIDES5__WRITE 0x000ff0ffU +#define PSEQ_SYSRAM_OVERRIDES5__PRESERVED 0x00000000U +#define PSEQ_SYSRAM_OVERRIDES5__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_SYSRAM_OVERRIDES5_MACRO__ */ + +/** @} end of sysram_overrides5 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_sysram_overrides6 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_sysram_overrides6 sysram_overrides6 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_SYSRAM_OVERRIDES6_MACRO__ +#define __PSEQ_SYSRAM_OVERRIDES6_MACRO__ + +/* macros for field override_sysram_sd_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_sysram_sd_val_field override_sysram_sd_val_field + * @brief macros for field override_sysram_sd_val + * @details If override is set, what is state of sysram's SD signals? [11:8] reserved [7] 16kB macro at high address space [6] 16kB macro [5] 16kB macro [4] 16kB macro [3] 16kB macro [2] 16kB macro [1] 16kB macro [0] 16kB macro at lowest address space + * @{ + */ +#define PSEQ_SYSRAM_OVERRIDES6__OVERRIDE_SYSRAM_SD_VAL__SHIFT 0 +#define PSEQ_SYSRAM_OVERRIDES6__OVERRIDE_SYSRAM_SD_VAL__WIDTH 8 +#define PSEQ_SYSRAM_OVERRIDES6__OVERRIDE_SYSRAM_SD_VAL__MASK 0x000000ffU +#define PSEQ_SYSRAM_OVERRIDES6__OVERRIDE_SYSRAM_SD_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES6__OVERRIDE_SYSRAM_SD_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES6__OVERRIDE_SYSRAM_SD_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES6__OVERRIDE_SYSRAM_SD_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define PSEQ_SYSRAM_OVERRIDES6__OVERRIDE_SYSRAM_SD_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_sysram_sd */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_sysram_sd_field override_sysram_sd_field + * @brief macros for field override_sysram_sd + * @details If set, software now has direct control of sysram's SD signals. [23:20] reserved [19] 16kB macro at high address space [18] 16kB macro [17] 16kB macro [16] 16kB macro [15] 16kB macro [14] 16kB macro [13] 16kB macro [12] 16kB macro at lowest address space + * @{ + */ +#define PSEQ_SYSRAM_OVERRIDES6__OVERRIDE_SYSRAM_SD__SHIFT 12 +#define PSEQ_SYSRAM_OVERRIDES6__OVERRIDE_SYSRAM_SD__WIDTH 8 +#define PSEQ_SYSRAM_OVERRIDES6__OVERRIDE_SYSRAM_SD__MASK 0x000ff000U +#define PSEQ_SYSRAM_OVERRIDES6__OVERRIDE_SYSRAM_SD__READ(src) \ + (((uint32_t)(src)\ + & 0x000ff000U) >> 12) +#define PSEQ_SYSRAM_OVERRIDES6__OVERRIDE_SYSRAM_SD__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x000ff000U) +#define PSEQ_SYSRAM_OVERRIDES6__OVERRIDE_SYSRAM_SD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ff000U) | (((uint32_t)(src) <<\ + 12) & 0x000ff000U) +#define PSEQ_SYSRAM_OVERRIDES6__OVERRIDE_SYSRAM_SD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x000ff000U))) +#define PSEQ_SYSRAM_OVERRIDES6__OVERRIDE_SYSRAM_SD__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_SYSRAM_OVERRIDES6__TYPE uint32_t +#define PSEQ_SYSRAM_OVERRIDES6__READ 0x000ff0ffU +#define PSEQ_SYSRAM_OVERRIDES6__WRITE 0x000ff0ffU +#define PSEQ_SYSRAM_OVERRIDES6__PRESERVED 0x00000000U +#define PSEQ_SYSRAM_OVERRIDES6__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_SYSRAM_OVERRIDES6_MACRO__ */ + +/** @} end of sysram_overrides6 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_sysram_overrides7 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_sysram_overrides7 sysram_overrides7 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_SYSRAM_OVERRIDES7_MACRO__ +#define __PSEQ_SYSRAM_OVERRIDES7_MACRO__ + +/* macros for field block_sysram_vddcut */ +/** + * @defgroup at_apb_pseq_paris_regs_core_block_sysram_vddcut_field block_sysram_vddcut_field + * @brief macros for field block_sysram_vddcut + * @details Block core's FSM from cutting the vdd supplies to the sysram. [11:8] reserved [7] 16kB macro at high address space [6] 16kB macro [5] 16kB macro [4] 16kB macro [3] 16kB macro [2] 16kB macro [1] 16kB macro [0] 16kB macro at lowest address space + * @{ + */ +#define PSEQ_SYSRAM_OVERRIDES7__BLOCK_SYSRAM_VDDCUT__SHIFT 0 +#define PSEQ_SYSRAM_OVERRIDES7__BLOCK_SYSRAM_VDDCUT__WIDTH 8 +#define PSEQ_SYSRAM_OVERRIDES7__BLOCK_SYSRAM_VDDCUT__MASK 0x000000ffU +#define PSEQ_SYSRAM_OVERRIDES7__BLOCK_SYSRAM_VDDCUT__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES7__BLOCK_SYSRAM_VDDCUT__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES7__BLOCK_SYSRAM_VDDCUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES7__BLOCK_SYSRAM_VDDCUT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define PSEQ_SYSRAM_OVERRIDES7__BLOCK_SYSRAM_VDDCUT__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_SYSRAM_OVERRIDES7__TYPE uint32_t +#define PSEQ_SYSRAM_OVERRIDES7__READ 0x000000ffU +#define PSEQ_SYSRAM_OVERRIDES7__WRITE 0x000000ffU +#define PSEQ_SYSRAM_OVERRIDES7__PRESERVED 0x00000000U +#define PSEQ_SYSRAM_OVERRIDES7__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_SYSRAM_OVERRIDES7_MACRO__ */ + +/** @} end of sysram_overrides7 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_sysram_overrides8 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_sysram_overrides8 sysram_overrides8 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_SYSRAM_OVERRIDES8_MACRO__ +#define __PSEQ_SYSRAM_OVERRIDES8_MACRO__ + +/* macros for field block_sysram_sd */ +/** + * @defgroup at_apb_pseq_paris_regs_core_block_sysram_sd_field block_sysram_sd_field + * @brief macros for field block_sysram_sd + * @details Block core's FSM from setting the SD signal to the sysram. [11:8] reserved [7] 16kB macro at high address space [6] 16kB macro [5] 16kB macro [4] 16kB macro [3] 16kB macro [2] 16kB macro [1] 16kB macro [0] 16kB macro at lowest address space + * @{ + */ +#define PSEQ_SYSRAM_OVERRIDES8__BLOCK_SYSRAM_SD__SHIFT 0 +#define PSEQ_SYSRAM_OVERRIDES8__BLOCK_SYSRAM_SD__WIDTH 8 +#define PSEQ_SYSRAM_OVERRIDES8__BLOCK_SYSRAM_SD__MASK 0x000000ffU +#define PSEQ_SYSRAM_OVERRIDES8__BLOCK_SYSRAM_SD__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES8__BLOCK_SYSRAM_SD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES8__BLOCK_SYSRAM_SD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define PSEQ_SYSRAM_OVERRIDES8__BLOCK_SYSRAM_SD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define PSEQ_SYSRAM_OVERRIDES8__BLOCK_SYSRAM_SD__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_SYSRAM_OVERRIDES8__TYPE uint32_t +#define PSEQ_SYSRAM_OVERRIDES8__READ 0x000000ffU +#define PSEQ_SYSRAM_OVERRIDES8__WRITE 0x000000ffU +#define PSEQ_SYSRAM_OVERRIDES8__PRESERVED 0x00000000U +#define PSEQ_SYSRAM_OVERRIDES8__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_SYSRAM_OVERRIDES8_MACRO__ */ + +/** @} end of sysram_overrides8 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_emram_overrides */ +/** + * @defgroup at_apb_pseq_paris_regs_core_emram_overrides emram_overrides + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_EMRAM_OVERRIDES_MACRO__ +#define __PSEQ_EMRAM_OVERRIDES_MACRO__ + +/* macros for field override_emram_vddcut_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_emram_vddcut_val_field override_emram_vddcut_val_field + * @brief macros for field override_emram_vddcut_val + * @details If override is set, what are the states of exchange memory vddcut signals? + * @{ + */ +#define PSEQ_EMRAM_OVERRIDES__OVERRIDE_EMRAM_VDDCUT_VAL__SHIFT 0 +#define PSEQ_EMRAM_OVERRIDES__OVERRIDE_EMRAM_VDDCUT_VAL__WIDTH 2 +#define PSEQ_EMRAM_OVERRIDES__OVERRIDE_EMRAM_VDDCUT_VAL__MASK 0x00000003U +#define PSEQ_EMRAM_OVERRIDES__OVERRIDE_EMRAM_VDDCUT_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES__OVERRIDE_EMRAM_VDDCUT_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES__OVERRIDE_EMRAM_VDDCUT_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES__OVERRIDE_EMRAM_VDDCUT_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define PSEQ_EMRAM_OVERRIDES__OVERRIDE_EMRAM_VDDCUT_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_emram_vddcut */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_emram_vddcut_field override_emram_vddcut_field + * @brief macros for field override_emram_vddcut + * @details If set, software now has direct control of exchange memory vddcut signals. + * @{ + */ +#define PSEQ_EMRAM_OVERRIDES__OVERRIDE_EMRAM_VDDCUT__SHIFT 12 +#define PSEQ_EMRAM_OVERRIDES__OVERRIDE_EMRAM_VDDCUT__WIDTH 2 +#define PSEQ_EMRAM_OVERRIDES__OVERRIDE_EMRAM_VDDCUT__MASK 0x00003000U +#define PSEQ_EMRAM_OVERRIDES__OVERRIDE_EMRAM_VDDCUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00003000U) >> 12) +#define PSEQ_EMRAM_OVERRIDES__OVERRIDE_EMRAM_VDDCUT__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00003000U) +#define PSEQ_EMRAM_OVERRIDES__OVERRIDE_EMRAM_VDDCUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((uint32_t)(src) <<\ + 12) & 0x00003000U) +#define PSEQ_EMRAM_OVERRIDES__OVERRIDE_EMRAM_VDDCUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00003000U))) +#define PSEQ_EMRAM_OVERRIDES__OVERRIDE_EMRAM_VDDCUT__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_EMRAM_OVERRIDES__TYPE uint32_t +#define PSEQ_EMRAM_OVERRIDES__READ 0x00003003U +#define PSEQ_EMRAM_OVERRIDES__WRITE 0x00003003U +#define PSEQ_EMRAM_OVERRIDES__PRESERVED 0x00000000U +#define PSEQ_EMRAM_OVERRIDES__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_EMRAM_OVERRIDES_MACRO__ */ + +/** @} end of emram_overrides */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_emram_overrides2 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_emram_overrides2 emram_overrides2 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_EMRAM_OVERRIDES2_MACRO__ +#define __PSEQ_EMRAM_OVERRIDES2_MACRO__ + +/* macros for field override_emram_clken_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_emram_clken_val_field override_emram_clken_val_field + * @brief macros for field override_emram_clken_val + * @details If override is set, what are the states of exchange memory clock enable signals? + * @{ + */ +#define PSEQ_EMRAM_OVERRIDES2__OVERRIDE_EMRAM_CLKEN_VAL__SHIFT 0 +#define PSEQ_EMRAM_OVERRIDES2__OVERRIDE_EMRAM_CLKEN_VAL__WIDTH 2 +#define PSEQ_EMRAM_OVERRIDES2__OVERRIDE_EMRAM_CLKEN_VAL__MASK 0x00000003U +#define PSEQ_EMRAM_OVERRIDES2__OVERRIDE_EMRAM_CLKEN_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES2__OVERRIDE_EMRAM_CLKEN_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES2__OVERRIDE_EMRAM_CLKEN_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES2__OVERRIDE_EMRAM_CLKEN_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define PSEQ_EMRAM_OVERRIDES2__OVERRIDE_EMRAM_CLKEN_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_emram_clken */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_emram_clken_field override_emram_clken_field + * @brief macros for field override_emram_clken + * @details If set, software now has direct control of exchange memory clock enable signals. + * @{ + */ +#define PSEQ_EMRAM_OVERRIDES2__OVERRIDE_EMRAM_CLKEN__SHIFT 12 +#define PSEQ_EMRAM_OVERRIDES2__OVERRIDE_EMRAM_CLKEN__WIDTH 2 +#define PSEQ_EMRAM_OVERRIDES2__OVERRIDE_EMRAM_CLKEN__MASK 0x00003000U +#define PSEQ_EMRAM_OVERRIDES2__OVERRIDE_EMRAM_CLKEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00003000U) >> 12) +#define PSEQ_EMRAM_OVERRIDES2__OVERRIDE_EMRAM_CLKEN__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00003000U) +#define PSEQ_EMRAM_OVERRIDES2__OVERRIDE_EMRAM_CLKEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((uint32_t)(src) <<\ + 12) & 0x00003000U) +#define PSEQ_EMRAM_OVERRIDES2__OVERRIDE_EMRAM_CLKEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00003000U))) +#define PSEQ_EMRAM_OVERRIDES2__OVERRIDE_EMRAM_CLKEN__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_EMRAM_OVERRIDES2__TYPE uint32_t +#define PSEQ_EMRAM_OVERRIDES2__READ 0x00003003U +#define PSEQ_EMRAM_OVERRIDES2__WRITE 0x00003003U +#define PSEQ_EMRAM_OVERRIDES2__PRESERVED 0x00000000U +#define PSEQ_EMRAM_OVERRIDES2__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_EMRAM_OVERRIDES2_MACRO__ */ + +/** @} end of emram_overrides2 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_emram_overrides3 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_emram_overrides3 emram_overrides3 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_EMRAM_OVERRIDES3_MACRO__ +#define __PSEQ_EMRAM_OVERRIDES3_MACRO__ + +/* macros for field override_emram_iso_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_emram_iso_val_field override_emram_iso_val_field + * @brief macros for field override_emram_iso_val + * @details If override is set, what are the states of exchange memory isolation signals? + * @{ + */ +#define PSEQ_EMRAM_OVERRIDES3__OVERRIDE_EMRAM_ISO_VAL__SHIFT 0 +#define PSEQ_EMRAM_OVERRIDES3__OVERRIDE_EMRAM_ISO_VAL__WIDTH 2 +#define PSEQ_EMRAM_OVERRIDES3__OVERRIDE_EMRAM_ISO_VAL__MASK 0x00000003U +#define PSEQ_EMRAM_OVERRIDES3__OVERRIDE_EMRAM_ISO_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES3__OVERRIDE_EMRAM_ISO_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES3__OVERRIDE_EMRAM_ISO_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES3__OVERRIDE_EMRAM_ISO_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define PSEQ_EMRAM_OVERRIDES3__OVERRIDE_EMRAM_ISO_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_emram_iso */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_emram_iso_field override_emram_iso_field + * @brief macros for field override_emram_iso + * @details If set, software now has direct control of exchange memory isolation signals. + * @{ + */ +#define PSEQ_EMRAM_OVERRIDES3__OVERRIDE_EMRAM_ISO__SHIFT 12 +#define PSEQ_EMRAM_OVERRIDES3__OVERRIDE_EMRAM_ISO__WIDTH 2 +#define PSEQ_EMRAM_OVERRIDES3__OVERRIDE_EMRAM_ISO__MASK 0x00003000U +#define PSEQ_EMRAM_OVERRIDES3__OVERRIDE_EMRAM_ISO__READ(src) \ + (((uint32_t)(src)\ + & 0x00003000U) >> 12) +#define PSEQ_EMRAM_OVERRIDES3__OVERRIDE_EMRAM_ISO__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00003000U) +#define PSEQ_EMRAM_OVERRIDES3__OVERRIDE_EMRAM_ISO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((uint32_t)(src) <<\ + 12) & 0x00003000U) +#define PSEQ_EMRAM_OVERRIDES3__OVERRIDE_EMRAM_ISO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00003000U))) +#define PSEQ_EMRAM_OVERRIDES3__OVERRIDE_EMRAM_ISO__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_EMRAM_OVERRIDES3__TYPE uint32_t +#define PSEQ_EMRAM_OVERRIDES3__READ 0x00003003U +#define PSEQ_EMRAM_OVERRIDES3__WRITE 0x00003003U +#define PSEQ_EMRAM_OVERRIDES3__PRESERVED 0x00000000U +#define PSEQ_EMRAM_OVERRIDES3__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_EMRAM_OVERRIDES3_MACRO__ */ + +/** @} end of emram_overrides3 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_emram_overrides4 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_emram_overrides4 emram_overrides4 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_EMRAM_OVERRIDES4_MACRO__ +#define __PSEQ_EMRAM_OVERRIDES4_MACRO__ + +/* macros for field override_emram_ls_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_emram_ls_val_field override_emram_ls_val_field + * @brief macros for field override_emram_ls_val + * @details If override is set, what are the states of exchange memory LS signals? + * @{ + */ +#define PSEQ_EMRAM_OVERRIDES4__OVERRIDE_EMRAM_LS_VAL__SHIFT 0 +#define PSEQ_EMRAM_OVERRIDES4__OVERRIDE_EMRAM_LS_VAL__WIDTH 2 +#define PSEQ_EMRAM_OVERRIDES4__OVERRIDE_EMRAM_LS_VAL__MASK 0x00000003U +#define PSEQ_EMRAM_OVERRIDES4__OVERRIDE_EMRAM_LS_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES4__OVERRIDE_EMRAM_LS_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES4__OVERRIDE_EMRAM_LS_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES4__OVERRIDE_EMRAM_LS_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define PSEQ_EMRAM_OVERRIDES4__OVERRIDE_EMRAM_LS_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_emram_ls */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_emram_ls_field override_emram_ls_field + * @brief macros for field override_emram_ls + * @details If set, software now has direct control of exchange memory LS signals. + * @{ + */ +#define PSEQ_EMRAM_OVERRIDES4__OVERRIDE_EMRAM_LS__SHIFT 12 +#define PSEQ_EMRAM_OVERRIDES4__OVERRIDE_EMRAM_LS__WIDTH 2 +#define PSEQ_EMRAM_OVERRIDES4__OVERRIDE_EMRAM_LS__MASK 0x00003000U +#define PSEQ_EMRAM_OVERRIDES4__OVERRIDE_EMRAM_LS__READ(src) \ + (((uint32_t)(src)\ + & 0x00003000U) >> 12) +#define PSEQ_EMRAM_OVERRIDES4__OVERRIDE_EMRAM_LS__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00003000U) +#define PSEQ_EMRAM_OVERRIDES4__OVERRIDE_EMRAM_LS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((uint32_t)(src) <<\ + 12) & 0x00003000U) +#define PSEQ_EMRAM_OVERRIDES4__OVERRIDE_EMRAM_LS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00003000U))) +#define PSEQ_EMRAM_OVERRIDES4__OVERRIDE_EMRAM_LS__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_EMRAM_OVERRIDES4__TYPE uint32_t +#define PSEQ_EMRAM_OVERRIDES4__READ 0x00003003U +#define PSEQ_EMRAM_OVERRIDES4__WRITE 0x00003003U +#define PSEQ_EMRAM_OVERRIDES4__PRESERVED 0x00000000U +#define PSEQ_EMRAM_OVERRIDES4__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_EMRAM_OVERRIDES4_MACRO__ */ + +/** @} end of emram_overrides4 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_emram_overrides5 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_emram_overrides5 emram_overrides5 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_EMRAM_OVERRIDES5_MACRO__ +#define __PSEQ_EMRAM_OVERRIDES5_MACRO__ + +/* macros for field override_emram_ds_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_emram_ds_val_field override_emram_ds_val_field + * @brief macros for field override_emram_ds_val + * @details If override is set, what are the states of exchange memory DS signals? + * @{ + */ +#define PSEQ_EMRAM_OVERRIDES5__OVERRIDE_EMRAM_DS_VAL__SHIFT 0 +#define PSEQ_EMRAM_OVERRIDES5__OVERRIDE_EMRAM_DS_VAL__WIDTH 2 +#define PSEQ_EMRAM_OVERRIDES5__OVERRIDE_EMRAM_DS_VAL__MASK 0x00000003U +#define PSEQ_EMRAM_OVERRIDES5__OVERRIDE_EMRAM_DS_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES5__OVERRIDE_EMRAM_DS_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES5__OVERRIDE_EMRAM_DS_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES5__OVERRIDE_EMRAM_DS_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define PSEQ_EMRAM_OVERRIDES5__OVERRIDE_EMRAM_DS_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_emram_ds */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_emram_ds_field override_emram_ds_field + * @brief macros for field override_emram_ds + * @details If set, software now has direct control of exchange memory DS signals. + * @{ + */ +#define PSEQ_EMRAM_OVERRIDES5__OVERRIDE_EMRAM_DS__SHIFT 12 +#define PSEQ_EMRAM_OVERRIDES5__OVERRIDE_EMRAM_DS__WIDTH 2 +#define PSEQ_EMRAM_OVERRIDES5__OVERRIDE_EMRAM_DS__MASK 0x00003000U +#define PSEQ_EMRAM_OVERRIDES5__OVERRIDE_EMRAM_DS__READ(src) \ + (((uint32_t)(src)\ + & 0x00003000U) >> 12) +#define PSEQ_EMRAM_OVERRIDES5__OVERRIDE_EMRAM_DS__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00003000U) +#define PSEQ_EMRAM_OVERRIDES5__OVERRIDE_EMRAM_DS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((uint32_t)(src) <<\ + 12) & 0x00003000U) +#define PSEQ_EMRAM_OVERRIDES5__OVERRIDE_EMRAM_DS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00003000U))) +#define PSEQ_EMRAM_OVERRIDES5__OVERRIDE_EMRAM_DS__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_EMRAM_OVERRIDES5__TYPE uint32_t +#define PSEQ_EMRAM_OVERRIDES5__READ 0x00003003U +#define PSEQ_EMRAM_OVERRIDES5__WRITE 0x00003003U +#define PSEQ_EMRAM_OVERRIDES5__PRESERVED 0x00000000U +#define PSEQ_EMRAM_OVERRIDES5__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_EMRAM_OVERRIDES5_MACRO__ */ + +/** @} end of emram_overrides5 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_emram_overrides6 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_emram_overrides6 emram_overrides6 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_EMRAM_OVERRIDES6_MACRO__ +#define __PSEQ_EMRAM_OVERRIDES6_MACRO__ + +/* macros for field override_emram_sd_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_emram_sd_val_field override_emram_sd_val_field + * @brief macros for field override_emram_sd_val + * @details If override is set, what are the states of exchange memory SD signals? + * @{ + */ +#define PSEQ_EMRAM_OVERRIDES6__OVERRIDE_EMRAM_SD_VAL__SHIFT 0 +#define PSEQ_EMRAM_OVERRIDES6__OVERRIDE_EMRAM_SD_VAL__WIDTH 2 +#define PSEQ_EMRAM_OVERRIDES6__OVERRIDE_EMRAM_SD_VAL__MASK 0x00000003U +#define PSEQ_EMRAM_OVERRIDES6__OVERRIDE_EMRAM_SD_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES6__OVERRIDE_EMRAM_SD_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES6__OVERRIDE_EMRAM_SD_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES6__OVERRIDE_EMRAM_SD_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define PSEQ_EMRAM_OVERRIDES6__OVERRIDE_EMRAM_SD_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_emram_sd */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_emram_sd_field override_emram_sd_field + * @brief macros for field override_emram_sd + * @details If set, software now has direct control of exchange memory SD signals. + * @{ + */ +#define PSEQ_EMRAM_OVERRIDES6__OVERRIDE_EMRAM_SD__SHIFT 12 +#define PSEQ_EMRAM_OVERRIDES6__OVERRIDE_EMRAM_SD__WIDTH 2 +#define PSEQ_EMRAM_OVERRIDES6__OVERRIDE_EMRAM_SD__MASK 0x00003000U +#define PSEQ_EMRAM_OVERRIDES6__OVERRIDE_EMRAM_SD__READ(src) \ + (((uint32_t)(src)\ + & 0x00003000U) >> 12) +#define PSEQ_EMRAM_OVERRIDES6__OVERRIDE_EMRAM_SD__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00003000U) +#define PSEQ_EMRAM_OVERRIDES6__OVERRIDE_EMRAM_SD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((uint32_t)(src) <<\ + 12) & 0x00003000U) +#define PSEQ_EMRAM_OVERRIDES6__OVERRIDE_EMRAM_SD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00003000U))) +#define PSEQ_EMRAM_OVERRIDES6__OVERRIDE_EMRAM_SD__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_EMRAM_OVERRIDES6__TYPE uint32_t +#define PSEQ_EMRAM_OVERRIDES6__READ 0x00003003U +#define PSEQ_EMRAM_OVERRIDES6__WRITE 0x00003003U +#define PSEQ_EMRAM_OVERRIDES6__PRESERVED 0x00000000U +#define PSEQ_EMRAM_OVERRIDES6__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_EMRAM_OVERRIDES6_MACRO__ */ + +/** @} end of emram_overrides6 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_emram_overrides7 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_emram_overrides7 emram_overrides7 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_EMRAM_OVERRIDES7_MACRO__ +#define __PSEQ_EMRAM_OVERRIDES7_MACRO__ + +/* macros for field block_emram_vddcut */ +/** + * @defgroup at_apb_pseq_paris_regs_core_block_emram_vddcut_field block_emram_vddcut_field + * @brief macros for field block_emram_vddcut + * @details If set, core's FSM cannot open the exchange memory head switches. + * @{ + */ +#define PSEQ_EMRAM_OVERRIDES7__BLOCK_EMRAM_VDDCUT__SHIFT 0 +#define PSEQ_EMRAM_OVERRIDES7__BLOCK_EMRAM_VDDCUT__WIDTH 2 +#define PSEQ_EMRAM_OVERRIDES7__BLOCK_EMRAM_VDDCUT__MASK 0x00000003U +#define PSEQ_EMRAM_OVERRIDES7__BLOCK_EMRAM_VDDCUT__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES7__BLOCK_EMRAM_VDDCUT__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES7__BLOCK_EMRAM_VDDCUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES7__BLOCK_EMRAM_VDDCUT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define PSEQ_EMRAM_OVERRIDES7__BLOCK_EMRAM_VDDCUT__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_EMRAM_OVERRIDES7__TYPE uint32_t +#define PSEQ_EMRAM_OVERRIDES7__READ 0x00000003U +#define PSEQ_EMRAM_OVERRIDES7__WRITE 0x00000003U +#define PSEQ_EMRAM_OVERRIDES7__PRESERVED 0x00000000U +#define PSEQ_EMRAM_OVERRIDES7__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_EMRAM_OVERRIDES7_MACRO__ */ + +/** @} end of emram_overrides7 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_emram_overrides8 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_emram_overrides8 emram_overrides8 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_EMRAM_OVERRIDES8_MACRO__ +#define __PSEQ_EMRAM_OVERRIDES8_MACRO__ + +/* macros for field block_emram_sd */ +/** + * @defgroup at_apb_pseq_paris_regs_core_block_emram_sd_field block_emram_sd_field + * @brief macros for field block_emram_sd + * @details If set, core's FSM cannot set the exchange memory SD signals. + * @{ + */ +#define PSEQ_EMRAM_OVERRIDES8__BLOCK_EMRAM_SD__SHIFT 0 +#define PSEQ_EMRAM_OVERRIDES8__BLOCK_EMRAM_SD__WIDTH 2 +#define PSEQ_EMRAM_OVERRIDES8__BLOCK_EMRAM_SD__MASK 0x00000003U +#define PSEQ_EMRAM_OVERRIDES8__BLOCK_EMRAM_SD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES8__BLOCK_EMRAM_SD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES8__BLOCK_EMRAM_SD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define PSEQ_EMRAM_OVERRIDES8__BLOCK_EMRAM_SD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define PSEQ_EMRAM_OVERRIDES8__BLOCK_EMRAM_SD__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_EMRAM_OVERRIDES8__TYPE uint32_t +#define PSEQ_EMRAM_OVERRIDES8__READ 0x00000003U +#define PSEQ_EMRAM_OVERRIDES8__WRITE 0x00000003U +#define PSEQ_EMRAM_OVERRIDES8__PRESERVED 0x00000000U +#define PSEQ_EMRAM_OVERRIDES8__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_EMRAM_OVERRIDES8_MACRO__ */ + +/** @} end of emram_overrides8 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_icache_overrides */ +/** + * @defgroup at_apb_pseq_paris_regs_core_icache_overrides icache_overrides + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_ICACHE_OVERRIDES_MACRO__ +#define __PSEQ_ICACHE_OVERRIDES_MACRO__ + +/* macros for field override_icache_vddcut_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_icache_vddcut_val_field override_icache_vddcut_val_field + * @brief macros for field override_icache_vddcut_val + * @details If override is set, what is state of cpu icache's head switches? [3] data1 macro; [1] head switch open [0] head switch close [2] data0 macro; [1] head switch open [0] head switch close [1] tag1 macro; [1] head switch open [0] head switch close [0] tag0 macro; [1] head switch open [0] head switch close + * @{ + */ +#define PSEQ_ICACHE_OVERRIDES__OVERRIDE_ICACHE_VDDCUT_VAL__SHIFT 0 +#define PSEQ_ICACHE_OVERRIDES__OVERRIDE_ICACHE_VDDCUT_VAL__WIDTH 4 +#define PSEQ_ICACHE_OVERRIDES__OVERRIDE_ICACHE_VDDCUT_VAL__MASK 0x0000000fU +#define PSEQ_ICACHE_OVERRIDES__OVERRIDE_ICACHE_VDDCUT_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES__OVERRIDE_ICACHE_VDDCUT_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES__OVERRIDE_ICACHE_VDDCUT_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES__OVERRIDE_ICACHE_VDDCUT_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define PSEQ_ICACHE_OVERRIDES__OVERRIDE_ICACHE_VDDCUT_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_icache_vddcut */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_icache_vddcut_field override_icache_vddcut_field + * @brief macros for field override_icache_vddcut + * @details If set, software now has direct control of cpu icache's head switches. [15] data1 macro [14] data0 macro [13] tag1 macro [12] tag0 macro + * @{ + */ +#define PSEQ_ICACHE_OVERRIDES__OVERRIDE_ICACHE_VDDCUT__SHIFT 12 +#define PSEQ_ICACHE_OVERRIDES__OVERRIDE_ICACHE_VDDCUT__WIDTH 4 +#define PSEQ_ICACHE_OVERRIDES__OVERRIDE_ICACHE_VDDCUT__MASK 0x0000f000U +#define PSEQ_ICACHE_OVERRIDES__OVERRIDE_ICACHE_VDDCUT__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f000U) >> 12) +#define PSEQ_ICACHE_OVERRIDES__OVERRIDE_ICACHE_VDDCUT__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0000f000U) +#define PSEQ_ICACHE_OVERRIDES__OVERRIDE_ICACHE_VDDCUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((uint32_t)(src) <<\ + 12) & 0x0000f000U) +#define PSEQ_ICACHE_OVERRIDES__OVERRIDE_ICACHE_VDDCUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0000f000U))) +#define PSEQ_ICACHE_OVERRIDES__OVERRIDE_ICACHE_VDDCUT__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_ICACHE_OVERRIDES__TYPE uint32_t +#define PSEQ_ICACHE_OVERRIDES__READ 0x0000f00fU +#define PSEQ_ICACHE_OVERRIDES__WRITE 0x0000f00fU +#define PSEQ_ICACHE_OVERRIDES__PRESERVED 0x00000000U +#define PSEQ_ICACHE_OVERRIDES__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_ICACHE_OVERRIDES_MACRO__ */ + +/** @} end of icache_overrides */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_icache_overrides2 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_icache_overrides2 icache_overrides2 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_ICACHE_OVERRIDES2_MACRO__ +#define __PSEQ_ICACHE_OVERRIDES2_MACRO__ + +/* macros for field override_icache_clken_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_icache_clken_val_field override_icache_clken_val_field + * @brief macros for field override_icache_clken_val + * @details If override is set, what is state of cpu icache's clock enable signals? [3] data1 macro [2] data0 macro [1] tag1 macro [0] tag0 macro + * @{ + */ +#define PSEQ_ICACHE_OVERRIDES2__OVERRIDE_ICACHE_CLKEN_VAL__SHIFT 0 +#define PSEQ_ICACHE_OVERRIDES2__OVERRIDE_ICACHE_CLKEN_VAL__WIDTH 4 +#define PSEQ_ICACHE_OVERRIDES2__OVERRIDE_ICACHE_CLKEN_VAL__MASK 0x0000000fU +#define PSEQ_ICACHE_OVERRIDES2__OVERRIDE_ICACHE_CLKEN_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES2__OVERRIDE_ICACHE_CLKEN_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES2__OVERRIDE_ICACHE_CLKEN_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES2__OVERRIDE_ICACHE_CLKEN_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define PSEQ_ICACHE_OVERRIDES2__OVERRIDE_ICACHE_CLKEN_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_icache_clken */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_icache_clken_field override_icache_clken_field + * @brief macros for field override_icache_clken + * @details If set, software now has direct control of cpu icache's clock enable signals. [15] data1 macro [14] data0 macro [13] tag1 macro [12] tag0 macro + * @{ + */ +#define PSEQ_ICACHE_OVERRIDES2__OVERRIDE_ICACHE_CLKEN__SHIFT 12 +#define PSEQ_ICACHE_OVERRIDES2__OVERRIDE_ICACHE_CLKEN__WIDTH 4 +#define PSEQ_ICACHE_OVERRIDES2__OVERRIDE_ICACHE_CLKEN__MASK 0x0000f000U +#define PSEQ_ICACHE_OVERRIDES2__OVERRIDE_ICACHE_CLKEN__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f000U) >> 12) +#define PSEQ_ICACHE_OVERRIDES2__OVERRIDE_ICACHE_CLKEN__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0000f000U) +#define PSEQ_ICACHE_OVERRIDES2__OVERRIDE_ICACHE_CLKEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((uint32_t)(src) <<\ + 12) & 0x0000f000U) +#define PSEQ_ICACHE_OVERRIDES2__OVERRIDE_ICACHE_CLKEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0000f000U))) +#define PSEQ_ICACHE_OVERRIDES2__OVERRIDE_ICACHE_CLKEN__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_ICACHE_OVERRIDES2__TYPE uint32_t +#define PSEQ_ICACHE_OVERRIDES2__READ 0x0000f00fU +#define PSEQ_ICACHE_OVERRIDES2__WRITE 0x0000f00fU +#define PSEQ_ICACHE_OVERRIDES2__PRESERVED 0x00000000U +#define PSEQ_ICACHE_OVERRIDES2__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_ICACHE_OVERRIDES2_MACRO__ */ + +/** @} end of icache_overrides2 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_icache_overrides3 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_icache_overrides3 icache_overrides3 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_ICACHE_OVERRIDES3_MACRO__ +#define __PSEQ_ICACHE_OVERRIDES3_MACRO__ + +/* macros for field override_icache_iso_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_icache_iso_val_field override_icache_iso_val_field + * @brief macros for field override_icache_iso_val + * @details If override is set, what is state of cpu icache's isolation signals? [3] data1 macro [2] data0 macro [1] tag1 macro [0] tag0 macro + * @{ + */ +#define PSEQ_ICACHE_OVERRIDES3__OVERRIDE_ICACHE_ISO_VAL__SHIFT 0 +#define PSEQ_ICACHE_OVERRIDES3__OVERRIDE_ICACHE_ISO_VAL__WIDTH 4 +#define PSEQ_ICACHE_OVERRIDES3__OVERRIDE_ICACHE_ISO_VAL__MASK 0x0000000fU +#define PSEQ_ICACHE_OVERRIDES3__OVERRIDE_ICACHE_ISO_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES3__OVERRIDE_ICACHE_ISO_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES3__OVERRIDE_ICACHE_ISO_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES3__OVERRIDE_ICACHE_ISO_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define PSEQ_ICACHE_OVERRIDES3__OVERRIDE_ICACHE_ISO_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_icache_iso */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_icache_iso_field override_icache_iso_field + * @brief macros for field override_icache_iso + * @details If set, software now has direct control of cpu icache's isolation signals. [15] data1 macro [14] data0 macro [13] tag1 macro [12] tag0 macro + * @{ + */ +#define PSEQ_ICACHE_OVERRIDES3__OVERRIDE_ICACHE_ISO__SHIFT 12 +#define PSEQ_ICACHE_OVERRIDES3__OVERRIDE_ICACHE_ISO__WIDTH 4 +#define PSEQ_ICACHE_OVERRIDES3__OVERRIDE_ICACHE_ISO__MASK 0x0000f000U +#define PSEQ_ICACHE_OVERRIDES3__OVERRIDE_ICACHE_ISO__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f000U) >> 12) +#define PSEQ_ICACHE_OVERRIDES3__OVERRIDE_ICACHE_ISO__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0000f000U) +#define PSEQ_ICACHE_OVERRIDES3__OVERRIDE_ICACHE_ISO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((uint32_t)(src) <<\ + 12) & 0x0000f000U) +#define PSEQ_ICACHE_OVERRIDES3__OVERRIDE_ICACHE_ISO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0000f000U))) +#define PSEQ_ICACHE_OVERRIDES3__OVERRIDE_ICACHE_ISO__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_ICACHE_OVERRIDES3__TYPE uint32_t +#define PSEQ_ICACHE_OVERRIDES3__READ 0x0000f00fU +#define PSEQ_ICACHE_OVERRIDES3__WRITE 0x0000f00fU +#define PSEQ_ICACHE_OVERRIDES3__PRESERVED 0x00000000U +#define PSEQ_ICACHE_OVERRIDES3__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_ICACHE_OVERRIDES3_MACRO__ */ + +/** @} end of icache_overrides3 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_icache_overrides4 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_icache_overrides4 icache_overrides4 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_ICACHE_OVERRIDES4_MACRO__ +#define __PSEQ_ICACHE_OVERRIDES4_MACRO__ + +/* macros for field override_icache_ls_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_icache_ls_val_field override_icache_ls_val_field + * @brief macros for field override_icache_ls_val + * @details If override is set, what is state of cpu icache's LS signals? [3] data1 macro [2] data0 macro [1] tag1 macro [0] tag0 macro + * @{ + */ +#define PSEQ_ICACHE_OVERRIDES4__OVERRIDE_ICACHE_LS_VAL__SHIFT 0 +#define PSEQ_ICACHE_OVERRIDES4__OVERRIDE_ICACHE_LS_VAL__WIDTH 4 +#define PSEQ_ICACHE_OVERRIDES4__OVERRIDE_ICACHE_LS_VAL__MASK 0x0000000fU +#define PSEQ_ICACHE_OVERRIDES4__OVERRIDE_ICACHE_LS_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES4__OVERRIDE_ICACHE_LS_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES4__OVERRIDE_ICACHE_LS_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES4__OVERRIDE_ICACHE_LS_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define PSEQ_ICACHE_OVERRIDES4__OVERRIDE_ICACHE_LS_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_icache_ls */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_icache_ls_field override_icache_ls_field + * @brief macros for field override_icache_ls + * @details If set, software now has direct control of cpu icache's LS signals. [15] data1 macro [14] data0 macro [13] tag1 macro [12] tag0 macro + * @{ + */ +#define PSEQ_ICACHE_OVERRIDES4__OVERRIDE_ICACHE_LS__SHIFT 12 +#define PSEQ_ICACHE_OVERRIDES4__OVERRIDE_ICACHE_LS__WIDTH 4 +#define PSEQ_ICACHE_OVERRIDES4__OVERRIDE_ICACHE_LS__MASK 0x0000f000U +#define PSEQ_ICACHE_OVERRIDES4__OVERRIDE_ICACHE_LS__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f000U) >> 12) +#define PSEQ_ICACHE_OVERRIDES4__OVERRIDE_ICACHE_LS__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0000f000U) +#define PSEQ_ICACHE_OVERRIDES4__OVERRIDE_ICACHE_LS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((uint32_t)(src) <<\ + 12) & 0x0000f000U) +#define PSEQ_ICACHE_OVERRIDES4__OVERRIDE_ICACHE_LS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0000f000U))) +#define PSEQ_ICACHE_OVERRIDES4__OVERRIDE_ICACHE_LS__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_ICACHE_OVERRIDES4__TYPE uint32_t +#define PSEQ_ICACHE_OVERRIDES4__READ 0x0000f00fU +#define PSEQ_ICACHE_OVERRIDES4__WRITE 0x0000f00fU +#define PSEQ_ICACHE_OVERRIDES4__PRESERVED 0x00000000U +#define PSEQ_ICACHE_OVERRIDES4__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_ICACHE_OVERRIDES4_MACRO__ */ + +/** @} end of icache_overrides4 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_icache_overrides5 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_icache_overrides5 icache_overrides5 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_ICACHE_OVERRIDES5_MACRO__ +#define __PSEQ_ICACHE_OVERRIDES5_MACRO__ + +/* macros for field override_icache_ds_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_icache_ds_val_field override_icache_ds_val_field + * @brief macros for field override_icache_ds_val + * @details If override is set, what is state of cpu icache's DS signals? [3] data1 macro [2] data0 macro [1] tag1 macro [0] tag0 macro + * @{ + */ +#define PSEQ_ICACHE_OVERRIDES5__OVERRIDE_ICACHE_DS_VAL__SHIFT 0 +#define PSEQ_ICACHE_OVERRIDES5__OVERRIDE_ICACHE_DS_VAL__WIDTH 4 +#define PSEQ_ICACHE_OVERRIDES5__OVERRIDE_ICACHE_DS_VAL__MASK 0x0000000fU +#define PSEQ_ICACHE_OVERRIDES5__OVERRIDE_ICACHE_DS_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES5__OVERRIDE_ICACHE_DS_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES5__OVERRIDE_ICACHE_DS_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES5__OVERRIDE_ICACHE_DS_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define PSEQ_ICACHE_OVERRIDES5__OVERRIDE_ICACHE_DS_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_icache_ds */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_icache_ds_field override_icache_ds_field + * @brief macros for field override_icache_ds + * @details If set, software now has direct control of cpu icache's DS signals. [15] data1 macro [14] data0 macro [13] tag1 macro [12] tag0 macro + * @{ + */ +#define PSEQ_ICACHE_OVERRIDES5__OVERRIDE_ICACHE_DS__SHIFT 12 +#define PSEQ_ICACHE_OVERRIDES5__OVERRIDE_ICACHE_DS__WIDTH 4 +#define PSEQ_ICACHE_OVERRIDES5__OVERRIDE_ICACHE_DS__MASK 0x0000f000U +#define PSEQ_ICACHE_OVERRIDES5__OVERRIDE_ICACHE_DS__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f000U) >> 12) +#define PSEQ_ICACHE_OVERRIDES5__OVERRIDE_ICACHE_DS__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0000f000U) +#define PSEQ_ICACHE_OVERRIDES5__OVERRIDE_ICACHE_DS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((uint32_t)(src) <<\ + 12) & 0x0000f000U) +#define PSEQ_ICACHE_OVERRIDES5__OVERRIDE_ICACHE_DS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0000f000U))) +#define PSEQ_ICACHE_OVERRIDES5__OVERRIDE_ICACHE_DS__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_ICACHE_OVERRIDES5__TYPE uint32_t +#define PSEQ_ICACHE_OVERRIDES5__READ 0x0000f00fU +#define PSEQ_ICACHE_OVERRIDES5__WRITE 0x0000f00fU +#define PSEQ_ICACHE_OVERRIDES5__PRESERVED 0x00000000U +#define PSEQ_ICACHE_OVERRIDES5__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_ICACHE_OVERRIDES5_MACRO__ */ + +/** @} end of icache_overrides5 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_icache_overrides6 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_icache_overrides6 icache_overrides6 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_ICACHE_OVERRIDES6_MACRO__ +#define __PSEQ_ICACHE_OVERRIDES6_MACRO__ + +/* macros for field override_icache_sd_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_icache_sd_val_field override_icache_sd_val_field + * @brief macros for field override_icache_sd_val + * @details If override is set, what is state of cpu icache's SD signals? [3] data1 macro [2] data0 macro [1] tag1 macro [0] tag0 macro + * @{ + */ +#define PSEQ_ICACHE_OVERRIDES6__OVERRIDE_ICACHE_SD_VAL__SHIFT 0 +#define PSEQ_ICACHE_OVERRIDES6__OVERRIDE_ICACHE_SD_VAL__WIDTH 4 +#define PSEQ_ICACHE_OVERRIDES6__OVERRIDE_ICACHE_SD_VAL__MASK 0x0000000fU +#define PSEQ_ICACHE_OVERRIDES6__OVERRIDE_ICACHE_SD_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES6__OVERRIDE_ICACHE_SD_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES6__OVERRIDE_ICACHE_SD_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES6__OVERRIDE_ICACHE_SD_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define PSEQ_ICACHE_OVERRIDES6__OVERRIDE_ICACHE_SD_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_icache_sd */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_icache_sd_field override_icache_sd_field + * @brief macros for field override_icache_sd + * @details If set, software now has direct control of cpu icache's SD signals. [15] data1 macro [14] data0 macro [13] tag1 macro [12] tag0 macro + * @{ + */ +#define PSEQ_ICACHE_OVERRIDES6__OVERRIDE_ICACHE_SD__SHIFT 12 +#define PSEQ_ICACHE_OVERRIDES6__OVERRIDE_ICACHE_SD__WIDTH 4 +#define PSEQ_ICACHE_OVERRIDES6__OVERRIDE_ICACHE_SD__MASK 0x0000f000U +#define PSEQ_ICACHE_OVERRIDES6__OVERRIDE_ICACHE_SD__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f000U) >> 12) +#define PSEQ_ICACHE_OVERRIDES6__OVERRIDE_ICACHE_SD__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0000f000U) +#define PSEQ_ICACHE_OVERRIDES6__OVERRIDE_ICACHE_SD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((uint32_t)(src) <<\ + 12) & 0x0000f000U) +#define PSEQ_ICACHE_OVERRIDES6__OVERRIDE_ICACHE_SD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0000f000U))) +#define PSEQ_ICACHE_OVERRIDES6__OVERRIDE_ICACHE_SD__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_ICACHE_OVERRIDES6__TYPE uint32_t +#define PSEQ_ICACHE_OVERRIDES6__READ 0x0000f00fU +#define PSEQ_ICACHE_OVERRIDES6__WRITE 0x0000f00fU +#define PSEQ_ICACHE_OVERRIDES6__PRESERVED 0x00000000U +#define PSEQ_ICACHE_OVERRIDES6__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_ICACHE_OVERRIDES6_MACRO__ */ + +/** @} end of icache_overrides6 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_icache_overrides7 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_icache_overrides7 icache_overrides7 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_ICACHE_OVERRIDES7_MACRO__ +#define __PSEQ_ICACHE_OVERRIDES7_MACRO__ + +/* macros for field block_icache_vddcut */ +/** + * @defgroup at_apb_pseq_paris_regs_core_block_icache_vddcut_field block_icache_vddcut_field + * @brief macros for field block_icache_vddcut + * @details Block core's FSM from cutting the vdd supplies to the icache. [3] data1 macro [2] data0 macro [1] tag1 macro [0] tag0 macro + * @{ + */ +#define PSEQ_ICACHE_OVERRIDES7__BLOCK_ICACHE_VDDCUT__SHIFT 0 +#define PSEQ_ICACHE_OVERRIDES7__BLOCK_ICACHE_VDDCUT__WIDTH 4 +#define PSEQ_ICACHE_OVERRIDES7__BLOCK_ICACHE_VDDCUT__MASK 0x0000000fU +#define PSEQ_ICACHE_OVERRIDES7__BLOCK_ICACHE_VDDCUT__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES7__BLOCK_ICACHE_VDDCUT__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES7__BLOCK_ICACHE_VDDCUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES7__BLOCK_ICACHE_VDDCUT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define PSEQ_ICACHE_OVERRIDES7__BLOCK_ICACHE_VDDCUT__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_ICACHE_OVERRIDES7__TYPE uint32_t +#define PSEQ_ICACHE_OVERRIDES7__READ 0x0000000fU +#define PSEQ_ICACHE_OVERRIDES7__WRITE 0x0000000fU +#define PSEQ_ICACHE_OVERRIDES7__PRESERVED 0x00000000U +#define PSEQ_ICACHE_OVERRIDES7__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_ICACHE_OVERRIDES7_MACRO__ */ + +/** @} end of icache_overrides7 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_icache_overrides8 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_icache_overrides8 icache_overrides8 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_ICACHE_OVERRIDES8_MACRO__ +#define __PSEQ_ICACHE_OVERRIDES8_MACRO__ + +/* macros for field block_icache_sd */ +/** + * @defgroup at_apb_pseq_paris_regs_core_block_icache_sd_field block_icache_sd_field + * @brief macros for field block_icache_sd + * @details Block core's FSM from setting the SD signal to the icache. [3] data1 macro [2] data0 macro [1] tag1 macro [0] tag0 macro + * @{ + */ +#define PSEQ_ICACHE_OVERRIDES8__BLOCK_ICACHE_SD__SHIFT 0 +#define PSEQ_ICACHE_OVERRIDES8__BLOCK_ICACHE_SD__WIDTH 4 +#define PSEQ_ICACHE_OVERRIDES8__BLOCK_ICACHE_SD__MASK 0x0000000fU +#define PSEQ_ICACHE_OVERRIDES8__BLOCK_ICACHE_SD__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES8__BLOCK_ICACHE_SD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES8__BLOCK_ICACHE_SD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define PSEQ_ICACHE_OVERRIDES8__BLOCK_ICACHE_SD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define PSEQ_ICACHE_OVERRIDES8__BLOCK_ICACHE_SD__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_ICACHE_OVERRIDES8__TYPE uint32_t +#define PSEQ_ICACHE_OVERRIDES8__READ 0x0000000fU +#define PSEQ_ICACHE_OVERRIDES8__WRITE 0x0000000fU +#define PSEQ_ICACHE_OVERRIDES8__PRESERVED 0x00000000U +#define PSEQ_ICACHE_OVERRIDES8__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_ICACHE_OVERRIDES8_MACRO__ */ + +/** @} end of icache_overrides8 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_rramcache_overrides */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rramcache_overrides rramcache_overrides + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_RRAMCACHE_OVERRIDES_MACRO__ +#define __PSEQ_RRAMCACHE_OVERRIDES_MACRO__ + +/* macros for field override_rramcache_vddcut_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rramcache_vddcut_val_field override_rramcache_vddcut_val_field + * @brief macros for field override_rramcache_vddcut_val + * @details If override is set, what is state of cpu rram cache's's head switches? [5] data1 macro; [1] head switch open [0] head switch close [4] data0 macro; [1] head switch open [0] head switch close [3] tag3 macro; [1] head switch open [0] head switch close [2] tag2 macro; [1] head switch open [0] head switch close [1] tag1 macro; [1] head switch open [0] head switch close [0] tag0 macro; [1] head switch open [0] head switch close + * @{ + */ +#define PSEQ_RRAMCACHE_OVERRIDES__OVERRIDE_RRAMCACHE_VDDCUT_VAL__SHIFT 0 +#define PSEQ_RRAMCACHE_OVERRIDES__OVERRIDE_RRAMCACHE_VDDCUT_VAL__WIDTH 6 +#define PSEQ_RRAMCACHE_OVERRIDES__OVERRIDE_RRAMCACHE_VDDCUT_VAL__MASK \ + 0x0000003fU +#define PSEQ_RRAMCACHE_OVERRIDES__OVERRIDE_RRAMCACHE_VDDCUT_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define PSEQ_RRAMCACHE_OVERRIDES__OVERRIDE_RRAMCACHE_VDDCUT_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define PSEQ_RRAMCACHE_OVERRIDES__OVERRIDE_RRAMCACHE_VDDCUT_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define PSEQ_RRAMCACHE_OVERRIDES__OVERRIDE_RRAMCACHE_VDDCUT_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define PSEQ_RRAMCACHE_OVERRIDES__OVERRIDE_RRAMCACHE_VDDCUT_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_rramcache_vddcut */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rramcache_vddcut_field override_rramcache_vddcut_field + * @brief macros for field override_rramcache_vddcut + * @details If set, software now has direct control of cpu rram cache's head switches. [17] data1 macro [16] data0 macro [15] tag3 macro [14] tag2 macro [13] tag1 macro [12] tag0 macro + * @{ + */ +#define PSEQ_RRAMCACHE_OVERRIDES__OVERRIDE_RRAMCACHE_VDDCUT__SHIFT 12 +#define PSEQ_RRAMCACHE_OVERRIDES__OVERRIDE_RRAMCACHE_VDDCUT__WIDTH 6 +#define PSEQ_RRAMCACHE_OVERRIDES__OVERRIDE_RRAMCACHE_VDDCUT__MASK 0x0003f000U +#define PSEQ_RRAMCACHE_OVERRIDES__OVERRIDE_RRAMCACHE_VDDCUT__READ(src) \ + (((uint32_t)(src)\ + & 0x0003f000U) >> 12) +#define PSEQ_RRAMCACHE_OVERRIDES__OVERRIDE_RRAMCACHE_VDDCUT__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0003f000U) +#define PSEQ_RRAMCACHE_OVERRIDES__OVERRIDE_RRAMCACHE_VDDCUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((uint32_t)(src) <<\ + 12) & 0x0003f000U) +#define PSEQ_RRAMCACHE_OVERRIDES__OVERRIDE_RRAMCACHE_VDDCUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0003f000U))) +#define PSEQ_RRAMCACHE_OVERRIDES__OVERRIDE_RRAMCACHE_VDDCUT__RESET_VALUE \ + 0x00000000U +/** @} */ +#define PSEQ_RRAMCACHE_OVERRIDES__TYPE uint32_t +#define PSEQ_RRAMCACHE_OVERRIDES__READ 0x0003f03fU +#define PSEQ_RRAMCACHE_OVERRIDES__WRITE 0x0003f03fU +#define PSEQ_RRAMCACHE_OVERRIDES__PRESERVED 0x00000000U +#define PSEQ_RRAMCACHE_OVERRIDES__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_RRAMCACHE_OVERRIDES_MACRO__ */ + +/** @} end of rramcache_overrides */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_rramcache_overrides2 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rramcache_overrides2 rramcache_overrides2 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_RRAMCACHE_OVERRIDES2_MACRO__ +#define __PSEQ_RRAMCACHE_OVERRIDES2_MACRO__ + +/* macros for field override_rramcache_clken_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rramcache_clken_val_field override_rramcache_clken_val_field + * @brief macros for field override_rramcache_clken_val + * @details If override is set, what is state of cpu rram cache's clock enable signals? [5] data1 macro [4] data0 macro [3] tag3 macro [2] tag2 macro [1] tag1 macro [0] tag0 macro + * @{ + */ +#define PSEQ_RRAMCACHE_OVERRIDES2__OVERRIDE_RRAMCACHE_CLKEN_VAL__SHIFT 0 +#define PSEQ_RRAMCACHE_OVERRIDES2__OVERRIDE_RRAMCACHE_CLKEN_VAL__WIDTH 6 +#define PSEQ_RRAMCACHE_OVERRIDES2__OVERRIDE_RRAMCACHE_CLKEN_VAL__MASK \ + 0x0000003fU +#define PSEQ_RRAMCACHE_OVERRIDES2__OVERRIDE_RRAMCACHE_CLKEN_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define PSEQ_RRAMCACHE_OVERRIDES2__OVERRIDE_RRAMCACHE_CLKEN_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define PSEQ_RRAMCACHE_OVERRIDES2__OVERRIDE_RRAMCACHE_CLKEN_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define PSEQ_RRAMCACHE_OVERRIDES2__OVERRIDE_RRAMCACHE_CLKEN_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define PSEQ_RRAMCACHE_OVERRIDES2__OVERRIDE_RRAMCACHE_CLKEN_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_rramcache_clken */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rramcache_clken_field override_rramcache_clken_field + * @brief macros for field override_rramcache_clken + * @details If set, software now has direct control of cpu rram cache's clock enable signals. [17] data1 macro [16] data0 macro [15] tag3 macro [14] tag2 macro [13] tag1 macro [12] tag0 macro + * @{ + */ +#define PSEQ_RRAMCACHE_OVERRIDES2__OVERRIDE_RRAMCACHE_CLKEN__SHIFT 12 +#define PSEQ_RRAMCACHE_OVERRIDES2__OVERRIDE_RRAMCACHE_CLKEN__WIDTH 6 +#define PSEQ_RRAMCACHE_OVERRIDES2__OVERRIDE_RRAMCACHE_CLKEN__MASK 0x0003f000U +#define PSEQ_RRAMCACHE_OVERRIDES2__OVERRIDE_RRAMCACHE_CLKEN__READ(src) \ + (((uint32_t)(src)\ + & 0x0003f000U) >> 12) +#define PSEQ_RRAMCACHE_OVERRIDES2__OVERRIDE_RRAMCACHE_CLKEN__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0003f000U) +#define PSEQ_RRAMCACHE_OVERRIDES2__OVERRIDE_RRAMCACHE_CLKEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((uint32_t)(src) <<\ + 12) & 0x0003f000U) +#define PSEQ_RRAMCACHE_OVERRIDES2__OVERRIDE_RRAMCACHE_CLKEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0003f000U))) +#define PSEQ_RRAMCACHE_OVERRIDES2__OVERRIDE_RRAMCACHE_CLKEN__RESET_VALUE \ + 0x00000000U +/** @} */ +#define PSEQ_RRAMCACHE_OVERRIDES2__TYPE uint32_t +#define PSEQ_RRAMCACHE_OVERRIDES2__READ 0x0003f03fU +#define PSEQ_RRAMCACHE_OVERRIDES2__WRITE 0x0003f03fU +#define PSEQ_RRAMCACHE_OVERRIDES2__PRESERVED 0x00000000U +#define PSEQ_RRAMCACHE_OVERRIDES2__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_RRAMCACHE_OVERRIDES2_MACRO__ */ + +/** @} end of rramcache_overrides2 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_rramcache_overrides3 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rramcache_overrides3 rramcache_overrides3 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_RRAMCACHE_OVERRIDES3_MACRO__ +#define __PSEQ_RRAMCACHE_OVERRIDES3_MACRO__ + +/* macros for field override_rramcache_iso_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rramcache_iso_val_field override_rramcache_iso_val_field + * @brief macros for field override_rramcache_iso_val + * @details If override is set, what is state of cpu rram cache's isolation signals? [5] data1 macro [4] data0 macro [3] tag3 macro [2] tag2 macro [1] tag1 macro [0] tag0 macro + * @{ + */ +#define PSEQ_RRAMCACHE_OVERRIDES3__OVERRIDE_RRAMCACHE_ISO_VAL__SHIFT 0 +#define PSEQ_RRAMCACHE_OVERRIDES3__OVERRIDE_RRAMCACHE_ISO_VAL__WIDTH 6 +#define PSEQ_RRAMCACHE_OVERRIDES3__OVERRIDE_RRAMCACHE_ISO_VAL__MASK 0x0000003fU +#define PSEQ_RRAMCACHE_OVERRIDES3__OVERRIDE_RRAMCACHE_ISO_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define PSEQ_RRAMCACHE_OVERRIDES3__OVERRIDE_RRAMCACHE_ISO_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define PSEQ_RRAMCACHE_OVERRIDES3__OVERRIDE_RRAMCACHE_ISO_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define PSEQ_RRAMCACHE_OVERRIDES3__OVERRIDE_RRAMCACHE_ISO_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define PSEQ_RRAMCACHE_OVERRIDES3__OVERRIDE_RRAMCACHE_ISO_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_rramcache_iso */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rramcache_iso_field override_rramcache_iso_field + * @brief macros for field override_rramcache_iso + * @details If set, software now has direct control of cpu rram cache's isolation signals. [17] data1 macro [16] data0 macro [15] tag3 macro [14] tag2 macro [13] tag1 macro [12] tag0 macro + * @{ + */ +#define PSEQ_RRAMCACHE_OVERRIDES3__OVERRIDE_RRAMCACHE_ISO__SHIFT 12 +#define PSEQ_RRAMCACHE_OVERRIDES3__OVERRIDE_RRAMCACHE_ISO__WIDTH 6 +#define PSEQ_RRAMCACHE_OVERRIDES3__OVERRIDE_RRAMCACHE_ISO__MASK 0x0003f000U +#define PSEQ_RRAMCACHE_OVERRIDES3__OVERRIDE_RRAMCACHE_ISO__READ(src) \ + (((uint32_t)(src)\ + & 0x0003f000U) >> 12) +#define PSEQ_RRAMCACHE_OVERRIDES3__OVERRIDE_RRAMCACHE_ISO__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0003f000U) +#define PSEQ_RRAMCACHE_OVERRIDES3__OVERRIDE_RRAMCACHE_ISO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((uint32_t)(src) <<\ + 12) & 0x0003f000U) +#define PSEQ_RRAMCACHE_OVERRIDES3__OVERRIDE_RRAMCACHE_ISO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0003f000U))) +#define PSEQ_RRAMCACHE_OVERRIDES3__OVERRIDE_RRAMCACHE_ISO__RESET_VALUE \ + 0x00000000U +/** @} */ +#define PSEQ_RRAMCACHE_OVERRIDES3__TYPE uint32_t +#define PSEQ_RRAMCACHE_OVERRIDES3__READ 0x0003f03fU +#define PSEQ_RRAMCACHE_OVERRIDES3__WRITE 0x0003f03fU +#define PSEQ_RRAMCACHE_OVERRIDES3__PRESERVED 0x00000000U +#define PSEQ_RRAMCACHE_OVERRIDES3__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_RRAMCACHE_OVERRIDES3_MACRO__ */ + +/** @} end of rramcache_overrides3 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_rramcache_overrides4 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rramcache_overrides4 rramcache_overrides4 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_RRAMCACHE_OVERRIDES4_MACRO__ +#define __PSEQ_RRAMCACHE_OVERRIDES4_MACRO__ + +/* macros for field override_rramcache_ls_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rramcache_ls_val_field override_rramcache_ls_val_field + * @brief macros for field override_rramcache_ls_val + * @details If override is set, what is state of cpu rram cache's LS signals? [5] data1 macro [4] data0 macro [3] tag3 macro [2] tag2 macro [1] tag1 macro [0] tag0 macro + * @{ + */ +#define PSEQ_RRAMCACHE_OVERRIDES4__OVERRIDE_RRAMCACHE_LS_VAL__SHIFT 0 +#define PSEQ_RRAMCACHE_OVERRIDES4__OVERRIDE_RRAMCACHE_LS_VAL__WIDTH 6 +#define PSEQ_RRAMCACHE_OVERRIDES4__OVERRIDE_RRAMCACHE_LS_VAL__MASK 0x0000003fU +#define PSEQ_RRAMCACHE_OVERRIDES4__OVERRIDE_RRAMCACHE_LS_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define PSEQ_RRAMCACHE_OVERRIDES4__OVERRIDE_RRAMCACHE_LS_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define PSEQ_RRAMCACHE_OVERRIDES4__OVERRIDE_RRAMCACHE_LS_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define PSEQ_RRAMCACHE_OVERRIDES4__OVERRIDE_RRAMCACHE_LS_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define PSEQ_RRAMCACHE_OVERRIDES4__OVERRIDE_RRAMCACHE_LS_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_rramcache_ls */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rramcache_ls_field override_rramcache_ls_field + * @brief macros for field override_rramcache_ls + * @details If set, software now has direct control of cpu rram cache's LS signals. [17] data1 macro [16] data0 macro [15] tag3 macro [14] tag2 macro [13] tag1 macro [12] tag0 macro + * @{ + */ +#define PSEQ_RRAMCACHE_OVERRIDES4__OVERRIDE_RRAMCACHE_LS__SHIFT 12 +#define PSEQ_RRAMCACHE_OVERRIDES4__OVERRIDE_RRAMCACHE_LS__WIDTH 6 +#define PSEQ_RRAMCACHE_OVERRIDES4__OVERRIDE_RRAMCACHE_LS__MASK 0x0003f000U +#define PSEQ_RRAMCACHE_OVERRIDES4__OVERRIDE_RRAMCACHE_LS__READ(src) \ + (((uint32_t)(src)\ + & 0x0003f000U) >> 12) +#define PSEQ_RRAMCACHE_OVERRIDES4__OVERRIDE_RRAMCACHE_LS__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0003f000U) +#define PSEQ_RRAMCACHE_OVERRIDES4__OVERRIDE_RRAMCACHE_LS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((uint32_t)(src) <<\ + 12) & 0x0003f000U) +#define PSEQ_RRAMCACHE_OVERRIDES4__OVERRIDE_RRAMCACHE_LS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0003f000U))) +#define PSEQ_RRAMCACHE_OVERRIDES4__OVERRIDE_RRAMCACHE_LS__RESET_VALUE \ + 0x00000000U +/** @} */ +#define PSEQ_RRAMCACHE_OVERRIDES4__TYPE uint32_t +#define PSEQ_RRAMCACHE_OVERRIDES4__READ 0x0003f03fU +#define PSEQ_RRAMCACHE_OVERRIDES4__WRITE 0x0003f03fU +#define PSEQ_RRAMCACHE_OVERRIDES4__PRESERVED 0x00000000U +#define PSEQ_RRAMCACHE_OVERRIDES4__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_RRAMCACHE_OVERRIDES4_MACRO__ */ + +/** @} end of rramcache_overrides4 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_rramcache_overrides5 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rramcache_overrides5 rramcache_overrides5 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_RRAMCACHE_OVERRIDES5_MACRO__ +#define __PSEQ_RRAMCACHE_OVERRIDES5_MACRO__ + +/* macros for field override_rramcache_ds_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rramcache_ds_val_field override_rramcache_ds_val_field + * @brief macros for field override_rramcache_ds_val + * @details If override is set, what is state of cpu rram cache's DS signals? [5] data1 macro [4] data0 macro + * @{ + */ +#define PSEQ_RRAMCACHE_OVERRIDES5__OVERRIDE_RRAMCACHE_DS_VAL__SHIFT 4 +#define PSEQ_RRAMCACHE_OVERRIDES5__OVERRIDE_RRAMCACHE_DS_VAL__WIDTH 2 +#define PSEQ_RRAMCACHE_OVERRIDES5__OVERRIDE_RRAMCACHE_DS_VAL__MASK 0x00000030U +#define PSEQ_RRAMCACHE_OVERRIDES5__OVERRIDE_RRAMCACHE_DS_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000030U) >> 4) +#define PSEQ_RRAMCACHE_OVERRIDES5__OVERRIDE_RRAMCACHE_DS_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000030U) +#define PSEQ_RRAMCACHE_OVERRIDES5__OVERRIDE_RRAMCACHE_DS_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((uint32_t)(src) <<\ + 4) & 0x00000030U) +#define PSEQ_RRAMCACHE_OVERRIDES5__OVERRIDE_RRAMCACHE_DS_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000030U))) +#define PSEQ_RRAMCACHE_OVERRIDES5__OVERRIDE_RRAMCACHE_DS_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_rramcache_ds */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rramcache_ds_field override_rramcache_ds_field + * @brief macros for field override_rramcache_ds + * @details If set, software now has direct control of cpu rram cache's DS signals. [17] data1 macro [16] data0 macro + * @{ + */ +#define PSEQ_RRAMCACHE_OVERRIDES5__OVERRIDE_RRAMCACHE_DS__SHIFT 16 +#define PSEQ_RRAMCACHE_OVERRIDES5__OVERRIDE_RRAMCACHE_DS__WIDTH 2 +#define PSEQ_RRAMCACHE_OVERRIDES5__OVERRIDE_RRAMCACHE_DS__MASK 0x00030000U +#define PSEQ_RRAMCACHE_OVERRIDES5__OVERRIDE_RRAMCACHE_DS__READ(src) \ + (((uint32_t)(src)\ + & 0x00030000U) >> 16) +#define PSEQ_RRAMCACHE_OVERRIDES5__OVERRIDE_RRAMCACHE_DS__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00030000U) +#define PSEQ_RRAMCACHE_OVERRIDES5__OVERRIDE_RRAMCACHE_DS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00030000U) | (((uint32_t)(src) <<\ + 16) & 0x00030000U) +#define PSEQ_RRAMCACHE_OVERRIDES5__OVERRIDE_RRAMCACHE_DS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00030000U))) +#define PSEQ_RRAMCACHE_OVERRIDES5__OVERRIDE_RRAMCACHE_DS__RESET_VALUE \ + 0x00000000U +/** @} */ +#define PSEQ_RRAMCACHE_OVERRIDES5__TYPE uint32_t +#define PSEQ_RRAMCACHE_OVERRIDES5__READ 0x00030030U +#define PSEQ_RRAMCACHE_OVERRIDES5__WRITE 0x00030030U +#define PSEQ_RRAMCACHE_OVERRIDES5__PRESERVED 0x00000000U +#define PSEQ_RRAMCACHE_OVERRIDES5__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_RRAMCACHE_OVERRIDES5_MACRO__ */ + +/** @} end of rramcache_overrides5 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_rramcache_overrides6 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rramcache_overrides6 rramcache_overrides6 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_RRAMCACHE_OVERRIDES6_MACRO__ +#define __PSEQ_RRAMCACHE_OVERRIDES6_MACRO__ + +/* macros for field override_rramcache_sd_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rramcache_sd_val_field override_rramcache_sd_val_field + * @brief macros for field override_rramcache_sd_val + * @details If override is set, what is state of cpu rram cache's SD signals? [5] data1 macro [4] data0 macro + * @{ + */ +#define PSEQ_RRAMCACHE_OVERRIDES6__OVERRIDE_RRAMCACHE_SD_VAL__SHIFT 4 +#define PSEQ_RRAMCACHE_OVERRIDES6__OVERRIDE_RRAMCACHE_SD_VAL__WIDTH 2 +#define PSEQ_RRAMCACHE_OVERRIDES6__OVERRIDE_RRAMCACHE_SD_VAL__MASK 0x00000030U +#define PSEQ_RRAMCACHE_OVERRIDES6__OVERRIDE_RRAMCACHE_SD_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000030U) >> 4) +#define PSEQ_RRAMCACHE_OVERRIDES6__OVERRIDE_RRAMCACHE_SD_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000030U) +#define PSEQ_RRAMCACHE_OVERRIDES6__OVERRIDE_RRAMCACHE_SD_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((uint32_t)(src) <<\ + 4) & 0x00000030U) +#define PSEQ_RRAMCACHE_OVERRIDES6__OVERRIDE_RRAMCACHE_SD_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000030U))) +#define PSEQ_RRAMCACHE_OVERRIDES6__OVERRIDE_RRAMCACHE_SD_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_rramcache_sd */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_rramcache_sd_field override_rramcache_sd_field + * @brief macros for field override_rramcache_sd + * @details If set, software now has direct control of cpu rram cache's SD signals. [17] data1 macro [16] data0 macro + * @{ + */ +#define PSEQ_RRAMCACHE_OVERRIDES6__OVERRIDE_RRAMCACHE_SD__SHIFT 16 +#define PSEQ_RRAMCACHE_OVERRIDES6__OVERRIDE_RRAMCACHE_SD__WIDTH 2 +#define PSEQ_RRAMCACHE_OVERRIDES6__OVERRIDE_RRAMCACHE_SD__MASK 0x00030000U +#define PSEQ_RRAMCACHE_OVERRIDES6__OVERRIDE_RRAMCACHE_SD__READ(src) \ + (((uint32_t)(src)\ + & 0x00030000U) >> 16) +#define PSEQ_RRAMCACHE_OVERRIDES6__OVERRIDE_RRAMCACHE_SD__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00030000U) +#define PSEQ_RRAMCACHE_OVERRIDES6__OVERRIDE_RRAMCACHE_SD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00030000U) | (((uint32_t)(src) <<\ + 16) & 0x00030000U) +#define PSEQ_RRAMCACHE_OVERRIDES6__OVERRIDE_RRAMCACHE_SD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00030000U))) +#define PSEQ_RRAMCACHE_OVERRIDES6__OVERRIDE_RRAMCACHE_SD__RESET_VALUE \ + 0x00000000U +/** @} */ +#define PSEQ_RRAMCACHE_OVERRIDES6__TYPE uint32_t +#define PSEQ_RRAMCACHE_OVERRIDES6__READ 0x00030030U +#define PSEQ_RRAMCACHE_OVERRIDES6__WRITE 0x00030030U +#define PSEQ_RRAMCACHE_OVERRIDES6__PRESERVED 0x00000000U +#define PSEQ_RRAMCACHE_OVERRIDES6__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_RRAMCACHE_OVERRIDES6_MACRO__ */ + +/** @} end of rramcache_overrides6 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_rramcache_overrides7 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rramcache_overrides7 rramcache_overrides7 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_RRAMCACHE_OVERRIDES7_MACRO__ +#define __PSEQ_RRAMCACHE_OVERRIDES7_MACRO__ + +/* macros for field block_rramcache_vddcut */ +/** + * @defgroup at_apb_pseq_paris_regs_core_block_rramcache_vddcut_field block_rramcache_vddcut_field + * @brief macros for field block_rramcache_vddcut + * @details Block core's FSM from cutting the vdd supplies to the rram cache. [5] data1 macro [4] data0 macro [3] tag3 macro [2] tag2 macro [1] tag1 macro [0] tag0 macro + * @{ + */ +#define PSEQ_RRAMCACHE_OVERRIDES7__BLOCK_RRAMCACHE_VDDCUT__SHIFT 0 +#define PSEQ_RRAMCACHE_OVERRIDES7__BLOCK_RRAMCACHE_VDDCUT__WIDTH 6 +#define PSEQ_RRAMCACHE_OVERRIDES7__BLOCK_RRAMCACHE_VDDCUT__MASK 0x0000003fU +#define PSEQ_RRAMCACHE_OVERRIDES7__BLOCK_RRAMCACHE_VDDCUT__READ(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define PSEQ_RRAMCACHE_OVERRIDES7__BLOCK_RRAMCACHE_VDDCUT__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define PSEQ_RRAMCACHE_OVERRIDES7__BLOCK_RRAMCACHE_VDDCUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define PSEQ_RRAMCACHE_OVERRIDES7__BLOCK_RRAMCACHE_VDDCUT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define PSEQ_RRAMCACHE_OVERRIDES7__BLOCK_RRAMCACHE_VDDCUT__RESET_VALUE \ + 0x00000000U +/** @} */ +#define PSEQ_RRAMCACHE_OVERRIDES7__TYPE uint32_t +#define PSEQ_RRAMCACHE_OVERRIDES7__READ 0x0000003fU +#define PSEQ_RRAMCACHE_OVERRIDES7__WRITE 0x0000003fU +#define PSEQ_RRAMCACHE_OVERRIDES7__PRESERVED 0x00000000U +#define PSEQ_RRAMCACHE_OVERRIDES7__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_RRAMCACHE_OVERRIDES7_MACRO__ */ + +/** @} end of rramcache_overrides7 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_rramcache_overrides8 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rramcache_overrides8 rramcache_overrides8 + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_RRAMCACHE_OVERRIDES8_MACRO__ +#define __PSEQ_RRAMCACHE_OVERRIDES8_MACRO__ + +/* macros for field block_rramcache_sd */ +/** + * @defgroup at_apb_pseq_paris_regs_core_block_rramcache_sd_field block_rramcache_sd_field + * @brief macros for field block_rramcache_sd + * @details Block core's FSM from setting the SD signal to the rram cache. [5] data1 macro [4] data0 macro + * @{ + */ +#define PSEQ_RRAMCACHE_OVERRIDES8__BLOCK_RRAMCACHE_SD__SHIFT 4 +#define PSEQ_RRAMCACHE_OVERRIDES8__BLOCK_RRAMCACHE_SD__WIDTH 2 +#define PSEQ_RRAMCACHE_OVERRIDES8__BLOCK_RRAMCACHE_SD__MASK 0x00000030U +#define PSEQ_RRAMCACHE_OVERRIDES8__BLOCK_RRAMCACHE_SD__READ(src) \ + (((uint32_t)(src)\ + & 0x00000030U) >> 4) +#define PSEQ_RRAMCACHE_OVERRIDES8__BLOCK_RRAMCACHE_SD__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000030U) +#define PSEQ_RRAMCACHE_OVERRIDES8__BLOCK_RRAMCACHE_SD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((uint32_t)(src) <<\ + 4) & 0x00000030U) +#define PSEQ_RRAMCACHE_OVERRIDES8__BLOCK_RRAMCACHE_SD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000030U))) +#define PSEQ_RRAMCACHE_OVERRIDES8__BLOCK_RRAMCACHE_SD__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_RRAMCACHE_OVERRIDES8__TYPE uint32_t +#define PSEQ_RRAMCACHE_OVERRIDES8__READ 0x00000030U +#define PSEQ_RRAMCACHE_OVERRIDES8__WRITE 0x00000030U +#define PSEQ_RRAMCACHE_OVERRIDES8__PRESERVED 0x00000000U +#define PSEQ_RRAMCACHE_OVERRIDES8__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_RRAMCACHE_OVERRIDES8_MACRO__ */ + +/** @} end of rramcache_overrides8 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_qspicache_overrides */ +/** + * @defgroup at_apb_pseq_paris_regs_core_qspicache_overrides qspicache_overrides + * @brief override portion of pmu control signals definitions. + * @{ + */ +#ifndef __PSEQ_QSPICACHE_OVERRIDES_MACRO__ +#define __PSEQ_QSPICACHE_OVERRIDES_MACRO__ + +/* macros for field block_qspicache_sd */ +/** + * @defgroup at_apb_pseq_paris_regs_core_block_qspicache_sd_field block_qspicache_sd_field + * @brief macros for field block_qspicache_sd + * @details if set, this core's FSM cannot assert the qspi cache SD pin + * @{ + */ +#define PSEQ_QSPICACHE_OVERRIDES__BLOCK_QSPICACHE_SD__SHIFT 0 +#define PSEQ_QSPICACHE_OVERRIDES__BLOCK_QSPICACHE_SD__WIDTH 1 +#define PSEQ_QSPICACHE_OVERRIDES__BLOCK_QSPICACHE_SD__MASK 0x00000001U +#define PSEQ_QSPICACHE_OVERRIDES__BLOCK_QSPICACHE_SD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_QSPICACHE_OVERRIDES__BLOCK_QSPICACHE_SD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_QSPICACHE_OVERRIDES__BLOCK_QSPICACHE_SD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_QSPICACHE_OVERRIDES__BLOCK_QSPICACHE_SD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_QSPICACHE_OVERRIDES__BLOCK_QSPICACHE_SD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_QSPICACHE_OVERRIDES__BLOCK_QSPICACHE_SD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_QSPICACHE_OVERRIDES__BLOCK_QSPICACHE_SD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field block_qspicache_vddcut */ +/** + * @defgroup at_apb_pseq_paris_regs_core_block_qspicache_vddcut_field block_qspicache_vddcut_field + * @brief macros for field block_qspicache_vddcut + * @details if set, this core's FSM cannot power off the qspi cache + * @{ + */ +#define PSEQ_QSPICACHE_OVERRIDES__BLOCK_QSPICACHE_VDDCUT__SHIFT 1 +#define PSEQ_QSPICACHE_OVERRIDES__BLOCK_QSPICACHE_VDDCUT__WIDTH 1 +#define PSEQ_QSPICACHE_OVERRIDES__BLOCK_QSPICACHE_VDDCUT__MASK 0x00000002U +#define PSEQ_QSPICACHE_OVERRIDES__BLOCK_QSPICACHE_VDDCUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_QSPICACHE_OVERRIDES__BLOCK_QSPICACHE_VDDCUT__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PSEQ_QSPICACHE_OVERRIDES__BLOCK_QSPICACHE_VDDCUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PSEQ_QSPICACHE_OVERRIDES__BLOCK_QSPICACHE_VDDCUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PSEQ_QSPICACHE_OVERRIDES__BLOCK_QSPICACHE_VDDCUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_QSPICACHE_OVERRIDES__BLOCK_QSPICACHE_VDDCUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_QSPICACHE_OVERRIDES__BLOCK_QSPICACHE_VDDCUT__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_qspicache_sd_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_qspicache_sd_val_field override_qspicache_sd_val_field + * @brief macros for field override_qspicache_sd_val + * @details if override is set, what value should be driven onto qspi cache SD pin? + * @{ + */ +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_SD_VAL__SHIFT 2 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_SD_VAL__WIDTH 1 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_SD_VAL__MASK 0x00000004U +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_SD_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_SD_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_SD_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_SD_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_SD_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_SD_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_SD_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_qspicache_sd */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_qspicache_sd_field override_qspicache_sd_field + * @brief macros for field override_qspicache_sd + * @details if set, software now has direct control of the qspi cache SD pin + * @{ + */ +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_SD__SHIFT 3 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_SD__WIDTH 1 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_SD__MASK 0x00000008U +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_SD__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_SD__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_SD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_SD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_SD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_SD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_SD__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_qspicache_ds_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_qspicache_ds_val_field override_qspicache_ds_val_field + * @brief macros for field override_qspicache_ds_val + * @details if override is set, what value should be driven onto qspi cache DS pin? + * @{ + */ +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_DS_VAL__SHIFT 4 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_DS_VAL__WIDTH 1 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_DS_VAL__MASK 0x00000010U +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_DS_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_DS_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_DS_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_DS_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_DS_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_DS_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_DS_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_qspicache_ds */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_qspicache_ds_field override_qspicache_ds_field + * @brief macros for field override_qspicache_ds + * @details if set, software now has direct control of the qspi cache DS pin + * @{ + */ +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_DS__SHIFT 5 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_DS__WIDTH 1 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_DS__MASK 0x00000020U +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_DS__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_DS__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_DS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_DS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_DS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_DS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_DS__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_qspicache_ls_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_qspicache_ls_val_field override_qspicache_ls_val_field + * @brief macros for field override_qspicache_ls_val + * @details if override is set, what value should be driven onto qspi cache LS pin? + * @{ + */ +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_LS_VAL__SHIFT 6 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_LS_VAL__WIDTH 1 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_LS_VAL__MASK 0x00000040U +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_LS_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_LS_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_LS_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_LS_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_LS_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_LS_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_LS_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_qspicache_ls */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_qspicache_ls_field override_qspicache_ls_field + * @brief macros for field override_qspicache_ls + * @details if set, software now has direct control of the qspi cache LS pin + * @{ + */ +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_LS__SHIFT 7 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_LS__WIDTH 1 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_LS__MASK 0x00000080U +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_LS__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_LS__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_LS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_LS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_LS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_LS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_LS__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_qspicache_iso_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_qspicache_iso_val_field override_qspicache_iso_val_field + * @brief macros for field override_qspicache_iso_val + * @details if override is set, what value should be driven onto qspi cache ISO pin? + * @{ + */ +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_ISO_VAL__SHIFT 8 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_ISO_VAL__WIDTH 1 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_ISO_VAL__MASK 0x00000100U +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_ISO_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_ISO_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_ISO_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_ISO_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_ISO_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_ISO_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_ISO_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_qspicache_iso */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_qspicache_iso_field override_qspicache_iso_field + * @brief macros for field override_qspicache_iso + * @details if set, software now has direct control of the qspi cache ISO pin + * @{ + */ +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_ISO__SHIFT 9 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_ISO__WIDTH 1 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_ISO__MASK 0x00000200U +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_ISO__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_ISO__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_ISO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_ISO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_ISO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_ISO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_ISO__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_qspicache_clken_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_qspicache_clken_val_field override_qspicache_clken_val_field + * @brief macros for field override_qspicache_clken_val + * @details if override is set, should the clock gate on the qspi cache be enabled? 1=clock running 0=clock gated off + * @{ + */ +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_CLKEN_VAL__SHIFT 10 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_CLKEN_VAL__WIDTH 1 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_CLKEN_VAL__MASK \ + 0x00000400U +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_CLKEN_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_CLKEN_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_CLKEN_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_CLKEN_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_CLKEN_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_CLKEN_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_CLKEN_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_qspicache_clken */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_qspicache_clken_field override_qspicache_clken_field + * @brief macros for field override_qspicache_clken + * @details if set, clock gating to qspi cache is now under software control + * @{ + */ +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_CLKEN__SHIFT 11 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_CLKEN__WIDTH 1 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_CLKEN__MASK 0x00000800U +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_CLKEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_CLKEN__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_CLKEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_CLKEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_CLKEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_CLKEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_CLKEN__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_qspicache_vddcut_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_qspicache_vddcut_val_field override_qspicache_vddcut_val_field + * @brief macros for field override_qspicache_vddcut_val + * @details if override is set, should head switch on qspi cache be open or close? 1=open 0=close + * @{ + */ +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_VDDCUT_VAL__SHIFT 12 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_VDDCUT_VAL__WIDTH 1 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_VDDCUT_VAL__MASK \ + 0x00001000U +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_VDDCUT_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_VDDCUT_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_VDDCUT_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_VDDCUT_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_VDDCUT_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_VDDCUT_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_VDDCUT_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field override_qspicache_vddcut */ +/** + * @defgroup at_apb_pseq_paris_regs_core_override_qspicache_vddcut_field override_qspicache_vddcut_field + * @brief macros for field override_qspicache_vddcut + * @details if set, head switch on qspi cache is now software controllable + * @{ + */ +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_VDDCUT__SHIFT 13 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_VDDCUT__WIDTH 1 +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_VDDCUT__MASK 0x00002000U +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_VDDCUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_VDDCUT__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_VDDCUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_VDDCUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_VDDCUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_VDDCUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define PSEQ_QSPICACHE_OVERRIDES__OVERRIDE_QSPICACHE_VDDCUT__RESET_VALUE \ + 0x00000000U +/** @} */ +#define PSEQ_QSPICACHE_OVERRIDES__TYPE uint32_t +#define PSEQ_QSPICACHE_OVERRIDES__READ 0x00003fffU +#define PSEQ_QSPICACHE_OVERRIDES__WRITE 0x00003fffU +#define PSEQ_QSPICACHE_OVERRIDES__PRESERVED 0x00000000U +#define PSEQ_QSPICACHE_OVERRIDES__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_QSPICACHE_OVERRIDES_MACRO__ */ + +/** @} end of qspicache_overrides */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_counter_control */ +/** + * @defgroup at_apb_pseq_paris_regs_core_counter_control counter_control + * @brief control signals for counters definitions. + * @{ + */ +#ifndef __PSEQ_COUNTER_CONTROL_MACRO__ +#define __PSEQ_COUNTER_CONTROL_MACRO__ + +/* macros for field halt_real_time_counter */ +/** + * @defgroup at_apb_pseq_paris_regs_core_halt_real_time_counter_field halt_real_time_counter_field + * @brief macros for field halt_real_time_counter + * @details stop the real time counter from advancing + * @{ + */ +#define PSEQ_COUNTER_CONTROL__HALT_REAL_TIME_COUNTER__SHIFT 0 +#define PSEQ_COUNTER_CONTROL__HALT_REAL_TIME_COUNTER__WIDTH 1 +#define PSEQ_COUNTER_CONTROL__HALT_REAL_TIME_COUNTER__MASK 0x00000001U +#define PSEQ_COUNTER_CONTROL__HALT_REAL_TIME_COUNTER__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_COUNTER_CONTROL__HALT_REAL_TIME_COUNTER__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_COUNTER_CONTROL__HALT_REAL_TIME_COUNTER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_COUNTER_CONTROL__HALT_REAL_TIME_COUNTER__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_COUNTER_CONTROL__HALT_REAL_TIME_COUNTER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_COUNTER_CONTROL__HALT_REAL_TIME_COUNTER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_COUNTER_CONTROL__HALT_REAL_TIME_COUNTER__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field load_count_down_timer */ +/** + * @defgroup at_apb_pseq_paris_regs_core_load_count_down_timer_field load_count_down_timer_field + * @brief macros for field load_count_down_timer + * @details loads on positive edge; hardware doesn't reset this bit + * @{ + */ +#define PSEQ_COUNTER_CONTROL__LOAD_COUNT_DOWN_TIMER__SHIFT 1 +#define PSEQ_COUNTER_CONTROL__LOAD_COUNT_DOWN_TIMER__WIDTH 1 +#define PSEQ_COUNTER_CONTROL__LOAD_COUNT_DOWN_TIMER__MASK 0x00000002U +#define PSEQ_COUNTER_CONTROL__LOAD_COUNT_DOWN_TIMER__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_COUNTER_CONTROL__LOAD_COUNT_DOWN_TIMER__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PSEQ_COUNTER_CONTROL__LOAD_COUNT_DOWN_TIMER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PSEQ_COUNTER_CONTROL__LOAD_COUNT_DOWN_TIMER__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PSEQ_COUNTER_CONTROL__LOAD_COUNT_DOWN_TIMER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_COUNTER_CONTROL__LOAD_COUNT_DOWN_TIMER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_COUNTER_CONTROL__LOAD_COUNT_DOWN_TIMER__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_COUNTER_CONTROL__TYPE uint32_t +#define PSEQ_COUNTER_CONTROL__READ 0x00000003U +#define PSEQ_COUNTER_CONTROL__WRITE 0x00000003U +#define PSEQ_COUNTER_CONTROL__PRESERVED 0x00000000U +#define PSEQ_COUNTER_CONTROL__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_COUNTER_CONTROL_MACRO__ */ + +/** @} end of counter_control */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_current_real_time */ +/** + * @defgroup at_apb_pseq_paris_regs_core_current_real_time current_real_time + * @brief counter value definitions. + * @{ + */ +#ifndef __PSEQ_CURRENT_REAL_TIME_MACRO__ +#define __PSEQ_CURRENT_REAL_TIME_MACRO__ + +/* macros for field val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_val_field val_field + * @brief macros for field val + * @details real time in clk_lpc clock cycles + * @{ + */ +#define PSEQ_CURRENT_REAL_TIME__VAL__SHIFT 0 +#define PSEQ_CURRENT_REAL_TIME__VAL__WIDTH 32 +#define PSEQ_CURRENT_REAL_TIME__VAL__MASK 0xffffffffU +#define PSEQ_CURRENT_REAL_TIME__VAL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PSEQ_CURRENT_REAL_TIME__VAL__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_CURRENT_REAL_TIME__TYPE uint32_t +#define PSEQ_CURRENT_REAL_TIME__READ 0xffffffffU +#define PSEQ_CURRENT_REAL_TIME__PRESERVED 0x00000000U +#define PSEQ_CURRENT_REAL_TIME__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_CURRENT_REAL_TIME_MACRO__ */ + +/** @} end of current_real_time */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_current_count_down_time */ +/** + * @defgroup at_apb_pseq_paris_regs_core_current_count_down_time current_count_down_time + * @brief counter value definitions. + * @{ + */ +#ifndef __PSEQ_CURRENT_COUNT_DOWN_TIME_MACRO__ +#define __PSEQ_CURRENT_COUNT_DOWN_TIME_MACRO__ + +/* macros for field val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_val_field val_field + * @brief macros for field val + * @details this value is on 32kHz domain; read twice and check value is the same; if it's not, reread + * @{ + */ +#define PSEQ_CURRENT_COUNT_DOWN_TIME__VAL__SHIFT 0 +#define PSEQ_CURRENT_COUNT_DOWN_TIME__VAL__WIDTH 32 +#define PSEQ_CURRENT_COUNT_DOWN_TIME__VAL__MASK 0xffffffffU +#define PSEQ_CURRENT_COUNT_DOWN_TIME__VAL__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define PSEQ_CURRENT_COUNT_DOWN_TIME__VAL__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_CURRENT_COUNT_DOWN_TIME__TYPE uint32_t +#define PSEQ_CURRENT_COUNT_DOWN_TIME__READ 0xffffffffU +#define PSEQ_CURRENT_COUNT_DOWN_TIME__PRESERVED 0x00000000U +#define PSEQ_CURRENT_COUNT_DOWN_TIME__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_CURRENT_COUNT_DOWN_TIME_MACRO__ */ + +/** @} end of current_count_down_time */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_init_count_down */ +/** + * @defgroup at_apb_pseq_paris_regs_core_init_count_down init_count_down + * @brief counter value definitions. + * @{ + */ +#ifndef __PSEQ_INIT_COUNT_DOWN_MACRO__ +#define __PSEQ_INIT_COUNT_DOWN_MACRO__ + +/* macros for field val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_val_field val_field + * @brief macros for field val + * @details initial value for count down timer + * @{ + */ +#define PSEQ_INIT_COUNT_DOWN__VAL__SHIFT 0 +#define PSEQ_INIT_COUNT_DOWN__VAL__WIDTH 32 +#define PSEQ_INIT_COUNT_DOWN__VAL__MASK 0xffffffffU +#define PSEQ_INIT_COUNT_DOWN__VAL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PSEQ_INIT_COUNT_DOWN__VAL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define PSEQ_INIT_COUNT_DOWN__VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define PSEQ_INIT_COUNT_DOWN__VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define PSEQ_INIT_COUNT_DOWN__VAL__RESET_VALUE 0x00000fffU +/** @} */ +#define PSEQ_INIT_COUNT_DOWN__TYPE uint32_t +#define PSEQ_INIT_COUNT_DOWN__READ 0xffffffffU +#define PSEQ_INIT_COUNT_DOWN__WRITE 0xffffffffU +#define PSEQ_INIT_COUNT_DOWN__PRESERVED 0x00000000U +#define PSEQ_INIT_COUNT_DOWN__RESET_VALUE 0x00000fffU + +#endif /* __PSEQ_INIT_COUNT_DOWN_MACRO__ */ + +/** @} end of init_count_down */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_inst_pending */ +/** + * @defgroup at_apb_pseq_paris_regs_core_inst_pending inst_pending + * @brief instructions from clk_mpc to clk_lpc still pending definitions. + * @{ + */ +#ifndef __PSEQ_INST_PENDING_MACRO__ +#define __PSEQ_INST_PENDING_MACRO__ + +/* macros for field cntdwn_timer_load */ +/** + * @defgroup at_apb_pseq_paris_regs_core_cntdwn_timer_load_field cntdwn_timer_load_field + * @brief macros for field cntdwn_timer_load + * @details load of count down timer is still pending + * @{ + */ +#define PSEQ_INST_PENDING__CNTDWN_TIMER_LOAD__SHIFT 16 +#define PSEQ_INST_PENDING__CNTDWN_TIMER_LOAD__WIDTH 1 +#define PSEQ_INST_PENDING__CNTDWN_TIMER_LOAD__MASK 0x00010000U +#define PSEQ_INST_PENDING__CNTDWN_TIMER_LOAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define PSEQ_INST_PENDING__CNTDWN_TIMER_LOAD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PSEQ_INST_PENDING__CNTDWN_TIMER_LOAD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PSEQ_INST_PENDING__CNTDWN_TIMER_LOAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wdog_timer_disable */ +/** + * @defgroup at_apb_pseq_paris_regs_core_wdog_timer_disable_field wdog_timer_disable_field + * @brief macros for field wdog_timer_disable + * @details disable/enable of watchdog timer is still pending + * @{ + */ +#define PSEQ_INST_PENDING__WDOG_TIMER_DISABLE__SHIFT 17 +#define PSEQ_INST_PENDING__WDOG_TIMER_DISABLE__WIDTH 1 +#define PSEQ_INST_PENDING__WDOG_TIMER_DISABLE__MASK 0x00020000U +#define PSEQ_INST_PENDING__WDOG_TIMER_DISABLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define PSEQ_INST_PENDING__WDOG_TIMER_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define PSEQ_INST_PENDING__WDOG_TIMER_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define PSEQ_INST_PENDING__WDOG_TIMER_DISABLE__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_INST_PENDING__TYPE uint32_t +#define PSEQ_INST_PENDING__READ 0x00030000U +#define PSEQ_INST_PENDING__PRESERVED 0x00000000U +#define PSEQ_INST_PENDING__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_INST_PENDING_MACRO__ */ + +/** @} end of inst_pending */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_status */ +/** + * @defgroup at_apb_pseq_paris_regs_core_status status + * @brief status signals definitions. + * @{ + */ +#ifndef __PSEQ_STATUS_MACRO__ +#define __PSEQ_STATUS_MACRO__ + +/* macros for field in_active_state */ +/** + * @defgroup at_apb_pseq_paris_regs_core_in_active_state_field in_active_state_field + * @brief macros for field in_active_state + * @details pseq is currently in active state + * @{ + */ +#define PSEQ_STATUS__IN_ACTIVE_STATE__SHIFT 0 +#define PSEQ_STATUS__IN_ACTIVE_STATE__WIDTH 1 +#define PSEQ_STATUS__IN_ACTIVE_STATE__MASK 0x00000001U +#define PSEQ_STATUS__IN_ACTIVE_STATE__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PSEQ_STATUS__IN_ACTIVE_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_STATUS__IN_ACTIVE_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_STATUS__IN_ACTIVE_STATE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field in_cpu_active_state */ +/** + * @defgroup at_apb_pseq_paris_regs_core_in_cpu_active_state_field in_cpu_active_state_field + * @brief macros for field in_cpu_active_state + * @details pseq is currently in cpu active state + * @{ + */ +#define PSEQ_STATUS__IN_CPU_ACTIVE_STATE__SHIFT 1 +#define PSEQ_STATUS__IN_CPU_ACTIVE_STATE__WIDTH 1 +#define PSEQ_STATUS__IN_CPU_ACTIVE_STATE__MASK 0x00000002U +#define PSEQ_STATUS__IN_CPU_ACTIVE_STATE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_STATUS__IN_CPU_ACTIVE_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_STATUS__IN_CPU_ACTIVE_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_STATUS__IN_CPU_ACTIVE_STATE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field in_hibernate_state */ +/** + * @defgroup at_apb_pseq_paris_regs_core_in_hibernate_state_field in_hibernate_state_field + * @brief macros for field in_hibernate_state + * @details pseq is currently in hibernate state + * @{ + */ +#define PSEQ_STATUS__IN_HIBERNATE_STATE__SHIFT 2 +#define PSEQ_STATUS__IN_HIBERNATE_STATE__WIDTH 1 +#define PSEQ_STATUS__IN_HIBERNATE_STATE__MASK 0x00000004U +#define PSEQ_STATUS__IN_HIBERNATE_STATE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PSEQ_STATUS__IN_HIBERNATE_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PSEQ_STATUS__IN_HIBERNATE_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PSEQ_STATUS__IN_HIBERNATE_STATE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field timer_triggered */ +/** + * @defgroup at_apb_pseq_paris_regs_core_timer_triggered_field timer_triggered_field + * @brief macros for field timer_triggered + * @details wake triggered by count down timer + * @{ + */ +#define PSEQ_STATUS__TIMER_TRIGGERED__SHIFT 8 +#define PSEQ_STATUS__TIMER_TRIGGERED__WIDTH 1 +#define PSEQ_STATUS__TIMER_TRIGGERED__MASK 0x00000100U +#define PSEQ_STATUS__TIMER_TRIGGERED__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define PSEQ_STATUS__TIMER_TRIGGERED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PSEQ_STATUS__TIMER_TRIGGERED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PSEQ_STATUS__TIMER_TRIGGERED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field gpio_triggered */ +/** + * @defgroup at_apb_pseq_paris_regs_core_gpio_triggered_field gpio_triggered_field + * @brief macros for field gpio_triggered + * @details wake triggered by gpio + * @{ + */ +#define PSEQ_STATUS__GPIO_TRIGGERED__SHIFT 9 +#define PSEQ_STATUS__GPIO_TRIGGERED__WIDTH 1 +#define PSEQ_STATUS__GPIO_TRIGGERED__MASK 0x00000200U +#define PSEQ_STATUS__GPIO_TRIGGERED__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PSEQ_STATUS__GPIO_TRIGGERED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PSEQ_STATUS__GPIO_TRIGGERED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PSEQ_STATUS__GPIO_TRIGGERED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wurx0_triggered */ +/** + * @defgroup at_apb_pseq_paris_regs_core_wurx0_triggered_field wurx0_triggered_field + * @brief macros for field wurx0_triggered + * @details wake triggered by wurx0 + * @{ + */ +#define PSEQ_STATUS__WURX0_TRIGGERED__SHIFT 10 +#define PSEQ_STATUS__WURX0_TRIGGERED__WIDTH 1 +#define PSEQ_STATUS__WURX0_TRIGGERED__MASK 0x00000400U +#define PSEQ_STATUS__WURX0_TRIGGERED__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define PSEQ_STATUS__WURX0_TRIGGERED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define PSEQ_STATUS__WURX0_TRIGGERED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define PSEQ_STATUS__WURX0_TRIGGERED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wurx1_triggered */ +/** + * @defgroup at_apb_pseq_paris_regs_core_wurx1_triggered_field wurx1_triggered_field + * @brief macros for field wurx1_triggered + * @details wake triggered by wurx1 + * @{ + */ +#define PSEQ_STATUS__WURX1_TRIGGERED__SHIFT 11 +#define PSEQ_STATUS__WURX1_TRIGGERED__WIDTH 1 +#define PSEQ_STATUS__WURX1_TRIGGERED__MASK 0x00000800U +#define PSEQ_STATUS__WURX1_TRIGGERED__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define PSEQ_STATUS__WURX1_TRIGGERED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define PSEQ_STATUS__WURX1_TRIGGERED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define PSEQ_STATUS__WURX1_TRIGGERED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field qdec_triggered */ +/** + * @defgroup at_apb_pseq_paris_regs_core_qdec_triggered_field qdec_triggered_field + * @brief macros for field qdec_triggered + * @details wake triggered by qdec activity + * @{ + */ +#define PSEQ_STATUS__QDEC_TRIGGERED__SHIFT 12 +#define PSEQ_STATUS__QDEC_TRIGGERED__WIDTH 1 +#define PSEQ_STATUS__QDEC_TRIGGERED__MASK 0x00001000U +#define PSEQ_STATUS__QDEC_TRIGGERED__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define PSEQ_STATUS__QDEC_TRIGGERED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define PSEQ_STATUS__QDEC_TRIGGERED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define PSEQ_STATUS__QDEC_TRIGGERED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ksm_triggered */ +/** + * @defgroup at_apb_pseq_paris_regs_core_ksm_triggered_field ksm_triggered_field + * @brief macros for field ksm_triggered + * @details wake triggered by ksm activity + * @{ + */ +#define PSEQ_STATUS__KSM_TRIGGERED__SHIFT 13 +#define PSEQ_STATUS__KSM_TRIGGERED__WIDTH 1 +#define PSEQ_STATUS__KSM_TRIGGERED__MASK 0x00002000U +#define PSEQ_STATUS__KSM_TRIGGERED__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define PSEQ_STATUS__KSM_TRIGGERED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define PSEQ_STATUS__KSM_TRIGGERED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define PSEQ_STATUS__KSM_TRIGGERED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dbg_triggered */ +/** + * @defgroup at_apb_pseq_paris_regs_core_dbg_triggered_field dbg_triggered_field + * @brief macros for field dbg_triggered + * @details wake triggered by debugger + * @{ + */ +#define PSEQ_STATUS__DBG_TRIGGERED__SHIFT 14 +#define PSEQ_STATUS__DBG_TRIGGERED__WIDTH 1 +#define PSEQ_STATUS__DBG_TRIGGERED__MASK 0x00004000U +#define PSEQ_STATUS__DBG_TRIGGERED__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PSEQ_STATUS__DBG_TRIGGERED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PSEQ_STATUS__DBG_TRIGGERED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PSEQ_STATUS__DBG_TRIGGERED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field shub_triggered */ +/** + * @defgroup at_apb_pseq_paris_regs_core_shub_triggered_field shub_triggered_field + * @brief macros for field shub_triggered + * @details wake triggered by sensor hub + * @{ + */ +#define PSEQ_STATUS__SHUB_TRIGGERED__SHIFT 15 +#define PSEQ_STATUS__SHUB_TRIGGERED__WIDTH 1 +#define PSEQ_STATUS__SHUB_TRIGGERED__MASK 0x00008000U +#define PSEQ_STATUS__SHUB_TRIGGERED__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define PSEQ_STATUS__SHUB_TRIGGERED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PSEQ_STATUS__SHUB_TRIGGERED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PSEQ_STATUS__SHUB_TRIGGERED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field spi_triggered */ +/** + * @defgroup at_apb_pseq_paris_regs_core_spi_triggered_field spi_triggered_field + * @brief macros for field spi_triggered + * @details wake triggered by spi slave activity + * @{ + */ +#define PSEQ_STATUS__SPI_TRIGGERED__SHIFT 16 +#define PSEQ_STATUS__SPI_TRIGGERED__WIDTH 1 +#define PSEQ_STATUS__SPI_TRIGGERED__MASK 0x00010000U +#define PSEQ_STATUS__SPI_TRIGGERED__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define PSEQ_STATUS__SPI_TRIGGERED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PSEQ_STATUS__SPI_TRIGGERED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PSEQ_STATUS__SPI_TRIGGERED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field i2c_triggered */ +/** + * @defgroup at_apb_pseq_paris_regs_core_i2c_triggered_field i2c_triggered_field + * @brief macros for field i2c_triggered + * @details wake triggered by i2c slave activity + * @{ + */ +#define PSEQ_STATUS__I2C_TRIGGERED__SHIFT 17 +#define PSEQ_STATUS__I2C_TRIGGERED__WIDTH 1 +#define PSEQ_STATUS__I2C_TRIGGERED__MASK 0x00020000U +#define PSEQ_STATUS__I2C_TRIGGERED__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define PSEQ_STATUS__I2C_TRIGGERED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define PSEQ_STATUS__I2C_TRIGGERED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define PSEQ_STATUS__I2C_TRIGGERED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pmu_timer_triggered */ +/** + * @defgroup at_apb_pseq_paris_regs_core_pmu_timer_triggered_field pmu_timer_triggered_field + * @brief macros for field pmu_timer_triggered + * @details wake triggered by pmu timer expiring + * @{ + */ +#define PSEQ_STATUS__PMU_TIMER_TRIGGERED__SHIFT 18 +#define PSEQ_STATUS__PMU_TIMER_TRIGGERED__WIDTH 1 +#define PSEQ_STATUS__PMU_TIMER_TRIGGERED__MASK 0x00040000U +#define PSEQ_STATUS__PMU_TIMER_TRIGGERED__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define PSEQ_STATUS__PMU_TIMER_TRIGGERED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define PSEQ_STATUS__PMU_TIMER_TRIGGERED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define PSEQ_STATUS__PMU_TIMER_TRIGGERED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pmu_lpcomp_triggered */ +/** + * @defgroup at_apb_pseq_paris_regs_core_pmu_lpcomp_triggered_field pmu_lpcomp_triggered_field + * @brief macros for field pmu_lpcomp_triggered + * @details wake triggered by pmu lpcomp threshold crossing + * @{ + */ +#define PSEQ_STATUS__PMU_LPCOMP_TRIGGERED__SHIFT 19 +#define PSEQ_STATUS__PMU_LPCOMP_TRIGGERED__WIDTH 1 +#define PSEQ_STATUS__PMU_LPCOMP_TRIGGERED__MASK 0x00080000U +#define PSEQ_STATUS__PMU_LPCOMP_TRIGGERED__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define PSEQ_STATUS__PMU_LPCOMP_TRIGGERED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define PSEQ_STATUS__PMU_LPCOMP_TRIGGERED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define PSEQ_STATUS__PMU_LPCOMP_TRIGGERED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field energy4CPU_triggered */ +/** + * @defgroup at_apb_pseq_paris_regs_core_energy4CPU_triggered_field energy4CPU_triggered_field + * @brief macros for field energy4CPU_triggered + * @details wake triggered by pmu energy4CPU + * @{ + */ +#define PSEQ_STATUS__ENERGY4CPU_TRIGGERED__SHIFT 20 +#define PSEQ_STATUS__ENERGY4CPU_TRIGGERED__WIDTH 1 +#define PSEQ_STATUS__ENERGY4CPU_TRIGGERED__MASK 0x00100000U +#define PSEQ_STATUS__ENERGY4CPU_TRIGGERED__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define PSEQ_STATUS__ENERGY4CPU_TRIGGERED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define PSEQ_STATUS__ENERGY4CPU_TRIGGERED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define PSEQ_STATUS__ENERGY4CPU_TRIGGERED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field energy4TX_triggered */ +/** + * @defgroup at_apb_pseq_paris_regs_core_energy4TX_triggered_field energy4TX_triggered_field + * @brief macros for field energy4TX_triggered + * @details wake triggered by pmu energy4TX + * @{ + */ +#define PSEQ_STATUS__ENERGY4TX_TRIGGERED__SHIFT 21 +#define PSEQ_STATUS__ENERGY4TX_TRIGGERED__WIDTH 1 +#define PSEQ_STATUS__ENERGY4TX_TRIGGERED__MASK 0x00200000U +#define PSEQ_STATUS__ENERGY4TX_TRIGGERED__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define PSEQ_STATUS__ENERGY4TX_TRIGGERED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define PSEQ_STATUS__ENERGY4TX_TRIGGERED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define PSEQ_STATUS__ENERGY4TX_TRIGGERED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field endoflife_triggered */ +/** + * @defgroup at_apb_pseq_paris_regs_core_endoflife_triggered_field endoflife_triggered_field + * @brief macros for field endoflife_triggered + * @details wake triggered by pmu endoflife + * @{ + */ +#define PSEQ_STATUS__ENDOFLIFE_TRIGGERED__SHIFT 22 +#define PSEQ_STATUS__ENDOFLIFE_TRIGGERED__WIDTH 1 +#define PSEQ_STATUS__ENDOFLIFE_TRIGGERED__MASK 0x00400000U +#define PSEQ_STATUS__ENDOFLIFE_TRIGGERED__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define PSEQ_STATUS__ENDOFLIFE_TRIGGERED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define PSEQ_STATUS__ENDOFLIFE_TRIGGERED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define PSEQ_STATUS__ENDOFLIFE_TRIGGERED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field brownout_triggered */ +/** + * @defgroup at_apb_pseq_paris_regs_core_brownout_triggered_field brownout_triggered_field + * @brief macros for field brownout_triggered + * @details wake triggered by pmu brownout + * @{ + */ +#define PSEQ_STATUS__BROWNOUT_TRIGGERED__SHIFT 23 +#define PSEQ_STATUS__BROWNOUT_TRIGGERED__WIDTH 1 +#define PSEQ_STATUS__BROWNOUT_TRIGGERED__MASK 0x00800000U +#define PSEQ_STATUS__BROWNOUT_TRIGGERED__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PSEQ_STATUS__BROWNOUT_TRIGGERED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PSEQ_STATUS__BROWNOUT_TRIGGERED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PSEQ_STATUS__BROWNOUT_TRIGGERED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wurx_triggered */ +/** + * @defgroup at_apb_pseq_paris_regs_core_wurx_triggered_field wurx_triggered_field + * @brief macros for field wurx_triggered + * @details wake triggered by multiple events of wurx. + * @{ + */ +#define PSEQ_STATUS__WURX_TRIGGERED__SHIFT 24 +#define PSEQ_STATUS__WURX_TRIGGERED__WIDTH 1 +#define PSEQ_STATUS__WURX_TRIGGERED__MASK 0x01000000U +#define PSEQ_STATUS__WURX_TRIGGERED__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define PSEQ_STATUS__WURX_TRIGGERED__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define PSEQ_STATUS__WURX_TRIGGERED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define PSEQ_STATUS__WURX_TRIGGERED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ble_osc_on_triggered */ +/** + * @defgroup at_apb_pseq_paris_regs_core_ble_osc_on_triggered_field ble_osc_on_triggered_field + * @brief macros for field ble_osc_on_triggered + * @details wake triggered by ble_osc_on + * @{ + */ +#define PSEQ_STATUS__BLE_OSC_ON_TRIGGERED__SHIFT 25 +#define PSEQ_STATUS__BLE_OSC_ON_TRIGGERED__WIDTH 1 +#define PSEQ_STATUS__BLE_OSC_ON_TRIGGERED__MASK 0x02000000U +#define PSEQ_STATUS__BLE_OSC_ON_TRIGGERED__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define PSEQ_STATUS__BLE_OSC_ON_TRIGGERED__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define PSEQ_STATUS__BLE_OSC_ON_TRIGGERED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define PSEQ_STATUS__BLE_OSC_ON_TRIGGERED__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_STATUS__TYPE uint32_t +#define PSEQ_STATUS__READ 0x03ffff07U +#define PSEQ_STATUS__PRESERVED 0x00000000U +#define PSEQ_STATUS__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_STATUS_MACRO__ */ + +/** @} end of status */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_persistent0 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_persistent0 persistent0 + * @brief persistent scratchpad register definitions. + * @{ + */ +#ifndef __PSEQ_PERSISTENT0_MACRO__ +#define __PSEQ_PERSISTENT0_MACRO__ + +/* macros for field data */ +/** + * @defgroup at_apb_pseq_paris_regs_core_data_field data_field + * @brief macros for field data + * @details holds persistent state; persists through hibernation; might be of use to sw + * @{ + */ +#define PSEQ_PERSISTENT0__DATA__SHIFT 0 +#define PSEQ_PERSISTENT0__DATA__WIDTH 32 +#define PSEQ_PERSISTENT0__DATA__MASK 0xffffffffU +#define PSEQ_PERSISTENT0__DATA__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PSEQ_PERSISTENT0__DATA__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define PSEQ_PERSISTENT0__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define PSEQ_PERSISTENT0__DATA__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define PSEQ_PERSISTENT0__DATA__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_PERSISTENT0__TYPE uint32_t +#define PSEQ_PERSISTENT0__READ 0xffffffffU +#define PSEQ_PERSISTENT0__WRITE 0xffffffffU +#define PSEQ_PERSISTENT0__PRESERVED 0x00000000U +#define PSEQ_PERSISTENT0__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_PERSISTENT0_MACRO__ */ + +/** @} end of persistent0 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_persistent1 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_persistent1 persistent1 + * @brief persistent scratchpad register definitions. + * @{ + */ +#ifndef __PSEQ_PERSISTENT1_MACRO__ +#define __PSEQ_PERSISTENT1_MACRO__ + +/* macros for field data */ +/** + * @defgroup at_apb_pseq_paris_regs_core_data_field data_field + * @brief macros for field data + * @details holds persistent state; persists through hibernation; might be of use to sw + * @{ + */ +#define PSEQ_PERSISTENT1__DATA__SHIFT 0 +#define PSEQ_PERSISTENT1__DATA__WIDTH 32 +#define PSEQ_PERSISTENT1__DATA__MASK 0xffffffffU +#define PSEQ_PERSISTENT1__DATA__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PSEQ_PERSISTENT1__DATA__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define PSEQ_PERSISTENT1__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define PSEQ_PERSISTENT1__DATA__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define PSEQ_PERSISTENT1__DATA__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_PERSISTENT1__TYPE uint32_t +#define PSEQ_PERSISTENT1__READ 0xffffffffU +#define PSEQ_PERSISTENT1__WRITE 0xffffffffU +#define PSEQ_PERSISTENT1__PRESERVED 0x00000000U +#define PSEQ_PERSISTENT1__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_PERSISTENT1_MACRO__ */ + +/** @} end of persistent1 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_persistent2 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_persistent2 persistent2 + * @brief persistent scratchpad register definitions. + * @{ + */ +#ifndef __PSEQ_PERSISTENT2_MACRO__ +#define __PSEQ_PERSISTENT2_MACRO__ + +/* macros for field data */ +/** + * @defgroup at_apb_pseq_paris_regs_core_data_field data_field + * @brief macros for field data + * @details holds persistent state; persists through hibernation; might be of use to sw + * @{ + */ +#define PSEQ_PERSISTENT2__DATA__SHIFT 0 +#define PSEQ_PERSISTENT2__DATA__WIDTH 32 +#define PSEQ_PERSISTENT2__DATA__MASK 0xffffffffU +#define PSEQ_PERSISTENT2__DATA__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PSEQ_PERSISTENT2__DATA__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define PSEQ_PERSISTENT2__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define PSEQ_PERSISTENT2__DATA__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define PSEQ_PERSISTENT2__DATA__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_PERSISTENT2__TYPE uint32_t +#define PSEQ_PERSISTENT2__READ 0xffffffffU +#define PSEQ_PERSISTENT2__WRITE 0xffffffffU +#define PSEQ_PERSISTENT2__PRESERVED 0x00000000U +#define PSEQ_PERSISTENT2__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_PERSISTENT2_MACRO__ */ + +/** @} end of persistent2 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_persistent3 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_persistent3 persistent3 + * @brief persistent scratchpad register definitions. + * @{ + */ +#ifndef __PSEQ_PERSISTENT3_MACRO__ +#define __PSEQ_PERSISTENT3_MACRO__ + +/* macros for field data */ +/** + * @defgroup at_apb_pseq_paris_regs_core_data_field data_field + * @brief macros for field data + * @details holds persistent state; persists through hibernation; might be of use to sw + * @{ + */ +#define PSEQ_PERSISTENT3__DATA__SHIFT 0 +#define PSEQ_PERSISTENT3__DATA__WIDTH 32 +#define PSEQ_PERSISTENT3__DATA__MASK 0xffffffffU +#define PSEQ_PERSISTENT3__DATA__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PSEQ_PERSISTENT3__DATA__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define PSEQ_PERSISTENT3__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define PSEQ_PERSISTENT3__DATA__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define PSEQ_PERSISTENT3__DATA__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_PERSISTENT3__TYPE uint32_t +#define PSEQ_PERSISTENT3__READ 0xffffffffU +#define PSEQ_PERSISTENT3__WRITE 0xffffffffU +#define PSEQ_PERSISTENT3__PRESERVED 0x00000000U +#define PSEQ_PERSISTENT3__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_PERSISTENT3_MACRO__ */ + +/** @} end of persistent3 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_persistent4 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_persistent4 persistent4 + * @brief persistent scratchpad register definitions. + * @{ + */ +#ifndef __PSEQ_PERSISTENT4_MACRO__ +#define __PSEQ_PERSISTENT4_MACRO__ + +/* macros for field data */ +/** + * @defgroup at_apb_pseq_paris_regs_core_data_field data_field + * @brief macros for field data + * @details holds persistent state; persists through hibernation; might be of use to sw + * @{ + */ +#define PSEQ_PERSISTENT4__DATA__SHIFT 0 +#define PSEQ_PERSISTENT4__DATA__WIDTH 32 +#define PSEQ_PERSISTENT4__DATA__MASK 0xffffffffU +#define PSEQ_PERSISTENT4__DATA__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PSEQ_PERSISTENT4__DATA__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define PSEQ_PERSISTENT4__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define PSEQ_PERSISTENT4__DATA__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define PSEQ_PERSISTENT4__DATA__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_PERSISTENT4__TYPE uint32_t +#define PSEQ_PERSISTENT4__READ 0xffffffffU +#define PSEQ_PERSISTENT4__WRITE 0xffffffffU +#define PSEQ_PERSISTENT4__PRESERVED 0x00000000U +#define PSEQ_PERSISTENT4__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_PERSISTENT4_MACRO__ */ + +/** @} end of persistent4 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_persistent5 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_persistent5 persistent5 + * @brief persistent scratchpad register definitions. + * @{ + */ +#ifndef __PSEQ_PERSISTENT5_MACRO__ +#define __PSEQ_PERSISTENT5_MACRO__ + +/* macros for field data */ +/** + * @defgroup at_apb_pseq_paris_regs_core_data_field data_field + * @brief macros for field data + * @details holds persistent state; persists through hibernation; might be of use to sw + * @{ + */ +#define PSEQ_PERSISTENT5__DATA__SHIFT 0 +#define PSEQ_PERSISTENT5__DATA__WIDTH 32 +#define PSEQ_PERSISTENT5__DATA__MASK 0xffffffffU +#define PSEQ_PERSISTENT5__DATA__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PSEQ_PERSISTENT5__DATA__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define PSEQ_PERSISTENT5__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define PSEQ_PERSISTENT5__DATA__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define PSEQ_PERSISTENT5__DATA__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_PERSISTENT5__TYPE uint32_t +#define PSEQ_PERSISTENT5__READ 0xffffffffU +#define PSEQ_PERSISTENT5__WRITE 0xffffffffU +#define PSEQ_PERSISTENT5__PRESERVED 0x00000000U +#define PSEQ_PERSISTENT5__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_PERSISTENT5_MACRO__ */ + +/** @} end of persistent5 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_persistent6 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_persistent6 persistent6 + * @brief persistent scratchpad register definitions. + * @{ + */ +#ifndef __PSEQ_PERSISTENT6_MACRO__ +#define __PSEQ_PERSISTENT6_MACRO__ + +/* macros for field data */ +/** + * @defgroup at_apb_pseq_paris_regs_core_data_field data_field + * @brief macros for field data + * @details holds persistent state; persists through hibernation; might be of use to sw + * @{ + */ +#define PSEQ_PERSISTENT6__DATA__SHIFT 0 +#define PSEQ_PERSISTENT6__DATA__WIDTH 32 +#define PSEQ_PERSISTENT6__DATA__MASK 0xffffffffU +#define PSEQ_PERSISTENT6__DATA__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PSEQ_PERSISTENT6__DATA__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define PSEQ_PERSISTENT6__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define PSEQ_PERSISTENT6__DATA__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define PSEQ_PERSISTENT6__DATA__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_PERSISTENT6__TYPE uint32_t +#define PSEQ_PERSISTENT6__READ 0xffffffffU +#define PSEQ_PERSISTENT6__WRITE 0xffffffffU +#define PSEQ_PERSISTENT6__PRESERVED 0x00000000U +#define PSEQ_PERSISTENT6__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_PERSISTENT6_MACRO__ */ + +/** @} end of persistent6 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_persistent7 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_persistent7 persistent7 + * @brief persistent scratchpad register definitions. + * @{ + */ +#ifndef __PSEQ_PERSISTENT7_MACRO__ +#define __PSEQ_PERSISTENT7_MACRO__ + +/* macros for field data */ +/** + * @defgroup at_apb_pseq_paris_regs_core_data_field data_field + * @brief macros for field data + * @details holds persistent state; persists through hibernation; might be of use to sw + * @{ + */ +#define PSEQ_PERSISTENT7__DATA__SHIFT 0 +#define PSEQ_PERSISTENT7__DATA__WIDTH 32 +#define PSEQ_PERSISTENT7__DATA__MASK 0xffffffffU +#define PSEQ_PERSISTENT7__DATA__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PSEQ_PERSISTENT7__DATA__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define PSEQ_PERSISTENT7__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define PSEQ_PERSISTENT7__DATA__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define PSEQ_PERSISTENT7__DATA__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_PERSISTENT7__TYPE uint32_t +#define PSEQ_PERSISTENT7__READ 0xffffffffU +#define PSEQ_PERSISTENT7__WRITE 0xffffffffU +#define PSEQ_PERSISTENT7__PRESERVED 0x00000000U +#define PSEQ_PERSISTENT7__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_PERSISTENT7_MACRO__ */ + +/** @} end of persistent7 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_sensor_hub_control */ +/** + * @defgroup at_apb_pseq_paris_regs_core_sensor_hub_control sensor_hub_control + * @brief control signals for sensor hub definitions. + * @{ + */ +#ifndef __PSEQ_SENSOR_HUB_CONTROL_MACRO__ +#define __PSEQ_SENSOR_HUB_CONTROL_MACRO__ + +/* macros for field enable_func */ +/** + * @defgroup at_apb_pseq_paris_regs_core_enable_func_field enable_func_field + * @brief macros for field enable_func + * @details 1= sensor hub can trigger pseq out of hibernation early due to a threshold crossing event in sensor hub. 0= sensor hub cannot trigger pseq out of hibernation. This bit does not disable the trigger signal to start the sensor functionality at the onset of hibernation. + * @{ + */ +#define PSEQ_SENSOR_HUB_CONTROL__ENABLE_FUNC__SHIFT 0 +#define PSEQ_SENSOR_HUB_CONTROL__ENABLE_FUNC__WIDTH 1 +#define PSEQ_SENSOR_HUB_CONTROL__ENABLE_FUNC__MASK 0x00000001U +#define PSEQ_SENSOR_HUB_CONTROL__ENABLE_FUNC__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_SENSOR_HUB_CONTROL__ENABLE_FUNC__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_SENSOR_HUB_CONTROL__ENABLE_FUNC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_SENSOR_HUB_CONTROL__ENABLE_FUNC__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_SENSOR_HUB_CONTROL__ENABLE_FUNC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_SENSOR_HUB_CONTROL__ENABLE_FUNC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_SENSOR_HUB_CONTROL__ENABLE_FUNC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field shub_reset */ +/** + * @defgroup at_apb_pseq_paris_regs_core_shub_reset_field shub_reset_field + * @brief macros for field shub_reset + * @details 1= keep shub in reset state; 0= release shub from reset + * @{ + */ +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET__SHIFT 1 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET__WIDTH 1 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET__MASK 0x00000002U +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field shub_running_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_shub_running_val_field shub_running_val_field + * @brief macros for field shub_running_val + * @details value fo shub_running when override is set + * @{ + */ +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RUNNING_VAL__SHIFT 2 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RUNNING_VAL__WIDTH 1 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RUNNING_VAL__MASK 0x00000004U +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RUNNING_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RUNNING_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RUNNING_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RUNNING_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RUNNING_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RUNNING_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RUNNING_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field shub_running_ovrd */ +/** + * @defgroup at_apb_pseq_paris_regs_core_shub_running_ovrd_field shub_running_ovrd_field + * @brief macros for field shub_running_ovrd + * @details 1= override + * @{ + */ +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RUNNING_OVRD__SHIFT 3 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RUNNING_OVRD__WIDTH 1 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RUNNING_OVRD__MASK 0x00000008U +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RUNNING_OVRD__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RUNNING_OVRD__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RUNNING_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RUNNING_OVRD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RUNNING_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RUNNING_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RUNNING_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field shub_clken */ +/** + * @defgroup at_apb_pseq_paris_regs_core_shub_clken_field shub_clken_field + * @brief macros for field shub_clken + * @details sensor hub clock enable 0 = clock gated off 1 = clock running + * @{ + */ +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN__SHIFT 4 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN__WIDTH 1 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN__MASK 0x00000010U +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field shub_iso */ +/** + * @defgroup at_apb_pseq_paris_regs_core_shub_iso_field shub_iso_field + * @brief macros for field shub_iso + * @details sensor hub isolation; do not assert/deassert in same cycle as shub_clken 0 = not isolated 1 = isolated + * @{ + */ +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_ISO__SHIFT 5 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_ISO__WIDTH 1 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_ISO__MASK 0x00000020U +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_ISO__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_ISO__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_ISO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_ISO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_ISO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_ISO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_ISO__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field shub_vddcut */ +/** + * @defgroup at_apb_pseq_paris_regs_core_shub_vddcut_field shub_vddcut_field + * @brief macros for field shub_vddcut + * @details sensor hub head switch control 0 = head switch is closed 1 = head switch is open + * @{ + */ +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_VDDCUT__SHIFT 6 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_VDDCUT__WIDTH 1 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_VDDCUT__MASK 0x00000040U +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_VDDCUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_VDDCUT__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_VDDCUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_VDDCUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_VDDCUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_VDDCUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_VDDCUT__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field shub_reset_slow */ +/** + * @defgroup at_apb_pseq_paris_regs_core_shub_reset_slow_field shub_reset_slow_field + * @brief macros for field shub_reset_slow + * @details for 32kHz portion; 1 = keep shub in reset state; 0 = release shub from reset + * @{ + */ +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET_SLOW__SHIFT 7 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET_SLOW__WIDTH 1 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET_SLOW__MASK 0x00000080U +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET_SLOW__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET_SLOW__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET_SLOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET_SLOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET_SLOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET_SLOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_RESET_SLOW__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field shub_clken_slow */ +/** + * @defgroup at_apb_pseq_paris_regs_core_shub_clken_slow_field shub_clken_slow_field + * @brief macros for field shub_clken_slow + * @details for 32kHz portion; sensor hub clock enable 0 = clock off 1 = clock running + * @{ + */ +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN_SLOW__SHIFT 8 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN_SLOW__WIDTH 1 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN_SLOW__MASK 0x00000100U +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN_SLOW__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN_SLOW__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN_SLOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN_SLOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN_SLOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN_SLOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_CLKEN_SLOW__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field shub_start_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_shub_start_val_field shub_start_val_field + * @brief macros for field shub_start_val + * @details value fo shub_start when override is set + * @{ + */ +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_VAL__SHIFT 9 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_VAL__WIDTH 1 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_VAL__MASK 0x00000200U +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field shub_start_ovrd */ +/** + * @defgroup at_apb_pseq_paris_regs_core_shub_start_ovrd_field shub_start_ovrd_field + * @brief macros for field shub_start_ovrd + * @details 1= override + * @{ + */ +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_OVRD__SHIFT 10 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_OVRD__WIDTH 1 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_OVRD__MASK 0x00000400U +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_OVRD__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_OVRD__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_OVRD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field shub_breakout_imm_en */ +/** + * @defgroup at_apb_pseq_paris_regs_core_shub_breakout_imm_en_field shub_breakout_imm_en_field + * @brief macros for field shub_breakout_imm_en + * @details 1= breakout sensor asap when a valid out-of-HIB event is triggered. 0= wait for sensor hub wrap-up. + * @{ + */ +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_BREAKOUT_IMM_EN__SHIFT 11 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_BREAKOUT_IMM_EN__WIDTH 1 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_BREAKOUT_IMM_EN__MASK 0x00000800U +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_BREAKOUT_IMM_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_BREAKOUT_IMM_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_BREAKOUT_IMM_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_BREAKOUT_IMM_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_BREAKOUT_IMM_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_BREAKOUT_IMM_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_BREAKOUT_IMM_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field shub_adv_enable */ +/** + * @defgroup at_apb_pseq_paris_regs_core_shub_adv_enable_field shub_adv_enable_field + * @brief macros for field shub_adv_enable + * @details 1= enable adv along with sensor hub. + * @{ + */ +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_ADV_ENABLE__SHIFT 12 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_ADV_ENABLE__WIDTH 1 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_ADV_ENABLE__MASK 0x00001000U +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_ADV_ENABLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_ADV_ENABLE__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_ADV_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_ADV_ENABLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_ADV_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_ADV_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_ADV_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field shub_start_adv_val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_shub_start_adv_val_field shub_start_adv_val_field + * @brief macros for field shub_start_adv_val + * @details value fo shub_start_adv when override is set + * @{ + */ +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_ADV_VAL__SHIFT 13 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_ADV_VAL__WIDTH 1 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_ADV_VAL__MASK 0x00002000U +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_ADV_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_ADV_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_ADV_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_ADV_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_ADV_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_ADV_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_ADV_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field shub_start_adv_ovrd */ +/** + * @defgroup at_apb_pseq_paris_regs_core_shub_start_adv_ovrd_field shub_start_adv_ovrd_field + * @brief macros for field shub_start_adv_ovrd + * @details 1= override + * @{ + */ +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_ADV_OVRD__SHIFT 14 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_ADV_OVRD__WIDTH 1 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_ADV_OVRD__MASK 0x00004000U +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_ADV_OVRD__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_ADV_OVRD__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_ADV_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_ADV_OVRD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_ADV_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_ADV_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_START_ADV_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field shub_hib_exit_en */ +/** + * @defgroup at_apb_pseq_paris_regs_core_shub_hib_exit_en_field shub_hib_exit_en_field + * @brief macros for field shub_hib_exit_en + * @details 1= exit out of hib, 0=exit out of retain. + * @{ + */ +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_HIB_EXIT_EN__SHIFT 15 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_HIB_EXIT_EN__WIDTH 1 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_HIB_EXIT_EN__MASK 0x00008000U +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_HIB_EXIT_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_HIB_EXIT_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_HIB_EXIT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_HIB_EXIT_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_HIB_EXIT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_HIB_EXIT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_HIB_EXIT_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field shub_sram0_acc_en */ +/** + * @defgroup at_apb_pseq_paris_regs_core_shub_sram0_acc_en_field shub_sram0_acc_en_field + * @brief macros for field shub_sram0_acc_en + * @details 1= allow shub access to sram0 + * @{ + */ +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM0_ACC_EN__SHIFT 28 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM0_ACC_EN__WIDTH 1 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM0_ACC_EN__MASK 0x10000000U +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM0_ACC_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM0_ACC_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM0_ACC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM0_ACC_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM0_ACC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM0_ACC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM0_ACC_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field shub_sram1_acc_en */ +/** + * @defgroup at_apb_pseq_paris_regs_core_shub_sram1_acc_en_field shub_sram1_acc_en_field + * @brief macros for field shub_sram1_acc_en + * @details 1= allow shub access to sram1 + * @{ + */ +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM1_ACC_EN__SHIFT 29 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM1_ACC_EN__WIDTH 1 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM1_ACC_EN__MASK 0x20000000U +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM1_ACC_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM1_ACC_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM1_ACC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM1_ACC_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM1_ACC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM1_ACC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM1_ACC_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field shub_sram2_acc_en */ +/** + * @defgroup at_apb_pseq_paris_regs_core_shub_sram2_acc_en_field shub_sram2_acc_en_field + * @brief macros for field shub_sram2_acc_en + * @details 1= allow shub access to sram2 + * @{ + */ +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM2_ACC_EN__SHIFT 30 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM2_ACC_EN__WIDTH 1 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM2_ACC_EN__MASK 0x40000000U +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM2_ACC_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM2_ACC_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM2_ACC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM2_ACC_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM2_ACC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM2_ACC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM2_ACC_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field shub_sram3_acc_en */ +/** + * @defgroup at_apb_pseq_paris_regs_core_shub_sram3_acc_en_field shub_sram3_acc_en_field + * @brief macros for field shub_sram3_acc_en + * @details 1= allow shub access to sram3 + * @{ + */ +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM3_ACC_EN__SHIFT 31 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM3_ACC_EN__WIDTH 1 +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM3_ACC_EN__MASK 0x80000000U +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM3_ACC_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM3_ACC_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM3_ACC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM3_ACC_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM3_ACC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM3_ACC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PSEQ_SENSOR_HUB_CONTROL__SHUB_SRAM3_ACC_EN__RESET_VALUE 0x00000001U +/** @} */ +#define PSEQ_SENSOR_HUB_CONTROL__TYPE uint32_t +#define PSEQ_SENSOR_HUB_CONTROL__READ 0xf000ffffU +#define PSEQ_SENSOR_HUB_CONTROL__WRITE 0xf000ffffU +#define PSEQ_SENSOR_HUB_CONTROL__PRESERVED 0x00000000U +#define PSEQ_SENSOR_HUB_CONTROL__RESET_VALUE 0xf00000e2U + +#endif /* __PSEQ_SENSOR_HUB_CONTROL_MACRO__ */ + +/** @} end of sensor_hub_control */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_ksmqdec_control */ +/** + * @defgroup at_apb_pseq_paris_regs_core_ksmqdec_control ksmqdec_control + * @brief keyboard and mouse power domain controls definitions. + * @{ + */ +#ifndef __PSEQ_KSMQDEC_CONTROL_MACRO__ +#define __PSEQ_KSMQDEC_CONTROL_MACRO__ + +/* macros for field ksmqdec_clken */ +/** + * @defgroup at_apb_pseq_paris_regs_core_ksmqdec_clken_field ksmqdec_clken_field + * @brief macros for field ksmqdec_clken + * @details clock enable 0 = clock gated off 1 = clock running + * @{ + */ +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_CLKEN__SHIFT 0 +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_CLKEN__WIDTH 1 +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_CLKEN__MASK 0x00000001U +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_CLKEN__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_CLKEN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_CLKEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_CLKEN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_CLKEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_CLKEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_CLKEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ksmqdec_frst */ +/** + * @defgroup at_apb_pseq_paris_regs_core_ksmqdec_frst_field ksmqdec_frst_field + * @brief macros for field ksmqdec_frst + * @details forced reset 1 = reset 0 = not reset + * @{ + */ +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_FRST__SHIFT 1 +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_FRST__WIDTH 1 +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_FRST__MASK 0x00000002U +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_FRST__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_FRST__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_FRST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_FRST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_FRST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_FRST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_FRST__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ksmqdec_iso */ +/** + * @defgroup at_apb_pseq_paris_regs_core_ksmqdec_iso_field ksmqdec_iso_field + * @brief macros for field ksmqdec_iso + * @details isolation 0 = not isolated 1 = isolated + * @{ + */ +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_ISO__SHIFT 2 +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_ISO__WIDTH 1 +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_ISO__MASK 0x00000004U +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_ISO__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_ISO__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_ISO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_ISO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_ISO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_ISO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_ISO__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ksmqdec_vddcut */ +/** + * @defgroup at_apb_pseq_paris_regs_core_ksmqdec_vddcut_field ksmqdec_vddcut_field + * @brief macros for field ksmqdec_vddcut + * @details head switch control 0 = head switch is closed 1 = head switch is open + * @{ + */ +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_VDDCUT__SHIFT 3 +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_VDDCUT__WIDTH 1 +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_VDDCUT__MASK 0x00000008U +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_VDDCUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_VDDCUT__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_VDDCUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_VDDCUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_VDDCUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_VDDCUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PSEQ_KSMQDEC_CONTROL__KSMQDEC_VDDCUT__RESET_VALUE 0x00000001U +/** @} */ +#define PSEQ_KSMQDEC_CONTROL__TYPE uint32_t +#define PSEQ_KSMQDEC_CONTROL__READ 0x0000000fU +#define PSEQ_KSMQDEC_CONTROL__WRITE 0x0000000fU +#define PSEQ_KSMQDEC_CONTROL__PRESERVED 0x00000000U +#define PSEQ_KSMQDEC_CONTROL__RESET_VALUE 0x0000000eU + +#endif /* __PSEQ_KSMQDEC_CONTROL_MACRO__ */ + +/** @} end of ksmqdec_control */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_spii2c_control */ +/** + * @defgroup at_apb_pseq_paris_regs_core_spii2c_control spii2c_control + * @brief spi and i2c power domain controls definitions. + * @{ + */ +#ifndef __PSEQ_SPII2C_CONTROL_MACRO__ +#define __PSEQ_SPII2C_CONTROL_MACRO__ + +/* macros for field spii2c_clken */ +/** + * @defgroup at_apb_pseq_paris_regs_core_spii2c_clken_field spii2c_clken_field + * @brief macros for field spii2c_clken + * @details clock enable 0 = clock gated off 1 = clock running + * @{ + */ +#define PSEQ_SPII2C_CONTROL__SPII2C_CLKEN__SHIFT 0 +#define PSEQ_SPII2C_CONTROL__SPII2C_CLKEN__WIDTH 1 +#define PSEQ_SPII2C_CONTROL__SPII2C_CLKEN__MASK 0x00000001U +#define PSEQ_SPII2C_CONTROL__SPII2C_CLKEN__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_SPII2C_CONTROL__SPII2C_CLKEN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_SPII2C_CONTROL__SPII2C_CLKEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_SPII2C_CONTROL__SPII2C_CLKEN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_SPII2C_CONTROL__SPII2C_CLKEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_SPII2C_CONTROL__SPII2C_CLKEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_SPII2C_CONTROL__SPII2C_CLKEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field spii2c_frst */ +/** + * @defgroup at_apb_pseq_paris_regs_core_spii2c_frst_field spii2c_frst_field + * @brief macros for field spii2c_frst + * @details forced reset 1 = reset 0 = not reset + * @{ + */ +#define PSEQ_SPII2C_CONTROL__SPII2C_FRST__SHIFT 1 +#define PSEQ_SPII2C_CONTROL__SPII2C_FRST__WIDTH 1 +#define PSEQ_SPII2C_CONTROL__SPII2C_FRST__MASK 0x00000002U +#define PSEQ_SPII2C_CONTROL__SPII2C_FRST__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_SPII2C_CONTROL__SPII2C_FRST__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PSEQ_SPII2C_CONTROL__SPII2C_FRST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PSEQ_SPII2C_CONTROL__SPII2C_FRST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PSEQ_SPII2C_CONTROL__SPII2C_FRST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_SPII2C_CONTROL__SPII2C_FRST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_SPII2C_CONTROL__SPII2C_FRST__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field spii2c_iso */ +/** + * @defgroup at_apb_pseq_paris_regs_core_spii2c_iso_field spii2c_iso_field + * @brief macros for field spii2c_iso + * @details isolation 0 = not isolated 1 = isolated + * @{ + */ +#define PSEQ_SPII2C_CONTROL__SPII2C_ISO__SHIFT 2 +#define PSEQ_SPII2C_CONTROL__SPII2C_ISO__WIDTH 1 +#define PSEQ_SPII2C_CONTROL__SPII2C_ISO__MASK 0x00000004U +#define PSEQ_SPII2C_CONTROL__SPII2C_ISO__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PSEQ_SPII2C_CONTROL__SPII2C_ISO__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PSEQ_SPII2C_CONTROL__SPII2C_ISO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PSEQ_SPII2C_CONTROL__SPII2C_ISO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PSEQ_SPII2C_CONTROL__SPII2C_ISO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PSEQ_SPII2C_CONTROL__SPII2C_ISO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PSEQ_SPII2C_CONTROL__SPII2C_ISO__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field spii2c_vddcut */ +/** + * @defgroup at_apb_pseq_paris_regs_core_spii2c_vddcut_field spii2c_vddcut_field + * @brief macros for field spii2c_vddcut + * @details head switch control 0 = head switch is closed 1 = head switch is open + * @{ + */ +#define PSEQ_SPII2C_CONTROL__SPII2C_VDDCUT__SHIFT 3 +#define PSEQ_SPII2C_CONTROL__SPII2C_VDDCUT__WIDTH 1 +#define PSEQ_SPII2C_CONTROL__SPII2C_VDDCUT__MASK 0x00000008U +#define PSEQ_SPII2C_CONTROL__SPII2C_VDDCUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PSEQ_SPII2C_CONTROL__SPII2C_VDDCUT__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PSEQ_SPII2C_CONTROL__SPII2C_VDDCUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PSEQ_SPII2C_CONTROL__SPII2C_VDDCUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PSEQ_SPII2C_CONTROL__SPII2C_VDDCUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PSEQ_SPII2C_CONTROL__SPII2C_VDDCUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PSEQ_SPII2C_CONTROL__SPII2C_VDDCUT__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field i2c0_slv_id_sel */ +/** + * @defgroup at_apb_pseq_paris_regs_core_i2c0_slv_id_sel_field i2c0_slv_id_sel_field + * @brief macros for field i2c0_slv_id_sel + * @details select secondary i2c device id for i2c0 + * @{ + */ +#define PSEQ_SPII2C_CONTROL__I2C0_SLV_ID_SEL__SHIFT 4 +#define PSEQ_SPII2C_CONTROL__I2C0_SLV_ID_SEL__WIDTH 1 +#define PSEQ_SPII2C_CONTROL__I2C0_SLV_ID_SEL__MASK 0x00000010U +#define PSEQ_SPII2C_CONTROL__I2C0_SLV_ID_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PSEQ_SPII2C_CONTROL__I2C0_SLV_ID_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PSEQ_SPII2C_CONTROL__I2C0_SLV_ID_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PSEQ_SPII2C_CONTROL__I2C0_SLV_ID_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PSEQ_SPII2C_CONTROL__I2C0_SLV_ID_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PSEQ_SPII2C_CONTROL__I2C0_SLV_ID_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PSEQ_SPII2C_CONTROL__I2C0_SLV_ID_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field i2c1_slv_id_sel */ +/** + * @defgroup at_apb_pseq_paris_regs_core_i2c1_slv_id_sel_field i2c1_slv_id_sel_field + * @brief macros for field i2c1_slv_id_sel + * @details select secondary i2c device id for i2c1 + * @{ + */ +#define PSEQ_SPII2C_CONTROL__I2C1_SLV_ID_SEL__SHIFT 5 +#define PSEQ_SPII2C_CONTROL__I2C1_SLV_ID_SEL__WIDTH 1 +#define PSEQ_SPII2C_CONTROL__I2C1_SLV_ID_SEL__MASK 0x00000020U +#define PSEQ_SPII2C_CONTROL__I2C1_SLV_ID_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PSEQ_SPII2C_CONTROL__I2C1_SLV_ID_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define PSEQ_SPII2C_CONTROL__I2C1_SLV_ID_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define PSEQ_SPII2C_CONTROL__I2C1_SLV_ID_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define PSEQ_SPII2C_CONTROL__I2C1_SLV_ID_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PSEQ_SPII2C_CONTROL__I2C1_SLV_ID_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PSEQ_SPII2C_CONTROL__I2C1_SLV_ID_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_SPII2C_CONTROL__TYPE uint32_t +#define PSEQ_SPII2C_CONTROL__READ 0x0000003fU +#define PSEQ_SPII2C_CONTROL__WRITE 0x0000003fU +#define PSEQ_SPII2C_CONTROL__PRESERVED 0x00000000U +#define PSEQ_SPII2C_CONTROL__RESET_VALUE 0x0000000eU + +#endif /* __PSEQ_SPII2C_CONTROL_MACRO__ */ + +/** @} end of spii2c_control */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_flash_control */ +/** + * @defgroup at_apb_pseq_paris_regs_core_flash_control flash_control + * @brief low power control of external flash needs definitions. + * @{ + */ +#ifndef __PSEQ_FLASH_CONTROL_MACRO__ +#define __PSEQ_FLASH_CONTROL_MACRO__ + +/* macros for field power_cycle_en */ +/** + * @defgroup at_apb_pseq_paris_regs_core_power_cycle_en_field power_cycle_en_field + * @brief macros for field power_cycle_en + * @details 1=trigger command to release flash from power down when waking up 0= no action + * @{ + */ +#define PSEQ_FLASH_CONTROL__POWER_CYCLE_EN__SHIFT 0 +#define PSEQ_FLASH_CONTROL__POWER_CYCLE_EN__WIDTH 1 +#define PSEQ_FLASH_CONTROL__POWER_CYCLE_EN__MASK 0x00000001U +#define PSEQ_FLASH_CONTROL__POWER_CYCLE_EN__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_FLASH_CONTROL__POWER_CYCLE_EN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_FLASH_CONTROL__POWER_CYCLE_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_FLASH_CONTROL__POWER_CYCLE_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_FLASH_CONTROL__POWER_CYCLE_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_FLASH_CONTROL__POWER_CYCLE_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_FLASH_CONTROL__POWER_CYCLE_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rpd_has_clock */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rpd_has_clock_field rpd_has_clock_field + * @brief macros for field rpd_has_clock + * @details 1=flash requires opcode to wakeup 0=flash requires only CS to wakeup + * @{ + */ +#define PSEQ_FLASH_CONTROL__RPD_HAS_CLOCK__SHIFT 1 +#define PSEQ_FLASH_CONTROL__RPD_HAS_CLOCK__WIDTH 1 +#define PSEQ_FLASH_CONTROL__RPD_HAS_CLOCK__MASK 0x00000002U +#define PSEQ_FLASH_CONTROL__RPD_HAS_CLOCK__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_FLASH_CONTROL__RPD_HAS_CLOCK__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PSEQ_FLASH_CONTROL__RPD_HAS_CLOCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PSEQ_FLASH_CONTROL__RPD_HAS_CLOCK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PSEQ_FLASH_CONTROL__RPD_HAS_CLOCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_FLASH_CONTROL__RPD_HAS_CLOCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_FLASH_CONTROL__RPD_HAS_CLOCK__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field mode */ +/** + * @defgroup at_apb_pseq_paris_regs_core_mode_field mode_field + * @brief macros for field mode + * @details defining interface bus width of opcode; 0,3=single 1=dual 2=quad For Macronix, set it to 0 because opcode is always serialized; For Micron, it depends on the pre-configured interface bus width on the flash device. + * @{ + */ +#define PSEQ_FLASH_CONTROL__MODE__SHIFT 2 +#define PSEQ_FLASH_CONTROL__MODE__WIDTH 2 +#define PSEQ_FLASH_CONTROL__MODE__MASK 0x0000000cU +#define PSEQ_FLASH_CONTROL__MODE__READ(src) \ + (((uint32_t)(src)\ + & 0x0000000cU) >> 2) +#define PSEQ_FLASH_CONTROL__MODE__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000000cU) +#define PSEQ_FLASH_CONTROL__MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((uint32_t)(src) <<\ + 2) & 0x0000000cU) +#define PSEQ_FLASH_CONTROL__MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000000cU))) +#define PSEQ_FLASH_CONTROL__MODE__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field opcode */ +/** + * @defgroup at_apb_pseq_paris_regs_core_opcode_field opcode_field + * @brief macros for field opcode + * @details opcode that wakes up the external flash from deep power down mode + * @{ + */ +#define PSEQ_FLASH_CONTROL__OPCODE__SHIFT 4 +#define PSEQ_FLASH_CONTROL__OPCODE__WIDTH 8 +#define PSEQ_FLASH_CONTROL__OPCODE__MASK 0x00000ff0U +#define PSEQ_FLASH_CONTROL__OPCODE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000ff0U) >> 4) +#define PSEQ_FLASH_CONTROL__OPCODE__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000ff0U) +#define PSEQ_FLASH_CONTROL__OPCODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000ff0U) | (((uint32_t)(src) <<\ + 4) & 0x00000ff0U) +#define PSEQ_FLASH_CONTROL__OPCODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000ff0U))) +#define PSEQ_FLASH_CONTROL__OPCODE__RESET_VALUE 0x000000abU +/** @} */ + +/* macros for field pd_opcode */ +/** + * @defgroup at_apb_pseq_paris_regs_core_pd_opcode_field pd_opcode_field + * @brief macros for field pd_opcode + * @details opcode that puts external flash into deep power down mode + * @{ + */ +#define PSEQ_FLASH_CONTROL__PD_OPCODE__SHIFT 12 +#define PSEQ_FLASH_CONTROL__PD_OPCODE__WIDTH 8 +#define PSEQ_FLASH_CONTROL__PD_OPCODE__MASK 0x000ff000U +#define PSEQ_FLASH_CONTROL__PD_OPCODE__READ(src) \ + (((uint32_t)(src)\ + & 0x000ff000U) >> 12) +#define PSEQ_FLASH_CONTROL__PD_OPCODE__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x000ff000U) +#define PSEQ_FLASH_CONTROL__PD_OPCODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ff000U) | (((uint32_t)(src) <<\ + 12) & 0x000ff000U) +#define PSEQ_FLASH_CONTROL__PD_OPCODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x000ff000U))) +#define PSEQ_FLASH_CONTROL__PD_OPCODE__RESET_VALUE 0x000000b9U +/** @} */ + +/* macros for field expm_opcode */ +/** + * @defgroup at_apb_pseq_paris_regs_core_expm_opcode_field expm_opcode_field + * @brief macros for field expm_opcode + * @details opcode that takes flash out of performance mode + * @{ + */ +#define PSEQ_FLASH_CONTROL__EXPM_OPCODE__SHIFT 20 +#define PSEQ_FLASH_CONTROL__EXPM_OPCODE__WIDTH 8 +#define PSEQ_FLASH_CONTROL__EXPM_OPCODE__MASK 0x0ff00000U +#define PSEQ_FLASH_CONTROL__EXPM_OPCODE__READ(src) \ + (((uint32_t)(src)\ + & 0x0ff00000U) >> 20) +#define PSEQ_FLASH_CONTROL__EXPM_OPCODE__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x0ff00000U) +#define PSEQ_FLASH_CONTROL__EXPM_OPCODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x0ff00000U) +#define PSEQ_FLASH_CONTROL__EXPM_OPCODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x0ff00000U))) +#define PSEQ_FLASH_CONTROL__EXPM_OPCODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field expm_en */ +/** + * @defgroup at_apb_pseq_paris_regs_core_expm_en_field expm_en_field + * @brief macros for field expm_en + * @details 1=exit performance mode before issuing pd_opcode 0=not in performance mode. + * @{ + */ +#define PSEQ_FLASH_CONTROL__EXPM_EN__SHIFT 28 +#define PSEQ_FLASH_CONTROL__EXPM_EN__WIDTH 1 +#define PSEQ_FLASH_CONTROL__EXPM_EN__MASK 0x10000000U +#define PSEQ_FLASH_CONTROL__EXPM_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define PSEQ_FLASH_CONTROL__EXPM_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define PSEQ_FLASH_CONTROL__EXPM_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define PSEQ_FLASH_CONTROL__EXPM_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define PSEQ_FLASH_CONTROL__EXPM_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define PSEQ_FLASH_CONTROL__EXPM_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define PSEQ_FLASH_CONTROL__EXPM_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pd_b4_sleep */ +/** + * @defgroup at_apb_pseq_paris_regs_core_pd_b4_sleep_field pd_b4_sleep_field + * @brief macros for field pd_b4_sleep + * @details 1=issue flash deep power down prior to low power mode 0=no command issue. + * @{ + */ +#define PSEQ_FLASH_CONTROL__PD_B4_SLEEP__SHIFT 29 +#define PSEQ_FLASH_CONTROL__PD_B4_SLEEP__WIDTH 1 +#define PSEQ_FLASH_CONTROL__PD_B4_SLEEP__MASK 0x20000000U +#define PSEQ_FLASH_CONTROL__PD_B4_SLEEP__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define PSEQ_FLASH_CONTROL__PD_B4_SLEEP__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define PSEQ_FLASH_CONTROL__PD_B4_SLEEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define PSEQ_FLASH_CONTROL__PD_B4_SLEEP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define PSEQ_FLASH_CONTROL__PD_B4_SLEEP__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define PSEQ_FLASH_CONTROL__PD_B4_SLEEP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define PSEQ_FLASH_CONTROL__PD_B4_SLEEP__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_FLASH_CONTROL__TYPE uint32_t +#define PSEQ_FLASH_CONTROL__READ 0x3fffffffU +#define PSEQ_FLASH_CONTROL__WRITE 0x3fffffffU +#define PSEQ_FLASH_CONTROL__PRESERVED 0x00000000U +#define PSEQ_FLASH_CONTROL__RESET_VALUE 0x100b9abaU + +#endif /* __PSEQ_FLASH_CONTROL_MACRO__ */ + +/** @} end of flash_control */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_flash_control2 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_flash_control2 flash_control2 + * @brief low power control of external flash needs definitions. + * @{ + */ +#ifndef __PSEQ_FLASH_CONTROL2_MACRO__ +#define __PSEQ_FLASH_CONTROL2_MACRO__ + +/* macros for field pseq_state_match */ +/** + * @defgroup at_apb_pseq_paris_regs_core_pseq_state_match_field pseq_state_match_field + * @brief macros for field pseq_state_match + * @details pseq state to trigger flash deep power down. + * @{ + */ +#define PSEQ_FLASH_CONTROL2__PSEQ_STATE_MATCH__SHIFT 0 +#define PSEQ_FLASH_CONTROL2__PSEQ_STATE_MATCH__WIDTH 8 +#define PSEQ_FLASH_CONTROL2__PSEQ_STATE_MATCH__MASK 0x000000ffU +#define PSEQ_FLASH_CONTROL2__PSEQ_STATE_MATCH__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PSEQ_FLASH_CONTROL2__PSEQ_STATE_MATCH__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PSEQ_FLASH_CONTROL2__PSEQ_STATE_MATCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define PSEQ_FLASH_CONTROL2__PSEQ_STATE_MATCH__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define PSEQ_FLASH_CONTROL2__PSEQ_STATE_MATCH__RESET_VALUE 0x0000007fU +/** @} */ + +/* macros for field expm_mode */ +/** + * @defgroup at_apb_pseq_paris_regs_core_expm_mode_field expm_mode_field + * @brief macros for field expm_mode + * @details defining interface bus width of performance exit command; 0,3=single 1=dual 2=quad For Macronix, set it to 2 as it's the only interface bus width equipped with performance enhancement mode For Micron, it depends on the pre-configured interface bus width on the flash device, likely quad. + * @{ + */ +#define PSEQ_FLASH_CONTROL2__EXPM_MODE__SHIFT 16 +#define PSEQ_FLASH_CONTROL2__EXPM_MODE__WIDTH 2 +#define PSEQ_FLASH_CONTROL2__EXPM_MODE__MASK 0x00030000U +#define PSEQ_FLASH_CONTROL2__EXPM_MODE__READ(src) \ + (((uint32_t)(src)\ + & 0x00030000U) >> 16) +#define PSEQ_FLASH_CONTROL2__EXPM_MODE__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00030000U) +#define PSEQ_FLASH_CONTROL2__EXPM_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00030000U) | (((uint32_t)(src) <<\ + 16) & 0x00030000U) +#define PSEQ_FLASH_CONTROL2__EXPM_MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00030000U))) +#define PSEQ_FLASH_CONTROL2__EXPM_MODE__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field enpm_clr_en */ +/** + * @defgroup at_apb_pseq_paris_regs_core_enpm_clr_en_field enpm_clr_en_field + * @brief macros for field enpm_clr_en + * @details 1=clears enable_performance_mode bit in qspi_ahb too if expm_opcode is sent to flash. + * @{ + */ +#define PSEQ_FLASH_CONTROL2__ENPM_CLR_EN__SHIFT 18 +#define PSEQ_FLASH_CONTROL2__ENPM_CLR_EN__WIDTH 1 +#define PSEQ_FLASH_CONTROL2__ENPM_CLR_EN__MASK 0x00040000U +#define PSEQ_FLASH_CONTROL2__ENPM_CLR_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define PSEQ_FLASH_CONTROL2__ENPM_CLR_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define PSEQ_FLASH_CONTROL2__ENPM_CLR_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define PSEQ_FLASH_CONTROL2__ENPM_CLR_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define PSEQ_FLASH_CONTROL2__ENPM_CLR_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define PSEQ_FLASH_CONTROL2__ENPM_CLR_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define PSEQ_FLASH_CONTROL2__ENPM_CLR_EN__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_FLASH_CONTROL2__TYPE uint32_t +#define PSEQ_FLASH_CONTROL2__READ 0x000700ffU +#define PSEQ_FLASH_CONTROL2__WRITE 0x000700ffU +#define PSEQ_FLASH_CONTROL2__PRESERVED 0x00000000U +#define PSEQ_FLASH_CONTROL2__RESET_VALUE 0x0002007fU + +#endif /* __PSEQ_FLASH_CONTROL2_MACRO__ */ + +/** @} end of flash_control2 */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_pmu_status */ +/** + * @defgroup at_apb_pseq_paris_regs_core_pmu_status pmu_status + * @brief pmu status information definitions. + * @{ + */ +#ifndef __PSEQ_PMU_STATUS_MACRO__ +#define __PSEQ_PMU_STATUS_MACRO__ + +/* macros for field energy4CPU */ +/** + * @defgroup at_apb_pseq_paris_regs_core_energy4CPU_field energy4CPU_field + * @brief macros for field energy4CPU + * @details enough energy is present to operation the CPU + * @{ + */ +#define PSEQ_PMU_STATUS__ENERGY4CPU__SHIFT 0 +#define PSEQ_PMU_STATUS__ENERGY4CPU__WIDTH 1 +#define PSEQ_PMU_STATUS__ENERGY4CPU__MASK 0x00000001U +#define PSEQ_PMU_STATUS__ENERGY4CPU__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PSEQ_PMU_STATUS__ENERGY4CPU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_PMU_STATUS__ENERGY4CPU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_PMU_STATUS__ENERGY4CPU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field energy4TX */ +/** + * @defgroup at_apb_pseq_paris_regs_core_energy4TX_field energy4TX_field + * @brief macros for field energy4TX + * @details enough energy is present to do a transmit + * @{ + */ +#define PSEQ_PMU_STATUS__ENERGY4TX__SHIFT 1 +#define PSEQ_PMU_STATUS__ENERGY4TX__WIDTH 1 +#define PSEQ_PMU_STATUS__ENERGY4TX__MASK 0x00000002U +#define PSEQ_PMU_STATUS__ENERGY4TX__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_PMU_STATUS__ENERGY4TX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_PMU_STATUS__ENERGY4TX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_PMU_STATUS__ENERGY4TX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field endoflife */ +/** + * @defgroup at_apb_pseq_paris_regs_core_endoflife_field endoflife_field + * @brief macros for field endoflife + * @details battery is detected to be at end of life; do not start flash writes or radio operation + * @{ + */ +#define PSEQ_PMU_STATUS__ENDOFLIFE__SHIFT 2 +#define PSEQ_PMU_STATUS__ENDOFLIFE__WIDTH 1 +#define PSEQ_PMU_STATUS__ENDOFLIFE__MASK 0x00000004U +#define PSEQ_PMU_STATUS__ENDOFLIFE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PSEQ_PMU_STATUS__ENDOFLIFE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PSEQ_PMU_STATUS__ENDOFLIFE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PSEQ_PMU_STATUS__ENDOFLIFE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field brownout */ +/** + * @defgroup at_apb_pseq_paris_regs_core_brownout_field brownout_field + * @brief macros for field brownout + * @details brownout detected; go to low power state as quickly as possible + * @{ + */ +#define PSEQ_PMU_STATUS__BROWNOUT__SHIFT 3 +#define PSEQ_PMU_STATUS__BROWNOUT__WIDTH 1 +#define PSEQ_PMU_STATUS__BROWNOUT__MASK 0x00000008U +#define PSEQ_PMU_STATUS__BROWNOUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PSEQ_PMU_STATUS__BROWNOUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PSEQ_PMU_STATUS__BROWNOUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PSEQ_PMU_STATUS__BROWNOUT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field si_det */ +/** + * @defgroup at_apb_pseq_paris_regs_core_si_det_field si_det_field + * @brief macros for field si_det + * @details tied high for B1 + * @{ + */ +#define PSEQ_PMU_STATUS__SI_DET__SHIFT 4 +#define PSEQ_PMU_STATUS__SI_DET__WIDTH 1 +#define PSEQ_PMU_STATUS__SI_DET__MASK 0x00000010U +#define PSEQ_PMU_STATUS__SI_DET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PSEQ_PMU_STATUS__SI_DET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PSEQ_PMU_STATUS__SI_DET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PSEQ_PMU_STATUS__SI_DET__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field soc_off_wkup_det */ +/** + * @defgroup at_apb_pseq_paris_regs_core_soc_off_wkup_det_field soc_off_wkup_det_field + * @brief macros for field soc_off_wkup_det + * @details returned from SOC Off state + * @{ + */ +#define PSEQ_PMU_STATUS__SOC_OFF_WKUP_DET__SHIFT 5 +#define PSEQ_PMU_STATUS__SOC_OFF_WKUP_DET__WIDTH 3 +#define PSEQ_PMU_STATUS__SOC_OFF_WKUP_DET__MASK 0x000000e0U +#define PSEQ_PMU_STATUS__SOC_OFF_WKUP_DET__READ(src) \ + (((uint32_t)(src)\ + & 0x000000e0U) >> 5) +#define PSEQ_PMU_STATUS__SOC_OFF_WKUP_DET__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_PMU_STATUS__TYPE uint32_t +#define PSEQ_PMU_STATUS__READ 0x000000ffU +#define PSEQ_PMU_STATUS__PRESERVED 0x00000000U +#define PSEQ_PMU_STATUS__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_PMU_STATUS_MACRO__ */ + +/** @} end of pmu_status */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_pmu_interrupt */ +/** + * @defgroup at_apb_pseq_paris_regs_core_pmu_interrupt pmu_interrupt + * @brief pmu interrupt source definitions. + * @{ + */ +#ifndef __PSEQ_PMU_INTERRUPT_MACRO__ +#define __PSEQ_PMU_INTERRUPT_MACRO__ + +/* macros for field energy4CPU_high */ +/** + * @defgroup at_apb_pseq_paris_regs_core_energy4CPU_high_field energy4CPU_high_field + * @brief macros for field energy4CPU_high + * @details 0 = pmu_status_energy4CPU level 1 = pmu_status_energy4CPU negated level 2 = pmu_status_energy4CPU rising edge 3 = pmu_status_energy4CPU falling edge 4 = pmu_status_energy4TX level 5 = pmu_status_energy4TX negated level 6 = pmu_status_energy4TX rising edge 7 = pmu_status_energy4TX falling edge 8 = pmu_status_endOfLife level 9 = pmu_status_endOfLife negated level 10 = pmu_status_endOfLife rising edge 11 = pmu_status_endOfLife falling edge 12 = pmu_status_brownout level 13 = pmu_status_brownout negated level 14 = pmu_status_brownout rising edge 15 = pmu_status_brownout falling edge + * @{ + */ +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_HIGH__SHIFT 0 +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_HIGH__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_HIGH__MASK 0x00000001U +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_HIGH__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_HIGH__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_HIGH__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_HIGH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_HIGH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_HIGH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field energy4CPU_low */ +/** + * @defgroup at_apb_pseq_paris_regs_core_energy4CPU_low_field energy4CPU_low_field + * @brief macros for field energy4CPU_low + * @details 0 = pmu_status_energy4CPU level 1 = pmu_status_energy4CPU negated level 2 = pmu_status_energy4CPU rising edge 3 = pmu_status_energy4CPU falling edge 4 = pmu_status_energy4TX level 5 = pmu_status_energy4TX negated level 6 = pmu_status_energy4TX rising edge 7 = pmu_status_energy4TX falling edge 8 = pmu_status_endOfLife level 9 = pmu_status_endOfLife negated level 10 = pmu_status_endOfLife rising edge 11 = pmu_status_endOfLife falling edge 12 = pmu_status_brownout level 13 = pmu_status_brownout negated level 14 = pmu_status_brownout rising edge 15 = pmu_status_brownout falling edge + * @{ + */ +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_LOW__SHIFT 1 +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_LOW__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_LOW__MASK 0x00000002U +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_LOW__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_LOW__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_LOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_LOW__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field energy4CPU_rising */ +/** + * @defgroup at_apb_pseq_paris_regs_core_energy4CPU_rising_field energy4CPU_rising_field + * @brief macros for field energy4CPU_rising + * @details 0 = pmu_status_energy4CPU level 1 = pmu_status_energy4CPU negated level 2 = pmu_status_energy4CPU rising edge 3 = pmu_status_energy4CPU falling edge 4 = pmu_status_energy4TX level 5 = pmu_status_energy4TX negated level 6 = pmu_status_energy4TX rising edge 7 = pmu_status_energy4TX falling edge 8 = pmu_status_endOfLife level 9 = pmu_status_endOfLife negated level 10 = pmu_status_endOfLife rising edge 11 = pmu_status_endOfLife falling edge 12 = pmu_status_brownout level 13 = pmu_status_brownout negated level 14 = pmu_status_brownout rising edge 15 = pmu_status_brownout falling edge + * @{ + */ +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_RISING__SHIFT 2 +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_RISING__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_RISING__MASK 0x00000004U +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_RISING__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_RISING__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_RISING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_RISING__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_RISING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_RISING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_RISING__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field energy4CPU_falling */ +/** + * @defgroup at_apb_pseq_paris_regs_core_energy4CPU_falling_field energy4CPU_falling_field + * @brief macros for field energy4CPU_falling + * @details 0 = pmu_status_energy4CPU level 1 = pmu_status_energy4CPU negated level 2 = pmu_status_energy4CPU rising edge 3 = pmu_status_energy4CPU falling edge 4 = pmu_status_energy4TX level 5 = pmu_status_energy4TX negated level 6 = pmu_status_energy4TX rising edge 7 = pmu_status_energy4TX falling edge 8 = pmu_status_endOfLife level 9 = pmu_status_endOfLife negated level 10 = pmu_status_endOfLife rising edge 11 = pmu_status_endOfLife falling edge 12 = pmu_status_brownout level 13 = pmu_status_brownout negated level 14 = pmu_status_brownout rising edge 15 = pmu_status_brownout falling edge + * @{ + */ +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_FALLING__SHIFT 3 +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_FALLING__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_FALLING__MASK 0x00000008U +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_FALLING__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_FALLING__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_FALLING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_FALLING__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_FALLING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_FALLING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PSEQ_PMU_INTERRUPT__ENERGY4CPU_FALLING__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field energy4TX_high */ +/** + * @defgroup at_apb_pseq_paris_regs_core_energy4TX_high_field energy4TX_high_field + * @brief macros for field energy4TX_high + * @details 0 = pmu_status_energy4CPU level 1 = pmu_status_energy4CPU negated level 2 = pmu_status_energy4CPU rising edge 3 = pmu_status_energy4CPU falling edge 4 = pmu_status_energy4TX level 5 = pmu_status_energy4TX negated level 6 = pmu_status_energy4TX rising edge 7 = pmu_status_energy4TX falling edge 8 = pmu_status_endOfLife level 9 = pmu_status_endOfLife negated level 10 = pmu_status_endOfLife rising edge 11 = pmu_status_endOfLife falling edge 12 = pmu_status_brownout level 13 = pmu_status_brownout negated level 14 = pmu_status_brownout rising edge 15 = pmu_status_brownout falling edge + * @{ + */ +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_HIGH__SHIFT 4 +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_HIGH__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_HIGH__MASK 0x00000010U +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_HIGH__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_HIGH__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_HIGH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_HIGH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_HIGH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_HIGH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field energy4TX_low */ +/** + * @defgroup at_apb_pseq_paris_regs_core_energy4TX_low_field energy4TX_low_field + * @brief macros for field energy4TX_low + * @details 0 = pmu_status_energy4CPU level 1 = pmu_status_energy4CPU negated level 2 = pmu_status_energy4CPU rising edge 3 = pmu_status_energy4CPU falling edge 4 = pmu_status_energy4TX level 5 = pmu_status_energy4TX negated level 6 = pmu_status_energy4TX rising edge 7 = pmu_status_energy4TX falling edge 8 = pmu_status_endOfLife level 9 = pmu_status_endOfLife negated level 10 = pmu_status_endOfLife rising edge 11 = pmu_status_endOfLife falling edge 12 = pmu_status_brownout level 13 = pmu_status_brownout negated level 14 = pmu_status_brownout rising edge 15 = pmu_status_brownout falling edge + * @{ + */ +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_LOW__SHIFT 5 +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_LOW__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_LOW__MASK 0x00000020U +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_LOW__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_LOW__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_LOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_LOW__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field energy4TX_rising */ +/** + * @defgroup at_apb_pseq_paris_regs_core_energy4TX_rising_field energy4TX_rising_field + * @brief macros for field energy4TX_rising + * @details 0 = pmu_status_energy4CPU level 1 = pmu_status_energy4CPU negated level 2 = pmu_status_energy4CPU rising edge 3 = pmu_status_energy4CPU falling edge 4 = pmu_status_energy4TX level 5 = pmu_status_energy4TX negated level 6 = pmu_status_energy4TX rising edge 7 = pmu_status_energy4TX falling edge 8 = pmu_status_endOfLife level 9 = pmu_status_endOfLife negated level 10 = pmu_status_endOfLife rising edge 11 = pmu_status_endOfLife falling edge 12 = pmu_status_brownout level 13 = pmu_status_brownout negated level 14 = pmu_status_brownout rising edge 15 = pmu_status_brownout falling edge + * @{ + */ +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_RISING__SHIFT 6 +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_RISING__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_RISING__MASK 0x00000040U +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_RISING__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_RISING__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_RISING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_RISING__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_RISING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_RISING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_RISING__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field energy4TX_falling */ +/** + * @defgroup at_apb_pseq_paris_regs_core_energy4TX_falling_field energy4TX_falling_field + * @brief macros for field energy4TX_falling + * @details 0 = pmu_status_energy4CPU level 1 = pmu_status_energy4CPU negated level 2 = pmu_status_energy4CPU rising edge 3 = pmu_status_energy4CPU falling edge 4 = pmu_status_energy4TX level 5 = pmu_status_energy4TX negated level 6 = pmu_status_energy4TX rising edge 7 = pmu_status_energy4TX falling edge 8 = pmu_status_endOfLife level 9 = pmu_status_endOfLife negated level 10 = pmu_status_endOfLife rising edge 11 = pmu_status_endOfLife falling edge 12 = pmu_status_brownout level 13 = pmu_status_brownout negated level 14 = pmu_status_brownout rising edge 15 = pmu_status_brownout falling edge + * @{ + */ +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_FALLING__SHIFT 7 +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_FALLING__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_FALLING__MASK 0x00000080U +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_FALLING__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_FALLING__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_FALLING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_FALLING__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_FALLING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_FALLING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define PSEQ_PMU_INTERRUPT__ENERGY4TX_FALLING__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field endOfLife_high */ +/** + * @defgroup at_apb_pseq_paris_regs_core_endOfLife_high_field endOfLife_high_field + * @brief macros for field endOfLife_high + * @details 0 = pmu_status_energy4CPU level 1 = pmu_status_energy4CPU negated level 2 = pmu_status_energy4CPU rising edge 3 = pmu_status_energy4CPU falling edge 4 = pmu_status_energy4TX level 5 = pmu_status_energy4TX negated level 6 = pmu_status_energy4TX rising edge 7 = pmu_status_energy4TX falling edge 8 = pmu_status_endOfLife level 9 = pmu_status_endOfLife negated level 10 = pmu_status_endOfLife rising edge 11 = pmu_status_endOfLife falling edge 12 = pmu_status_brownout level 13 = pmu_status_brownout negated level 14 = pmu_status_brownout rising edge 15 = pmu_status_brownout falling edge + * @{ + */ +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_HIGH__SHIFT 8 +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_HIGH__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_HIGH__MASK 0x00000100U +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_HIGH__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_HIGH__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_HIGH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_HIGH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_HIGH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_HIGH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field endOfLife_low */ +/** + * @defgroup at_apb_pseq_paris_regs_core_endOfLife_low_field endOfLife_low_field + * @brief macros for field endOfLife_low + * @details 0 = pmu_status_energy4CPU level 1 = pmu_status_energy4CPU negated level 2 = pmu_status_energy4CPU rising edge 3 = pmu_status_energy4CPU falling edge 4 = pmu_status_energy4TX level 5 = pmu_status_energy4TX negated level 6 = pmu_status_energy4TX rising edge 7 = pmu_status_energy4TX falling edge 8 = pmu_status_endOfLife level 9 = pmu_status_endOfLife negated level 10 = pmu_status_endOfLife rising edge 11 = pmu_status_endOfLife falling edge 12 = pmu_status_brownout level 13 = pmu_status_brownout negated level 14 = pmu_status_brownout rising edge 15 = pmu_status_brownout falling edge + * @{ + */ +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_LOW__SHIFT 9 +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_LOW__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_LOW__MASK 0x00000200U +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_LOW__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_LOW__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_LOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_LOW__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field endOfLife_rising */ +/** + * @defgroup at_apb_pseq_paris_regs_core_endOfLife_rising_field endOfLife_rising_field + * @brief macros for field endOfLife_rising + * @details 0 = pmu_status_energy4CPU level 1 = pmu_status_energy4CPU negated level 2 = pmu_status_energy4CPU rising edge 3 = pmu_status_energy4CPU falling edge 4 = pmu_status_energy4TX level 5 = pmu_status_energy4TX negated level 6 = pmu_status_energy4TX rising edge 7 = pmu_status_energy4TX falling edge 8 = pmu_status_endOfLife level 9 = pmu_status_endOfLife negated level 10 = pmu_status_endOfLife rising edge 11 = pmu_status_endOfLife falling edge 12 = pmu_status_brownout level 13 = pmu_status_brownout negated level 14 = pmu_status_brownout rising edge 15 = pmu_status_brownout falling edge + * @{ + */ +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_RISING__SHIFT 10 +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_RISING__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_RISING__MASK 0x00000400U +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_RISING__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_RISING__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_RISING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_RISING__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_RISING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_RISING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_RISING__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field endOfLife_falling */ +/** + * @defgroup at_apb_pseq_paris_regs_core_endOfLife_falling_field endOfLife_falling_field + * @brief macros for field endOfLife_falling + * @details 0 = pmu_status_energy4CPU level 1 = pmu_status_energy4CPU negated level 2 = pmu_status_energy4CPU rising edge 3 = pmu_status_energy4CPU falling edge 4 = pmu_status_energy4TX level 5 = pmu_status_energy4TX negated level 6 = pmu_status_energy4TX rising edge 7 = pmu_status_energy4TX falling edge 8 = pmu_status_endOfLife level 9 = pmu_status_endOfLife negated level 10 = pmu_status_endOfLife rising edge 11 = pmu_status_endOfLife falling edge 12 = pmu_status_brownout level 13 = pmu_status_brownout negated level 14 = pmu_status_brownout rising edge 15 = pmu_status_brownout falling edge + * @{ + */ +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_FALLING__SHIFT 11 +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_FALLING__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_FALLING__MASK 0x00000800U +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_FALLING__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_FALLING__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_FALLING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_FALLING__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_FALLING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_FALLING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define PSEQ_PMU_INTERRUPT__ENDOFLIFE_FALLING__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field brownout_high */ +/** + * @defgroup at_apb_pseq_paris_regs_core_brownout_high_field brownout_high_field + * @brief macros for field brownout_high + * @details 0 = pmu_status_energy4CPU level 1 = pmu_status_energy4CPU negated level 2 = pmu_status_energy4CPU rising edge 3 = pmu_status_energy4CPU falling edge 4 = pmu_status_energy4TX level 5 = pmu_status_energy4TX negated level 6 = pmu_status_energy4TX rising edge 7 = pmu_status_energy4TX falling edge 8 = pmu_status_endOfLife level 9 = pmu_status_endOfLife negated level 10 = pmu_status_endOfLife rising edge 11 = pmu_status_endOfLife falling edge 12 = pmu_status_brownout level 13 = pmu_status_brownout negated level 14 = pmu_status_brownout rising edge 15 = pmu_status_brownout falling edge + * @{ + */ +#define PSEQ_PMU_INTERRUPT__BROWNOUT_HIGH__SHIFT 12 +#define PSEQ_PMU_INTERRUPT__BROWNOUT_HIGH__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__BROWNOUT_HIGH__MASK 0x00001000U +#define PSEQ_PMU_INTERRUPT__BROWNOUT_HIGH__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_HIGH__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_HIGH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_HIGH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_HIGH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_HIGH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field brownout_low */ +/** + * @defgroup at_apb_pseq_paris_regs_core_brownout_low_field brownout_low_field + * @brief macros for field brownout_low + * @details 0 = pmu_status_energy4CPU level 1 = pmu_status_energy4CPU negated level 2 = pmu_status_energy4CPU rising edge 3 = pmu_status_energy4CPU falling edge 4 = pmu_status_energy4TX level 5 = pmu_status_energy4TX negated level 6 = pmu_status_energy4TX rising edge 7 = pmu_status_energy4TX falling edge 8 = pmu_status_endOfLife level 9 = pmu_status_endOfLife negated level 10 = pmu_status_endOfLife rising edge 11 = pmu_status_endOfLife falling edge 12 = pmu_status_brownout level 13 = pmu_status_brownout negated level 14 = pmu_status_brownout rising edge 15 = pmu_status_brownout falling edge + * @{ + */ +#define PSEQ_PMU_INTERRUPT__BROWNOUT_LOW__SHIFT 13 +#define PSEQ_PMU_INTERRUPT__BROWNOUT_LOW__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__BROWNOUT_LOW__MASK 0x00002000U +#define PSEQ_PMU_INTERRUPT__BROWNOUT_LOW__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_LOW__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_LOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_LOW__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field brownout_rising */ +/** + * @defgroup at_apb_pseq_paris_regs_core_brownout_rising_field brownout_rising_field + * @brief macros for field brownout_rising + * @details 0 = pmu_status_energy4CPU level 1 = pmu_status_energy4CPU negated level 2 = pmu_status_energy4CPU rising edge 3 = pmu_status_energy4CPU falling edge 4 = pmu_status_energy4TX level 5 = pmu_status_energy4TX negated level 6 = pmu_status_energy4TX rising edge 7 = pmu_status_energy4TX falling edge 8 = pmu_status_endOfLife level 9 = pmu_status_endOfLife negated level 10 = pmu_status_endOfLife rising edge 11 = pmu_status_endOfLife falling edge 12 = pmu_status_brownout level 13 = pmu_status_brownout negated level 14 = pmu_status_brownout rising edge 15 = pmu_status_brownout falling edge + * @{ + */ +#define PSEQ_PMU_INTERRUPT__BROWNOUT_RISING__SHIFT 14 +#define PSEQ_PMU_INTERRUPT__BROWNOUT_RISING__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__BROWNOUT_RISING__MASK 0x00004000U +#define PSEQ_PMU_INTERRUPT__BROWNOUT_RISING__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_RISING__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_RISING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_RISING__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_RISING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_RISING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_RISING__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field brownout_falling */ +/** + * @defgroup at_apb_pseq_paris_regs_core_brownout_falling_field brownout_falling_field + * @brief macros for field brownout_falling + * @details 0 = pmu_status_energy4CPU level 1 = pmu_status_energy4CPU negated level 2 = pmu_status_energy4CPU rising edge 3 = pmu_status_energy4CPU falling edge 4 = pmu_status_energy4TX level 5 = pmu_status_energy4TX negated level 6 = pmu_status_energy4TX rising edge 7 = pmu_status_energy4TX falling edge 8 = pmu_status_endOfLife level 9 = pmu_status_endOfLife negated level 10 = pmu_status_endOfLife rising edge 11 = pmu_status_endOfLife falling edge 12 = pmu_status_brownout level 13 = pmu_status_brownout negated level 14 = pmu_status_brownout rising edge 15 = pmu_status_brownout falling edge + * @{ + */ +#define PSEQ_PMU_INTERRUPT__BROWNOUT_FALLING__SHIFT 15 +#define PSEQ_PMU_INTERRUPT__BROWNOUT_FALLING__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__BROWNOUT_FALLING__MASK 0x00008000U +#define PSEQ_PMU_INTERRUPT__BROWNOUT_FALLING__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_FALLING__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_FALLING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_FALLING__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_FALLING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_FALLING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PSEQ_PMU_INTERRUPT__BROWNOUT_FALLING__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field si_det_high */ +/** + * @defgroup at_apb_pseq_paris_regs_core_si_det_high_field si_det_high_field + * @brief macros for field si_det_high + * @details 0 = pmu_status_energy4CPU level 1 = pmu_status_energy4CPU negated level 2 = pmu_status_energy4CPU rising edge 3 = pmu_status_energy4CPU falling edge 4 = pmu_status_energy4TX level 5 = pmu_status_energy4TX negated level 6 = pmu_status_energy4TX rising edge 7 = pmu_status_energy4TX falling edge 8 = pmu_status_endOfLife level 9 = pmu_status_endOfLife negated level 10 = pmu_status_endOfLife rising edge 11 = pmu_status_endOfLife falling edge 12 = pmu_status_brownout level 13 = pmu_status_brownout negated level 14 = pmu_status_brownout rising edge 15 = pmu_status_brownout falling edge + * @{ + */ +#define PSEQ_PMU_INTERRUPT__SI_DET_HIGH__SHIFT 16 +#define PSEQ_PMU_INTERRUPT__SI_DET_HIGH__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__SI_DET_HIGH__MASK 0x00010000U +#define PSEQ_PMU_INTERRUPT__SI_DET_HIGH__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define PSEQ_PMU_INTERRUPT__SI_DET_HIGH__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define PSEQ_PMU_INTERRUPT__SI_DET_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define PSEQ_PMU_INTERRUPT__SI_DET_HIGH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define PSEQ_PMU_INTERRUPT__SI_DET_HIGH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PSEQ_PMU_INTERRUPT__SI_DET_HIGH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PSEQ_PMU_INTERRUPT__SI_DET_HIGH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field si_det_low */ +/** + * @defgroup at_apb_pseq_paris_regs_core_si_det_low_field si_det_low_field + * @brief macros for field si_det_low + * @details 0 = pmu_status_energy4CPU level 1 = pmu_status_energy4CPU negated level 2 = pmu_status_energy4CPU rising edge 3 = pmu_status_energy4CPU falling edge 4 = pmu_status_energy4TX level 5 = pmu_status_energy4TX negated level 6 = pmu_status_energy4TX rising edge 7 = pmu_status_energy4TX falling edge 8 = pmu_status_endOfLife level 9 = pmu_status_endOfLife negated level 10 = pmu_status_endOfLife rising edge 11 = pmu_status_endOfLife falling edge 12 = pmu_status_brownout level 13 = pmu_status_brownout negated level 14 = pmu_status_brownout rising edge 15 = pmu_status_brownout falling edge + * @{ + */ +#define PSEQ_PMU_INTERRUPT__SI_DET_LOW__SHIFT 17 +#define PSEQ_PMU_INTERRUPT__SI_DET_LOW__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__SI_DET_LOW__MASK 0x00020000U +#define PSEQ_PMU_INTERRUPT__SI_DET_LOW__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define PSEQ_PMU_INTERRUPT__SI_DET_LOW__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define PSEQ_PMU_INTERRUPT__SI_DET_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define PSEQ_PMU_INTERRUPT__SI_DET_LOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define PSEQ_PMU_INTERRUPT__SI_DET_LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define PSEQ_PMU_INTERRUPT__SI_DET_LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define PSEQ_PMU_INTERRUPT__SI_DET_LOW__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field si_det_rising */ +/** + * @defgroup at_apb_pseq_paris_regs_core_si_det_rising_field si_det_rising_field + * @brief macros for field si_det_rising + * @details 0 = pmu_status_energy4CPU level 1 = pmu_status_energy4CPU negated level 2 = pmu_status_energy4CPU rising edge 3 = pmu_status_energy4CPU falling edge 4 = pmu_status_energy4TX level 5 = pmu_status_energy4TX negated level 6 = pmu_status_energy4TX rising edge 7 = pmu_status_energy4TX falling edge 8 = pmu_status_endOfLife level 9 = pmu_status_endOfLife negated level 10 = pmu_status_endOfLife rising edge 11 = pmu_status_endOfLife falling edge 12 = pmu_status_brownout level 13 = pmu_status_brownout negated level 14 = pmu_status_brownout rising edge 15 = pmu_status_brownout falling edge + * @{ + */ +#define PSEQ_PMU_INTERRUPT__SI_DET_RISING__SHIFT 18 +#define PSEQ_PMU_INTERRUPT__SI_DET_RISING__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__SI_DET_RISING__MASK 0x00040000U +#define PSEQ_PMU_INTERRUPT__SI_DET_RISING__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define PSEQ_PMU_INTERRUPT__SI_DET_RISING__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define PSEQ_PMU_INTERRUPT__SI_DET_RISING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define PSEQ_PMU_INTERRUPT__SI_DET_RISING__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define PSEQ_PMU_INTERRUPT__SI_DET_RISING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define PSEQ_PMU_INTERRUPT__SI_DET_RISING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define PSEQ_PMU_INTERRUPT__SI_DET_RISING__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field si_det_falling */ +/** + * @defgroup at_apb_pseq_paris_regs_core_si_det_falling_field si_det_falling_field + * @brief macros for field si_det_falling + * @details 0 = pmu_status_energy4CPU level 1 = pmu_status_energy4CPU negated level 2 = pmu_status_energy4CPU rising edge 3 = pmu_status_energy4CPU falling edge 4 = pmu_status_energy4TX level 5 = pmu_status_energy4TX negated level 6 = pmu_status_energy4TX rising edge 7 = pmu_status_energy4TX falling edge 8 = pmu_status_endOfLife level 9 = pmu_status_endOfLife negated level 10 = pmu_status_endOfLife rising edge 11 = pmu_status_endOfLife falling edge 12 = pmu_status_brownout level 13 = pmu_status_brownout negated level 14 = pmu_status_brownout rising edge 15 = pmu_status_brownout falling edge + * @{ + */ +#define PSEQ_PMU_INTERRUPT__SI_DET_FALLING__SHIFT 19 +#define PSEQ_PMU_INTERRUPT__SI_DET_FALLING__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__SI_DET_FALLING__MASK 0x00080000U +#define PSEQ_PMU_INTERRUPT__SI_DET_FALLING__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define PSEQ_PMU_INTERRUPT__SI_DET_FALLING__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define PSEQ_PMU_INTERRUPT__SI_DET_FALLING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define PSEQ_PMU_INTERRUPT__SI_DET_FALLING__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define PSEQ_PMU_INTERRUPT__SI_DET_FALLING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define PSEQ_PMU_INTERRUPT__SI_DET_FALLING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define PSEQ_PMU_INTERRUPT__SI_DET_FALLING__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_re_energy4CPU */ +/** + * @defgroup at_apb_pseq_paris_regs_core_clear_re_energy4CPU_field clear_re_energy4CPU_field + * @brief macros for field clear_re_energy4CPU + * @details clear the falling edge capture blocks + * @{ + */ +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENERGY4CPU__SHIFT 20 +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENERGY4CPU__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENERGY4CPU__MASK 0x00100000U +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENERGY4CPU__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENERGY4CPU__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENERGY4CPU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENERGY4CPU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENERGY4CPU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENERGY4CPU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENERGY4CPU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_re_energy4TX */ +/** + * @defgroup at_apb_pseq_paris_regs_core_clear_re_energy4TX_field clear_re_energy4TX_field + * @brief macros for field clear_re_energy4TX + * @details clear the falling edge capture blocks + * @{ + */ +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENERGY4TX__SHIFT 21 +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENERGY4TX__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENERGY4TX__MASK 0x00200000U +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENERGY4TX__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENERGY4TX__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENERGY4TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENERGY4TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENERGY4TX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENERGY4TX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENERGY4TX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_re_endOfLife */ +/** + * @defgroup at_apb_pseq_paris_regs_core_clear_re_endOfLife_field clear_re_endOfLife_field + * @brief macros for field clear_re_endOfLife + * @details clear the falling edge capture blocks + * @{ + */ +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENDOFLIFE__SHIFT 22 +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENDOFLIFE__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENDOFLIFE__MASK 0x00400000U +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENDOFLIFE__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENDOFLIFE__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENDOFLIFE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENDOFLIFE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENDOFLIFE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENDOFLIFE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_ENDOFLIFE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_re_brownout */ +/** + * @defgroup at_apb_pseq_paris_regs_core_clear_re_brownout_field clear_re_brownout_field + * @brief macros for field clear_re_brownout + * @details clear the falling edge capture blocks + * @{ + */ +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_BROWNOUT__SHIFT 23 +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_BROWNOUT__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_BROWNOUT__MASK 0x00800000U +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_BROWNOUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_BROWNOUT__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_BROWNOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_BROWNOUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_BROWNOUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_BROWNOUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_BROWNOUT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_re_si_det */ +/** + * @defgroup at_apb_pseq_paris_regs_core_clear_re_si_det_field clear_re_si_det_field + * @brief macros for field clear_re_si_det + * @details clear the falling edge capture blocks + * @{ + */ +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_SI_DET__SHIFT 24 +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_SI_DET__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_SI_DET__MASK 0x01000000U +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_SI_DET__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_SI_DET__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_SI_DET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_SI_DET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_SI_DET__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_SI_DET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define PSEQ_PMU_INTERRUPT__CLEAR_RE_SI_DET__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_fe_energy4CPU */ +/** + * @defgroup at_apb_pseq_paris_regs_core_clear_fe_energy4CPU_field clear_fe_energy4CPU_field + * @brief macros for field clear_fe_energy4CPU + * @details clear the rising edge capture blocks + * @{ + */ +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENERGY4CPU__SHIFT 25 +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENERGY4CPU__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENERGY4CPU__MASK 0x02000000U +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENERGY4CPU__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENERGY4CPU__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENERGY4CPU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENERGY4CPU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENERGY4CPU__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENERGY4CPU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENERGY4CPU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_fe_energy4TX */ +/** + * @defgroup at_apb_pseq_paris_regs_core_clear_fe_energy4TX_field clear_fe_energy4TX_field + * @brief macros for field clear_fe_energy4TX + * @details clear the rising edge capture blocks + * @{ + */ +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENERGY4TX__SHIFT 26 +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENERGY4TX__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENERGY4TX__MASK 0x04000000U +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENERGY4TX__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENERGY4TX__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENERGY4TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENERGY4TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENERGY4TX__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENERGY4TX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENERGY4TX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_fe_endOfLife */ +/** + * @defgroup at_apb_pseq_paris_regs_core_clear_fe_endOfLife_field clear_fe_endOfLife_field + * @brief macros for field clear_fe_endOfLife + * @details clear the rising edge capture blocks + * @{ + */ +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENDOFLIFE__SHIFT 27 +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENDOFLIFE__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENDOFLIFE__MASK 0x08000000U +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENDOFLIFE__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENDOFLIFE__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENDOFLIFE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENDOFLIFE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENDOFLIFE__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENDOFLIFE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_ENDOFLIFE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_fe_brownout */ +/** + * @defgroup at_apb_pseq_paris_regs_core_clear_fe_brownout_field clear_fe_brownout_field + * @brief macros for field clear_fe_brownout + * @details clear the rising edge capture blocks + * @{ + */ +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_BROWNOUT__SHIFT 28 +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_BROWNOUT__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_BROWNOUT__MASK 0x10000000U +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_BROWNOUT__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_BROWNOUT__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_BROWNOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_BROWNOUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_BROWNOUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_BROWNOUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_BROWNOUT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_fe_si_det */ +/** + * @defgroup at_apb_pseq_paris_regs_core_clear_fe_si_det_field clear_fe_si_det_field + * @brief macros for field clear_fe_si_det + * @details clear the rising edge capture blocks + * @{ + */ +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_SI_DET__SHIFT 29 +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_SI_DET__WIDTH 1 +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_SI_DET__MASK 0x20000000U +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_SI_DET__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_SI_DET__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_SI_DET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_SI_DET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_SI_DET__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_SI_DET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define PSEQ_PMU_INTERRUPT__CLEAR_FE_SI_DET__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_PMU_INTERRUPT__TYPE uint32_t +#define PSEQ_PMU_INTERRUPT__READ 0x3fffffffU +#define PSEQ_PMU_INTERRUPT__WRITE 0x3fffffffU +#define PSEQ_PMU_INTERRUPT__PRESERVED 0x00000000U +#define PSEQ_PMU_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_PMU_INTERRUPT_MACRO__ */ + +/** @} end of pmu_interrupt */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_sysram_write_block_cfg */ +/** + * @defgroup at_apb_pseq_paris_regs_core_sysram_write_block_cfg sysram_write_block_cfg + * @brief Contains register fields associated with sysram_write_block_cfg. definitions. + * @{ + */ +#ifndef __PSEQ_SYSRAM_WRITE_BLOCK_CFG_MACRO__ +#define __PSEQ_SYSRAM_WRITE_BLOCK_CFG_MACRO__ + +/* macros for field a_lo */ +/** + * @defgroup at_apb_pseq_paris_regs_core_a_lo_field a_lo_field + * @brief macros for field a_lo + * @details low address on word boundary; any address from high address to low address is no longer writable once enable is set + * @{ + */ +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__A_LO__SHIFT 0 +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__A_LO__WIDTH 13 +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__A_LO__MASK 0x00001fffU +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__A_LO__READ(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__A_LO__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__A_LO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fffU) | ((uint32_t)(src) &\ + 0x00001fffU) +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__A_LO__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00001fffU))) +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__A_LO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field a_hi */ +/** + * @defgroup at_apb_pseq_paris_regs_core_a_hi_field a_hi_field + * @brief macros for field a_hi + * @details high address on word boundary + * @{ + */ +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__A_HI__SHIFT 13 +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__A_HI__WIDTH 13 +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__A_HI__MASK 0x03ffe000U +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__A_HI__READ(src) \ + (((uint32_t)(src)\ + & 0x03ffe000U) >> 13) +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__A_HI__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x03ffe000U) +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__A_HI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03ffe000U) | (((uint32_t)(src) <<\ + 13) & 0x03ffe000U) +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__A_HI__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x03ffe000U))) +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__A_HI__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_wrblk */ +/** + * @defgroup at_apb_pseq_paris_regs_core_en_wrblk_field en_wrblk_field + * @brief macros for field en_wrblk + * @details enable the sysram write lock; can't be undone unless a porst_soc is issued by pmu + * @{ + */ +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__EN_WRBLK__SHIFT 26 +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__EN_WRBLK__WIDTH 1 +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__EN_WRBLK__MASK 0x04000000U +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__EN_WRBLK__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__EN_WRBLK__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__EN_WRBLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__EN_WRBLK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__EN_WRBLK__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__EN_WRBLK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__EN_WRBLK__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__TYPE uint32_t +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__READ 0x07ffffffU +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__WRITE 0x07ffffffU +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__PRESERVED 0x00000000U +#define PSEQ_SYSRAM_WRITE_BLOCK_CFG__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_SYSRAM_WRITE_BLOCK_CFG_MACRO__ */ + +/** @} end of sysram_write_block_cfg */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_sysram_ssrs_cfg */ +/** + * @defgroup at_apb_pseq_paris_regs_core_sysram_ssrs_cfg sysram_ssrs_cfg + * @brief Contains register fields associated with sysram_ssrs_cfg. definitions. + * @{ + */ +#ifndef __PSEQ_SYSRAM_SSRS_CFG_MACRO__ +#define __PSEQ_SYSRAM_SSRS_CFG_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_apb_pseq_paris_regs_core_addr_field addr_field + * @brief macros for field addr + * @details sysram starting address for ssrs operation + * @{ + */ +#define PSEQ_SYSRAM_SSRS_CFG__ADDR__SHIFT 0 +#define PSEQ_SYSRAM_SSRS_CFG__ADDR__WIDTH 15 +#define PSEQ_SYSRAM_SSRS_CFG__ADDR__MASK 0x00007fffU +#define PSEQ_SYSRAM_SSRS_CFG__ADDR__READ(src) ((uint32_t)(src) & 0x00007fffU) +#define PSEQ_SYSRAM_SSRS_CFG__ADDR__WRITE(src) ((uint32_t)(src) & 0x00007fffU) +#define PSEQ_SYSRAM_SSRS_CFG__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007fffU) | ((uint32_t)(src) &\ + 0x00007fffU) +#define PSEQ_SYSRAM_SSRS_CFG__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00007fffU))) +#define PSEQ_SYSRAM_SSRS_CFG__ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enable */ +/** + * @defgroup at_apb_pseq_paris_regs_core_enable_field enable_field + * @brief macros for field enable + * @details when set, enables r/w access to sysram during ssrs operation + * @{ + */ +#define PSEQ_SYSRAM_SSRS_CFG__ENABLE__SHIFT 15 +#define PSEQ_SYSRAM_SSRS_CFG__ENABLE__WIDTH 1 +#define PSEQ_SYSRAM_SSRS_CFG__ENABLE__MASK 0x00008000U +#define PSEQ_SYSRAM_SSRS_CFG__ENABLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define PSEQ_SYSRAM_SSRS_CFG__ENABLE__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define PSEQ_SYSRAM_SSRS_CFG__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define PSEQ_SYSRAM_SSRS_CFG__ENABLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define PSEQ_SYSRAM_SSRS_CFG__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PSEQ_SYSRAM_SSRS_CFG__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PSEQ_SYSRAM_SSRS_CFG__ENABLE__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_SYSRAM_SSRS_CFG__TYPE uint32_t +#define PSEQ_SYSRAM_SSRS_CFG__READ 0x0000ffffU +#define PSEQ_SYSRAM_SSRS_CFG__WRITE 0x0000ffffU +#define PSEQ_SYSRAM_SSRS_CFG__PRESERVED 0x00000000U +#define PSEQ_SYSRAM_SSRS_CFG__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_SYSRAM_SSRS_CFG_MACRO__ */ + +/** @} end of sysram_ssrs_cfg */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_interrupt_status */ +/** + * @defgroup at_apb_pseq_paris_regs_core_interrupt_status interrupt_status + * @brief interrupt status definitions. + * @{ + */ +#ifndef __PSEQ_INTERRUPT_STATUS_MACRO__ +#define __PSEQ_INTERRUPT_STATUS_MACRO__ + +/* macros for field returned_from_lp_state */ +/** + * @defgroup at_apb_pseq_paris_regs_core_returned_from_lp_state_field returned_from_lp_state_field + * @brief macros for field returned_from_lp_state + * @details indicates system returned from low power state (as oppposed to first power on) + * @{ + */ +#define PSEQ_INTERRUPT_STATUS__RETURNED_FROM_LP_STATE__SHIFT 0 +#define PSEQ_INTERRUPT_STATUS__RETURNED_FROM_LP_STATE__WIDTH 1 +#define PSEQ_INTERRUPT_STATUS__RETURNED_FROM_LP_STATE__MASK 0x00000001U +#define PSEQ_INTERRUPT_STATUS__RETURNED_FROM_LP_STATE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_INTERRUPT_STATUS__RETURNED_FROM_LP_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_INTERRUPT_STATUS__RETURNED_FROM_LP_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_INTERRUPT_STATUS__RETURNED_FROM_LP_STATE__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_INTERRUPT_STATUS__TYPE uint32_t +#define PSEQ_INTERRUPT_STATUS__READ 0x00000001U +#define PSEQ_INTERRUPT_STATUS__PRESERVED 0x00000000U +#define PSEQ_INTERRUPT_STATUS__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_INTERRUPT_STATUS_MACRO__ */ + +/** @} end of interrupt_status */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_interrupt_mask */ +/** + * @defgroup at_apb_pseq_paris_regs_core_interrupt_mask interrupt_mask + * @brief interrupt mask definitions. + * @{ + */ +#ifndef __PSEQ_INTERRUPT_MASK_MACRO__ +#define __PSEQ_INTERRUPT_MASK_MACRO__ + +/* macros for field intrpt_mask */ +/** + * @defgroup at_apb_pseq_paris_regs_core_intrpt_mask_field intrpt_mask_field + * @brief macros for field intrpt_mask + * @details if nth bit set, the nth interrupt source is allowed to propogate to core's interrupt + * @{ + */ +#define PSEQ_INTERRUPT_MASK__INTRPT_MASK__SHIFT 0 +#define PSEQ_INTERRUPT_MASK__INTRPT_MASK__WIDTH 1 +#define PSEQ_INTERRUPT_MASK__INTRPT_MASK__MASK 0x00000001U +#define PSEQ_INTERRUPT_MASK__INTRPT_MASK__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_INTERRUPT_MASK__INTRPT_MASK__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_INTERRUPT_MASK__INTRPT_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_INTERRUPT_MASK__INTRPT_MASK__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_INTERRUPT_MASK__INTRPT_MASK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_INTERRUPT_MASK__INTRPT_MASK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_INTERRUPT_MASK__INTRPT_MASK__RESET_VALUE 0x00000001U +/** @} */ +#define PSEQ_INTERRUPT_MASK__TYPE uint32_t +#define PSEQ_INTERRUPT_MASK__READ 0x00000001U +#define PSEQ_INTERRUPT_MASK__WRITE 0x00000001U +#define PSEQ_INTERRUPT_MASK__PRESERVED 0x00000000U +#define PSEQ_INTERRUPT_MASK__RESET_VALUE 0x00000001U + +#endif /* __PSEQ_INTERRUPT_MASK_MACRO__ */ + +/** @} end of interrupt_mask */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_reset_interrupt */ +/** + * @defgroup at_apb_pseq_paris_regs_core_reset_interrupt reset_interrupt + * @brief interrupt resets definitions. + * @{ + */ +#ifndef __PSEQ_RESET_INTERRUPT_MACRO__ +#define __PSEQ_RESET_INTERRUPT_MACRO__ + +/* macros for field intrpt_reset */ +/** + * @defgroup at_apb_pseq_paris_regs_core_intrpt_reset_field intrpt_reset_field + * @brief macros for field intrpt_reset + * @details not self clearing + * @{ + */ +#define PSEQ_RESET_INTERRUPT__INTRPT_RESET__SHIFT 0 +#define PSEQ_RESET_INTERRUPT__INTRPT_RESET__WIDTH 1 +#define PSEQ_RESET_INTERRUPT__INTRPT_RESET__MASK 0x00000001U +#define PSEQ_RESET_INTERRUPT__INTRPT_RESET__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_RESET_INTERRUPT__INTRPT_RESET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_RESET_INTERRUPT__INTRPT_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_RESET_INTERRUPT__INTRPT_RESET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_RESET_INTERRUPT__INTRPT_RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_RESET_INTERRUPT__INTRPT_RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_RESET_INTERRUPT__INTRPT_RESET__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_RESET_INTERRUPT__TYPE uint32_t +#define PSEQ_RESET_INTERRUPT__READ 0x00000001U +#define PSEQ_RESET_INTERRUPT__WRITE 0x00000001U +#define PSEQ_RESET_INTERRUPT__PRESERVED 0x00000000U +#define PSEQ_RESET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_RESET_INTERRUPT_MACRO__ */ + +/** @} end of reset_interrupt */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_fpga_cfg */ +/** + * @defgroup at_apb_pseq_paris_regs_core_fpga_cfg fpga_cfg + * @brief Contains register fields associated with fpga_cfg. definitions. + * @{ + */ +#ifndef __PSEQ_FPGA_CFG_MACRO__ +#define __PSEQ_FPGA_CFG_MACRO__ + +/* macros for field cfg */ +/** + * @defgroup at_apb_pseq_paris_regs_core_cfg_field cfg_field + * @brief macros for field cfg + * @{ + */ +#define PSEQ_FPGA_CFG__CFG__SHIFT 0 +#define PSEQ_FPGA_CFG__CFG__WIDTH 16 +#define PSEQ_FPGA_CFG__CFG__MASK 0x0000ffffU +#define PSEQ_FPGA_CFG__CFG__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define PSEQ_FPGA_CFG__CFG__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define PSEQ_FPGA_CFG__CFG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define PSEQ_FPGA_CFG__CFG__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define PSEQ_FPGA_CFG__CFG__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_FPGA_CFG__TYPE uint32_t +#define PSEQ_FPGA_CFG__READ 0x0000ffffU +#define PSEQ_FPGA_CFG__WRITE 0x0000ffffU +#define PSEQ_FPGA_CFG__PRESERVED 0x00000000U +#define PSEQ_FPGA_CFG__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_FPGA_CFG_MACRO__ */ + +/** @} end of fpga_cfg */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_pll */ +/** + * @defgroup at_apb_pseq_paris_regs_core_pll pll + * @brief Contains register fields associated with pll. definitions. + * @{ + */ +#ifndef __PSEQ_PLL_MACRO__ +#define __PSEQ_PLL_MACRO__ + +/* macros for field filtr */ +/** + * @defgroup at_apb_pseq_paris_regs_core_filtr_field filtr_field + * @brief macros for field filtr + * @{ + */ +#define PSEQ_PLL__FILTR__SHIFT 4 +#define PSEQ_PLL__FILTR__WIDTH 4 +#define PSEQ_PLL__FILTR__MASK 0x000000f0U +#define PSEQ_PLL__FILTR__READ(src) (((uint32_t)(src) & 0x000000f0U) >> 4) +#define PSEQ_PLL__FILTR__WRITE(src) (((uint32_t)(src) << 4) & 0x000000f0U) +#define PSEQ_PLL__FILTR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define PSEQ_PLL__FILTR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define PSEQ_PLL__FILTR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field filtc */ +/** + * @defgroup at_apb_pseq_paris_regs_core_filtc_field filtc_field + * @brief macros for field filtc + * @{ + */ +#define PSEQ_PLL__FILTC__SHIFT 8 +#define PSEQ_PLL__FILTC__WIDTH 2 +#define PSEQ_PLL__FILTC__MASK 0x00000300U +#define PSEQ_PLL__FILTC__READ(src) (((uint32_t)(src) & 0x00000300U) >> 8) +#define PSEQ_PLL__FILTC__WRITE(src) (((uint32_t)(src) << 8) & 0x00000300U) +#define PSEQ_PLL__FILTC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((uint32_t)(src) <<\ + 8) & 0x00000300U) +#define PSEQ_PLL__FILTC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000300U))) +#define PSEQ_PLL__FILTC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cpcur */ +/** + * @defgroup at_apb_pseq_paris_regs_core_cpcur_field cpcur_field + * @brief macros for field cpcur + * @{ + */ +#define PSEQ_PLL__CPCUR__SHIFT 10 +#define PSEQ_PLL__CPCUR__WIDTH 6 +#define PSEQ_PLL__CPCUR__MASK 0x0000fc00U +#define PSEQ_PLL__CPCUR__READ(src) (((uint32_t)(src) & 0x0000fc00U) >> 10) +#define PSEQ_PLL__CPCUR__WRITE(src) (((uint32_t)(src) << 10) & 0x0000fc00U) +#define PSEQ_PLL__CPCUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fc00U) | (((uint32_t)(src) <<\ + 10) & 0x0000fc00U) +#define PSEQ_PLL__CPCUR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x0000fc00U))) +#define PSEQ_PLL__CPCUR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field div2out */ +/** + * @defgroup at_apb_pseq_paris_regs_core_div2out_field div2out_field + * @brief macros for field div2out + * @{ + */ +#define PSEQ_PLL__DIV2OUT__SHIFT 16 +#define PSEQ_PLL__DIV2OUT__WIDTH 1 +#define PSEQ_PLL__DIV2OUT__MASK 0x00010000U +#define PSEQ_PLL__DIV2OUT__READ(src) (((uint32_t)(src) & 0x00010000U) >> 16) +#define PSEQ_PLL__DIV2OUT__WRITE(src) (((uint32_t)(src) << 16) & 0x00010000U) +#define PSEQ_PLL__DIV2OUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define PSEQ_PLL__DIV2OUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define PSEQ_PLL__DIV2OUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PSEQ_PLL__DIV2OUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PSEQ_PLL__DIV2OUT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field divout */ +/** + * @defgroup at_apb_pseq_paris_regs_core_divout_field divout_field + * @brief macros for field divout + * @{ + */ +#define PSEQ_PLL__DIVOUT__SHIFT 17 +#define PSEQ_PLL__DIVOUT__WIDTH 3 +#define PSEQ_PLL__DIVOUT__MASK 0x000e0000U +#define PSEQ_PLL__DIVOUT__READ(src) (((uint32_t)(src) & 0x000e0000U) >> 17) +#define PSEQ_PLL__DIVOUT__WRITE(src) (((uint32_t)(src) << 17) & 0x000e0000U) +#define PSEQ_PLL__DIVOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((uint32_t)(src) <<\ + 17) & 0x000e0000U) +#define PSEQ_PLL__DIVOUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x000e0000U))) +#define PSEQ_PLL__DIVOUT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field divfb */ +/** + * @defgroup at_apb_pseq_paris_regs_core_divfb_field divfb_field + * @brief macros for field divfb + * @{ + */ +#define PSEQ_PLL__DIVFB__SHIFT 20 +#define PSEQ_PLL__DIVFB__WIDTH 6 +#define PSEQ_PLL__DIVFB__MASK 0x03f00000U +#define PSEQ_PLL__DIVFB__READ(src) (((uint32_t)(src) & 0x03f00000U) >> 20) +#define PSEQ_PLL__DIVFB__WRITE(src) (((uint32_t)(src) << 20) & 0x03f00000U) +#define PSEQ_PLL__DIVFB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03f00000U) | (((uint32_t)(src) <<\ + 20) & 0x03f00000U) +#define PSEQ_PLL__DIVFB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x03f00000U))) +#define PSEQ_PLL__DIVFB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field divref */ +/** + * @defgroup at_apb_pseq_paris_regs_core_divref_field divref_field + * @brief macros for field divref + * @{ + */ +#define PSEQ_PLL__DIVREF__SHIFT 26 +#define PSEQ_PLL__DIVREF__WIDTH 3 +#define PSEQ_PLL__DIVREF__MASK 0x1c000000U +#define PSEQ_PLL__DIVREF__READ(src) (((uint32_t)(src) & 0x1c000000U) >> 26) +#define PSEQ_PLL__DIVREF__WRITE(src) (((uint32_t)(src) << 26) & 0x1c000000U) +#define PSEQ_PLL__DIVREF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((uint32_t)(src) <<\ + 26) & 0x1c000000U) +#define PSEQ_PLL__DIVREF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x1c000000U))) +#define PSEQ_PLL__DIVREF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field divaccess */ +/** + * @defgroup at_apb_pseq_paris_regs_core_divaccess_field divaccess_field + * @brief macros for field divaccess + * @{ + */ +#define PSEQ_PLL__DIVACCESS__SHIFT 29 +#define PSEQ_PLL__DIVACCESS__WIDTH 1 +#define PSEQ_PLL__DIVACCESS__MASK 0x20000000U +#define PSEQ_PLL__DIVACCESS__READ(src) (((uint32_t)(src) & 0x20000000U) >> 29) +#define PSEQ_PLL__DIVACCESS__WRITE(src) (((uint32_t)(src) << 29) & 0x20000000U) +#define PSEQ_PLL__DIVACCESS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define PSEQ_PLL__DIVACCESS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define PSEQ_PLL__DIVACCESS__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define PSEQ_PLL__DIVACCESS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define PSEQ_PLL__DIVACCESS__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_PLL__TYPE uint32_t +#define PSEQ_PLL__READ 0x3ffffff0U +#define PSEQ_PLL__WRITE 0x3ffffff0U +#define PSEQ_PLL__PRESERVED 0x00000000U +#define PSEQ_PLL__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_PLL_MACRO__ */ + +/** @} end of pll */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_radio_status */ +/** + * @defgroup at_apb_pseq_paris_regs_core_radio_status radio_status + * @brief Contains register fields associated with radio_status. definitions. + * @{ + */ +#ifndef __PSEQ_RADIO_STATUS_MACRO__ +#define __PSEQ_RADIO_STATUS_MACRO__ + +/* macros for field xtal_stable */ +/** + * @defgroup at_apb_pseq_paris_regs_core_xtal_stable_field xtal_stable_field + * @brief macros for field xtal_stable + * @{ + */ +#define PSEQ_RADIO_STATUS__XTAL_STABLE__SHIFT 0 +#define PSEQ_RADIO_STATUS__XTAL_STABLE__WIDTH 1 +#define PSEQ_RADIO_STATUS__XTAL_STABLE__MASK 0x00000001U +#define PSEQ_RADIO_STATUS__XTAL_STABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_RADIO_STATUS__XTAL_STABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_RADIO_STATUS__XTAL_STABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_RADIO_STATUS__XTAL_STABLE__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_RADIO_STATUS__TYPE uint32_t +#define PSEQ_RADIO_STATUS__READ 0x00000001U +#define PSEQ_RADIO_STATUS__PRESERVED 0x00000000U +#define PSEQ_RADIO_STATUS__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_RADIO_STATUS_MACRO__ */ + +/** @} end of radio_status */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_rram_read_config_lo */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rram_read_config_lo rram_read_config_lo + * @brief Contains register fields associated with rram_read_config_lo. definitions. + * @{ + */ +#ifndef __PSEQ_RRAM_READ_CONFIG_LO_MACRO__ +#define __PSEQ_RRAM_READ_CONFIG_LO_MACRO__ + +/* macros for field dout */ +/** + * @defgroup at_apb_pseq_paris_regs_core_dout_field dout_field + * @brief macros for field dout + * @{ + */ +#define PSEQ_RRAM_READ_CONFIG_LO__DOUT__SHIFT 0 +#define PSEQ_RRAM_READ_CONFIG_LO__DOUT__WIDTH 32 +#define PSEQ_RRAM_READ_CONFIG_LO__DOUT__MASK 0xffffffffU +#define PSEQ_RRAM_READ_CONFIG_LO__DOUT__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define PSEQ_RRAM_READ_CONFIG_LO__DOUT__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_RRAM_READ_CONFIG_LO__TYPE uint32_t +#define PSEQ_RRAM_READ_CONFIG_LO__READ 0xffffffffU +#define PSEQ_RRAM_READ_CONFIG_LO__PRESERVED 0x00000000U +#define PSEQ_RRAM_READ_CONFIG_LO__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_RRAM_READ_CONFIG_LO_MACRO__ */ + +/** @} end of rram_read_config_lo */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_rram_read_config_hi */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rram_read_config_hi rram_read_config_hi + * @brief Contains register fields associated with rram_read_config_hi. definitions. + * @{ + */ +#ifndef __PSEQ_RRAM_READ_CONFIG_HI_MACRO__ +#define __PSEQ_RRAM_READ_CONFIG_HI_MACRO__ + +/* macros for field dout */ +/** + * @defgroup at_apb_pseq_paris_regs_core_dout_field dout_field + * @brief macros for field dout + * @{ + */ +#define PSEQ_RRAM_READ_CONFIG_HI__DOUT__SHIFT 0 +#define PSEQ_RRAM_READ_CONFIG_HI__DOUT__WIDTH 32 +#define PSEQ_RRAM_READ_CONFIG_HI__DOUT__MASK 0xffffffffU +#define PSEQ_RRAM_READ_CONFIG_HI__DOUT__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define PSEQ_RRAM_READ_CONFIG_HI__DOUT__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_RRAM_READ_CONFIG_HI__TYPE uint32_t +#define PSEQ_RRAM_READ_CONFIG_HI__READ 0xffffffffU +#define PSEQ_RRAM_READ_CONFIG_HI__PRESERVED 0x00000000U +#define PSEQ_RRAM_READ_CONFIG_HI__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_RRAM_READ_CONFIG_HI_MACRO__ */ + +/** @} end of rram_read_config_hi */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_sensor_hub_imm_breakout_mask */ +/** + * @defgroup at_apb_pseq_paris_regs_core_sensor_hub_imm_breakout_mask sensor_hub_imm_breakout_mask + * @brief control signals for sensor hub definitions. + * @{ + */ +#ifndef __PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK_MACRO__ +#define __PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK_MACRO__ + +/* macros for field watch_gpio */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_gpio_field watch_gpio_field + * @brief macros for field watch_gpio + * @details valid to immediately breakout on gpio activity + * @{ + */ +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_GPIO__SHIFT 0 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_GPIO__WIDTH 1 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_GPIO__MASK 0x00000001U +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_GPIO__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_GPIO__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_GPIO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_GPIO__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_GPIO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_GPIO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_GPIO__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field watch_cntdown */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_cntdown_field watch_cntdown_field + * @brief macros for field watch_cntdown + * @details valid to immediately breakout on count down timer expiring + * @{ + */ +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_CNTDOWN__SHIFT 1 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_CNTDOWN__WIDTH 1 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_CNTDOWN__MASK 0x00000002U +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_CNTDOWN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_CNTDOWN__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_CNTDOWN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_CNTDOWN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_CNTDOWN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_CNTDOWN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_CNTDOWN__RESET_VALUE \ + 0x00000001U +/** @} */ + +/* macros for field watch_wurx0 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_wurx0_field watch_wurx0_field + * @brief macros for field watch_wurx0 + * @details valid to immediately breakout on wurx0 detect + * @{ + */ +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX0__SHIFT 2 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX0__WIDTH 1 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX0__MASK 0x00000004U +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX0__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX0__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX0__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field watch_wurx1 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_wurx1_field watch_wurx1_field + * @brief macros for field watch_wurx1 + * @details valid to immediately breakout on wurx1 detect + * @{ + */ +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX1__SHIFT 3 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX1__WIDTH 1 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX1__MASK 0x00000008U +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX1__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX1__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field watch_qdec */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_qdec_field watch_qdec_field + * @brief macros for field watch_qdec + * @details valid to immediately breakout on qdec activity + * @{ + */ +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_QDEC__SHIFT 4 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_QDEC__WIDTH 1 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_QDEC__MASK 0x00000010U +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_QDEC__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_QDEC__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_QDEC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_QDEC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_QDEC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_QDEC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_QDEC__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field watch_ksm */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_ksm_field watch_ksm_field + * @brief macros for field watch_ksm + * @details valid to immediately breakout on keyboard activity + * @{ + */ +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_KSM__SHIFT 5 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_KSM__WIDTH 1 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_KSM__MASK 0x00000020U +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_KSM__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_KSM__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_KSM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_KSM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_KSM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_KSM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_KSM__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field watch_shub */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_shub_field watch_shub_field + * @brief macros for field watch_shub + * @details valid to immediately breakout on sensor hub trigger + * @{ + */ +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_SHUB__SHIFT 6 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_SHUB__WIDTH 1 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_SHUB__MASK 0x00000040U +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_SHUB__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_SHUB__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_SHUB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_SHUB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_SHUB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_SHUB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_SHUB__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field watch_spi */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_spi_field watch_spi_field + * @brief macros for field watch_spi + * @details valid to immediately breakout on spi slave activity + * @{ + */ +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_SPI__SHIFT 7 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_SPI__WIDTH 1 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_SPI__MASK 0x00000080U +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_SPI__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_SPI__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_SPI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_SPI__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_SPI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_SPI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_SPI__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field watch_i2c */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_i2c_field watch_i2c_field + * @brief macros for field watch_i2c + * @details valid to immediately breakout on i2c slave activity + * @{ + */ +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_I2C__SHIFT 8 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_I2C__WIDTH 1 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_I2C__MASK 0x00000100U +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_I2C__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_I2C__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_I2C__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_I2C__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_I2C__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_I2C__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_I2C__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field watch_pmu_lpcomp */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_pmu_lpcomp_field watch_pmu_lpcomp_field + * @brief macros for field watch_pmu_lpcomp + * @details valid to immediately breakout on pmu lpcomp threshold crossing + * @{ + */ +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_PMU_LPCOMP__SHIFT 9 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_PMU_LPCOMP__WIDTH 1 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_PMU_LPCOMP__MASK 0x00000200U +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_PMU_LPCOMP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_PMU_LPCOMP__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_PMU_LPCOMP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_PMU_LPCOMP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_PMU_LPCOMP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_PMU_LPCOMP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_PMU_LPCOMP__RESET_VALUE \ + 0x00000001U +/** @} */ + +/* macros for field watch_pmu_timer */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_pmu_timer_field watch_pmu_timer_field + * @brief macros for field watch_pmu_timer + * @details valid to immediately breakout on pmu timer expiring + * @{ + */ +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_PMU_TIMER__SHIFT 10 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_PMU_TIMER__WIDTH 1 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_PMU_TIMER__MASK 0x00000400U +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_PMU_TIMER__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_PMU_TIMER__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_PMU_TIMER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_PMU_TIMER__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_PMU_TIMER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_PMU_TIMER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_PMU_TIMER__RESET_VALUE \ + 0x00000001U +/** @} */ + +/* macros for field watch_energy4CPU */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_energy4CPU_field watch_energy4CPU_field + * @brief macros for field watch_energy4CPU + * @details valid to immediately breakout on pmu asserting energy4CPU + * @{ + */ +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENERGY4CPU__SHIFT 11 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENERGY4CPU__WIDTH 1 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENERGY4CPU__MASK 0x00000800U +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENERGY4CPU__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENERGY4CPU__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENERGY4CPU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENERGY4CPU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENERGY4CPU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENERGY4CPU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENERGY4CPU__RESET_VALUE \ + 0x00000001U +/** @} */ + +/* macros for field watch_energy4TX */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_energy4TX_field watch_energy4TX_field + * @brief macros for field watch_energy4TX + * @details valid to immediately breakout on pmu asserting energy4TX + * @{ + */ +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENERGY4TX__SHIFT 12 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENERGY4TX__WIDTH 1 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENERGY4TX__MASK 0x00001000U +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENERGY4TX__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENERGY4TX__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENERGY4TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENERGY4TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENERGY4TX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENERGY4TX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENERGY4TX__RESET_VALUE \ + 0x00000001U +/** @} */ + +/* macros for field watch_endoflife */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_endoflife_field watch_endoflife_field + * @brief macros for field watch_endoflife + * @details valid to immediately breakout on pmu asserting endoflife + * @{ + */ +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENDOFLIFE__SHIFT 13 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENDOFLIFE__WIDTH 1 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENDOFLIFE__MASK 0x00002000U +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENDOFLIFE__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENDOFLIFE__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENDOFLIFE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENDOFLIFE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENDOFLIFE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENDOFLIFE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_ENDOFLIFE__RESET_VALUE \ + 0x00000001U +/** @} */ + +/* macros for field watch_brownout */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_brownout_field watch_brownout_field + * @brief macros for field watch_brownout + * @details valid to immediately breakout on pmu asserting brownout + * @{ + */ +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_BROWNOUT__SHIFT 14 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_BROWNOUT__WIDTH 1 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_BROWNOUT__MASK 0x00004000U +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_BROWNOUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_BROWNOUT__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_BROWNOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_BROWNOUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_BROWNOUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_BROWNOUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_BROWNOUT__RESET_VALUE \ + 0x00000001U +/** @} */ + +/* macros for field watch_wurx */ +/** + * @defgroup at_apb_pseq_paris_regs_core_watch_wurx_field watch_wurx_field + * @brief macros for field watch_wurx + * @details valid to immediately breakout on multiple wurx detects in certain amount of time + * @{ + */ +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX__SHIFT 15 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX__WIDTH 1 +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX__MASK 0x00008000U +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WATCH_WURX__RESET_VALUE 0x00000001U +/** @} */ +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__TYPE uint32_t +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__READ 0x0000ffffU +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__WRITE 0x0000ffffU +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__PRESERVED 0x00000000U +#define PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK__RESET_VALUE 0x0000ffffU + +#endif /* __PSEQ_SENSOR_HUB_IMM_BREAKOUT_MASK_MACRO__ */ + +/** @} end of sensor_hub_imm_breakout_mask */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_fsm_tuningA */ +/** + * @defgroup at_apb_pseq_paris_regs_core_fsm_tuningA fsm_tuningA + * @brief Contains register fields associated with fsm_tuningA. definitions. + * @{ + */ +#ifndef __PSEQ_FSM_TUNINGA_MACRO__ +#define __PSEQ_FSM_TUNINGA_MACRO__ + +/* macros for field cnt0 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_cnt0_field cnt0_field + * @brief macros for field cnt0 + * @details additional clk_lpc cycles to wait in states tied to cnt0 + * @{ + */ +#define PSEQ_FSM_TUNINGA__CNT0__SHIFT 0 +#define PSEQ_FSM_TUNINGA__CNT0__WIDTH 3 +#define PSEQ_FSM_TUNINGA__CNT0__MASK 0x00000007U +#define PSEQ_FSM_TUNINGA__CNT0__READ(src) ((uint32_t)(src) & 0x00000007U) +#define PSEQ_FSM_TUNINGA__CNT0__WRITE(src) ((uint32_t)(src) & 0x00000007U) +#define PSEQ_FSM_TUNINGA__CNT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define PSEQ_FSM_TUNINGA__CNT0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define PSEQ_FSM_TUNINGA__CNT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cnt1 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_cnt1_field cnt1_field + * @brief macros for field cnt1 + * @details additional clk_lpc cycles to wait in states tied to cnt1 + * @{ + */ +#define PSEQ_FSM_TUNINGA__CNT1__SHIFT 3 +#define PSEQ_FSM_TUNINGA__CNT1__WIDTH 3 +#define PSEQ_FSM_TUNINGA__CNT1__MASK 0x00000038U +#define PSEQ_FSM_TUNINGA__CNT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define PSEQ_FSM_TUNINGA__CNT1__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define PSEQ_FSM_TUNINGA__CNT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define PSEQ_FSM_TUNINGA__CNT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define PSEQ_FSM_TUNINGA__CNT1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cnt2 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_cnt2_field cnt2_field + * @brief macros for field cnt2 + * @details additional clk_lpc cycles to wait in states tied to cnt2 + * @{ + */ +#define PSEQ_FSM_TUNINGA__CNT2__SHIFT 6 +#define PSEQ_FSM_TUNINGA__CNT2__WIDTH 3 +#define PSEQ_FSM_TUNINGA__CNT2__MASK 0x000001c0U +#define PSEQ_FSM_TUNINGA__CNT2__READ(src) \ + (((uint32_t)(src)\ + & 0x000001c0U) >> 6) +#define PSEQ_FSM_TUNINGA__CNT2__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000001c0U) +#define PSEQ_FSM_TUNINGA__CNT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((uint32_t)(src) <<\ + 6) & 0x000001c0U) +#define PSEQ_FSM_TUNINGA__CNT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000001c0U))) +#define PSEQ_FSM_TUNINGA__CNT2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cnt3 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_cnt3_field cnt3_field + * @brief macros for field cnt3 + * @details additional clk_lpc cycles to wait in states tied to cnt3 + * @{ + */ +#define PSEQ_FSM_TUNINGA__CNT3__SHIFT 9 +#define PSEQ_FSM_TUNINGA__CNT3__WIDTH 3 +#define PSEQ_FSM_TUNINGA__CNT3__MASK 0x00000e00U +#define PSEQ_FSM_TUNINGA__CNT3__READ(src) \ + (((uint32_t)(src)\ + & 0x00000e00U) >> 9) +#define PSEQ_FSM_TUNINGA__CNT3__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000e00U) +#define PSEQ_FSM_TUNINGA__CNT3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((uint32_t)(src) <<\ + 9) & 0x00000e00U) +#define PSEQ_FSM_TUNINGA__CNT3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000e00U))) +#define PSEQ_FSM_TUNINGA__CNT3__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cnt4 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_cnt4_field cnt4_field + * @brief macros for field cnt4 + * @details additional clk_lpc cycles to wait in states tied to cnt4 + * @{ + */ +#define PSEQ_FSM_TUNINGA__CNT4__SHIFT 12 +#define PSEQ_FSM_TUNINGA__CNT4__WIDTH 3 +#define PSEQ_FSM_TUNINGA__CNT4__MASK 0x00007000U +#define PSEQ_FSM_TUNINGA__CNT4__READ(src) \ + (((uint32_t)(src)\ + & 0x00007000U) >> 12) +#define PSEQ_FSM_TUNINGA__CNT4__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00007000U) +#define PSEQ_FSM_TUNINGA__CNT4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((uint32_t)(src) <<\ + 12) & 0x00007000U) +#define PSEQ_FSM_TUNINGA__CNT4__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00007000U))) +#define PSEQ_FSM_TUNINGA__CNT4__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cnt5 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_cnt5_field cnt5_field + * @brief macros for field cnt5 + * @details additional clk_lpc cycles to wait in states tied to cnt5 + * @{ + */ +#define PSEQ_FSM_TUNINGA__CNT5__SHIFT 15 +#define PSEQ_FSM_TUNINGA__CNT5__WIDTH 3 +#define PSEQ_FSM_TUNINGA__CNT5__MASK 0x00038000U +#define PSEQ_FSM_TUNINGA__CNT5__READ(src) \ + (((uint32_t)(src)\ + & 0x00038000U) >> 15) +#define PSEQ_FSM_TUNINGA__CNT5__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00038000U) +#define PSEQ_FSM_TUNINGA__CNT5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((uint32_t)(src) <<\ + 15) & 0x00038000U) +#define PSEQ_FSM_TUNINGA__CNT5__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00038000U))) +#define PSEQ_FSM_TUNINGA__CNT5__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field cnt6 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_cnt6_field cnt6_field + * @brief macros for field cnt6 + * @details additional clk_lpc cycles to wait in states tied to cnt6 + * @{ + */ +#define PSEQ_FSM_TUNINGA__CNT6__SHIFT 18 +#define PSEQ_FSM_TUNINGA__CNT6__WIDTH 3 +#define PSEQ_FSM_TUNINGA__CNT6__MASK 0x001c0000U +#define PSEQ_FSM_TUNINGA__CNT6__READ(src) \ + (((uint32_t)(src)\ + & 0x001c0000U) >> 18) +#define PSEQ_FSM_TUNINGA__CNT6__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x001c0000U) +#define PSEQ_FSM_TUNINGA__CNT6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((uint32_t)(src) <<\ + 18) & 0x001c0000U) +#define PSEQ_FSM_TUNINGA__CNT6__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x001c0000U))) +#define PSEQ_FSM_TUNINGA__CNT6__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cnt7 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_cnt7_field cnt7_field + * @brief macros for field cnt7 + * @details additional clk_lpc cycles to wait in states tied to cnt7 + * @{ + */ +#define PSEQ_FSM_TUNINGA__CNT7__SHIFT 21 +#define PSEQ_FSM_TUNINGA__CNT7__WIDTH 3 +#define PSEQ_FSM_TUNINGA__CNT7__MASK 0x00e00000U +#define PSEQ_FSM_TUNINGA__CNT7__READ(src) \ + (((uint32_t)(src)\ + & 0x00e00000U) >> 21) +#define PSEQ_FSM_TUNINGA__CNT7__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00e00000U) +#define PSEQ_FSM_TUNINGA__CNT7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((uint32_t)(src) <<\ + 21) & 0x00e00000U) +#define PSEQ_FSM_TUNINGA__CNT7__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00e00000U))) +#define PSEQ_FSM_TUNINGA__CNT7__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cnt8 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_cnt8_field cnt8_field + * @brief macros for field cnt8 + * @details additional clk_lpc cycles to wait in states tied to cnt8 + * @{ + */ +#define PSEQ_FSM_TUNINGA__CNT8__SHIFT 24 +#define PSEQ_FSM_TUNINGA__CNT8__WIDTH 3 +#define PSEQ_FSM_TUNINGA__CNT8__MASK 0x07000000U +#define PSEQ_FSM_TUNINGA__CNT8__READ(src) \ + (((uint32_t)(src)\ + & 0x07000000U) >> 24) +#define PSEQ_FSM_TUNINGA__CNT8__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x07000000U) +#define PSEQ_FSM_TUNINGA__CNT8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((uint32_t)(src) <<\ + 24) & 0x07000000U) +#define PSEQ_FSM_TUNINGA__CNT8__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x07000000U))) +#define PSEQ_FSM_TUNINGA__CNT8__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cnt9_lsb */ +/** + * @defgroup at_apb_pseq_paris_regs_core_cnt9_lsb_field cnt9_lsb_field + * @brief macros for field cnt9_lsb + * @details additional clk_lpc cycles to wait in states tied to cnt9 (lsb's); determines cpu_ldo wait to setttle time + * @{ + */ +#define PSEQ_FSM_TUNINGA__CNT9_LSB__SHIFT 27 +#define PSEQ_FSM_TUNINGA__CNT9_LSB__WIDTH 5 +#define PSEQ_FSM_TUNINGA__CNT9_LSB__MASK 0xf8000000U +#define PSEQ_FSM_TUNINGA__CNT9_LSB__READ(src) \ + (((uint32_t)(src)\ + & 0xf8000000U) >> 27) +#define PSEQ_FSM_TUNINGA__CNT9_LSB__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0xf8000000U) +#define PSEQ_FSM_TUNINGA__CNT9_LSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((uint32_t)(src) <<\ + 27) & 0xf8000000U) +#define PSEQ_FSM_TUNINGA__CNT9_LSB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0xf8000000U))) +#define PSEQ_FSM_TUNINGA__CNT9_LSB__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_FSM_TUNINGA__TYPE uint32_t +#define PSEQ_FSM_TUNINGA__READ 0xffffffffU +#define PSEQ_FSM_TUNINGA__WRITE 0xffffffffU +#define PSEQ_FSM_TUNINGA__PRESERVED 0x00000000U +#define PSEQ_FSM_TUNINGA__RESET_VALUE 0x00008000U + +#endif /* __PSEQ_FSM_TUNINGA_MACRO__ */ + +/** @} end of fsm_tuningA */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_fsm_tuningB */ +/** + * @defgroup at_apb_pseq_paris_regs_core_fsm_tuningB fsm_tuningB + * @brief Contains register fields associated with fsm_tuningB. definitions. + * @{ + */ +#ifndef __PSEQ_FSM_TUNINGB_MACRO__ +#define __PSEQ_FSM_TUNINGB_MACRO__ + +/* macros for field rcnt0 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rcnt0_field rcnt0_field + * @brief macros for field rcnt0 + * @details additional clk_lpc cycles to wait in states tied to rcnt0 + * @{ + */ +#define PSEQ_FSM_TUNINGB__RCNT0__SHIFT 0 +#define PSEQ_FSM_TUNINGB__RCNT0__WIDTH 3 +#define PSEQ_FSM_TUNINGB__RCNT0__MASK 0x00000007U +#define PSEQ_FSM_TUNINGB__RCNT0__READ(src) ((uint32_t)(src) & 0x00000007U) +#define PSEQ_FSM_TUNINGB__RCNT0__WRITE(src) ((uint32_t)(src) & 0x00000007U) +#define PSEQ_FSM_TUNINGB__RCNT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define PSEQ_FSM_TUNINGB__RCNT0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define PSEQ_FSM_TUNINGB__RCNT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rcnt1 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rcnt1_field rcnt1_field + * @brief macros for field rcnt1 + * @details additional clk_lpc cycles to wait in states tied to rcnt1 + * @{ + */ +#define PSEQ_FSM_TUNINGB__RCNT1__SHIFT 3 +#define PSEQ_FSM_TUNINGB__RCNT1__WIDTH 3 +#define PSEQ_FSM_TUNINGB__RCNT1__MASK 0x00000038U +#define PSEQ_FSM_TUNINGB__RCNT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define PSEQ_FSM_TUNINGB__RCNT1__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define PSEQ_FSM_TUNINGB__RCNT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define PSEQ_FSM_TUNINGB__RCNT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define PSEQ_FSM_TUNINGB__RCNT1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rcnt2 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rcnt2_field rcnt2_field + * @brief macros for field rcnt2 + * @details additional clk_lpc cycles to wait in states tied to rcnt2 + * @{ + */ +#define PSEQ_FSM_TUNINGB__RCNT2__SHIFT 6 +#define PSEQ_FSM_TUNINGB__RCNT2__WIDTH 3 +#define PSEQ_FSM_TUNINGB__RCNT2__MASK 0x000001c0U +#define PSEQ_FSM_TUNINGB__RCNT2__READ(src) \ + (((uint32_t)(src)\ + & 0x000001c0U) >> 6) +#define PSEQ_FSM_TUNINGB__RCNT2__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000001c0U) +#define PSEQ_FSM_TUNINGB__RCNT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((uint32_t)(src) <<\ + 6) & 0x000001c0U) +#define PSEQ_FSM_TUNINGB__RCNT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000001c0U))) +#define PSEQ_FSM_TUNINGB__RCNT2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rcnt3 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rcnt3_field rcnt3_field + * @brief macros for field rcnt3 + * @details additional clk_lpc cycles to wait in states tied to rcnt3 + * @{ + */ +#define PSEQ_FSM_TUNINGB__RCNT3__SHIFT 9 +#define PSEQ_FSM_TUNINGB__RCNT3__WIDTH 3 +#define PSEQ_FSM_TUNINGB__RCNT3__MASK 0x00000e00U +#define PSEQ_FSM_TUNINGB__RCNT3__READ(src) \ + (((uint32_t)(src)\ + & 0x00000e00U) >> 9) +#define PSEQ_FSM_TUNINGB__RCNT3__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000e00U) +#define PSEQ_FSM_TUNINGB__RCNT3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((uint32_t)(src) <<\ + 9) & 0x00000e00U) +#define PSEQ_FSM_TUNINGB__RCNT3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000e00U))) +#define PSEQ_FSM_TUNINGB__RCNT3__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rcnt4 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rcnt4_field rcnt4_field + * @brief macros for field rcnt4 + * @details additional clk_lpc cycles to wait in states tied to rcnt4 + * @{ + */ +#define PSEQ_FSM_TUNINGB__RCNT4__SHIFT 12 +#define PSEQ_FSM_TUNINGB__RCNT4__WIDTH 3 +#define PSEQ_FSM_TUNINGB__RCNT4__MASK 0x00007000U +#define PSEQ_FSM_TUNINGB__RCNT4__READ(src) \ + (((uint32_t)(src)\ + & 0x00007000U) >> 12) +#define PSEQ_FSM_TUNINGB__RCNT4__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00007000U) +#define PSEQ_FSM_TUNINGB__RCNT4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((uint32_t)(src) <<\ + 12) & 0x00007000U) +#define PSEQ_FSM_TUNINGB__RCNT4__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00007000U))) +#define PSEQ_FSM_TUNINGB__RCNT4__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rcnt5 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rcnt5_field rcnt5_field + * @brief macros for field rcnt5 + * @details additional clk_lpc cycles to wait in states tied to rcnt5 + * @{ + */ +#define PSEQ_FSM_TUNINGB__RCNT5__SHIFT 15 +#define PSEQ_FSM_TUNINGB__RCNT5__WIDTH 3 +#define PSEQ_FSM_TUNINGB__RCNT5__MASK 0x00038000U +#define PSEQ_FSM_TUNINGB__RCNT5__READ(src) \ + (((uint32_t)(src)\ + & 0x00038000U) >> 15) +#define PSEQ_FSM_TUNINGB__RCNT5__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00038000U) +#define PSEQ_FSM_TUNINGB__RCNT5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((uint32_t)(src) <<\ + 15) & 0x00038000U) +#define PSEQ_FSM_TUNINGB__RCNT5__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00038000U))) +#define PSEQ_FSM_TUNINGB__RCNT5__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rcnt6 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rcnt6_field rcnt6_field + * @brief macros for field rcnt6 + * @details additional clk_lpc cycles to wait in states tied to rcnt6 + * @{ + */ +#define PSEQ_FSM_TUNINGB__RCNT6__SHIFT 18 +#define PSEQ_FSM_TUNINGB__RCNT6__WIDTH 3 +#define PSEQ_FSM_TUNINGB__RCNT6__MASK 0x001c0000U +#define PSEQ_FSM_TUNINGB__RCNT6__READ(src) \ + (((uint32_t)(src)\ + & 0x001c0000U) >> 18) +#define PSEQ_FSM_TUNINGB__RCNT6__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x001c0000U) +#define PSEQ_FSM_TUNINGB__RCNT6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((uint32_t)(src) <<\ + 18) & 0x001c0000U) +#define PSEQ_FSM_TUNINGB__RCNT6__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x001c0000U))) +#define PSEQ_FSM_TUNINGB__RCNT6__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rcnt7 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rcnt7_field rcnt7_field + * @brief macros for field rcnt7 + * @details additional clk_lpc cycles to wait in states tied to rcnt7 + * @{ + */ +#define PSEQ_FSM_TUNINGB__RCNT7__SHIFT 21 +#define PSEQ_FSM_TUNINGB__RCNT7__WIDTH 3 +#define PSEQ_FSM_TUNINGB__RCNT7__MASK 0x00e00000U +#define PSEQ_FSM_TUNINGB__RCNT7__READ(src) \ + (((uint32_t)(src)\ + & 0x00e00000U) >> 21) +#define PSEQ_FSM_TUNINGB__RCNT7__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00e00000U) +#define PSEQ_FSM_TUNINGB__RCNT7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((uint32_t)(src) <<\ + 21) & 0x00e00000U) +#define PSEQ_FSM_TUNINGB__RCNT7__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00e00000U))) +#define PSEQ_FSM_TUNINGB__RCNT7__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rcnt8 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rcnt8_field rcnt8_field + * @brief macros for field rcnt8 + * @details additional clk_lpc cycles to wait in states tied to rcnt8 + * @{ + */ +#define PSEQ_FSM_TUNINGB__RCNT8__SHIFT 24 +#define PSEQ_FSM_TUNINGB__RCNT8__WIDTH 3 +#define PSEQ_FSM_TUNINGB__RCNT8__MASK 0x07000000U +#define PSEQ_FSM_TUNINGB__RCNT8__READ(src) \ + (((uint32_t)(src)\ + & 0x07000000U) >> 24) +#define PSEQ_FSM_TUNINGB__RCNT8__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x07000000U) +#define PSEQ_FSM_TUNINGB__RCNT8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((uint32_t)(src) <<\ + 24) & 0x07000000U) +#define PSEQ_FSM_TUNINGB__RCNT8__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x07000000U))) +#define PSEQ_FSM_TUNINGB__RCNT8__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rcnt9 */ +/** + * @defgroup at_apb_pseq_paris_regs_core_rcnt9_field rcnt9_field + * @brief macros for field rcnt9 + * @details additional clk_lpc cycles to wait in states tied to rcnt9 + * @{ + */ +#define PSEQ_FSM_TUNINGB__RCNT9__SHIFT 27 +#define PSEQ_FSM_TUNINGB__RCNT9__WIDTH 3 +#define PSEQ_FSM_TUNINGB__RCNT9__MASK 0x38000000U +#define PSEQ_FSM_TUNINGB__RCNT9__READ(src) \ + (((uint32_t)(src)\ + & 0x38000000U) >> 27) +#define PSEQ_FSM_TUNINGB__RCNT9__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x38000000U) +#define PSEQ_FSM_TUNINGB__RCNT9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x38000000U) | (((uint32_t)(src) <<\ + 27) & 0x38000000U) +#define PSEQ_FSM_TUNINGB__RCNT9__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x38000000U))) +#define PSEQ_FSM_TUNINGB__RCNT9__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cnt9_msb */ +/** + * @defgroup at_apb_pseq_paris_regs_core_cnt9_msb_field cnt9_msb_field + * @brief macros for field cnt9_msb + * @details additional clk_lpc cycles to wait in states tied to cnt9 (msb's) + * @{ + */ +#define PSEQ_FSM_TUNINGB__CNT9_MSB__SHIFT 30 +#define PSEQ_FSM_TUNINGB__CNT9_MSB__WIDTH 2 +#define PSEQ_FSM_TUNINGB__CNT9_MSB__MASK 0xc0000000U +#define PSEQ_FSM_TUNINGB__CNT9_MSB__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define PSEQ_FSM_TUNINGB__CNT9_MSB__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define PSEQ_FSM_TUNINGB__CNT9_MSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define PSEQ_FSM_TUNINGB__CNT9_MSB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define PSEQ_FSM_TUNINGB__CNT9_MSB__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_FSM_TUNINGB__TYPE uint32_t +#define PSEQ_FSM_TUNINGB__READ 0xffffffffU +#define PSEQ_FSM_TUNINGB__WRITE 0xffffffffU +#define PSEQ_FSM_TUNINGB__PRESERVED 0x00000000U +#define PSEQ_FSM_TUNINGB__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_FSM_TUNINGB_MACRO__ */ + +/** @} end of fsm_tuningB */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_wdog_control */ +/** + * @defgroup at_apb_pseq_paris_regs_core_wdog_control wdog_control + * @brief control signals for 32KHz watchdog timer definitions. + * @{ + */ +#ifndef __PSEQ_WDOG_CONTROL_MACRO__ +#define __PSEQ_WDOG_CONTROL_MACRO__ + +/* macros for field disable */ +/** + * @defgroup at_apb_pseq_paris_regs_core_disable_field disable_field + * @brief macros for field disable + * @details 1= disables wdog timer + * @{ + */ +#define PSEQ_WDOG_CONTROL__DISABLE__SHIFT 0 +#define PSEQ_WDOG_CONTROL__DISABLE__WIDTH 1 +#define PSEQ_WDOG_CONTROL__DISABLE__MASK 0x00000001U +#define PSEQ_WDOG_CONTROL__DISABLE__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PSEQ_WDOG_CONTROL__DISABLE__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PSEQ_WDOG_CONTROL__DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PSEQ_WDOG_CONTROL__DISABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PSEQ_WDOG_CONTROL__DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PSEQ_WDOG_CONTROL__DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PSEQ_WDOG_CONTROL__DISABLE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field timer_val_sel */ +/** + * @defgroup at_apb_pseq_paris_regs_core_timer_val_sel_field timer_val_sel_field + * @brief macros for field timer_val_sel + * @details selects timer value to load 1= 1-sec 0= 100-msec in 32KHz cycles + * @{ + */ +#define PSEQ_WDOG_CONTROL__TIMER_VAL_SEL__SHIFT 1 +#define PSEQ_WDOG_CONTROL__TIMER_VAL_SEL__WIDTH 1 +#define PSEQ_WDOG_CONTROL__TIMER_VAL_SEL__MASK 0x00000002U +#define PSEQ_WDOG_CONTROL__TIMER_VAL_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PSEQ_WDOG_CONTROL__TIMER_VAL_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PSEQ_WDOG_CONTROL__TIMER_VAL_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PSEQ_WDOG_CONTROL__TIMER_VAL_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PSEQ_WDOG_CONTROL__TIMER_VAL_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PSEQ_WDOG_CONTROL__TIMER_VAL_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PSEQ_WDOG_CONTROL__TIMER_VAL_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field internal_scan */ +/** + * @defgroup at_apb_pseq_paris_regs_core_internal_scan_field internal_scan_field + * @brief macros for field internal_scan + * @{ + */ +#define PSEQ_WDOG_CONTROL__INTERNAL_SCAN__SHIFT 2 +#define PSEQ_WDOG_CONTROL__INTERNAL_SCAN__WIDTH 1 +#define PSEQ_WDOG_CONTROL__INTERNAL_SCAN__MASK 0x00000004U +#define PSEQ_WDOG_CONTROL__INTERNAL_SCAN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PSEQ_WDOG_CONTROL__INTERNAL_SCAN__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PSEQ_WDOG_CONTROL__INTERNAL_SCAN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PSEQ_WDOG_CONTROL__INTERNAL_SCAN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PSEQ_WDOG_CONTROL__INTERNAL_SCAN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PSEQ_WDOG_CONTROL__INTERNAL_SCAN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PSEQ_WDOG_CONTROL__INTERNAL_SCAN__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_WDOG_CONTROL__TYPE uint32_t +#define PSEQ_WDOG_CONTROL__READ 0x00000007U +#define PSEQ_WDOG_CONTROL__WRITE 0x00000007U +#define PSEQ_WDOG_CONTROL__PRESERVED 0x00000000U +#define PSEQ_WDOG_CONTROL__RESET_VALUE 0x00000001U + +#endif /* __PSEQ_WDOG_CONTROL_MACRO__ */ + +/** @} end of wdog_control */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_wdog_timer */ +/** + * @defgroup at_apb_pseq_paris_regs_core_wdog_timer wdog_timer + * @brief Read current 32KHz watchdog timer value definitions. + * @{ + */ +#ifndef __PSEQ_WDOG_TIMER_MACRO__ +#define __PSEQ_WDOG_TIMER_MACRO__ + +/* macros for field val */ +/** + * @defgroup at_apb_pseq_paris_regs_core_val_field val_field + * @brief macros for field val + * @details this value is on 32kHz domain; read twice and check value is the same; if it's not, reread + * @{ + */ +#define PSEQ_WDOG_TIMER__VAL__SHIFT 0 +#define PSEQ_WDOG_TIMER__VAL__WIDTH 16 +#define PSEQ_WDOG_TIMER__VAL__MASK 0x0000ffffU +#define PSEQ_WDOG_TIMER__VAL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define PSEQ_WDOG_TIMER__VAL__RESET_VALUE 0x00000000U +/** @} */ +#define PSEQ_WDOG_TIMER__TYPE uint32_t +#define PSEQ_WDOG_TIMER__READ 0x0000ffffU +#define PSEQ_WDOG_TIMER__PRESERVED 0x00000000U +#define PSEQ_WDOG_TIMER__RESET_VALUE 0x00000000U + +#endif /* __PSEQ_WDOG_TIMER_MACRO__ */ + +/** @} end of wdog_timer */ + +/* macros for BlueprintGlobalNameSpace::PSEQ_core_id */ +/** + * @defgroup at_apb_pseq_paris_regs_core_core_id core_id + * @brief core's id definitions. + * @{ + */ +#ifndef __PSEQ_CORE_ID_MACRO__ +#define __PSEQ_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_pseq_paris_regs_core_id_field id_field + * @brief macros for field id + * @details PSEQ in ASCII + * @{ + */ +#define PSEQ_CORE_ID__ID__SHIFT 0 +#define PSEQ_CORE_ID__ID__WIDTH 32 +#define PSEQ_CORE_ID__ID__MASK 0xffffffffU +#define PSEQ_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PSEQ_CORE_ID__ID__RESET_VALUE 0x50534551U +/** @} */ +#define PSEQ_CORE_ID__TYPE uint32_t +#define PSEQ_CORE_ID__READ 0xffffffffU +#define PSEQ_CORE_ID__PRESERVED 0x00000000U +#define PSEQ_CORE_ID__RESET_VALUE 0x50534551U + +#endif /* __PSEQ_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of AT_APB_PSEQ_PARIS_REGS_CORE */ +#define PSEQ_SYSRAM_SSRS_BLOCK_SIZE 1952 +#endif /* __REG_AT_APB_PSEQ_PARIS_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_apb_pwm_regs_core_macro.h b/ATM33xx-5/include/reg/at_apb_pwm_regs_core_macro.h new file mode 100644 index 0000000..f4a70dd --- /dev/null +++ b/ATM33xx-5/include/reg/at_apb_pwm_regs_core_macro.h @@ -0,0 +1,3570 @@ +/* */ +/* File: at_apb_pwm_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_apb_pwm_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_APB_PWM_REGS_CORE_H__ +#define __REG_AT_APB_PWM_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_APB_PWM_REGS_CORE at_apb_pwm_regs_core + * @ingroup AT_REG + * @brief at_apb_pwm_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm_ctrl */ +/** + * @defgroup at_apb_pwm_regs_core_pwm_ctrl pwm_ctrl + * @brief control signals for all pwm channels definitions. + * @{ + */ +#ifndef __PWM_PWM_CTRL_MACRO__ +#define __PWM_PWM_CTRL_MACRO__ + +/* macros for field alt_ok_to_run */ +/** + * @defgroup at_apb_pwm_regs_core_alt_ok_to_run_field alt_ok_to_run_field + * @brief macros for field alt_ok_to_run + * @details alternative mechanism to start pwm channels; useful if application requires all used pwm channels start together [0] = start pwm0 channel [1] = start pwm1 channel [2] = start pwm2 channel [3] = start pwm3 channel [4] = start pwm4 channel [5] = start pwm5 channel [6] = start pwm6 channel [7] = start pwm7 channel + * @{ + */ +#define PWM_PWM_CTRL__ALT_OK_TO_RUN__SHIFT 0 +#define PWM_PWM_CTRL__ALT_OK_TO_RUN__WIDTH 8 +#define PWM_PWM_CTRL__ALT_OK_TO_RUN__MASK 0x000000ffU +#define PWM_PWM_CTRL__ALT_OK_TO_RUN__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define PWM_PWM_CTRL__ALT_OK_TO_RUN__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define PWM_PWM_CTRL__ALT_OK_TO_RUN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define PWM_PWM_CTRL__ALT_OK_TO_RUN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define PWM_PWM_CTRL__ALT_OK_TO_RUN__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM_CTRL__TYPE uint32_t +#define PWM_PWM_CTRL__READ 0x000000ffU +#define PWM_PWM_CTRL__WRITE 0x000000ffU +#define PWM_PWM_CTRL__PRESERVED 0x00000000U +#define PWM_PWM_CTRL__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM_CTRL_MACRO__ */ + +/** @} end of pwm_ctrl */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm0_ctrl */ +/** + * @defgroup at_apb_pwm_regs_core_pwm0_ctrl pwm0_ctrl + * @brief control signals for pwm0 channel definitions. + * @{ + */ +#ifndef __PWM_PWM0_CTRL_MACRO__ +#define __PWM_PWM0_CTRL_MACRO__ + +/* macros for field ok_to_run */ +/** + * @defgroup at_apb_pwm_regs_core_ok_to_run_field ok_to_run_field + * @brief macros for field ok_to_run + * @details start pwm channel with its rising edge. Its de-assertion stops the channel at the end of the next frame. + * @{ + */ +#define PWM_PWM0_CTRL__OK_TO_RUN__SHIFT 0 +#define PWM_PWM0_CTRL__OK_TO_RUN__WIDTH 1 +#define PWM_PWM0_CTRL__OK_TO_RUN__MASK 0x00000001U +#define PWM_PWM0_CTRL__OK_TO_RUN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PWM_PWM0_CTRL__OK_TO_RUN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PWM_PWM0_CTRL__OK_TO_RUN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PWM_PWM0_CTRL__OK_TO_RUN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PWM_PWM0_CTRL__OK_TO_RUN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PWM_PWM0_CTRL__OK_TO_RUN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PWM_PWM0_CTRL__OK_TO_RUN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mode */ +/** + * @defgroup at_apb_pwm_regs_core_mode_field mode_field + * @brief macros for field mode + * @details mode of operations: 00 = CONTINUOUS_MODE: each frame is repeated indefinately. hi_dur and lo_dur parameters are sampled once per frame. 01 = COUNTER_MODE: a group of frames is run once after ok_to_run is set. hi_dur and lo_dur parameters are sampled once at the start of the group. 10 = IR_MODE: a group of frames is run and repeated indefinitely after ok_to_run is set. hi_dur, lo_dur and frame_count paramters are sampled once before each group is run. 11 = IR_FIFO_MODE: the same IR_MODE but the group parameters are pulled from the fifo. The mode is reserved if the fifo is not assigned to the channel. + * @{ + */ +#define PWM_PWM0_CTRL__MODE__SHIFT 1 +#define PWM_PWM0_CTRL__MODE__WIDTH 2 +#define PWM_PWM0_CTRL__MODE__MASK 0x00000006U +#define PWM_PWM0_CTRL__MODE__READ(src) (((uint32_t)(src) & 0x00000006U) >> 1) +#define PWM_PWM0_CTRL__MODE__WRITE(src) (((uint32_t)(src) << 1) & 0x00000006U) +#define PWM_PWM0_CTRL__MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000006U) | (((uint32_t)(src) <<\ + 1) & 0x00000006U) +#define PWM_PWM0_CTRL__MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000006U))) +#define PWM_PWM0_CTRL__MODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field invert */ +/** + * @defgroup at_apb_pwm_regs_core_invert_field invert_field + * @brief macros for field invert + * @details invert pwm output. + * @{ + */ +#define PWM_PWM0_CTRL__INVERT__SHIFT 3 +#define PWM_PWM0_CTRL__INVERT__WIDTH 1 +#define PWM_PWM0_CTRL__INVERT__MASK 0x00000008U +#define PWM_PWM0_CTRL__INVERT__READ(src) (((uint32_t)(src) & 0x00000008U) >> 3) +#define PWM_PWM0_CTRL__INVERT__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PWM_PWM0_CTRL__INVERT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PWM_PWM0_CTRL__INVERT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PWM_PWM0_CTRL__INVERT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PWM_PWM0_CTRL__INVERT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PWM_PWM0_CTRL__INVERT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field idle_polarity */ +/** + * @defgroup at_apb_pwm_regs_core_idle_polarity_field idle_polarity_field + * @brief macros for field idle_polarity + * @details polarity in idle state + * @{ + */ +#define PWM_PWM0_CTRL__IDLE_POLARITY__SHIFT 4 +#define PWM_PWM0_CTRL__IDLE_POLARITY__WIDTH 1 +#define PWM_PWM0_CTRL__IDLE_POLARITY__MASK 0x00000010U +#define PWM_PWM0_CTRL__IDLE_POLARITY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PWM_PWM0_CTRL__IDLE_POLARITY__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PWM_PWM0_CTRL__IDLE_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PWM_PWM0_CTRL__IDLE_POLARITY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PWM_PWM0_CTRL__IDLE_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PWM_PWM0_CTRL__IDLE_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PWM_PWM0_CTRL__IDLE_POLARITY__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM0_CTRL__TYPE uint32_t +#define PWM_PWM0_CTRL__READ 0x0000001fU +#define PWM_PWM0_CTRL__WRITE 0x0000001fU +#define PWM_PWM0_CTRL__PRESERVED 0x00000000U +#define PWM_PWM0_CTRL__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM0_CTRL_MACRO__ */ + +/** @} end of pwm0_ctrl */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm0_dur */ +/** + * @defgroup at_apb_pwm_regs_core_pwm0_dur pwm0_dur + * @brief durations config for pwm0 channel definitions. + * @{ + */ +#ifndef __PWM_PWM0_DUR_MACRO__ +#define __PWM_PWM0_DUR_MACRO__ + +/* macros for field lo_dur */ +/** + * @defgroup at_apb_pwm_regs_core_lo_dur_field lo_dur_field + * @brief macros for field lo_dur + * @details duration of low portion of period in clk_mpc clock cycles = lo_dur. (lo_dur=1/hi_dur=0 not supported) + * @{ + */ +#define PWM_PWM0_DUR__LO_DUR__SHIFT 0 +#define PWM_PWM0_DUR__LO_DUR__WIDTH 16 +#define PWM_PWM0_DUR__LO_DUR__MASK 0x0000ffffU +#define PWM_PWM0_DUR__LO_DUR__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define PWM_PWM0_DUR__LO_DUR__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define PWM_PWM0_DUR__LO_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define PWM_PWM0_DUR__LO_DUR__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define PWM_PWM0_DUR__LO_DUR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hi_dur */ +/** + * @defgroup at_apb_pwm_regs_core_hi_dur_field hi_dur_field + * @brief macros for field hi_dur + * @details duration of high portion of period in clk_mpc clock cycles = hi_dur. (hi_dur=1/lo_dur=0 not supported) + * @{ + */ +#define PWM_PWM0_DUR__HI_DUR__SHIFT 16 +#define PWM_PWM0_DUR__HI_DUR__WIDTH 16 +#define PWM_PWM0_DUR__HI_DUR__MASK 0xffff0000U +#define PWM_PWM0_DUR__HI_DUR__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define PWM_PWM0_DUR__HI_DUR__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0xffff0000U) +#define PWM_PWM0_DUR__HI_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define PWM_PWM0_DUR__HI_DUR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define PWM_PWM0_DUR__HI_DUR__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM0_DUR__TYPE uint32_t +#define PWM_PWM0_DUR__READ 0xffffffffU +#define PWM_PWM0_DUR__WRITE 0xffffffffU +#define PWM_PWM0_DUR__PRESERVED 0x00000000U +#define PWM_PWM0_DUR__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM0_DUR_MACRO__ */ + +/** @} end of pwm0_dur */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm0_cfg */ +/** + * @defgroup at_apb_pwm_regs_core_pwm0_cfg pwm0_cfg + * @brief configuration for pwm0 channel definitions. + * @{ + */ +#ifndef __PWM_PWM0_CFG_MACRO__ +#define __PWM_PWM0_CFG_MACRO__ + +/* macros for field frame_count */ +/** + * @defgroup at_apb_pwm_regs_core_frame_count_field frame_count_field + * @brief macros for field frame_count + * @details number of frames in the group = frame_count + 1 + * @{ + */ +#define PWM_PWM0_CFG__FRAME_COUNT__SHIFT 0 +#define PWM_PWM0_CFG__FRAME_COUNT__WIDTH 14 +#define PWM_PWM0_CFG__FRAME_COUNT__MASK 0x00003fffU +#define PWM_PWM0_CFG__FRAME_COUNT__READ(src) ((uint32_t)(src) & 0x00003fffU) +#define PWM_PWM0_CFG__FRAME_COUNT__WRITE(src) ((uint32_t)(src) & 0x00003fffU) +#define PWM_PWM0_CFG__FRAME_COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((uint32_t)(src) &\ + 0x00003fffU) +#define PWM_PWM0_CFG__FRAME_COUNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00003fffU))) +#define PWM_PWM0_CFG__FRAME_COUNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field update */ +/** + * @defgroup at_apb_pwm_regs_core_update_field update_field + * @brief macros for field update + * @details this bit synchronize channel parameters (lo/hi dur + frame count) update, when set it triggers HW capture and it auto-cleares afterwards during CONTINUOUS and IR_FIFO modes, this bit is don't care. + * @{ + */ +#define PWM_PWM0_CFG__UPDATE__SHIFT 31 +#define PWM_PWM0_CFG__UPDATE__WIDTH 1 +#define PWM_PWM0_CFG__UPDATE__MASK 0x80000000U +#define PWM_PWM0_CFG__UPDATE__READ(src) (((uint32_t)(src) & 0x80000000U) >> 31) +#define PWM_PWM0_CFG__UPDATE__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define PWM_PWM0_CFG__UPDATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define PWM_PWM0_CFG__UPDATE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define PWM_PWM0_CFG__UPDATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PWM_PWM0_CFG__UPDATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PWM_PWM0_CFG__UPDATE__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM0_CFG__TYPE uint32_t +#define PWM_PWM0_CFG__READ 0x80003fffU +#define PWM_PWM0_CFG__WRITE 0x80003fffU +#define PWM_PWM0_CFG__PRESERVED 0x00000000U +#define PWM_PWM0_CFG__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM0_CFG_MACRO__ */ + +/** @} end of pwm0_cfg */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm1_ctrl */ +/** + * @defgroup at_apb_pwm_regs_core_pwm1_ctrl pwm1_ctrl + * @brief control signals for pwm1 channel definitions. + * @{ + */ +#ifndef __PWM_PWM1_CTRL_MACRO__ +#define __PWM_PWM1_CTRL_MACRO__ + +/* macros for field ok_to_run */ +/** + * @defgroup at_apb_pwm_regs_core_ok_to_run_field ok_to_run_field + * @brief macros for field ok_to_run + * @details start pwm channel with its rising edge. Its de-assertion stops the channel at the end of the next frame. + * @{ + */ +#define PWM_PWM1_CTRL__OK_TO_RUN__SHIFT 0 +#define PWM_PWM1_CTRL__OK_TO_RUN__WIDTH 1 +#define PWM_PWM1_CTRL__OK_TO_RUN__MASK 0x00000001U +#define PWM_PWM1_CTRL__OK_TO_RUN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PWM_PWM1_CTRL__OK_TO_RUN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PWM_PWM1_CTRL__OK_TO_RUN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PWM_PWM1_CTRL__OK_TO_RUN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PWM_PWM1_CTRL__OK_TO_RUN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PWM_PWM1_CTRL__OK_TO_RUN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PWM_PWM1_CTRL__OK_TO_RUN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mode */ +/** + * @defgroup at_apb_pwm_regs_core_mode_field mode_field + * @brief macros for field mode + * @details mode of operations: 00 = CONTINUOUS_MODE: each frame is repeated indefinately. hi_dur and lo_dur parameters are sampled once per frame. 01 = COUNTER_MODE: a group of frames is run once after ok_to_run is set. hi_dur and lo_dur parameters are sampled once at the start of the group. 10 = IR_MODE: a group of frames is run and repeated indefinitely after ok_to_run is set. hi_dur, lo_dur and frame_count paramters are sampled once before each group is run. 11 = IR_FIFO_MODE: the same IR_MODE but the group parameters are pulled from the fifo. The mode is reserved if the fifo is not assigned to the channel. + * @{ + */ +#define PWM_PWM1_CTRL__MODE__SHIFT 1 +#define PWM_PWM1_CTRL__MODE__WIDTH 2 +#define PWM_PWM1_CTRL__MODE__MASK 0x00000006U +#define PWM_PWM1_CTRL__MODE__READ(src) (((uint32_t)(src) & 0x00000006U) >> 1) +#define PWM_PWM1_CTRL__MODE__WRITE(src) (((uint32_t)(src) << 1) & 0x00000006U) +#define PWM_PWM1_CTRL__MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000006U) | (((uint32_t)(src) <<\ + 1) & 0x00000006U) +#define PWM_PWM1_CTRL__MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000006U))) +#define PWM_PWM1_CTRL__MODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field invert */ +/** + * @defgroup at_apb_pwm_regs_core_invert_field invert_field + * @brief macros for field invert + * @details invert pwm output. + * @{ + */ +#define PWM_PWM1_CTRL__INVERT__SHIFT 3 +#define PWM_PWM1_CTRL__INVERT__WIDTH 1 +#define PWM_PWM1_CTRL__INVERT__MASK 0x00000008U +#define PWM_PWM1_CTRL__INVERT__READ(src) (((uint32_t)(src) & 0x00000008U) >> 3) +#define PWM_PWM1_CTRL__INVERT__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PWM_PWM1_CTRL__INVERT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PWM_PWM1_CTRL__INVERT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PWM_PWM1_CTRL__INVERT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PWM_PWM1_CTRL__INVERT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PWM_PWM1_CTRL__INVERT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field idle_polarity */ +/** + * @defgroup at_apb_pwm_regs_core_idle_polarity_field idle_polarity_field + * @brief macros for field idle_polarity + * @details polarity in idle state + * @{ + */ +#define PWM_PWM1_CTRL__IDLE_POLARITY__SHIFT 4 +#define PWM_PWM1_CTRL__IDLE_POLARITY__WIDTH 1 +#define PWM_PWM1_CTRL__IDLE_POLARITY__MASK 0x00000010U +#define PWM_PWM1_CTRL__IDLE_POLARITY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PWM_PWM1_CTRL__IDLE_POLARITY__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PWM_PWM1_CTRL__IDLE_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PWM_PWM1_CTRL__IDLE_POLARITY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PWM_PWM1_CTRL__IDLE_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PWM_PWM1_CTRL__IDLE_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PWM_PWM1_CTRL__IDLE_POLARITY__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM1_CTRL__TYPE uint32_t +#define PWM_PWM1_CTRL__READ 0x0000001fU +#define PWM_PWM1_CTRL__WRITE 0x0000001fU +#define PWM_PWM1_CTRL__PRESERVED 0x00000000U +#define PWM_PWM1_CTRL__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM1_CTRL_MACRO__ */ + +/** @} end of pwm1_ctrl */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm1_dur */ +/** + * @defgroup at_apb_pwm_regs_core_pwm1_dur pwm1_dur + * @brief durations config for pwm1 channel definitions. + * @{ + */ +#ifndef __PWM_PWM1_DUR_MACRO__ +#define __PWM_PWM1_DUR_MACRO__ + +/* macros for field lo_dur */ +/** + * @defgroup at_apb_pwm_regs_core_lo_dur_field lo_dur_field + * @brief macros for field lo_dur + * @details duration of low portion of period in clk_mpc clock cycles = lo_dur. (lo_dur=1/hi_dur=0 not supported) + * @{ + */ +#define PWM_PWM1_DUR__LO_DUR__SHIFT 0 +#define PWM_PWM1_DUR__LO_DUR__WIDTH 16 +#define PWM_PWM1_DUR__LO_DUR__MASK 0x0000ffffU +#define PWM_PWM1_DUR__LO_DUR__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define PWM_PWM1_DUR__LO_DUR__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define PWM_PWM1_DUR__LO_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define PWM_PWM1_DUR__LO_DUR__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define PWM_PWM1_DUR__LO_DUR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hi_dur */ +/** + * @defgroup at_apb_pwm_regs_core_hi_dur_field hi_dur_field + * @brief macros for field hi_dur + * @details duration of high portion of period in clk_mpc clock cycles = hi_dur. (hi_dur=1/lo_dur=0 not supported) + * @{ + */ +#define PWM_PWM1_DUR__HI_DUR__SHIFT 16 +#define PWM_PWM1_DUR__HI_DUR__WIDTH 16 +#define PWM_PWM1_DUR__HI_DUR__MASK 0xffff0000U +#define PWM_PWM1_DUR__HI_DUR__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define PWM_PWM1_DUR__HI_DUR__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0xffff0000U) +#define PWM_PWM1_DUR__HI_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define PWM_PWM1_DUR__HI_DUR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define PWM_PWM1_DUR__HI_DUR__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM1_DUR__TYPE uint32_t +#define PWM_PWM1_DUR__READ 0xffffffffU +#define PWM_PWM1_DUR__WRITE 0xffffffffU +#define PWM_PWM1_DUR__PRESERVED 0x00000000U +#define PWM_PWM1_DUR__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM1_DUR_MACRO__ */ + +/** @} end of pwm1_dur */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm1_cfg */ +/** + * @defgroup at_apb_pwm_regs_core_pwm1_cfg pwm1_cfg + * @brief configuration for pwm1 channel definitions. + * @{ + */ +#ifndef __PWM_PWM1_CFG_MACRO__ +#define __PWM_PWM1_CFG_MACRO__ + +/* macros for field frame_count */ +/** + * @defgroup at_apb_pwm_regs_core_frame_count_field frame_count_field + * @brief macros for field frame_count + * @details number of frames in the group = frame_count + 1 + * @{ + */ +#define PWM_PWM1_CFG__FRAME_COUNT__SHIFT 0 +#define PWM_PWM1_CFG__FRAME_COUNT__WIDTH 14 +#define PWM_PWM1_CFG__FRAME_COUNT__MASK 0x00003fffU +#define PWM_PWM1_CFG__FRAME_COUNT__READ(src) ((uint32_t)(src) & 0x00003fffU) +#define PWM_PWM1_CFG__FRAME_COUNT__WRITE(src) ((uint32_t)(src) & 0x00003fffU) +#define PWM_PWM1_CFG__FRAME_COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((uint32_t)(src) &\ + 0x00003fffU) +#define PWM_PWM1_CFG__FRAME_COUNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00003fffU))) +#define PWM_PWM1_CFG__FRAME_COUNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field update */ +/** + * @defgroup at_apb_pwm_regs_core_update_field update_field + * @brief macros for field update + * @details this bit synchronize channel parameters (lo/hi dur + frame count) update, when set it triggers HW capture and it auto-cleares afterwards during CONTINUOUS and IR_FIFO modes, this bit is don't care. + * @{ + */ +#define PWM_PWM1_CFG__UPDATE__SHIFT 31 +#define PWM_PWM1_CFG__UPDATE__WIDTH 1 +#define PWM_PWM1_CFG__UPDATE__MASK 0x80000000U +#define PWM_PWM1_CFG__UPDATE__READ(src) (((uint32_t)(src) & 0x80000000U) >> 31) +#define PWM_PWM1_CFG__UPDATE__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define PWM_PWM1_CFG__UPDATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define PWM_PWM1_CFG__UPDATE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define PWM_PWM1_CFG__UPDATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PWM_PWM1_CFG__UPDATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PWM_PWM1_CFG__UPDATE__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM1_CFG__TYPE uint32_t +#define PWM_PWM1_CFG__READ 0x80003fffU +#define PWM_PWM1_CFG__WRITE 0x80003fffU +#define PWM_PWM1_CFG__PRESERVED 0x00000000U +#define PWM_PWM1_CFG__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM1_CFG_MACRO__ */ + +/** @} end of pwm1_cfg */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm2_ctrl */ +/** + * @defgroup at_apb_pwm_regs_core_pwm2_ctrl pwm2_ctrl + * @brief control signals for pwm2 channel definitions. + * @{ + */ +#ifndef __PWM_PWM2_CTRL_MACRO__ +#define __PWM_PWM2_CTRL_MACRO__ + +/* macros for field ok_to_run */ +/** + * @defgroup at_apb_pwm_regs_core_ok_to_run_field ok_to_run_field + * @brief macros for field ok_to_run + * @details start pwm channel with its rising edge. Its de-assertion stops the channel at the end of the next frame. + * @{ + */ +#define PWM_PWM2_CTRL__OK_TO_RUN__SHIFT 0 +#define PWM_PWM2_CTRL__OK_TO_RUN__WIDTH 1 +#define PWM_PWM2_CTRL__OK_TO_RUN__MASK 0x00000001U +#define PWM_PWM2_CTRL__OK_TO_RUN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PWM_PWM2_CTRL__OK_TO_RUN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PWM_PWM2_CTRL__OK_TO_RUN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PWM_PWM2_CTRL__OK_TO_RUN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PWM_PWM2_CTRL__OK_TO_RUN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PWM_PWM2_CTRL__OK_TO_RUN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PWM_PWM2_CTRL__OK_TO_RUN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mode */ +/** + * @defgroup at_apb_pwm_regs_core_mode_field mode_field + * @brief macros for field mode + * @details mode of operations: 00 = CONTINUOUS_MODE: each frame is repeated indefinately. hi_dur and lo_dur parameters are sampled once per frame. 01 = COUNTER_MODE: a group of frames is run once after ok_to_run is set. hi_dur and lo_dur parameters are sampled once at the start of the group. 10 = IR_MODE: a group of frames is run and repeated indefinitely after ok_to_run is set. hi_dur, lo_dur and frame_count paramters are sampled once before each group is run. 11 = IR_FIFO_MODE: the same IR_MODE but the group parameters are pulled from the fifo. The mode is reserved if the fifo is not assigned to the channel. + * @{ + */ +#define PWM_PWM2_CTRL__MODE__SHIFT 1 +#define PWM_PWM2_CTRL__MODE__WIDTH 2 +#define PWM_PWM2_CTRL__MODE__MASK 0x00000006U +#define PWM_PWM2_CTRL__MODE__READ(src) (((uint32_t)(src) & 0x00000006U) >> 1) +#define PWM_PWM2_CTRL__MODE__WRITE(src) (((uint32_t)(src) << 1) & 0x00000006U) +#define PWM_PWM2_CTRL__MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000006U) | (((uint32_t)(src) <<\ + 1) & 0x00000006U) +#define PWM_PWM2_CTRL__MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000006U))) +#define PWM_PWM2_CTRL__MODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field invert */ +/** + * @defgroup at_apb_pwm_regs_core_invert_field invert_field + * @brief macros for field invert + * @details invert pwm output. + * @{ + */ +#define PWM_PWM2_CTRL__INVERT__SHIFT 3 +#define PWM_PWM2_CTRL__INVERT__WIDTH 1 +#define PWM_PWM2_CTRL__INVERT__MASK 0x00000008U +#define PWM_PWM2_CTRL__INVERT__READ(src) (((uint32_t)(src) & 0x00000008U) >> 3) +#define PWM_PWM2_CTRL__INVERT__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PWM_PWM2_CTRL__INVERT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PWM_PWM2_CTRL__INVERT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PWM_PWM2_CTRL__INVERT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PWM_PWM2_CTRL__INVERT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PWM_PWM2_CTRL__INVERT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field idle_polarity */ +/** + * @defgroup at_apb_pwm_regs_core_idle_polarity_field idle_polarity_field + * @brief macros for field idle_polarity + * @details polarity in idle state + * @{ + */ +#define PWM_PWM2_CTRL__IDLE_POLARITY__SHIFT 4 +#define PWM_PWM2_CTRL__IDLE_POLARITY__WIDTH 1 +#define PWM_PWM2_CTRL__IDLE_POLARITY__MASK 0x00000010U +#define PWM_PWM2_CTRL__IDLE_POLARITY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PWM_PWM2_CTRL__IDLE_POLARITY__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PWM_PWM2_CTRL__IDLE_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PWM_PWM2_CTRL__IDLE_POLARITY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PWM_PWM2_CTRL__IDLE_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PWM_PWM2_CTRL__IDLE_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PWM_PWM2_CTRL__IDLE_POLARITY__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM2_CTRL__TYPE uint32_t +#define PWM_PWM2_CTRL__READ 0x0000001fU +#define PWM_PWM2_CTRL__WRITE 0x0000001fU +#define PWM_PWM2_CTRL__PRESERVED 0x00000000U +#define PWM_PWM2_CTRL__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM2_CTRL_MACRO__ */ + +/** @} end of pwm2_ctrl */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm2_dur */ +/** + * @defgroup at_apb_pwm_regs_core_pwm2_dur pwm2_dur + * @brief durations config for pwm2 channel definitions. + * @{ + */ +#ifndef __PWM_PWM2_DUR_MACRO__ +#define __PWM_PWM2_DUR_MACRO__ + +/* macros for field lo_dur */ +/** + * @defgroup at_apb_pwm_regs_core_lo_dur_field lo_dur_field + * @brief macros for field lo_dur + * @details duration of low portion of period in clk_mpc clock cycles = lo_dur. (lo_dur=1/hi_dur=0 not supported) + * @{ + */ +#define PWM_PWM2_DUR__LO_DUR__SHIFT 0 +#define PWM_PWM2_DUR__LO_DUR__WIDTH 16 +#define PWM_PWM2_DUR__LO_DUR__MASK 0x0000ffffU +#define PWM_PWM2_DUR__LO_DUR__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define PWM_PWM2_DUR__LO_DUR__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define PWM_PWM2_DUR__LO_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define PWM_PWM2_DUR__LO_DUR__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define PWM_PWM2_DUR__LO_DUR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hi_dur */ +/** + * @defgroup at_apb_pwm_regs_core_hi_dur_field hi_dur_field + * @brief macros for field hi_dur + * @details duration of high portion of period in clk_mpc clock cycles = hi_dur. (hi_dur=1/lo_dur=0 not supported) + * @{ + */ +#define PWM_PWM2_DUR__HI_DUR__SHIFT 16 +#define PWM_PWM2_DUR__HI_DUR__WIDTH 16 +#define PWM_PWM2_DUR__HI_DUR__MASK 0xffff0000U +#define PWM_PWM2_DUR__HI_DUR__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define PWM_PWM2_DUR__HI_DUR__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0xffff0000U) +#define PWM_PWM2_DUR__HI_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define PWM_PWM2_DUR__HI_DUR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define PWM_PWM2_DUR__HI_DUR__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM2_DUR__TYPE uint32_t +#define PWM_PWM2_DUR__READ 0xffffffffU +#define PWM_PWM2_DUR__WRITE 0xffffffffU +#define PWM_PWM2_DUR__PRESERVED 0x00000000U +#define PWM_PWM2_DUR__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM2_DUR_MACRO__ */ + +/** @} end of pwm2_dur */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm2_cfg */ +/** + * @defgroup at_apb_pwm_regs_core_pwm2_cfg pwm2_cfg + * @brief configuration for pwm2 channel definitions. + * @{ + */ +#ifndef __PWM_PWM2_CFG_MACRO__ +#define __PWM_PWM2_CFG_MACRO__ + +/* macros for field frame_count */ +/** + * @defgroup at_apb_pwm_regs_core_frame_count_field frame_count_field + * @brief macros for field frame_count + * @details number of frames in the group = frame_count + 1 + * @{ + */ +#define PWM_PWM2_CFG__FRAME_COUNT__SHIFT 0 +#define PWM_PWM2_CFG__FRAME_COUNT__WIDTH 14 +#define PWM_PWM2_CFG__FRAME_COUNT__MASK 0x00003fffU +#define PWM_PWM2_CFG__FRAME_COUNT__READ(src) ((uint32_t)(src) & 0x00003fffU) +#define PWM_PWM2_CFG__FRAME_COUNT__WRITE(src) ((uint32_t)(src) & 0x00003fffU) +#define PWM_PWM2_CFG__FRAME_COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((uint32_t)(src) &\ + 0x00003fffU) +#define PWM_PWM2_CFG__FRAME_COUNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00003fffU))) +#define PWM_PWM2_CFG__FRAME_COUNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field update */ +/** + * @defgroup at_apb_pwm_regs_core_update_field update_field + * @brief macros for field update + * @details this bit synchronize channel parameters (lo/hi dur + frame count) update, when set it triggers HW capture and it auto-cleares afterwards during CONTINUOUS and IR_FIFO modes, this bit is don't care. + * @{ + */ +#define PWM_PWM2_CFG__UPDATE__SHIFT 31 +#define PWM_PWM2_CFG__UPDATE__WIDTH 1 +#define PWM_PWM2_CFG__UPDATE__MASK 0x80000000U +#define PWM_PWM2_CFG__UPDATE__READ(src) (((uint32_t)(src) & 0x80000000U) >> 31) +#define PWM_PWM2_CFG__UPDATE__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define PWM_PWM2_CFG__UPDATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define PWM_PWM2_CFG__UPDATE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define PWM_PWM2_CFG__UPDATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PWM_PWM2_CFG__UPDATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PWM_PWM2_CFG__UPDATE__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM2_CFG__TYPE uint32_t +#define PWM_PWM2_CFG__READ 0x80003fffU +#define PWM_PWM2_CFG__WRITE 0x80003fffU +#define PWM_PWM2_CFG__PRESERVED 0x00000000U +#define PWM_PWM2_CFG__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM2_CFG_MACRO__ */ + +/** @} end of pwm2_cfg */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm3_ctrl */ +/** + * @defgroup at_apb_pwm_regs_core_pwm3_ctrl pwm3_ctrl + * @brief control signals for pwm3 channel definitions. + * @{ + */ +#ifndef __PWM_PWM3_CTRL_MACRO__ +#define __PWM_PWM3_CTRL_MACRO__ + +/* macros for field ok_to_run */ +/** + * @defgroup at_apb_pwm_regs_core_ok_to_run_field ok_to_run_field + * @brief macros for field ok_to_run + * @details start pwm channel with its rising edge. Its de-assertion stops the channel at the end of the next frame. + * @{ + */ +#define PWM_PWM3_CTRL__OK_TO_RUN__SHIFT 0 +#define PWM_PWM3_CTRL__OK_TO_RUN__WIDTH 1 +#define PWM_PWM3_CTRL__OK_TO_RUN__MASK 0x00000001U +#define PWM_PWM3_CTRL__OK_TO_RUN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PWM_PWM3_CTRL__OK_TO_RUN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PWM_PWM3_CTRL__OK_TO_RUN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PWM_PWM3_CTRL__OK_TO_RUN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PWM_PWM3_CTRL__OK_TO_RUN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PWM_PWM3_CTRL__OK_TO_RUN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PWM_PWM3_CTRL__OK_TO_RUN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mode */ +/** + * @defgroup at_apb_pwm_regs_core_mode_field mode_field + * @brief macros for field mode + * @details mode of operations: 00 = CONTINUOUS_MODE: each frame is repeated indefinately. hi_dur and lo_dur parameters are sampled once per frame. 01 = COUNTER_MODE: a group of frames is run once after ok_to_run is set. hi_dur and lo_dur parameters are sampled once at the start of the group. 10 = IR_MODE: a group of frames is run and repeated indefinitely after ok_to_run is set. hi_dur, lo_dur and frame_count paramters are sampled once before each group is run. 11 = IR_FIFO_MODE: the same IR_MODE but the group parameters are pulled from the fifo. The mode is reserved if the fifo is not assigned to the channel. + * @{ + */ +#define PWM_PWM3_CTRL__MODE__SHIFT 1 +#define PWM_PWM3_CTRL__MODE__WIDTH 2 +#define PWM_PWM3_CTRL__MODE__MASK 0x00000006U +#define PWM_PWM3_CTRL__MODE__READ(src) (((uint32_t)(src) & 0x00000006U) >> 1) +#define PWM_PWM3_CTRL__MODE__WRITE(src) (((uint32_t)(src) << 1) & 0x00000006U) +#define PWM_PWM3_CTRL__MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000006U) | (((uint32_t)(src) <<\ + 1) & 0x00000006U) +#define PWM_PWM3_CTRL__MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000006U))) +#define PWM_PWM3_CTRL__MODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field invert */ +/** + * @defgroup at_apb_pwm_regs_core_invert_field invert_field + * @brief macros for field invert + * @details invert pwm output. + * @{ + */ +#define PWM_PWM3_CTRL__INVERT__SHIFT 3 +#define PWM_PWM3_CTRL__INVERT__WIDTH 1 +#define PWM_PWM3_CTRL__INVERT__MASK 0x00000008U +#define PWM_PWM3_CTRL__INVERT__READ(src) (((uint32_t)(src) & 0x00000008U) >> 3) +#define PWM_PWM3_CTRL__INVERT__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PWM_PWM3_CTRL__INVERT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PWM_PWM3_CTRL__INVERT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PWM_PWM3_CTRL__INVERT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PWM_PWM3_CTRL__INVERT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PWM_PWM3_CTRL__INVERT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field idle_polarity */ +/** + * @defgroup at_apb_pwm_regs_core_idle_polarity_field idle_polarity_field + * @brief macros for field idle_polarity + * @details polarity in idle state + * @{ + */ +#define PWM_PWM3_CTRL__IDLE_POLARITY__SHIFT 4 +#define PWM_PWM3_CTRL__IDLE_POLARITY__WIDTH 1 +#define PWM_PWM3_CTRL__IDLE_POLARITY__MASK 0x00000010U +#define PWM_PWM3_CTRL__IDLE_POLARITY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PWM_PWM3_CTRL__IDLE_POLARITY__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PWM_PWM3_CTRL__IDLE_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PWM_PWM3_CTRL__IDLE_POLARITY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PWM_PWM3_CTRL__IDLE_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PWM_PWM3_CTRL__IDLE_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PWM_PWM3_CTRL__IDLE_POLARITY__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM3_CTRL__TYPE uint32_t +#define PWM_PWM3_CTRL__READ 0x0000001fU +#define PWM_PWM3_CTRL__WRITE 0x0000001fU +#define PWM_PWM3_CTRL__PRESERVED 0x00000000U +#define PWM_PWM3_CTRL__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM3_CTRL_MACRO__ */ + +/** @} end of pwm3_ctrl */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm3_dur */ +/** + * @defgroup at_apb_pwm_regs_core_pwm3_dur pwm3_dur + * @brief durations config for pwm3 channel definitions. + * @{ + */ +#ifndef __PWM_PWM3_DUR_MACRO__ +#define __PWM_PWM3_DUR_MACRO__ + +/* macros for field lo_dur */ +/** + * @defgroup at_apb_pwm_regs_core_lo_dur_field lo_dur_field + * @brief macros for field lo_dur + * @details duration of low portion of period in clk_mpc clock cycles = lo_dur. (lo_dur=1/hi_dur=0 not supported) + * @{ + */ +#define PWM_PWM3_DUR__LO_DUR__SHIFT 0 +#define PWM_PWM3_DUR__LO_DUR__WIDTH 16 +#define PWM_PWM3_DUR__LO_DUR__MASK 0x0000ffffU +#define PWM_PWM3_DUR__LO_DUR__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define PWM_PWM3_DUR__LO_DUR__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define PWM_PWM3_DUR__LO_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define PWM_PWM3_DUR__LO_DUR__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define PWM_PWM3_DUR__LO_DUR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hi_dur */ +/** + * @defgroup at_apb_pwm_regs_core_hi_dur_field hi_dur_field + * @brief macros for field hi_dur + * @details duration of high portion of period in clk_mpc clock cycles = hi_dur. (hi_dur=1/lo_dur=0 not supported) + * @{ + */ +#define PWM_PWM3_DUR__HI_DUR__SHIFT 16 +#define PWM_PWM3_DUR__HI_DUR__WIDTH 16 +#define PWM_PWM3_DUR__HI_DUR__MASK 0xffff0000U +#define PWM_PWM3_DUR__HI_DUR__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define PWM_PWM3_DUR__HI_DUR__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0xffff0000U) +#define PWM_PWM3_DUR__HI_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define PWM_PWM3_DUR__HI_DUR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define PWM_PWM3_DUR__HI_DUR__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM3_DUR__TYPE uint32_t +#define PWM_PWM3_DUR__READ 0xffffffffU +#define PWM_PWM3_DUR__WRITE 0xffffffffU +#define PWM_PWM3_DUR__PRESERVED 0x00000000U +#define PWM_PWM3_DUR__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM3_DUR_MACRO__ */ + +/** @} end of pwm3_dur */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm3_cfg */ +/** + * @defgroup at_apb_pwm_regs_core_pwm3_cfg pwm3_cfg + * @brief configuration for pwm3 channel definitions. + * @{ + */ +#ifndef __PWM_PWM3_CFG_MACRO__ +#define __PWM_PWM3_CFG_MACRO__ + +/* macros for field frame_count */ +/** + * @defgroup at_apb_pwm_regs_core_frame_count_field frame_count_field + * @brief macros for field frame_count + * @details number of frames in the group = frame_count + 1 + * @{ + */ +#define PWM_PWM3_CFG__FRAME_COUNT__SHIFT 0 +#define PWM_PWM3_CFG__FRAME_COUNT__WIDTH 14 +#define PWM_PWM3_CFG__FRAME_COUNT__MASK 0x00003fffU +#define PWM_PWM3_CFG__FRAME_COUNT__READ(src) ((uint32_t)(src) & 0x00003fffU) +#define PWM_PWM3_CFG__FRAME_COUNT__WRITE(src) ((uint32_t)(src) & 0x00003fffU) +#define PWM_PWM3_CFG__FRAME_COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((uint32_t)(src) &\ + 0x00003fffU) +#define PWM_PWM3_CFG__FRAME_COUNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00003fffU))) +#define PWM_PWM3_CFG__FRAME_COUNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field update */ +/** + * @defgroup at_apb_pwm_regs_core_update_field update_field + * @brief macros for field update + * @details this bit synchronize channel parameters (lo/hi dur + frame count) update, when set it triggers HW capture and it auto-cleares afterwards during CONTINUOUS and IR_FIFO modes, this bit is don't care. + * @{ + */ +#define PWM_PWM3_CFG__UPDATE__SHIFT 31 +#define PWM_PWM3_CFG__UPDATE__WIDTH 1 +#define PWM_PWM3_CFG__UPDATE__MASK 0x80000000U +#define PWM_PWM3_CFG__UPDATE__READ(src) (((uint32_t)(src) & 0x80000000U) >> 31) +#define PWM_PWM3_CFG__UPDATE__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define PWM_PWM3_CFG__UPDATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define PWM_PWM3_CFG__UPDATE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define PWM_PWM3_CFG__UPDATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PWM_PWM3_CFG__UPDATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PWM_PWM3_CFG__UPDATE__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM3_CFG__TYPE uint32_t +#define PWM_PWM3_CFG__READ 0x80003fffU +#define PWM_PWM3_CFG__WRITE 0x80003fffU +#define PWM_PWM3_CFG__PRESERVED 0x00000000U +#define PWM_PWM3_CFG__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM3_CFG_MACRO__ */ + +/** @} end of pwm3_cfg */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm4_ctrl */ +/** + * @defgroup at_apb_pwm_regs_core_pwm4_ctrl pwm4_ctrl + * @brief control signals for pwm4 channel definitions. + * @{ + */ +#ifndef __PWM_PWM4_CTRL_MACRO__ +#define __PWM_PWM4_CTRL_MACRO__ + +/* macros for field ok_to_run */ +/** + * @defgroup at_apb_pwm_regs_core_ok_to_run_field ok_to_run_field + * @brief macros for field ok_to_run + * @details start pwm channel with its rising edge. Its de-assertion stops the channel at the end of the next frame. + * @{ + */ +#define PWM_PWM4_CTRL__OK_TO_RUN__SHIFT 0 +#define PWM_PWM4_CTRL__OK_TO_RUN__WIDTH 1 +#define PWM_PWM4_CTRL__OK_TO_RUN__MASK 0x00000001U +#define PWM_PWM4_CTRL__OK_TO_RUN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PWM_PWM4_CTRL__OK_TO_RUN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PWM_PWM4_CTRL__OK_TO_RUN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PWM_PWM4_CTRL__OK_TO_RUN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PWM_PWM4_CTRL__OK_TO_RUN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PWM_PWM4_CTRL__OK_TO_RUN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PWM_PWM4_CTRL__OK_TO_RUN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mode */ +/** + * @defgroup at_apb_pwm_regs_core_mode_field mode_field + * @brief macros for field mode + * @details mode of operations: 00 = CONTINUOUS_MODE: each frame is repeated indefinately. hi_dur and lo_dur parameters are sampled once per frame. 01 = COUNTER_MODE: a group of frames is run once after ok_to_run is set. hi_dur and lo_dur parameters are sampled once at the start of the group. 10 = IR_MODE: a group of frames is run and repeated indefinitely after ok_to_run is set. hi_dur, lo_dur and frame_count paramters are sampled once before each group is run. 11 = IR_FIFO_MODE: the same IR_MODE but the group parameters are pulled from the fifo. The mode is reserved if the fifo is not assigned to the channel. + * @{ + */ +#define PWM_PWM4_CTRL__MODE__SHIFT 1 +#define PWM_PWM4_CTRL__MODE__WIDTH 2 +#define PWM_PWM4_CTRL__MODE__MASK 0x00000006U +#define PWM_PWM4_CTRL__MODE__READ(src) (((uint32_t)(src) & 0x00000006U) >> 1) +#define PWM_PWM4_CTRL__MODE__WRITE(src) (((uint32_t)(src) << 1) & 0x00000006U) +#define PWM_PWM4_CTRL__MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000006U) | (((uint32_t)(src) <<\ + 1) & 0x00000006U) +#define PWM_PWM4_CTRL__MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000006U))) +#define PWM_PWM4_CTRL__MODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field invert */ +/** + * @defgroup at_apb_pwm_regs_core_invert_field invert_field + * @brief macros for field invert + * @details invert pwm output. + * @{ + */ +#define PWM_PWM4_CTRL__INVERT__SHIFT 3 +#define PWM_PWM4_CTRL__INVERT__WIDTH 1 +#define PWM_PWM4_CTRL__INVERT__MASK 0x00000008U +#define PWM_PWM4_CTRL__INVERT__READ(src) (((uint32_t)(src) & 0x00000008U) >> 3) +#define PWM_PWM4_CTRL__INVERT__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PWM_PWM4_CTRL__INVERT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PWM_PWM4_CTRL__INVERT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PWM_PWM4_CTRL__INVERT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PWM_PWM4_CTRL__INVERT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PWM_PWM4_CTRL__INVERT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field idle_polarity */ +/** + * @defgroup at_apb_pwm_regs_core_idle_polarity_field idle_polarity_field + * @brief macros for field idle_polarity + * @details polarity in idle state + * @{ + */ +#define PWM_PWM4_CTRL__IDLE_POLARITY__SHIFT 4 +#define PWM_PWM4_CTRL__IDLE_POLARITY__WIDTH 1 +#define PWM_PWM4_CTRL__IDLE_POLARITY__MASK 0x00000010U +#define PWM_PWM4_CTRL__IDLE_POLARITY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PWM_PWM4_CTRL__IDLE_POLARITY__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PWM_PWM4_CTRL__IDLE_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PWM_PWM4_CTRL__IDLE_POLARITY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PWM_PWM4_CTRL__IDLE_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PWM_PWM4_CTRL__IDLE_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PWM_PWM4_CTRL__IDLE_POLARITY__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM4_CTRL__TYPE uint32_t +#define PWM_PWM4_CTRL__READ 0x0000001fU +#define PWM_PWM4_CTRL__WRITE 0x0000001fU +#define PWM_PWM4_CTRL__PRESERVED 0x00000000U +#define PWM_PWM4_CTRL__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM4_CTRL_MACRO__ */ + +/** @} end of pwm4_ctrl */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm4_dur */ +/** + * @defgroup at_apb_pwm_regs_core_pwm4_dur pwm4_dur + * @brief durations config for pwm4 channel definitions. + * @{ + */ +#ifndef __PWM_PWM4_DUR_MACRO__ +#define __PWM_PWM4_DUR_MACRO__ + +/* macros for field lo_dur */ +/** + * @defgroup at_apb_pwm_regs_core_lo_dur_field lo_dur_field + * @brief macros for field lo_dur + * @details duration of low portion of period in clk_mpc clock cycles = lo_dur. (lo_dur=1/hi_dur=0 not supported) + * @{ + */ +#define PWM_PWM4_DUR__LO_DUR__SHIFT 0 +#define PWM_PWM4_DUR__LO_DUR__WIDTH 16 +#define PWM_PWM4_DUR__LO_DUR__MASK 0x0000ffffU +#define PWM_PWM4_DUR__LO_DUR__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define PWM_PWM4_DUR__LO_DUR__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define PWM_PWM4_DUR__LO_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define PWM_PWM4_DUR__LO_DUR__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define PWM_PWM4_DUR__LO_DUR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hi_dur */ +/** + * @defgroup at_apb_pwm_regs_core_hi_dur_field hi_dur_field + * @brief macros for field hi_dur + * @details duration of high portion of period in clk_mpc clock cycles = hi_dur. (hi_dur=1/lo_dur=0 not supported) + * @{ + */ +#define PWM_PWM4_DUR__HI_DUR__SHIFT 16 +#define PWM_PWM4_DUR__HI_DUR__WIDTH 16 +#define PWM_PWM4_DUR__HI_DUR__MASK 0xffff0000U +#define PWM_PWM4_DUR__HI_DUR__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define PWM_PWM4_DUR__HI_DUR__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0xffff0000U) +#define PWM_PWM4_DUR__HI_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define PWM_PWM4_DUR__HI_DUR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define PWM_PWM4_DUR__HI_DUR__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM4_DUR__TYPE uint32_t +#define PWM_PWM4_DUR__READ 0xffffffffU +#define PWM_PWM4_DUR__WRITE 0xffffffffU +#define PWM_PWM4_DUR__PRESERVED 0x00000000U +#define PWM_PWM4_DUR__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM4_DUR_MACRO__ */ + +/** @} end of pwm4_dur */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm4_cfg */ +/** + * @defgroup at_apb_pwm_regs_core_pwm4_cfg pwm4_cfg + * @brief configuration for pwm4 channel definitions. + * @{ + */ +#ifndef __PWM_PWM4_CFG_MACRO__ +#define __PWM_PWM4_CFG_MACRO__ + +/* macros for field frame_count */ +/** + * @defgroup at_apb_pwm_regs_core_frame_count_field frame_count_field + * @brief macros for field frame_count + * @details number of frames in the group = frame_count + 1 + * @{ + */ +#define PWM_PWM4_CFG__FRAME_COUNT__SHIFT 0 +#define PWM_PWM4_CFG__FRAME_COUNT__WIDTH 14 +#define PWM_PWM4_CFG__FRAME_COUNT__MASK 0x00003fffU +#define PWM_PWM4_CFG__FRAME_COUNT__READ(src) ((uint32_t)(src) & 0x00003fffU) +#define PWM_PWM4_CFG__FRAME_COUNT__WRITE(src) ((uint32_t)(src) & 0x00003fffU) +#define PWM_PWM4_CFG__FRAME_COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((uint32_t)(src) &\ + 0x00003fffU) +#define PWM_PWM4_CFG__FRAME_COUNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00003fffU))) +#define PWM_PWM4_CFG__FRAME_COUNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field update */ +/** + * @defgroup at_apb_pwm_regs_core_update_field update_field + * @brief macros for field update + * @details this bit synchronize channel parameters (lo/hi dur + frame count) update, when set it triggers HW capture and it auto-cleares afterwards during CONTINUOUS and IR_FIFO modes, this bit is don't care. + * @{ + */ +#define PWM_PWM4_CFG__UPDATE__SHIFT 31 +#define PWM_PWM4_CFG__UPDATE__WIDTH 1 +#define PWM_PWM4_CFG__UPDATE__MASK 0x80000000U +#define PWM_PWM4_CFG__UPDATE__READ(src) (((uint32_t)(src) & 0x80000000U) >> 31) +#define PWM_PWM4_CFG__UPDATE__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define PWM_PWM4_CFG__UPDATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define PWM_PWM4_CFG__UPDATE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define PWM_PWM4_CFG__UPDATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PWM_PWM4_CFG__UPDATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PWM_PWM4_CFG__UPDATE__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM4_CFG__TYPE uint32_t +#define PWM_PWM4_CFG__READ 0x80003fffU +#define PWM_PWM4_CFG__WRITE 0x80003fffU +#define PWM_PWM4_CFG__PRESERVED 0x00000000U +#define PWM_PWM4_CFG__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM4_CFG_MACRO__ */ + +/** @} end of pwm4_cfg */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm5_ctrl */ +/** + * @defgroup at_apb_pwm_regs_core_pwm5_ctrl pwm5_ctrl + * @brief control signals for pwm5 channel definitions. + * @{ + */ +#ifndef __PWM_PWM5_CTRL_MACRO__ +#define __PWM_PWM5_CTRL_MACRO__ + +/* macros for field ok_to_run */ +/** + * @defgroup at_apb_pwm_regs_core_ok_to_run_field ok_to_run_field + * @brief macros for field ok_to_run + * @details start pwm channel with its rising edge. Its de-assertion stops the channel at the end of the next frame. + * @{ + */ +#define PWM_PWM5_CTRL__OK_TO_RUN__SHIFT 0 +#define PWM_PWM5_CTRL__OK_TO_RUN__WIDTH 1 +#define PWM_PWM5_CTRL__OK_TO_RUN__MASK 0x00000001U +#define PWM_PWM5_CTRL__OK_TO_RUN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PWM_PWM5_CTRL__OK_TO_RUN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PWM_PWM5_CTRL__OK_TO_RUN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PWM_PWM5_CTRL__OK_TO_RUN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PWM_PWM5_CTRL__OK_TO_RUN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PWM_PWM5_CTRL__OK_TO_RUN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PWM_PWM5_CTRL__OK_TO_RUN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mode */ +/** + * @defgroup at_apb_pwm_regs_core_mode_field mode_field + * @brief macros for field mode + * @details mode of operations: 00 = CONTINUOUS_MODE: each frame is repeated indefinately. hi_dur and lo_dur parameters are sampled once per frame. 01 = COUNTER_MODE: a group of frames is run once after ok_to_run is set. hi_dur and lo_dur parameters are sampled once at the start of the group. 10 = IR_MODE: a group of frames is run and repeated indefinitely after ok_to_run is set. hi_dur, lo_dur and frame_count paramters are sampled once before each group is run. 11 = IR_FIFO_MODE: the same IR_MODE but the group parameters are pulled from the fifo. The mode is reserved if the fifo is not assigned to the channel. + * @{ + */ +#define PWM_PWM5_CTRL__MODE__SHIFT 1 +#define PWM_PWM5_CTRL__MODE__WIDTH 2 +#define PWM_PWM5_CTRL__MODE__MASK 0x00000006U +#define PWM_PWM5_CTRL__MODE__READ(src) (((uint32_t)(src) & 0x00000006U) >> 1) +#define PWM_PWM5_CTRL__MODE__WRITE(src) (((uint32_t)(src) << 1) & 0x00000006U) +#define PWM_PWM5_CTRL__MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000006U) | (((uint32_t)(src) <<\ + 1) & 0x00000006U) +#define PWM_PWM5_CTRL__MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000006U))) +#define PWM_PWM5_CTRL__MODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field invert */ +/** + * @defgroup at_apb_pwm_regs_core_invert_field invert_field + * @brief macros for field invert + * @details invert pwm output. + * @{ + */ +#define PWM_PWM5_CTRL__INVERT__SHIFT 3 +#define PWM_PWM5_CTRL__INVERT__WIDTH 1 +#define PWM_PWM5_CTRL__INVERT__MASK 0x00000008U +#define PWM_PWM5_CTRL__INVERT__READ(src) (((uint32_t)(src) & 0x00000008U) >> 3) +#define PWM_PWM5_CTRL__INVERT__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PWM_PWM5_CTRL__INVERT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PWM_PWM5_CTRL__INVERT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PWM_PWM5_CTRL__INVERT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PWM_PWM5_CTRL__INVERT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PWM_PWM5_CTRL__INVERT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field idle_polarity */ +/** + * @defgroup at_apb_pwm_regs_core_idle_polarity_field idle_polarity_field + * @brief macros for field idle_polarity + * @details polarity in idle state + * @{ + */ +#define PWM_PWM5_CTRL__IDLE_POLARITY__SHIFT 4 +#define PWM_PWM5_CTRL__IDLE_POLARITY__WIDTH 1 +#define PWM_PWM5_CTRL__IDLE_POLARITY__MASK 0x00000010U +#define PWM_PWM5_CTRL__IDLE_POLARITY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PWM_PWM5_CTRL__IDLE_POLARITY__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PWM_PWM5_CTRL__IDLE_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PWM_PWM5_CTRL__IDLE_POLARITY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PWM_PWM5_CTRL__IDLE_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PWM_PWM5_CTRL__IDLE_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PWM_PWM5_CTRL__IDLE_POLARITY__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM5_CTRL__TYPE uint32_t +#define PWM_PWM5_CTRL__READ 0x0000001fU +#define PWM_PWM5_CTRL__WRITE 0x0000001fU +#define PWM_PWM5_CTRL__PRESERVED 0x00000000U +#define PWM_PWM5_CTRL__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM5_CTRL_MACRO__ */ + +/** @} end of pwm5_ctrl */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm5_dur */ +/** + * @defgroup at_apb_pwm_regs_core_pwm5_dur pwm5_dur + * @brief durations config for pwm5 channel definitions. + * @{ + */ +#ifndef __PWM_PWM5_DUR_MACRO__ +#define __PWM_PWM5_DUR_MACRO__ + +/* macros for field lo_dur */ +/** + * @defgroup at_apb_pwm_regs_core_lo_dur_field lo_dur_field + * @brief macros for field lo_dur + * @details duration of low portion of period in clk_mpc clock cycles = lo_dur. (lo_dur=1/hi_dur=0 not supported) + * @{ + */ +#define PWM_PWM5_DUR__LO_DUR__SHIFT 0 +#define PWM_PWM5_DUR__LO_DUR__WIDTH 16 +#define PWM_PWM5_DUR__LO_DUR__MASK 0x0000ffffU +#define PWM_PWM5_DUR__LO_DUR__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define PWM_PWM5_DUR__LO_DUR__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define PWM_PWM5_DUR__LO_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define PWM_PWM5_DUR__LO_DUR__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define PWM_PWM5_DUR__LO_DUR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hi_dur */ +/** + * @defgroup at_apb_pwm_regs_core_hi_dur_field hi_dur_field + * @brief macros for field hi_dur + * @details duration of high portion of period in clk_mpc clock cycles = hi_dur. (hi_dur=1/lo_dur=0 not supported) + * @{ + */ +#define PWM_PWM5_DUR__HI_DUR__SHIFT 16 +#define PWM_PWM5_DUR__HI_DUR__WIDTH 16 +#define PWM_PWM5_DUR__HI_DUR__MASK 0xffff0000U +#define PWM_PWM5_DUR__HI_DUR__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define PWM_PWM5_DUR__HI_DUR__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0xffff0000U) +#define PWM_PWM5_DUR__HI_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define PWM_PWM5_DUR__HI_DUR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define PWM_PWM5_DUR__HI_DUR__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM5_DUR__TYPE uint32_t +#define PWM_PWM5_DUR__READ 0xffffffffU +#define PWM_PWM5_DUR__WRITE 0xffffffffU +#define PWM_PWM5_DUR__PRESERVED 0x00000000U +#define PWM_PWM5_DUR__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM5_DUR_MACRO__ */ + +/** @} end of pwm5_dur */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm5_cfg */ +/** + * @defgroup at_apb_pwm_regs_core_pwm5_cfg pwm5_cfg + * @brief configuration for pwm5 channel definitions. + * @{ + */ +#ifndef __PWM_PWM5_CFG_MACRO__ +#define __PWM_PWM5_CFG_MACRO__ + +/* macros for field frame_count */ +/** + * @defgroup at_apb_pwm_regs_core_frame_count_field frame_count_field + * @brief macros for field frame_count + * @details number of frames in the group = frame_count + 1 + * @{ + */ +#define PWM_PWM5_CFG__FRAME_COUNT__SHIFT 0 +#define PWM_PWM5_CFG__FRAME_COUNT__WIDTH 14 +#define PWM_PWM5_CFG__FRAME_COUNT__MASK 0x00003fffU +#define PWM_PWM5_CFG__FRAME_COUNT__READ(src) ((uint32_t)(src) & 0x00003fffU) +#define PWM_PWM5_CFG__FRAME_COUNT__WRITE(src) ((uint32_t)(src) & 0x00003fffU) +#define PWM_PWM5_CFG__FRAME_COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((uint32_t)(src) &\ + 0x00003fffU) +#define PWM_PWM5_CFG__FRAME_COUNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00003fffU))) +#define PWM_PWM5_CFG__FRAME_COUNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field update */ +/** + * @defgroup at_apb_pwm_regs_core_update_field update_field + * @brief macros for field update + * @details this bit synchronize channel parameters (lo/hi dur + frame count) update, when set it triggers HW capture and it auto-cleares afterwards during CONTINUOUS and IR_FIFO modes, this bit is don't care. + * @{ + */ +#define PWM_PWM5_CFG__UPDATE__SHIFT 31 +#define PWM_PWM5_CFG__UPDATE__WIDTH 1 +#define PWM_PWM5_CFG__UPDATE__MASK 0x80000000U +#define PWM_PWM5_CFG__UPDATE__READ(src) (((uint32_t)(src) & 0x80000000U) >> 31) +#define PWM_PWM5_CFG__UPDATE__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define PWM_PWM5_CFG__UPDATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define PWM_PWM5_CFG__UPDATE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define PWM_PWM5_CFG__UPDATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PWM_PWM5_CFG__UPDATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PWM_PWM5_CFG__UPDATE__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM5_CFG__TYPE uint32_t +#define PWM_PWM5_CFG__READ 0x80003fffU +#define PWM_PWM5_CFG__WRITE 0x80003fffU +#define PWM_PWM5_CFG__PRESERVED 0x00000000U +#define PWM_PWM5_CFG__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM5_CFG_MACRO__ */ + +/** @} end of pwm5_cfg */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm6_ctrl */ +/** + * @defgroup at_apb_pwm_regs_core_pwm6_ctrl pwm6_ctrl + * @brief control signals for pwm6 channel definitions. + * @{ + */ +#ifndef __PWM_PWM6_CTRL_MACRO__ +#define __PWM_PWM6_CTRL_MACRO__ + +/* macros for field ok_to_run */ +/** + * @defgroup at_apb_pwm_regs_core_ok_to_run_field ok_to_run_field + * @brief macros for field ok_to_run + * @details start pwm channel with its rising edge. Its de-assertion stops the channel at the end of the next frame. + * @{ + */ +#define PWM_PWM6_CTRL__OK_TO_RUN__SHIFT 0 +#define PWM_PWM6_CTRL__OK_TO_RUN__WIDTH 1 +#define PWM_PWM6_CTRL__OK_TO_RUN__MASK 0x00000001U +#define PWM_PWM6_CTRL__OK_TO_RUN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PWM_PWM6_CTRL__OK_TO_RUN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PWM_PWM6_CTRL__OK_TO_RUN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PWM_PWM6_CTRL__OK_TO_RUN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PWM_PWM6_CTRL__OK_TO_RUN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PWM_PWM6_CTRL__OK_TO_RUN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PWM_PWM6_CTRL__OK_TO_RUN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mode */ +/** + * @defgroup at_apb_pwm_regs_core_mode_field mode_field + * @brief macros for field mode + * @details mode of operations: 00 = CONTINUOUS_MODE: each frame is repeated indefinately. hi_dur and lo_dur parameters are sampled once per frame. 01 = COUNTER_MODE: a group of frames is run once after ok_to_run is set. hi_dur and lo_dur parameters are sampled once at the start of the group. 10 = IR_MODE: a group of frames is run and repeated indefinitely after ok_to_run is set. hi_dur, lo_dur and frame_count paramters are sampled once before each group is run. 11 = IR_FIFO_MODE: the same IR_MODE but the group parameters are pulled from the fifo. The mode is reserved if the fifo is not assigned to the channel. + * @{ + */ +#define PWM_PWM6_CTRL__MODE__SHIFT 1 +#define PWM_PWM6_CTRL__MODE__WIDTH 2 +#define PWM_PWM6_CTRL__MODE__MASK 0x00000006U +#define PWM_PWM6_CTRL__MODE__READ(src) (((uint32_t)(src) & 0x00000006U) >> 1) +#define PWM_PWM6_CTRL__MODE__WRITE(src) (((uint32_t)(src) << 1) & 0x00000006U) +#define PWM_PWM6_CTRL__MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000006U) | (((uint32_t)(src) <<\ + 1) & 0x00000006U) +#define PWM_PWM6_CTRL__MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000006U))) +#define PWM_PWM6_CTRL__MODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field invert */ +/** + * @defgroup at_apb_pwm_regs_core_invert_field invert_field + * @brief macros for field invert + * @details invert pwm output. + * @{ + */ +#define PWM_PWM6_CTRL__INVERT__SHIFT 3 +#define PWM_PWM6_CTRL__INVERT__WIDTH 1 +#define PWM_PWM6_CTRL__INVERT__MASK 0x00000008U +#define PWM_PWM6_CTRL__INVERT__READ(src) (((uint32_t)(src) & 0x00000008U) >> 3) +#define PWM_PWM6_CTRL__INVERT__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PWM_PWM6_CTRL__INVERT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PWM_PWM6_CTRL__INVERT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PWM_PWM6_CTRL__INVERT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PWM_PWM6_CTRL__INVERT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PWM_PWM6_CTRL__INVERT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field idle_polarity */ +/** + * @defgroup at_apb_pwm_regs_core_idle_polarity_field idle_polarity_field + * @brief macros for field idle_polarity + * @details polarity in idle state + * @{ + */ +#define PWM_PWM6_CTRL__IDLE_POLARITY__SHIFT 4 +#define PWM_PWM6_CTRL__IDLE_POLARITY__WIDTH 1 +#define PWM_PWM6_CTRL__IDLE_POLARITY__MASK 0x00000010U +#define PWM_PWM6_CTRL__IDLE_POLARITY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PWM_PWM6_CTRL__IDLE_POLARITY__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PWM_PWM6_CTRL__IDLE_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PWM_PWM6_CTRL__IDLE_POLARITY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PWM_PWM6_CTRL__IDLE_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PWM_PWM6_CTRL__IDLE_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PWM_PWM6_CTRL__IDLE_POLARITY__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM6_CTRL__TYPE uint32_t +#define PWM_PWM6_CTRL__READ 0x0000001fU +#define PWM_PWM6_CTRL__WRITE 0x0000001fU +#define PWM_PWM6_CTRL__PRESERVED 0x00000000U +#define PWM_PWM6_CTRL__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM6_CTRL_MACRO__ */ + +/** @} end of pwm6_ctrl */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm6_dur */ +/** + * @defgroup at_apb_pwm_regs_core_pwm6_dur pwm6_dur + * @brief durations config for pwm6 channel definitions. + * @{ + */ +#ifndef __PWM_PWM6_DUR_MACRO__ +#define __PWM_PWM6_DUR_MACRO__ + +/* macros for field lo_dur */ +/** + * @defgroup at_apb_pwm_regs_core_lo_dur_field lo_dur_field + * @brief macros for field lo_dur + * @details duration of low portion of period in clk_mpc clock cycles = lo_dur. (lo_dur=1/hi_dur=0 not supported) + * @{ + */ +#define PWM_PWM6_DUR__LO_DUR__SHIFT 0 +#define PWM_PWM6_DUR__LO_DUR__WIDTH 16 +#define PWM_PWM6_DUR__LO_DUR__MASK 0x0000ffffU +#define PWM_PWM6_DUR__LO_DUR__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define PWM_PWM6_DUR__LO_DUR__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define PWM_PWM6_DUR__LO_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define PWM_PWM6_DUR__LO_DUR__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define PWM_PWM6_DUR__LO_DUR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hi_dur */ +/** + * @defgroup at_apb_pwm_regs_core_hi_dur_field hi_dur_field + * @brief macros for field hi_dur + * @details duration of high portion of period in clk_mpc clock cycles = hi_dur. (hi_dur=1/lo_dur=0 not supported) + * @{ + */ +#define PWM_PWM6_DUR__HI_DUR__SHIFT 16 +#define PWM_PWM6_DUR__HI_DUR__WIDTH 16 +#define PWM_PWM6_DUR__HI_DUR__MASK 0xffff0000U +#define PWM_PWM6_DUR__HI_DUR__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define PWM_PWM6_DUR__HI_DUR__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0xffff0000U) +#define PWM_PWM6_DUR__HI_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define PWM_PWM6_DUR__HI_DUR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define PWM_PWM6_DUR__HI_DUR__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM6_DUR__TYPE uint32_t +#define PWM_PWM6_DUR__READ 0xffffffffU +#define PWM_PWM6_DUR__WRITE 0xffffffffU +#define PWM_PWM6_DUR__PRESERVED 0x00000000U +#define PWM_PWM6_DUR__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM6_DUR_MACRO__ */ + +/** @} end of pwm6_dur */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm6_cfg */ +/** + * @defgroup at_apb_pwm_regs_core_pwm6_cfg pwm6_cfg + * @brief configuration for pwm6 channel definitions. + * @{ + */ +#ifndef __PWM_PWM6_CFG_MACRO__ +#define __PWM_PWM6_CFG_MACRO__ + +/* macros for field frame_count */ +/** + * @defgroup at_apb_pwm_regs_core_frame_count_field frame_count_field + * @brief macros for field frame_count + * @details number of frames in the group = frame_count + 1 + * @{ + */ +#define PWM_PWM6_CFG__FRAME_COUNT__SHIFT 0 +#define PWM_PWM6_CFG__FRAME_COUNT__WIDTH 14 +#define PWM_PWM6_CFG__FRAME_COUNT__MASK 0x00003fffU +#define PWM_PWM6_CFG__FRAME_COUNT__READ(src) ((uint32_t)(src) & 0x00003fffU) +#define PWM_PWM6_CFG__FRAME_COUNT__WRITE(src) ((uint32_t)(src) & 0x00003fffU) +#define PWM_PWM6_CFG__FRAME_COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((uint32_t)(src) &\ + 0x00003fffU) +#define PWM_PWM6_CFG__FRAME_COUNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00003fffU))) +#define PWM_PWM6_CFG__FRAME_COUNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field update */ +/** + * @defgroup at_apb_pwm_regs_core_update_field update_field + * @brief macros for field update + * @details this bit synchronize channel parameters (lo/hi dur + frame count) update, when set it triggers HW capture and it auto-cleares afterwards during CONTINUOUS and IR_FIFO modes, this bit is don't care. + * @{ + */ +#define PWM_PWM6_CFG__UPDATE__SHIFT 31 +#define PWM_PWM6_CFG__UPDATE__WIDTH 1 +#define PWM_PWM6_CFG__UPDATE__MASK 0x80000000U +#define PWM_PWM6_CFG__UPDATE__READ(src) (((uint32_t)(src) & 0x80000000U) >> 31) +#define PWM_PWM6_CFG__UPDATE__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define PWM_PWM6_CFG__UPDATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define PWM_PWM6_CFG__UPDATE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define PWM_PWM6_CFG__UPDATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PWM_PWM6_CFG__UPDATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PWM_PWM6_CFG__UPDATE__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM6_CFG__TYPE uint32_t +#define PWM_PWM6_CFG__READ 0x80003fffU +#define PWM_PWM6_CFG__WRITE 0x80003fffU +#define PWM_PWM6_CFG__PRESERVED 0x00000000U +#define PWM_PWM6_CFG__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM6_CFG_MACRO__ */ + +/** @} end of pwm6_cfg */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm7_ctrl */ +/** + * @defgroup at_apb_pwm_regs_core_pwm7_ctrl pwm7_ctrl + * @brief control signals for pwm7 channel definitions. + * @{ + */ +#ifndef __PWM_PWM7_CTRL_MACRO__ +#define __PWM_PWM7_CTRL_MACRO__ + +/* macros for field ok_to_run */ +/** + * @defgroup at_apb_pwm_regs_core_ok_to_run_field ok_to_run_field + * @brief macros for field ok_to_run + * @details start pwm channel with its rising edge. Its de-assertion stops the channel at the end of the next frame. + * @{ + */ +#define PWM_PWM7_CTRL__OK_TO_RUN__SHIFT 0 +#define PWM_PWM7_CTRL__OK_TO_RUN__WIDTH 1 +#define PWM_PWM7_CTRL__OK_TO_RUN__MASK 0x00000001U +#define PWM_PWM7_CTRL__OK_TO_RUN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PWM_PWM7_CTRL__OK_TO_RUN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PWM_PWM7_CTRL__OK_TO_RUN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PWM_PWM7_CTRL__OK_TO_RUN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PWM_PWM7_CTRL__OK_TO_RUN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PWM_PWM7_CTRL__OK_TO_RUN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PWM_PWM7_CTRL__OK_TO_RUN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mode */ +/** + * @defgroup at_apb_pwm_regs_core_mode_field mode_field + * @brief macros for field mode + * @details mode of operations: 00 = CONTINUOUS_MODE: each frame is repeated indefinately. hi_dur and lo_dur parameters are sampled once per frame. 01 = COUNTER_MODE: a group of frames is run once after ok_to_run is set. hi_dur and lo_dur parameters are sampled once at the start of the group. 10 = IR_MODE: a group of frames is run and repeated indefinitely after ok_to_run is set. hi_dur, lo_dur and frame_count paramters are sampled once before each group is run. 11 = IR_FIFO_MODE: the same IR_MODE but the group parameters are pulled from the fifo. The mode is reserved if the fifo is not assigned to the channel. + * @{ + */ +#define PWM_PWM7_CTRL__MODE__SHIFT 1 +#define PWM_PWM7_CTRL__MODE__WIDTH 2 +#define PWM_PWM7_CTRL__MODE__MASK 0x00000006U +#define PWM_PWM7_CTRL__MODE__READ(src) (((uint32_t)(src) & 0x00000006U) >> 1) +#define PWM_PWM7_CTRL__MODE__WRITE(src) (((uint32_t)(src) << 1) & 0x00000006U) +#define PWM_PWM7_CTRL__MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000006U) | (((uint32_t)(src) <<\ + 1) & 0x00000006U) +#define PWM_PWM7_CTRL__MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000006U))) +#define PWM_PWM7_CTRL__MODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field invert */ +/** + * @defgroup at_apb_pwm_regs_core_invert_field invert_field + * @brief macros for field invert + * @details invert pwm output. + * @{ + */ +#define PWM_PWM7_CTRL__INVERT__SHIFT 3 +#define PWM_PWM7_CTRL__INVERT__WIDTH 1 +#define PWM_PWM7_CTRL__INVERT__MASK 0x00000008U +#define PWM_PWM7_CTRL__INVERT__READ(src) (((uint32_t)(src) & 0x00000008U) >> 3) +#define PWM_PWM7_CTRL__INVERT__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PWM_PWM7_CTRL__INVERT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PWM_PWM7_CTRL__INVERT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PWM_PWM7_CTRL__INVERT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PWM_PWM7_CTRL__INVERT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PWM_PWM7_CTRL__INVERT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field idle_polarity */ +/** + * @defgroup at_apb_pwm_regs_core_idle_polarity_field idle_polarity_field + * @brief macros for field idle_polarity + * @details polarity in idle state + * @{ + */ +#define PWM_PWM7_CTRL__IDLE_POLARITY__SHIFT 4 +#define PWM_PWM7_CTRL__IDLE_POLARITY__WIDTH 1 +#define PWM_PWM7_CTRL__IDLE_POLARITY__MASK 0x00000010U +#define PWM_PWM7_CTRL__IDLE_POLARITY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PWM_PWM7_CTRL__IDLE_POLARITY__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PWM_PWM7_CTRL__IDLE_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PWM_PWM7_CTRL__IDLE_POLARITY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PWM_PWM7_CTRL__IDLE_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PWM_PWM7_CTRL__IDLE_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PWM_PWM7_CTRL__IDLE_POLARITY__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM7_CTRL__TYPE uint32_t +#define PWM_PWM7_CTRL__READ 0x0000001fU +#define PWM_PWM7_CTRL__WRITE 0x0000001fU +#define PWM_PWM7_CTRL__PRESERVED 0x00000000U +#define PWM_PWM7_CTRL__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM7_CTRL_MACRO__ */ + +/** @} end of pwm7_ctrl */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm7_dur */ +/** + * @defgroup at_apb_pwm_regs_core_pwm7_dur pwm7_dur + * @brief durations config for pwm7 channel definitions. + * @{ + */ +#ifndef __PWM_PWM7_DUR_MACRO__ +#define __PWM_PWM7_DUR_MACRO__ + +/* macros for field lo_dur */ +/** + * @defgroup at_apb_pwm_regs_core_lo_dur_field lo_dur_field + * @brief macros for field lo_dur + * @details duration of low portion of period in clk_mpc clock cycles = lo_dur. (lo_dur=1/hi_dur=0 not supported) + * @{ + */ +#define PWM_PWM7_DUR__LO_DUR__SHIFT 0 +#define PWM_PWM7_DUR__LO_DUR__WIDTH 16 +#define PWM_PWM7_DUR__LO_DUR__MASK 0x0000ffffU +#define PWM_PWM7_DUR__LO_DUR__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define PWM_PWM7_DUR__LO_DUR__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define PWM_PWM7_DUR__LO_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define PWM_PWM7_DUR__LO_DUR__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define PWM_PWM7_DUR__LO_DUR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hi_dur */ +/** + * @defgroup at_apb_pwm_regs_core_hi_dur_field hi_dur_field + * @brief macros for field hi_dur + * @details duration of high portion of period in clk_mpc clock cycles = hi_dur. (hi_dur=1/lo_dur=0 not supported) + * @{ + */ +#define PWM_PWM7_DUR__HI_DUR__SHIFT 16 +#define PWM_PWM7_DUR__HI_DUR__WIDTH 16 +#define PWM_PWM7_DUR__HI_DUR__MASK 0xffff0000U +#define PWM_PWM7_DUR__HI_DUR__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define PWM_PWM7_DUR__HI_DUR__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0xffff0000U) +#define PWM_PWM7_DUR__HI_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define PWM_PWM7_DUR__HI_DUR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define PWM_PWM7_DUR__HI_DUR__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM7_DUR__TYPE uint32_t +#define PWM_PWM7_DUR__READ 0xffffffffU +#define PWM_PWM7_DUR__WRITE 0xffffffffU +#define PWM_PWM7_DUR__PRESERVED 0x00000000U +#define PWM_PWM7_DUR__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM7_DUR_MACRO__ */ + +/** @} end of pwm7_dur */ + +/* macros for BlueprintGlobalNameSpace::PWM_pwm7_cfg */ +/** + * @defgroup at_apb_pwm_regs_core_pwm7_cfg pwm7_cfg + * @brief configuration for pwm7 channel definitions. + * @{ + */ +#ifndef __PWM_PWM7_CFG_MACRO__ +#define __PWM_PWM7_CFG_MACRO__ + +/* macros for field frame_count */ +/** + * @defgroup at_apb_pwm_regs_core_frame_count_field frame_count_field + * @brief macros for field frame_count + * @details number of frames in the group = frame_count + 1 + * @{ + */ +#define PWM_PWM7_CFG__FRAME_COUNT__SHIFT 0 +#define PWM_PWM7_CFG__FRAME_COUNT__WIDTH 14 +#define PWM_PWM7_CFG__FRAME_COUNT__MASK 0x00003fffU +#define PWM_PWM7_CFG__FRAME_COUNT__READ(src) ((uint32_t)(src) & 0x00003fffU) +#define PWM_PWM7_CFG__FRAME_COUNT__WRITE(src) ((uint32_t)(src) & 0x00003fffU) +#define PWM_PWM7_CFG__FRAME_COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((uint32_t)(src) &\ + 0x00003fffU) +#define PWM_PWM7_CFG__FRAME_COUNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00003fffU))) +#define PWM_PWM7_CFG__FRAME_COUNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field update */ +/** + * @defgroup at_apb_pwm_regs_core_update_field update_field + * @brief macros for field update + * @details this bit synchronize channel parameters (lo/hi dur + frame count) update, when set it triggers HW capture and it auto-cleares afterwards during CONTINUOUS and IR_FIFO modes, this bit is don't care. + * @{ + */ +#define PWM_PWM7_CFG__UPDATE__SHIFT 31 +#define PWM_PWM7_CFG__UPDATE__WIDTH 1 +#define PWM_PWM7_CFG__UPDATE__MASK 0x80000000U +#define PWM_PWM7_CFG__UPDATE__READ(src) (((uint32_t)(src) & 0x80000000U) >> 31) +#define PWM_PWM7_CFG__UPDATE__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define PWM_PWM7_CFG__UPDATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define PWM_PWM7_CFG__UPDATE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define PWM_PWM7_CFG__UPDATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PWM_PWM7_CFG__UPDATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PWM_PWM7_CFG__UPDATE__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_PWM7_CFG__TYPE uint32_t +#define PWM_PWM7_CFG__READ 0x80003fffU +#define PWM_PWM7_CFG__WRITE 0x80003fffU +#define PWM_PWM7_CFG__PRESERVED 0x00000000U +#define PWM_PWM7_CFG__RESET_VALUE 0x00000000U + +#endif /* __PWM_PWM7_CFG_MACRO__ */ + +/** @} end of pwm7_cfg */ + +/* macros for BlueprintGlobalNameSpace::PWM_fsm_state */ +/** + * @defgroup at_apb_pwm_regs_core_fsm_state fsm_state + * @brief fsm state definitions. + * @{ + */ +#ifndef __PWM_FSM_STATE_MACRO__ +#define __PWM_FSM_STATE_MACRO__ + +/* macros for field ch0 */ +/** + * @defgroup at_apb_pwm_regs_core_ch0_field ch0_field + * @brief macros for field ch0 + * @details current state of pwm0 channel. + * @{ + */ +#define PWM_FSM_STATE__CH0__SHIFT 0 +#define PWM_FSM_STATE__CH0__WIDTH 2 +#define PWM_FSM_STATE__CH0__MASK 0x00000003U +#define PWM_FSM_STATE__CH0__READ(src) ((uint32_t)(src) & 0x00000003U) +#define PWM_FSM_STATE__CH0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch1 */ +/** + * @defgroup at_apb_pwm_regs_core_ch1_field ch1_field + * @brief macros for field ch1 + * @details current state of pwm1 channel. + * @{ + */ +#define PWM_FSM_STATE__CH1__SHIFT 2 +#define PWM_FSM_STATE__CH1__WIDTH 2 +#define PWM_FSM_STATE__CH1__MASK 0x0000000cU +#define PWM_FSM_STATE__CH1__READ(src) (((uint32_t)(src) & 0x0000000cU) >> 2) +#define PWM_FSM_STATE__CH1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch2 */ +/** + * @defgroup at_apb_pwm_regs_core_ch2_field ch2_field + * @brief macros for field ch2 + * @details current state of pwm2 channel. + * @{ + */ +#define PWM_FSM_STATE__CH2__SHIFT 4 +#define PWM_FSM_STATE__CH2__WIDTH 2 +#define PWM_FSM_STATE__CH2__MASK 0x00000030U +#define PWM_FSM_STATE__CH2__READ(src) (((uint32_t)(src) & 0x00000030U) >> 4) +#define PWM_FSM_STATE__CH2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch3 */ +/** + * @defgroup at_apb_pwm_regs_core_ch3_field ch3_field + * @brief macros for field ch3 + * @details current state of pwm3 channel. + * @{ + */ +#define PWM_FSM_STATE__CH3__SHIFT 6 +#define PWM_FSM_STATE__CH3__WIDTH 2 +#define PWM_FSM_STATE__CH3__MASK 0x000000c0U +#define PWM_FSM_STATE__CH3__READ(src) (((uint32_t)(src) & 0x000000c0U) >> 6) +#define PWM_FSM_STATE__CH3__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch4 */ +/** + * @defgroup at_apb_pwm_regs_core_ch4_field ch4_field + * @brief macros for field ch4 + * @details current state of pwm4 channel. + * @{ + */ +#define PWM_FSM_STATE__CH4__SHIFT 8 +#define PWM_FSM_STATE__CH4__WIDTH 2 +#define PWM_FSM_STATE__CH4__MASK 0x00000300U +#define PWM_FSM_STATE__CH4__READ(src) (((uint32_t)(src) & 0x00000300U) >> 8) +#define PWM_FSM_STATE__CH4__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch5 */ +/** + * @defgroup at_apb_pwm_regs_core_ch5_field ch5_field + * @brief macros for field ch5 + * @details current state of pwm5 channel. + * @{ + */ +#define PWM_FSM_STATE__CH5__SHIFT 10 +#define PWM_FSM_STATE__CH5__WIDTH 2 +#define PWM_FSM_STATE__CH5__MASK 0x00000c00U +#define PWM_FSM_STATE__CH5__READ(src) (((uint32_t)(src) & 0x00000c00U) >> 10) +#define PWM_FSM_STATE__CH5__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch6 */ +/** + * @defgroup at_apb_pwm_regs_core_ch6_field ch6_field + * @brief macros for field ch6 + * @details current state of pwm6 channel. + * @{ + */ +#define PWM_FSM_STATE__CH6__SHIFT 12 +#define PWM_FSM_STATE__CH6__WIDTH 2 +#define PWM_FSM_STATE__CH6__MASK 0x00003000U +#define PWM_FSM_STATE__CH6__READ(src) (((uint32_t)(src) & 0x00003000U) >> 12) +#define PWM_FSM_STATE__CH6__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch7 */ +/** + * @defgroup at_apb_pwm_regs_core_ch7_field ch7_field + * @brief macros for field ch7 + * @details current state of pwm7 channel. + * @{ + */ +#define PWM_FSM_STATE__CH7__SHIFT 14 +#define PWM_FSM_STATE__CH7__WIDTH 2 +#define PWM_FSM_STATE__CH7__MASK 0x0000c000U +#define PWM_FSM_STATE__CH7__READ(src) (((uint32_t)(src) & 0x0000c000U) >> 14) +#define PWM_FSM_STATE__CH7__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_FSM_STATE__TYPE uint32_t +#define PWM_FSM_STATE__READ 0x0000ffffU +#define PWM_FSM_STATE__PRESERVED 0x00000000U +#define PWM_FSM_STATE__RESET_VALUE 0x00000000U + +#endif /* __PWM_FSM_STATE_MACRO__ */ + +/** @} end of fsm_state */ + +/* macros for BlueprintGlobalNameSpace::PWM_fifo_cfg */ +/** + * @defgroup at_apb_pwm_regs_core_fifo_cfg fifo_cfg + * @brief fifo configuration definitions. + * @{ + */ +#ifndef __PWM_FIFO_CFG_MACRO__ +#define __PWM_FIFO_CFG_MACRO__ + +/* macros for field lwm */ +/** + * @defgroup at_apb_pwm_regs_core_lwm_field lwm_field + * @brief macros for field lwm + * @details low water mark (lwm) of FIF0; a trigger is issued when FIFO has been drained to these many open slots. Constraint (1<= LWM <= 16) triggers when the number of open slots changes from (lwm - 1) to (lwm). lwm = 15 means an interrupt is issued as the number of open slots changes from 14 to 15. In other words, the number of entries in the fifo changes from 2 to 1. + * @{ + */ +#define PWM_FIFO_CFG__LWM__SHIFT 0 +#define PWM_FIFO_CFG__LWM__WIDTH 5 +#define PWM_FIFO_CFG__LWM__MASK 0x0000001fU +#define PWM_FIFO_CFG__LWM__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define PWM_FIFO_CFG__LWM__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define PWM_FIFO_CFG__LWM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define PWM_FIFO_CFG__LWM__VERIFY(src) (!(((uint32_t)(src) & ~0x0000001fU))) +#define PWM_FIFO_CFG__LWM__RESET_VALUE 0x0000000fU +/** @} */ + +/* macros for field flush */ +/** + * @defgroup at_apb_pwm_regs_core_flush_field flush_field + * @brief macros for field flush + * @details Signal's rising edge clears out fifo. Not self-clearing + * @{ + */ +#define PWM_FIFO_CFG__FLUSH__SHIFT 6 +#define PWM_FIFO_CFG__FLUSH__WIDTH 1 +#define PWM_FIFO_CFG__FLUSH__MASK 0x00000040U +#define PWM_FIFO_CFG__FLUSH__READ(src) (((uint32_t)(src) & 0x00000040U) >> 6) +#define PWM_FIFO_CFG__FLUSH__WRITE(src) (((uint32_t)(src) << 6) & 0x00000040U) +#define PWM_FIFO_CFG__FLUSH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PWM_FIFO_CFG__FLUSH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PWM_FIFO_CFG__FLUSH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PWM_FIFO_CFG__FLUSH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PWM_FIFO_CFG__FLUSH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch_stop */ +/** + * @defgroup at_apb_pwm_regs_core_ch_stop_field ch_stop_field + * @brief macros for field ch_stop + * @details when set, stops channel running in IR_FIFO_MODE after last fifo command is done. otherwise, the last command keeps repeating. + * @{ + */ +#define PWM_FIFO_CFG__CH_STOP__SHIFT 7 +#define PWM_FIFO_CFG__CH_STOP__WIDTH 1 +#define PWM_FIFO_CFG__CH_STOP__MASK 0x00000080U +#define PWM_FIFO_CFG__CH_STOP__READ(src) (((uint32_t)(src) & 0x00000080U) >> 7) +#define PWM_FIFO_CFG__CH_STOP__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define PWM_FIFO_CFG__CH_STOP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define PWM_FIFO_CFG__CH_STOP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define PWM_FIFO_CFG__CH_STOP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define PWM_FIFO_CFG__CH_STOP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define PWM_FIFO_CFG__CH_STOP__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_FIFO_CFG__TYPE uint32_t +#define PWM_FIFO_CFG__READ 0x000000dfU +#define PWM_FIFO_CFG__WRITE 0x000000dfU +#define PWM_FIFO_CFG__PRESERVED 0x00000000U +#define PWM_FIFO_CFG__RESET_VALUE 0x0000000fU + +#endif /* __PWM_FIFO_CFG_MACRO__ */ + +/** @} end of fifo_cfg */ + +/* macros for BlueprintGlobalNameSpace::PWM_fifo_carrier1_dur */ +/** + * @defgroup at_apb_pwm_regs_core_fifo_carrier1_dur fifo_carrier1_dur + * @brief carrier1 frequency durations for IR_FIFO_MODE definitions. + * @{ + */ +#ifndef __PWM_FIFO_CARRIER1_DUR_MACRO__ +#define __PWM_FIFO_CARRIER1_DUR_MACRO__ + +/* macros for field lo_dur */ +/** + * @defgroup at_apb_pwm_regs_core_lo_dur_field lo_dur_field + * @brief macros for field lo_dur + * @details duration of low portion of period in clk_mpc clock cycles = lo_dur. (lo_dur=1/hi_dur=0 not supported) + * @{ + */ +#define PWM_FIFO_CARRIER1_DUR__LO_DUR__SHIFT 0 +#define PWM_FIFO_CARRIER1_DUR__LO_DUR__WIDTH 16 +#define PWM_FIFO_CARRIER1_DUR__LO_DUR__MASK 0x0000ffffU +#define PWM_FIFO_CARRIER1_DUR__LO_DUR__READ(src) \ + ((uint32_t)(src)\ + & 0x0000ffffU) +#define PWM_FIFO_CARRIER1_DUR__LO_DUR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000ffffU) +#define PWM_FIFO_CARRIER1_DUR__LO_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define PWM_FIFO_CARRIER1_DUR__LO_DUR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000ffffU))) +#define PWM_FIFO_CARRIER1_DUR__LO_DUR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hi_dur */ +/** + * @defgroup at_apb_pwm_regs_core_hi_dur_field hi_dur_field + * @brief macros for field hi_dur + * @details duration of high portion of period in clk_mpc clock cycles = hi_dur.(hi_dur=1/lo_dur=0 not supported) + * @{ + */ +#define PWM_FIFO_CARRIER1_DUR__HI_DUR__SHIFT 16 +#define PWM_FIFO_CARRIER1_DUR__HI_DUR__WIDTH 16 +#define PWM_FIFO_CARRIER1_DUR__HI_DUR__MASK 0xffff0000U +#define PWM_FIFO_CARRIER1_DUR__HI_DUR__READ(src) \ + (((uint32_t)(src)\ + & 0xffff0000U) >> 16) +#define PWM_FIFO_CARRIER1_DUR__HI_DUR__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0xffff0000U) +#define PWM_FIFO_CARRIER1_DUR__HI_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define PWM_FIFO_CARRIER1_DUR__HI_DUR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define PWM_FIFO_CARRIER1_DUR__HI_DUR__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_FIFO_CARRIER1_DUR__TYPE uint32_t +#define PWM_FIFO_CARRIER1_DUR__READ 0xffffffffU +#define PWM_FIFO_CARRIER1_DUR__WRITE 0xffffffffU +#define PWM_FIFO_CARRIER1_DUR__PRESERVED 0x00000000U +#define PWM_FIFO_CARRIER1_DUR__RESET_VALUE 0x00000000U + +#endif /* __PWM_FIFO_CARRIER1_DUR_MACRO__ */ + +/** @} end of fifo_carrier1_dur */ + +/* macros for BlueprintGlobalNameSpace::PWM_fifo_carrier2_dur */ +/** + * @defgroup at_apb_pwm_regs_core_fifo_carrier2_dur fifo_carrier2_dur + * @brief carrier2 frequency durations for IR_FIFO_MODE definitions. + * @{ + */ +#ifndef __PWM_FIFO_CARRIER2_DUR_MACRO__ +#define __PWM_FIFO_CARRIER2_DUR_MACRO__ + +/* macros for field lo_dur */ +/** + * @defgroup at_apb_pwm_regs_core_lo_dur_field lo_dur_field + * @brief macros for field lo_dur + * @details duration of low portion of period in clk_mpc clock cycles = lo_dur. (lo_dur=1/hi_dur=0 not supported) + * @{ + */ +#define PWM_FIFO_CARRIER2_DUR__LO_DUR__SHIFT 0 +#define PWM_FIFO_CARRIER2_DUR__LO_DUR__WIDTH 16 +#define PWM_FIFO_CARRIER2_DUR__LO_DUR__MASK 0x0000ffffU +#define PWM_FIFO_CARRIER2_DUR__LO_DUR__READ(src) \ + ((uint32_t)(src)\ + & 0x0000ffffU) +#define PWM_FIFO_CARRIER2_DUR__LO_DUR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000ffffU) +#define PWM_FIFO_CARRIER2_DUR__LO_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define PWM_FIFO_CARRIER2_DUR__LO_DUR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000ffffU))) +#define PWM_FIFO_CARRIER2_DUR__LO_DUR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hi_dur */ +/** + * @defgroup at_apb_pwm_regs_core_hi_dur_field hi_dur_field + * @brief macros for field hi_dur + * @details duration of high portion of period in clk_mpc clock cycles = hi_dur.(hi_dur=1/lo_dur=0 not supported) + * @{ + */ +#define PWM_FIFO_CARRIER2_DUR__HI_DUR__SHIFT 16 +#define PWM_FIFO_CARRIER2_DUR__HI_DUR__WIDTH 16 +#define PWM_FIFO_CARRIER2_DUR__HI_DUR__MASK 0xffff0000U +#define PWM_FIFO_CARRIER2_DUR__HI_DUR__READ(src) \ + (((uint32_t)(src)\ + & 0xffff0000U) >> 16) +#define PWM_FIFO_CARRIER2_DUR__HI_DUR__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0xffff0000U) +#define PWM_FIFO_CARRIER2_DUR__HI_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define PWM_FIFO_CARRIER2_DUR__HI_DUR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define PWM_FIFO_CARRIER2_DUR__HI_DUR__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_FIFO_CARRIER2_DUR__TYPE uint32_t +#define PWM_FIFO_CARRIER2_DUR__READ 0xffffffffU +#define PWM_FIFO_CARRIER2_DUR__WRITE 0xffffffffU +#define PWM_FIFO_CARRIER2_DUR__PRESERVED 0x00000000U +#define PWM_FIFO_CARRIER2_DUR__RESET_VALUE 0x00000000U + +#endif /* __PWM_FIFO_CARRIER2_DUR_MACRO__ */ + +/** @} end of fifo_carrier2_dur */ + +/* macros for BlueprintGlobalNameSpace::PWM_fifo_stat */ +/** + * @defgroup at_apb_pwm_regs_core_fifo_stat fifo_stat + * @brief fifo status definitions. + * @{ + */ +#ifndef __PWM_FIFO_STAT_MACRO__ +#define __PWM_FIFO_STAT_MACRO__ + +/* macros for field full */ +/** + * @defgroup at_apb_pwm_regs_core_full_field full_field + * @brief macros for field full + * @details fifo is full. APB is stalled if a write is requested. + * @{ + */ +#define PWM_FIFO_STAT__FULL__SHIFT 0 +#define PWM_FIFO_STAT__FULL__WIDTH 1 +#define PWM_FIFO_STAT__FULL__MASK 0x00000001U +#define PWM_FIFO_STAT__FULL__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PWM_FIFO_STAT__FULL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PWM_FIFO_STAT__FULL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PWM_FIFO_STAT__FULL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field empty */ +/** + * @defgroup at_apb_pwm_regs_core_empty_field empty_field + * @brief macros for field empty + * @details fifo is empty. + * @{ + */ +#define PWM_FIFO_STAT__EMPTY__SHIFT 1 +#define PWM_FIFO_STAT__EMPTY__WIDTH 1 +#define PWM_FIFO_STAT__EMPTY__MASK 0x00000002U +#define PWM_FIFO_STAT__EMPTY__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define PWM_FIFO_STAT__EMPTY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PWM_FIFO_STAT__EMPTY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PWM_FIFO_STAT__EMPTY__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_FIFO_STAT__TYPE uint32_t +#define PWM_FIFO_STAT__READ 0x00000003U +#define PWM_FIFO_STAT__PRESERVED 0x00000000U +#define PWM_FIFO_STAT__RESET_VALUE 0x00000000U + +#endif /* __PWM_FIFO_STAT_MACRO__ */ + +/** @} end of fifo_stat */ + +/* macros for BlueprintGlobalNameSpace::PWM_fifo_stat1 */ +/** + * @defgroup at_apb_pwm_regs_core_fifo_stat1 fifo_stat1 + * @brief fifo status definitions. + * @{ + */ +#ifndef __PWM_FIFO_STAT1_MACRO__ +#define __PWM_FIFO_STAT1_MACRO__ + +/* macros for field num_open_slots */ +/** + * @defgroup at_apb_pwm_regs_core_num_open_slots_field num_open_slots_field + * @brief macros for field num_open_slots + * @details open slots in FIFO + * @{ + */ +#define PWM_FIFO_STAT1__NUM_OPEN_SLOTS__SHIFT 0 +#define PWM_FIFO_STAT1__NUM_OPEN_SLOTS__WIDTH 5 +#define PWM_FIFO_STAT1__NUM_OPEN_SLOTS__MASK 0x0000001fU +#define PWM_FIFO_STAT1__NUM_OPEN_SLOTS__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define PWM_FIFO_STAT1__NUM_OPEN_SLOTS__RESET_VALUE 0x00000010U +/** @} */ +#define PWM_FIFO_STAT1__TYPE uint32_t +#define PWM_FIFO_STAT1__READ 0x0000001fU +#define PWM_FIFO_STAT1__PRESERVED 0x00000000U +#define PWM_FIFO_STAT1__RESET_VALUE 0x00000010U + +#endif /* __PWM_FIFO_STAT1_MACRO__ */ + +/** @} end of fifo_stat1 */ + +/* macros for BlueprintGlobalNameSpace::PWM_fifo_sel_err_source */ +/** + * @defgroup at_apb_pwm_regs_core_fifo_sel_err_source fifo_sel_err_source + * @brief HW sets and SW write 0 to clear and 1 to set these bits. Set takes precedence. definitions. + * @{ + */ +#ifndef __PWM_FIFO_SEL_ERR_SOURCE_MACRO__ +#define __PWM_FIFO_SEL_ERR_SOURCE_MACRO__ + +/* macros for field ch0_fifo_sel_err */ +/** + * @defgroup at_apb_pwm_regs_core_ch0_fifo_sel_err_field ch0_fifo_sel_err_field + * @brief macros for field ch0_fifo_sel_err + * @details pwm0 channel caused fifo_sel_err_intrpt; + * @{ + */ +#define PWM_FIFO_SEL_ERR_SOURCE__CH0_FIFO_SEL_ERR__SHIFT 0 +#define PWM_FIFO_SEL_ERR_SOURCE__CH0_FIFO_SEL_ERR__WIDTH 1 +#define PWM_FIFO_SEL_ERR_SOURCE__CH0_FIFO_SEL_ERR__MASK 0x00000001U +#define PWM_FIFO_SEL_ERR_SOURCE__CH0_FIFO_SEL_ERR__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PWM_FIFO_SEL_ERR_SOURCE__CH0_FIFO_SEL_ERR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PWM_FIFO_SEL_ERR_SOURCE__CH0_FIFO_SEL_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PWM_FIFO_SEL_ERR_SOURCE__CH0_FIFO_SEL_ERR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PWM_FIFO_SEL_ERR_SOURCE__CH0_FIFO_SEL_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PWM_FIFO_SEL_ERR_SOURCE__CH0_FIFO_SEL_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PWM_FIFO_SEL_ERR_SOURCE__CH0_FIFO_SEL_ERR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch1_fifo_sel_err */ +/** + * @defgroup at_apb_pwm_regs_core_ch1_fifo_sel_err_field ch1_fifo_sel_err_field + * @brief macros for field ch1_fifo_sel_err + * @details pwm1 channel caused fifo_sel_err_intrpt; + * @{ + */ +#define PWM_FIFO_SEL_ERR_SOURCE__CH1_FIFO_SEL_ERR__SHIFT 1 +#define PWM_FIFO_SEL_ERR_SOURCE__CH1_FIFO_SEL_ERR__WIDTH 1 +#define PWM_FIFO_SEL_ERR_SOURCE__CH1_FIFO_SEL_ERR__MASK 0x00000002U +#define PWM_FIFO_SEL_ERR_SOURCE__CH1_FIFO_SEL_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PWM_FIFO_SEL_ERR_SOURCE__CH1_FIFO_SEL_ERR__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PWM_FIFO_SEL_ERR_SOURCE__CH1_FIFO_SEL_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PWM_FIFO_SEL_ERR_SOURCE__CH1_FIFO_SEL_ERR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PWM_FIFO_SEL_ERR_SOURCE__CH1_FIFO_SEL_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PWM_FIFO_SEL_ERR_SOURCE__CH1_FIFO_SEL_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PWM_FIFO_SEL_ERR_SOURCE__CH1_FIFO_SEL_ERR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch2_fifo_sel_err */ +/** + * @defgroup at_apb_pwm_regs_core_ch2_fifo_sel_err_field ch2_fifo_sel_err_field + * @brief macros for field ch2_fifo_sel_err + * @details pwm2 channel caused fifo_sel_err_intrpt; + * @{ + */ +#define PWM_FIFO_SEL_ERR_SOURCE__CH2_FIFO_SEL_ERR__SHIFT 2 +#define PWM_FIFO_SEL_ERR_SOURCE__CH2_FIFO_SEL_ERR__WIDTH 1 +#define PWM_FIFO_SEL_ERR_SOURCE__CH2_FIFO_SEL_ERR__MASK 0x00000004U +#define PWM_FIFO_SEL_ERR_SOURCE__CH2_FIFO_SEL_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PWM_FIFO_SEL_ERR_SOURCE__CH2_FIFO_SEL_ERR__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PWM_FIFO_SEL_ERR_SOURCE__CH2_FIFO_SEL_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PWM_FIFO_SEL_ERR_SOURCE__CH2_FIFO_SEL_ERR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PWM_FIFO_SEL_ERR_SOURCE__CH2_FIFO_SEL_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PWM_FIFO_SEL_ERR_SOURCE__CH2_FIFO_SEL_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PWM_FIFO_SEL_ERR_SOURCE__CH2_FIFO_SEL_ERR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch3_fifo_sel_err */ +/** + * @defgroup at_apb_pwm_regs_core_ch3_fifo_sel_err_field ch3_fifo_sel_err_field + * @brief macros for field ch3_fifo_sel_err + * @details pwm3 channel caused fifo_sel_err_intrpt; + * @{ + */ +#define PWM_FIFO_SEL_ERR_SOURCE__CH3_FIFO_SEL_ERR__SHIFT 3 +#define PWM_FIFO_SEL_ERR_SOURCE__CH3_FIFO_SEL_ERR__WIDTH 1 +#define PWM_FIFO_SEL_ERR_SOURCE__CH3_FIFO_SEL_ERR__MASK 0x00000008U +#define PWM_FIFO_SEL_ERR_SOURCE__CH3_FIFO_SEL_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PWM_FIFO_SEL_ERR_SOURCE__CH3_FIFO_SEL_ERR__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PWM_FIFO_SEL_ERR_SOURCE__CH3_FIFO_SEL_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PWM_FIFO_SEL_ERR_SOURCE__CH3_FIFO_SEL_ERR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PWM_FIFO_SEL_ERR_SOURCE__CH3_FIFO_SEL_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PWM_FIFO_SEL_ERR_SOURCE__CH3_FIFO_SEL_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PWM_FIFO_SEL_ERR_SOURCE__CH3_FIFO_SEL_ERR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch4_fifo_sel_err */ +/** + * @defgroup at_apb_pwm_regs_core_ch4_fifo_sel_err_field ch4_fifo_sel_err_field + * @brief macros for field ch4_fifo_sel_err + * @details pwm4 channel caused fifo_sel_err_intrpt; + * @{ + */ +#define PWM_FIFO_SEL_ERR_SOURCE__CH4_FIFO_SEL_ERR__SHIFT 4 +#define PWM_FIFO_SEL_ERR_SOURCE__CH4_FIFO_SEL_ERR__WIDTH 1 +#define PWM_FIFO_SEL_ERR_SOURCE__CH4_FIFO_SEL_ERR__MASK 0x00000010U +#define PWM_FIFO_SEL_ERR_SOURCE__CH4_FIFO_SEL_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PWM_FIFO_SEL_ERR_SOURCE__CH4_FIFO_SEL_ERR__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PWM_FIFO_SEL_ERR_SOURCE__CH4_FIFO_SEL_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PWM_FIFO_SEL_ERR_SOURCE__CH4_FIFO_SEL_ERR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PWM_FIFO_SEL_ERR_SOURCE__CH4_FIFO_SEL_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PWM_FIFO_SEL_ERR_SOURCE__CH4_FIFO_SEL_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PWM_FIFO_SEL_ERR_SOURCE__CH4_FIFO_SEL_ERR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch5_fifo_sel_err */ +/** + * @defgroup at_apb_pwm_regs_core_ch5_fifo_sel_err_field ch5_fifo_sel_err_field + * @brief macros for field ch5_fifo_sel_err + * @details pwm5 channel caused fifo_sel_err_intrpt; + * @{ + */ +#define PWM_FIFO_SEL_ERR_SOURCE__CH5_FIFO_SEL_ERR__SHIFT 5 +#define PWM_FIFO_SEL_ERR_SOURCE__CH5_FIFO_SEL_ERR__WIDTH 1 +#define PWM_FIFO_SEL_ERR_SOURCE__CH5_FIFO_SEL_ERR__MASK 0x00000020U +#define PWM_FIFO_SEL_ERR_SOURCE__CH5_FIFO_SEL_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PWM_FIFO_SEL_ERR_SOURCE__CH5_FIFO_SEL_ERR__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define PWM_FIFO_SEL_ERR_SOURCE__CH5_FIFO_SEL_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define PWM_FIFO_SEL_ERR_SOURCE__CH5_FIFO_SEL_ERR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define PWM_FIFO_SEL_ERR_SOURCE__CH5_FIFO_SEL_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PWM_FIFO_SEL_ERR_SOURCE__CH5_FIFO_SEL_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PWM_FIFO_SEL_ERR_SOURCE__CH5_FIFO_SEL_ERR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch6_fifo_sel_err */ +/** + * @defgroup at_apb_pwm_regs_core_ch6_fifo_sel_err_field ch6_fifo_sel_err_field + * @brief macros for field ch6_fifo_sel_err + * @details pwm6 channel caused fifo_sel_err_intrpt; + * @{ + */ +#define PWM_FIFO_SEL_ERR_SOURCE__CH6_FIFO_SEL_ERR__SHIFT 6 +#define PWM_FIFO_SEL_ERR_SOURCE__CH6_FIFO_SEL_ERR__WIDTH 1 +#define PWM_FIFO_SEL_ERR_SOURCE__CH6_FIFO_SEL_ERR__MASK 0x00000040U +#define PWM_FIFO_SEL_ERR_SOURCE__CH6_FIFO_SEL_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define PWM_FIFO_SEL_ERR_SOURCE__CH6_FIFO_SEL_ERR__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define PWM_FIFO_SEL_ERR_SOURCE__CH6_FIFO_SEL_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PWM_FIFO_SEL_ERR_SOURCE__CH6_FIFO_SEL_ERR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PWM_FIFO_SEL_ERR_SOURCE__CH6_FIFO_SEL_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PWM_FIFO_SEL_ERR_SOURCE__CH6_FIFO_SEL_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PWM_FIFO_SEL_ERR_SOURCE__CH6_FIFO_SEL_ERR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ch7_fifo_sel_err */ +/** + * @defgroup at_apb_pwm_regs_core_ch7_fifo_sel_err_field ch7_fifo_sel_err_field + * @brief macros for field ch7_fifo_sel_err + * @details pwm7 channel caused fifo_sel_err_intrpt; + * @{ + */ +#define PWM_FIFO_SEL_ERR_SOURCE__CH7_FIFO_SEL_ERR__SHIFT 7 +#define PWM_FIFO_SEL_ERR_SOURCE__CH7_FIFO_SEL_ERR__WIDTH 1 +#define PWM_FIFO_SEL_ERR_SOURCE__CH7_FIFO_SEL_ERR__MASK 0x00000080U +#define PWM_FIFO_SEL_ERR_SOURCE__CH7_FIFO_SEL_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define PWM_FIFO_SEL_ERR_SOURCE__CH7_FIFO_SEL_ERR__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define PWM_FIFO_SEL_ERR_SOURCE__CH7_FIFO_SEL_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define PWM_FIFO_SEL_ERR_SOURCE__CH7_FIFO_SEL_ERR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define PWM_FIFO_SEL_ERR_SOURCE__CH7_FIFO_SEL_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define PWM_FIFO_SEL_ERR_SOURCE__CH7_FIFO_SEL_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define PWM_FIFO_SEL_ERR_SOURCE__CH7_FIFO_SEL_ERR__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_FIFO_SEL_ERR_SOURCE__TYPE uint32_t +#define PWM_FIFO_SEL_ERR_SOURCE__READ 0x000000ffU +#define PWM_FIFO_SEL_ERR_SOURCE__WRITE 0x000000ffU +#define PWM_FIFO_SEL_ERR_SOURCE__PRESERVED 0x00000000U +#define PWM_FIFO_SEL_ERR_SOURCE__RESET_VALUE 0x00000000U + +#endif /* __PWM_FIFO_SEL_ERR_SOURCE_MACRO__ */ + +/** @} end of fifo_sel_err_source */ + +/* macros for BlueprintGlobalNameSpace::PWM_interrupts */ +/** + * @defgroup at_apb_pwm_regs_core_interrupts interrupts + * @brief Contains register fields associated with interrupts. definitions. + * @{ + */ +#ifndef __PWM_INTERRUPTS_MACRO__ +#define __PWM_INTERRUPTS_MACRO__ + +/* macros for field fifo_ovrflow_intrpt */ +/** + * @defgroup at_apb_pwm_regs_core_fifo_ovrflow_intrpt_field fifo_ovrflow_intrpt_field + * @brief macros for field fifo_ovrflow_intrpt + * @details HW sets when a write to fifo happens when fifo is full. + * @{ + */ +#define PWM_INTERRUPTS__FIFO_OVRFLOW_INTRPT__SHIFT 0 +#define PWM_INTERRUPTS__FIFO_OVRFLOW_INTRPT__WIDTH 1 +#define PWM_INTERRUPTS__FIFO_OVRFLOW_INTRPT__MASK 0x00000001U +#define PWM_INTERRUPTS__FIFO_OVRFLOW_INTRPT__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PWM_INTERRUPTS__FIFO_OVRFLOW_INTRPT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PWM_INTERRUPTS__FIFO_OVRFLOW_INTRPT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PWM_INTERRUPTS__FIFO_OVRFLOW_INTRPT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fifo_lwm_hit_intrpt */ +/** + * @defgroup at_apb_pwm_regs_core_fifo_lwm_hit_intrpt_field fifo_lwm_hit_intrpt_field + * @brief macros for field fifo_lwm_hit_intrpt + * @details HW sets when lwm condition is hit. + * @{ + */ +#define PWM_INTERRUPTS__FIFO_LWM_HIT_INTRPT__SHIFT 1 +#define PWM_INTERRUPTS__FIFO_LWM_HIT_INTRPT__WIDTH 1 +#define PWM_INTERRUPTS__FIFO_LWM_HIT_INTRPT__MASK 0x00000002U +#define PWM_INTERRUPTS__FIFO_LWM_HIT_INTRPT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PWM_INTERRUPTS__FIFO_LWM_HIT_INTRPT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PWM_INTERRUPTS__FIFO_LWM_HIT_INTRPT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PWM_INTERRUPTS__FIFO_LWM_HIT_INTRPT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fifo_sel_err_intrpt */ +/** + * @defgroup at_apb_pwm_regs_core_fifo_sel_err_intrpt_field fifo_sel_err_intrpt_field + * @brief macros for field fifo_sel_err_intrpt + * @details HW sets when a channel is in IR_FIFO_MODE but not given the FIFO; FIFO being used by another channel. With the conflict condition as described, an error assertion happens when channel is in idle and ok_to_run is issued. Consequently, the internal state registers of the channel revert to default values. + * @{ + */ +#define PWM_INTERRUPTS__FIFO_SEL_ERR_INTRPT__SHIFT 2 +#define PWM_INTERRUPTS__FIFO_SEL_ERR_INTRPT__WIDTH 1 +#define PWM_INTERRUPTS__FIFO_SEL_ERR_INTRPT__MASK 0x00000004U +#define PWM_INTERRUPTS__FIFO_SEL_ERR_INTRPT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PWM_INTERRUPTS__FIFO_SEL_ERR_INTRPT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PWM_INTERRUPTS__FIFO_SEL_ERR_INTRPT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PWM_INTERRUPTS__FIFO_SEL_ERR_INTRPT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fifo_cmd_done_intrpt */ +/** + * @defgroup at_apb_pwm_regs_core_fifo_cmd_done_intrpt_field fifo_cmd_done_intrpt_field + * @brief macros for field fifo_cmd_done_intrpt + * @details HW sets when a channel is in IR_FIFO_MODE and last cmmand in fifo is done. + * @{ + */ +#define PWM_INTERRUPTS__FIFO_CMD_DONE_INTRPT__SHIFT 3 +#define PWM_INTERRUPTS__FIFO_CMD_DONE_INTRPT__WIDTH 1 +#define PWM_INTERRUPTS__FIFO_CMD_DONE_INTRPT__MASK 0x00000008U +#define PWM_INTERRUPTS__FIFO_CMD_DONE_INTRPT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PWM_INTERRUPTS__FIFO_CMD_DONE_INTRPT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PWM_INTERRUPTS__FIFO_CMD_DONE_INTRPT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PWM_INTERRUPTS__FIFO_CMD_DONE_INTRPT__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_INTERRUPTS__TYPE uint32_t +#define PWM_INTERRUPTS__READ 0x0000000fU +#define PWM_INTERRUPTS__PRESERVED 0x00000000U +#define PWM_INTERRUPTS__RESET_VALUE 0x00000000U + +#endif /* __PWM_INTERRUPTS_MACRO__ */ + +/** @} end of interrupts */ + +/* macros for BlueprintGlobalNameSpace::PWM_interrupts_mask */ +/** + * @defgroup at_apb_pwm_regs_core_interrupts_mask interrupts_mask + * @brief Contains register fields associated with interrupts_mask. definitions. + * @{ + */ +#ifndef __PWM_INTERRUPTS_MASK_MACRO__ +#define __PWM_INTERRUPTS_MASK_MACRO__ + +/* macros for field mask_intrpt0 */ +/** + * @defgroup at_apb_pwm_regs_core_mask_intrpt0_field mask_intrpt0_field + * @brief macros for field mask_intrpt0 + * @details allows fifo_ovrflow_intrpt to propogate to channel's combined interrupt. + * @{ + */ +#define PWM_INTERRUPTS_MASK__MASK_INTRPT0__SHIFT 0 +#define PWM_INTERRUPTS_MASK__MASK_INTRPT0__WIDTH 1 +#define PWM_INTERRUPTS_MASK__MASK_INTRPT0__MASK 0x00000001U +#define PWM_INTERRUPTS_MASK__MASK_INTRPT0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT0__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT0__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field mask_intrpt1 */ +/** + * @defgroup at_apb_pwm_regs_core_mask_intrpt1_field mask_intrpt1_field + * @brief macros for field mask_intrpt1 + * @details allows lwm_hit_intrpt to propogate to channel's combined interrupt. + * @{ + */ +#define PWM_INTERRUPTS_MASK__MASK_INTRPT1__SHIFT 1 +#define PWM_INTERRUPTS_MASK__MASK_INTRPT1__WIDTH 1 +#define PWM_INTERRUPTS_MASK__MASK_INTRPT1__MASK 0x00000002U +#define PWM_INTERRUPTS_MASK__MASK_INTRPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT1__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT1__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field mask_intrpt2 */ +/** + * @defgroup at_apb_pwm_regs_core_mask_intrpt2_field mask_intrpt2_field + * @brief macros for field mask_intrpt2 + * @details allows fifo_sel_err_intrpt to propagate to channel's combined interrupt. + * @{ + */ +#define PWM_INTERRUPTS_MASK__MASK_INTRPT2__SHIFT 2 +#define PWM_INTERRUPTS_MASK__MASK_INTRPT2__WIDTH 1 +#define PWM_INTERRUPTS_MASK__MASK_INTRPT2__MASK 0x00000004U +#define PWM_INTERRUPTS_MASK__MASK_INTRPT2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT2__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mask_intrpt3 */ +/** + * @defgroup at_apb_pwm_regs_core_mask_intrpt3_field mask_intrpt3_field + * @brief macros for field mask_intrpt3 + * @details allows fifo_cmd_done_intrpt to propagate to channel's combined interrupt. + * @{ + */ +#define PWM_INTERRUPTS_MASK__MASK_INTRPT3__SHIFT 3 +#define PWM_INTERRUPTS_MASK__MASK_INTRPT3__WIDTH 1 +#define PWM_INTERRUPTS_MASK__MASK_INTRPT3__MASK 0x00000008U +#define PWM_INTERRUPTS_MASK__MASK_INTRPT3__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT3__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PWM_INTERRUPTS_MASK__MASK_INTRPT3__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_INTERRUPTS_MASK__TYPE uint32_t +#define PWM_INTERRUPTS_MASK__READ 0x0000000fU +#define PWM_INTERRUPTS_MASK__WRITE 0x0000000fU +#define PWM_INTERRUPTS_MASK__PRESERVED 0x00000000U +#define PWM_INTERRUPTS_MASK__RESET_VALUE 0x00000003U + +#endif /* __PWM_INTERRUPTS_MASK_MACRO__ */ + +/** @} end of interrupts_mask */ + +/* macros for BlueprintGlobalNameSpace::PWM_interrupts_clear */ +/** + * @defgroup at_apb_pwm_regs_core_interrupts_clear interrupts_clear + * @brief Contains register fields associated with interrupts_clear. definitions. + * @{ + */ +#ifndef __PWM_INTERRUPTS_CLEAR_MACRO__ +#define __PWM_INTERRUPTS_CLEAR_MACRO__ + +/* macros for field clear_intrpt0 */ +/** + * @defgroup at_apb_pwm_regs_core_clear_intrpt0_field clear_intrpt0_field + * @brief macros for field clear_intrpt0 + * @details clears fifo_overflow_intrpt; not auto cleared. + * @{ + */ +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT0__SHIFT 0 +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT0__WIDTH 1 +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT0__MASK 0x00000001U +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT0__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_intrpt1 */ +/** + * @defgroup at_apb_pwm_regs_core_clear_intrpt1_field clear_intrpt1_field + * @brief macros for field clear_intrpt1 + * @details clears lwm_hit_intrpt; not auto cleared. + * @{ + */ +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT1__SHIFT 1 +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT1__WIDTH 1 +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT1__MASK 0x00000002U +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT1__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_intrpt2 */ +/** + * @defgroup at_apb_pwm_regs_core_clear_intrpt2_field clear_intrpt2_field + * @brief macros for field clear_intrpt2 + * @details clears fifo_sel_error_intrpt; not auto cleared. + * @{ + */ +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT2__SHIFT 2 +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT2__WIDTH 1 +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT2__MASK 0x00000004U +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT2__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_intrpt3 */ +/** + * @defgroup at_apb_pwm_regs_core_clear_intrpt3_field clear_intrpt3_field + * @brief macros for field clear_intrpt3 + * @details clears fifo_cmd_done_intrpt; not auto cleared. + * @{ + */ +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT3__SHIFT 3 +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT3__WIDTH 1 +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT3__MASK 0x00000008U +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT3__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT3__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PWM_INTERRUPTS_CLEAR__CLEAR_INTRPT3__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_INTERRUPTS_CLEAR__TYPE uint32_t +#define PWM_INTERRUPTS_CLEAR__READ 0x0000000fU +#define PWM_INTERRUPTS_CLEAR__WRITE 0x0000000fU +#define PWM_INTERRUPTS_CLEAR__PRESERVED 0x00000000U +#define PWM_INTERRUPTS_CLEAR__RESET_VALUE 0x00000000U + +#endif /* __PWM_INTERRUPTS_CLEAR_MACRO__ */ + +/** @} end of interrupts_clear */ + +/* macros for BlueprintGlobalNameSpace::PWM_interrupts_set */ +/** + * @defgroup at_apb_pwm_regs_core_interrupts_set interrupts_set + * @brief Contains register fields associated with interrupts_set. definitions. + * @{ + */ +#ifndef __PWM_INTERRUPTS_SET_MACRO__ +#define __PWM_INTERRUPTS_SET_MACRO__ + +/* macros for field set_intrpt0 */ +/** + * @defgroup at_apb_pwm_regs_core_set_intrpt0_field set_intrpt0_field + * @brief macros for field set_intrpt0 + * @details sets fifo_overflow_intrpt; not auto cleared. + * @{ + */ +#define PWM_INTERRUPTS_SET__SET_INTRPT0__SHIFT 0 +#define PWM_INTERRUPTS_SET__SET_INTRPT0__WIDTH 1 +#define PWM_INTERRUPTS_SET__SET_INTRPT0__MASK 0x00000001U +#define PWM_INTERRUPTS_SET__SET_INTRPT0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PWM_INTERRUPTS_SET__SET_INTRPT0__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PWM_INTERRUPTS_SET__SET_INTRPT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PWM_INTERRUPTS_SET__SET_INTRPT0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PWM_INTERRUPTS_SET__SET_INTRPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PWM_INTERRUPTS_SET__SET_INTRPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PWM_INTERRUPTS_SET__SET_INTRPT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field set_intrpt1 */ +/** + * @defgroup at_apb_pwm_regs_core_set_intrpt1_field set_intrpt1_field + * @brief macros for field set_intrpt1 + * @details sets lwm_hit_intrpt; not auto cleared. + * @{ + */ +#define PWM_INTERRUPTS_SET__SET_INTRPT1__SHIFT 1 +#define PWM_INTERRUPTS_SET__SET_INTRPT1__WIDTH 1 +#define PWM_INTERRUPTS_SET__SET_INTRPT1__MASK 0x00000002U +#define PWM_INTERRUPTS_SET__SET_INTRPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PWM_INTERRUPTS_SET__SET_INTRPT1__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PWM_INTERRUPTS_SET__SET_INTRPT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PWM_INTERRUPTS_SET__SET_INTRPT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PWM_INTERRUPTS_SET__SET_INTRPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PWM_INTERRUPTS_SET__SET_INTRPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PWM_INTERRUPTS_SET__SET_INTRPT1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field set_intrpt2 */ +/** + * @defgroup at_apb_pwm_regs_core_set_intrpt2_field set_intrpt2_field + * @brief macros for field set_intrpt2 + * @details sets fifo_sel_error_intrpt; not auto cleared. + * @{ + */ +#define PWM_INTERRUPTS_SET__SET_INTRPT2__SHIFT 2 +#define PWM_INTERRUPTS_SET__SET_INTRPT2__WIDTH 1 +#define PWM_INTERRUPTS_SET__SET_INTRPT2__MASK 0x00000004U +#define PWM_INTERRUPTS_SET__SET_INTRPT2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PWM_INTERRUPTS_SET__SET_INTRPT2__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PWM_INTERRUPTS_SET__SET_INTRPT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PWM_INTERRUPTS_SET__SET_INTRPT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PWM_INTERRUPTS_SET__SET_INTRPT2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PWM_INTERRUPTS_SET__SET_INTRPT2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PWM_INTERRUPTS_SET__SET_INTRPT2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field set_intrpt3 */ +/** + * @defgroup at_apb_pwm_regs_core_set_intrpt3_field set_intrpt3_field + * @brief macros for field set_intrpt3 + * @details sets fifo_cmd_done_intrpt; not auto cleared. + * @{ + */ +#define PWM_INTERRUPTS_SET__SET_INTRPT3__SHIFT 3 +#define PWM_INTERRUPTS_SET__SET_INTRPT3__WIDTH 1 +#define PWM_INTERRUPTS_SET__SET_INTRPT3__MASK 0x00000008U +#define PWM_INTERRUPTS_SET__SET_INTRPT3__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PWM_INTERRUPTS_SET__SET_INTRPT3__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PWM_INTERRUPTS_SET__SET_INTRPT3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PWM_INTERRUPTS_SET__SET_INTRPT3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PWM_INTERRUPTS_SET__SET_INTRPT3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PWM_INTERRUPTS_SET__SET_INTRPT3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PWM_INTERRUPTS_SET__SET_INTRPT3__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_INTERRUPTS_SET__TYPE uint32_t +#define PWM_INTERRUPTS_SET__READ 0x0000000fU +#define PWM_INTERRUPTS_SET__WRITE 0x0000000fU +#define PWM_INTERRUPTS_SET__PRESERVED 0x00000000U +#define PWM_INTERRUPTS_SET__RESET_VALUE 0x00000000U + +#endif /* __PWM_INTERRUPTS_SET_MACRO__ */ + +/** @} end of interrupts_set */ + +/* macros for BlueprintGlobalNameSpace::PWM_fifo_data */ +/** + * @defgroup at_apb_pwm_regs_core_fifo_data fifo_data + * @brief write data to be stored in fifo definitions. + * @{ + */ +#ifndef __PWM_FIFO_DATA_MACRO__ +#define __PWM_FIFO_DATA_MACRO__ + +/* macros for field wdata */ +/** + * @defgroup at_apb_pwm_regs_core_wdata_field wdata_field + * @brief macros for field wdata + * @details [15] selects carrier frequency 0: use carrier frequency defined by fifo_carrier1_dur 1: use carrier frequency defined by fifo_carrier2_dur [14] selects between mark and space IR regions 0: output lo for the space region in IR. space region frame: hi_dur=0, lo_dur= hi+lo dur of selected carrier frequency max lo_dur is limited to 16bits. 1: output value defined by hi/lo dur for the mark region in IR [13:0]: frame_count + * @{ + */ +#define PWM_FIFO_DATA__WDATA__SHIFT 0 +#define PWM_FIFO_DATA__WDATA__WIDTH 16 +#define PWM_FIFO_DATA__WDATA__MASK 0x0000ffffU +#define PWM_FIFO_DATA__WDATA__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define PWM_FIFO_DATA__WDATA__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define PWM_FIFO_DATA__WDATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define PWM_FIFO_DATA__WDATA__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define PWM_FIFO_DATA__WDATA__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_FIFO_DATA__TYPE uint32_t +#define PWM_FIFO_DATA__READ 0x0000ffffU +#define PWM_FIFO_DATA__WRITE 0x0000ffffU +#define PWM_FIFO_DATA__PRESERVED 0x00000000U +#define PWM_FIFO_DATA__RESET_VALUE 0x00000000U + +#endif /* __PWM_FIFO_DATA_MACRO__ */ + +/** @} end of fifo_data */ + +/* macros for BlueprintGlobalNameSpace::PWM_core_id */ +/** + * @defgroup at_apb_pwm_regs_core_core_id core_id + * @brief Contains register fields associated with core_id. definitions. + * @{ + */ +#ifndef __PWM_CORE_ID_MACRO__ +#define __PWM_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_pwm_regs_core_id_field id_field + * @brief macros for field id + * @details PWM in ASCII + * @{ + */ +#define PWM_CORE_ID__ID__SHIFT 0 +#define PWM_CORE_ID__ID__WIDTH 32 +#define PWM_CORE_ID__ID__MASK 0xffffffffU +#define PWM_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PWM_CORE_ID__ID__RESET_VALUE 0x50574d20U +/** @} */ +#define PWM_CORE_ID__TYPE uint32_t +#define PWM_CORE_ID__READ 0xffffffffU +#define PWM_CORE_ID__PRESERVED 0x00000000U +#define PWM_CORE_ID__RESET_VALUE 0x50574d20U + +#endif /* __PWM_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/* macros for BlueprintGlobalNameSpace::PWM_rev_hash */ +/** + * @defgroup at_apb_pwm_regs_core_rev_hash rev_hash + * @brief Contains register fields associated with rev_hash. definitions. + * @{ + */ +#ifndef __PWM_REV_HASH_MACRO__ +#define __PWM_REV_HASH_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_pwm_regs_core_id_field id_field + * @brief macros for field id + * @details crc32 of this document; don't change value to anything other than 32'h00000000; scripts will fill it out in the verilog + * @{ + */ +#define PWM_REV_HASH__ID__SHIFT 0 +#define PWM_REV_HASH__ID__WIDTH 32 +#define PWM_REV_HASH__ID__MASK 0xffffffffU +#define PWM_REV_HASH__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PWM_REV_HASH__ID__RESET_VALUE 0x00000000U +/** @} */ +#define PWM_REV_HASH__TYPE uint32_t +#define PWM_REV_HASH__READ 0xffffffffU +#define PWM_REV_HASH__PRESERVED 0x00000000U +#define PWM_REV_HASH__RESET_VALUE 0x00000000U + +#endif /* __PWM_REV_HASH_MACRO__ */ + +/** @} end of rev_hash */ + +/* macros for BlueprintGlobalNameSpace::PWM_rev_key */ +/** + * @defgroup at_apb_pwm_regs_core_rev_key rev_key + * @brief Contains register fields associated with rev_key. definitions. + * @{ + */ +#ifndef __PWM_REV_KEY_MACRO__ +#define __PWM_REV_KEY_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_pwm_regs_core_id_field id_field + * @brief macros for field id + * @details REV in ASCII + * @{ + */ +#define PWM_REV_KEY__ID__SHIFT 0 +#define PWM_REV_KEY__ID__WIDTH 32 +#define PWM_REV_KEY__ID__MASK 0xffffffffU +#define PWM_REV_KEY__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PWM_REV_KEY__ID__RESET_VALUE 0x52455620U +/** @} */ +#define PWM_REV_KEY__TYPE uint32_t +#define PWM_REV_KEY__READ 0xffffffffU +#define PWM_REV_KEY__PRESERVED 0x00000000U +#define PWM_REV_KEY__RESET_VALUE 0x52455620U + +#endif /* __PWM_REV_KEY_MACRO__ */ + +/** @} end of rev_key */ + +/** @} end of AT_APB_PWM_REGS_CORE */ +#endif /* __REG_AT_APB_PWM_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_apb_qdec_regs_core_macro.h b/ATM33xx-5/include/reg/at_apb_qdec_regs_core_macro.h new file mode 100644 index 0000000..675fdbc --- /dev/null +++ b/ATM33xx-5/include/reg/at_apb_qdec_regs_core_macro.h @@ -0,0 +1,1100 @@ +/* */ +/* File: at_apb_qdec_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_apb_qdec_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_APB_QDEC_REGS_CORE_H__ +#define __REG_AT_APB_QDEC_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_APB_QDEC_REGS_CORE at_apb_qdec_regs_core + * @ingroup AT_REG + * @brief at_apb_qdec_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::QDEC_setup_for_axis_0 */ +/** + * @defgroup at_apb_qdec_regs_core_setup_for_axis_0 setup_for_axis_0 + * @brief Contains register fields associated with setup_for_axis_0. definitions. + * @{ + */ +#ifndef __QDEC_SETUP_FOR_AXIS_0_MACRO__ +#define __QDEC_SETUP_FOR_AXIS_0_MACRO__ + +/* macros for field enable_loopback */ +/** + * @defgroup at_apb_qdec_regs_core_enable_loopback_field enable_loopback_field + * @brief macros for field enable_loopback + * @{ + */ +#define QDEC_SETUP_FOR_AXIS_0__ENABLE_LOOPBACK__SHIFT 0 +#define QDEC_SETUP_FOR_AXIS_0__ENABLE_LOOPBACK__WIDTH 1 +#define QDEC_SETUP_FOR_AXIS_0__ENABLE_LOOPBACK__MASK 0x00000001U +#define QDEC_SETUP_FOR_AXIS_0__ENABLE_LOOPBACK__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define QDEC_SETUP_FOR_AXIS_0__ENABLE_LOOPBACK__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define QDEC_SETUP_FOR_AXIS_0__ENABLE_LOOPBACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define QDEC_SETUP_FOR_AXIS_0__ENABLE_LOOPBACK__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define QDEC_SETUP_FOR_AXIS_0__ENABLE_LOOPBACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define QDEC_SETUP_FOR_AXIS_0__ENABLE_LOOPBACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define QDEC_SETUP_FOR_AXIS_0__ENABLE_LOOPBACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field qsig_b_loopback_val */ +/** + * @defgroup at_apb_qdec_regs_core_qsig_b_loopback_val_field qsig_b_loopback_val_field + * @brief macros for field qsig_b_loopback_val + * @{ + */ +#define QDEC_SETUP_FOR_AXIS_0__QSIG_B_LOOPBACK_VAL__SHIFT 1 +#define QDEC_SETUP_FOR_AXIS_0__QSIG_B_LOOPBACK_VAL__WIDTH 1 +#define QDEC_SETUP_FOR_AXIS_0__QSIG_B_LOOPBACK_VAL__MASK 0x00000002U +#define QDEC_SETUP_FOR_AXIS_0__QSIG_B_LOOPBACK_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define QDEC_SETUP_FOR_AXIS_0__QSIG_B_LOOPBACK_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define QDEC_SETUP_FOR_AXIS_0__QSIG_B_LOOPBACK_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define QDEC_SETUP_FOR_AXIS_0__QSIG_B_LOOPBACK_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define QDEC_SETUP_FOR_AXIS_0__QSIG_B_LOOPBACK_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define QDEC_SETUP_FOR_AXIS_0__QSIG_B_LOOPBACK_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define QDEC_SETUP_FOR_AXIS_0__QSIG_B_LOOPBACK_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field qsig_a_loopback_val */ +/** + * @defgroup at_apb_qdec_regs_core_qsig_a_loopback_val_field qsig_a_loopback_val_field + * @brief macros for field qsig_a_loopback_val + * @{ + */ +#define QDEC_SETUP_FOR_AXIS_0__QSIG_A_LOOPBACK_VAL__SHIFT 2 +#define QDEC_SETUP_FOR_AXIS_0__QSIG_A_LOOPBACK_VAL__WIDTH 1 +#define QDEC_SETUP_FOR_AXIS_0__QSIG_A_LOOPBACK_VAL__MASK 0x00000004U +#define QDEC_SETUP_FOR_AXIS_0__QSIG_A_LOOPBACK_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define QDEC_SETUP_FOR_AXIS_0__QSIG_A_LOOPBACK_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define QDEC_SETUP_FOR_AXIS_0__QSIG_A_LOOPBACK_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define QDEC_SETUP_FOR_AXIS_0__QSIG_A_LOOPBACK_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define QDEC_SETUP_FOR_AXIS_0__QSIG_A_LOOPBACK_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define QDEC_SETUP_FOR_AXIS_0__QSIG_A_LOOPBACK_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define QDEC_SETUP_FOR_AXIS_0__QSIG_A_LOOPBACK_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reverse_polarity */ +/** + * @defgroup at_apb_qdec_regs_core_reverse_polarity_field reverse_polarity_field + * @brief macros for field reverse_polarity + * @{ + */ +#define QDEC_SETUP_FOR_AXIS_0__REVERSE_POLARITY__SHIFT 3 +#define QDEC_SETUP_FOR_AXIS_0__REVERSE_POLARITY__WIDTH 1 +#define QDEC_SETUP_FOR_AXIS_0__REVERSE_POLARITY__MASK 0x00000008U +#define QDEC_SETUP_FOR_AXIS_0__REVERSE_POLARITY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define QDEC_SETUP_FOR_AXIS_0__REVERSE_POLARITY__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define QDEC_SETUP_FOR_AXIS_0__REVERSE_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define QDEC_SETUP_FOR_AXIS_0__REVERSE_POLARITY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define QDEC_SETUP_FOR_AXIS_0__REVERSE_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define QDEC_SETUP_FOR_AXIS_0__REVERSE_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define QDEC_SETUP_FOR_AXIS_0__REVERSE_POLARITY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field purge_accum_post_read */ +/** + * @defgroup at_apb_qdec_regs_core_purge_accum_post_read_field purge_accum_post_read_field + * @brief macros for field purge_accum_post_read + * @{ + */ +#define QDEC_SETUP_FOR_AXIS_0__PURGE_ACCUM_POST_READ__SHIFT 4 +#define QDEC_SETUP_FOR_AXIS_0__PURGE_ACCUM_POST_READ__WIDTH 1 +#define QDEC_SETUP_FOR_AXIS_0__PURGE_ACCUM_POST_READ__MASK 0x00000010U +#define QDEC_SETUP_FOR_AXIS_0__PURGE_ACCUM_POST_READ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define QDEC_SETUP_FOR_AXIS_0__PURGE_ACCUM_POST_READ__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define QDEC_SETUP_FOR_AXIS_0__PURGE_ACCUM_POST_READ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define QDEC_SETUP_FOR_AXIS_0__PURGE_ACCUM_POST_READ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define QDEC_SETUP_FOR_AXIS_0__PURGE_ACCUM_POST_READ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define QDEC_SETUP_FOR_AXIS_0__PURGE_ACCUM_POST_READ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define QDEC_SETUP_FOR_AXIS_0__PURGE_ACCUM_POST_READ__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field purge_err_post_read */ +/** + * @defgroup at_apb_qdec_regs_core_purge_err_post_read_field purge_err_post_read_field + * @brief macros for field purge_err_post_read + * @{ + */ +#define QDEC_SETUP_FOR_AXIS_0__PURGE_ERR_POST_READ__SHIFT 5 +#define QDEC_SETUP_FOR_AXIS_0__PURGE_ERR_POST_READ__WIDTH 1 +#define QDEC_SETUP_FOR_AXIS_0__PURGE_ERR_POST_READ__MASK 0x00000020U +#define QDEC_SETUP_FOR_AXIS_0__PURGE_ERR_POST_READ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define QDEC_SETUP_FOR_AXIS_0__PURGE_ERR_POST_READ__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define QDEC_SETUP_FOR_AXIS_0__PURGE_ERR_POST_READ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define QDEC_SETUP_FOR_AXIS_0__PURGE_ERR_POST_READ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define QDEC_SETUP_FOR_AXIS_0__PURGE_ERR_POST_READ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define QDEC_SETUP_FOR_AXIS_0__PURGE_ERR_POST_READ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define QDEC_SETUP_FOR_AXIS_0__PURGE_ERR_POST_READ__RESET_VALUE 0x00000001U +/** @} */ +#define QDEC_SETUP_FOR_AXIS_0__TYPE uint32_t +#define QDEC_SETUP_FOR_AXIS_0__READ 0x0000003fU +#define QDEC_SETUP_FOR_AXIS_0__WRITE 0x0000003fU +#define QDEC_SETUP_FOR_AXIS_0__PRESERVED 0x00000000U +#define QDEC_SETUP_FOR_AXIS_0__RESET_VALUE 0x00000030U + +#endif /* __QDEC_SETUP_FOR_AXIS_0_MACRO__ */ + +/** @} end of setup_for_axis_0 */ + +/* macros for BlueprintGlobalNameSpace::QDEC_accum_purge_status_for_axis_0 */ +/** + * @defgroup at_apb_qdec_regs_core_accum_purge_status_for_axis_0 accum_purge_status_for_axis_0 + * @brief Contains register fields associated with accum_purge_status_for_axis_0. definitions. + * @{ + */ +#ifndef __QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_0_MACRO__ +#define __QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_0_MACRO__ + +/* macros for field accum_purge_sts */ +/** + * @defgroup at_apb_qdec_regs_core_accum_purge_sts_field accum_purge_sts_field + * @brief macros for field accum_purge_sts + * @{ + */ +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_0__ACCUM_PURGE_STS__SHIFT 0 +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_0__ACCUM_PURGE_STS__WIDTH 1 +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_0__ACCUM_PURGE_STS__MASK 0x00000001U +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_0__ACCUM_PURGE_STS__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_0__ACCUM_PURGE_STS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_0__ACCUM_PURGE_STS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_0__ACCUM_PURGE_STS__RESET_VALUE \ + 0x00000000U +/** @} */ +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_0__TYPE uint32_t +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_0__READ 0x00000001U +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_0__PRESERVED 0x00000000U +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_0__RESET_VALUE 0x00000000U + +#endif /* __QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_0_MACRO__ */ + +/** @} end of accum_purge_status_for_axis_0 */ + +/* macros for BlueprintGlobalNameSpace::QDEC_accumulator_value_for_axis_0 */ +/** + * @defgroup at_apb_qdec_regs_core_accumulator_value_for_axis_0 accumulator_value_for_axis_0 + * @brief Contains register fields associated with accumulator_value_for_axis_0. definitions. + * @{ + */ +#ifndef __QDEC_ACCUMULATOR_VALUE_FOR_AXIS_0_MACRO__ +#define __QDEC_ACCUMULATOR_VALUE_FOR_AXIS_0_MACRO__ + +/* macros for field accum_val */ +/** + * @defgroup at_apb_qdec_regs_core_accum_val_field accum_val_field + * @brief macros for field accum_val + * @{ + */ +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_0__ACCUM_VAL__SHIFT 0 +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_0__ACCUM_VAL__WIDTH 32 +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_0__ACCUM_VAL__MASK 0xffffffffU +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_0__ACCUM_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_0__ACCUM_VAL__RESET_VALUE 0x00000000U +/** @} */ +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_0__TYPE uint32_t +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_0__READ 0xffffffffU +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_0__PRESERVED 0x00000000U +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_0__RESET_VALUE 0x00000000U + +#endif /* __QDEC_ACCUMULATOR_VALUE_FOR_AXIS_0_MACRO__ */ + +/** @} end of accumulator_value_for_axis_0 */ + +/* macros for BlueprintGlobalNameSpace::QDEC_err_purge_status_for_axis_0 */ +/** + * @defgroup at_apb_qdec_regs_core_err_purge_status_for_axis_0 err_purge_status_for_axis_0 + * @brief Contains register fields associated with err_purge_status_for_axis_0. definitions. + * @{ + */ +#ifndef __QDEC_ERR_PURGE_STATUS_FOR_AXIS_0_MACRO__ +#define __QDEC_ERR_PURGE_STATUS_FOR_AXIS_0_MACRO__ + +/* macros for field err_purge_sts */ +/** + * @defgroup at_apb_qdec_regs_core_err_purge_sts_field err_purge_sts_field + * @brief macros for field err_purge_sts + * @{ + */ +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_0__ERR_PURGE_STS__SHIFT 0 +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_0__ERR_PURGE_STS__WIDTH 1 +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_0__ERR_PURGE_STS__MASK 0x00000001U +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_0__ERR_PURGE_STS__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_0__ERR_PURGE_STS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_0__ERR_PURGE_STS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_0__ERR_PURGE_STS__RESET_VALUE \ + 0x00000000U +/** @} */ +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_0__TYPE uint32_t +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_0__READ 0x00000001U +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_0__PRESERVED 0x00000000U +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_0__RESET_VALUE 0x00000000U + +#endif /* __QDEC_ERR_PURGE_STATUS_FOR_AXIS_0_MACRO__ */ + +/** @} end of err_purge_status_for_axis_0 */ + +/* macros for BlueprintGlobalNameSpace::QDEC_error_count_for_axis_0 */ +/** + * @defgroup at_apb_qdec_regs_core_error_count_for_axis_0 error_count_for_axis_0 + * @brief Contains register fields associated with error_count_for_axis_0. definitions. + * @{ + */ +#ifndef __QDEC_ERROR_COUNT_FOR_AXIS_0_MACRO__ +#define __QDEC_ERROR_COUNT_FOR_AXIS_0_MACRO__ + +/* macros for field err_cnt */ +/** + * @defgroup at_apb_qdec_regs_core_err_cnt_field err_cnt_field + * @brief macros for field err_cnt + * @{ + */ +#define QDEC_ERROR_COUNT_FOR_AXIS_0__ERR_CNT__SHIFT 0 +#define QDEC_ERROR_COUNT_FOR_AXIS_0__ERR_CNT__WIDTH 32 +#define QDEC_ERROR_COUNT_FOR_AXIS_0__ERR_CNT__MASK 0xffffffffU +#define QDEC_ERROR_COUNT_FOR_AXIS_0__ERR_CNT__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define QDEC_ERROR_COUNT_FOR_AXIS_0__ERR_CNT__RESET_VALUE 0x00000000U +/** @} */ +#define QDEC_ERROR_COUNT_FOR_AXIS_0__TYPE uint32_t +#define QDEC_ERROR_COUNT_FOR_AXIS_0__READ 0xffffffffU +#define QDEC_ERROR_COUNT_FOR_AXIS_0__PRESERVED 0x00000000U +#define QDEC_ERROR_COUNT_FOR_AXIS_0__RESET_VALUE 0x00000000U + +#endif /* __QDEC_ERROR_COUNT_FOR_AXIS_0_MACRO__ */ + +/** @} end of error_count_for_axis_0 */ + +/* macros for BlueprintGlobalNameSpace::QDEC_setup_for_axis_1 */ +/** + * @defgroup at_apb_qdec_regs_core_setup_for_axis_1 setup_for_axis_1 + * @brief Contains register fields associated with setup_for_axis_1. definitions. + * @{ + */ +#ifndef __QDEC_SETUP_FOR_AXIS_1_MACRO__ +#define __QDEC_SETUP_FOR_AXIS_1_MACRO__ + +/* macros for field enable_loopback */ +/** + * @defgroup at_apb_qdec_regs_core_enable_loopback_field enable_loopback_field + * @brief macros for field enable_loopback + * @{ + */ +#define QDEC_SETUP_FOR_AXIS_1__ENABLE_LOOPBACK__SHIFT 0 +#define QDEC_SETUP_FOR_AXIS_1__ENABLE_LOOPBACK__WIDTH 1 +#define QDEC_SETUP_FOR_AXIS_1__ENABLE_LOOPBACK__MASK 0x00000001U +#define QDEC_SETUP_FOR_AXIS_1__ENABLE_LOOPBACK__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define QDEC_SETUP_FOR_AXIS_1__ENABLE_LOOPBACK__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define QDEC_SETUP_FOR_AXIS_1__ENABLE_LOOPBACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define QDEC_SETUP_FOR_AXIS_1__ENABLE_LOOPBACK__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define QDEC_SETUP_FOR_AXIS_1__ENABLE_LOOPBACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define QDEC_SETUP_FOR_AXIS_1__ENABLE_LOOPBACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define QDEC_SETUP_FOR_AXIS_1__ENABLE_LOOPBACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field qsig_b_loopback_val */ +/** + * @defgroup at_apb_qdec_regs_core_qsig_b_loopback_val_field qsig_b_loopback_val_field + * @brief macros for field qsig_b_loopback_val + * @{ + */ +#define QDEC_SETUP_FOR_AXIS_1__QSIG_B_LOOPBACK_VAL__SHIFT 1 +#define QDEC_SETUP_FOR_AXIS_1__QSIG_B_LOOPBACK_VAL__WIDTH 1 +#define QDEC_SETUP_FOR_AXIS_1__QSIG_B_LOOPBACK_VAL__MASK 0x00000002U +#define QDEC_SETUP_FOR_AXIS_1__QSIG_B_LOOPBACK_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define QDEC_SETUP_FOR_AXIS_1__QSIG_B_LOOPBACK_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define QDEC_SETUP_FOR_AXIS_1__QSIG_B_LOOPBACK_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define QDEC_SETUP_FOR_AXIS_1__QSIG_B_LOOPBACK_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define QDEC_SETUP_FOR_AXIS_1__QSIG_B_LOOPBACK_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define QDEC_SETUP_FOR_AXIS_1__QSIG_B_LOOPBACK_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define QDEC_SETUP_FOR_AXIS_1__QSIG_B_LOOPBACK_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field qsig_a_loopback_val */ +/** + * @defgroup at_apb_qdec_regs_core_qsig_a_loopback_val_field qsig_a_loopback_val_field + * @brief macros for field qsig_a_loopback_val + * @{ + */ +#define QDEC_SETUP_FOR_AXIS_1__QSIG_A_LOOPBACK_VAL__SHIFT 2 +#define QDEC_SETUP_FOR_AXIS_1__QSIG_A_LOOPBACK_VAL__WIDTH 1 +#define QDEC_SETUP_FOR_AXIS_1__QSIG_A_LOOPBACK_VAL__MASK 0x00000004U +#define QDEC_SETUP_FOR_AXIS_1__QSIG_A_LOOPBACK_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define QDEC_SETUP_FOR_AXIS_1__QSIG_A_LOOPBACK_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define QDEC_SETUP_FOR_AXIS_1__QSIG_A_LOOPBACK_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define QDEC_SETUP_FOR_AXIS_1__QSIG_A_LOOPBACK_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define QDEC_SETUP_FOR_AXIS_1__QSIG_A_LOOPBACK_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define QDEC_SETUP_FOR_AXIS_1__QSIG_A_LOOPBACK_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define QDEC_SETUP_FOR_AXIS_1__QSIG_A_LOOPBACK_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reverse_polarity */ +/** + * @defgroup at_apb_qdec_regs_core_reverse_polarity_field reverse_polarity_field + * @brief macros for field reverse_polarity + * @{ + */ +#define QDEC_SETUP_FOR_AXIS_1__REVERSE_POLARITY__SHIFT 3 +#define QDEC_SETUP_FOR_AXIS_1__REVERSE_POLARITY__WIDTH 1 +#define QDEC_SETUP_FOR_AXIS_1__REVERSE_POLARITY__MASK 0x00000008U +#define QDEC_SETUP_FOR_AXIS_1__REVERSE_POLARITY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define QDEC_SETUP_FOR_AXIS_1__REVERSE_POLARITY__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define QDEC_SETUP_FOR_AXIS_1__REVERSE_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define QDEC_SETUP_FOR_AXIS_1__REVERSE_POLARITY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define QDEC_SETUP_FOR_AXIS_1__REVERSE_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define QDEC_SETUP_FOR_AXIS_1__REVERSE_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define QDEC_SETUP_FOR_AXIS_1__REVERSE_POLARITY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field purge_accum_post_read */ +/** + * @defgroup at_apb_qdec_regs_core_purge_accum_post_read_field purge_accum_post_read_field + * @brief macros for field purge_accum_post_read + * @{ + */ +#define QDEC_SETUP_FOR_AXIS_1__PURGE_ACCUM_POST_READ__SHIFT 4 +#define QDEC_SETUP_FOR_AXIS_1__PURGE_ACCUM_POST_READ__WIDTH 1 +#define QDEC_SETUP_FOR_AXIS_1__PURGE_ACCUM_POST_READ__MASK 0x00000010U +#define QDEC_SETUP_FOR_AXIS_1__PURGE_ACCUM_POST_READ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define QDEC_SETUP_FOR_AXIS_1__PURGE_ACCUM_POST_READ__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define QDEC_SETUP_FOR_AXIS_1__PURGE_ACCUM_POST_READ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define QDEC_SETUP_FOR_AXIS_1__PURGE_ACCUM_POST_READ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define QDEC_SETUP_FOR_AXIS_1__PURGE_ACCUM_POST_READ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define QDEC_SETUP_FOR_AXIS_1__PURGE_ACCUM_POST_READ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define QDEC_SETUP_FOR_AXIS_1__PURGE_ACCUM_POST_READ__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field purge_err_post_read */ +/** + * @defgroup at_apb_qdec_regs_core_purge_err_post_read_field purge_err_post_read_field + * @brief macros for field purge_err_post_read + * @{ + */ +#define QDEC_SETUP_FOR_AXIS_1__PURGE_ERR_POST_READ__SHIFT 5 +#define QDEC_SETUP_FOR_AXIS_1__PURGE_ERR_POST_READ__WIDTH 1 +#define QDEC_SETUP_FOR_AXIS_1__PURGE_ERR_POST_READ__MASK 0x00000020U +#define QDEC_SETUP_FOR_AXIS_1__PURGE_ERR_POST_READ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define QDEC_SETUP_FOR_AXIS_1__PURGE_ERR_POST_READ__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define QDEC_SETUP_FOR_AXIS_1__PURGE_ERR_POST_READ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define QDEC_SETUP_FOR_AXIS_1__PURGE_ERR_POST_READ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define QDEC_SETUP_FOR_AXIS_1__PURGE_ERR_POST_READ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define QDEC_SETUP_FOR_AXIS_1__PURGE_ERR_POST_READ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define QDEC_SETUP_FOR_AXIS_1__PURGE_ERR_POST_READ__RESET_VALUE 0x00000001U +/** @} */ +#define QDEC_SETUP_FOR_AXIS_1__TYPE uint32_t +#define QDEC_SETUP_FOR_AXIS_1__READ 0x0000003fU +#define QDEC_SETUP_FOR_AXIS_1__WRITE 0x0000003fU +#define QDEC_SETUP_FOR_AXIS_1__PRESERVED 0x00000000U +#define QDEC_SETUP_FOR_AXIS_1__RESET_VALUE 0x00000030U + +#endif /* __QDEC_SETUP_FOR_AXIS_1_MACRO__ */ + +/** @} end of setup_for_axis_1 */ + +/* macros for BlueprintGlobalNameSpace::QDEC_accum_purge_status_for_axis_1 */ +/** + * @defgroup at_apb_qdec_regs_core_accum_purge_status_for_axis_1 accum_purge_status_for_axis_1 + * @brief Contains register fields associated with accum_purge_status_for_axis_1. definitions. + * @{ + */ +#ifndef __QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_1_MACRO__ +#define __QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_1_MACRO__ + +/* macros for field accum_purge_sts */ +/** + * @defgroup at_apb_qdec_regs_core_accum_purge_sts_field accum_purge_sts_field + * @brief macros for field accum_purge_sts + * @{ + */ +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_1__ACCUM_PURGE_STS__SHIFT 0 +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_1__ACCUM_PURGE_STS__WIDTH 1 +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_1__ACCUM_PURGE_STS__MASK 0x00000001U +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_1__ACCUM_PURGE_STS__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_1__ACCUM_PURGE_STS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_1__ACCUM_PURGE_STS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_1__ACCUM_PURGE_STS__RESET_VALUE \ + 0x00000000U +/** @} */ +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_1__TYPE uint32_t +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_1__READ 0x00000001U +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_1__PRESERVED 0x00000000U +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_1__RESET_VALUE 0x00000000U + +#endif /* __QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_1_MACRO__ */ + +/** @} end of accum_purge_status_for_axis_1 */ + +/* macros for BlueprintGlobalNameSpace::QDEC_accumulator_value_for_axis_1 */ +/** + * @defgroup at_apb_qdec_regs_core_accumulator_value_for_axis_1 accumulator_value_for_axis_1 + * @brief Contains register fields associated with accumulator_value_for_axis_1. definitions. + * @{ + */ +#ifndef __QDEC_ACCUMULATOR_VALUE_FOR_AXIS_1_MACRO__ +#define __QDEC_ACCUMULATOR_VALUE_FOR_AXIS_1_MACRO__ + +/* macros for field accum_val */ +/** + * @defgroup at_apb_qdec_regs_core_accum_val_field accum_val_field + * @brief macros for field accum_val + * @{ + */ +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_1__ACCUM_VAL__SHIFT 0 +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_1__ACCUM_VAL__WIDTH 32 +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_1__ACCUM_VAL__MASK 0xffffffffU +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_1__ACCUM_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_1__ACCUM_VAL__RESET_VALUE 0x00000000U +/** @} */ +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_1__TYPE uint32_t +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_1__READ 0xffffffffU +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_1__PRESERVED 0x00000000U +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_1__RESET_VALUE 0x00000000U + +#endif /* __QDEC_ACCUMULATOR_VALUE_FOR_AXIS_1_MACRO__ */ + +/** @} end of accumulator_value_for_axis_1 */ + +/* macros for BlueprintGlobalNameSpace::QDEC_err_purge_status_for_axis_1 */ +/** + * @defgroup at_apb_qdec_regs_core_err_purge_status_for_axis_1 err_purge_status_for_axis_1 + * @brief Contains register fields associated with err_purge_status_for_axis_1. definitions. + * @{ + */ +#ifndef __QDEC_ERR_PURGE_STATUS_FOR_AXIS_1_MACRO__ +#define __QDEC_ERR_PURGE_STATUS_FOR_AXIS_1_MACRO__ + +/* macros for field err_purge_sts */ +/** + * @defgroup at_apb_qdec_regs_core_err_purge_sts_field err_purge_sts_field + * @brief macros for field err_purge_sts + * @{ + */ +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_1__ERR_PURGE_STS__SHIFT 0 +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_1__ERR_PURGE_STS__WIDTH 1 +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_1__ERR_PURGE_STS__MASK 0x00000001U +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_1__ERR_PURGE_STS__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_1__ERR_PURGE_STS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_1__ERR_PURGE_STS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_1__ERR_PURGE_STS__RESET_VALUE \ + 0x00000000U +/** @} */ +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_1__TYPE uint32_t +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_1__READ 0x00000001U +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_1__PRESERVED 0x00000000U +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_1__RESET_VALUE 0x00000000U + +#endif /* __QDEC_ERR_PURGE_STATUS_FOR_AXIS_1_MACRO__ */ + +/** @} end of err_purge_status_for_axis_1 */ + +/* macros for BlueprintGlobalNameSpace::QDEC_error_count_for_axis_1 */ +/** + * @defgroup at_apb_qdec_regs_core_error_count_for_axis_1 error_count_for_axis_1 + * @brief Contains register fields associated with error_count_for_axis_1. definitions. + * @{ + */ +#ifndef __QDEC_ERROR_COUNT_FOR_AXIS_1_MACRO__ +#define __QDEC_ERROR_COUNT_FOR_AXIS_1_MACRO__ + +/* macros for field err_cnt */ +/** + * @defgroup at_apb_qdec_regs_core_err_cnt_field err_cnt_field + * @brief macros for field err_cnt + * @{ + */ +#define QDEC_ERROR_COUNT_FOR_AXIS_1__ERR_CNT__SHIFT 0 +#define QDEC_ERROR_COUNT_FOR_AXIS_1__ERR_CNT__WIDTH 32 +#define QDEC_ERROR_COUNT_FOR_AXIS_1__ERR_CNT__MASK 0xffffffffU +#define QDEC_ERROR_COUNT_FOR_AXIS_1__ERR_CNT__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define QDEC_ERROR_COUNT_FOR_AXIS_1__ERR_CNT__RESET_VALUE 0x00000000U +/** @} */ +#define QDEC_ERROR_COUNT_FOR_AXIS_1__TYPE uint32_t +#define QDEC_ERROR_COUNT_FOR_AXIS_1__READ 0xffffffffU +#define QDEC_ERROR_COUNT_FOR_AXIS_1__PRESERVED 0x00000000U +#define QDEC_ERROR_COUNT_FOR_AXIS_1__RESET_VALUE 0x00000000U + +#endif /* __QDEC_ERROR_COUNT_FOR_AXIS_1_MACRO__ */ + +/** @} end of error_count_for_axis_1 */ + +/* macros for BlueprintGlobalNameSpace::QDEC_setup_for_axis_2 */ +/** + * @defgroup at_apb_qdec_regs_core_setup_for_axis_2 setup_for_axis_2 + * @brief Contains register fields associated with setup_for_axis_2. definitions. + * @{ + */ +#ifndef __QDEC_SETUP_FOR_AXIS_2_MACRO__ +#define __QDEC_SETUP_FOR_AXIS_2_MACRO__ + +/* macros for field enable_loopback */ +/** + * @defgroup at_apb_qdec_regs_core_enable_loopback_field enable_loopback_field + * @brief macros for field enable_loopback + * @{ + */ +#define QDEC_SETUP_FOR_AXIS_2__ENABLE_LOOPBACK__SHIFT 0 +#define QDEC_SETUP_FOR_AXIS_2__ENABLE_LOOPBACK__WIDTH 1 +#define QDEC_SETUP_FOR_AXIS_2__ENABLE_LOOPBACK__MASK 0x00000001U +#define QDEC_SETUP_FOR_AXIS_2__ENABLE_LOOPBACK__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define QDEC_SETUP_FOR_AXIS_2__ENABLE_LOOPBACK__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define QDEC_SETUP_FOR_AXIS_2__ENABLE_LOOPBACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define QDEC_SETUP_FOR_AXIS_2__ENABLE_LOOPBACK__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define QDEC_SETUP_FOR_AXIS_2__ENABLE_LOOPBACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define QDEC_SETUP_FOR_AXIS_2__ENABLE_LOOPBACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define QDEC_SETUP_FOR_AXIS_2__ENABLE_LOOPBACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field qsig_b_loopback_val */ +/** + * @defgroup at_apb_qdec_regs_core_qsig_b_loopback_val_field qsig_b_loopback_val_field + * @brief macros for field qsig_b_loopback_val + * @{ + */ +#define QDEC_SETUP_FOR_AXIS_2__QSIG_B_LOOPBACK_VAL__SHIFT 1 +#define QDEC_SETUP_FOR_AXIS_2__QSIG_B_LOOPBACK_VAL__WIDTH 1 +#define QDEC_SETUP_FOR_AXIS_2__QSIG_B_LOOPBACK_VAL__MASK 0x00000002U +#define QDEC_SETUP_FOR_AXIS_2__QSIG_B_LOOPBACK_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define QDEC_SETUP_FOR_AXIS_2__QSIG_B_LOOPBACK_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define QDEC_SETUP_FOR_AXIS_2__QSIG_B_LOOPBACK_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define QDEC_SETUP_FOR_AXIS_2__QSIG_B_LOOPBACK_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define QDEC_SETUP_FOR_AXIS_2__QSIG_B_LOOPBACK_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define QDEC_SETUP_FOR_AXIS_2__QSIG_B_LOOPBACK_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define QDEC_SETUP_FOR_AXIS_2__QSIG_B_LOOPBACK_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field qsig_a_loopback_val */ +/** + * @defgroup at_apb_qdec_regs_core_qsig_a_loopback_val_field qsig_a_loopback_val_field + * @brief macros for field qsig_a_loopback_val + * @{ + */ +#define QDEC_SETUP_FOR_AXIS_2__QSIG_A_LOOPBACK_VAL__SHIFT 2 +#define QDEC_SETUP_FOR_AXIS_2__QSIG_A_LOOPBACK_VAL__WIDTH 1 +#define QDEC_SETUP_FOR_AXIS_2__QSIG_A_LOOPBACK_VAL__MASK 0x00000004U +#define QDEC_SETUP_FOR_AXIS_2__QSIG_A_LOOPBACK_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define QDEC_SETUP_FOR_AXIS_2__QSIG_A_LOOPBACK_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define QDEC_SETUP_FOR_AXIS_2__QSIG_A_LOOPBACK_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define QDEC_SETUP_FOR_AXIS_2__QSIG_A_LOOPBACK_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define QDEC_SETUP_FOR_AXIS_2__QSIG_A_LOOPBACK_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define QDEC_SETUP_FOR_AXIS_2__QSIG_A_LOOPBACK_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define QDEC_SETUP_FOR_AXIS_2__QSIG_A_LOOPBACK_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reverse_polarity */ +/** + * @defgroup at_apb_qdec_regs_core_reverse_polarity_field reverse_polarity_field + * @brief macros for field reverse_polarity + * @{ + */ +#define QDEC_SETUP_FOR_AXIS_2__REVERSE_POLARITY__SHIFT 3 +#define QDEC_SETUP_FOR_AXIS_2__REVERSE_POLARITY__WIDTH 1 +#define QDEC_SETUP_FOR_AXIS_2__REVERSE_POLARITY__MASK 0x00000008U +#define QDEC_SETUP_FOR_AXIS_2__REVERSE_POLARITY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define QDEC_SETUP_FOR_AXIS_2__REVERSE_POLARITY__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define QDEC_SETUP_FOR_AXIS_2__REVERSE_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define QDEC_SETUP_FOR_AXIS_2__REVERSE_POLARITY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define QDEC_SETUP_FOR_AXIS_2__REVERSE_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define QDEC_SETUP_FOR_AXIS_2__REVERSE_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define QDEC_SETUP_FOR_AXIS_2__REVERSE_POLARITY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field purge_accum_post_read */ +/** + * @defgroup at_apb_qdec_regs_core_purge_accum_post_read_field purge_accum_post_read_field + * @brief macros for field purge_accum_post_read + * @{ + */ +#define QDEC_SETUP_FOR_AXIS_2__PURGE_ACCUM_POST_READ__SHIFT 4 +#define QDEC_SETUP_FOR_AXIS_2__PURGE_ACCUM_POST_READ__WIDTH 1 +#define QDEC_SETUP_FOR_AXIS_2__PURGE_ACCUM_POST_READ__MASK 0x00000010U +#define QDEC_SETUP_FOR_AXIS_2__PURGE_ACCUM_POST_READ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define QDEC_SETUP_FOR_AXIS_2__PURGE_ACCUM_POST_READ__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define QDEC_SETUP_FOR_AXIS_2__PURGE_ACCUM_POST_READ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define QDEC_SETUP_FOR_AXIS_2__PURGE_ACCUM_POST_READ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define QDEC_SETUP_FOR_AXIS_2__PURGE_ACCUM_POST_READ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define QDEC_SETUP_FOR_AXIS_2__PURGE_ACCUM_POST_READ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define QDEC_SETUP_FOR_AXIS_2__PURGE_ACCUM_POST_READ__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field purge_err_post_read */ +/** + * @defgroup at_apb_qdec_regs_core_purge_err_post_read_field purge_err_post_read_field + * @brief macros for field purge_err_post_read + * @{ + */ +#define QDEC_SETUP_FOR_AXIS_2__PURGE_ERR_POST_READ__SHIFT 5 +#define QDEC_SETUP_FOR_AXIS_2__PURGE_ERR_POST_READ__WIDTH 1 +#define QDEC_SETUP_FOR_AXIS_2__PURGE_ERR_POST_READ__MASK 0x00000020U +#define QDEC_SETUP_FOR_AXIS_2__PURGE_ERR_POST_READ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define QDEC_SETUP_FOR_AXIS_2__PURGE_ERR_POST_READ__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define QDEC_SETUP_FOR_AXIS_2__PURGE_ERR_POST_READ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define QDEC_SETUP_FOR_AXIS_2__PURGE_ERR_POST_READ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define QDEC_SETUP_FOR_AXIS_2__PURGE_ERR_POST_READ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define QDEC_SETUP_FOR_AXIS_2__PURGE_ERR_POST_READ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define QDEC_SETUP_FOR_AXIS_2__PURGE_ERR_POST_READ__RESET_VALUE 0x00000001U +/** @} */ +#define QDEC_SETUP_FOR_AXIS_2__TYPE uint32_t +#define QDEC_SETUP_FOR_AXIS_2__READ 0x0000003fU +#define QDEC_SETUP_FOR_AXIS_2__WRITE 0x0000003fU +#define QDEC_SETUP_FOR_AXIS_2__PRESERVED 0x00000000U +#define QDEC_SETUP_FOR_AXIS_2__RESET_VALUE 0x00000030U + +#endif /* __QDEC_SETUP_FOR_AXIS_2_MACRO__ */ + +/** @} end of setup_for_axis_2 */ + +/* macros for BlueprintGlobalNameSpace::QDEC_accum_purge_status_for_axis_2 */ +/** + * @defgroup at_apb_qdec_regs_core_accum_purge_status_for_axis_2 accum_purge_status_for_axis_2 + * @brief Contains register fields associated with accum_purge_status_for_axis_2. definitions. + * @{ + */ +#ifndef __QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_2_MACRO__ +#define __QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_2_MACRO__ + +/* macros for field accum_purge_sts */ +/** + * @defgroup at_apb_qdec_regs_core_accum_purge_sts_field accum_purge_sts_field + * @brief macros for field accum_purge_sts + * @{ + */ +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_2__ACCUM_PURGE_STS__SHIFT 0 +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_2__ACCUM_PURGE_STS__WIDTH 1 +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_2__ACCUM_PURGE_STS__MASK 0x00000001U +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_2__ACCUM_PURGE_STS__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_2__ACCUM_PURGE_STS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_2__ACCUM_PURGE_STS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_2__ACCUM_PURGE_STS__RESET_VALUE \ + 0x00000000U +/** @} */ +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_2__TYPE uint32_t +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_2__READ 0x00000001U +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_2__PRESERVED 0x00000000U +#define QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_2__RESET_VALUE 0x00000000U + +#endif /* __QDEC_ACCUM_PURGE_STATUS_FOR_AXIS_2_MACRO__ */ + +/** @} end of accum_purge_status_for_axis_2 */ + +/* macros for BlueprintGlobalNameSpace::QDEC_accumulator_value_for_axis_2 */ +/** + * @defgroup at_apb_qdec_regs_core_accumulator_value_for_axis_2 accumulator_value_for_axis_2 + * @brief Contains register fields associated with accumulator_value_for_axis_2. definitions. + * @{ + */ +#ifndef __QDEC_ACCUMULATOR_VALUE_FOR_AXIS_2_MACRO__ +#define __QDEC_ACCUMULATOR_VALUE_FOR_AXIS_2_MACRO__ + +/* macros for field accum_val */ +/** + * @defgroup at_apb_qdec_regs_core_accum_val_field accum_val_field + * @brief macros for field accum_val + * @{ + */ +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_2__ACCUM_VAL__SHIFT 0 +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_2__ACCUM_VAL__WIDTH 32 +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_2__ACCUM_VAL__MASK 0xffffffffU +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_2__ACCUM_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_2__ACCUM_VAL__RESET_VALUE 0x00000000U +/** @} */ +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_2__TYPE uint32_t +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_2__READ 0xffffffffU +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_2__PRESERVED 0x00000000U +#define QDEC_ACCUMULATOR_VALUE_FOR_AXIS_2__RESET_VALUE 0x00000000U + +#endif /* __QDEC_ACCUMULATOR_VALUE_FOR_AXIS_2_MACRO__ */ + +/** @} end of accumulator_value_for_axis_2 */ + +/* macros for BlueprintGlobalNameSpace::QDEC_err_purge_status_for_axis_2 */ +/** + * @defgroup at_apb_qdec_regs_core_err_purge_status_for_axis_2 err_purge_status_for_axis_2 + * @brief Contains register fields associated with err_purge_status_for_axis_2. definitions. + * @{ + */ +#ifndef __QDEC_ERR_PURGE_STATUS_FOR_AXIS_2_MACRO__ +#define __QDEC_ERR_PURGE_STATUS_FOR_AXIS_2_MACRO__ + +/* macros for field err_purge_sts */ +/** + * @defgroup at_apb_qdec_regs_core_err_purge_sts_field err_purge_sts_field + * @brief macros for field err_purge_sts + * @{ + */ +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_2__ERR_PURGE_STS__SHIFT 0 +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_2__ERR_PURGE_STS__WIDTH 1 +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_2__ERR_PURGE_STS__MASK 0x00000001U +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_2__ERR_PURGE_STS__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_2__ERR_PURGE_STS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_2__ERR_PURGE_STS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_2__ERR_PURGE_STS__RESET_VALUE \ + 0x00000000U +/** @} */ +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_2__TYPE uint32_t +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_2__READ 0x00000001U +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_2__PRESERVED 0x00000000U +#define QDEC_ERR_PURGE_STATUS_FOR_AXIS_2__RESET_VALUE 0x00000000U + +#endif /* __QDEC_ERR_PURGE_STATUS_FOR_AXIS_2_MACRO__ */ + +/** @} end of err_purge_status_for_axis_2 */ + +/* macros for BlueprintGlobalNameSpace::QDEC_error_count_for_axis_2 */ +/** + * @defgroup at_apb_qdec_regs_core_error_count_for_axis_2 error_count_for_axis_2 + * @brief Contains register fields associated with error_count_for_axis_2. definitions. + * @{ + */ +#ifndef __QDEC_ERROR_COUNT_FOR_AXIS_2_MACRO__ +#define __QDEC_ERROR_COUNT_FOR_AXIS_2_MACRO__ + +/* macros for field err_cnt */ +/** + * @defgroup at_apb_qdec_regs_core_err_cnt_field err_cnt_field + * @brief macros for field err_cnt + * @{ + */ +#define QDEC_ERROR_COUNT_FOR_AXIS_2__ERR_CNT__SHIFT 0 +#define QDEC_ERROR_COUNT_FOR_AXIS_2__ERR_CNT__WIDTH 32 +#define QDEC_ERROR_COUNT_FOR_AXIS_2__ERR_CNT__MASK 0xffffffffU +#define QDEC_ERROR_COUNT_FOR_AXIS_2__ERR_CNT__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define QDEC_ERROR_COUNT_FOR_AXIS_2__ERR_CNT__RESET_VALUE 0x00000000U +/** @} */ +#define QDEC_ERROR_COUNT_FOR_AXIS_2__TYPE uint32_t +#define QDEC_ERROR_COUNT_FOR_AXIS_2__READ 0xffffffffU +#define QDEC_ERROR_COUNT_FOR_AXIS_2__PRESERVED 0x00000000U +#define QDEC_ERROR_COUNT_FOR_AXIS_2__RESET_VALUE 0x00000000U + +#endif /* __QDEC_ERROR_COUNT_FOR_AXIS_2_MACRO__ */ + +/** @} end of error_count_for_axis_2 */ + +/* macros for BlueprintGlobalNameSpace::QDEC_core_id */ +/** + * @defgroup at_apb_qdec_regs_core_core_id core_id + * @brief Contains register fields associated with core_id. definitions. + * @{ + */ +#ifndef __QDEC_CORE_ID_MACRO__ +#define __QDEC_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_qdec_regs_core_id_field id_field + * @brief macros for field id + * @details QDEC in ASCII + * @{ + */ +#define QDEC_CORE_ID__ID__SHIFT 0 +#define QDEC_CORE_ID__ID__WIDTH 32 +#define QDEC_CORE_ID__ID__MASK 0xffffffffU +#define QDEC_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define QDEC_CORE_ID__ID__RESET_VALUE 0x51444543U +/** @} */ +#define QDEC_CORE_ID__TYPE uint32_t +#define QDEC_CORE_ID__READ 0xffffffffU +#define QDEC_CORE_ID__PRESERVED 0x00000000U +#define QDEC_CORE_ID__RESET_VALUE 0x51444543U + +#endif /* __QDEC_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of AT_APB_QDEC_REGS_CORE */ +#endif /* __REG_AT_APB_QDEC_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_apb_qspi_regs_core_macro.h b/ATM33xx-5/include/reg/at_apb_qspi_regs_core_macro.h new file mode 100644 index 0000000..4cfb138 --- /dev/null +++ b/ATM33xx-5/include/reg/at_apb_qspi_regs_core_macro.h @@ -0,0 +1,1844 @@ +/* */ +/* File: at_apb_qspi_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_apb_qspi_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_APB_QSPI_REGS_CORE_H__ +#define __REG_AT_APB_QSPI_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_APB_QSPI_REGS_CORE at_apb_qspi_regs_core + * @ingroup AT_REG + * @brief at_apb_qspi_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::QSPI_transaction_setup */ +/** + * @defgroup at_apb_qspi_regs_core_transaction_setup transaction_setup + * @brief Contains register fields associated with transaction_setup. definitions. + * @{ + */ +#ifndef __QSPI_TRANSACTION_SETUP_MACRO__ +#define __QSPI_TRANSACTION_SETUP_MACRO__ + +/* macros for field sample_din */ +/** + * @defgroup at_apb_qspi_regs_core_sample_din_field sample_din_field + * @brief macros for field sample_din + * @{ + */ +#define QSPI_TRANSACTION_SETUP__SAMPLE_DIN__SHIFT 0 +#define QSPI_TRANSACTION_SETUP__SAMPLE_DIN__WIDTH 8 +#define QSPI_TRANSACTION_SETUP__SAMPLE_DIN__MASK 0x000000ffU +#define QSPI_TRANSACTION_SETUP__SAMPLE_DIN__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define QSPI_TRANSACTION_SETUP__SAMPLE_DIN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define QSPI_TRANSACTION_SETUP__SAMPLE_DIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define QSPI_TRANSACTION_SETUP__SAMPLE_DIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define QSPI_TRANSACTION_SETUP__SAMPLE_DIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dout_0_ctrl */ +/** + * @defgroup at_apb_qspi_regs_core_dout_0_ctrl_field dout_0_ctrl_field + * @brief macros for field dout_0_ctrl + * @details {oe val, drive val} + * @{ + */ +#define QSPI_TRANSACTION_SETUP__DOUT_0_CTRL__SHIFT 8 +#define QSPI_TRANSACTION_SETUP__DOUT_0_CTRL__WIDTH 2 +#define QSPI_TRANSACTION_SETUP__DOUT_0_CTRL__MASK 0x00000300U +#define QSPI_TRANSACTION_SETUP__DOUT_0_CTRL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000300U) >> 8) +#define QSPI_TRANSACTION_SETUP__DOUT_0_CTRL__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000300U) +#define QSPI_TRANSACTION_SETUP__DOUT_0_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((uint32_t)(src) <<\ + 8) & 0x00000300U) +#define QSPI_TRANSACTION_SETUP__DOUT_0_CTRL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000300U))) +#define QSPI_TRANSACTION_SETUP__DOUT_0_CTRL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dout_1_ctrl */ +/** + * @defgroup at_apb_qspi_regs_core_dout_1_ctrl_field dout_1_ctrl_field + * @brief macros for field dout_1_ctrl + * @details {oe val, drive val} + * @{ + */ +#define QSPI_TRANSACTION_SETUP__DOUT_1_CTRL__SHIFT 12 +#define QSPI_TRANSACTION_SETUP__DOUT_1_CTRL__WIDTH 2 +#define QSPI_TRANSACTION_SETUP__DOUT_1_CTRL__MASK 0x00003000U +#define QSPI_TRANSACTION_SETUP__DOUT_1_CTRL__READ(src) \ + (((uint32_t)(src)\ + & 0x00003000U) >> 12) +#define QSPI_TRANSACTION_SETUP__DOUT_1_CTRL__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00003000U) +#define QSPI_TRANSACTION_SETUP__DOUT_1_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((uint32_t)(src) <<\ + 12) & 0x00003000U) +#define QSPI_TRANSACTION_SETUP__DOUT_1_CTRL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00003000U))) +#define QSPI_TRANSACTION_SETUP__DOUT_1_CTRL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dout_2_ctrl */ +/** + * @defgroup at_apb_qspi_regs_core_dout_2_ctrl_field dout_2_ctrl_field + * @brief macros for field dout_2_ctrl + * @details {oe val, drive val} + * @{ + */ +#define QSPI_TRANSACTION_SETUP__DOUT_2_CTRL__SHIFT 16 +#define QSPI_TRANSACTION_SETUP__DOUT_2_CTRL__WIDTH 2 +#define QSPI_TRANSACTION_SETUP__DOUT_2_CTRL__MASK 0x00030000U +#define QSPI_TRANSACTION_SETUP__DOUT_2_CTRL__READ(src) \ + (((uint32_t)(src)\ + & 0x00030000U) >> 16) +#define QSPI_TRANSACTION_SETUP__DOUT_2_CTRL__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00030000U) +#define QSPI_TRANSACTION_SETUP__DOUT_2_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00030000U) | (((uint32_t)(src) <<\ + 16) & 0x00030000U) +#define QSPI_TRANSACTION_SETUP__DOUT_2_CTRL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00030000U))) +#define QSPI_TRANSACTION_SETUP__DOUT_2_CTRL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dout_3_ctrl */ +/** + * @defgroup at_apb_qspi_regs_core_dout_3_ctrl_field dout_3_ctrl_field + * @brief macros for field dout_3_ctrl + * @details {oe val, drive val} + * @{ + */ +#define QSPI_TRANSACTION_SETUP__DOUT_3_CTRL__SHIFT 20 +#define QSPI_TRANSACTION_SETUP__DOUT_3_CTRL__WIDTH 2 +#define QSPI_TRANSACTION_SETUP__DOUT_3_CTRL__MASK 0x00300000U +#define QSPI_TRANSACTION_SETUP__DOUT_3_CTRL__READ(src) \ + (((uint32_t)(src)\ + & 0x00300000U) >> 20) +#define QSPI_TRANSACTION_SETUP__DOUT_3_CTRL__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00300000U) +#define QSPI_TRANSACTION_SETUP__DOUT_3_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00300000U) | (((uint32_t)(src) <<\ + 20) & 0x00300000U) +#define QSPI_TRANSACTION_SETUP__DOUT_3_CTRL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00300000U))) +#define QSPI_TRANSACTION_SETUP__DOUT_3_CTRL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clk_val */ +/** + * @defgroup at_apb_qspi_regs_core_clk_val_field clk_val_field + * @brief macros for field clk_val + * @{ + */ +#define QSPI_TRANSACTION_SETUP__CLK_VAL__SHIFT 24 +#define QSPI_TRANSACTION_SETUP__CLK_VAL__WIDTH 1 +#define QSPI_TRANSACTION_SETUP__CLK_VAL__MASK 0x01000000U +#define QSPI_TRANSACTION_SETUP__CLK_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define QSPI_TRANSACTION_SETUP__CLK_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define QSPI_TRANSACTION_SETUP__CLK_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define QSPI_TRANSACTION_SETUP__CLK_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define QSPI_TRANSACTION_SETUP__CLK_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define QSPI_TRANSACTION_SETUP__CLK_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define QSPI_TRANSACTION_SETUP__CLK_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field csn_val */ +/** + * @defgroup at_apb_qspi_regs_core_csn_val_field csn_val_field + * @brief macros for field csn_val + * @{ + */ +#define QSPI_TRANSACTION_SETUP__CSN_VAL__SHIFT 25 +#define QSPI_TRANSACTION_SETUP__CSN_VAL__WIDTH 1 +#define QSPI_TRANSACTION_SETUP__CSN_VAL__MASK 0x02000000U +#define QSPI_TRANSACTION_SETUP__CSN_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define QSPI_TRANSACTION_SETUP__CSN_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define QSPI_TRANSACTION_SETUP__CSN_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define QSPI_TRANSACTION_SETUP__CSN_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define QSPI_TRANSACTION_SETUP__CSN_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define QSPI_TRANSACTION_SETUP__CSN_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define QSPI_TRANSACTION_SETUP__CSN_VAL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field remote_ahb_qspi_has_control */ +/** + * @defgroup at_apb_qspi_regs_core_remote_ahb_qspi_has_control_field remote_ahb_qspi_has_control_field + * @brief macros for field remote_ahb_qspi_has_control + * @{ + */ +#define QSPI_TRANSACTION_SETUP__REMOTE_AHB_QSPI_HAS_CONTROL__SHIFT 28 +#define QSPI_TRANSACTION_SETUP__REMOTE_AHB_QSPI_HAS_CONTROL__WIDTH 1 +#define QSPI_TRANSACTION_SETUP__REMOTE_AHB_QSPI_HAS_CONTROL__MASK 0x10000000U +#define QSPI_TRANSACTION_SETUP__REMOTE_AHB_QSPI_HAS_CONTROL__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define QSPI_TRANSACTION_SETUP__REMOTE_AHB_QSPI_HAS_CONTROL__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define QSPI_TRANSACTION_SETUP__REMOTE_AHB_QSPI_HAS_CONTROL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define QSPI_TRANSACTION_SETUP__REMOTE_AHB_QSPI_HAS_CONTROL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define QSPI_TRANSACTION_SETUP__REMOTE_AHB_QSPI_HAS_CONTROL__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define QSPI_TRANSACTION_SETUP__REMOTE_AHB_QSPI_HAS_CONTROL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define QSPI_TRANSACTION_SETUP__REMOTE_AHB_QSPI_HAS_CONTROL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field remote_spi_has_control */ +/** + * @defgroup at_apb_qspi_regs_core_remote_spi_has_control_field remote_spi_has_control_field + * @brief macros for field remote_spi_has_control + * @{ + */ +#define QSPI_TRANSACTION_SETUP__REMOTE_SPI_HAS_CONTROL__SHIFT 29 +#define QSPI_TRANSACTION_SETUP__REMOTE_SPI_HAS_CONTROL__WIDTH 1 +#define QSPI_TRANSACTION_SETUP__REMOTE_SPI_HAS_CONTROL__MASK 0x20000000U +#define QSPI_TRANSACTION_SETUP__REMOTE_SPI_HAS_CONTROL__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define QSPI_TRANSACTION_SETUP__REMOTE_SPI_HAS_CONTROL__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define QSPI_TRANSACTION_SETUP__REMOTE_SPI_HAS_CONTROL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define QSPI_TRANSACTION_SETUP__REMOTE_SPI_HAS_CONTROL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define QSPI_TRANSACTION_SETUP__REMOTE_SPI_HAS_CONTROL__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define QSPI_TRANSACTION_SETUP__REMOTE_SPI_HAS_CONTROL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define QSPI_TRANSACTION_SETUP__REMOTE_SPI_HAS_CONTROL__RESET_VALUE 0x00000001U +/** @} */ +#define QSPI_TRANSACTION_SETUP__TYPE uint32_t +#define QSPI_TRANSACTION_SETUP__READ 0x333333ffU +#define QSPI_TRANSACTION_SETUP__WRITE 0x333333ffU +#define QSPI_TRANSACTION_SETUP__PRESERVED 0x00000000U +#define QSPI_TRANSACTION_SETUP__RESET_VALUE 0x22000000U + +#endif /* __QSPI_TRANSACTION_SETUP_MACRO__ */ + +/** @} end of transaction_setup */ + +/* macros for BlueprintGlobalNameSpace::QSPI_read_data */ +/** + * @defgroup at_apb_qspi_regs_core_read_data read_data + * @brief Contains register fields associated with read_data. definitions. + * @{ + */ +#ifndef __QSPI_READ_DATA_MACRO__ +#define __QSPI_READ_DATA_MACRO__ + +/* macros for field rdata */ +/** + * @defgroup at_apb_qspi_regs_core_rdata_field rdata_field + * @brief macros for field rdata + * @{ + */ +#define QSPI_READ_DATA__RDATA__SHIFT 0 +#define QSPI_READ_DATA__RDATA__WIDTH 8 +#define QSPI_READ_DATA__RDATA__MASK 0x000000ffU +#define QSPI_READ_DATA__RDATA__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define QSPI_READ_DATA__RDATA__RESET_VALUE 0x00000000U +/** @} */ +#define QSPI_READ_DATA__TYPE uint32_t +#define QSPI_READ_DATA__READ 0x000000ffU +#define QSPI_READ_DATA__PRESERVED 0x00000000U +#define QSPI_READ_DATA__RESET_VALUE 0x00000000U + +#endif /* __QSPI_READ_DATA_MACRO__ */ + +/** @} end of read_data */ + +/* macros for BlueprintGlobalNameSpace::QSPI_override_din */ +/** + * @defgroup at_apb_qspi_regs_core_override_din override_din + * @brief Contains register fields associated with override_din. definitions. + * @{ + */ +#ifndef __QSPI_OVERRIDE_DIN_MACRO__ +#define __QSPI_OVERRIDE_DIN_MACRO__ + +/* macros for field din_override_val */ +/** + * @defgroup at_apb_qspi_regs_core_din_override_val_field din_override_val_field + * @brief macros for field din_override_val + * @{ + */ +#define QSPI_OVERRIDE_DIN__DIN_OVERRIDE_VAL__SHIFT 0 +#define QSPI_OVERRIDE_DIN__DIN_OVERRIDE_VAL__WIDTH 4 +#define QSPI_OVERRIDE_DIN__DIN_OVERRIDE_VAL__MASK 0x0000000fU +#define QSPI_OVERRIDE_DIN__DIN_OVERRIDE_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define QSPI_OVERRIDE_DIN__DIN_OVERRIDE_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define QSPI_OVERRIDE_DIN__DIN_OVERRIDE_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define QSPI_OVERRIDE_DIN__DIN_OVERRIDE_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define QSPI_OVERRIDE_DIN__DIN_OVERRIDE_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_din */ +/** + * @defgroup at_apb_qspi_regs_core_override_din_field override_din_field + * @brief macros for field override_din + * @{ + */ +#define QSPI_OVERRIDE_DIN__OVERRIDE_DIN__SHIFT 4 +#define QSPI_OVERRIDE_DIN__OVERRIDE_DIN__WIDTH 1 +#define QSPI_OVERRIDE_DIN__OVERRIDE_DIN__MASK 0x00000010U +#define QSPI_OVERRIDE_DIN__OVERRIDE_DIN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define QSPI_OVERRIDE_DIN__OVERRIDE_DIN__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define QSPI_OVERRIDE_DIN__OVERRIDE_DIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define QSPI_OVERRIDE_DIN__OVERRIDE_DIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define QSPI_OVERRIDE_DIN__OVERRIDE_DIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define QSPI_OVERRIDE_DIN__OVERRIDE_DIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define QSPI_OVERRIDE_DIN__OVERRIDE_DIN__RESET_VALUE 0x00000000U +/** @} */ +#define QSPI_OVERRIDE_DIN__TYPE uint32_t +#define QSPI_OVERRIDE_DIN__READ 0x0000001fU +#define QSPI_OVERRIDE_DIN__WRITE 0x0000001fU +#define QSPI_OVERRIDE_DIN__PRESERVED 0x00000000U +#define QSPI_OVERRIDE_DIN__RESET_VALUE 0x00000000U + +#endif /* __QSPI_OVERRIDE_DIN_MACRO__ */ + +/** @} end of override_din */ + +/* macros for BlueprintGlobalNameSpace::QSPI_mode */ +/** + * @defgroup at_apb_qspi_regs_core_mode mode + * @brief Contains register fields associated with mode. definitions. + * @{ + */ +#ifndef __QSPI_MODE_MACRO__ +#define __QSPI_MODE_MACRO__ + +/* macros for field is_dual */ +/** + * @defgroup at_apb_qspi_regs_core_is_dual_field is_dual_field + * @brief macros for field is_dual + * @details for debug + * @{ + */ +#define QSPI_MODE__IS_DUAL__SHIFT 0 +#define QSPI_MODE__IS_DUAL__WIDTH 1 +#define QSPI_MODE__IS_DUAL__MASK 0x00000001U +#define QSPI_MODE__IS_DUAL__READ(src) ((uint32_t)(src) & 0x00000001U) +#define QSPI_MODE__IS_DUAL__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define QSPI_MODE__IS_DUAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define QSPI_MODE__IS_DUAL__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define QSPI_MODE__IS_DUAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define QSPI_MODE__IS_DUAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define QSPI_MODE__IS_DUAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field is_quad */ +/** + * @defgroup at_apb_qspi_regs_core_is_quad_field is_quad_field + * @brief macros for field is_quad + * @details high priority than is_dual + * @{ + */ +#define QSPI_MODE__IS_QUAD__SHIFT 1 +#define QSPI_MODE__IS_QUAD__WIDTH 1 +#define QSPI_MODE__IS_QUAD__MASK 0x00000002U +#define QSPI_MODE__IS_QUAD__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define QSPI_MODE__IS_QUAD__WRITE(src) (((uint32_t)(src) << 1) & 0x00000002U) +#define QSPI_MODE__IS_QUAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define QSPI_MODE__IS_QUAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define QSPI_MODE__IS_QUAD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define QSPI_MODE__IS_QUAD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define QSPI_MODE__IS_QUAD__RESET_VALUE 0x00000001U +/** @} */ +#define QSPI_MODE__TYPE uint32_t +#define QSPI_MODE__READ 0x00000003U +#define QSPI_MODE__WRITE 0x00000003U +#define QSPI_MODE__PRESERVED 0x00000000U +#define QSPI_MODE__RESET_VALUE 0x00000002U + +#endif /* __QSPI_MODE_MACRO__ */ + +/** @} end of mode */ + +/* macros for BlueprintGlobalNameSpace::QSPI_remote_ahb_setup */ +/** + * @defgroup at_apb_qspi_regs_core_remote_ahb_setup remote_ahb_setup + * @brief Contains register fields associated with remote_ahb_setup. definitions. + * @{ + */ +#ifndef __QSPI_REMOTE_AHB_SETUP_MACRO__ +#define __QSPI_REMOTE_AHB_SETUP_MACRO__ + +/* macros for field dummy_cycles */ +/** + * @defgroup at_apb_qspi_regs_core_dummy_cycles_field dummy_cycles_field + * @brief macros for field dummy_cycles + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP__DUMMY_CYCLES__SHIFT 0 +#define QSPI_REMOTE_AHB_SETUP__DUMMY_CYCLES__WIDTH 4 +#define QSPI_REMOTE_AHB_SETUP__DUMMY_CYCLES__MASK 0x0000000fU +#define QSPI_REMOTE_AHB_SETUP__DUMMY_CYCLES__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define QSPI_REMOTE_AHB_SETUP__DUMMY_CYCLES__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define QSPI_REMOTE_AHB_SETUP__DUMMY_CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define QSPI_REMOTE_AHB_SETUP__DUMMY_CYCLES__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define QSPI_REMOTE_AHB_SETUP__DUMMY_CYCLES__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mode */ +/** + * @defgroup at_apb_qspi_regs_core_mode_field mode_field + * @brief macros for field mode + * @details 0,3=single 1=dual 2=quad + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP__MODE__SHIFT 4 +#define QSPI_REMOTE_AHB_SETUP__MODE__WIDTH 2 +#define QSPI_REMOTE_AHB_SETUP__MODE__MASK 0x00000030U +#define QSPI_REMOTE_AHB_SETUP__MODE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000030U) >> 4) +#define QSPI_REMOTE_AHB_SETUP__MODE__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000030U) +#define QSPI_REMOTE_AHB_SETUP__MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((uint32_t)(src) <<\ + 4) & 0x00000030U) +#define QSPI_REMOTE_AHB_SETUP__MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000030U))) +#define QSPI_REMOTE_AHB_SETUP__MODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field is_opcode */ +/** + * @defgroup at_apb_qspi_regs_core_is_opcode_field is_opcode_field + * @brief macros for field is_opcode + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP__IS_OPCODE__SHIFT 6 +#define QSPI_REMOTE_AHB_SETUP__IS_OPCODE__WIDTH 1 +#define QSPI_REMOTE_AHB_SETUP__IS_OPCODE__MASK 0x00000040U +#define QSPI_REMOTE_AHB_SETUP__IS_OPCODE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define QSPI_REMOTE_AHB_SETUP__IS_OPCODE__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define QSPI_REMOTE_AHB_SETUP__IS_OPCODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define QSPI_REMOTE_AHB_SETUP__IS_OPCODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define QSPI_REMOTE_AHB_SETUP__IS_OPCODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define QSPI_REMOTE_AHB_SETUP__IS_OPCODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define QSPI_REMOTE_AHB_SETUP__IS_OPCODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field opcode */ +/** + * @defgroup at_apb_qspi_regs_core_opcode_field opcode_field + * @brief macros for field opcode + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP__OPCODE__SHIFT 8 +#define QSPI_REMOTE_AHB_SETUP__OPCODE__WIDTH 8 +#define QSPI_REMOTE_AHB_SETUP__OPCODE__MASK 0x0000ff00U +#define QSPI_REMOTE_AHB_SETUP__OPCODE__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define QSPI_REMOTE_AHB_SETUP__OPCODE__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define QSPI_REMOTE_AHB_SETUP__OPCODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define QSPI_REMOTE_AHB_SETUP__OPCODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define QSPI_REMOTE_AHB_SETUP__OPCODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clkdivsel */ +/** + * @defgroup at_apb_qspi_regs_core_clkdivsel_field clkdivsel_field + * @brief macros for field clkdivsel + * @details 0=1x 1=2x 2=4x 3=8x + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP__CLKDIVSEL__SHIFT 16 +#define QSPI_REMOTE_AHB_SETUP__CLKDIVSEL__WIDTH 2 +#define QSPI_REMOTE_AHB_SETUP__CLKDIVSEL__MASK 0x00030000U +#define QSPI_REMOTE_AHB_SETUP__CLKDIVSEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00030000U) >> 16) +#define QSPI_REMOTE_AHB_SETUP__CLKDIVSEL__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00030000U) +#define QSPI_REMOTE_AHB_SETUP__CLKDIVSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00030000U) | (((uint32_t)(src) <<\ + 16) & 0x00030000U) +#define QSPI_REMOTE_AHB_SETUP__CLKDIVSEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00030000U))) +#define QSPI_REMOTE_AHB_SETUP__CLKDIVSEL__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field rdata_byte_swap */ +/** + * @defgroup at_apb_qspi_regs_core_rdata_byte_swap_field rdata_byte_swap_field + * @brief macros for field rdata_byte_swap + * @details does a byte swap before passing rdata to backplane + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP__RDATA_BYTE_SWAP__SHIFT 18 +#define QSPI_REMOTE_AHB_SETUP__RDATA_BYTE_SWAP__WIDTH 1 +#define QSPI_REMOTE_AHB_SETUP__RDATA_BYTE_SWAP__MASK 0x00040000U +#define QSPI_REMOTE_AHB_SETUP__RDATA_BYTE_SWAP__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define QSPI_REMOTE_AHB_SETUP__RDATA_BYTE_SWAP__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define QSPI_REMOTE_AHB_SETUP__RDATA_BYTE_SWAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define QSPI_REMOTE_AHB_SETUP__RDATA_BYTE_SWAP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define QSPI_REMOTE_AHB_SETUP__RDATA_BYTE_SWAP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define QSPI_REMOTE_AHB_SETUP__RDATA_BYTE_SWAP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define QSPI_REMOTE_AHB_SETUP__RDATA_BYTE_SWAP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field quad_overhead */ +/** + * @defgroup at_apb_qspi_regs_core_quad_overhead_field quad_overhead_field + * @brief macros for field quad_overhead + * @details adds overhead cycles during quad I/O read mode 1 = opcode is fully serial (8-cycles), adds two cycles for performance enhance; (macronix, gigadev, winbond) 0 = opcode is parallelized (2-cycles); no performance enhance cycles needed (micron) + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP__QUAD_OVERHEAD__SHIFT 19 +#define QSPI_REMOTE_AHB_SETUP__QUAD_OVERHEAD__WIDTH 1 +#define QSPI_REMOTE_AHB_SETUP__QUAD_OVERHEAD__MASK 0x00080000U +#define QSPI_REMOTE_AHB_SETUP__QUAD_OVERHEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define QSPI_REMOTE_AHB_SETUP__QUAD_OVERHEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define QSPI_REMOTE_AHB_SETUP__QUAD_OVERHEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define QSPI_REMOTE_AHB_SETUP__QUAD_OVERHEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define QSPI_REMOTE_AHB_SETUP__QUAD_OVERHEAD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define QSPI_REMOTE_AHB_SETUP__QUAD_OVERHEAD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define QSPI_REMOTE_AHB_SETUP__QUAD_OVERHEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wdata_byte_swap */ +/** + * @defgroup at_apb_qspi_regs_core_wdata_byte_swap_field wdata_byte_swap_field + * @brief macros for field wdata_byte_swap + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP__WDATA_BYTE_SWAP__SHIFT 20 +#define QSPI_REMOTE_AHB_SETUP__WDATA_BYTE_SWAP__WIDTH 1 +#define QSPI_REMOTE_AHB_SETUP__WDATA_BYTE_SWAP__MASK 0x00100000U +#define QSPI_REMOTE_AHB_SETUP__WDATA_BYTE_SWAP__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define QSPI_REMOTE_AHB_SETUP__WDATA_BYTE_SWAP__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define QSPI_REMOTE_AHB_SETUP__WDATA_BYTE_SWAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define QSPI_REMOTE_AHB_SETUP__WDATA_BYTE_SWAP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define QSPI_REMOTE_AHB_SETUP__WDATA_BYTE_SWAP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define QSPI_REMOTE_AHB_SETUP__WDATA_BYTE_SWAP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define QSPI_REMOTE_AHB_SETUP__WDATA_BYTE_SWAP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wdata_halfword_swap */ +/** + * @defgroup at_apb_qspi_regs_core_wdata_halfword_swap_field wdata_halfword_swap_field + * @brief macros for field wdata_halfword_swap + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP__WDATA_HALFWORD_SWAP__SHIFT 21 +#define QSPI_REMOTE_AHB_SETUP__WDATA_HALFWORD_SWAP__WIDTH 1 +#define QSPI_REMOTE_AHB_SETUP__WDATA_HALFWORD_SWAP__MASK 0x00200000U +#define QSPI_REMOTE_AHB_SETUP__WDATA_HALFWORD_SWAP__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define QSPI_REMOTE_AHB_SETUP__WDATA_HALFWORD_SWAP__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define QSPI_REMOTE_AHB_SETUP__WDATA_HALFWORD_SWAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define QSPI_REMOTE_AHB_SETUP__WDATA_HALFWORD_SWAP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define QSPI_REMOTE_AHB_SETUP__WDATA_HALFWORD_SWAP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define QSPI_REMOTE_AHB_SETUP__WDATA_HALFWORD_SWAP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define QSPI_REMOTE_AHB_SETUP__WDATA_HALFWORD_SWAP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wdata_word_swap */ +/** + * @defgroup at_apb_qspi_regs_core_wdata_word_swap_field wdata_word_swap_field + * @brief macros for field wdata_word_swap + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP__WDATA_WORD_SWAP__SHIFT 22 +#define QSPI_REMOTE_AHB_SETUP__WDATA_WORD_SWAP__WIDTH 1 +#define QSPI_REMOTE_AHB_SETUP__WDATA_WORD_SWAP__MASK 0x00400000U +#define QSPI_REMOTE_AHB_SETUP__WDATA_WORD_SWAP__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define QSPI_REMOTE_AHB_SETUP__WDATA_WORD_SWAP__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define QSPI_REMOTE_AHB_SETUP__WDATA_WORD_SWAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define QSPI_REMOTE_AHB_SETUP__WDATA_WORD_SWAP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define QSPI_REMOTE_AHB_SETUP__WDATA_WORD_SWAP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define QSPI_REMOTE_AHB_SETUP__WDATA_WORD_SWAP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define QSPI_REMOTE_AHB_SETUP__WDATA_WORD_SWAP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enable_clocks */ +/** + * @defgroup at_apb_qspi_regs_core_enable_clocks_field enable_clocks_field + * @brief macros for field enable_clocks + * @details for the core clocks not the qspi interface clock + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP__ENABLE_CLOCKS__SHIFT 23 +#define QSPI_REMOTE_AHB_SETUP__ENABLE_CLOCKS__WIDTH 1 +#define QSPI_REMOTE_AHB_SETUP__ENABLE_CLOCKS__MASK 0x00800000U +#define QSPI_REMOTE_AHB_SETUP__ENABLE_CLOCKS__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define QSPI_REMOTE_AHB_SETUP__ENABLE_CLOCKS__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define QSPI_REMOTE_AHB_SETUP__ENABLE_CLOCKS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define QSPI_REMOTE_AHB_SETUP__ENABLE_CLOCKS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define QSPI_REMOTE_AHB_SETUP__ENABLE_CLOCKS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define QSPI_REMOTE_AHB_SETUP__ENABLE_CLOCKS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define QSPI_REMOTE_AHB_SETUP__ENABLE_CLOCKS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enable_cache */ +/** + * @defgroup at_apb_qspi_regs_core_enable_cache_field enable_cache_field + * @brief macros for field enable_cache + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP__ENABLE_CACHE__SHIFT 24 +#define QSPI_REMOTE_AHB_SETUP__ENABLE_CACHE__WIDTH 1 +#define QSPI_REMOTE_AHB_SETUP__ENABLE_CACHE__MASK 0x01000000U +#define QSPI_REMOTE_AHB_SETUP__ENABLE_CACHE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define QSPI_REMOTE_AHB_SETUP__ENABLE_CACHE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define QSPI_REMOTE_AHB_SETUP__ENABLE_CACHE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define QSPI_REMOTE_AHB_SETUP__ENABLE_CACHE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define QSPI_REMOTE_AHB_SETUP__ENABLE_CACHE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define QSPI_REMOTE_AHB_SETUP__ENABLE_CACHE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define QSPI_REMOTE_AHB_SETUP__ENABLE_CACHE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enable_fine_clock_gating */ +/** + * @defgroup at_apb_qspi_regs_core_enable_fine_clock_gating_field enable_fine_clock_gating_field + * @brief macros for field enable_fine_clock_gating + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP__ENABLE_FINE_CLOCK_GATING__SHIFT 25 +#define QSPI_REMOTE_AHB_SETUP__ENABLE_FINE_CLOCK_GATING__WIDTH 1 +#define QSPI_REMOTE_AHB_SETUP__ENABLE_FINE_CLOCK_GATING__MASK 0x02000000U +#define QSPI_REMOTE_AHB_SETUP__ENABLE_FINE_CLOCK_GATING__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define QSPI_REMOTE_AHB_SETUP__ENABLE_FINE_CLOCK_GATING__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define QSPI_REMOTE_AHB_SETUP__ENABLE_FINE_CLOCK_GATING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define QSPI_REMOTE_AHB_SETUP__ENABLE_FINE_CLOCK_GATING__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define QSPI_REMOTE_AHB_SETUP__ENABLE_FINE_CLOCK_GATING__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define QSPI_REMOTE_AHB_SETUP__ENABLE_FINE_CLOCK_GATING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define QSPI_REMOTE_AHB_SETUP__ENABLE_FINE_CLOCK_GATING__RESET_VALUE \ + 0x00000001U +/** @} */ + +/* macros for field invalidate_entire_cache */ +/** + * @defgroup at_apb_qspi_regs_core_invalidate_entire_cache_field invalidate_entire_cache_field + * @brief macros for field invalidate_entire_cache + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP__INVALIDATE_ENTIRE_CACHE__SHIFT 26 +#define QSPI_REMOTE_AHB_SETUP__INVALIDATE_ENTIRE_CACHE__WIDTH 1 +#define QSPI_REMOTE_AHB_SETUP__INVALIDATE_ENTIRE_CACHE__MASK 0x04000000U +#define QSPI_REMOTE_AHB_SETUP__INVALIDATE_ENTIRE_CACHE__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define QSPI_REMOTE_AHB_SETUP__INVALIDATE_ENTIRE_CACHE__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define QSPI_REMOTE_AHB_SETUP__INVALIDATE_ENTIRE_CACHE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define QSPI_REMOTE_AHB_SETUP__INVALIDATE_ENTIRE_CACHE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define QSPI_REMOTE_AHB_SETUP__INVALIDATE_ENTIRE_CACHE__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define QSPI_REMOTE_AHB_SETUP__INVALIDATE_ENTIRE_CACHE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define QSPI_REMOTE_AHB_SETUP__INVALIDATE_ENTIRE_CACHE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field serialize_pp_address */ +/** + * @defgroup at_apb_qspi_regs_core_serialize_pp_address_field serialize_pp_address_field + * @brief macros for field serialize_pp_address + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP__SERIALIZE_PP_ADDRESS__SHIFT 27 +#define QSPI_REMOTE_AHB_SETUP__SERIALIZE_PP_ADDRESS__WIDTH 1 +#define QSPI_REMOTE_AHB_SETUP__SERIALIZE_PP_ADDRESS__MASK 0x08000000U +#define QSPI_REMOTE_AHB_SETUP__SERIALIZE_PP_ADDRESS__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define QSPI_REMOTE_AHB_SETUP__SERIALIZE_PP_ADDRESS__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define QSPI_REMOTE_AHB_SETUP__SERIALIZE_PP_ADDRESS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define QSPI_REMOTE_AHB_SETUP__SERIALIZE_PP_ADDRESS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define QSPI_REMOTE_AHB_SETUP__SERIALIZE_PP_ADDRESS__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define QSPI_REMOTE_AHB_SETUP__SERIALIZE_PP_ADDRESS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define QSPI_REMOTE_AHB_SETUP__SERIALIZE_PP_ADDRESS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field skew_csn_act_wen */ +/** + * @defgroup at_apb_qspi_regs_core_skew_csn_act_wen_field skew_csn_act_wen_field + * @brief macros for field skew_csn_act_wen + * @details in a write sequence, controller stalls the start of the sequence; set if div-by-1 + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP__SKEW_CSN_ACT_WEN__SHIFT 28 +#define QSPI_REMOTE_AHB_SETUP__SKEW_CSN_ACT_WEN__WIDTH 1 +#define QSPI_REMOTE_AHB_SETUP__SKEW_CSN_ACT_WEN__MASK 0x10000000U +#define QSPI_REMOTE_AHB_SETUP__SKEW_CSN_ACT_WEN__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define QSPI_REMOTE_AHB_SETUP__SKEW_CSN_ACT_WEN__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define QSPI_REMOTE_AHB_SETUP__SKEW_CSN_ACT_WEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define QSPI_REMOTE_AHB_SETUP__SKEW_CSN_ACT_WEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define QSPI_REMOTE_AHB_SETUP__SKEW_CSN_ACT_WEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define QSPI_REMOTE_AHB_SETUP__SKEW_CSN_ACT_WEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define QSPI_REMOTE_AHB_SETUP__SKEW_CSN_ACT_WEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hyper */ +/** + * @defgroup at_apb_qspi_regs_core_hyper_field hyper_field + * @brief macros for field hyper + * @details core runs at 32MHz instead of 16MHz + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP__HYPER__SHIFT 29 +#define QSPI_REMOTE_AHB_SETUP__HYPER__WIDTH 1 +#define QSPI_REMOTE_AHB_SETUP__HYPER__MASK 0x20000000U +#define QSPI_REMOTE_AHB_SETUP__HYPER__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define QSPI_REMOTE_AHB_SETUP__HYPER__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define QSPI_REMOTE_AHB_SETUP__HYPER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define QSPI_REMOTE_AHB_SETUP__HYPER__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define QSPI_REMOTE_AHB_SETUP__HYPER__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define QSPI_REMOTE_AHB_SETUP__HYPER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define QSPI_REMOTE_AHB_SETUP__HYPER__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field slip_half_cycle */ +/** + * @defgroup at_apb_qspi_regs_core_slip_half_cycle_field slip_half_cycle_field + * @brief macros for field slip_half_cycle + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP__SLIP_HALF_CYCLE__SHIFT 30 +#define QSPI_REMOTE_AHB_SETUP__SLIP_HALF_CYCLE__WIDTH 1 +#define QSPI_REMOTE_AHB_SETUP__SLIP_HALF_CYCLE__MASK 0x40000000U +#define QSPI_REMOTE_AHB_SETUP__SLIP_HALF_CYCLE__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define QSPI_REMOTE_AHB_SETUP__SLIP_HALF_CYCLE__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define QSPI_REMOTE_AHB_SETUP__SLIP_HALF_CYCLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define QSPI_REMOTE_AHB_SETUP__SLIP_HALF_CYCLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define QSPI_REMOTE_AHB_SETUP__SLIP_HALF_CYCLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define QSPI_REMOTE_AHB_SETUP__SLIP_HALF_CYCLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define QSPI_REMOTE_AHB_SETUP__SLIP_HALF_CYCLE__RESET_VALUE 0x00000000U +/** @} */ +#define QSPI_REMOTE_AHB_SETUP__TYPE uint32_t +#define QSPI_REMOTE_AHB_SETUP__READ 0x7fffff7fU +#define QSPI_REMOTE_AHB_SETUP__WRITE 0x7fffff7fU +#define QSPI_REMOTE_AHB_SETUP__PRESERVED 0x00000000U +#define QSPI_REMOTE_AHB_SETUP__RESET_VALUE 0x02030000U + +#endif /* __QSPI_REMOTE_AHB_SETUP_MACRO__ */ + +/** @} end of remote_ahb_setup */ + +/* macros for BlueprintGlobalNameSpace::QSPI_remote_ahb_setup_2 */ +/** + * @defgroup at_apb_qspi_regs_core_remote_ahb_setup_2 remote_ahb_setup_2 + * @brief Contains register fields associated with remote_ahb_setup_2. definitions. + * @{ + */ +#ifndef __QSPI_REMOTE_AHB_SETUP_2_MACRO__ +#define __QSPI_REMOTE_AHB_SETUP_2_MACRO__ + +/* macros for field opcode_we */ +/** + * @defgroup at_apb_qspi_regs_core_opcode_we_field opcode_we_field + * @brief macros for field opcode_we + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_WE__SHIFT 0 +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_WE__WIDTH 8 +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_WE__MASK 0x000000ffU +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_WE__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_WE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_WE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_WE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_WE__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field opcode_pp */ +/** + * @defgroup at_apb_qspi_regs_core_opcode_pp_field opcode_pp_field + * @brief macros for field opcode_pp + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_PP__SHIFT 8 +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_PP__WIDTH 8 +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_PP__MASK 0x0000ff00U +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_PP__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_PP__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_PP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_PP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_PP__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field opcode_wip */ +/** + * @defgroup at_apb_qspi_regs_core_opcode_wip_field opcode_wip_field + * @brief macros for field opcode_wip + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_WIP__SHIFT 16 +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_WIP__WIDTH 8 +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_WIP__MASK 0x00ff0000U +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_WIP__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_WIP__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_WIP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_WIP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_WIP__RESET_VALUE 0x00000005U +/** @} */ + +/* macros for field opcode_se */ +/** + * @defgroup at_apb_qspi_regs_core_opcode_se_field opcode_se_field + * @brief macros for field opcode_se + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_SE__SHIFT 24 +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_SE__WIDTH 8 +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_SE__MASK 0xff000000U +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_SE__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_SE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_SE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_SE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define QSPI_REMOTE_AHB_SETUP_2__OPCODE_SE__RESET_VALUE 0x00000020U +/** @} */ +#define QSPI_REMOTE_AHB_SETUP_2__TYPE uint32_t +#define QSPI_REMOTE_AHB_SETUP_2__READ 0xffffffffU +#define QSPI_REMOTE_AHB_SETUP_2__WRITE 0xffffffffU +#define QSPI_REMOTE_AHB_SETUP_2__PRESERVED 0x00000000U +#define QSPI_REMOTE_AHB_SETUP_2__RESET_VALUE 0x20050206U + +#endif /* __QSPI_REMOTE_AHB_SETUP_2_MACRO__ */ + +/** @} end of remote_ahb_setup_2 */ + +/* macros for BlueprintGlobalNameSpace::QSPI_remote_ahb_setup_3 */ +/** + * @defgroup at_apb_qspi_regs_core_remote_ahb_setup_3 remote_ahb_setup_3 + * @brief Contains register fields associated with remote_ahb_setup_3. definitions. + * @{ + */ +#ifndef __QSPI_REMOTE_AHB_SETUP_3_MACRO__ +#define __QSPI_REMOTE_AHB_SETUP_3_MACRO__ + +/* macros for field opcode_performance_mode */ +/** + * @defgroup at_apb_qspi_regs_core_opcode_performance_mode_field opcode_performance_mode_field + * @brief macros for field opcode_performance_mode + * @details performance enhance mode opcode macronix = 8'h5A gigadev = 8'hAx winbond = 8'h20 + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP_3__OPCODE_PERFORMANCE_MODE__SHIFT 14 +#define QSPI_REMOTE_AHB_SETUP_3__OPCODE_PERFORMANCE_MODE__WIDTH 8 +#define QSPI_REMOTE_AHB_SETUP_3__OPCODE_PERFORMANCE_MODE__MASK 0x003fc000U +#define QSPI_REMOTE_AHB_SETUP_3__OPCODE_PERFORMANCE_MODE__READ(src) \ + (((uint32_t)(src)\ + & 0x003fc000U) >> 14) +#define QSPI_REMOTE_AHB_SETUP_3__OPCODE_PERFORMANCE_MODE__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x003fc000U) +#define QSPI_REMOTE_AHB_SETUP_3__OPCODE_PERFORMANCE_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fc000U) | (((uint32_t)(src) <<\ + 14) & 0x003fc000U) +#define QSPI_REMOTE_AHB_SETUP_3__OPCODE_PERFORMANCE_MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x003fc000U))) +#define QSPI_REMOTE_AHB_SETUP_3__OPCODE_PERFORMANCE_MODE__RESET_VALUE \ + 0x0000005aU +/** @} */ + +/* macros for field enable_performance_mode */ +/** + * @defgroup at_apb_qspi_regs_core_enable_performance_mode_field enable_performance_mode_field + * @brief macros for field enable_performance_mode + * @details enable performace enhance mode for supported flash + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP_3__ENABLE_PERFORMANCE_MODE__SHIFT 22 +#define QSPI_REMOTE_AHB_SETUP_3__ENABLE_PERFORMANCE_MODE__WIDTH 1 +#define QSPI_REMOTE_AHB_SETUP_3__ENABLE_PERFORMANCE_MODE__MASK 0x00400000U +#define QSPI_REMOTE_AHB_SETUP_3__ENABLE_PERFORMANCE_MODE__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define QSPI_REMOTE_AHB_SETUP_3__ENABLE_PERFORMANCE_MODE__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define QSPI_REMOTE_AHB_SETUP_3__ENABLE_PERFORMANCE_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define QSPI_REMOTE_AHB_SETUP_3__ENABLE_PERFORMANCE_MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define QSPI_REMOTE_AHB_SETUP_3__ENABLE_PERFORMANCE_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define QSPI_REMOTE_AHB_SETUP_3__ENABLE_PERFORMANCE_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define QSPI_REMOTE_AHB_SETUP_3__ENABLE_PERFORMANCE_MODE__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field wle_polarity */ +/** + * @defgroup at_apb_qspi_regs_core_wle_polarity_field wle_polarity_field + * @brief macros for field wle_polarity + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP_3__WLE_POLARITY__SHIFT 23 +#define QSPI_REMOTE_AHB_SETUP_3__WLE_POLARITY__WIDTH 1 +#define QSPI_REMOTE_AHB_SETUP_3__WLE_POLARITY__MASK 0x00800000U +#define QSPI_REMOTE_AHB_SETUP_3__WLE_POLARITY__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define QSPI_REMOTE_AHB_SETUP_3__WLE_POLARITY__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define QSPI_REMOTE_AHB_SETUP_3__WLE_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define QSPI_REMOTE_AHB_SETUP_3__WLE_POLARITY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define QSPI_REMOTE_AHB_SETUP_3__WLE_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define QSPI_REMOTE_AHB_SETUP_3__WLE_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define QSPI_REMOTE_AHB_SETUP_3__WLE_POLARITY__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field wle_bit */ +/** + * @defgroup at_apb_qspi_regs_core_wle_bit_field wle_bit_field + * @brief macros for field wle_bit + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP_3__WLE_BIT__SHIFT 24 +#define QSPI_REMOTE_AHB_SETUP_3__WLE_BIT__WIDTH 3 +#define QSPI_REMOTE_AHB_SETUP_3__WLE_BIT__MASK 0x07000000U +#define QSPI_REMOTE_AHB_SETUP_3__WLE_BIT__READ(src) \ + (((uint32_t)(src)\ + & 0x07000000U) >> 24) +#define QSPI_REMOTE_AHB_SETUP_3__WLE_BIT__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x07000000U) +#define QSPI_REMOTE_AHB_SETUP_3__WLE_BIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((uint32_t)(src) <<\ + 24) & 0x07000000U) +#define QSPI_REMOTE_AHB_SETUP_3__WLE_BIT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x07000000U))) +#define QSPI_REMOTE_AHB_SETUP_3__WLE_BIT__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field wip_polarity */ +/** + * @defgroup at_apb_qspi_regs_core_wip_polarity_field wip_polarity_field + * @brief macros for field wip_polarity + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP_3__WIP_POLARITY__SHIFT 27 +#define QSPI_REMOTE_AHB_SETUP_3__WIP_POLARITY__WIDTH 1 +#define QSPI_REMOTE_AHB_SETUP_3__WIP_POLARITY__MASK 0x08000000U +#define QSPI_REMOTE_AHB_SETUP_3__WIP_POLARITY__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define QSPI_REMOTE_AHB_SETUP_3__WIP_POLARITY__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define QSPI_REMOTE_AHB_SETUP_3__WIP_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define QSPI_REMOTE_AHB_SETUP_3__WIP_POLARITY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define QSPI_REMOTE_AHB_SETUP_3__WIP_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define QSPI_REMOTE_AHB_SETUP_3__WIP_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define QSPI_REMOTE_AHB_SETUP_3__WIP_POLARITY__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field wip_bit */ +/** + * @defgroup at_apb_qspi_regs_core_wip_bit_field wip_bit_field + * @brief macros for field wip_bit + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP_3__WIP_BIT__SHIFT 28 +#define QSPI_REMOTE_AHB_SETUP_3__WIP_BIT__WIDTH 3 +#define QSPI_REMOTE_AHB_SETUP_3__WIP_BIT__MASK 0x70000000U +#define QSPI_REMOTE_AHB_SETUP_3__WIP_BIT__READ(src) \ + (((uint32_t)(src)\ + & 0x70000000U) >> 28) +#define QSPI_REMOTE_AHB_SETUP_3__WIP_BIT__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x70000000U) +#define QSPI_REMOTE_AHB_SETUP_3__WIP_BIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x70000000U) | (((uint32_t)(src) <<\ + 28) & 0x70000000U) +#define QSPI_REMOTE_AHB_SETUP_3__WIP_BIT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x70000000U))) +#define QSPI_REMOTE_AHB_SETUP_3__WIP_BIT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field check_wle */ +/** + * @defgroup at_apb_qspi_regs_core_check_wle_field check_wle_field + * @brief macros for field check_wle + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP_3__CHECK_WLE__SHIFT 31 +#define QSPI_REMOTE_AHB_SETUP_3__CHECK_WLE__WIDTH 1 +#define QSPI_REMOTE_AHB_SETUP_3__CHECK_WLE__MASK 0x80000000U +#define QSPI_REMOTE_AHB_SETUP_3__CHECK_WLE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define QSPI_REMOTE_AHB_SETUP_3__CHECK_WLE__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define QSPI_REMOTE_AHB_SETUP_3__CHECK_WLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define QSPI_REMOTE_AHB_SETUP_3__CHECK_WLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define QSPI_REMOTE_AHB_SETUP_3__CHECK_WLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define QSPI_REMOTE_AHB_SETUP_3__CHECK_WLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define QSPI_REMOTE_AHB_SETUP_3__CHECK_WLE__RESET_VALUE 0x00000000U +/** @} */ +#define QSPI_REMOTE_AHB_SETUP_3__TYPE uint32_t +#define QSPI_REMOTE_AHB_SETUP_3__READ 0xffffc000U +#define QSPI_REMOTE_AHB_SETUP_3__WRITE 0xffffc000U +#define QSPI_REMOTE_AHB_SETUP_3__PRESERVED 0x00000000U +#define QSPI_REMOTE_AHB_SETUP_3__RESET_VALUE 0x09968000U + +#endif /* __QSPI_REMOTE_AHB_SETUP_3_MACRO__ */ + +/** @} end of remote_ahb_setup_3 */ + +/* macros for BlueprintGlobalNameSpace::QSPI_remote_ahb_setup_4 */ +/** + * @defgroup at_apb_qspi_regs_core_remote_ahb_setup_4 remote_ahb_setup_4 + * @brief Contains register fields associated with remote_ahb_setup_4. definitions. + * @{ + */ +#ifndef __QSPI_REMOTE_AHB_SETUP_4_MACRO__ +#define __QSPI_REMOTE_AHB_SETUP_4_MACRO__ + +/* macros for field invert_addr */ +/** + * @defgroup at_apb_qspi_regs_core_invert_addr_field invert_addr_field + * @brief macros for field invert_addr + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP_4__INVERT_ADDR__SHIFT 0 +#define QSPI_REMOTE_AHB_SETUP_4__INVERT_ADDR__WIDTH 24 +#define QSPI_REMOTE_AHB_SETUP_4__INVERT_ADDR__MASK 0x00ffffffU +#define QSPI_REMOTE_AHB_SETUP_4__INVERT_ADDR__READ(src) \ + ((uint32_t)(src)\ + & 0x00ffffffU) +#define QSPI_REMOTE_AHB_SETUP_4__INVERT_ADDR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00ffffffU) +#define QSPI_REMOTE_AHB_SETUP_4__INVERT_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((uint32_t)(src) &\ + 0x00ffffffU) +#define QSPI_REMOTE_AHB_SETUP_4__INVERT_ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00ffffffU))) +#define QSPI_REMOTE_AHB_SETUP_4__INVERT_ADDR__RESET_VALUE 0x00000000U +/** @} */ +#define QSPI_REMOTE_AHB_SETUP_4__TYPE uint32_t +#define QSPI_REMOTE_AHB_SETUP_4__READ 0x00ffffffU +#define QSPI_REMOTE_AHB_SETUP_4__WRITE 0x00ffffffU +#define QSPI_REMOTE_AHB_SETUP_4__PRESERVED 0x00000000U +#define QSPI_REMOTE_AHB_SETUP_4__RESET_VALUE 0x00000000U + +#endif /* __QSPI_REMOTE_AHB_SETUP_4_MACRO__ */ + +/** @} end of remote_ahb_setup_4 */ + +/* macros for BlueprintGlobalNameSpace::QSPI_remote_ahb_setup_5 */ +/** + * @defgroup at_apb_qspi_regs_core_remote_ahb_setup_5 remote_ahb_setup_5 + * @brief Contains register fields associated with remote_ahb_setup_5. definitions. + * @{ + */ +#ifndef __QSPI_REMOTE_AHB_SETUP_5_MACRO__ +#define __QSPI_REMOTE_AHB_SETUP_5_MACRO__ + +/* macros for field pp_stall_wip */ +/** + * @defgroup at_apb_qspi_regs_core_pp_stall_wip_field pp_stall_wip_field + * @brief macros for field pp_stall_wip + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP_5__PP_STALL_WIP__SHIFT 0 +#define QSPI_REMOTE_AHB_SETUP_5__PP_STALL_WIP__WIDTH 10 +#define QSPI_REMOTE_AHB_SETUP_5__PP_STALL_WIP__MASK 0x000003ffU +#define QSPI_REMOTE_AHB_SETUP_5__PP_STALL_WIP__READ(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define QSPI_REMOTE_AHB_SETUP_5__PP_STALL_WIP__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define QSPI_REMOTE_AHB_SETUP_5__PP_STALL_WIP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define QSPI_REMOTE_AHB_SETUP_5__PP_STALL_WIP__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define QSPI_REMOTE_AHB_SETUP_5__PP_STALL_WIP__RESET_VALUE 0x00000200U +/** @} */ + +/* macros for field stall_wle */ +/** + * @defgroup at_apb_qspi_regs_core_stall_wle_field stall_wle_field + * @brief macros for field stall_wle + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP_5__STALL_WLE__SHIFT 10 +#define QSPI_REMOTE_AHB_SETUP_5__STALL_WLE__WIDTH 10 +#define QSPI_REMOTE_AHB_SETUP_5__STALL_WLE__MASK 0x000ffc00U +#define QSPI_REMOTE_AHB_SETUP_5__STALL_WLE__READ(src) \ + (((uint32_t)(src)\ + & 0x000ffc00U) >> 10) +#define QSPI_REMOTE_AHB_SETUP_5__STALL_WLE__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x000ffc00U) +#define QSPI_REMOTE_AHB_SETUP_5__STALL_WLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define QSPI_REMOTE_AHB_SETUP_5__STALL_WLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define QSPI_REMOTE_AHB_SETUP_5__STALL_WLE__RESET_VALUE 0x00000020U +/** @} */ + +/* macros for field stall_we2pp */ +/** + * @defgroup at_apb_qspi_regs_core_stall_we2pp_field stall_we2pp_field + * @brief macros for field stall_we2pp + * @details wen or wle to pp depending on check_wle setting + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP_5__STALL_WE2PP__SHIFT 20 +#define QSPI_REMOTE_AHB_SETUP_5__STALL_WE2PP__WIDTH 10 +#define QSPI_REMOTE_AHB_SETUP_5__STALL_WE2PP__MASK 0x3ff00000U +#define QSPI_REMOTE_AHB_SETUP_5__STALL_WE2PP__READ(src) \ + (((uint32_t)(src)\ + & 0x3ff00000U) >> 20) +#define QSPI_REMOTE_AHB_SETUP_5__STALL_WE2PP__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x3ff00000U) +#define QSPI_REMOTE_AHB_SETUP_5__STALL_WE2PP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define QSPI_REMOTE_AHB_SETUP_5__STALL_WE2PP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define QSPI_REMOTE_AHB_SETUP_5__STALL_WE2PP__RESET_VALUE 0x00000020U +/** @} */ +#define QSPI_REMOTE_AHB_SETUP_5__TYPE uint32_t +#define QSPI_REMOTE_AHB_SETUP_5__READ 0x3fffffffU +#define QSPI_REMOTE_AHB_SETUP_5__WRITE 0x3fffffffU +#define QSPI_REMOTE_AHB_SETUP_5__PRESERVED 0x00000000U +#define QSPI_REMOTE_AHB_SETUP_5__RESET_VALUE 0x02008200U + +#endif /* __QSPI_REMOTE_AHB_SETUP_5_MACRO__ */ + +/** @} end of remote_ahb_setup_5 */ + +/* macros for BlueprintGlobalNameSpace::QSPI_remote_ahb_setup_6 */ +/** + * @defgroup at_apb_qspi_regs_core_remote_ahb_setup_6 remote_ahb_setup_6 + * @brief Contains register fields associated with remote_ahb_setup_6. definitions. + * @{ + */ +#ifndef __QSPI_REMOTE_AHB_SETUP_6_MACRO__ +#define __QSPI_REMOTE_AHB_SETUP_6_MACRO__ + +/* macros for field se_stall_wip */ +/** + * @defgroup at_apb_qspi_regs_core_se_stall_wip_field se_stall_wip_field + * @brief macros for field se_stall_wip + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP_6__SE_STALL_WIP__SHIFT 0 +#define QSPI_REMOTE_AHB_SETUP_6__SE_STALL_WIP__WIDTH 16 +#define QSPI_REMOTE_AHB_SETUP_6__SE_STALL_WIP__MASK 0x0000ffffU +#define QSPI_REMOTE_AHB_SETUP_6__SE_STALL_WIP__READ(src) \ + ((uint32_t)(src)\ + & 0x0000ffffU) +#define QSPI_REMOTE_AHB_SETUP_6__SE_STALL_WIP__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000ffffU) +#define QSPI_REMOTE_AHB_SETUP_6__SE_STALL_WIP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define QSPI_REMOTE_AHB_SETUP_6__SE_STALL_WIP__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000ffffU))) +#define QSPI_REMOTE_AHB_SETUP_6__SE_STALL_WIP__RESET_VALUE 0x00001fffU +/** @} */ +#define QSPI_REMOTE_AHB_SETUP_6__TYPE uint32_t +#define QSPI_REMOTE_AHB_SETUP_6__READ 0x0000ffffU +#define QSPI_REMOTE_AHB_SETUP_6__WRITE 0x0000ffffU +#define QSPI_REMOTE_AHB_SETUP_6__PRESERVED 0x00000000U +#define QSPI_REMOTE_AHB_SETUP_6__RESET_VALUE 0x00001fffU + +#endif /* __QSPI_REMOTE_AHB_SETUP_6_MACRO__ */ + +/** @} end of remote_ahb_setup_6 */ + +/* macros for BlueprintGlobalNameSpace::QSPI_remote_ahb_setup_7 */ +/** + * @defgroup at_apb_qspi_regs_core_remote_ahb_setup_7 remote_ahb_setup_7 + * @brief Contains register fields associated with remote_ahb_setup_7. definitions. + * @{ + */ +#ifndef __QSPI_REMOTE_AHB_SETUP_7_MACRO__ +#define __QSPI_REMOTE_AHB_SETUP_7_MACRO__ + +/* macros for field remap_table */ +/** + * @defgroup at_apb_qspi_regs_core_remap_table_field remap_table_field + * @brief macros for field remap_table + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_TABLE__SHIFT 0 +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_TABLE__WIDTH 24 +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_TABLE__MASK 0x00ffffffU +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_TABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00ffffffU) +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_TABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00ffffffU) +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_TABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((uint32_t)(src) &\ + 0x00ffffffU) +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_TABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00ffffffU))) +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_TABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field remap_msb_loc_sub2 */ +/** + * @defgroup at_apb_qspi_regs_core_remap_msb_loc_sub2_field remap_msb_loc_sub2_field + * @brief macros for field remap_msb_loc_sub2 + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_MSB_LOC_SUB2__SHIFT 24 +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_MSB_LOC_SUB2__WIDTH 5 +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_MSB_LOC_SUB2__MASK 0x1f000000U +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_MSB_LOC_SUB2__READ(src) \ + (((uint32_t)(src)\ + & 0x1f000000U) >> 24) +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_MSB_LOC_SUB2__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x1f000000U) +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_MSB_LOC_SUB2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1f000000U) | (((uint32_t)(src) <<\ + 24) & 0x1f000000U) +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_MSB_LOC_SUB2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x1f000000U))) +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_MSB_LOC_SUB2__RESET_VALUE 0x00000015U +/** @} */ + +/* macros for field remap_legacy */ +/** + * @defgroup at_apb_qspi_regs_core_remap_legacy_field remap_legacy_field + * @brief macros for field remap_legacy + * @{ + */ +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_LEGACY__SHIFT 29 +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_LEGACY__WIDTH 1 +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_LEGACY__MASK 0x20000000U +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_LEGACY__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_LEGACY__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_LEGACY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_LEGACY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_LEGACY__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_LEGACY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define QSPI_REMOTE_AHB_SETUP_7__REMAP_LEGACY__RESET_VALUE 0x00000001U +/** @} */ +#define QSPI_REMOTE_AHB_SETUP_7__TYPE uint32_t +#define QSPI_REMOTE_AHB_SETUP_7__READ 0x3fffffffU +#define QSPI_REMOTE_AHB_SETUP_7__WRITE 0x3fffffffU +#define QSPI_REMOTE_AHB_SETUP_7__PRESERVED 0x00000000U +#define QSPI_REMOTE_AHB_SETUP_7__RESET_VALUE 0x35000000U + +#endif /* __QSPI_REMOTE_AHB_SETUP_7_MACRO__ */ + +/** @} end of remote_ahb_setup_7 */ + +/* macros for BlueprintGlobalNameSpace::QSPI_remote_ahb_wle_cnt */ +/** + * @defgroup at_apb_qspi_regs_core_remote_ahb_wle_cnt remote_ahb_wle_cnt + * @brief Contains register fields associated with remote_ahb_wle_cnt. definitions. + * @{ + */ +#ifndef __QSPI_REMOTE_AHB_WLE_CNT_MACRO__ +#define __QSPI_REMOTE_AHB_WLE_CNT_MACRO__ + +/* macros for field wle_cnt */ +/** + * @defgroup at_apb_qspi_regs_core_wle_cnt_field wle_cnt_field + * @brief macros for field wle_cnt + * @details number of wle checks before it is true. + * @{ + */ +#define QSPI_REMOTE_AHB_WLE_CNT__WLE_CNT__SHIFT 0 +#define QSPI_REMOTE_AHB_WLE_CNT__WLE_CNT__WIDTH 10 +#define QSPI_REMOTE_AHB_WLE_CNT__WLE_CNT__MASK 0x000003ffU +#define QSPI_REMOTE_AHB_WLE_CNT__WLE_CNT__READ(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define QSPI_REMOTE_AHB_WLE_CNT__WLE_CNT__RESET_VALUE 0x00000000U +/** @} */ +#define QSPI_REMOTE_AHB_WLE_CNT__TYPE uint32_t +#define QSPI_REMOTE_AHB_WLE_CNT__READ 0x000003ffU +#define QSPI_REMOTE_AHB_WLE_CNT__PRESERVED 0x00000000U +#define QSPI_REMOTE_AHB_WLE_CNT__RESET_VALUE 0x00000000U + +#endif /* __QSPI_REMOTE_AHB_WLE_CNT_MACRO__ */ + +/** @} end of remote_ahb_wle_cnt */ + +/* macros for BlueprintGlobalNameSpace::QSPI_remote_ahb_wip_cnt */ +/** + * @defgroup at_apb_qspi_regs_core_remote_ahb_wip_cnt remote_ahb_wip_cnt + * @brief Contains register fields associated with remote_ahb_wip_cnt. definitions. + * @{ + */ +#ifndef __QSPI_REMOTE_AHB_WIP_CNT_MACRO__ +#define __QSPI_REMOTE_AHB_WIP_CNT_MACRO__ + +/* macros for field wip_cnt */ +/** + * @defgroup at_apb_qspi_regs_core_wip_cnt_field wip_cnt_field + * @brief macros for field wip_cnt + * @details number of wip checks before it is over. + * @{ + */ +#define QSPI_REMOTE_AHB_WIP_CNT__WIP_CNT__SHIFT 0 +#define QSPI_REMOTE_AHB_WIP_CNT__WIP_CNT__WIDTH 10 +#define QSPI_REMOTE_AHB_WIP_CNT__WIP_CNT__MASK 0x000003ffU +#define QSPI_REMOTE_AHB_WIP_CNT__WIP_CNT__READ(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define QSPI_REMOTE_AHB_WIP_CNT__WIP_CNT__RESET_VALUE 0x00000000U +/** @} */ +#define QSPI_REMOTE_AHB_WIP_CNT__TYPE uint32_t +#define QSPI_REMOTE_AHB_WIP_CNT__READ 0x000003ffU +#define QSPI_REMOTE_AHB_WIP_CNT__PRESERVED 0x00000000U +#define QSPI_REMOTE_AHB_WIP_CNT__RESET_VALUE 0x00000000U + +#endif /* __QSPI_REMOTE_AHB_WIP_CNT_MACRO__ */ + +/** @} end of remote_ahb_wip_cnt */ + +/* macros for BlueprintGlobalNameSpace::QSPI_remote_ahb_dbg0 */ +/** + * @defgroup at_apb_qspi_regs_core_remote_ahb_dbg0 remote_ahb_dbg0 + * @brief Contains register fields associated with remote_ahb_dbg0. definitions. + * @{ + */ +#ifndef __QSPI_REMOTE_AHB_DBG0_MACRO__ +#define __QSPI_REMOTE_AHB_DBG0_MACRO__ + +/* macros for field dbg0 */ +/** + * @defgroup at_apb_qspi_regs_core_dbg0_field dbg0_field + * @brief macros for field dbg0 + * @{ + */ +#define QSPI_REMOTE_AHB_DBG0__DBG0__SHIFT 0 +#define QSPI_REMOTE_AHB_DBG0__DBG0__WIDTH 32 +#define QSPI_REMOTE_AHB_DBG0__DBG0__MASK 0xffffffffU +#define QSPI_REMOTE_AHB_DBG0__DBG0__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define QSPI_REMOTE_AHB_DBG0__DBG0__RESET_VALUE 0x00000000U +/** @} */ +#define QSPI_REMOTE_AHB_DBG0__TYPE uint32_t +#define QSPI_REMOTE_AHB_DBG0__READ 0xffffffffU +#define QSPI_REMOTE_AHB_DBG0__PRESERVED 0x00000000U +#define QSPI_REMOTE_AHB_DBG0__RESET_VALUE 0x00000000U + +#endif /* __QSPI_REMOTE_AHB_DBG0_MACRO__ */ + +/** @} end of remote_ahb_dbg0 */ + +/* macros for BlueprintGlobalNameSpace::QSPI_remote_ahb_dbg1 */ +/** + * @defgroup at_apb_qspi_regs_core_remote_ahb_dbg1 remote_ahb_dbg1 + * @brief Contains register fields associated with remote_ahb_dbg1. definitions. + * @{ + */ +#ifndef __QSPI_REMOTE_AHB_DBG1_MACRO__ +#define __QSPI_REMOTE_AHB_DBG1_MACRO__ + +/* macros for field dbg1 */ +/** + * @defgroup at_apb_qspi_regs_core_dbg1_field dbg1_field + * @brief macros for field dbg1 + * @{ + */ +#define QSPI_REMOTE_AHB_DBG1__DBG1__SHIFT 0 +#define QSPI_REMOTE_AHB_DBG1__DBG1__WIDTH 32 +#define QSPI_REMOTE_AHB_DBG1__DBG1__MASK 0xffffffffU +#define QSPI_REMOTE_AHB_DBG1__DBG1__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define QSPI_REMOTE_AHB_DBG1__DBG1__RESET_VALUE 0x00000000U +/** @} */ +#define QSPI_REMOTE_AHB_DBG1__TYPE uint32_t +#define QSPI_REMOTE_AHB_DBG1__READ 0xffffffffU +#define QSPI_REMOTE_AHB_DBG1__PRESERVED 0x00000000U +#define QSPI_REMOTE_AHB_DBG1__RESET_VALUE 0x00000000U + +#endif /* __QSPI_REMOTE_AHB_DBG1_MACRO__ */ + +/** @} end of remote_ahb_dbg1 */ + +/* macros for BlueprintGlobalNameSpace::QSPI_remote_ahb_dbg2 */ +/** + * @defgroup at_apb_qspi_regs_core_remote_ahb_dbg2 remote_ahb_dbg2 + * @brief Contains register fields associated with remote_ahb_dbg2. definitions. + * @{ + */ +#ifndef __QSPI_REMOTE_AHB_DBG2_MACRO__ +#define __QSPI_REMOTE_AHB_DBG2_MACRO__ + +/* macros for field dbg2 */ +/** + * @defgroup at_apb_qspi_regs_core_dbg2_field dbg2_field + * @brief macros for field dbg2 + * @{ + */ +#define QSPI_REMOTE_AHB_DBG2__DBG2__SHIFT 0 +#define QSPI_REMOTE_AHB_DBG2__DBG2__WIDTH 32 +#define QSPI_REMOTE_AHB_DBG2__DBG2__MASK 0xffffffffU +#define QSPI_REMOTE_AHB_DBG2__DBG2__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define QSPI_REMOTE_AHB_DBG2__DBG2__RESET_VALUE 0x00000000U +/** @} */ +#define QSPI_REMOTE_AHB_DBG2__TYPE uint32_t +#define QSPI_REMOTE_AHB_DBG2__READ 0xffffffffU +#define QSPI_REMOTE_AHB_DBG2__PRESERVED 0x00000000U +#define QSPI_REMOTE_AHB_DBG2__RESET_VALUE 0x00000000U + +#endif /* __QSPI_REMOTE_AHB_DBG2_MACRO__ */ + +/** @} end of remote_ahb_dbg2 */ + +/* macros for BlueprintGlobalNameSpace::QSPI_core_id */ +/** + * @defgroup at_apb_qspi_regs_core_core_id core_id + * @brief Contains register fields associated with core_id. definitions. + * @{ + */ +#ifndef __QSPI_CORE_ID_MACRO__ +#define __QSPI_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_qspi_regs_core_id_field id_field + * @brief macros for field id + * @details QSPI in ASCII + * @{ + */ +#define QSPI_CORE_ID__ID__SHIFT 0 +#define QSPI_CORE_ID__ID__WIDTH 32 +#define QSPI_CORE_ID__ID__MASK 0xffffffffU +#define QSPI_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define QSPI_CORE_ID__ID__RESET_VALUE 0x51535049U +/** @} */ +#define QSPI_CORE_ID__TYPE uint32_t +#define QSPI_CORE_ID__READ 0xffffffffU +#define QSPI_CORE_ID__PRESERVED 0x00000000U +#define QSPI_CORE_ID__RESET_VALUE 0x51535049U + +#endif /* __QSPI_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of AT_APB_QSPI_REGS_CORE */ +#endif /* __REG_AT_APB_QSPI_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_apb_rcos_cal_regs_core_macro.h b/ATM33xx-5/include/reg/at_apb_rcos_cal_regs_core_macro.h new file mode 100644 index 0000000..93545ee --- /dev/null +++ b/ATM33xx-5/include/reg/at_apb_rcos_cal_regs_core_macro.h @@ -0,0 +1,672 @@ +/* */ +/* File: at_apb_rcos_cal_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_apb_rcos_cal_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_APB_RCOS_CAL_REGS_CORE_H__ +#define __REG_AT_APB_RCOS_CAL_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_APB_RCOS_CAL_REGS_CORE at_apb_rcos_cal_regs_core + * @ingroup AT_REG + * @brief at_apb_rcos_cal_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::RCOS_CAL_cal_ctrl */ +/** + * @defgroup at_apb_rcos_cal_regs_core_cal_ctrl cal_ctrl + * @brief Contains register fields associated with cal_ctrl. definitions. + * @{ + */ +#ifndef __RCOS_CAL_CAL_CTRL_MACRO__ +#define __RCOS_CAL_CAL_CTRL_MACRO__ + +/* macros for field sw_cal */ +/** + * @defgroup at_apb_rcos_cal_regs_core_sw_cal_field sw_cal_field + * @brief macros for field sw_cal + * @details rising edge starts SW cal, falling edge terminates cal if cal is not done; best to leave it on once set. + * @{ + */ +#define RCOS_CAL_CAL_CTRL__SW_CAL__SHIFT 0 +#define RCOS_CAL_CAL_CTRL__SW_CAL__WIDTH 1 +#define RCOS_CAL_CAL_CTRL__SW_CAL__MASK 0x00000001U +#define RCOS_CAL_CAL_CTRL__SW_CAL__READ(src) ((uint32_t)(src) & 0x00000001U) +#define RCOS_CAL_CAL_CTRL__SW_CAL__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define RCOS_CAL_CAL_CTRL__SW_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define RCOS_CAL_CAL_CTRL__SW_CAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define RCOS_CAL_CAL_CTRL__SW_CAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define RCOS_CAL_CAL_CTRL__SW_CAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define RCOS_CAL_CAL_CTRL__SW_CAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hw_cal_sel */ +/** + * @defgroup at_apb_rcos_cal_regs_core_hw_cal_sel_field hw_cal_sel_field + * @brief macros for field hw_cal_sel + * @details 1=choose cal from HW; 0=choose cal from SW + * @{ + */ +#define RCOS_CAL_CAL_CTRL__HW_CAL_SEL__SHIFT 1 +#define RCOS_CAL_CAL_CTRL__HW_CAL_SEL__WIDTH 1 +#define RCOS_CAL_CAL_CTRL__HW_CAL_SEL__MASK 0x00000002U +#define RCOS_CAL_CAL_CTRL__HW_CAL_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define RCOS_CAL_CAL_CTRL__HW_CAL_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define RCOS_CAL_CAL_CTRL__HW_CAL_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define RCOS_CAL_CAL_CTRL__HW_CAL_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define RCOS_CAL_CAL_CTRL__HW_CAL_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define RCOS_CAL_CAL_CTRL__HW_CAL_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define RCOS_CAL_CAL_CTRL__HW_CAL_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define RCOS_CAL_CAL_CTRL__TYPE uint32_t +#define RCOS_CAL_CAL_CTRL__READ 0x00000003U +#define RCOS_CAL_CAL_CTRL__WRITE 0x00000003U +#define RCOS_CAL_CAL_CTRL__PRESERVED 0x00000000U +#define RCOS_CAL_CAL_CTRL__RESET_VALUE 0x00000000U + +#endif /* __RCOS_CAL_CAL_CTRL_MACRO__ */ + +/** @} end of cal_ctrl */ + +/* macros for BlueprintGlobalNameSpace::RCOS_CAL_slow_clk_set */ +/** + * @defgroup at_apb_rcos_cal_regs_core_slow_clk_set slow_clk_set + * @brief Contains register fields associated with slow_clk_set. definitions. + * @{ + */ +#ifndef __RCOS_CAL_SLOW_CLK_SET_MACRO__ +#define __RCOS_CAL_SLOW_CLK_SET_MACRO__ + +/* macros for field slow_clk_set */ +/** + * @defgroup at_apb_rcos_cal_regs_core_slow_clk_set_field slow_clk_set_field + * @brief macros for field slow_clk_set + * @details set the number of cycles to run slow clock; counting stops when this number is reached or cal is pulled down. constraint: 1 <= slow_clk_set <= 63; if set 0, hardware will use 1. + * @{ + */ +#define RCOS_CAL_SLOW_CLK_SET__SLOW_CLK_SET__SHIFT 0 +#define RCOS_CAL_SLOW_CLK_SET__SLOW_CLK_SET__WIDTH 12 +#define RCOS_CAL_SLOW_CLK_SET__SLOW_CLK_SET__MASK 0x00000fffU +#define RCOS_CAL_SLOW_CLK_SET__SLOW_CLK_SET__READ(src) \ + ((uint32_t)(src)\ + & 0x00000fffU) +#define RCOS_CAL_SLOW_CLK_SET__SLOW_CLK_SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000fffU) +#define RCOS_CAL_SLOW_CLK_SET__SLOW_CLK_SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((uint32_t)(src) &\ + 0x00000fffU) +#define RCOS_CAL_SLOW_CLK_SET__SLOW_CLK_SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000fffU))) +#define RCOS_CAL_SLOW_CLK_SET__SLOW_CLK_SET__RESET_VALUE 0x00000064U +/** @} */ +#define RCOS_CAL_SLOW_CLK_SET__TYPE uint32_t +#define RCOS_CAL_SLOW_CLK_SET__READ 0x00000fffU +#define RCOS_CAL_SLOW_CLK_SET__WRITE 0x00000fffU +#define RCOS_CAL_SLOW_CLK_SET__PRESERVED 0x00000000U +#define RCOS_CAL_SLOW_CLK_SET__RESET_VALUE 0x00000064U + +#endif /* __RCOS_CAL_SLOW_CLK_SET_MACRO__ */ + +/** @} end of slow_clk_set */ + +/* macros for BlueprintGlobalNameSpace::RCOS_CAL_slow_clk_cnt */ +/** + * @defgroup at_apb_rcos_cal_regs_core_slow_clk_cnt slow_clk_cnt + * @brief Contains register fields associated with slow_clk_cnt. definitions. + * @{ + */ +#ifndef __RCOS_CAL_SLOW_CLK_CNT_MACRO__ +#define __RCOS_CAL_SLOW_CLK_CNT_MACRO__ + +/* macros for field slow_clk_cnt */ +/** + * @defgroup at_apb_rcos_cal_regs_core_slow_clk_cnt_field slow_clk_cnt_field + * @brief macros for field slow_clk_cnt + * @details number of cycles counted by slow clock. + * @{ + */ +#define RCOS_CAL_SLOW_CLK_CNT__SLOW_CLK_CNT__SHIFT 0 +#define RCOS_CAL_SLOW_CLK_CNT__SLOW_CLK_CNT__WIDTH 12 +#define RCOS_CAL_SLOW_CLK_CNT__SLOW_CLK_CNT__MASK 0x00000fffU +#define RCOS_CAL_SLOW_CLK_CNT__SLOW_CLK_CNT__READ(src) \ + ((uint32_t)(src)\ + & 0x00000fffU) +#define RCOS_CAL_SLOW_CLK_CNT__SLOW_CLK_CNT__RESET_VALUE 0x00000000U +/** @} */ +#define RCOS_CAL_SLOW_CLK_CNT__TYPE uint32_t +#define RCOS_CAL_SLOW_CLK_CNT__READ 0x00000fffU +#define RCOS_CAL_SLOW_CLK_CNT__PRESERVED 0x00000000U +#define RCOS_CAL_SLOW_CLK_CNT__RESET_VALUE 0x00000000U + +#endif /* __RCOS_CAL_SLOW_CLK_CNT_MACRO__ */ + +/** @} end of slow_clk_cnt */ + +/* macros for BlueprintGlobalNameSpace::RCOS_CAL_fast_clk_cnt */ +/** + * @defgroup at_apb_rcos_cal_regs_core_fast_clk_cnt fast_clk_cnt + * @brief Contains register fields associated with fast_clk_cnt. definitions. + * @{ + */ +#ifndef __RCOS_CAL_FAST_CLK_CNT_MACRO__ +#define __RCOS_CAL_FAST_CLK_CNT_MACRO__ + +/* macros for field fast_clk_cnt */ +/** + * @defgroup at_apb_rcos_cal_regs_core_fast_clk_cnt_field fast_clk_cnt_field + * @brief macros for field fast_clk_cnt + * @details number of cycles counted by fast clock. 10 bits more than slow_clk_cnt/set because fast clock is 1000 times faster. + * @{ + */ +#define RCOS_CAL_FAST_CLK_CNT__FAST_CLK_CNT__SHIFT 0 +#define RCOS_CAL_FAST_CLK_CNT__FAST_CLK_CNT__WIDTH 22 +#define RCOS_CAL_FAST_CLK_CNT__FAST_CLK_CNT__MASK 0x003fffffU +#define RCOS_CAL_FAST_CLK_CNT__FAST_CLK_CNT__READ(src) \ + ((uint32_t)(src)\ + & 0x003fffffU) +#define RCOS_CAL_FAST_CLK_CNT__FAST_CLK_CNT__RESET_VALUE 0x00000000U +/** @} */ +#define RCOS_CAL_FAST_CLK_CNT__TYPE uint32_t +#define RCOS_CAL_FAST_CLK_CNT__READ 0x003fffffU +#define RCOS_CAL_FAST_CLK_CNT__PRESERVED 0x00000000U +#define RCOS_CAL_FAST_CLK_CNT__RESET_VALUE 0x00000000U + +#endif /* __RCOS_CAL_FAST_CLK_CNT_MACRO__ */ + +/** @} end of fast_clk_cnt */ + +/* macros for BlueprintGlobalNameSpace::RCOS_CAL_source_clk_sel */ +/** + * @defgroup at_apb_rcos_cal_regs_core_source_clk_sel source_clk_sel + * @brief Contains register fields associated with source_clk_sel. definitions. + * @{ + */ +#ifndef __RCOS_CAL_SOURCE_CLK_SEL_MACRO__ +#define __RCOS_CAL_SOURCE_CLK_SEL_MACRO__ + +/* macros for field slow_clk_sel */ +/** + * @defgroup at_apb_rcos_cal_regs_core_slow_clk_sel_field slow_clk_sel_field + * @brief macros for field slow_clk_sel + * @details 0=slow clk source is clk_lpc;1=slow clk source is clk_calfc + * @{ + */ +#define RCOS_CAL_SOURCE_CLK_SEL__SLOW_CLK_SEL__SHIFT 0 +#define RCOS_CAL_SOURCE_CLK_SEL__SLOW_CLK_SEL__WIDTH 1 +#define RCOS_CAL_SOURCE_CLK_SEL__SLOW_CLK_SEL__MASK 0x00000001U +#define RCOS_CAL_SOURCE_CLK_SEL__SLOW_CLK_SEL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RCOS_CAL_SOURCE_CLK_SEL__SLOW_CLK_SEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RCOS_CAL_SOURCE_CLK_SEL__SLOW_CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define RCOS_CAL_SOURCE_CLK_SEL__SLOW_CLK_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define RCOS_CAL_SOURCE_CLK_SEL__SLOW_CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define RCOS_CAL_SOURCE_CLK_SEL__SLOW_CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define RCOS_CAL_SOURCE_CLK_SEL__SLOW_CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fast_clk_sel */ +/** + * @defgroup at_apb_rcos_cal_regs_core_fast_clk_sel_field fast_clk_sel_field + * @brief macros for field fast_clk_sel + * @details 0=fast clk source is PCLk; 1=fast clk source is clk_calfc + * @{ + */ +#define RCOS_CAL_SOURCE_CLK_SEL__FAST_CLK_SEL__SHIFT 1 +#define RCOS_CAL_SOURCE_CLK_SEL__FAST_CLK_SEL__WIDTH 1 +#define RCOS_CAL_SOURCE_CLK_SEL__FAST_CLK_SEL__MASK 0x00000002U +#define RCOS_CAL_SOURCE_CLK_SEL__FAST_CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define RCOS_CAL_SOURCE_CLK_SEL__FAST_CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define RCOS_CAL_SOURCE_CLK_SEL__FAST_CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define RCOS_CAL_SOURCE_CLK_SEL__FAST_CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define RCOS_CAL_SOURCE_CLK_SEL__FAST_CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define RCOS_CAL_SOURCE_CLK_SEL__FAST_CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define RCOS_CAL_SOURCE_CLK_SEL__FAST_CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define RCOS_CAL_SOURCE_CLK_SEL__TYPE uint32_t +#define RCOS_CAL_SOURCE_CLK_SEL__READ 0x00000003U +#define RCOS_CAL_SOURCE_CLK_SEL__WRITE 0x00000003U +#define RCOS_CAL_SOURCE_CLK_SEL__PRESERVED 0x00000000U +#define RCOS_CAL_SOURCE_CLK_SEL__RESET_VALUE 0x00000000U + +#endif /* __RCOS_CAL_SOURCE_CLK_SEL_MACRO__ */ + +/** @} end of source_clk_sel */ + +/* macros for BlueprintGlobalNameSpace::RCOS_CAL_force_reset */ +/** + * @defgroup at_apb_rcos_cal_regs_core_force_reset force_reset + * @brief Contains register fields associated with force_reset. definitions. + * @{ + */ +#ifndef __RCOS_CAL_FORCE_RESET_MACRO__ +#define __RCOS_CAL_FORCE_RESET_MACRO__ + +/* macros for field force_reset */ +/** + * @defgroup at_apb_rcos_cal_regs_core_force_reset_field force_reset_field + * @brief macros for field force_reset + * @details 1=apply force reset to fast domain and slow domain. 0=release force reset. + * @{ + */ +#define RCOS_CAL_FORCE_RESET__FORCE_RESET__SHIFT 0 +#define RCOS_CAL_FORCE_RESET__FORCE_RESET__WIDTH 1 +#define RCOS_CAL_FORCE_RESET__FORCE_RESET__MASK 0x00000001U +#define RCOS_CAL_FORCE_RESET__FORCE_RESET__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RCOS_CAL_FORCE_RESET__FORCE_RESET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RCOS_CAL_FORCE_RESET__FORCE_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define RCOS_CAL_FORCE_RESET__FORCE_RESET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define RCOS_CAL_FORCE_RESET__FORCE_RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define RCOS_CAL_FORCE_RESET__FORCE_RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define RCOS_CAL_FORCE_RESET__FORCE_RESET__RESET_VALUE 0x00000000U +/** @} */ +#define RCOS_CAL_FORCE_RESET__TYPE uint32_t +#define RCOS_CAL_FORCE_RESET__READ 0x00000001U +#define RCOS_CAL_FORCE_RESET__WRITE 0x00000001U +#define RCOS_CAL_FORCE_RESET__PRESERVED 0x00000000U +#define RCOS_CAL_FORCE_RESET__RESET_VALUE 0x00000000U + +#endif /* __RCOS_CAL_FORCE_RESET_MACRO__ */ + +/** @} end of force_reset */ + +/* macros for BlueprintGlobalNameSpace::RCOS_CAL_stat */ +/** + * @defgroup at_apb_rcos_cal_regs_core_stat stat + * @brief Contains register fields associated with stat. definitions. + * @{ + */ +#ifndef __RCOS_CAL_STAT_MACRO__ +#define __RCOS_CAL_STAT_MACRO__ + +/* macros for field running */ +/** + * @defgroup at_apb_rcos_cal_regs_core_running_field running_field + * @brief macros for field running + * @{ + */ +#define RCOS_CAL_STAT__RUNNING__SHIFT 0 +#define RCOS_CAL_STAT__RUNNING__WIDTH 1 +#define RCOS_CAL_STAT__RUNNING__MASK 0x00000001U +#define RCOS_CAL_STAT__RUNNING__READ(src) ((uint32_t)(src) & 0x00000001U) +#define RCOS_CAL_STAT__RUNNING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define RCOS_CAL_STAT__RUNNING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define RCOS_CAL_STAT__RUNNING__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field high_precision_run */ +/** + * @defgroup at_apb_rcos_cal_regs_core_high_precision_run_field high_precision_run_field + * @brief macros for field high_precision_run + * @details 1=high-precisioned clock was used at the beginning of cal; 0=low precisioned clock + * @{ + */ +#define RCOS_CAL_STAT__HIGH_PRECISION_RUN__SHIFT 1 +#define RCOS_CAL_STAT__HIGH_PRECISION_RUN__WIDTH 1 +#define RCOS_CAL_STAT__HIGH_PRECISION_RUN__MASK 0x00000002U +#define RCOS_CAL_STAT__HIGH_PRECISION_RUN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define RCOS_CAL_STAT__HIGH_PRECISION_RUN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define RCOS_CAL_STAT__HIGH_PRECISION_RUN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define RCOS_CAL_STAT__HIGH_PRECISION_RUN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field slow_domain_reset_stat */ +/** + * @defgroup at_apb_rcos_cal_regs_core_slow_domain_reset_stat_field slow_domain_reset_stat_field + * @brief macros for field slow_domain_reset_stat + * @details 1=slow_clk domain is still in reset; don't triger cal + * @{ + */ +#define RCOS_CAL_STAT__SLOW_DOMAIN_RESET_STAT__SHIFT 2 +#define RCOS_CAL_STAT__SLOW_DOMAIN_RESET_STAT__WIDTH 1 +#define RCOS_CAL_STAT__SLOW_DOMAIN_RESET_STAT__MASK 0x00000004U +#define RCOS_CAL_STAT__SLOW_DOMAIN_RESET_STAT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define RCOS_CAL_STAT__SLOW_DOMAIN_RESET_STAT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define RCOS_CAL_STAT__SLOW_DOMAIN_RESET_STAT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define RCOS_CAL_STAT__SLOW_DOMAIN_RESET_STAT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fast_domain_reset_stat */ +/** + * @defgroup at_apb_rcos_cal_regs_core_fast_domain_reset_stat_field fast_domain_reset_stat_field + * @brief macros for field fast_domain_reset_stat + * @details 1=fast_clk domain is still in reset; don't triger cal + * @{ + */ +#define RCOS_CAL_STAT__FAST_DOMAIN_RESET_STAT__SHIFT 3 +#define RCOS_CAL_STAT__FAST_DOMAIN_RESET_STAT__WIDTH 1 +#define RCOS_CAL_STAT__FAST_DOMAIN_RESET_STAT__MASK 0x00000008U +#define RCOS_CAL_STAT__FAST_DOMAIN_RESET_STAT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define RCOS_CAL_STAT__FAST_DOMAIN_RESET_STAT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define RCOS_CAL_STAT__FAST_DOMAIN_RESET_STAT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define RCOS_CAL_STAT__FAST_DOMAIN_RESET_STAT__RESET_VALUE 0x00000000U +/** @} */ +#define RCOS_CAL_STAT__TYPE uint32_t +#define RCOS_CAL_STAT__READ 0x0000000fU +#define RCOS_CAL_STAT__PRESERVED 0x00000000U +#define RCOS_CAL_STAT__RESET_VALUE 0x00000000U + +#endif /* __RCOS_CAL_STAT_MACRO__ */ + +/** @} end of stat */ + +/* macros for BlueprintGlobalNameSpace::RCOS_CAL_interrupt_status */ +/** + * @defgroup at_apb_rcos_cal_regs_core_interrupt_status interrupt_status + * @brief Contains register fields associated with interrupt_status. definitions. + * @{ + */ +#ifndef __RCOS_CAL_INTERRUPT_STATUS_MACRO__ +#define __RCOS_CAL_INTERRUPT_STATUS_MACRO__ + +/* macros for field rcos_done */ +/** + * @defgroup at_apb_rcos_cal_regs_core_rcos_done_field rcos_done_field + * @brief macros for field rcos_done + * @{ + */ +#define RCOS_CAL_INTERRUPT_STATUS__RCOS_DONE__SHIFT 0 +#define RCOS_CAL_INTERRUPT_STATUS__RCOS_DONE__WIDTH 1 +#define RCOS_CAL_INTERRUPT_STATUS__RCOS_DONE__MASK 0x00000001U +#define RCOS_CAL_INTERRUPT_STATUS__RCOS_DONE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RCOS_CAL_INTERRUPT_STATUS__RCOS_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define RCOS_CAL_INTERRUPT_STATUS__RCOS_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define RCOS_CAL_INTERRUPT_STATUS__RCOS_DONE__RESET_VALUE 0x00000000U +/** @} */ +#define RCOS_CAL_INTERRUPT_STATUS__TYPE uint32_t +#define RCOS_CAL_INTERRUPT_STATUS__READ 0x00000001U +#define RCOS_CAL_INTERRUPT_STATUS__PRESERVED 0x00000000U +#define RCOS_CAL_INTERRUPT_STATUS__RESET_VALUE 0x00000000U + +#endif /* __RCOS_CAL_INTERRUPT_STATUS_MACRO__ */ + +/** @} end of interrupt_status */ + +/* macros for BlueprintGlobalNameSpace::RCOS_CAL_interrupt_mask */ +/** + * @defgroup at_apb_rcos_cal_regs_core_interrupt_mask interrupt_mask + * @brief Contains register fields associated with interrupt_mask. definitions. + * @{ + */ +#ifndef __RCOS_CAL_INTERRUPT_MASK_MACRO__ +#define __RCOS_CAL_INTERRUPT_MASK_MACRO__ + +/* macros for field intrpt_mask */ +/** + * @defgroup at_apb_rcos_cal_regs_core_intrpt_mask_field intrpt_mask_field + * @brief macros for field intrpt_mask + * @details if nth bit set, the nth interrupt source is allowed to propogate to core's interrupt + * @{ + */ +#define RCOS_CAL_INTERRUPT_MASK__INTRPT_MASK__SHIFT 0 +#define RCOS_CAL_INTERRUPT_MASK__INTRPT_MASK__WIDTH 1 +#define RCOS_CAL_INTERRUPT_MASK__INTRPT_MASK__MASK 0x00000001U +#define RCOS_CAL_INTERRUPT_MASK__INTRPT_MASK__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RCOS_CAL_INTERRUPT_MASK__INTRPT_MASK__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RCOS_CAL_INTERRUPT_MASK__INTRPT_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define RCOS_CAL_INTERRUPT_MASK__INTRPT_MASK__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define RCOS_CAL_INTERRUPT_MASK__INTRPT_MASK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define RCOS_CAL_INTERRUPT_MASK__INTRPT_MASK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define RCOS_CAL_INTERRUPT_MASK__INTRPT_MASK__RESET_VALUE 0x00000001U +/** @} */ +#define RCOS_CAL_INTERRUPT_MASK__TYPE uint32_t +#define RCOS_CAL_INTERRUPT_MASK__READ 0x00000001U +#define RCOS_CAL_INTERRUPT_MASK__WRITE 0x00000001U +#define RCOS_CAL_INTERRUPT_MASK__PRESERVED 0x00000000U +#define RCOS_CAL_INTERRUPT_MASK__RESET_VALUE 0x00000001U + +#endif /* __RCOS_CAL_INTERRUPT_MASK_MACRO__ */ + +/** @} end of interrupt_mask */ + +/* macros for BlueprintGlobalNameSpace::RCOS_CAL_set_interrupt */ +/** + * @defgroup at_apb_rcos_cal_regs_core_set_interrupt set_interrupt + * @brief Contains register fields associated with set_interrupt. definitions. + * @{ + */ +#ifndef __RCOS_CAL_SET_INTERRUPT_MACRO__ +#define __RCOS_CAL_SET_INTERRUPT_MACRO__ + +/* macros for field intrpt_set */ +/** + * @defgroup at_apb_rcos_cal_regs_core_intrpt_set_field intrpt_set_field + * @brief macros for field intrpt_set + * @details not self clearing + * @{ + */ +#define RCOS_CAL_SET_INTERRUPT__INTRPT_SET__SHIFT 0 +#define RCOS_CAL_SET_INTERRUPT__INTRPT_SET__WIDTH 1 +#define RCOS_CAL_SET_INTERRUPT__INTRPT_SET__MASK 0x00000001U +#define RCOS_CAL_SET_INTERRUPT__INTRPT_SET__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RCOS_CAL_SET_INTERRUPT__INTRPT_SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RCOS_CAL_SET_INTERRUPT__INTRPT_SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define RCOS_CAL_SET_INTERRUPT__INTRPT_SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define RCOS_CAL_SET_INTERRUPT__INTRPT_SET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define RCOS_CAL_SET_INTERRUPT__INTRPT_SET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define RCOS_CAL_SET_INTERRUPT__INTRPT_SET__RESET_VALUE 0x00000000U +/** @} */ +#define RCOS_CAL_SET_INTERRUPT__TYPE uint32_t +#define RCOS_CAL_SET_INTERRUPT__READ 0x00000001U +#define RCOS_CAL_SET_INTERRUPT__WRITE 0x00000001U +#define RCOS_CAL_SET_INTERRUPT__PRESERVED 0x00000000U +#define RCOS_CAL_SET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __RCOS_CAL_SET_INTERRUPT_MACRO__ */ + +/** @} end of set_interrupt */ + +/* macros for BlueprintGlobalNameSpace::RCOS_CAL_reset_interrupt */ +/** + * @defgroup at_apb_rcos_cal_regs_core_reset_interrupt reset_interrupt + * @brief Contains register fields associated with reset_interrupt. definitions. + * @{ + */ +#ifndef __RCOS_CAL_RESET_INTERRUPT_MACRO__ +#define __RCOS_CAL_RESET_INTERRUPT_MACRO__ + +/* macros for field intrpt_reset */ +/** + * @defgroup at_apb_rcos_cal_regs_core_intrpt_reset_field intrpt_reset_field + * @brief macros for field intrpt_reset + * @details not self clearing + * @{ + */ +#define RCOS_CAL_RESET_INTERRUPT__INTRPT_RESET__SHIFT 0 +#define RCOS_CAL_RESET_INTERRUPT__INTRPT_RESET__WIDTH 1 +#define RCOS_CAL_RESET_INTERRUPT__INTRPT_RESET__MASK 0x00000001U +#define RCOS_CAL_RESET_INTERRUPT__INTRPT_RESET__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RCOS_CAL_RESET_INTERRUPT__INTRPT_RESET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RCOS_CAL_RESET_INTERRUPT__INTRPT_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define RCOS_CAL_RESET_INTERRUPT__INTRPT_RESET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define RCOS_CAL_RESET_INTERRUPT__INTRPT_RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define RCOS_CAL_RESET_INTERRUPT__INTRPT_RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define RCOS_CAL_RESET_INTERRUPT__INTRPT_RESET__RESET_VALUE 0x00000000U +/** @} */ +#define RCOS_CAL_RESET_INTERRUPT__TYPE uint32_t +#define RCOS_CAL_RESET_INTERRUPT__READ 0x00000001U +#define RCOS_CAL_RESET_INTERRUPT__WRITE 0x00000001U +#define RCOS_CAL_RESET_INTERRUPT__PRESERVED 0x00000000U +#define RCOS_CAL_RESET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __RCOS_CAL_RESET_INTERRUPT_MACRO__ */ + +/** @} end of reset_interrupt */ + +/* macros for BlueprintGlobalNameSpace::RCOS_CAL_core_id */ +/** + * @defgroup at_apb_rcos_cal_regs_core_core_id core_id + * @brief Contains register fields associated with core_id. definitions. + * @{ + */ +#ifndef __RCOS_CAL_CORE_ID_MACRO__ +#define __RCOS_CAL_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_rcos_cal_regs_core_id_field id_field + * @brief macros for field id + * @details RCOS in ASCII + * @{ + */ +#define RCOS_CAL_CORE_ID__ID__SHIFT 0 +#define RCOS_CAL_CORE_ID__ID__WIDTH 32 +#define RCOS_CAL_CORE_ID__ID__MASK 0xffffffffU +#define RCOS_CAL_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define RCOS_CAL_CORE_ID__ID__RESET_VALUE 0x52434f53U +/** @} */ +#define RCOS_CAL_CORE_ID__TYPE uint32_t +#define RCOS_CAL_CORE_ID__READ 0xffffffffU +#define RCOS_CAL_CORE_ID__PRESERVED 0x00000000U +#define RCOS_CAL_CORE_ID__RESET_VALUE 0x52434f53U + +#endif /* __RCOS_CAL_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of AT_APB_RCOS_CAL_REGS_CORE */ +#endif /* __REG_AT_APB_RCOS_CAL_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_apb_shub_regs_core_macro.h b/ATM33xx-5/include/reg/at_apb_shub_regs_core_macro.h new file mode 100644 index 0000000..3baae1d --- /dev/null +++ b/ATM33xx-5/include/reg/at_apb_shub_regs_core_macro.h @@ -0,0 +1,13794 @@ +/* */ +/* File: at_apb_shub_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_apb_shub_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_APB_SHUB_REGS_CORE_H__ +#define __REG_AT_APB_SHUB_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_APB_SHUB_REGS_CORE at_apb_shub_regs_core + * @ingroup AT_REG + * @brief at_apb_shub_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::SHUB_setup0 */ +/** + * @defgroup at_apb_shub_regs_core_setup0 setup0 + * @brief Contains register fields associated with setup0. definitions. + * @{ + */ +#ifndef __SHUB_SETUP0_MACRO__ +#define __SHUB_SETUP0_MACRO__ + +/* macros for field go */ +/** + * @defgroup at_apb_shub_regs_core_go_field go_field + * @brief macros for field go + * @details not self reseting + * @{ + */ +#define SHUB_SETUP0__GO__SHIFT 0 +#define SHUB_SETUP0__GO__WIDTH 1 +#define SHUB_SETUP0__GO__MASK 0x00000001U +#define SHUB_SETUP0__GO__READ(src) ((uint32_t)(src) & 0x00000001U) +#define SHUB_SETUP0__GO__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define SHUB_SETUP0__GO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_SETUP0__GO__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define SHUB_SETUP0__GO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_SETUP0__GO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_SETUP0__GO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field breakout */ +/** + * @defgroup at_apb_shub_regs_core_breakout_field breakout_field + * @brief macros for field breakout + * @details useful for testing + * @{ + */ +#define SHUB_SETUP0__BREAKOUT__SHIFT 1 +#define SHUB_SETUP0__BREAKOUT__WIDTH 1 +#define SHUB_SETUP0__BREAKOUT__MASK 0x00000002U +#define SHUB_SETUP0__BREAKOUT__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define SHUB_SETUP0__BREAKOUT__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define SHUB_SETUP0__BREAKOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define SHUB_SETUP0__BREAKOUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define SHUB_SETUP0__BREAKOUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SHUB_SETUP0__BREAKOUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SHUB_SETUP0__BREAKOUT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field store_in_sram */ +/** + * @defgroup at_apb_shub_regs_core_store_in_sram_field store_in_sram_field + * @brief macros for field store_in_sram + * @details 0=data gets stored in flash, 1=data gets stored in SRAM + * @{ + */ +#define SHUB_SETUP0__STORE_IN_SRAM__SHIFT 2 +#define SHUB_SETUP0__STORE_IN_SRAM__WIDTH 1 +#define SHUB_SETUP0__STORE_IN_SRAM__MASK 0x00000004U +#define SHUB_SETUP0__STORE_IN_SRAM__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define SHUB_SETUP0__STORE_IN_SRAM__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define SHUB_SETUP0__STORE_IN_SRAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define SHUB_SETUP0__STORE_IN_SRAM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define SHUB_SETUP0__STORE_IN_SRAM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define SHUB_SETUP0__STORE_IN_SRAM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define SHUB_SETUP0__STORE_IN_SRAM__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adv_mode */ +/** + * @defgroup at_apb_shub_regs_core_adv_mode_field adv_mode_field + * @brief macros for field adv_mode + * @details 1=sensor hub's cpu enabled. + * @{ + */ +#define SHUB_SETUP0__ADV_MODE__SHIFT 3 +#define SHUB_SETUP0__ADV_MODE__WIDTH 1 +#define SHUB_SETUP0__ADV_MODE__MASK 0x00000008U +#define SHUB_SETUP0__ADV_MODE__READ(src) (((uint32_t)(src) & 0x00000008U) >> 3) +#define SHUB_SETUP0__ADV_MODE__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define SHUB_SETUP0__ADV_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define SHUB_SETUP0__ADV_MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define SHUB_SETUP0__ADV_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define SHUB_SETUP0__ADV_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define SHUB_SETUP0__ADV_MODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field shub_trig_mode */ +/** + * @defgroup at_apb_shub_regs_core_shub_trig_mode_field shub_trig_mode_field + * @brief macros for field shub_trig_mode + * @details 0=continuous mode 1=trigger mode. + * @{ + */ +#define SHUB_SETUP0__SHUB_TRIG_MODE__SHIFT 4 +#define SHUB_SETUP0__SHUB_TRIG_MODE__WIDTH 1 +#define SHUB_SETUP0__SHUB_TRIG_MODE__MASK 0x00000010U +#define SHUB_SETUP0__SHUB_TRIG_MODE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define SHUB_SETUP0__SHUB_TRIG_MODE__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define SHUB_SETUP0__SHUB_TRIG_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define SHUB_SETUP0__SHUB_TRIG_MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define SHUB_SETUP0__SHUB_TRIG_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define SHUB_SETUP0__SHUB_TRIG_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define SHUB_SETUP0__SHUB_TRIG_MODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field shub_disable */ +/** + * @defgroup at_apb_shub_regs_core_shub_disable_field shub_disable_field + * @brief macros for field shub_disable + * @details 0=enable sensor hub. + * @{ + */ +#define SHUB_SETUP0__SHUB_DISABLE__SHIFT 5 +#define SHUB_SETUP0__SHUB_DISABLE__WIDTH 1 +#define SHUB_SETUP0__SHUB_DISABLE__MASK 0x00000020U +#define SHUB_SETUP0__SHUB_DISABLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define SHUB_SETUP0__SHUB_DISABLE__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define SHUB_SETUP0__SHUB_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define SHUB_SETUP0__SHUB_DISABLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define SHUB_SETUP0__SHUB_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define SHUB_SETUP0__SHUB_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define SHUB_SETUP0__SHUB_DISABLE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_SETUP0__TYPE uint32_t +#define SHUB_SETUP0__READ 0x0000003fU +#define SHUB_SETUP0__WRITE 0x0000003fU +#define SHUB_SETUP0__PRESERVED 0x00000000U +#define SHUB_SETUP0__RESET_VALUE 0x00000000U + +#endif /* __SHUB_SETUP0_MACRO__ */ + +/** @} end of setup0 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_setup1 */ +/** + * @defgroup at_apb_shub_regs_core_setup1 setup1 + * @brief Contains register fields associated with setup1. definitions. + * @{ + */ +#ifndef __SHUB_SETUP1_MACRO__ +#define __SHUB_SETUP1_MACRO__ + +/* macros for field loop_time */ +/** + * @defgroup at_apb_shub_regs_core_loop_time_field loop_time_field + * @brief macros for field loop_time + * @details how long should each iteration (sensor read and flash write) be ? (800 = wr_delay*2 + 16bytes read + overhead). The multiplier of 2 is needed beause when there are mulitple data bytes straddling the page boundary, the shub issues the page program twice. The first one sends all bytes up to the at the page boundary, and the second sends the rest of the data bytes. + * @{ + */ +#define SHUB_SETUP1__LOOP_TIME__SHIFT 0 +#define SHUB_SETUP1__LOOP_TIME__WIDTH 32 +#define SHUB_SETUP1__LOOP_TIME__MASK 0xffffffffU +#define SHUB_SETUP1__LOOP_TIME__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define SHUB_SETUP1__LOOP_TIME__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define SHUB_SETUP1__LOOP_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define SHUB_SETUP1__LOOP_TIME__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define SHUB_SETUP1__LOOP_TIME__RESET_VALUE 0x00003fffU +/** @} */ +#define SHUB_SETUP1__TYPE uint32_t +#define SHUB_SETUP1__READ 0xffffffffU +#define SHUB_SETUP1__WRITE 0xffffffffU +#define SHUB_SETUP1__PRESERVED 0xffffffffU +#define SHUB_SETUP1__RESET_VALUE 0x00003fffU + +#endif /* __SHUB_SETUP1_MACRO__ */ + +/** @} end of setup1 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_setup */ +/** + * @defgroup at_apb_shub_regs_core_port0_setup port0_setup + * @brief Contains register fields associated with port0_setup. definitions. + * @{ + */ +#ifndef __SHUB_PORT0_SETUP_MACRO__ +#define __SHUB_PORT0_SETUP_MACRO__ + +/* macros for field port_en */ +/** + * @defgroup at_apb_shub_regs_core_port_en_field port_en_field + * @brief macros for field port_en + * @{ + */ +#define SHUB_PORT0_SETUP__PORT_EN__SHIFT 0 +#define SHUB_PORT0_SETUP__PORT_EN__WIDTH 1 +#define SHUB_PORT0_SETUP__PORT_EN__MASK 0x00000001U +#define SHUB_PORT0_SETUP__PORT_EN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define SHUB_PORT0_SETUP__PORT_EN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define SHUB_PORT0_SETUP__PORT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_SETUP__PORT_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_SETUP__PORT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_SETUP__PORT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_SETUP__PORT_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field spi_n_i2c */ +/** + * @defgroup at_apb_shub_regs_core_spi_n_i2c_field spi_n_i2c_field + * @brief macros for field spi_n_i2c + * @details 1= use spi for port0, 0= use i2c + * @{ + */ +#define SHUB_PORT0_SETUP__SPI_N_I2C__SHIFT 1 +#define SHUB_PORT0_SETUP__SPI_N_I2C__WIDTH 1 +#define SHUB_PORT0_SETUP__SPI_N_I2C__MASK 0x00000002U +#define SHUB_PORT0_SETUP__SPI_N_I2C__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define SHUB_PORT0_SETUP__SPI_N_I2C__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define SHUB_PORT0_SETUP__SPI_N_I2C__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define SHUB_PORT0_SETUP__SPI_N_I2C__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define SHUB_PORT0_SETUP__SPI_N_I2C__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SHUB_PORT0_SETUP__SPI_N_I2C__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SHUB_PORT0_SETUP__SPI_N_I2C__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field num_sensors */ +/** + * @defgroup at_apb_shub_regs_core_num_sensors_field num_sensors_field + * @brief macros for field num_sensors + * @details number of sensors connected to port = num_sensors + 1 + * @{ + */ +#define SHUB_PORT0_SETUP__NUM_SENSORS__SHIFT 4 +#define SHUB_PORT0_SETUP__NUM_SENSORS__WIDTH 3 +#define SHUB_PORT0_SETUP__NUM_SENSORS__MASK 0x00000070U +#define SHUB_PORT0_SETUP__NUM_SENSORS__READ(src) \ + (((uint32_t)(src)\ + & 0x00000070U) >> 4) +#define SHUB_PORT0_SETUP__NUM_SENSORS__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000070U) +#define SHUB_PORT0_SETUP__NUM_SENSORS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((uint32_t)(src) <<\ + 4) & 0x00000070U) +#define SHUB_PORT0_SETUP__NUM_SENSORS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000070U))) +#define SHUB_PORT0_SETUP__NUM_SENSORS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field trig_en */ +/** + * @defgroup at_apb_shub_regs_core_trig_en_field trig_en_field + * @brief macros for field trig_en + * @details 1= enable threshold comparison with measurement results. + * @{ + */ +#define SHUB_PORT0_SETUP__TRIG_EN__SHIFT 11 +#define SHUB_PORT0_SETUP__TRIG_EN__WIDTH 1 +#define SHUB_PORT0_SETUP__TRIG_EN__MASK 0x00000800U +#define SHUB_PORT0_SETUP__TRIG_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define SHUB_PORT0_SETUP__TRIG_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define SHUB_PORT0_SETUP__TRIG_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define SHUB_PORT0_SETUP__TRIG_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define SHUB_PORT0_SETUP__TRIG_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define SHUB_PORT0_SETUP__TRIG_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define SHUB_PORT0_SETUP__TRIG_EN__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_SETUP__TYPE uint32_t +#define SHUB_PORT0_SETUP__READ 0x00000873U +#define SHUB_PORT0_SETUP__WRITE 0x00000873U +#define SHUB_PORT0_SETUP__PRESERVED 0x00000873U +#define SHUB_PORT0_SETUP__RESET_VALUE 0x00000000U + +#endif /* __SHUB_PORT0_SETUP_MACRO__ */ + +/** @} end of port0_setup */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_sensor0_setup */ +/** + * @defgroup at_apb_shub_regs_core_port0_sensor0_setup port0_sensor0_setup + * @brief Contains register fields associated with port0_sensor0_setup. definitions. + * @{ + */ +#ifndef __SHUB_PORT0_SENSOR0_SETUP_MACRO__ +#define __SHUB_PORT0_SENSOR0_SETUP_MACRO__ + +/* macros for field num_bytes */ +/** + * @defgroup at_apb_shub_regs_core_num_bytes_field num_bytes_field + * @brief macros for field num_bytes + * @details total number of bytes in sensor data = num_bytes+1 + * @{ + */ +#define SHUB_PORT0_SENSOR0_SETUP__NUM_BYTES__SHIFT 0 +#define SHUB_PORT0_SENSOR0_SETUP__NUM_BYTES__WIDTH 5 +#define SHUB_PORT0_SENSOR0_SETUP__NUM_BYTES__MASK 0x0000001fU +#define SHUB_PORT0_SENSOR0_SETUP__NUM_BYTES__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT0_SENSOR0_SETUP__NUM_BYTES__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT0_SENSOR0_SETUP__NUM_BYTES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define SHUB_PORT0_SENSOR0_SETUP__NUM_BYTES__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define SHUB_PORT0_SENSOR0_SETUP__NUM_BYTES__RESET_VALUE 0x00000001U +/** @} */ +#define SHUB_PORT0_SENSOR0_SETUP__TYPE uint32_t +#define SHUB_PORT0_SENSOR0_SETUP__READ 0x0000001fU +#define SHUB_PORT0_SENSOR0_SETUP__WRITE 0x0000001fU +#define SHUB_PORT0_SENSOR0_SETUP__PRESERVED 0x0000001fU +#define SHUB_PORT0_SENSOR0_SETUP__RESET_VALUE 0x00000001U + +#endif /* __SHUB_PORT0_SENSOR0_SETUP_MACRO__ */ + +/** @} end of port0_sensor0_setup */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_sensor1_setup */ +/** + * @defgroup at_apb_shub_regs_core_port0_sensor1_setup port0_sensor1_setup + * @brief Contains register fields associated with port0_sensor1_setup. definitions. + * @{ + */ +#ifndef __SHUB_PORT0_SENSOR1_SETUP_MACRO__ +#define __SHUB_PORT0_SENSOR1_SETUP_MACRO__ + +/* macros for field num_bytes */ +/** + * @defgroup at_apb_shub_regs_core_num_bytes_field num_bytes_field + * @brief macros for field num_bytes + * @details total number of bytes in sensor data = num_bytes+1 + * @{ + */ +#define SHUB_PORT0_SENSOR1_SETUP__NUM_BYTES__SHIFT 0 +#define SHUB_PORT0_SENSOR1_SETUP__NUM_BYTES__WIDTH 5 +#define SHUB_PORT0_SENSOR1_SETUP__NUM_BYTES__MASK 0x0000001fU +#define SHUB_PORT0_SENSOR1_SETUP__NUM_BYTES__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT0_SENSOR1_SETUP__NUM_BYTES__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT0_SENSOR1_SETUP__NUM_BYTES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define SHUB_PORT0_SENSOR1_SETUP__NUM_BYTES__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define SHUB_PORT0_SENSOR1_SETUP__NUM_BYTES__RESET_VALUE 0x00000001U +/** @} */ +#define SHUB_PORT0_SENSOR1_SETUP__TYPE uint32_t +#define SHUB_PORT0_SENSOR1_SETUP__READ 0x0000001fU +#define SHUB_PORT0_SENSOR1_SETUP__WRITE 0x0000001fU +#define SHUB_PORT0_SENSOR1_SETUP__PRESERVED 0x0000001fU +#define SHUB_PORT0_SENSOR1_SETUP__RESET_VALUE 0x00000001U + +#endif /* __SHUB_PORT0_SENSOR1_SETUP_MACRO__ */ + +/** @} end of port0_sensor1_setup */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_sensor2_setup */ +/** + * @defgroup at_apb_shub_regs_core_port0_sensor2_setup port0_sensor2_setup + * @brief Contains register fields associated with port0_sensor2_setup. definitions. + * @{ + */ +#ifndef __SHUB_PORT0_SENSOR2_SETUP_MACRO__ +#define __SHUB_PORT0_SENSOR2_SETUP_MACRO__ + +/* macros for field num_bytes */ +/** + * @defgroup at_apb_shub_regs_core_num_bytes_field num_bytes_field + * @brief macros for field num_bytes + * @details total number of bytes in sensor data = num_bytes+1 + * @{ + */ +#define SHUB_PORT0_SENSOR2_SETUP__NUM_BYTES__SHIFT 0 +#define SHUB_PORT0_SENSOR2_SETUP__NUM_BYTES__WIDTH 5 +#define SHUB_PORT0_SENSOR2_SETUP__NUM_BYTES__MASK 0x0000001fU +#define SHUB_PORT0_SENSOR2_SETUP__NUM_BYTES__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT0_SENSOR2_SETUP__NUM_BYTES__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT0_SENSOR2_SETUP__NUM_BYTES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define SHUB_PORT0_SENSOR2_SETUP__NUM_BYTES__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define SHUB_PORT0_SENSOR2_SETUP__NUM_BYTES__RESET_VALUE 0x00000001U +/** @} */ +#define SHUB_PORT0_SENSOR2_SETUP__TYPE uint32_t +#define SHUB_PORT0_SENSOR2_SETUP__READ 0x0000001fU +#define SHUB_PORT0_SENSOR2_SETUP__WRITE 0x0000001fU +#define SHUB_PORT0_SENSOR2_SETUP__PRESERVED 0x0000001fU +#define SHUB_PORT0_SENSOR2_SETUP__RESET_VALUE 0x00000001U + +#endif /* __SHUB_PORT0_SENSOR2_SETUP_MACRO__ */ + +/** @} end of port0_sensor2_setup */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_sensor3_setup */ +/** + * @defgroup at_apb_shub_regs_core_port0_sensor3_setup port0_sensor3_setup + * @brief Contains register fields associated with port0_sensor3_setup. definitions. + * @{ + */ +#ifndef __SHUB_PORT0_SENSOR3_SETUP_MACRO__ +#define __SHUB_PORT0_SENSOR3_SETUP_MACRO__ + +/* macros for field num_bytes */ +/** + * @defgroup at_apb_shub_regs_core_num_bytes_field num_bytes_field + * @brief macros for field num_bytes + * @details total number of bytes in sensor data = num_bytes+1 + * @{ + */ +#define SHUB_PORT0_SENSOR3_SETUP__NUM_BYTES__SHIFT 0 +#define SHUB_PORT0_SENSOR3_SETUP__NUM_BYTES__WIDTH 5 +#define SHUB_PORT0_SENSOR3_SETUP__NUM_BYTES__MASK 0x0000001fU +#define SHUB_PORT0_SENSOR3_SETUP__NUM_BYTES__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT0_SENSOR3_SETUP__NUM_BYTES__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT0_SENSOR3_SETUP__NUM_BYTES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define SHUB_PORT0_SENSOR3_SETUP__NUM_BYTES__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define SHUB_PORT0_SENSOR3_SETUP__NUM_BYTES__RESET_VALUE 0x00000001U +/** @} */ +#define SHUB_PORT0_SENSOR3_SETUP__TYPE uint32_t +#define SHUB_PORT0_SENSOR3_SETUP__READ 0x0000001fU +#define SHUB_PORT0_SENSOR3_SETUP__WRITE 0x0000001fU +#define SHUB_PORT0_SENSOR3_SETUP__PRESERVED 0x0000001fU +#define SHUB_PORT0_SENSOR3_SETUP__RESET_VALUE 0x00000001U + +#endif /* __SHUB_PORT0_SENSOR3_SETUP_MACRO__ */ + +/** @} end of port0_sensor3_setup */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_sensor4_setup */ +/** + * @defgroup at_apb_shub_regs_core_port0_sensor4_setup port0_sensor4_setup + * @brief Contains register fields associated with port0_sensor4_setup. definitions. + * @{ + */ +#ifndef __SHUB_PORT0_SENSOR4_SETUP_MACRO__ +#define __SHUB_PORT0_SENSOR4_SETUP_MACRO__ + +/* macros for field num_bytes */ +/** + * @defgroup at_apb_shub_regs_core_num_bytes_field num_bytes_field + * @brief macros for field num_bytes + * @details total number of bytes in sensor data = num_bytes+1 + * @{ + */ +#define SHUB_PORT0_SENSOR4_SETUP__NUM_BYTES__SHIFT 0 +#define SHUB_PORT0_SENSOR4_SETUP__NUM_BYTES__WIDTH 5 +#define SHUB_PORT0_SENSOR4_SETUP__NUM_BYTES__MASK 0x0000001fU +#define SHUB_PORT0_SENSOR4_SETUP__NUM_BYTES__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT0_SENSOR4_SETUP__NUM_BYTES__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT0_SENSOR4_SETUP__NUM_BYTES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define SHUB_PORT0_SENSOR4_SETUP__NUM_BYTES__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define SHUB_PORT0_SENSOR4_SETUP__NUM_BYTES__RESET_VALUE 0x00000001U +/** @} */ +#define SHUB_PORT0_SENSOR4_SETUP__TYPE uint32_t +#define SHUB_PORT0_SENSOR4_SETUP__READ 0x0000001fU +#define SHUB_PORT0_SENSOR4_SETUP__WRITE 0x0000001fU +#define SHUB_PORT0_SENSOR4_SETUP__PRESERVED 0x0000001fU +#define SHUB_PORT0_SENSOR4_SETUP__RESET_VALUE 0x00000001U + +#endif /* __SHUB_PORT0_SENSOR4_SETUP_MACRO__ */ + +/** @} end of port0_sensor4_setup */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_sensor5_setup */ +/** + * @defgroup at_apb_shub_regs_core_port0_sensor5_setup port0_sensor5_setup + * @brief Contains register fields associated with port0_sensor5_setup. definitions. + * @{ + */ +#ifndef __SHUB_PORT0_SENSOR5_SETUP_MACRO__ +#define __SHUB_PORT0_SENSOR5_SETUP_MACRO__ + +/* macros for field num_bytes */ +/** + * @defgroup at_apb_shub_regs_core_num_bytes_field num_bytes_field + * @brief macros for field num_bytes + * @details total number of bytes in sensor data = num_bytes+1 + * @{ + */ +#define SHUB_PORT0_SENSOR5_SETUP__NUM_BYTES__SHIFT 0 +#define SHUB_PORT0_SENSOR5_SETUP__NUM_BYTES__WIDTH 5 +#define SHUB_PORT0_SENSOR5_SETUP__NUM_BYTES__MASK 0x0000001fU +#define SHUB_PORT0_SENSOR5_SETUP__NUM_BYTES__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT0_SENSOR5_SETUP__NUM_BYTES__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT0_SENSOR5_SETUP__NUM_BYTES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define SHUB_PORT0_SENSOR5_SETUP__NUM_BYTES__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define SHUB_PORT0_SENSOR5_SETUP__NUM_BYTES__RESET_VALUE 0x00000001U +/** @} */ +#define SHUB_PORT0_SENSOR5_SETUP__TYPE uint32_t +#define SHUB_PORT0_SENSOR5_SETUP__READ 0x0000001fU +#define SHUB_PORT0_SENSOR5_SETUP__WRITE 0x0000001fU +#define SHUB_PORT0_SENSOR5_SETUP__PRESERVED 0x0000001fU +#define SHUB_PORT0_SENSOR5_SETUP__RESET_VALUE 0x00000001U + +#endif /* __SHUB_PORT0_SENSOR5_SETUP_MACRO__ */ + +/** @} end of port0_sensor5_setup */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_sensor6_setup */ +/** + * @defgroup at_apb_shub_regs_core_port0_sensor6_setup port0_sensor6_setup + * @brief Contains register fields associated with port0_sensor6_setup. definitions. + * @{ + */ +#ifndef __SHUB_PORT0_SENSOR6_SETUP_MACRO__ +#define __SHUB_PORT0_SENSOR6_SETUP_MACRO__ + +/* macros for field num_bytes */ +/** + * @defgroup at_apb_shub_regs_core_num_bytes_field num_bytes_field + * @brief macros for field num_bytes + * @details total number of bytes in sensor data = num_bytes+1 + * @{ + */ +#define SHUB_PORT0_SENSOR6_SETUP__NUM_BYTES__SHIFT 0 +#define SHUB_PORT0_SENSOR6_SETUP__NUM_BYTES__WIDTH 5 +#define SHUB_PORT0_SENSOR6_SETUP__NUM_BYTES__MASK 0x0000001fU +#define SHUB_PORT0_SENSOR6_SETUP__NUM_BYTES__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT0_SENSOR6_SETUP__NUM_BYTES__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT0_SENSOR6_SETUP__NUM_BYTES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define SHUB_PORT0_SENSOR6_SETUP__NUM_BYTES__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define SHUB_PORT0_SENSOR6_SETUP__NUM_BYTES__RESET_VALUE 0x00000001U +/** @} */ +#define SHUB_PORT0_SENSOR6_SETUP__TYPE uint32_t +#define SHUB_PORT0_SENSOR6_SETUP__READ 0x0000001fU +#define SHUB_PORT0_SENSOR6_SETUP__WRITE 0x0000001fU +#define SHUB_PORT0_SENSOR6_SETUP__PRESERVED 0x0000001fU +#define SHUB_PORT0_SENSOR6_SETUP__RESET_VALUE 0x00000001U + +#endif /* __SHUB_PORT0_SENSOR6_SETUP_MACRO__ */ + +/** @} end of port0_sensor6_setup */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_sensor7_setup */ +/** + * @defgroup at_apb_shub_regs_core_port0_sensor7_setup port0_sensor7_setup + * @brief Contains register fields associated with port0_sensor7_setup. definitions. + * @{ + */ +#ifndef __SHUB_PORT0_SENSOR7_SETUP_MACRO__ +#define __SHUB_PORT0_SENSOR7_SETUP_MACRO__ + +/* macros for field num_bytes */ +/** + * @defgroup at_apb_shub_regs_core_num_bytes_field num_bytes_field + * @brief macros for field num_bytes + * @details total number of bytes in sensor data = num_bytes+1 + * @{ + */ +#define SHUB_PORT0_SENSOR7_SETUP__NUM_BYTES__SHIFT 0 +#define SHUB_PORT0_SENSOR7_SETUP__NUM_BYTES__WIDTH 5 +#define SHUB_PORT0_SENSOR7_SETUP__NUM_BYTES__MASK 0x0000001fU +#define SHUB_PORT0_SENSOR7_SETUP__NUM_BYTES__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT0_SENSOR7_SETUP__NUM_BYTES__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT0_SENSOR7_SETUP__NUM_BYTES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define SHUB_PORT0_SENSOR7_SETUP__NUM_BYTES__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define SHUB_PORT0_SENSOR7_SETUP__NUM_BYTES__RESET_VALUE 0x00000001U +/** @} */ +#define SHUB_PORT0_SENSOR7_SETUP__TYPE uint32_t +#define SHUB_PORT0_SENSOR7_SETUP__READ 0x0000001fU +#define SHUB_PORT0_SENSOR7_SETUP__WRITE 0x0000001fU +#define SHUB_PORT0_SENSOR7_SETUP__PRESERVED 0x0000001fU +#define SHUB_PORT0_SENSOR7_SETUP__RESET_VALUE 0x00000001U + +#endif /* __SHUB_PORT0_SENSOR7_SETUP_MACRO__ */ + +/** @} end of port0_sensor7_setup */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_spi_eng0_ctrl */ +/** + * @defgroup at_apb_shub_regs_core_port0_spi_eng0_ctrl port0_spi_eng0_ctrl + * @brief Contains register fields associated with port0_spi_eng0_ctrl. definitions. + * @{ + */ +#ifndef __SHUB_PORT0_SPI_ENG0_CTRL_MACRO__ +#define __SHUB_PORT0_SPI_ENG0_CTRL_MACRO__ + +/* macros for field sensor_opcode */ +/** + * @defgroup at_apb_shub_regs_core_sensor_opcode_field sensor_opcode_field + * @brief macros for field sensor_opcode + * @details opcode used to communicate with sensor in spi mode + * @{ + */ +#define SHUB_PORT0_SPI_ENG0_CTRL__SENSOR_OPCODE__SHIFT 0 +#define SHUB_PORT0_SPI_ENG0_CTRL__SENSOR_OPCODE__WIDTH 8 +#define SHUB_PORT0_SPI_ENG0_CTRL__SENSOR_OPCODE__MASK 0x000000ffU +#define SHUB_PORT0_SPI_ENG0_CTRL__SENSOR_OPCODE__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_SPI_ENG0_CTRL__SENSOR_OPCODE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_SPI_ENG0_CTRL__SENSOR_OPCODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_PORT0_SPI_ENG0_CTRL__SENSOR_OPCODE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_PORT0_SPI_ENG0_CTRL__SENSOR_OPCODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cpha */ +/** + * @defgroup at_apb_shub_regs_core_cpha_field cpha_field + * @brief macros for field cpha + * @details spi clcok phase mode + * @{ + */ +#define SHUB_PORT0_SPI_ENG0_CTRL__CPHA__SHIFT 30 +#define SHUB_PORT0_SPI_ENG0_CTRL__CPHA__WIDTH 1 +#define SHUB_PORT0_SPI_ENG0_CTRL__CPHA__MASK 0x40000000U +#define SHUB_PORT0_SPI_ENG0_CTRL__CPHA__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define SHUB_PORT0_SPI_ENG0_CTRL__CPHA__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define SHUB_PORT0_SPI_ENG0_CTRL__CPHA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define SHUB_PORT0_SPI_ENG0_CTRL__CPHA__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define SHUB_PORT0_SPI_ENG0_CTRL__CPHA__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define SHUB_PORT0_SPI_ENG0_CTRL__CPHA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define SHUB_PORT0_SPI_ENG0_CTRL__CPHA__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cpol */ +/** + * @defgroup at_apb_shub_regs_core_cpol_field cpol_field + * @brief macros for field cpol + * @details spi clock polarity mode. 0 = posedge-sensitive, 1 = negedge + * @{ + */ +#define SHUB_PORT0_SPI_ENG0_CTRL__CPOL__SHIFT 31 +#define SHUB_PORT0_SPI_ENG0_CTRL__CPOL__WIDTH 1 +#define SHUB_PORT0_SPI_ENG0_CTRL__CPOL__MASK 0x80000000U +#define SHUB_PORT0_SPI_ENG0_CTRL__CPOL__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define SHUB_PORT0_SPI_ENG0_CTRL__CPOL__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define SHUB_PORT0_SPI_ENG0_CTRL__CPOL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define SHUB_PORT0_SPI_ENG0_CTRL__CPOL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define SHUB_PORT0_SPI_ENG0_CTRL__CPOL__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define SHUB_PORT0_SPI_ENG0_CTRL__CPOL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define SHUB_PORT0_SPI_ENG0_CTRL__CPOL__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_SPI_ENG0_CTRL__TYPE uint32_t +#define SHUB_PORT0_SPI_ENG0_CTRL__READ 0xc00000ffU +#define SHUB_PORT0_SPI_ENG0_CTRL__WRITE 0xc00000ffU +#define SHUB_PORT0_SPI_ENG0_CTRL__PRESERVED 0xc00000ffU +#define SHUB_PORT0_SPI_ENG0_CTRL__RESET_VALUE 0x00000000U + +#endif /* __SHUB_PORT0_SPI_ENG0_CTRL_MACRO__ */ + +/** @} end of port0_spi_eng0_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_idw_0 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_idw_0 port0_i2c_idw_0 + * @brief id(read) of sensor0 on port0 prior to pointer address write definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_IDW_0_MACRO__ +#define __SHUB_PORT0_I2C_IDW_0_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_IDW_0__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDW_0__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_IDW_0__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_0__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_IDW_0__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_IDW_0__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDW_0__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDW_0__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_IDW_0__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_IDW_0__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_IDW_0__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_IDW_0__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_IDW_0__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_IDW_0__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_IDW_0__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_IDW_0__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDW_0__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDW_0__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_IDW_0__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_IDW_0__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_IDW_0__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_IDW_0__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_IDW_0__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_IDW_0__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDW_0__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDW_0__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_IDW_0__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_IDW_0__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_IDW_0__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_0__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_IDW_0__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_IDW_0__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDW_0__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDW_0__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_IDW_0__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_IDW_0__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_IDW_0__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_IDW_0__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_IDW_0__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_0__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_IDW_0__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_IDW_0__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDW_0__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDW_0__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_IDW_0__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_IDW_0__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_IDW_0__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_IDW_0__TYPE uint32_t +#define SHUB_PORT0_I2C_IDW_0__READ 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_0__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_0__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_0__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_IDW_0_MACRO__ */ + +/** @} end of port0_i2c_idw_0 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_idw_1 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_idw_1 port0_i2c_idw_1 + * @brief id(read) of sensor1 on port0 prior to pointer address write definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_IDW_1_MACRO__ +#define __SHUB_PORT0_I2C_IDW_1_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_IDW_1__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDW_1__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_IDW_1__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_1__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_IDW_1__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_IDW_1__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDW_1__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDW_1__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_IDW_1__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_IDW_1__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_IDW_1__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_IDW_1__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_IDW_1__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_IDW_1__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_IDW_1__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_IDW_1__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDW_1__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDW_1__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_IDW_1__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_IDW_1__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_IDW_1__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_IDW_1__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_IDW_1__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_IDW_1__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDW_1__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDW_1__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_IDW_1__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_IDW_1__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_IDW_1__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_1__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_IDW_1__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_IDW_1__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDW_1__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDW_1__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_IDW_1__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_IDW_1__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_IDW_1__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_IDW_1__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_IDW_1__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_1__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_IDW_1__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_IDW_1__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDW_1__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDW_1__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_IDW_1__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_IDW_1__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_IDW_1__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_IDW_1__TYPE uint32_t +#define SHUB_PORT0_I2C_IDW_1__READ 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_1__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_1__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_1__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_IDW_1_MACRO__ */ + +/** @} end of port0_i2c_idw_1 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_idw_2 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_idw_2 port0_i2c_idw_2 + * @brief id(read) of sensor2 on port0 prior to pointer address write definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_IDW_2_MACRO__ +#define __SHUB_PORT0_I2C_IDW_2_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_IDW_2__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDW_2__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_IDW_2__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_2__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_IDW_2__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_IDW_2__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDW_2__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDW_2__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_IDW_2__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_IDW_2__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_IDW_2__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_IDW_2__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_IDW_2__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_IDW_2__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_IDW_2__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_IDW_2__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDW_2__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDW_2__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_IDW_2__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_IDW_2__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_IDW_2__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_IDW_2__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_IDW_2__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_IDW_2__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDW_2__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDW_2__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_IDW_2__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_IDW_2__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_IDW_2__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_2__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_IDW_2__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_IDW_2__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDW_2__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDW_2__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_IDW_2__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_IDW_2__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_IDW_2__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_IDW_2__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_IDW_2__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_2__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_IDW_2__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_IDW_2__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDW_2__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDW_2__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_IDW_2__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_IDW_2__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_IDW_2__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_IDW_2__TYPE uint32_t +#define SHUB_PORT0_I2C_IDW_2__READ 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_2__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_2__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_2__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_IDW_2_MACRO__ */ + +/** @} end of port0_i2c_idw_2 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_idw_3 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_idw_3 port0_i2c_idw_3 + * @brief id(read) of sensor3 on port0 prior to pointer address write definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_IDW_3_MACRO__ +#define __SHUB_PORT0_I2C_IDW_3_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_IDW_3__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDW_3__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_IDW_3__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_3__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_IDW_3__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_IDW_3__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDW_3__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDW_3__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_IDW_3__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_IDW_3__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_IDW_3__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_IDW_3__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_IDW_3__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_IDW_3__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_IDW_3__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_IDW_3__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDW_3__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDW_3__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_IDW_3__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_IDW_3__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_IDW_3__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_IDW_3__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_IDW_3__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_IDW_3__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDW_3__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDW_3__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_IDW_3__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_IDW_3__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_IDW_3__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_3__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_IDW_3__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_IDW_3__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDW_3__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDW_3__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_IDW_3__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_IDW_3__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_IDW_3__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_IDW_3__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_IDW_3__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_3__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_IDW_3__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_IDW_3__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDW_3__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDW_3__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_IDW_3__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_IDW_3__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_IDW_3__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_IDW_3__TYPE uint32_t +#define SHUB_PORT0_I2C_IDW_3__READ 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_3__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_3__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_3__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_IDW_3_MACRO__ */ + +/** @} end of port0_i2c_idw_3 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_idw_4 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_idw_4 port0_i2c_idw_4 + * @brief id(read) of sensor4 on port0 prior to pointer address write definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_IDW_4_MACRO__ +#define __SHUB_PORT0_I2C_IDW_4_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_IDW_4__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDW_4__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_IDW_4__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_4__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_IDW_4__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_IDW_4__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDW_4__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDW_4__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_IDW_4__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_IDW_4__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_IDW_4__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_IDW_4__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_IDW_4__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_IDW_4__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_IDW_4__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_IDW_4__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDW_4__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDW_4__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_IDW_4__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_IDW_4__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_IDW_4__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_IDW_4__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_IDW_4__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_IDW_4__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDW_4__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDW_4__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_IDW_4__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_IDW_4__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_IDW_4__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_4__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_IDW_4__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_IDW_4__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDW_4__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDW_4__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_IDW_4__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_IDW_4__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_IDW_4__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_IDW_4__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_IDW_4__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_4__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_IDW_4__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_IDW_4__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDW_4__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDW_4__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_IDW_4__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_IDW_4__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_IDW_4__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_IDW_4__TYPE uint32_t +#define SHUB_PORT0_I2C_IDW_4__READ 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_4__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_4__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_4__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_IDW_4_MACRO__ */ + +/** @} end of port0_i2c_idw_4 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_idw_5 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_idw_5 port0_i2c_idw_5 + * @brief id(read) of sensor5 on port0 prior to pointer address write definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_IDW_5_MACRO__ +#define __SHUB_PORT0_I2C_IDW_5_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_IDW_5__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDW_5__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_IDW_5__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_5__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_IDW_5__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_IDW_5__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDW_5__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDW_5__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_IDW_5__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_IDW_5__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_IDW_5__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_IDW_5__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_IDW_5__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_IDW_5__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_IDW_5__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_IDW_5__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDW_5__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDW_5__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_IDW_5__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_IDW_5__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_IDW_5__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_IDW_5__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_IDW_5__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_IDW_5__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDW_5__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDW_5__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_IDW_5__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_IDW_5__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_IDW_5__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_5__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_IDW_5__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_IDW_5__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDW_5__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDW_5__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_IDW_5__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_IDW_5__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_IDW_5__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_IDW_5__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_IDW_5__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_5__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_IDW_5__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_IDW_5__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDW_5__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDW_5__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_IDW_5__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_IDW_5__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_IDW_5__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_IDW_5__TYPE uint32_t +#define SHUB_PORT0_I2C_IDW_5__READ 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_5__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_5__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_5__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_IDW_5_MACRO__ */ + +/** @} end of port0_i2c_idw_5 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_idw_6 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_idw_6 port0_i2c_idw_6 + * @brief id(read) of sensor6 on port0 prior to pointer address write definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_IDW_6_MACRO__ +#define __SHUB_PORT0_I2C_IDW_6_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_IDW_6__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDW_6__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_IDW_6__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_6__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_IDW_6__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_IDW_6__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDW_6__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDW_6__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_IDW_6__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_IDW_6__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_IDW_6__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_IDW_6__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_IDW_6__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_IDW_6__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_IDW_6__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_IDW_6__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDW_6__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDW_6__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_IDW_6__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_IDW_6__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_IDW_6__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_IDW_6__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_IDW_6__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_IDW_6__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDW_6__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDW_6__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_IDW_6__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_IDW_6__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_IDW_6__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_6__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_IDW_6__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_IDW_6__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDW_6__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDW_6__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_IDW_6__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_IDW_6__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_IDW_6__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_IDW_6__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_IDW_6__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_6__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_IDW_6__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_IDW_6__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDW_6__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDW_6__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_IDW_6__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_IDW_6__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_IDW_6__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_IDW_6__TYPE uint32_t +#define SHUB_PORT0_I2C_IDW_6__READ 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_6__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_6__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_6__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_IDW_6_MACRO__ */ + +/** @} end of port0_i2c_idw_6 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_idw_7 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_idw_7 port0_i2c_idw_7 + * @brief id(read) of sensor7 on port0 prior to pointer address write definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_IDW_7_MACRO__ +#define __SHUB_PORT0_I2C_IDW_7_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_IDW_7__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDW_7__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_IDW_7__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_7__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_IDW_7__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_IDW_7__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDW_7__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDW_7__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_IDW_7__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_IDW_7__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_IDW_7__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_IDW_7__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_IDW_7__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_IDW_7__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_IDW_7__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_IDW_7__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDW_7__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDW_7__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_IDW_7__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_IDW_7__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_IDW_7__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_IDW_7__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_IDW_7__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_IDW_7__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDW_7__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDW_7__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_IDW_7__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_IDW_7__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_IDW_7__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_7__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_IDW_7__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_IDW_7__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDW_7__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDW_7__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_IDW_7__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_IDW_7__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_IDW_7__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_IDW_7__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_IDW_7__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_IDW_7__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_IDW_7__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_IDW_7__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDW_7__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDW_7__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_IDW_7__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_IDW_7__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_IDW_7__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_IDW_7__TYPE uint32_t +#define SHUB_PORT0_I2C_IDW_7__READ 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_7__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_7__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_IDW_7__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_IDW_7_MACRO__ */ + +/** @} end of port0_i2c_idw_7 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_addr_0 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_addr_0 port0_i2c_addr_0 + * @brief pointer addr of sensor0 on port0 definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_ADDR_0_MACRO__ +#define __SHUB_PORT0_I2C_ADDR_0_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_ADDR_0__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_0__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_ADDR_0__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_0__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_ADDR_0__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_ADDR_0__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_ADDR_0__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_ADDR_0__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_ADDR_0__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_ADDR_0__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_ADDR_0__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_0__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_ADDR_0__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_ADDR_0__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_ADDR_0__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_ADDR_0__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_ADDR_0__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_ADDR_0__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_ADDR_0__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_0__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_ADDR_0__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_ADDR_0__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_ADDR_0__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_ADDR_0__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_ADDR_0__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_ADDR_0__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_ADDR_0__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_0__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_ADDR_0__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_0__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_ADDR_0__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_ADDR_0__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_ADDR_0__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_ADDR_0__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_ADDR_0__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_ADDR_0__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_ADDR_0__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_0__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_ADDR_0__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_0__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_ADDR_0__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_ADDR_0__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_ADDR_0__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_ADDR_0__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_ADDR_0__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_ADDR_0__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_ADDR_0__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_ADDR_0__TYPE uint32_t +#define SHUB_PORT0_I2C_ADDR_0__READ 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_0__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_0__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_0__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_ADDR_0_MACRO__ */ + +/** @} end of port0_i2c_addr_0 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_addr_1 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_addr_1 port0_i2c_addr_1 + * @brief pointer addr of sensor1 on port0 definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_ADDR_1_MACRO__ +#define __SHUB_PORT0_I2C_ADDR_1_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_ADDR_1__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_1__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_ADDR_1__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_1__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_ADDR_1__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_ADDR_1__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_ADDR_1__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_ADDR_1__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_ADDR_1__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_ADDR_1__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_ADDR_1__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_1__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_ADDR_1__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_ADDR_1__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_ADDR_1__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_ADDR_1__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_ADDR_1__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_ADDR_1__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_ADDR_1__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_1__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_ADDR_1__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_ADDR_1__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_ADDR_1__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_ADDR_1__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_ADDR_1__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_ADDR_1__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_ADDR_1__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_1__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_ADDR_1__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_1__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_ADDR_1__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_ADDR_1__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_ADDR_1__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_ADDR_1__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_ADDR_1__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_ADDR_1__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_ADDR_1__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_1__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_ADDR_1__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_1__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_ADDR_1__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_ADDR_1__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_ADDR_1__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_ADDR_1__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_ADDR_1__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_ADDR_1__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_ADDR_1__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_ADDR_1__TYPE uint32_t +#define SHUB_PORT0_I2C_ADDR_1__READ 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_1__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_1__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_1__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_ADDR_1_MACRO__ */ + +/** @} end of port0_i2c_addr_1 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_addr_2 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_addr_2 port0_i2c_addr_2 + * @brief pointer addr of sensor2 on port0 definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_ADDR_2_MACRO__ +#define __SHUB_PORT0_I2C_ADDR_2_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_ADDR_2__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_2__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_ADDR_2__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_2__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_ADDR_2__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_ADDR_2__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_ADDR_2__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_ADDR_2__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_ADDR_2__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_ADDR_2__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_ADDR_2__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_2__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_ADDR_2__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_ADDR_2__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_ADDR_2__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_ADDR_2__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_ADDR_2__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_ADDR_2__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_ADDR_2__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_2__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_ADDR_2__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_ADDR_2__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_ADDR_2__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_ADDR_2__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_ADDR_2__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_ADDR_2__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_ADDR_2__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_2__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_ADDR_2__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_2__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_ADDR_2__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_ADDR_2__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_ADDR_2__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_ADDR_2__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_ADDR_2__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_ADDR_2__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_ADDR_2__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_2__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_ADDR_2__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_2__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_ADDR_2__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_ADDR_2__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_ADDR_2__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_ADDR_2__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_ADDR_2__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_ADDR_2__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_ADDR_2__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_ADDR_2__TYPE uint32_t +#define SHUB_PORT0_I2C_ADDR_2__READ 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_2__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_2__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_2__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_ADDR_2_MACRO__ */ + +/** @} end of port0_i2c_addr_2 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_addr_3 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_addr_3 port0_i2c_addr_3 + * @brief pointer addr of sensor3 on port0 definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_ADDR_3_MACRO__ +#define __SHUB_PORT0_I2C_ADDR_3_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_ADDR_3__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_3__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_ADDR_3__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_3__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_ADDR_3__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_ADDR_3__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_ADDR_3__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_ADDR_3__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_ADDR_3__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_ADDR_3__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_ADDR_3__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_3__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_ADDR_3__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_ADDR_3__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_ADDR_3__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_ADDR_3__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_ADDR_3__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_ADDR_3__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_ADDR_3__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_3__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_ADDR_3__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_ADDR_3__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_ADDR_3__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_ADDR_3__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_ADDR_3__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_ADDR_3__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_ADDR_3__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_3__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_ADDR_3__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_3__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_ADDR_3__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_ADDR_3__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_ADDR_3__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_ADDR_3__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_ADDR_3__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_ADDR_3__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_ADDR_3__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_3__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_ADDR_3__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_3__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_ADDR_3__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_ADDR_3__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_ADDR_3__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_ADDR_3__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_ADDR_3__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_ADDR_3__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_ADDR_3__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_ADDR_3__TYPE uint32_t +#define SHUB_PORT0_I2C_ADDR_3__READ 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_3__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_3__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_3__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_ADDR_3_MACRO__ */ + +/** @} end of port0_i2c_addr_3 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_addr_4 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_addr_4 port0_i2c_addr_4 + * @brief pointer addr of sensor4 on port0 definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_ADDR_4_MACRO__ +#define __SHUB_PORT0_I2C_ADDR_4_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_ADDR_4__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_4__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_ADDR_4__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_4__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_ADDR_4__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_ADDR_4__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_ADDR_4__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_ADDR_4__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_ADDR_4__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_ADDR_4__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_ADDR_4__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_4__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_ADDR_4__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_ADDR_4__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_ADDR_4__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_ADDR_4__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_ADDR_4__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_ADDR_4__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_ADDR_4__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_4__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_ADDR_4__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_ADDR_4__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_ADDR_4__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_ADDR_4__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_ADDR_4__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_ADDR_4__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_ADDR_4__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_4__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_ADDR_4__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_4__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_ADDR_4__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_ADDR_4__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_ADDR_4__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_ADDR_4__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_ADDR_4__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_ADDR_4__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_ADDR_4__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_4__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_ADDR_4__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_4__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_ADDR_4__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_ADDR_4__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_ADDR_4__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_ADDR_4__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_ADDR_4__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_ADDR_4__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_ADDR_4__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_ADDR_4__TYPE uint32_t +#define SHUB_PORT0_I2C_ADDR_4__READ 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_4__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_4__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_4__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_ADDR_4_MACRO__ */ + +/** @} end of port0_i2c_addr_4 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_addr_5 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_addr_5 port0_i2c_addr_5 + * @brief pointer addr of sensor5 on port0 definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_ADDR_5_MACRO__ +#define __SHUB_PORT0_I2C_ADDR_5_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_ADDR_5__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_5__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_ADDR_5__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_5__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_ADDR_5__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_ADDR_5__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_ADDR_5__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_ADDR_5__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_ADDR_5__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_ADDR_5__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_ADDR_5__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_5__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_ADDR_5__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_ADDR_5__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_ADDR_5__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_ADDR_5__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_ADDR_5__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_ADDR_5__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_ADDR_5__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_5__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_ADDR_5__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_ADDR_5__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_ADDR_5__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_ADDR_5__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_ADDR_5__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_ADDR_5__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_ADDR_5__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_5__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_ADDR_5__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_5__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_ADDR_5__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_ADDR_5__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_ADDR_5__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_ADDR_5__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_ADDR_5__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_ADDR_5__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_ADDR_5__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_5__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_ADDR_5__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_5__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_ADDR_5__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_ADDR_5__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_ADDR_5__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_ADDR_5__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_ADDR_5__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_ADDR_5__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_ADDR_5__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_ADDR_5__TYPE uint32_t +#define SHUB_PORT0_I2C_ADDR_5__READ 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_5__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_5__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_5__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_ADDR_5_MACRO__ */ + +/** @} end of port0_i2c_addr_5 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_addr_6 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_addr_6 port0_i2c_addr_6 + * @brief pointer addr of sensor6 on port0 definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_ADDR_6_MACRO__ +#define __SHUB_PORT0_I2C_ADDR_6_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_ADDR_6__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_6__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_ADDR_6__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_6__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_ADDR_6__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_ADDR_6__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_ADDR_6__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_ADDR_6__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_ADDR_6__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_ADDR_6__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_ADDR_6__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_6__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_ADDR_6__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_ADDR_6__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_ADDR_6__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_ADDR_6__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_ADDR_6__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_ADDR_6__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_ADDR_6__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_6__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_ADDR_6__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_ADDR_6__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_ADDR_6__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_ADDR_6__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_ADDR_6__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_ADDR_6__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_ADDR_6__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_6__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_ADDR_6__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_6__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_ADDR_6__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_ADDR_6__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_ADDR_6__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_ADDR_6__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_ADDR_6__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_ADDR_6__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_ADDR_6__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_6__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_ADDR_6__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_6__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_ADDR_6__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_ADDR_6__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_ADDR_6__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_ADDR_6__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_ADDR_6__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_ADDR_6__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_ADDR_6__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_ADDR_6__TYPE uint32_t +#define SHUB_PORT0_I2C_ADDR_6__READ 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_6__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_6__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_6__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_ADDR_6_MACRO__ */ + +/** @} end of port0_i2c_addr_6 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_addr_7 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_addr_7 port0_i2c_addr_7 + * @brief pointer addr of sensor7 on port0 definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_ADDR_7_MACRO__ +#define __SHUB_PORT0_I2C_ADDR_7_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_ADDR_7__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_7__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_ADDR_7__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_7__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_ADDR_7__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_ADDR_7__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_ADDR_7__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_ADDR_7__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_ADDR_7__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_ADDR_7__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_ADDR_7__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_7__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_ADDR_7__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_ADDR_7__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_ADDR_7__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_ADDR_7__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_ADDR_7__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_ADDR_7__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_ADDR_7__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_7__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_ADDR_7__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_ADDR_7__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_ADDR_7__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_ADDR_7__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_ADDR_7__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_ADDR_7__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_ADDR_7__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_7__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_ADDR_7__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_7__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_ADDR_7__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_ADDR_7__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_ADDR_7__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_ADDR_7__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_ADDR_7__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_ADDR_7__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_ADDR_7__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_ADDR_7__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_ADDR_7__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_ADDR_7__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_ADDR_7__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_ADDR_7__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_ADDR_7__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_ADDR_7__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_ADDR_7__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_ADDR_7__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_ADDR_7__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_ADDR_7__TYPE uint32_t +#define SHUB_PORT0_I2C_ADDR_7__READ 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_7__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_7__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_ADDR_7__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_ADDR_7_MACRO__ */ + +/** @} end of port0_i2c_addr_7 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_idr_0 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_idr_0 port0_i2c_idr_0 + * @brief id(read) of sensor0 on port0 prior to data read definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_IDR_0_MACRO__ +#define __SHUB_PORT0_I2C_IDR_0_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_IDR_0__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDR_0__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_IDR_0__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_0__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_IDR_0__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_IDR_0__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDR_0__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDR_0__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_IDR_0__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_IDR_0__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_IDR_0__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_IDR_0__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_IDR_0__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_IDR_0__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_IDR_0__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_IDR_0__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDR_0__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDR_0__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_IDR_0__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_IDR_0__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_IDR_0__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_IDR_0__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_IDR_0__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_IDR_0__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDR_0__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDR_0__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_IDR_0__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_IDR_0__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_IDR_0__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_0__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_IDR_0__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_IDR_0__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDR_0__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDR_0__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_IDR_0__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_IDR_0__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_IDR_0__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_IDR_0__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_IDR_0__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_0__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_IDR_0__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_IDR_0__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDR_0__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDR_0__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_IDR_0__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_IDR_0__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_IDR_0__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_IDR_0__TYPE uint32_t +#define SHUB_PORT0_I2C_IDR_0__READ 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_0__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_0__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_0__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_IDR_0_MACRO__ */ + +/** @} end of port0_i2c_idr_0 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_idr_1 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_idr_1 port0_i2c_idr_1 + * @brief id(read) of sensor1 on port0 prior to data read definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_IDR_1_MACRO__ +#define __SHUB_PORT0_I2C_IDR_1_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_IDR_1__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDR_1__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_IDR_1__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_1__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_IDR_1__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_IDR_1__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDR_1__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDR_1__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_IDR_1__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_IDR_1__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_IDR_1__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_IDR_1__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_IDR_1__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_IDR_1__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_IDR_1__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_IDR_1__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDR_1__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDR_1__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_IDR_1__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_IDR_1__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_IDR_1__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_IDR_1__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_IDR_1__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_IDR_1__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDR_1__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDR_1__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_IDR_1__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_IDR_1__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_IDR_1__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_1__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_IDR_1__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_IDR_1__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDR_1__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDR_1__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_IDR_1__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_IDR_1__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_IDR_1__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_IDR_1__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_IDR_1__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_1__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_IDR_1__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_IDR_1__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDR_1__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDR_1__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_IDR_1__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_IDR_1__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_IDR_1__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_IDR_1__TYPE uint32_t +#define SHUB_PORT0_I2C_IDR_1__READ 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_1__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_1__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_1__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_IDR_1_MACRO__ */ + +/** @} end of port0_i2c_idr_1 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_idr_2 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_idr_2 port0_i2c_idr_2 + * @brief id(read) of sensor2 on port0 prior to data read definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_IDR_2_MACRO__ +#define __SHUB_PORT0_I2C_IDR_2_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_IDR_2__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDR_2__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_IDR_2__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_2__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_IDR_2__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_IDR_2__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDR_2__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDR_2__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_IDR_2__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_IDR_2__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_IDR_2__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_IDR_2__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_IDR_2__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_IDR_2__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_IDR_2__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_IDR_2__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDR_2__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDR_2__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_IDR_2__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_IDR_2__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_IDR_2__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_IDR_2__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_IDR_2__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_IDR_2__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDR_2__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDR_2__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_IDR_2__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_IDR_2__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_IDR_2__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_2__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_IDR_2__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_IDR_2__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDR_2__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDR_2__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_IDR_2__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_IDR_2__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_IDR_2__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_IDR_2__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_IDR_2__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_2__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_IDR_2__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_IDR_2__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDR_2__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDR_2__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_IDR_2__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_IDR_2__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_IDR_2__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_IDR_2__TYPE uint32_t +#define SHUB_PORT0_I2C_IDR_2__READ 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_2__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_2__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_2__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_IDR_2_MACRO__ */ + +/** @} end of port0_i2c_idr_2 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_idr_3 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_idr_3 port0_i2c_idr_3 + * @brief id(read) of sensor3 on port0 prior to data read definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_IDR_3_MACRO__ +#define __SHUB_PORT0_I2C_IDR_3_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_IDR_3__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDR_3__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_IDR_3__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_3__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_IDR_3__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_IDR_3__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDR_3__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDR_3__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_IDR_3__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_IDR_3__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_IDR_3__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_IDR_3__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_IDR_3__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_IDR_3__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_IDR_3__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_IDR_3__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDR_3__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDR_3__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_IDR_3__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_IDR_3__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_IDR_3__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_IDR_3__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_IDR_3__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_IDR_3__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDR_3__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDR_3__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_IDR_3__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_IDR_3__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_IDR_3__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_3__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_IDR_3__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_IDR_3__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDR_3__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDR_3__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_IDR_3__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_IDR_3__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_IDR_3__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_IDR_3__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_IDR_3__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_3__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_IDR_3__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_IDR_3__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDR_3__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDR_3__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_IDR_3__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_IDR_3__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_IDR_3__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_IDR_3__TYPE uint32_t +#define SHUB_PORT0_I2C_IDR_3__READ 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_3__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_3__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_3__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_IDR_3_MACRO__ */ + +/** @} end of port0_i2c_idr_3 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_idr_4 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_idr_4 port0_i2c_idr_4 + * @brief id(read) of sensor4 on port0 prior to data read definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_IDR_4_MACRO__ +#define __SHUB_PORT0_I2C_IDR_4_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_IDR_4__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDR_4__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_IDR_4__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_4__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_IDR_4__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_IDR_4__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDR_4__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDR_4__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_IDR_4__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_IDR_4__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_IDR_4__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_IDR_4__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_IDR_4__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_IDR_4__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_IDR_4__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_IDR_4__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDR_4__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDR_4__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_IDR_4__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_IDR_4__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_IDR_4__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_IDR_4__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_IDR_4__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_IDR_4__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDR_4__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDR_4__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_IDR_4__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_IDR_4__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_IDR_4__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_4__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_IDR_4__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_IDR_4__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDR_4__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDR_4__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_IDR_4__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_IDR_4__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_IDR_4__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_IDR_4__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_IDR_4__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_4__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_IDR_4__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_IDR_4__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDR_4__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDR_4__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_IDR_4__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_IDR_4__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_IDR_4__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_IDR_4__TYPE uint32_t +#define SHUB_PORT0_I2C_IDR_4__READ 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_4__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_4__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_4__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_IDR_4_MACRO__ */ + +/** @} end of port0_i2c_idr_4 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_idr_5 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_idr_5 port0_i2c_idr_5 + * @brief id(read) of sensor5 on port0 prior to data read definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_IDR_5_MACRO__ +#define __SHUB_PORT0_I2C_IDR_5_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_IDR_5__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDR_5__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_IDR_5__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_5__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_IDR_5__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_IDR_5__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDR_5__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDR_5__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_IDR_5__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_IDR_5__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_IDR_5__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_IDR_5__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_IDR_5__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_IDR_5__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_IDR_5__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_IDR_5__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDR_5__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDR_5__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_IDR_5__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_IDR_5__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_IDR_5__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_IDR_5__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_IDR_5__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_IDR_5__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDR_5__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDR_5__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_IDR_5__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_IDR_5__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_IDR_5__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_5__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_IDR_5__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_IDR_5__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDR_5__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDR_5__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_IDR_5__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_IDR_5__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_IDR_5__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_IDR_5__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_IDR_5__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_5__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_IDR_5__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_IDR_5__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDR_5__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDR_5__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_IDR_5__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_IDR_5__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_IDR_5__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_IDR_5__TYPE uint32_t +#define SHUB_PORT0_I2C_IDR_5__READ 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_5__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_5__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_5__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_IDR_5_MACRO__ */ + +/** @} end of port0_i2c_idr_5 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_idr_6 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_idr_6 port0_i2c_idr_6 + * @brief id(read) of sensor6 on port0 prior to data read definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_IDR_6_MACRO__ +#define __SHUB_PORT0_I2C_IDR_6_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_IDR_6__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDR_6__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_IDR_6__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_6__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_IDR_6__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_IDR_6__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDR_6__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDR_6__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_IDR_6__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_IDR_6__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_IDR_6__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_IDR_6__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_IDR_6__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_IDR_6__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_IDR_6__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_IDR_6__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDR_6__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDR_6__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_IDR_6__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_IDR_6__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_IDR_6__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_IDR_6__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_IDR_6__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_IDR_6__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDR_6__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDR_6__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_IDR_6__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_IDR_6__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_IDR_6__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_6__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_IDR_6__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_IDR_6__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDR_6__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDR_6__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_IDR_6__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_IDR_6__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_IDR_6__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_IDR_6__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_IDR_6__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_6__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_IDR_6__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_IDR_6__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDR_6__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDR_6__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_IDR_6__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_IDR_6__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_IDR_6__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_IDR_6__TYPE uint32_t +#define SHUB_PORT0_I2C_IDR_6__READ 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_6__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_6__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_6__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_IDR_6_MACRO__ */ + +/** @} end of port0_i2c_idr_6 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_idr_7 */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_idr_7 port0_i2c_idr_7 + * @brief id(read) of sensor7 on port0 prior to data read definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_IDR_7_MACRO__ +#define __SHUB_PORT0_I2C_IDR_7_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_IDR_7__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_IDR_7__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_IDR_7__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_7__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_IDR_7__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_IDR_7__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDR_7__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_IDR_7__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_IDR_7__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_IDR_7__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_IDR_7__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_IDR_7__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_IDR_7__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_IDR_7__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_IDR_7__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_IDR_7__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDR_7__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_IDR_7__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_IDR_7__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_IDR_7__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_IDR_7__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_IDR_7__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_IDR_7__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_IDR_7__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDR_7__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_IDR_7__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_IDR_7__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_IDR_7__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_IDR_7__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_7__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_IDR_7__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_IDR_7__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDR_7__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_IDR_7__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_IDR_7__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_IDR_7__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_IDR_7__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_IDR_7__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_IDR_7__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_IDR_7__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_IDR_7__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_IDR_7__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDR_7__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_IDR_7__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_IDR_7__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_IDR_7__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_IDR_7__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_IDR_7__TYPE uint32_t +#define SHUB_PORT0_I2C_IDR_7__READ 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_7__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_7__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_IDR_7__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_IDR_7_MACRO__ */ + +/** @} end of port0_i2c_idr_7 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_dat_ctrl */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_dat_ctrl port0_i2c_dat_ctrl + * @brief slave(port0) data byte read (used in not the last byte) definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_DAT_CTRL_MACRO__ +#define __SHUB_PORT0_I2C_DAT_CTRL_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_DAT_CTRL__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE \ + 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_DAT_CTRL__TYPE uint32_t +#define SHUB_PORT0_I2C_DAT_CTRL__READ 0x01ffffffU +#define SHUB_PORT0_I2C_DAT_CTRL__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_DAT_CTRL__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_DAT_CTRL__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_DAT_CTRL_MACRO__ */ + +/** @} end of port0_i2c_dat_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_i2c_dat_last_ctrl */ +/** + * @defgroup at_apb_shub_regs_core_port0_i2c_dat_last_ctrl port0_i2c_dat_last_ctrl + * @brief slave(port0) data byte read (used in the last byte) definitions. + * @{ + */ +#ifndef __SHUB_PORT0_I2C_DAT_LAST_CTRL_MACRO__ +#define __SHUB_PORT0_I2C_DAT_LAST_CTRL_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_HEAD__SHIFT 19 +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_HEAD__WIDTH 2 +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_TAIL__SHIFT 21 +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_TAIL__WIDTH 2 +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_MASTER_DRIVES_ACK__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE \ + 0x00000000U +/** @} */ +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__TYPE uint32_t +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__READ 0x01ffffffU +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__WRITE 0x01ffffffU +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__PRESERVED 0x01ffffffU +#define SHUB_PORT0_I2C_DAT_LAST_CTRL__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT0_I2C_DAT_LAST_CTRL_MACRO__ */ + +/** @} end of port0_i2c_dat_last_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_alm0_quan_ctrl */ +/** + * @defgroup at_apb_shub_regs_core_port0_alm0_quan_ctrl port0_alm0_quan_ctrl + * @brief alarm0 quantity's definition definitions. + * @{ + */ +#ifndef __SHUB_PORT0_ALM0_QUAN_CTRL_MACRO__ +#define __SHUB_PORT0_ALM0_QUAN_CTRL_MACRO__ + +/* macros for field quan0_pos */ +/** + * @defgroup at_apb_shub_regs_core_quan0_pos_field quan0_pos_field + * @brief macros for field quan0_pos + * @{ + */ +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN0_POS__SHIFT 0 +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN0_POS__WIDTH 5 +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN0_POS__MASK 0x0000001fU +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN0_POS__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN0_POS__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN0_POS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN0_POS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN0_POS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field quan1_pos */ +/** + * @defgroup at_apb_shub_regs_core_quan1_pos_field quan1_pos_field + * @brief macros for field quan1_pos + * @{ + */ +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN1_POS__SHIFT 5 +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN1_POS__WIDTH 5 +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN1_POS__MASK 0x000003e0U +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN1_POS__READ(src) \ + (((uint32_t)(src)\ + & 0x000003e0U) >> 5) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN1_POS__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x000003e0U) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN1_POS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((uint32_t)(src) <<\ + 5) & 0x000003e0U) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN1_POS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000003e0U))) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN1_POS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field quan2_pos */ +/** + * @defgroup at_apb_shub_regs_core_quan2_pos_field quan2_pos_field + * @brief macros for field quan2_pos + * @{ + */ +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN2_POS__SHIFT 10 +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN2_POS__WIDTH 5 +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN2_POS__MASK 0x00007c00U +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN2_POS__READ(src) \ + (((uint32_t)(src)\ + & 0x00007c00U) >> 10) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN2_POS__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00007c00U) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN2_POS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((uint32_t)(src) <<\ + 10) & 0x00007c00U) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN2_POS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00007c00U))) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN2_POS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field quan3_pos */ +/** + * @defgroup at_apb_shub_regs_core_quan3_pos_field quan3_pos_field + * @brief macros for field quan3_pos + * @details starting position of the quantity + * @{ + */ +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN3_POS__SHIFT 15 +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN3_POS__WIDTH 5 +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN3_POS__MASK 0x000f8000U +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN3_POS__READ(src) \ + (((uint32_t)(src)\ + & 0x000f8000U) >> 15) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN3_POS__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x000f8000U) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN3_POS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((uint32_t)(src) <<\ + 15) & 0x000f8000U) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN3_POS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x000f8000U))) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN3_POS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field quan0_size */ +/** + * @defgroup at_apb_shub_regs_core_quan0_size_field quan0_size_field + * @brief macros for field quan0_size + * @{ + */ +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN0_SIZE__SHIFT 20 +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN0_SIZE__WIDTH 2 +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN0_SIZE__MASK 0x00300000U +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN0_SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0x00300000U) >> 20) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN0_SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00300000U) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN0_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00300000U) | (((uint32_t)(src) <<\ + 20) & 0x00300000U) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN0_SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00300000U))) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN0_SIZE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field quan1_size */ +/** + * @defgroup at_apb_shub_regs_core_quan1_size_field quan1_size_field + * @brief macros for field quan1_size + * @{ + */ +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN1_SIZE__SHIFT 22 +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN1_SIZE__WIDTH 2 +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN1_SIZE__MASK 0x00c00000U +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN1_SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0x00c00000U) >> 22) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN1_SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00c00000U) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN1_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00c00000U) | (((uint32_t)(src) <<\ + 22) & 0x00c00000U) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN1_SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00c00000U))) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN1_SIZE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field quan2_size */ +/** + * @defgroup at_apb_shub_regs_core_quan2_size_field quan2_size_field + * @brief macros for field quan2_size + * @{ + */ +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN2_SIZE__SHIFT 24 +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN2_SIZE__WIDTH 2 +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN2_SIZE__MASK 0x03000000U +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN2_SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0x03000000U) >> 24) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN2_SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x03000000U) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN2_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((uint32_t)(src) <<\ + 24) & 0x03000000U) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN2_SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x03000000U))) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN2_SIZE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field quan3_size */ +/** + * @defgroup at_apb_shub_regs_core_quan3_size_field quan3_size_field + * @brief macros for field quan3_size + * @details number of bytes making up the quantity data = programmed quan3_size + 1 + * @{ + */ +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN3_SIZE__SHIFT 26 +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN3_SIZE__WIDTH 2 +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN3_SIZE__MASK 0x0c000000U +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN3_SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0x0c000000U) >> 26) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN3_SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x0c000000U) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN3_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((uint32_t)(src) <<\ + 26) & 0x0c000000U) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN3_SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x0c000000U))) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN3_SIZE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field lsb_first */ +/** + * @defgroup at_apb_shub_regs_core_lsb_first_field lsb_first_field + * @brief macros for field lsb_first + * @details 1= quantity data is big endian ; 0= small endian + * @{ + */ +#define SHUB_PORT0_ALM0_QUAN_CTRL__LSB_FIRST__SHIFT 30 +#define SHUB_PORT0_ALM0_QUAN_CTRL__LSB_FIRST__WIDTH 1 +#define SHUB_PORT0_ALM0_QUAN_CTRL__LSB_FIRST__MASK 0x40000000U +#define SHUB_PORT0_ALM0_QUAN_CTRL__LSB_FIRST__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define SHUB_PORT0_ALM0_QUAN_CTRL__LSB_FIRST__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define SHUB_PORT0_ALM0_QUAN_CTRL__LSB_FIRST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define SHUB_PORT0_ALM0_QUAN_CTRL__LSB_FIRST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define SHUB_PORT0_ALM0_QUAN_CTRL__LSB_FIRST__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define SHUB_PORT0_ALM0_QUAN_CTRL__LSB_FIRST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define SHUB_PORT0_ALM0_QUAN_CTRL__LSB_FIRST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field quan_dat_is_signed */ +/** + * @defgroup at_apb_shub_regs_core_quan_dat_is_signed_field quan_dat_is_signed_field + * @brief macros for field quan_dat_is_signed + * @details quantity data is a signed data + * @{ + */ +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN_DAT_IS_SIGNED__SHIFT 31 +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN_DAT_IS_SIGNED__WIDTH 1 +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN_DAT_IS_SIGNED__MASK 0x80000000U +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN_DAT_IS_SIGNED__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN_DAT_IS_SIGNED__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN_DAT_IS_SIGNED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN_DAT_IS_SIGNED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN_DAT_IS_SIGNED__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN_DAT_IS_SIGNED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define SHUB_PORT0_ALM0_QUAN_CTRL__QUAN_DAT_IS_SIGNED__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_ALM0_QUAN_CTRL__TYPE uint32_t +#define SHUB_PORT0_ALM0_QUAN_CTRL__READ 0xcfffffffU +#define SHUB_PORT0_ALM0_QUAN_CTRL__WRITE 0xcfffffffU +#define SHUB_PORT0_ALM0_QUAN_CTRL__PRESERVED 0xcfffffffU +#define SHUB_PORT0_ALM0_QUAN_CTRL__RESET_VALUE 0x05500000U + +#endif /* __SHUB_PORT0_ALM0_QUAN_CTRL_MACRO__ */ + +/** @} end of port0_alm0_quan_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_alm1_quan_ctrl */ +/** + * @defgroup at_apb_shub_regs_core_port0_alm1_quan_ctrl port0_alm1_quan_ctrl + * @brief alarm1 quantity's definition definitions. + * @{ + */ +#ifndef __SHUB_PORT0_ALM1_QUAN_CTRL_MACRO__ +#define __SHUB_PORT0_ALM1_QUAN_CTRL_MACRO__ + +/* macros for field quan0_pos */ +/** + * @defgroup at_apb_shub_regs_core_quan0_pos_field quan0_pos_field + * @brief macros for field quan0_pos + * @{ + */ +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN0_POS__SHIFT 0 +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN0_POS__WIDTH 5 +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN0_POS__MASK 0x0000001fU +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN0_POS__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN0_POS__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN0_POS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN0_POS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN0_POS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field quan1_pos */ +/** + * @defgroup at_apb_shub_regs_core_quan1_pos_field quan1_pos_field + * @brief macros for field quan1_pos + * @{ + */ +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN1_POS__SHIFT 5 +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN1_POS__WIDTH 5 +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN1_POS__MASK 0x000003e0U +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN1_POS__READ(src) \ + (((uint32_t)(src)\ + & 0x000003e0U) >> 5) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN1_POS__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x000003e0U) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN1_POS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((uint32_t)(src) <<\ + 5) & 0x000003e0U) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN1_POS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000003e0U))) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN1_POS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field quan2_pos */ +/** + * @defgroup at_apb_shub_regs_core_quan2_pos_field quan2_pos_field + * @brief macros for field quan2_pos + * @{ + */ +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN2_POS__SHIFT 10 +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN2_POS__WIDTH 5 +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN2_POS__MASK 0x00007c00U +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN2_POS__READ(src) \ + (((uint32_t)(src)\ + & 0x00007c00U) >> 10) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN2_POS__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00007c00U) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN2_POS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((uint32_t)(src) <<\ + 10) & 0x00007c00U) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN2_POS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00007c00U))) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN2_POS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field quan3_pos */ +/** + * @defgroup at_apb_shub_regs_core_quan3_pos_field quan3_pos_field + * @brief macros for field quan3_pos + * @details starting position of the quantity + * @{ + */ +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN3_POS__SHIFT 15 +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN3_POS__WIDTH 5 +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN3_POS__MASK 0x000f8000U +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN3_POS__READ(src) \ + (((uint32_t)(src)\ + & 0x000f8000U) >> 15) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN3_POS__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x000f8000U) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN3_POS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((uint32_t)(src) <<\ + 15) & 0x000f8000U) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN3_POS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x000f8000U))) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN3_POS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field quan0_size */ +/** + * @defgroup at_apb_shub_regs_core_quan0_size_field quan0_size_field + * @brief macros for field quan0_size + * @{ + */ +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN0_SIZE__SHIFT 20 +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN0_SIZE__WIDTH 2 +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN0_SIZE__MASK 0x00300000U +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN0_SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0x00300000U) >> 20) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN0_SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00300000U) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN0_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00300000U) | (((uint32_t)(src) <<\ + 20) & 0x00300000U) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN0_SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00300000U))) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN0_SIZE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field quan1_size */ +/** + * @defgroup at_apb_shub_regs_core_quan1_size_field quan1_size_field + * @brief macros for field quan1_size + * @{ + */ +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN1_SIZE__SHIFT 22 +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN1_SIZE__WIDTH 2 +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN1_SIZE__MASK 0x00c00000U +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN1_SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0x00c00000U) >> 22) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN1_SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00c00000U) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN1_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00c00000U) | (((uint32_t)(src) <<\ + 22) & 0x00c00000U) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN1_SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00c00000U))) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN1_SIZE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field quan2_size */ +/** + * @defgroup at_apb_shub_regs_core_quan2_size_field quan2_size_field + * @brief macros for field quan2_size + * @{ + */ +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN2_SIZE__SHIFT 24 +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN2_SIZE__WIDTH 2 +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN2_SIZE__MASK 0x03000000U +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN2_SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0x03000000U) >> 24) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN2_SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x03000000U) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN2_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((uint32_t)(src) <<\ + 24) & 0x03000000U) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN2_SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x03000000U))) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN2_SIZE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field quan3_size */ +/** + * @defgroup at_apb_shub_regs_core_quan3_size_field quan3_size_field + * @brief macros for field quan3_size + * @details number of bytes making up the quantity data = programmed quan3_size + 1 + * @{ + */ +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN3_SIZE__SHIFT 26 +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN3_SIZE__WIDTH 2 +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN3_SIZE__MASK 0x0c000000U +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN3_SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0x0c000000U) >> 26) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN3_SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x0c000000U) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN3_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((uint32_t)(src) <<\ + 26) & 0x0c000000U) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN3_SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x0c000000U))) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN3_SIZE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field lsb_first */ +/** + * @defgroup at_apb_shub_regs_core_lsb_first_field lsb_first_field + * @brief macros for field lsb_first + * @details 1= quantity data is big endian ; 0= small endian + * @{ + */ +#define SHUB_PORT0_ALM1_QUAN_CTRL__LSB_FIRST__SHIFT 30 +#define SHUB_PORT0_ALM1_QUAN_CTRL__LSB_FIRST__WIDTH 1 +#define SHUB_PORT0_ALM1_QUAN_CTRL__LSB_FIRST__MASK 0x40000000U +#define SHUB_PORT0_ALM1_QUAN_CTRL__LSB_FIRST__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define SHUB_PORT0_ALM1_QUAN_CTRL__LSB_FIRST__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define SHUB_PORT0_ALM1_QUAN_CTRL__LSB_FIRST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define SHUB_PORT0_ALM1_QUAN_CTRL__LSB_FIRST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define SHUB_PORT0_ALM1_QUAN_CTRL__LSB_FIRST__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define SHUB_PORT0_ALM1_QUAN_CTRL__LSB_FIRST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define SHUB_PORT0_ALM1_QUAN_CTRL__LSB_FIRST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field quan_dat_is_signed */ +/** + * @defgroup at_apb_shub_regs_core_quan_dat_is_signed_field quan_dat_is_signed_field + * @brief macros for field quan_dat_is_signed + * @details quantity data is a signed data + * @{ + */ +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN_DAT_IS_SIGNED__SHIFT 31 +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN_DAT_IS_SIGNED__WIDTH 1 +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN_DAT_IS_SIGNED__MASK 0x80000000U +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN_DAT_IS_SIGNED__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN_DAT_IS_SIGNED__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN_DAT_IS_SIGNED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN_DAT_IS_SIGNED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN_DAT_IS_SIGNED__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN_DAT_IS_SIGNED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define SHUB_PORT0_ALM1_QUAN_CTRL__QUAN_DAT_IS_SIGNED__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_ALM1_QUAN_CTRL__TYPE uint32_t +#define SHUB_PORT0_ALM1_QUAN_CTRL__READ 0xcfffffffU +#define SHUB_PORT0_ALM1_QUAN_CTRL__WRITE 0xcfffffffU +#define SHUB_PORT0_ALM1_QUAN_CTRL__PRESERVED 0xcfffffffU +#define SHUB_PORT0_ALM1_QUAN_CTRL__RESET_VALUE 0x05500000U + +#endif /* __SHUB_PORT0_ALM1_QUAN_CTRL_MACRO__ */ + +/** @} end of port0_alm1_quan_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_alm0_trig_ctrl */ +/** + * @defgroup at_apb_shub_regs_core_port0_alm0_trig_ctrl port0_alm0_trig_ctrl + * @brief alarm0 trigger function: trigger = trig_func_en( out_of_range(quan3), out_of_range(quan2),out_of_range(quan1),out_of_range(quan0)) definitions. + * @{ + */ +#ifndef __SHUB_PORT0_ALM0_TRIG_CTRL_MACRO__ +#define __SHUB_PORT0_ALM0_TRIG_CTRL_MACRO__ + +/* macros for field trig_func_en */ +/** + * @defgroup at_apb_shub_regs_core_trig_func_en_field trig_func_en_field + * @brief macros for field trig_func_en + * @{ + */ +#define SHUB_PORT0_ALM0_TRIG_CTRL__TRIG_FUNC_EN__SHIFT 0 +#define SHUB_PORT0_ALM0_TRIG_CTRL__TRIG_FUNC_EN__WIDTH 16 +#define SHUB_PORT0_ALM0_TRIG_CTRL__TRIG_FUNC_EN__MASK 0x0000ffffU +#define SHUB_PORT0_ALM0_TRIG_CTRL__TRIG_FUNC_EN__READ(src) \ + ((uint32_t)(src)\ + & 0x0000ffffU) +#define SHUB_PORT0_ALM0_TRIG_CTRL__TRIG_FUNC_EN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000ffffU) +#define SHUB_PORT0_ALM0_TRIG_CTRL__TRIG_FUNC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define SHUB_PORT0_ALM0_TRIG_CTRL__TRIG_FUNC_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000ffffU))) +#define SHUB_PORT0_ALM0_TRIG_CTRL__TRIG_FUNC_EN__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_ALM0_TRIG_CTRL__TYPE uint32_t +#define SHUB_PORT0_ALM0_TRIG_CTRL__READ 0x0000ffffU +#define SHUB_PORT0_ALM0_TRIG_CTRL__WRITE 0x0000ffffU +#define SHUB_PORT0_ALM0_TRIG_CTRL__PRESERVED 0x0000ffffU +#define SHUB_PORT0_ALM0_TRIG_CTRL__RESET_VALUE 0x00000000U + +#endif /* __SHUB_PORT0_ALM0_TRIG_CTRL_MACRO__ */ + +/** @} end of port0_alm0_trig_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_alm1_trig_ctrl */ +/** + * @defgroup at_apb_shub_regs_core_port0_alm1_trig_ctrl port0_alm1_trig_ctrl + * @brief alarm1 trigger function: trigger = trig_func_en( out_of_range(quan3), out_of_range(quan2),out_of_range(quan1),out_of_range(quan0)) definitions. + * @{ + */ +#ifndef __SHUB_PORT0_ALM1_TRIG_CTRL_MACRO__ +#define __SHUB_PORT0_ALM1_TRIG_CTRL_MACRO__ + +/* macros for field trig_func_en */ +/** + * @defgroup at_apb_shub_regs_core_trig_func_en_field trig_func_en_field + * @brief macros for field trig_func_en + * @{ + */ +#define SHUB_PORT0_ALM1_TRIG_CTRL__TRIG_FUNC_EN__SHIFT 0 +#define SHUB_PORT0_ALM1_TRIG_CTRL__TRIG_FUNC_EN__WIDTH 16 +#define SHUB_PORT0_ALM1_TRIG_CTRL__TRIG_FUNC_EN__MASK 0x0000ffffU +#define SHUB_PORT0_ALM1_TRIG_CTRL__TRIG_FUNC_EN__READ(src) \ + ((uint32_t)(src)\ + & 0x0000ffffU) +#define SHUB_PORT0_ALM1_TRIG_CTRL__TRIG_FUNC_EN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000ffffU) +#define SHUB_PORT0_ALM1_TRIG_CTRL__TRIG_FUNC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define SHUB_PORT0_ALM1_TRIG_CTRL__TRIG_FUNC_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000ffffU))) +#define SHUB_PORT0_ALM1_TRIG_CTRL__TRIG_FUNC_EN__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_ALM1_TRIG_CTRL__TYPE uint32_t +#define SHUB_PORT0_ALM1_TRIG_CTRL__READ 0x0000ffffU +#define SHUB_PORT0_ALM1_TRIG_CTRL__WRITE 0x0000ffffU +#define SHUB_PORT0_ALM1_TRIG_CTRL__PRESERVED 0x0000ffffU +#define SHUB_PORT0_ALM1_TRIG_CTRL__RESET_VALUE 0x00000000U + +#endif /* __SHUB_PORT0_ALM1_TRIG_CTRL_MACRO__ */ + +/** @} end of port0_alm1_trig_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_alm0_thrhld_max_0 */ +/** + * @defgroup at_apb_shub_regs_core_port0_alm0_thrhld_max_0 port0_alm0_thrhld_max_0 + * @brief threshold of sensor results definitions. + * @{ + */ +#ifndef __SHUB_PORT0_ALM0_THRHLD_MAX_0_MACRO__ +#define __SHUB_PORT0_ALM0_THRHLD_MAX_0_MACRO__ + +/* macros for field byte_max_00 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_00_field byte_max_00_field + * @brief macros for field byte_max_00 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_00__SHIFT 0 +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_00__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_00__MASK 0x000000ffU +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_00__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_00__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_00__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_00__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_00__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_01 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_01_field byte_max_01_field + * @brief macros for field byte_max_01 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_01__SHIFT 8 +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_01__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_01__MASK 0x0000ff00U +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_01__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_01__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_01__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_01__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_01__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_02 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_02_field byte_max_02_field + * @brief macros for field byte_max_02 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_02__SHIFT 16 +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_02__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_02__MASK 0x00ff0000U +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_02__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_02__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_02__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_02__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_02__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_03 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_03_field byte_max_03_field + * @brief macros for field byte_max_03 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_03__SHIFT 24 +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_03__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_03__MASK 0xff000000U +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_03__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_03__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_03__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_03__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__BYTE_MAX_03__RESET_VALUE 0x000000ffU +/** @} */ +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__TYPE uint32_t +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__READ 0xffffffffU +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__WRITE 0xffffffffU +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__PRESERVED 0xffffffffU +#define SHUB_PORT0_ALM0_THRHLD_MAX_0__RESET_VALUE 0xffffffffU + +#endif /* __SHUB_PORT0_ALM0_THRHLD_MAX_0_MACRO__ */ + +/** @} end of port0_alm0_thrhld_max_0 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_alm0_thrhld_max_1 */ +/** + * @defgroup at_apb_shub_regs_core_port0_alm0_thrhld_max_1 port0_alm0_thrhld_max_1 + * @brief threshold of sensor results definitions. + * @{ + */ +#ifndef __SHUB_PORT0_ALM0_THRHLD_MAX_1_MACRO__ +#define __SHUB_PORT0_ALM0_THRHLD_MAX_1_MACRO__ + +/* macros for field byte_max_04 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_04_field byte_max_04_field + * @brief macros for field byte_max_04 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_04__SHIFT 0 +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_04__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_04__MASK 0x000000ffU +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_04__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_04__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_04__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_04__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_04__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_05 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_05_field byte_max_05_field + * @brief macros for field byte_max_05 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_05__SHIFT 8 +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_05__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_05__MASK 0x0000ff00U +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_05__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_05__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_05__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_05__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_05__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_06 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_06_field byte_max_06_field + * @brief macros for field byte_max_06 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_06__SHIFT 16 +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_06__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_06__MASK 0x00ff0000U +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_06__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_06__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_06__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_06__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_06__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_07 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_07_field byte_max_07_field + * @brief macros for field byte_max_07 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_07__SHIFT 24 +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_07__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_07__MASK 0xff000000U +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_07__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_07__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_07__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_07__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__BYTE_MAX_07__RESET_VALUE 0x000000ffU +/** @} */ +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__TYPE uint32_t +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__READ 0xffffffffU +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__WRITE 0xffffffffU +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__PRESERVED 0xffffffffU +#define SHUB_PORT0_ALM0_THRHLD_MAX_1__RESET_VALUE 0xffffffffU + +#endif /* __SHUB_PORT0_ALM0_THRHLD_MAX_1_MACRO__ */ + +/** @} end of port0_alm0_thrhld_max_1 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_alm0_thrhld_max_2 */ +/** + * @defgroup at_apb_shub_regs_core_port0_alm0_thrhld_max_2 port0_alm0_thrhld_max_2 + * @brief threshold of sensor results definitions. + * @{ + */ +#ifndef __SHUB_PORT0_ALM0_THRHLD_MAX_2_MACRO__ +#define __SHUB_PORT0_ALM0_THRHLD_MAX_2_MACRO__ + +/* macros for field byte_max_08 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_08_field byte_max_08_field + * @brief macros for field byte_max_08 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_08__SHIFT 0 +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_08__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_08__MASK 0x000000ffU +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_08__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_08__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_08__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_08__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_08__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_09 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_09_field byte_max_09_field + * @brief macros for field byte_max_09 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_09__SHIFT 8 +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_09__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_09__MASK 0x0000ff00U +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_09__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_09__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_09__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_09__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_09__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_10 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_10_field byte_max_10_field + * @brief macros for field byte_max_10 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_10__SHIFT 16 +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_10__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_10__MASK 0x00ff0000U +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_10__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_10__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_10__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_10__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_11 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_11_field byte_max_11_field + * @brief macros for field byte_max_11 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_11__SHIFT 24 +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_11__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_11__MASK 0xff000000U +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_11__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_11__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_11__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__BYTE_MAX_11__RESET_VALUE 0x000000ffU +/** @} */ +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__TYPE uint32_t +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__READ 0xffffffffU +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__WRITE 0xffffffffU +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__PRESERVED 0xffffffffU +#define SHUB_PORT0_ALM0_THRHLD_MAX_2__RESET_VALUE 0xffffffffU + +#endif /* __SHUB_PORT0_ALM0_THRHLD_MAX_2_MACRO__ */ + +/** @} end of port0_alm0_thrhld_max_2 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_alm0_thrhld_min_0 */ +/** + * @defgroup at_apb_shub_regs_core_port0_alm0_thrhld_min_0 port0_alm0_thrhld_min_0 + * @brief threshold of sensor results definitions. + * @{ + */ +#ifndef __SHUB_PORT0_ALM0_THRHLD_MIN_0_MACRO__ +#define __SHUB_PORT0_ALM0_THRHLD_MIN_0_MACRO__ + +/* macros for field byte_min_00 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_00_field byte_min_00_field + * @brief macros for field byte_min_00 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_00__SHIFT 0 +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_00__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_00__MASK 0x000000ffU +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_00__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_00__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_00__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_00__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_00__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_01 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_01_field byte_min_01_field + * @brief macros for field byte_min_01 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_01__SHIFT 8 +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_01__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_01__MASK 0x0000ff00U +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_01__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_01__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_01__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_01__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_01__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_02 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_02_field byte_min_02_field + * @brief macros for field byte_min_02 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_02__SHIFT 16 +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_02__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_02__MASK 0x00ff0000U +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_02__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_02__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_02__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_02__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_02__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_03 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_03_field byte_min_03_field + * @brief macros for field byte_min_03 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_03__SHIFT 24 +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_03__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_03__MASK 0xff000000U +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_03__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_03__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_03__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_03__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__BYTE_MIN_03__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__TYPE uint32_t +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__READ 0xffffffffU +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__WRITE 0xffffffffU +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__PRESERVED 0xffffffffU +#define SHUB_PORT0_ALM0_THRHLD_MIN_0__RESET_VALUE 0x00000000U + +#endif /* __SHUB_PORT0_ALM0_THRHLD_MIN_0_MACRO__ */ + +/** @} end of port0_alm0_thrhld_min_0 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_alm0_thrhld_min_1 */ +/** + * @defgroup at_apb_shub_regs_core_port0_alm0_thrhld_min_1 port0_alm0_thrhld_min_1 + * @brief threshold of sensor results definitions. + * @{ + */ +#ifndef __SHUB_PORT0_ALM0_THRHLD_MIN_1_MACRO__ +#define __SHUB_PORT0_ALM0_THRHLD_MIN_1_MACRO__ + +/* macros for field byte_min_04 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_04_field byte_min_04_field + * @brief macros for field byte_min_04 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_04__SHIFT 0 +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_04__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_04__MASK 0x000000ffU +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_04__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_04__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_04__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_04__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_04__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_05 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_05_field byte_min_05_field + * @brief macros for field byte_min_05 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_05__SHIFT 8 +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_05__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_05__MASK 0x0000ff00U +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_05__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_05__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_05__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_05__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_05__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_06 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_06_field byte_min_06_field + * @brief macros for field byte_min_06 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_06__SHIFT 16 +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_06__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_06__MASK 0x00ff0000U +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_06__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_06__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_06__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_06__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_06__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_07 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_07_field byte_min_07_field + * @brief macros for field byte_min_07 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_07__SHIFT 24 +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_07__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_07__MASK 0xff000000U +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_07__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_07__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_07__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_07__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__BYTE_MIN_07__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__TYPE uint32_t +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__READ 0xffffffffU +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__WRITE 0xffffffffU +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__PRESERVED 0xffffffffU +#define SHUB_PORT0_ALM0_THRHLD_MIN_1__RESET_VALUE 0x00000000U + +#endif /* __SHUB_PORT0_ALM0_THRHLD_MIN_1_MACRO__ */ + +/** @} end of port0_alm0_thrhld_min_1 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_alm0_thrhld_min_2 */ +/** + * @defgroup at_apb_shub_regs_core_port0_alm0_thrhld_min_2 port0_alm0_thrhld_min_2 + * @brief threshold of sensor results definitions. + * @{ + */ +#ifndef __SHUB_PORT0_ALM0_THRHLD_MIN_2_MACRO__ +#define __SHUB_PORT0_ALM0_THRHLD_MIN_2_MACRO__ + +/* macros for field byte_min_08 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_08_field byte_min_08_field + * @brief macros for field byte_min_08 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_08__SHIFT 0 +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_08__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_08__MASK 0x000000ffU +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_08__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_08__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_08__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_08__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_08__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_09 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_09_field byte_min_09_field + * @brief macros for field byte_min_09 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_09__SHIFT 8 +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_09__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_09__MASK 0x0000ff00U +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_09__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_09__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_09__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_09__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_09__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_10 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_10_field byte_min_10_field + * @brief macros for field byte_min_10 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_10__SHIFT 16 +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_10__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_10__MASK 0x00ff0000U +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_10__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_10__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_10__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_10__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_11 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_11_field byte_min_11_field + * @brief macros for field byte_min_11 + * @{ + */ +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_11__SHIFT 24 +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_11__WIDTH 8 +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_11__MASK 0xff000000U +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_11__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_11__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_11__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__BYTE_MIN_11__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__TYPE uint32_t +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__READ 0xffffffffU +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__WRITE 0xffffffffU +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__PRESERVED 0xffffffffU +#define SHUB_PORT0_ALM0_THRHLD_MIN_2__RESET_VALUE 0x00000000U + +#endif /* __SHUB_PORT0_ALM0_THRHLD_MIN_2_MACRO__ */ + +/** @} end of port0_alm0_thrhld_min_2 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_alm1_thrhld_max_0 */ +/** + * @defgroup at_apb_shub_regs_core_port0_alm1_thrhld_max_0 port0_alm1_thrhld_max_0 + * @brief threshold of sensor results definitions. + * @{ + */ +#ifndef __SHUB_PORT0_ALM1_THRHLD_MAX_0_MACRO__ +#define __SHUB_PORT0_ALM1_THRHLD_MAX_0_MACRO__ + +/* macros for field byte_max_00 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_00_field byte_max_00_field + * @brief macros for field byte_max_00 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_00__SHIFT 0 +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_00__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_00__MASK 0x000000ffU +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_00__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_00__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_00__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_00__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_00__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_01 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_01_field byte_max_01_field + * @brief macros for field byte_max_01 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_01__SHIFT 8 +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_01__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_01__MASK 0x0000ff00U +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_01__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_01__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_01__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_01__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_01__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_02 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_02_field byte_max_02_field + * @brief macros for field byte_max_02 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_02__SHIFT 16 +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_02__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_02__MASK 0x00ff0000U +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_02__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_02__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_02__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_02__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_02__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_03 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_03_field byte_max_03_field + * @brief macros for field byte_max_03 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_03__SHIFT 24 +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_03__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_03__MASK 0xff000000U +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_03__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_03__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_03__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_03__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__BYTE_MAX_03__RESET_VALUE 0x000000ffU +/** @} */ +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__TYPE uint32_t +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__READ 0xffffffffU +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__WRITE 0xffffffffU +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__PRESERVED 0xffffffffU +#define SHUB_PORT0_ALM1_THRHLD_MAX_0__RESET_VALUE 0xffffffffU + +#endif /* __SHUB_PORT0_ALM1_THRHLD_MAX_0_MACRO__ */ + +/** @} end of port0_alm1_thrhld_max_0 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_alm1_thrhld_max_1 */ +/** + * @defgroup at_apb_shub_regs_core_port0_alm1_thrhld_max_1 port0_alm1_thrhld_max_1 + * @brief threshold of sensor results definitions. + * @{ + */ +#ifndef __SHUB_PORT0_ALM1_THRHLD_MAX_1_MACRO__ +#define __SHUB_PORT0_ALM1_THRHLD_MAX_1_MACRO__ + +/* macros for field byte_max_04 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_04_field byte_max_04_field + * @brief macros for field byte_max_04 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_04__SHIFT 0 +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_04__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_04__MASK 0x000000ffU +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_04__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_04__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_04__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_04__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_04__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_05 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_05_field byte_max_05_field + * @brief macros for field byte_max_05 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_05__SHIFT 8 +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_05__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_05__MASK 0x0000ff00U +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_05__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_05__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_05__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_05__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_05__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_06 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_06_field byte_max_06_field + * @brief macros for field byte_max_06 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_06__SHIFT 16 +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_06__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_06__MASK 0x00ff0000U +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_06__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_06__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_06__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_06__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_06__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_07 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_07_field byte_max_07_field + * @brief macros for field byte_max_07 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_07__SHIFT 24 +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_07__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_07__MASK 0xff000000U +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_07__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_07__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_07__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_07__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__BYTE_MAX_07__RESET_VALUE 0x000000ffU +/** @} */ +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__TYPE uint32_t +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__READ 0xffffffffU +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__WRITE 0xffffffffU +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__PRESERVED 0xffffffffU +#define SHUB_PORT0_ALM1_THRHLD_MAX_1__RESET_VALUE 0xffffffffU + +#endif /* __SHUB_PORT0_ALM1_THRHLD_MAX_1_MACRO__ */ + +/** @} end of port0_alm1_thrhld_max_1 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_alm1_thrhld_max_2 */ +/** + * @defgroup at_apb_shub_regs_core_port0_alm1_thrhld_max_2 port0_alm1_thrhld_max_2 + * @brief threshold of sensor results definitions. + * @{ + */ +#ifndef __SHUB_PORT0_ALM1_THRHLD_MAX_2_MACRO__ +#define __SHUB_PORT0_ALM1_THRHLD_MAX_2_MACRO__ + +/* macros for field byte_max_08 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_08_field byte_max_08_field + * @brief macros for field byte_max_08 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_08__SHIFT 0 +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_08__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_08__MASK 0x000000ffU +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_08__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_08__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_08__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_08__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_08__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_09 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_09_field byte_max_09_field + * @brief macros for field byte_max_09 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_09__SHIFT 8 +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_09__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_09__MASK 0x0000ff00U +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_09__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_09__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_09__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_09__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_09__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_10 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_10_field byte_max_10_field + * @brief macros for field byte_max_10 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_10__SHIFT 16 +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_10__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_10__MASK 0x00ff0000U +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_10__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_10__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_10__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_10__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_11 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_11_field byte_max_11_field + * @brief macros for field byte_max_11 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_11__SHIFT 24 +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_11__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_11__MASK 0xff000000U +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_11__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_11__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_11__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__BYTE_MAX_11__RESET_VALUE 0x000000ffU +/** @} */ +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__TYPE uint32_t +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__READ 0xffffffffU +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__WRITE 0xffffffffU +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__PRESERVED 0xffffffffU +#define SHUB_PORT0_ALM1_THRHLD_MAX_2__RESET_VALUE 0xffffffffU + +#endif /* __SHUB_PORT0_ALM1_THRHLD_MAX_2_MACRO__ */ + +/** @} end of port0_alm1_thrhld_max_2 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_alm1_thrhld_min_0 */ +/** + * @defgroup at_apb_shub_regs_core_port0_alm1_thrhld_min_0 port0_alm1_thrhld_min_0 + * @brief threshold of sensor results definitions. + * @{ + */ +#ifndef __SHUB_PORT0_ALM1_THRHLD_MIN_0_MACRO__ +#define __SHUB_PORT0_ALM1_THRHLD_MIN_0_MACRO__ + +/* macros for field byte_min_00 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_00_field byte_min_00_field + * @brief macros for field byte_min_00 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_00__SHIFT 0 +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_00__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_00__MASK 0x000000ffU +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_00__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_00__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_00__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_00__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_00__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_01 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_01_field byte_min_01_field + * @brief macros for field byte_min_01 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_01__SHIFT 8 +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_01__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_01__MASK 0x0000ff00U +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_01__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_01__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_01__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_01__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_01__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_02 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_02_field byte_min_02_field + * @brief macros for field byte_min_02 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_02__SHIFT 16 +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_02__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_02__MASK 0x00ff0000U +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_02__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_02__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_02__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_02__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_02__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_03 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_03_field byte_min_03_field + * @brief macros for field byte_min_03 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_03__SHIFT 24 +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_03__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_03__MASK 0xff000000U +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_03__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_03__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_03__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_03__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__BYTE_MIN_03__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__TYPE uint32_t +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__READ 0xffffffffU +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__WRITE 0xffffffffU +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__PRESERVED 0xffffffffU +#define SHUB_PORT0_ALM1_THRHLD_MIN_0__RESET_VALUE 0x00000000U + +#endif /* __SHUB_PORT0_ALM1_THRHLD_MIN_0_MACRO__ */ + +/** @} end of port0_alm1_thrhld_min_0 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_alm1_thrhld_min_1 */ +/** + * @defgroup at_apb_shub_regs_core_port0_alm1_thrhld_min_1 port0_alm1_thrhld_min_1 + * @brief threshold of sensor results definitions. + * @{ + */ +#ifndef __SHUB_PORT0_ALM1_THRHLD_MIN_1_MACRO__ +#define __SHUB_PORT0_ALM1_THRHLD_MIN_1_MACRO__ + +/* macros for field byte_min_04 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_04_field byte_min_04_field + * @brief macros for field byte_min_04 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_04__SHIFT 0 +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_04__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_04__MASK 0x000000ffU +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_04__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_04__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_04__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_04__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_04__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_05 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_05_field byte_min_05_field + * @brief macros for field byte_min_05 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_05__SHIFT 8 +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_05__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_05__MASK 0x0000ff00U +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_05__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_05__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_05__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_05__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_05__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_06 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_06_field byte_min_06_field + * @brief macros for field byte_min_06 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_06__SHIFT 16 +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_06__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_06__MASK 0x00ff0000U +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_06__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_06__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_06__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_06__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_06__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_07 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_07_field byte_min_07_field + * @brief macros for field byte_min_07 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_07__SHIFT 24 +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_07__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_07__MASK 0xff000000U +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_07__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_07__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_07__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_07__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__BYTE_MIN_07__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__TYPE uint32_t +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__READ 0xffffffffU +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__WRITE 0xffffffffU +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__PRESERVED 0xffffffffU +#define SHUB_PORT0_ALM1_THRHLD_MIN_1__RESET_VALUE 0x00000000U + +#endif /* __SHUB_PORT0_ALM1_THRHLD_MIN_1_MACRO__ */ + +/** @} end of port0_alm1_thrhld_min_1 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_alm1_thrhld_min_2 */ +/** + * @defgroup at_apb_shub_regs_core_port0_alm1_thrhld_min_2 port0_alm1_thrhld_min_2 + * @brief threshold of sensor results definitions. + * @{ + */ +#ifndef __SHUB_PORT0_ALM1_THRHLD_MIN_2_MACRO__ +#define __SHUB_PORT0_ALM1_THRHLD_MIN_2_MACRO__ + +/* macros for field byte_min_08 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_08_field byte_min_08_field + * @brief macros for field byte_min_08 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_08__SHIFT 0 +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_08__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_08__MASK 0x000000ffU +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_08__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_08__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_08__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_08__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_08__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_09 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_09_field byte_min_09_field + * @brief macros for field byte_min_09 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_09__SHIFT 8 +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_09__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_09__MASK 0x0000ff00U +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_09__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_09__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_09__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_09__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_09__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_10 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_10_field byte_min_10_field + * @brief macros for field byte_min_10 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_10__SHIFT 16 +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_10__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_10__MASK 0x00ff0000U +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_10__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_10__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_10__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_10__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_11 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_11_field byte_min_11_field + * @brief macros for field byte_min_11 + * @{ + */ +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_11__SHIFT 24 +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_11__WIDTH 8 +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_11__MASK 0xff000000U +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_11__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_11__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_11__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__BYTE_MIN_11__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__TYPE uint32_t +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__READ 0xffffffffU +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__WRITE 0xffffffffU +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__PRESERVED 0xffffffffU +#define SHUB_PORT0_ALM1_THRHLD_MIN_2__RESET_VALUE 0x00000000U + +#endif /* __SHUB_PORT0_ALM1_THRHLD_MIN_2_MACRO__ */ + +/** @} end of port0_alm1_thrhld_min_2 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port0_status */ +/** + * @defgroup at_apb_shub_regs_core_port0_status port0_status + * @brief Contains register fields associated with port0_status. definitions. + * @{ + */ +#ifndef __SHUB_PORT0_STATUS_MACRO__ +#define __SHUB_PORT0_STATUS_MACRO__ + +/* macros for field out_of_range_stat */ +/** + * @defgroup at_apb_shub_regs_core_out_of_range_stat_field out_of_range_stat_field + * @brief macros for field out_of_range_stat + * @{ + */ +#define SHUB_PORT0_STATUS__OUT_OF_RANGE_STAT__SHIFT 0 +#define SHUB_PORT0_STATUS__OUT_OF_RANGE_STAT__WIDTH 4 +#define SHUB_PORT0_STATUS__OUT_OF_RANGE_STAT__MASK 0x0000000fU +#define SHUB_PORT0_STATUS__OUT_OF_RANGE_STAT__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define SHUB_PORT0_STATUS__OUT_OF_RANGE_STAT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field triggered */ +/** + * @defgroup at_apb_shub_regs_core_triggered_field triggered_field + * @brief macros for field triggered + * @{ + */ +#define SHUB_PORT0_STATUS__TRIGGERED__SHIFT 24 +#define SHUB_PORT0_STATUS__TRIGGERED__WIDTH 1 +#define SHUB_PORT0_STATUS__TRIGGERED__MASK 0x01000000U +#define SHUB_PORT0_STATUS__TRIGGERED__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT0_STATUS__TRIGGERED__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT0_STATUS__TRIGGERED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT0_STATUS__TRIGGERED__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT0_STATUS__TYPE uint32_t +#define SHUB_PORT0_STATUS__READ 0x0100000fU +#define SHUB_PORT0_STATUS__PRESERVED 0x00000000U +#define SHUB_PORT0_STATUS__RESET_VALUE 0x00000000U + +#endif /* __SHUB_PORT0_STATUS_MACRO__ */ + +/** @} end of port0_status */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port1_setup */ +/** + * @defgroup at_apb_shub_regs_core_port1_setup port1_setup + * @brief Contains register fields associated with port1_setup. definitions. + * @{ + */ +#ifndef __SHUB_PORT1_SETUP_MACRO__ +#define __SHUB_PORT1_SETUP_MACRO__ + +/* macros for field port_en */ +/** + * @defgroup at_apb_shub_regs_core_port_en_field port_en_field + * @brief macros for field port_en + * @{ + */ +#define SHUB_PORT1_SETUP__PORT_EN__SHIFT 0 +#define SHUB_PORT1_SETUP__PORT_EN__WIDTH 1 +#define SHUB_PORT1_SETUP__PORT_EN__MASK 0x00000001U +#define SHUB_PORT1_SETUP__PORT_EN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define SHUB_PORT1_SETUP__PORT_EN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define SHUB_PORT1_SETUP__PORT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT1_SETUP__PORT_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT1_SETUP__PORT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT1_SETUP__PORT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT1_SETUP__PORT_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field spi_n_i2c */ +/** + * @defgroup at_apb_shub_regs_core_spi_n_i2c_field spi_n_i2c_field + * @brief macros for field spi_n_i2c + * @details 1= use spi for port0, 0= use i2c + * @{ + */ +#define SHUB_PORT1_SETUP__SPI_N_I2C__SHIFT 1 +#define SHUB_PORT1_SETUP__SPI_N_I2C__WIDTH 1 +#define SHUB_PORT1_SETUP__SPI_N_I2C__MASK 0x00000002U +#define SHUB_PORT1_SETUP__SPI_N_I2C__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define SHUB_PORT1_SETUP__SPI_N_I2C__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define SHUB_PORT1_SETUP__SPI_N_I2C__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define SHUB_PORT1_SETUP__SPI_N_I2C__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define SHUB_PORT1_SETUP__SPI_N_I2C__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SHUB_PORT1_SETUP__SPI_N_I2C__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SHUB_PORT1_SETUP__SPI_N_I2C__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field num_sensors */ +/** + * @defgroup at_apb_shub_regs_core_num_sensors_field num_sensors_field + * @brief macros for field num_sensors + * @details number of sensors connected to port = num_sensors + 1 + * @{ + */ +#define SHUB_PORT1_SETUP__NUM_SENSORS__SHIFT 4 +#define SHUB_PORT1_SETUP__NUM_SENSORS__WIDTH 3 +#define SHUB_PORT1_SETUP__NUM_SENSORS__MASK 0x00000070U +#define SHUB_PORT1_SETUP__NUM_SENSORS__READ(src) \ + (((uint32_t)(src)\ + & 0x00000070U) >> 4) +#define SHUB_PORT1_SETUP__NUM_SENSORS__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000070U) +#define SHUB_PORT1_SETUP__NUM_SENSORS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((uint32_t)(src) <<\ + 4) & 0x00000070U) +#define SHUB_PORT1_SETUP__NUM_SENSORS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000070U))) +#define SHUB_PORT1_SETUP__NUM_SENSORS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field trig_en */ +/** + * @defgroup at_apb_shub_regs_core_trig_en_field trig_en_field + * @brief macros for field trig_en + * @details 1= enable threshold comparison with measurement results. + * @{ + */ +#define SHUB_PORT1_SETUP__TRIG_EN__SHIFT 11 +#define SHUB_PORT1_SETUP__TRIG_EN__WIDTH 1 +#define SHUB_PORT1_SETUP__TRIG_EN__MASK 0x00000800U +#define SHUB_PORT1_SETUP__TRIG_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define SHUB_PORT1_SETUP__TRIG_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define SHUB_PORT1_SETUP__TRIG_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define SHUB_PORT1_SETUP__TRIG_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define SHUB_PORT1_SETUP__TRIG_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define SHUB_PORT1_SETUP__TRIG_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define SHUB_PORT1_SETUP__TRIG_EN__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT1_SETUP__TYPE uint32_t +#define SHUB_PORT1_SETUP__READ 0x00000873U +#define SHUB_PORT1_SETUP__WRITE 0x00000873U +#define SHUB_PORT1_SETUP__PRESERVED 0x00000873U +#define SHUB_PORT1_SETUP__RESET_VALUE 0x00000000U + +#endif /* __SHUB_PORT1_SETUP_MACRO__ */ + +/** @} end of port1_setup */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port1_sensor0_setup */ +/** + * @defgroup at_apb_shub_regs_core_port1_sensor0_setup port1_sensor0_setup + * @brief Contains register fields associated with port1_sensor0_setup. definitions. + * @{ + */ +#ifndef __SHUB_PORT1_SENSOR0_SETUP_MACRO__ +#define __SHUB_PORT1_SENSOR0_SETUP_MACRO__ + +/* macros for field num_bytes */ +/** + * @defgroup at_apb_shub_regs_core_num_bytes_field num_bytes_field + * @brief macros for field num_bytes + * @details total number of bytes in sensor data = num_bytes+1 + * @{ + */ +#define SHUB_PORT1_SENSOR0_SETUP__NUM_BYTES__SHIFT 0 +#define SHUB_PORT1_SENSOR0_SETUP__NUM_BYTES__WIDTH 5 +#define SHUB_PORT1_SENSOR0_SETUP__NUM_BYTES__MASK 0x0000001fU +#define SHUB_PORT1_SENSOR0_SETUP__NUM_BYTES__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT1_SENSOR0_SETUP__NUM_BYTES__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT1_SENSOR0_SETUP__NUM_BYTES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define SHUB_PORT1_SENSOR0_SETUP__NUM_BYTES__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define SHUB_PORT1_SENSOR0_SETUP__NUM_BYTES__RESET_VALUE 0x00000001U +/** @} */ +#define SHUB_PORT1_SENSOR0_SETUP__TYPE uint32_t +#define SHUB_PORT1_SENSOR0_SETUP__READ 0x0000001fU +#define SHUB_PORT1_SENSOR0_SETUP__WRITE 0x0000001fU +#define SHUB_PORT1_SENSOR0_SETUP__PRESERVED 0x0000001fU +#define SHUB_PORT1_SENSOR0_SETUP__RESET_VALUE 0x00000001U + +#endif /* __SHUB_PORT1_SENSOR0_SETUP_MACRO__ */ + +/** @} end of port1_sensor0_setup */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port1_spi_eng0_ctrl */ +/** + * @defgroup at_apb_shub_regs_core_port1_spi_eng0_ctrl port1_spi_eng0_ctrl + * @brief Contains register fields associated with port1_spi_eng0_ctrl. definitions. + * @{ + */ +#ifndef __SHUB_PORT1_SPI_ENG0_CTRL_MACRO__ +#define __SHUB_PORT1_SPI_ENG0_CTRL_MACRO__ + +/* macros for field sensor_opcode */ +/** + * @defgroup at_apb_shub_regs_core_sensor_opcode_field sensor_opcode_field + * @brief macros for field sensor_opcode + * @details opcode used to communicate with sensor in spi mode + * @{ + */ +#define SHUB_PORT1_SPI_ENG0_CTRL__SENSOR_OPCODE__SHIFT 0 +#define SHUB_PORT1_SPI_ENG0_CTRL__SENSOR_OPCODE__WIDTH 8 +#define SHUB_PORT1_SPI_ENG0_CTRL__SENSOR_OPCODE__MASK 0x000000ffU +#define SHUB_PORT1_SPI_ENG0_CTRL__SENSOR_OPCODE__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT1_SPI_ENG0_CTRL__SENSOR_OPCODE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT1_SPI_ENG0_CTRL__SENSOR_OPCODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_PORT1_SPI_ENG0_CTRL__SENSOR_OPCODE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_PORT1_SPI_ENG0_CTRL__SENSOR_OPCODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cpha */ +/** + * @defgroup at_apb_shub_regs_core_cpha_field cpha_field + * @brief macros for field cpha + * @details spi clcok phase mode + * @{ + */ +#define SHUB_PORT1_SPI_ENG0_CTRL__CPHA__SHIFT 30 +#define SHUB_PORT1_SPI_ENG0_CTRL__CPHA__WIDTH 1 +#define SHUB_PORT1_SPI_ENG0_CTRL__CPHA__MASK 0x40000000U +#define SHUB_PORT1_SPI_ENG0_CTRL__CPHA__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define SHUB_PORT1_SPI_ENG0_CTRL__CPHA__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define SHUB_PORT1_SPI_ENG0_CTRL__CPHA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define SHUB_PORT1_SPI_ENG0_CTRL__CPHA__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define SHUB_PORT1_SPI_ENG0_CTRL__CPHA__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define SHUB_PORT1_SPI_ENG0_CTRL__CPHA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define SHUB_PORT1_SPI_ENG0_CTRL__CPHA__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cpol */ +/** + * @defgroup at_apb_shub_regs_core_cpol_field cpol_field + * @brief macros for field cpol + * @details spi clock polarity mode. 0 = posedge-sensitive, 1 = negedge + * @{ + */ +#define SHUB_PORT1_SPI_ENG0_CTRL__CPOL__SHIFT 31 +#define SHUB_PORT1_SPI_ENG0_CTRL__CPOL__WIDTH 1 +#define SHUB_PORT1_SPI_ENG0_CTRL__CPOL__MASK 0x80000000U +#define SHUB_PORT1_SPI_ENG0_CTRL__CPOL__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define SHUB_PORT1_SPI_ENG0_CTRL__CPOL__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define SHUB_PORT1_SPI_ENG0_CTRL__CPOL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define SHUB_PORT1_SPI_ENG0_CTRL__CPOL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define SHUB_PORT1_SPI_ENG0_CTRL__CPOL__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define SHUB_PORT1_SPI_ENG0_CTRL__CPOL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define SHUB_PORT1_SPI_ENG0_CTRL__CPOL__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT1_SPI_ENG0_CTRL__TYPE uint32_t +#define SHUB_PORT1_SPI_ENG0_CTRL__READ 0xc00000ffU +#define SHUB_PORT1_SPI_ENG0_CTRL__WRITE 0xc00000ffU +#define SHUB_PORT1_SPI_ENG0_CTRL__PRESERVED 0xc00000ffU +#define SHUB_PORT1_SPI_ENG0_CTRL__RESET_VALUE 0x00000000U + +#endif /* __SHUB_PORT1_SPI_ENG0_CTRL_MACRO__ */ + +/** @} end of port1_spi_eng0_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port1_i2c_idw_0 */ +/** + * @defgroup at_apb_shub_regs_core_port1_i2c_idw_0 port1_i2c_idw_0 + * @brief id(read) of sensor0 on port0 prior to pointer address write definitions. + * @{ + */ +#ifndef __SHUB_PORT1_I2C_IDW_0_MACRO__ +#define __SHUB_PORT1_I2C_IDW_0_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT1_I2C_IDW_0__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT1_I2C_IDW_0__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT1_I2C_IDW_0__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT1_I2C_IDW_0__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT1_I2C_IDW_0__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT1_I2C_IDW_0__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT1_I2C_IDW_0__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT1_I2C_IDW_0__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT1_I2C_IDW_0__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT1_I2C_IDW_0__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT1_I2C_IDW_0__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT1_I2C_IDW_0__EXT_HEAD__SHIFT 19 +#define SHUB_PORT1_I2C_IDW_0__EXT_HEAD__WIDTH 2 +#define SHUB_PORT1_I2C_IDW_0__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT1_I2C_IDW_0__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT1_I2C_IDW_0__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT1_I2C_IDW_0__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT1_I2C_IDW_0__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT1_I2C_IDW_0__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT1_I2C_IDW_0__EXT_TAIL__SHIFT 21 +#define SHUB_PORT1_I2C_IDW_0__EXT_TAIL__WIDTH 2 +#define SHUB_PORT1_I2C_IDW_0__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT1_I2C_IDW_0__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT1_I2C_IDW_0__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT1_I2C_IDW_0__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT1_I2C_IDW_0__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT1_I2C_IDW_0__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT1_I2C_IDW_0__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT1_I2C_IDW_0__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT1_I2C_IDW_0__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT1_I2C_IDW_0__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT1_I2C_IDW_0__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT1_I2C_IDW_0__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT1_I2C_IDW_0__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT1_I2C_IDW_0__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT1_I2C_IDW_0__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT1_I2C_IDW_0__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT1_I2C_IDW_0__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT1_I2C_IDW_0__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT1_I2C_IDW_0__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT1_I2C_IDW_0__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT1_I2C_IDW_0__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT1_I2C_IDW_0__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT1_I2C_IDW_0__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT1_I2C_IDW_0__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT1_I2C_IDW_0__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT1_I2C_IDW_0__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT1_I2C_IDW_0__TYPE uint32_t +#define SHUB_PORT1_I2C_IDW_0__READ 0x01ffffffU +#define SHUB_PORT1_I2C_IDW_0__WRITE 0x01ffffffU +#define SHUB_PORT1_I2C_IDW_0__PRESERVED 0x01ffffffU +#define SHUB_PORT1_I2C_IDW_0__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT1_I2C_IDW_0_MACRO__ */ + +/** @} end of port1_i2c_idw_0 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port1_i2c_addr_0 */ +/** + * @defgroup at_apb_shub_regs_core_port1_i2c_addr_0 port1_i2c_addr_0 + * @brief pointer addr of sensor0 on port0 definitions. + * @{ + */ +#ifndef __SHUB_PORT1_I2C_ADDR_0_MACRO__ +#define __SHUB_PORT1_I2C_ADDR_0_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT1_I2C_ADDR_0__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT1_I2C_ADDR_0__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT1_I2C_ADDR_0__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT1_I2C_ADDR_0__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT1_I2C_ADDR_0__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT1_I2C_ADDR_0__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT1_I2C_ADDR_0__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT1_I2C_ADDR_0__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT1_I2C_ADDR_0__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT1_I2C_ADDR_0__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT1_I2C_ADDR_0__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT1_I2C_ADDR_0__EXT_HEAD__SHIFT 19 +#define SHUB_PORT1_I2C_ADDR_0__EXT_HEAD__WIDTH 2 +#define SHUB_PORT1_I2C_ADDR_0__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT1_I2C_ADDR_0__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT1_I2C_ADDR_0__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT1_I2C_ADDR_0__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT1_I2C_ADDR_0__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT1_I2C_ADDR_0__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT1_I2C_ADDR_0__EXT_TAIL__SHIFT 21 +#define SHUB_PORT1_I2C_ADDR_0__EXT_TAIL__WIDTH 2 +#define SHUB_PORT1_I2C_ADDR_0__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT1_I2C_ADDR_0__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT1_I2C_ADDR_0__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT1_I2C_ADDR_0__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT1_I2C_ADDR_0__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT1_I2C_ADDR_0__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT1_I2C_ADDR_0__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT1_I2C_ADDR_0__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT1_I2C_ADDR_0__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT1_I2C_ADDR_0__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT1_I2C_ADDR_0__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT1_I2C_ADDR_0__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT1_I2C_ADDR_0__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT1_I2C_ADDR_0__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT1_I2C_ADDR_0__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT1_I2C_ADDR_0__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT1_I2C_ADDR_0__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT1_I2C_ADDR_0__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT1_I2C_ADDR_0__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT1_I2C_ADDR_0__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT1_I2C_ADDR_0__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT1_I2C_ADDR_0__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT1_I2C_ADDR_0__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT1_I2C_ADDR_0__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT1_I2C_ADDR_0__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT1_I2C_ADDR_0__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT1_I2C_ADDR_0__TYPE uint32_t +#define SHUB_PORT1_I2C_ADDR_0__READ 0x01ffffffU +#define SHUB_PORT1_I2C_ADDR_0__WRITE 0x01ffffffU +#define SHUB_PORT1_I2C_ADDR_0__PRESERVED 0x01ffffffU +#define SHUB_PORT1_I2C_ADDR_0__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT1_I2C_ADDR_0_MACRO__ */ + +/** @} end of port1_i2c_addr_0 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port1_i2c_idr_0 */ +/** + * @defgroup at_apb_shub_regs_core_port1_i2c_idr_0 port1_i2c_idr_0 + * @brief id(read) of sensor0 on port0 prior to data read definitions. + * @{ + */ +#ifndef __SHUB_PORT1_I2C_IDR_0_MACRO__ +#define __SHUB_PORT1_I2C_IDR_0_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT1_I2C_IDR_0__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT1_I2C_IDR_0__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT1_I2C_IDR_0__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT1_I2C_IDR_0__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT1_I2C_IDR_0__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT1_I2C_IDR_0__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT1_I2C_IDR_0__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT1_I2C_IDR_0__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT1_I2C_IDR_0__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT1_I2C_IDR_0__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT1_I2C_IDR_0__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT1_I2C_IDR_0__EXT_HEAD__SHIFT 19 +#define SHUB_PORT1_I2C_IDR_0__EXT_HEAD__WIDTH 2 +#define SHUB_PORT1_I2C_IDR_0__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT1_I2C_IDR_0__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT1_I2C_IDR_0__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT1_I2C_IDR_0__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT1_I2C_IDR_0__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT1_I2C_IDR_0__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT1_I2C_IDR_0__EXT_TAIL__SHIFT 21 +#define SHUB_PORT1_I2C_IDR_0__EXT_TAIL__WIDTH 2 +#define SHUB_PORT1_I2C_IDR_0__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT1_I2C_IDR_0__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT1_I2C_IDR_0__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT1_I2C_IDR_0__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT1_I2C_IDR_0__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT1_I2C_IDR_0__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT1_I2C_IDR_0__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT1_I2C_IDR_0__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT1_I2C_IDR_0__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT1_I2C_IDR_0__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT1_I2C_IDR_0__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT1_I2C_IDR_0__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT1_I2C_IDR_0__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT1_I2C_IDR_0__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT1_I2C_IDR_0__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT1_I2C_IDR_0__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT1_I2C_IDR_0__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT1_I2C_IDR_0__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT1_I2C_IDR_0__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT1_I2C_IDR_0__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT1_I2C_IDR_0__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT1_I2C_IDR_0__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT1_I2C_IDR_0__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT1_I2C_IDR_0__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT1_I2C_IDR_0__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT1_I2C_IDR_0__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT1_I2C_IDR_0__TYPE uint32_t +#define SHUB_PORT1_I2C_IDR_0__READ 0x01ffffffU +#define SHUB_PORT1_I2C_IDR_0__WRITE 0x01ffffffU +#define SHUB_PORT1_I2C_IDR_0__PRESERVED 0x01ffffffU +#define SHUB_PORT1_I2C_IDR_0__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT1_I2C_IDR_0_MACRO__ */ + +/** @} end of port1_i2c_idr_0 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port1_i2c_dat_ctrl */ +/** + * @defgroup at_apb_shub_regs_core_port1_i2c_dat_ctrl port1_i2c_dat_ctrl + * @brief slave(port0) data byte read (used in not the last byte) definitions. + * @{ + */ +#ifndef __SHUB_PORT1_I2C_DAT_CTRL_MACRO__ +#define __SHUB_PORT1_I2C_DAT_CTRL_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_HEAD__SHIFT 19 +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_HEAD__WIDTH 2 +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_TAIL__SHIFT 21 +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_TAIL__WIDTH 2 +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_MASTER_DRIVES_ACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT1_I2C_DAT_CTRL__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE \ + 0x00000000U +/** @} */ +#define SHUB_PORT1_I2C_DAT_CTRL__TYPE uint32_t +#define SHUB_PORT1_I2C_DAT_CTRL__READ 0x01ffffffU +#define SHUB_PORT1_I2C_DAT_CTRL__WRITE 0x01ffffffU +#define SHUB_PORT1_I2C_DAT_CTRL__PRESERVED 0x01ffffffU +#define SHUB_PORT1_I2C_DAT_CTRL__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT1_I2C_DAT_CTRL_MACRO__ */ + +/** @} end of port1_i2c_dat_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port1_i2c_dat_last_ctrl */ +/** + * @defgroup at_apb_shub_regs_core_port1_i2c_dat_last_ctrl port1_i2c_dat_last_ctrl + * @brief slave(port0) data byte read (used in the last byte) definitions. + * @{ + */ +#ifndef __SHUB_PORT1_I2C_DAT_LAST_CTRL_MACRO__ +#define __SHUB_PORT1_I2C_DAT_LAST_CTRL_MACRO__ + +/* macros for field ext_data_ie_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_ie_ovrd_field ext_data_ie_ovrd_field + * @brief macros for field ext_data_ie_ovrd + * @{ + */ +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_IE_OVRD__SHIFT 0 +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_IE_OVRD__WIDTH 1 +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_IE_OVRD__MASK 0x00000001U +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_IE_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_IE_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_IE_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_IE_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_IE_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_IE_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_IE_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_o */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_o_field ext_data_o_field + * @brief macros for field ext_data_o + * @{ + */ +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_O__SHIFT 1 +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_O__WIDTH 8 +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_O__MASK 0x000001feU +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_O__READ(src) \ + (((uint32_t)(src)\ + & 0x000001feU) >> 1) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_O__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000001feU) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_O__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_O__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_O__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_data_oe */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_oe_field ext_data_oe_field + * @brief macros for field ext_data_oe + * @{ + */ +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_OE__SHIFT 9 +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_OE__WIDTH 8 +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_OE__MASK 0x0001fe00U +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_OE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fe00U) >> 9) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_OE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0001fe00U) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_OE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_OE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_OE__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field ext_data_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_data_pu_field ext_data_pu_field + * @brief macros for field ext_data_pu + * @{ + */ +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_PU__SHIFT 17 +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_PU__WIDTH 1 +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_PU__MASK 0x00020000U +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_DATA_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_clk_pu */ +/** + * @defgroup at_apb_shub_regs_core_ext_clk_pu_field ext_clk_pu_field + * @brief macros for field ext_clk_pu + * @{ + */ +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_CLK_PU__SHIFT 18 +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_CLK_PU__WIDTH 1 +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_CLK_PU__MASK 0x00040000U +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_CLK_PU__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_CLK_PU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_CLK_PU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_CLK_PU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_CLK_PU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_CLK_PU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_CLK_PU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_head */ +/** + * @defgroup at_apb_shub_regs_core_ext_head_field ext_head_field + * @brief macros for field ext_head + * @{ + */ +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_HEAD__SHIFT 19 +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_HEAD__WIDTH 2 +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_HEAD__MASK 0x00180000U +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_HEAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_HEAD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_HEAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_HEAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_tail */ +/** + * @defgroup at_apb_shub_regs_core_ext_tail_field ext_tail_field + * @brief macros for field ext_tail + * @{ + */ +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_TAIL__SHIFT 21 +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_TAIL__WIDTH 2 +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_TAIL__MASK 0x00600000U +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_TAIL__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_TAIL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_TAIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_TAIL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_TAIL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ext_master_drives_ack */ +/** + * @defgroup at_apb_shub_regs_core_ext_master_drives_ack_field ext_master_drives_ack_field + * @brief macros for field ext_master_drives_ack + * @{ + */ +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_MASTER_DRIVES_ACK__SHIFT 23 +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_MASTER_DRIVES_ACK__WIDTH 1 +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_MASTER_DRIVES_ACK__MASK 0x00800000U +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_MASTER_DRIVES_ACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_MASTER_DRIVES_ACK__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_MASTER_DRIVES_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_MASTER_DRIVES_ACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_MASTER_DRIVES_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_MASTER_DRIVES_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_MASTER_DRIVES_ACK__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field ext_ack_value_to_drive */ +/** + * @defgroup at_apb_shub_regs_core_ext_ack_value_to_drive_field ext_ack_value_to_drive_field + * @brief macros for field ext_ack_value_to_drive + * @{ + */ +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_ACK_VALUE_TO_DRIVE__SHIFT 24 +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_ACK_VALUE_TO_DRIVE__WIDTH 1 +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_ACK_VALUE_TO_DRIVE__MASK 0x01000000U +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_ACK_VALUE_TO_DRIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_ACK_VALUE_TO_DRIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_ACK_VALUE_TO_DRIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_ACK_VALUE_TO_DRIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_ACK_VALUE_TO_DRIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_ACK_VALUE_TO_DRIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__EXT_ACK_VALUE_TO_DRIVE__RESET_VALUE \ + 0x00000000U +/** @} */ +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__TYPE uint32_t +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__READ 0x01ffffffU +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__WRITE 0x01ffffffU +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__PRESERVED 0x01ffffffU +#define SHUB_PORT1_I2C_DAT_LAST_CTRL__RESET_VALUE 0x0001fe00U + +#endif /* __SHUB_PORT1_I2C_DAT_LAST_CTRL_MACRO__ */ + +/** @} end of port1_i2c_dat_last_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port1_alm0_quan_ctrl */ +/** + * @defgroup at_apb_shub_regs_core_port1_alm0_quan_ctrl port1_alm0_quan_ctrl + * @brief alarm0 quantity's definition definitions. + * @{ + */ +#ifndef __SHUB_PORT1_ALM0_QUAN_CTRL_MACRO__ +#define __SHUB_PORT1_ALM0_QUAN_CTRL_MACRO__ + +/* macros for field quan0_pos */ +/** + * @defgroup at_apb_shub_regs_core_quan0_pos_field quan0_pos_field + * @brief macros for field quan0_pos + * @{ + */ +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN0_POS__SHIFT 0 +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN0_POS__WIDTH 5 +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN0_POS__MASK 0x0000001fU +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN0_POS__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN0_POS__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN0_POS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN0_POS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN0_POS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field quan1_pos */ +/** + * @defgroup at_apb_shub_regs_core_quan1_pos_field quan1_pos_field + * @brief macros for field quan1_pos + * @{ + */ +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN1_POS__SHIFT 5 +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN1_POS__WIDTH 5 +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN1_POS__MASK 0x000003e0U +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN1_POS__READ(src) \ + (((uint32_t)(src)\ + & 0x000003e0U) >> 5) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN1_POS__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x000003e0U) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN1_POS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((uint32_t)(src) <<\ + 5) & 0x000003e0U) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN1_POS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000003e0U))) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN1_POS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field quan2_pos */ +/** + * @defgroup at_apb_shub_regs_core_quan2_pos_field quan2_pos_field + * @brief macros for field quan2_pos + * @{ + */ +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN2_POS__SHIFT 10 +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN2_POS__WIDTH 5 +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN2_POS__MASK 0x00007c00U +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN2_POS__READ(src) \ + (((uint32_t)(src)\ + & 0x00007c00U) >> 10) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN2_POS__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00007c00U) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN2_POS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((uint32_t)(src) <<\ + 10) & 0x00007c00U) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN2_POS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00007c00U))) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN2_POS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field quan3_pos */ +/** + * @defgroup at_apb_shub_regs_core_quan3_pos_field quan3_pos_field + * @brief macros for field quan3_pos + * @details starting position of the quantity + * @{ + */ +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN3_POS__SHIFT 15 +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN3_POS__WIDTH 5 +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN3_POS__MASK 0x000f8000U +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN3_POS__READ(src) \ + (((uint32_t)(src)\ + & 0x000f8000U) >> 15) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN3_POS__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x000f8000U) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN3_POS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((uint32_t)(src) <<\ + 15) & 0x000f8000U) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN3_POS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x000f8000U))) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN3_POS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field quan0_size */ +/** + * @defgroup at_apb_shub_regs_core_quan0_size_field quan0_size_field + * @brief macros for field quan0_size + * @{ + */ +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN0_SIZE__SHIFT 20 +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN0_SIZE__WIDTH 2 +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN0_SIZE__MASK 0x00300000U +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN0_SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0x00300000U) >> 20) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN0_SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00300000U) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN0_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00300000U) | (((uint32_t)(src) <<\ + 20) & 0x00300000U) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN0_SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00300000U))) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN0_SIZE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field quan1_size */ +/** + * @defgroup at_apb_shub_regs_core_quan1_size_field quan1_size_field + * @brief macros for field quan1_size + * @{ + */ +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN1_SIZE__SHIFT 22 +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN1_SIZE__WIDTH 2 +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN1_SIZE__MASK 0x00c00000U +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN1_SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0x00c00000U) >> 22) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN1_SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00c00000U) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN1_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00c00000U) | (((uint32_t)(src) <<\ + 22) & 0x00c00000U) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN1_SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00c00000U))) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN1_SIZE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field quan2_size */ +/** + * @defgroup at_apb_shub_regs_core_quan2_size_field quan2_size_field + * @brief macros for field quan2_size + * @{ + */ +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN2_SIZE__SHIFT 24 +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN2_SIZE__WIDTH 2 +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN2_SIZE__MASK 0x03000000U +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN2_SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0x03000000U) >> 24) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN2_SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x03000000U) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN2_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((uint32_t)(src) <<\ + 24) & 0x03000000U) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN2_SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x03000000U))) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN2_SIZE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field quan3_size */ +/** + * @defgroup at_apb_shub_regs_core_quan3_size_field quan3_size_field + * @brief macros for field quan3_size + * @details number of bytes making up the quantity data = programmed quan3_size + 1 + * @{ + */ +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN3_SIZE__SHIFT 26 +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN3_SIZE__WIDTH 2 +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN3_SIZE__MASK 0x0c000000U +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN3_SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0x0c000000U) >> 26) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN3_SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x0c000000U) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN3_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((uint32_t)(src) <<\ + 26) & 0x0c000000U) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN3_SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x0c000000U))) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN3_SIZE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field lsb_first */ +/** + * @defgroup at_apb_shub_regs_core_lsb_first_field lsb_first_field + * @brief macros for field lsb_first + * @details 1= quantity data is big endian ; 0= small endian + * @{ + */ +#define SHUB_PORT1_ALM0_QUAN_CTRL__LSB_FIRST__SHIFT 30 +#define SHUB_PORT1_ALM0_QUAN_CTRL__LSB_FIRST__WIDTH 1 +#define SHUB_PORT1_ALM0_QUAN_CTRL__LSB_FIRST__MASK 0x40000000U +#define SHUB_PORT1_ALM0_QUAN_CTRL__LSB_FIRST__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define SHUB_PORT1_ALM0_QUAN_CTRL__LSB_FIRST__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define SHUB_PORT1_ALM0_QUAN_CTRL__LSB_FIRST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define SHUB_PORT1_ALM0_QUAN_CTRL__LSB_FIRST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define SHUB_PORT1_ALM0_QUAN_CTRL__LSB_FIRST__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define SHUB_PORT1_ALM0_QUAN_CTRL__LSB_FIRST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define SHUB_PORT1_ALM0_QUAN_CTRL__LSB_FIRST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field quan_dat_is_signed */ +/** + * @defgroup at_apb_shub_regs_core_quan_dat_is_signed_field quan_dat_is_signed_field + * @brief macros for field quan_dat_is_signed + * @details quantity data is a signed data + * @{ + */ +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN_DAT_IS_SIGNED__SHIFT 31 +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN_DAT_IS_SIGNED__WIDTH 1 +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN_DAT_IS_SIGNED__MASK 0x80000000U +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN_DAT_IS_SIGNED__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN_DAT_IS_SIGNED__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN_DAT_IS_SIGNED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN_DAT_IS_SIGNED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN_DAT_IS_SIGNED__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN_DAT_IS_SIGNED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define SHUB_PORT1_ALM0_QUAN_CTRL__QUAN_DAT_IS_SIGNED__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT1_ALM0_QUAN_CTRL__TYPE uint32_t +#define SHUB_PORT1_ALM0_QUAN_CTRL__READ 0xcfffffffU +#define SHUB_PORT1_ALM0_QUAN_CTRL__WRITE 0xcfffffffU +#define SHUB_PORT1_ALM0_QUAN_CTRL__PRESERVED 0xcfffffffU +#define SHUB_PORT1_ALM0_QUAN_CTRL__RESET_VALUE 0x05500000U + +#endif /* __SHUB_PORT1_ALM0_QUAN_CTRL_MACRO__ */ + +/** @} end of port1_alm0_quan_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port1_alm0_trig_ctrl */ +/** + * @defgroup at_apb_shub_regs_core_port1_alm0_trig_ctrl port1_alm0_trig_ctrl + * @brief alarm0 trigger function: trigger = trig_func_en( out_of_range(quan3), out_of_range(quan2),out_of_range(quan1),out_of_range(quan0)) definitions. + * @{ + */ +#ifndef __SHUB_PORT1_ALM0_TRIG_CTRL_MACRO__ +#define __SHUB_PORT1_ALM0_TRIG_CTRL_MACRO__ + +/* macros for field trig_func_en */ +/** + * @defgroup at_apb_shub_regs_core_trig_func_en_field trig_func_en_field + * @brief macros for field trig_func_en + * @{ + */ +#define SHUB_PORT1_ALM0_TRIG_CTRL__TRIG_FUNC_EN__SHIFT 0 +#define SHUB_PORT1_ALM0_TRIG_CTRL__TRIG_FUNC_EN__WIDTH 16 +#define SHUB_PORT1_ALM0_TRIG_CTRL__TRIG_FUNC_EN__MASK 0x0000ffffU +#define SHUB_PORT1_ALM0_TRIG_CTRL__TRIG_FUNC_EN__READ(src) \ + ((uint32_t)(src)\ + & 0x0000ffffU) +#define SHUB_PORT1_ALM0_TRIG_CTRL__TRIG_FUNC_EN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000ffffU) +#define SHUB_PORT1_ALM0_TRIG_CTRL__TRIG_FUNC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define SHUB_PORT1_ALM0_TRIG_CTRL__TRIG_FUNC_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000ffffU))) +#define SHUB_PORT1_ALM0_TRIG_CTRL__TRIG_FUNC_EN__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT1_ALM0_TRIG_CTRL__TYPE uint32_t +#define SHUB_PORT1_ALM0_TRIG_CTRL__READ 0x0000ffffU +#define SHUB_PORT1_ALM0_TRIG_CTRL__WRITE 0x0000ffffU +#define SHUB_PORT1_ALM0_TRIG_CTRL__PRESERVED 0x0000ffffU +#define SHUB_PORT1_ALM0_TRIG_CTRL__RESET_VALUE 0x00000000U + +#endif /* __SHUB_PORT1_ALM0_TRIG_CTRL_MACRO__ */ + +/** @} end of port1_alm0_trig_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port1_alm0_thrhld_max_0 */ +/** + * @defgroup at_apb_shub_regs_core_port1_alm0_thrhld_max_0 port1_alm0_thrhld_max_0 + * @brief threshold of sensor results definitions. + * @{ + */ +#ifndef __SHUB_PORT1_ALM0_THRHLD_MAX_0_MACRO__ +#define __SHUB_PORT1_ALM0_THRHLD_MAX_0_MACRO__ + +/* macros for field byte_max_00 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_00_field byte_max_00_field + * @brief macros for field byte_max_00 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_00__SHIFT 0 +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_00__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_00__MASK 0x000000ffU +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_00__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_00__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_00__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_00__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_00__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_01 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_01_field byte_max_01_field + * @brief macros for field byte_max_01 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_01__SHIFT 8 +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_01__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_01__MASK 0x0000ff00U +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_01__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_01__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_01__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_01__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_01__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_02 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_02_field byte_max_02_field + * @brief macros for field byte_max_02 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_02__SHIFT 16 +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_02__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_02__MASK 0x00ff0000U +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_02__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_02__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_02__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_02__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_02__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_03 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_03_field byte_max_03_field + * @brief macros for field byte_max_03 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_03__SHIFT 24 +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_03__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_03__MASK 0xff000000U +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_03__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_03__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_03__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_03__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__BYTE_MAX_03__RESET_VALUE 0x000000ffU +/** @} */ +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__TYPE uint32_t +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__READ 0xffffffffU +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__WRITE 0xffffffffU +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__PRESERVED 0xffffffffU +#define SHUB_PORT1_ALM0_THRHLD_MAX_0__RESET_VALUE 0xffffffffU + +#endif /* __SHUB_PORT1_ALM0_THRHLD_MAX_0_MACRO__ */ + +/** @} end of port1_alm0_thrhld_max_0 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port1_alm0_thrhld_max_1 */ +/** + * @defgroup at_apb_shub_regs_core_port1_alm0_thrhld_max_1 port1_alm0_thrhld_max_1 + * @brief threshold of sensor results definitions. + * @{ + */ +#ifndef __SHUB_PORT1_ALM0_THRHLD_MAX_1_MACRO__ +#define __SHUB_PORT1_ALM0_THRHLD_MAX_1_MACRO__ + +/* macros for field byte_max_04 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_04_field byte_max_04_field + * @brief macros for field byte_max_04 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_04__SHIFT 0 +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_04__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_04__MASK 0x000000ffU +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_04__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_04__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_04__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_04__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_04__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_05 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_05_field byte_max_05_field + * @brief macros for field byte_max_05 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_05__SHIFT 8 +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_05__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_05__MASK 0x0000ff00U +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_05__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_05__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_05__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_05__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_05__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_06 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_06_field byte_max_06_field + * @brief macros for field byte_max_06 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_06__SHIFT 16 +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_06__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_06__MASK 0x00ff0000U +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_06__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_06__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_06__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_06__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_06__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_07 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_07_field byte_max_07_field + * @brief macros for field byte_max_07 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_07__SHIFT 24 +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_07__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_07__MASK 0xff000000U +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_07__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_07__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_07__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_07__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__BYTE_MAX_07__RESET_VALUE 0x000000ffU +/** @} */ +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__TYPE uint32_t +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__READ 0xffffffffU +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__WRITE 0xffffffffU +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__PRESERVED 0xffffffffU +#define SHUB_PORT1_ALM0_THRHLD_MAX_1__RESET_VALUE 0xffffffffU + +#endif /* __SHUB_PORT1_ALM0_THRHLD_MAX_1_MACRO__ */ + +/** @} end of port1_alm0_thrhld_max_1 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port1_alm0_thrhld_max_2 */ +/** + * @defgroup at_apb_shub_regs_core_port1_alm0_thrhld_max_2 port1_alm0_thrhld_max_2 + * @brief threshold of sensor results definitions. + * @{ + */ +#ifndef __SHUB_PORT1_ALM0_THRHLD_MAX_2_MACRO__ +#define __SHUB_PORT1_ALM0_THRHLD_MAX_2_MACRO__ + +/* macros for field byte_max_08 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_08_field byte_max_08_field + * @brief macros for field byte_max_08 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_08__SHIFT 0 +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_08__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_08__MASK 0x000000ffU +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_08__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_08__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_08__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_08__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_08__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_09 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_09_field byte_max_09_field + * @brief macros for field byte_max_09 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_09__SHIFT 8 +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_09__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_09__MASK 0x0000ff00U +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_09__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_09__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_09__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_09__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_09__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_10 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_10_field byte_max_10_field + * @brief macros for field byte_max_10 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_10__SHIFT 16 +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_10__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_10__MASK 0x00ff0000U +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_10__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_10__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_10__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_10__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field byte_max_11 */ +/** + * @defgroup at_apb_shub_regs_core_byte_max_11_field byte_max_11_field + * @brief macros for field byte_max_11 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_11__SHIFT 24 +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_11__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_11__MASK 0xff000000U +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_11__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_11__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_11__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__BYTE_MAX_11__RESET_VALUE 0x000000ffU +/** @} */ +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__TYPE uint32_t +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__READ 0xffffffffU +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__WRITE 0xffffffffU +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__PRESERVED 0xffffffffU +#define SHUB_PORT1_ALM0_THRHLD_MAX_2__RESET_VALUE 0xffffffffU + +#endif /* __SHUB_PORT1_ALM0_THRHLD_MAX_2_MACRO__ */ + +/** @} end of port1_alm0_thrhld_max_2 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port1_alm0_thrhld_min_0 */ +/** + * @defgroup at_apb_shub_regs_core_port1_alm0_thrhld_min_0 port1_alm0_thrhld_min_0 + * @brief threshold of sensor results definitions. + * @{ + */ +#ifndef __SHUB_PORT1_ALM0_THRHLD_MIN_0_MACRO__ +#define __SHUB_PORT1_ALM0_THRHLD_MIN_0_MACRO__ + +/* macros for field byte_min_00 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_00_field byte_min_00_field + * @brief macros for field byte_min_00 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_00__SHIFT 0 +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_00__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_00__MASK 0x000000ffU +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_00__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_00__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_00__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_00__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_00__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_01 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_01_field byte_min_01_field + * @brief macros for field byte_min_01 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_01__SHIFT 8 +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_01__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_01__MASK 0x0000ff00U +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_01__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_01__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_01__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_01__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_01__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_02 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_02_field byte_min_02_field + * @brief macros for field byte_min_02 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_02__SHIFT 16 +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_02__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_02__MASK 0x00ff0000U +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_02__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_02__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_02__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_02__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_02__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_03 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_03_field byte_min_03_field + * @brief macros for field byte_min_03 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_03__SHIFT 24 +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_03__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_03__MASK 0xff000000U +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_03__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_03__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_03__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_03__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__BYTE_MIN_03__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__TYPE uint32_t +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__READ 0xffffffffU +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__WRITE 0xffffffffU +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__PRESERVED 0xffffffffU +#define SHUB_PORT1_ALM0_THRHLD_MIN_0__RESET_VALUE 0x00000000U + +#endif /* __SHUB_PORT1_ALM0_THRHLD_MIN_0_MACRO__ */ + +/** @} end of port1_alm0_thrhld_min_0 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port1_alm0_thrhld_min_1 */ +/** + * @defgroup at_apb_shub_regs_core_port1_alm0_thrhld_min_1 port1_alm0_thrhld_min_1 + * @brief threshold of sensor results definitions. + * @{ + */ +#ifndef __SHUB_PORT1_ALM0_THRHLD_MIN_1_MACRO__ +#define __SHUB_PORT1_ALM0_THRHLD_MIN_1_MACRO__ + +/* macros for field byte_min_04 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_04_field byte_min_04_field + * @brief macros for field byte_min_04 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_04__SHIFT 0 +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_04__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_04__MASK 0x000000ffU +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_04__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_04__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_04__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_04__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_04__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_05 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_05_field byte_min_05_field + * @brief macros for field byte_min_05 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_05__SHIFT 8 +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_05__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_05__MASK 0x0000ff00U +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_05__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_05__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_05__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_05__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_05__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_06 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_06_field byte_min_06_field + * @brief macros for field byte_min_06 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_06__SHIFT 16 +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_06__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_06__MASK 0x00ff0000U +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_06__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_06__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_06__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_06__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_06__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_07 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_07_field byte_min_07_field + * @brief macros for field byte_min_07 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_07__SHIFT 24 +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_07__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_07__MASK 0xff000000U +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_07__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_07__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_07__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_07__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__BYTE_MIN_07__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__TYPE uint32_t +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__READ 0xffffffffU +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__WRITE 0xffffffffU +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__PRESERVED 0xffffffffU +#define SHUB_PORT1_ALM0_THRHLD_MIN_1__RESET_VALUE 0x00000000U + +#endif /* __SHUB_PORT1_ALM0_THRHLD_MIN_1_MACRO__ */ + +/** @} end of port1_alm0_thrhld_min_1 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port1_alm0_thrhld_min_2 */ +/** + * @defgroup at_apb_shub_regs_core_port1_alm0_thrhld_min_2 port1_alm0_thrhld_min_2 + * @brief threshold of sensor results definitions. + * @{ + */ +#ifndef __SHUB_PORT1_ALM0_THRHLD_MIN_2_MACRO__ +#define __SHUB_PORT1_ALM0_THRHLD_MIN_2_MACRO__ + +/* macros for field byte_min_08 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_08_field byte_min_08_field + * @brief macros for field byte_min_08 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_08__SHIFT 0 +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_08__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_08__MASK 0x000000ffU +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_08__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_08__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_08__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_08__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_08__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_09 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_09_field byte_min_09_field + * @brief macros for field byte_min_09 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_09__SHIFT 8 +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_09__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_09__MASK 0x0000ff00U +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_09__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_09__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_09__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_09__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_09__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_10 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_10_field byte_min_10_field + * @brief macros for field byte_min_10 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_10__SHIFT 16 +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_10__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_10__MASK 0x00ff0000U +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_10__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_10__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_10__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_10__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte_min_11 */ +/** + * @defgroup at_apb_shub_regs_core_byte_min_11_field byte_min_11_field + * @brief macros for field byte_min_11 + * @{ + */ +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_11__SHIFT 24 +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_11__WIDTH 8 +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_11__MASK 0xff000000U +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_11__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_11__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_11__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__BYTE_MIN_11__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__TYPE uint32_t +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__READ 0xffffffffU +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__WRITE 0xffffffffU +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__PRESERVED 0xffffffffU +#define SHUB_PORT1_ALM0_THRHLD_MIN_2__RESET_VALUE 0x00000000U + +#endif /* __SHUB_PORT1_ALM0_THRHLD_MIN_2_MACRO__ */ + +/** @} end of port1_alm0_thrhld_min_2 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_port1_status */ +/** + * @defgroup at_apb_shub_regs_core_port1_status port1_status + * @brief Contains register fields associated with port1_status. definitions. + * @{ + */ +#ifndef __SHUB_PORT1_STATUS_MACRO__ +#define __SHUB_PORT1_STATUS_MACRO__ + +/* macros for field out_of_range_stat */ +/** + * @defgroup at_apb_shub_regs_core_out_of_range_stat_field out_of_range_stat_field + * @brief macros for field out_of_range_stat + * @{ + */ +#define SHUB_PORT1_STATUS__OUT_OF_RANGE_STAT__SHIFT 0 +#define SHUB_PORT1_STATUS__OUT_OF_RANGE_STAT__WIDTH 4 +#define SHUB_PORT1_STATUS__OUT_OF_RANGE_STAT__MASK 0x0000000fU +#define SHUB_PORT1_STATUS__OUT_OF_RANGE_STAT__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define SHUB_PORT1_STATUS__OUT_OF_RANGE_STAT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field triggered */ +/** + * @defgroup at_apb_shub_regs_core_triggered_field triggered_field + * @brief macros for field triggered + * @{ + */ +#define SHUB_PORT1_STATUS__TRIGGERED__SHIFT 24 +#define SHUB_PORT1_STATUS__TRIGGERED__WIDTH 1 +#define SHUB_PORT1_STATUS__TRIGGERED__MASK 0x01000000U +#define SHUB_PORT1_STATUS__TRIGGERED__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_PORT1_STATUS__TRIGGERED__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_PORT1_STATUS__TRIGGERED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_PORT1_STATUS__TRIGGERED__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PORT1_STATUS__TYPE uint32_t +#define SHUB_PORT1_STATUS__READ 0x0100000fU +#define SHUB_PORT1_STATUS__PRESERVED 0x00000000U +#define SHUB_PORT1_STATUS__RESET_VALUE 0x00000000U + +#endif /* __SHUB_PORT1_STATUS_MACRO__ */ + +/** @} end of port1_status */ + +/* macros for BlueprintGlobalNameSpace::SHUB_flash_ctrl0 */ +/** + * @defgroup at_apb_shub_regs_core_flash_ctrl0 flash_ctrl0 + * @brief Contains register fields associated with flash_ctrl0. definitions. + * @{ + */ +#ifndef __SHUB_FLASH_CTRL0_MACRO__ +#define __SHUB_FLASH_CTRL0_MACRO__ + +/* macros for field opcode_wren */ +/** + * @defgroup at_apb_shub_regs_core_opcode_wren_field opcode_wren_field + * @brief macros for field opcode_wren + * @details write_enable opcode + * @{ + */ +#define SHUB_FLASH_CTRL0__OPCODE_WREN__SHIFT 0 +#define SHUB_FLASH_CTRL0__OPCODE_WREN__WIDTH 8 +#define SHUB_FLASH_CTRL0__OPCODE_WREN__MASK 0x000000ffU +#define SHUB_FLASH_CTRL0__OPCODE_WREN__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_FLASH_CTRL0__OPCODE_WREN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SHUB_FLASH_CTRL0__OPCODE_WREN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SHUB_FLASH_CTRL0__OPCODE_WREN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SHUB_FLASH_CTRL0__OPCODE_WREN__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field opcode_pp */ +/** + * @defgroup at_apb_shub_regs_core_opcode_pp_field opcode_pp_field + * @brief macros for field opcode_pp + * @details page program opcode + * @{ + */ +#define SHUB_FLASH_CTRL0__OPCODE_PP__SHIFT 8 +#define SHUB_FLASH_CTRL0__OPCODE_PP__WIDTH 8 +#define SHUB_FLASH_CTRL0__OPCODE_PP__MASK 0x0000ff00U +#define SHUB_FLASH_CTRL0__OPCODE_PP__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SHUB_FLASH_CTRL0__OPCODE_PP__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SHUB_FLASH_CTRL0__OPCODE_PP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SHUB_FLASH_CTRL0__OPCODE_PP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SHUB_FLASH_CTRL0__OPCODE_PP__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field opcode_pd */ +/** + * @defgroup at_apb_shub_regs_core_opcode_pd_field opcode_pd_field + * @brief macros for field opcode_pd + * @details power down opcode + * @{ + */ +#define SHUB_FLASH_CTRL0__OPCODE_PD__SHIFT 16 +#define SHUB_FLASH_CTRL0__OPCODE_PD__WIDTH 8 +#define SHUB_FLASH_CTRL0__OPCODE_PD__MASK 0x00ff0000U +#define SHUB_FLASH_CTRL0__OPCODE_PD__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SHUB_FLASH_CTRL0__OPCODE_PD__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SHUB_FLASH_CTRL0__OPCODE_PD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SHUB_FLASH_CTRL0__OPCODE_PD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SHUB_FLASH_CTRL0__OPCODE_PD__RESET_VALUE 0x000000b9U +/** @} */ + +/* macros for field opcode_rpd */ +/** + * @defgroup at_apb_shub_regs_core_opcode_rpd_field opcode_rpd_field + * @brief macros for field opcode_rpd + * @details release_power_down (not needed for macronix) + * @{ + */ +#define SHUB_FLASH_CTRL0__OPCODE_RPD__SHIFT 24 +#define SHUB_FLASH_CTRL0__OPCODE_RPD__WIDTH 8 +#define SHUB_FLASH_CTRL0__OPCODE_RPD__MASK 0xff000000U +#define SHUB_FLASH_CTRL0__OPCODE_RPD__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SHUB_FLASH_CTRL0__OPCODE_RPD__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SHUB_FLASH_CTRL0__OPCODE_RPD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SHUB_FLASH_CTRL0__OPCODE_RPD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SHUB_FLASH_CTRL0__OPCODE_RPD__RESET_VALUE 0x000000abU +/** @} */ +#define SHUB_FLASH_CTRL0__TYPE uint32_t +#define SHUB_FLASH_CTRL0__READ 0xffffffffU +#define SHUB_FLASH_CTRL0__WRITE 0xffffffffU +#define SHUB_FLASH_CTRL0__PRESERVED 0xffffffffU +#define SHUB_FLASH_CTRL0__RESET_VALUE 0xabb90206U + +#endif /* __SHUB_FLASH_CTRL0_MACRO__ */ + +/** @} end of flash_ctrl0 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_flash_ctrl1 */ +/** + * @defgroup at_apb_shub_regs_core_flash_ctrl1 flash_ctrl1 + * @brief Contains register fields associated with flash_ctrl1. definitions. + * @{ + */ +#ifndef __SHUB_FLASH_CTRL1_MACRO__ +#define __SHUB_FLASH_CTRL1_MACRO__ + +/* macros for field wr_start_address */ +/** + * @defgroup at_apb_shub_regs_core_wr_start_address_field wr_start_address_field + * @brief macros for field wr_start_address + * @{ + */ +#define SHUB_FLASH_CTRL1__WR_START_ADDRESS__SHIFT 0 +#define SHUB_FLASH_CTRL1__WR_START_ADDRESS__WIDTH 24 +#define SHUB_FLASH_CTRL1__WR_START_ADDRESS__MASK 0x00ffffffU +#define SHUB_FLASH_CTRL1__WR_START_ADDRESS__READ(src) \ + ((uint32_t)(src)\ + & 0x00ffffffU) +#define SHUB_FLASH_CTRL1__WR_START_ADDRESS__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00ffffffU) +#define SHUB_FLASH_CTRL1__WR_START_ADDRESS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((uint32_t)(src) &\ + 0x00ffffffU) +#define SHUB_FLASH_CTRL1__WR_START_ADDRESS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00ffffffU))) +#define SHUB_FLASH_CTRL1__WR_START_ADDRESS__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_FLASH_CTRL1__TYPE uint32_t +#define SHUB_FLASH_CTRL1__READ 0x00ffffffU +#define SHUB_FLASH_CTRL1__WRITE 0x00ffffffU +#define SHUB_FLASH_CTRL1__PRESERVED 0x00ffffffU +#define SHUB_FLASH_CTRL1__RESET_VALUE 0x00000000U + +#endif /* __SHUB_FLASH_CTRL1_MACRO__ */ + +/** @} end of flash_ctrl1 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_flash_ctrl2 */ +/** + * @defgroup at_apb_shub_regs_core_flash_ctrl2 flash_ctrl2 + * @brief Contains register fields associated with flash_ctrl2. definitions. + * @{ + */ +#ifndef __SHUB_FLASH_CTRL2_MACRO__ +#define __SHUB_FLASH_CTRL2_MACRO__ + +/* macros for field wr_max_address */ +/** + * @defgroup at_apb_shub_regs_core_wr_max_address_field wr_max_address_field + * @brief macros for field wr_max_address + * @{ + */ +#define SHUB_FLASH_CTRL2__WR_MAX_ADDRESS__SHIFT 0 +#define SHUB_FLASH_CTRL2__WR_MAX_ADDRESS__WIDTH 24 +#define SHUB_FLASH_CTRL2__WR_MAX_ADDRESS__MASK 0x00ffffffU +#define SHUB_FLASH_CTRL2__WR_MAX_ADDRESS__READ(src) \ + ((uint32_t)(src)\ + & 0x00ffffffU) +#define SHUB_FLASH_CTRL2__WR_MAX_ADDRESS__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00ffffffU) +#define SHUB_FLASH_CTRL2__WR_MAX_ADDRESS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((uint32_t)(src) &\ + 0x00ffffffU) +#define SHUB_FLASH_CTRL2__WR_MAX_ADDRESS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00ffffffU))) +#define SHUB_FLASH_CTRL2__WR_MAX_ADDRESS__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_FLASH_CTRL2__TYPE uint32_t +#define SHUB_FLASH_CTRL2__READ 0x00ffffffU +#define SHUB_FLASH_CTRL2__WRITE 0x00ffffffU +#define SHUB_FLASH_CTRL2__PRESERVED 0x00ffffffU +#define SHUB_FLASH_CTRL2__RESET_VALUE 0x00000000U + +#endif /* __SHUB_FLASH_CTRL2_MACRO__ */ + +/** @} end of flash_ctrl2 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_flash_ctrl3 */ +/** + * @defgroup at_apb_shub_regs_core_flash_ctrl3 flash_ctrl3 + * @brief Contains register fields associated with flash_ctrl3. definitions. + * @{ + */ +#ifndef __SHUB_FLASH_CTRL3_MACRO__ +#define __SHUB_FLASH_CTRL3_MACRO__ + +/* macros for field power_cycle_en */ +/** + * @defgroup at_apb_shub_regs_core_power_cycle_en_field power_cycle_en_field + * @brief macros for field power_cycle_en + * @details 1= cycle flash into and out of deep power down mode. + * @{ + */ +#define SHUB_FLASH_CTRL3__POWER_CYCLE_EN__SHIFT 0 +#define SHUB_FLASH_CTRL3__POWER_CYCLE_EN__WIDTH 1 +#define SHUB_FLASH_CTRL3__POWER_CYCLE_EN__MASK 0x00000001U +#define SHUB_FLASH_CTRL3__POWER_CYCLE_EN__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_FLASH_CTRL3__POWER_CYCLE_EN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_FLASH_CTRL3__POWER_CYCLE_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_FLASH_CTRL3__POWER_CYCLE_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_FLASH_CTRL3__POWER_CYCLE_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_FLASH_CTRL3__POWER_CYCLE_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_FLASH_CTRL3__POWER_CYCLE_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field serialize_opcode */ +/** + * @defgroup at_apb_shub_regs_core_serialize_opcode_field serialize_opcode_field + * @brief macros for field serialize_opcode + * @details 1= opcode is serial even in quad mode. + * @{ + */ +#define SHUB_FLASH_CTRL3__SERIALIZE_OPCODE__SHIFT 1 +#define SHUB_FLASH_CTRL3__SERIALIZE_OPCODE__WIDTH 1 +#define SHUB_FLASH_CTRL3__SERIALIZE_OPCODE__MASK 0x00000002U +#define SHUB_FLASH_CTRL3__SERIALIZE_OPCODE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define SHUB_FLASH_CTRL3__SERIALIZE_OPCODE__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define SHUB_FLASH_CTRL3__SERIALIZE_OPCODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define SHUB_FLASH_CTRL3__SERIALIZE_OPCODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define SHUB_FLASH_CTRL3__SERIALIZE_OPCODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SHUB_FLASH_CTRL3__SERIALIZE_OPCODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SHUB_FLASH_CTRL3__SERIALIZE_OPCODE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field qspi_mode */ +/** + * @defgroup at_apb_shub_regs_core_qspi_mode_field qspi_mode_field + * @brief macros for field qspi_mode + * @details 0,1,3 = single spi mode; 2 = qspi mode + * @{ + */ +#define SHUB_FLASH_CTRL3__QSPI_MODE__SHIFT 2 +#define SHUB_FLASH_CTRL3__QSPI_MODE__WIDTH 2 +#define SHUB_FLASH_CTRL3__QSPI_MODE__MASK 0x0000000cU +#define SHUB_FLASH_CTRL3__QSPI_MODE__READ(src) \ + (((uint32_t)(src)\ + & 0x0000000cU) >> 2) +#define SHUB_FLASH_CTRL3__QSPI_MODE__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000000cU) +#define SHUB_FLASH_CTRL3__QSPI_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((uint32_t)(src) <<\ + 2) & 0x0000000cU) +#define SHUB_FLASH_CTRL3__QSPI_MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000000cU))) +#define SHUB_FLASH_CTRL3__QSPI_MODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_flash_overflow */ +/** + * @defgroup at_apb_shub_regs_core_clear_flash_overflow_field clear_flash_overflow_field + * @brief macros for field clear_flash_overflow + * @{ + */ +#define SHUB_FLASH_CTRL3__CLEAR_FLASH_OVERFLOW__SHIFT 4 +#define SHUB_FLASH_CTRL3__CLEAR_FLASH_OVERFLOW__WIDTH 1 +#define SHUB_FLASH_CTRL3__CLEAR_FLASH_OVERFLOW__MASK 0x00000010U +#define SHUB_FLASH_CTRL3__CLEAR_FLASH_OVERFLOW__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define SHUB_FLASH_CTRL3__CLEAR_FLASH_OVERFLOW__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define SHUB_FLASH_CTRL3__CLEAR_FLASH_OVERFLOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define SHUB_FLASH_CTRL3__CLEAR_FLASH_OVERFLOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define SHUB_FLASH_CTRL3__CLEAR_FLASH_OVERFLOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define SHUB_FLASH_CTRL3__CLEAR_FLASH_OVERFLOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define SHUB_FLASH_CTRL3__CLEAR_FLASH_OVERFLOW__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clear_lost_write_cnt */ +/** + * @defgroup at_apb_shub_regs_core_clear_lost_write_cnt_field clear_lost_write_cnt_field + * @brief macros for field clear_lost_write_cnt + * @{ + */ +#define SHUB_FLASH_CTRL3__CLEAR_LOST_WRITE_CNT__SHIFT 5 +#define SHUB_FLASH_CTRL3__CLEAR_LOST_WRITE_CNT__WIDTH 1 +#define SHUB_FLASH_CTRL3__CLEAR_LOST_WRITE_CNT__MASK 0x00000020U +#define SHUB_FLASH_CTRL3__CLEAR_LOST_WRITE_CNT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define SHUB_FLASH_CTRL3__CLEAR_LOST_WRITE_CNT__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define SHUB_FLASH_CTRL3__CLEAR_LOST_WRITE_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define SHUB_FLASH_CTRL3__CLEAR_LOST_WRITE_CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define SHUB_FLASH_CTRL3__CLEAR_LOST_WRITE_CNT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define SHUB_FLASH_CTRL3__CLEAR_LOST_WRITE_CNT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define SHUB_FLASH_CTRL3__CLEAR_LOST_WRITE_CNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field serialize_pp_address */ +/** + * @defgroup at_apb_shub_regs_core_serialize_pp_address_field serialize_pp_address_field + * @brief macros for field serialize_pp_address + * @{ + */ +#define SHUB_FLASH_CTRL3__SERIALIZE_PP_ADDRESS__SHIFT 6 +#define SHUB_FLASH_CTRL3__SERIALIZE_PP_ADDRESS__WIDTH 1 +#define SHUB_FLASH_CTRL3__SERIALIZE_PP_ADDRESS__MASK 0x00000040U +#define SHUB_FLASH_CTRL3__SERIALIZE_PP_ADDRESS__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define SHUB_FLASH_CTRL3__SERIALIZE_PP_ADDRESS__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define SHUB_FLASH_CTRL3__SERIALIZE_PP_ADDRESS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define SHUB_FLASH_CTRL3__SERIALIZE_PP_ADDRESS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define SHUB_FLASH_CTRL3__SERIALIZE_PP_ADDRESS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define SHUB_FLASH_CTRL3__SERIALIZE_PP_ADDRESS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define SHUB_FLASH_CTRL3__SERIALIZE_PP_ADDRESS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rpd_has_clock */ +/** + * @defgroup at_apb_shub_regs_core_rpd_has_clock_field rpd_has_clock_field + * @brief macros for field rpd_has_clock + * @details for Macronix flash, rpd has no clock + * @{ + */ +#define SHUB_FLASH_CTRL3__RPD_HAS_CLOCK__SHIFT 7 +#define SHUB_FLASH_CTRL3__RPD_HAS_CLOCK__WIDTH 1 +#define SHUB_FLASH_CTRL3__RPD_HAS_CLOCK__MASK 0x00000080U +#define SHUB_FLASH_CTRL3__RPD_HAS_CLOCK__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define SHUB_FLASH_CTRL3__RPD_HAS_CLOCK__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define SHUB_FLASH_CTRL3__RPD_HAS_CLOCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define SHUB_FLASH_CTRL3__RPD_HAS_CLOCK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define SHUB_FLASH_CTRL3__RPD_HAS_CLOCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define SHUB_FLASH_CTRL3__RPD_HAS_CLOCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define SHUB_FLASH_CTRL3__RPD_HAS_CLOCK__RESET_VALUE 0x00000001U +/** @} */ +#define SHUB_FLASH_CTRL3__TYPE uint32_t +#define SHUB_FLASH_CTRL3__READ 0x000000ffU +#define SHUB_FLASH_CTRL3__WRITE 0x000000ffU +#define SHUB_FLASH_CTRL3__PRESERVED 0x000000ffU +#define SHUB_FLASH_CTRL3__RESET_VALUE 0x00000082U + +#endif /* __SHUB_FLASH_CTRL3_MACRO__ */ + +/** @} end of flash_ctrl3 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_flash_ctrl4 */ +/** + * @defgroup at_apb_shub_regs_core_flash_ctrl4 flash_ctrl4 + * @brief Contains register fields associated with flash_ctrl4. definitions. + * @{ + */ +#ifndef __SHUB_FLASH_CTRL4_MACRO__ +#define __SHUB_FLASH_CTRL4_MACRO__ + +/* macros for field pp_delay */ +/** + * @defgroup at_apb_shub_regs_core_pp_delay_field pp_delay_field + * @brief macros for field pp_delay + * @details delay cycles (pp_delay+1) after flash write. (320 cycles of 32k clock = 10ms pp time from Macronix) + * @{ + */ +#define SHUB_FLASH_CTRL4__PP_DELAY__SHIFT 0 +#define SHUB_FLASH_CTRL4__PP_DELAY__WIDTH 12 +#define SHUB_FLASH_CTRL4__PP_DELAY__MASK 0x00000fffU +#define SHUB_FLASH_CTRL4__PP_DELAY__READ(src) ((uint32_t)(src) & 0x00000fffU) +#define SHUB_FLASH_CTRL4__PP_DELAY__WRITE(src) ((uint32_t)(src) & 0x00000fffU) +#define SHUB_FLASH_CTRL4__PP_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((uint32_t)(src) &\ + 0x00000fffU) +#define SHUB_FLASH_CTRL4__PP_DELAY__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000fffU))) +#define SHUB_FLASH_CTRL4__PP_DELAY__RESET_VALUE 0x00000140U +/** @} */ + +/* macros for field pd_delay */ +/** + * @defgroup at_apb_shub_regs_core_pd_delay_field pd_delay_field + * @brief macros for field pd_delay + * @details delay cycles (pd_delay+1) after flash power down / release from power down + * @{ + */ +#define SHUB_FLASH_CTRL4__PD_DELAY__SHIFT 20 +#define SHUB_FLASH_CTRL4__PD_DELAY__WIDTH 8 +#define SHUB_FLASH_CTRL4__PD_DELAY__MASK 0x0ff00000U +#define SHUB_FLASH_CTRL4__PD_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x0ff00000U) >> 20) +#define SHUB_FLASH_CTRL4__PD_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x0ff00000U) +#define SHUB_FLASH_CTRL4__PD_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x0ff00000U) +#define SHUB_FLASH_CTRL4__PD_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x0ff00000U))) +#define SHUB_FLASH_CTRL4__PD_DELAY__RESET_VALUE 0x00000002U +/** @} */ +#define SHUB_FLASH_CTRL4__TYPE uint32_t +#define SHUB_FLASH_CTRL4__READ 0x0ff00fffU +#define SHUB_FLASH_CTRL4__WRITE 0x0ff00fffU +#define SHUB_FLASH_CTRL4__PRESERVED 0x0ff00fffU +#define SHUB_FLASH_CTRL4__RESET_VALUE 0x00200140U + +#endif /* __SHUB_FLASH_CTRL4_MACRO__ */ + +/** @} end of flash_ctrl4 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_flash_status0 */ +/** + * @defgroup at_apb_shub_regs_core_flash_status0 flash_status0 + * @brief Contains register fields associated with flash_status0. definitions. + * @{ + */ +#ifndef __SHUB_FLASH_STATUS0_MACRO__ +#define __SHUB_FLASH_STATUS0_MACRO__ + +/* macros for field wr_current_address */ +/** + * @defgroup at_apb_shub_regs_core_wr_current_address_field wr_current_address_field + * @brief macros for field wr_current_address + * @details the next address to write to. Number of bytes in storage = wr_current_address - wr_start_address. + * @{ + */ +#define SHUB_FLASH_STATUS0__WR_CURRENT_ADDRESS__SHIFT 0 +#define SHUB_FLASH_STATUS0__WR_CURRENT_ADDRESS__WIDTH 24 +#define SHUB_FLASH_STATUS0__WR_CURRENT_ADDRESS__MASK 0x00ffffffU +#define SHUB_FLASH_STATUS0__WR_CURRENT_ADDRESS__READ(src) \ + ((uint32_t)(src)\ + & 0x00ffffffU) +#define SHUB_FLASH_STATUS0__WR_CURRENT_ADDRESS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wr_saturated */ +/** + * @defgroup at_apb_shub_regs_core_wr_saturated_field wr_saturated_field + * @brief macros for field wr_saturated + * @details indicates overflow. + * @{ + */ +#define SHUB_FLASH_STATUS0__WR_SATURATED__SHIFT 24 +#define SHUB_FLASH_STATUS0__WR_SATURATED__WIDTH 1 +#define SHUB_FLASH_STATUS0__WR_SATURATED__MASK 0x01000000U +#define SHUB_FLASH_STATUS0__WR_SATURATED__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SHUB_FLASH_STATUS0__WR_SATURATED__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SHUB_FLASH_STATUS0__WR_SATURATED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SHUB_FLASH_STATUS0__WR_SATURATED__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_FLASH_STATUS0__TYPE uint32_t +#define SHUB_FLASH_STATUS0__READ 0x01ffffffU +#define SHUB_FLASH_STATUS0__PRESERVED 0x00000000U +#define SHUB_FLASH_STATUS0__RESET_VALUE 0x00000000U + +#endif /* __SHUB_FLASH_STATUS0_MACRO__ */ + +/** @} end of flash_status0 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_flash_status1 */ +/** + * @defgroup at_apb_shub_regs_core_flash_status1 flash_status1 + * @brief Contains register fields associated with flash_status1. definitions. + * @{ + */ +#ifndef __SHUB_FLASH_STATUS1_MACRO__ +#define __SHUB_FLASH_STATUS1_MACRO__ + +/* macros for field lost_write_cnt */ +/** + * @defgroup at_apb_shub_regs_core_lost_write_cnt_field lost_write_cnt_field + * @brief macros for field lost_write_cnt + * @{ + */ +#define SHUB_FLASH_STATUS1__LOST_WRITE_CNT__SHIFT 0 +#define SHUB_FLASH_STATUS1__LOST_WRITE_CNT__WIDTH 32 +#define SHUB_FLASH_STATUS1__LOST_WRITE_CNT__MASK 0xffffffffU +#define SHUB_FLASH_STATUS1__LOST_WRITE_CNT__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define SHUB_FLASH_STATUS1__LOST_WRITE_CNT__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_FLASH_STATUS1__TYPE uint32_t +#define SHUB_FLASH_STATUS1__READ 0xffffffffU +#define SHUB_FLASH_STATUS1__PRESERVED 0x00000000U +#define SHUB_FLASH_STATUS1__RESET_VALUE 0x00000000U + +#endif /* __SHUB_FLASH_STATUS1_MACRO__ */ + +/** @} end of flash_status1 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_shub_status0 */ +/** + * @defgroup at_apb_shub_regs_core_shub_status0 shub_status0 + * @brief Contains register fields associated with shub_status0. definitions. + * @{ + */ +#ifndef __SHUB_SHUB_STATUS0_MACRO__ +#define __SHUB_SHUB_STATUS0_MACRO__ + +/* macros for field state */ +/** + * @defgroup at_apb_shub_regs_core_state_field state_field + * @brief macros for field state + * @details useful for testing + * @{ + */ +#define SHUB_SHUB_STATUS0__STATE__SHIFT 0 +#define SHUB_SHUB_STATUS0__STATE__WIDTH 5 +#define SHUB_SHUB_STATUS0__STATE__MASK 0x0000001fU +#define SHUB_SHUB_STATUS0__STATE__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define SHUB_SHUB_STATUS0__STATE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cpu_running */ +/** + * @defgroup at_apb_shub_regs_core_cpu_running_field cpu_running_field + * @brief macros for field cpu_running + * @details useful for testing + * @{ + */ +#define SHUB_SHUB_STATUS0__CPU_RUNNING__SHIFT 31 +#define SHUB_SHUB_STATUS0__CPU_RUNNING__WIDTH 1 +#define SHUB_SHUB_STATUS0__CPU_RUNNING__MASK 0x80000000U +#define SHUB_SHUB_STATUS0__CPU_RUNNING__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define SHUB_SHUB_STATUS0__CPU_RUNNING__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define SHUB_SHUB_STATUS0__CPU_RUNNING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define SHUB_SHUB_STATUS0__CPU_RUNNING__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_SHUB_STATUS0__TYPE uint32_t +#define SHUB_SHUB_STATUS0__READ 0x8000001fU +#define SHUB_SHUB_STATUS0__PRESERVED 0x00000000U +#define SHUB_SHUB_STATUS0__RESET_VALUE 0x00000000U + +#endif /* __SHUB_SHUB_STATUS0_MACRO__ */ + +/** @} end of shub_status0 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_pc_ctrl */ +/** + * @defgroup at_apb_shub_regs_core_pc_ctrl pc_ctrl + * @brief Contains register fields associated with pc_ctrl. definitions. + * @{ + */ +#ifndef __SHUB_PC_CTRL_MACRO__ +#define __SHUB_PC_CTRL_MACRO__ + +/* macros for field pc_init */ +/** + * @defgroup at_apb_shub_regs_core_pc_init_field pc_init_field + * @brief macros for field pc_init + * @details iniital pc value + * @{ + */ +#define SHUB_PC_CTRL__PC_INIT__SHIFT 0 +#define SHUB_PC_CTRL__PC_INIT__WIDTH 32 +#define SHUB_PC_CTRL__PC_INIT__MASK 0xffffffffU +#define SHUB_PC_CTRL__PC_INIT__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define SHUB_PC_CTRL__PC_INIT__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define SHUB_PC_CTRL__PC_INIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define SHUB_PC_CTRL__PC_INIT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define SHUB_PC_CTRL__PC_INIT__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PC_CTRL__TYPE uint32_t +#define SHUB_PC_CTRL__READ 0xffffffffU +#define SHUB_PC_CTRL__WRITE 0xffffffffU +#define SHUB_PC_CTRL__PRESERVED 0xffffffffU +#define SHUB_PC_CTRL__RESET_VALUE 0x00000000U + +#endif /* __SHUB_PC_CTRL_MACRO__ */ + +/** @} end of pc_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SHUB_pc_ctrl2 */ +/** + * @defgroup at_apb_shub_regs_core_pc_ctrl2 pc_ctrl2 + * @brief Contains register fields associated with pc_ctrl2. definitions. + * @{ + */ +#ifndef __SHUB_PC_CTRL2_MACRO__ +#define __SHUB_PC_CTRL2_MACRO__ + +/* macros for field pc_init_load */ +/** + * @defgroup at_apb_shub_regs_core_pc_init_load_field pc_init_load_field + * @brief macros for field pc_init_load + * @details iniital pc value load; not self-clearing + * @{ + */ +#define SHUB_PC_CTRL2__PC_INIT_LOAD__SHIFT 0 +#define SHUB_PC_CTRL2__PC_INIT_LOAD__WIDTH 1 +#define SHUB_PC_CTRL2__PC_INIT_LOAD__MASK 0x00000001U +#define SHUB_PC_CTRL2__PC_INIT_LOAD__READ(src) ((uint32_t)(src) & 0x00000001U) +#define SHUB_PC_CTRL2__PC_INIT_LOAD__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define SHUB_PC_CTRL2__PC_INIT_LOAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_PC_CTRL2__PC_INIT_LOAD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_PC_CTRL2__PC_INIT_LOAD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_PC_CTRL2__PC_INIT_LOAD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_PC_CTRL2__PC_INIT_LOAD__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_PC_CTRL2__TYPE uint32_t +#define SHUB_PC_CTRL2__READ 0x00000001U +#define SHUB_PC_CTRL2__WRITE 0x00000001U +#define SHUB_PC_CTRL2__PRESERVED 0x00000001U +#define SHUB_PC_CTRL2__RESET_VALUE 0x00000000U + +#endif /* __SHUB_PC_CTRL2_MACRO__ */ + +/** @} end of pc_ctrl2 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_reg7 */ +/** + * @defgroup at_apb_shub_regs_core_reg7 reg7 + * @brief Contains register fields associated with reg7. definitions. + * @{ + */ +#ifndef __SHUB_REG7_MACRO__ +#define __SHUB_REG7_MACRO__ + +/* macros for field r7 */ +/** + * @defgroup at_apb_shub_regs_core_r7_field r7_field + * @brief macros for field r7 + * @details value of reg7 + * @{ + */ +#define SHUB_REG7__R7__SHIFT 0 +#define SHUB_REG7__R7__WIDTH 32 +#define SHUB_REG7__R7__MASK 0xffffffffU +#define SHUB_REG7__R7__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define SHUB_REG7__R7__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_REG7__TYPE uint32_t +#define SHUB_REG7__READ 0xffffffffU +#define SHUB_REG7__PRESERVED 0x00000000U +#define SHUB_REG7__RESET_VALUE 0x00000000U + +#endif /* __SHUB_REG7_MACRO__ */ + +/** @} end of reg7 */ + +/* macros for BlueprintGlobalNameSpace::SHUB_shub_sram_clk_sel */ +/** + * @defgroup at_apb_shub_regs_core_shub_sram_clk_sel shub_sram_clk_sel + * @brief clock selection between PCLK and clk_lpc as to drive SRAM. definitions. + * @{ + */ +#ifndef __SHUB_SHUB_SRAM_CLK_SEL_MACRO__ +#define __SHUB_SHUB_SRAM_CLK_SEL_MACRO__ + +/* macros for field shub_sram_clk_sel_ovrd */ +/** + * @defgroup at_apb_shub_regs_core_shub_sram_clk_sel_ovrd_field shub_sram_clk_sel_ovrd_field + * @brief macros for field shub_sram_clk_sel_ovrd + * @details override bit to shub_sram_clk mux + * @{ + */ +#define SHUB_SHUB_SRAM_CLK_SEL__SHUB_SRAM_CLK_SEL_OVRD__SHIFT 0 +#define SHUB_SHUB_SRAM_CLK_SEL__SHUB_SRAM_CLK_SEL_OVRD__WIDTH 1 +#define SHUB_SHUB_SRAM_CLK_SEL__SHUB_SRAM_CLK_SEL_OVRD__MASK 0x00000001U +#define SHUB_SHUB_SRAM_CLK_SEL__SHUB_SRAM_CLK_SEL_OVRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_SHUB_SRAM_CLK_SEL__SHUB_SRAM_CLK_SEL_OVRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SHUB_SHUB_SRAM_CLK_SEL__SHUB_SRAM_CLK_SEL_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SHUB_SHUB_SRAM_CLK_SEL__SHUB_SRAM_CLK_SEL_OVRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SHUB_SHUB_SRAM_CLK_SEL__SHUB_SRAM_CLK_SEL_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SHUB_SHUB_SRAM_CLK_SEL__SHUB_SRAM_CLK_SEL_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SHUB_SHUB_SRAM_CLK_SEL__SHUB_SRAM_CLK_SEL_OVRD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field shub_sram_clk_sel_val */ +/** + * @defgroup at_apb_shub_regs_core_shub_sram_clk_sel_val_field shub_sram_clk_sel_val_field + * @brief macros for field shub_sram_clk_sel_val + * @details override val to shub_sram_clk mux. 0=PCLK ; 1=clk_lpc + * @{ + */ +#define SHUB_SHUB_SRAM_CLK_SEL__SHUB_SRAM_CLK_SEL_VAL__SHIFT 1 +#define SHUB_SHUB_SRAM_CLK_SEL__SHUB_SRAM_CLK_SEL_VAL__WIDTH 1 +#define SHUB_SHUB_SRAM_CLK_SEL__SHUB_SRAM_CLK_SEL_VAL__MASK 0x00000002U +#define SHUB_SHUB_SRAM_CLK_SEL__SHUB_SRAM_CLK_SEL_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define SHUB_SHUB_SRAM_CLK_SEL__SHUB_SRAM_CLK_SEL_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define SHUB_SHUB_SRAM_CLK_SEL__SHUB_SRAM_CLK_SEL_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define SHUB_SHUB_SRAM_CLK_SEL__SHUB_SRAM_CLK_SEL_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define SHUB_SHUB_SRAM_CLK_SEL__SHUB_SRAM_CLK_SEL_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SHUB_SHUB_SRAM_CLK_SEL__SHUB_SRAM_CLK_SEL_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SHUB_SHUB_SRAM_CLK_SEL__SHUB_SRAM_CLK_SEL_VAL__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_SHUB_SRAM_CLK_SEL__TYPE uint32_t +#define SHUB_SHUB_SRAM_CLK_SEL__READ 0x00000003U +#define SHUB_SHUB_SRAM_CLK_SEL__WRITE 0x00000003U +#define SHUB_SHUB_SRAM_CLK_SEL__PRESERVED 0x00000003U +#define SHUB_SHUB_SRAM_CLK_SEL__RESET_VALUE 0x00000000U + +#endif /* __SHUB_SHUB_SRAM_CLK_SEL_MACRO__ */ + +/** @} end of shub_sram_clk_sel */ + +/* macros for BlueprintGlobalNameSpace::SHUB_regfile_sel */ +/** + * @defgroup at_apb_shub_regs_core_regfile_sel regfile_sel + * @brief Contains register fields associated with regfile_sel. definitions. + * @{ + */ +#ifndef __SHUB_REGFILE_SEL_MACRO__ +#define __SHUB_REGFILE_SEL_MACRO__ + +/* macros for field sel */ +/** + * @defgroup at_apb_shub_regs_core_sel_field sel_field + * @brief macros for field sel + * @details select which reg in regfile to be connected to reg7 + * @{ + */ +#define SHUB_REGFILE_SEL__SEL__SHIFT 0 +#define SHUB_REGFILE_SEL__SEL__WIDTH 4 +#define SHUB_REGFILE_SEL__SEL__MASK 0x0000000fU +#define SHUB_REGFILE_SEL__SEL__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define SHUB_REGFILE_SEL__SEL__WRITE(src) ((uint32_t)(src) & 0x0000000fU) +#define SHUB_REGFILE_SEL__SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define SHUB_REGFILE_SEL__SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define SHUB_REGFILE_SEL__SEL__RESET_VALUE 0x00000007U +/** @} */ +#define SHUB_REGFILE_SEL__TYPE uint32_t +#define SHUB_REGFILE_SEL__READ 0x0000000fU +#define SHUB_REGFILE_SEL__WRITE 0x0000000fU +#define SHUB_REGFILE_SEL__PRESERVED 0x00000000U +#define SHUB_REGFILE_SEL__RESET_VALUE 0x00000007U + +#endif /* __SHUB_REGFILE_SEL_MACRO__ */ + +/** @} end of regfile_sel */ + +/* macros for BlueprintGlobalNameSpace::SHUB_regfile_regw */ +/** + * @defgroup at_apb_shub_regs_core_regfile_regw regfile_regw + * @brief Contains register fields associated with regfile_regw. definitions. + * @{ + */ +#ifndef __SHUB_REGFILE_REGW_MACRO__ +#define __SHUB_REGFILE_REGW_MACRO__ + +/* macros for field regfile_wdata */ +/** + * @defgroup at_apb_shub_regs_core_regfile_wdata_field regfile_wdata_field + * @brief macros for field regfile_wdata + * @details write data to selected reg in regfile. The selection pointer is regfile_sel + * @{ + */ +#define SHUB_REGFILE_REGW__REGFILE_WDATA__SHIFT 0 +#define SHUB_REGFILE_REGW__REGFILE_WDATA__WIDTH 32 +#define SHUB_REGFILE_REGW__REGFILE_WDATA__MASK 0xffffffffU +#define SHUB_REGFILE_REGW__REGFILE_WDATA__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define SHUB_REGFILE_REGW__REGFILE_WDATA__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define SHUB_REGFILE_REGW__REGFILE_WDATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define SHUB_REGFILE_REGW__REGFILE_WDATA__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define SHUB_REGFILE_REGW__REGFILE_WDATA__RESET_VALUE 0x00000000U +/** @} */ +#define SHUB_REGFILE_REGW__TYPE uint32_t +#define SHUB_REGFILE_REGW__READ 0xffffffffU +#define SHUB_REGFILE_REGW__WRITE 0xffffffffU +#define SHUB_REGFILE_REGW__PRESERVED 0x00000000U +#define SHUB_REGFILE_REGW__RESET_VALUE 0x00000000U + +#endif /* __SHUB_REGFILE_REGW_MACRO__ */ + +/** @} end of regfile_regw */ + +/* macros for BlueprintGlobalNameSpace::SHUB_id */ +/** + * @defgroup at_apb_shub_regs_core_id id + * @brief Contains register fields associated with id. definitions. + * @{ + */ +#ifndef __SHUB_ID_MACRO__ +#define __SHUB_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_shub_regs_core_id_field id_field + * @brief macros for field id + * @details SHUB in ASCII + * @{ + */ +#define SHUB_ID__ID__SHIFT 0 +#define SHUB_ID__ID__WIDTH 32 +#define SHUB_ID__ID__MASK 0xffffffffU +#define SHUB_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define SHUB_ID__ID__RESET_VALUE 0x53485542U +/** @} */ +#define SHUB_ID__TYPE uint32_t +#define SHUB_ID__READ 0xffffffffU +#define SHUB_ID__PRESERVED 0x00000000U +#define SHUB_ID__RESET_VALUE 0x53485542U + +#endif /* __SHUB_ID_MACRO__ */ + +/** @} end of id */ + +/** @} end of AT_APB_SHUB_REGS_CORE */ +#endif /* __REG_AT_APB_SHUB_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_apb_slwtimer_regs_core_macro.h b/ATM33xx-5/include/reg/at_apb_slwtimer_regs_core_macro.h new file mode 100644 index 0000000..c358c9a --- /dev/null +++ b/ATM33xx-5/include/reg/at_apb_slwtimer_regs_core_macro.h @@ -0,0 +1,970 @@ +/* */ +/* File: at_apb_slwtimer_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_apb_slwtimer_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_APB_SLWTIMER_REGS_CORE_H__ +#define __REG_AT_APB_SLWTIMER_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_APB_SLWTIMER_REGS_CORE at_apb_slwtimer_regs_core + * @ingroup AT_REG + * @brief at_apb_slwtimer_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::SLW_control */ +/** + * @defgroup at_apb_slwtimer_regs_core_control control + * @brief control definitions. + * @{ + */ +#ifndef __SLW_CONTROL_MACRO__ +#define __SLW_CONTROL_MACRO__ + +/* macros for field clear */ +/** + * @defgroup at_apb_slwtimer_regs_core_clear_field clear_field + * @brief macros for field clear + * @details clear slow timer + * @{ + */ +#define SLW_CONTROL__CLEAR__SHIFT 0 +#define SLW_CONTROL__CLEAR__WIDTH 1 +#define SLW_CONTROL__CLEAR__MASK 0x00000001U +#define SLW_CONTROL__CLEAR__READ(src) ((uint32_t)(src) & 0x00000001U) +#define SLW_CONTROL__CLEAR__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define SLW_CONTROL__CLEAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SLW_CONTROL__CLEAR__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define SLW_CONTROL__CLEAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SLW_CONTROL__CLEAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SLW_CONTROL__CLEAR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field load */ +/** + * @defgroup at_apb_slwtimer_regs_core_load_field load_field + * @brief macros for field load + * @details load slow timer + * @{ + */ +#define SLW_CONTROL__LOAD__SHIFT 1 +#define SLW_CONTROL__LOAD__WIDTH 1 +#define SLW_CONTROL__LOAD__MASK 0x00000002U +#define SLW_CONTROL__LOAD__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define SLW_CONTROL__LOAD__WRITE(src) (((uint32_t)(src) << 1) & 0x00000002U) +#define SLW_CONTROL__LOAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define SLW_CONTROL__LOAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define SLW_CONTROL__LOAD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SLW_CONTROL__LOAD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SLW_CONTROL__LOAD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reset_expired */ +/** + * @defgroup at_apb_slwtimer_regs_core_reset_expired_field reset_expired_field + * @brief macros for field reset_expired + * @details reset expired interrupt; not self clearing + * @{ + */ +#define SLW_CONTROL__RESET_EXPIRED__SHIFT 2 +#define SLW_CONTROL__RESET_EXPIRED__WIDTH 1 +#define SLW_CONTROL__RESET_EXPIRED__MASK 0x00000004U +#define SLW_CONTROL__RESET_EXPIRED__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define SLW_CONTROL__RESET_EXPIRED__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define SLW_CONTROL__RESET_EXPIRED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define SLW_CONTROL__RESET_EXPIRED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define SLW_CONTROL__RESET_EXPIRED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define SLW_CONTROL__RESET_EXPIRED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define SLW_CONTROL__RESET_EXPIRED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reset_thres0 */ +/** + * @defgroup at_apb_slwtimer_regs_core_reset_thres0_field reset_thres0_field + * @brief macros for field reset_thres0 + * @details reset thres0 interrupt; not self clearing + * @{ + */ +#define SLW_CONTROL__RESET_THRES0__SHIFT 3 +#define SLW_CONTROL__RESET_THRES0__WIDTH 1 +#define SLW_CONTROL__RESET_THRES0__MASK 0x00000008U +#define SLW_CONTROL__RESET_THRES0__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define SLW_CONTROL__RESET_THRES0__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define SLW_CONTROL__RESET_THRES0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define SLW_CONTROL__RESET_THRES0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define SLW_CONTROL__RESET_THRES0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define SLW_CONTROL__RESET_THRES0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define SLW_CONTROL__RESET_THRES0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reset_thres1 */ +/** + * @defgroup at_apb_slwtimer_regs_core_reset_thres1_field reset_thres1_field + * @brief macros for field reset_thres1 + * @details reset thres1 interrupt; not self clearing + * @{ + */ +#define SLW_CONTROL__RESET_THRES1__SHIFT 4 +#define SLW_CONTROL__RESET_THRES1__WIDTH 1 +#define SLW_CONTROL__RESET_THRES1__MASK 0x00000010U +#define SLW_CONTROL__RESET_THRES1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define SLW_CONTROL__RESET_THRES1__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define SLW_CONTROL__RESET_THRES1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define SLW_CONTROL__RESET_THRES1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define SLW_CONTROL__RESET_THRES1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define SLW_CONTROL__RESET_THRES1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define SLW_CONTROL__RESET_THRES1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reset_thres2 */ +/** + * @defgroup at_apb_slwtimer_regs_core_reset_thres2_field reset_thres2_field + * @brief macros for field reset_thres2 + * @details reset thres2 interrupt; not self clearing + * @{ + */ +#define SLW_CONTROL__RESET_THRES2__SHIFT 5 +#define SLW_CONTROL__RESET_THRES2__WIDTH 1 +#define SLW_CONTROL__RESET_THRES2__MASK 0x00000020U +#define SLW_CONTROL__RESET_THRES2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define SLW_CONTROL__RESET_THRES2__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define SLW_CONTROL__RESET_THRES2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define SLW_CONTROL__RESET_THRES2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define SLW_CONTROL__RESET_THRES2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define SLW_CONTROL__RESET_THRES2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define SLW_CONTROL__RESET_THRES2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field auto_reload */ +/** + * @defgroup at_apb_slwtimer_regs_core_auto_reload_field auto_reload_field + * @brief macros for field auto_reload + * @details auto reload slow timer with initial value after expiring + * @{ + */ +#define SLW_CONTROL__AUTO_RELOAD__SHIFT 8 +#define SLW_CONTROL__AUTO_RELOAD__WIDTH 1 +#define SLW_CONTROL__AUTO_RELOAD__MASK 0x00000100U +#define SLW_CONTROL__AUTO_RELOAD__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define SLW_CONTROL__AUTO_RELOAD__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define SLW_CONTROL__AUTO_RELOAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define SLW_CONTROL__AUTO_RELOAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define SLW_CONTROL__AUTO_RELOAD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define SLW_CONTROL__AUTO_RELOAD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define SLW_CONTROL__AUTO_RELOAD__RESET_VALUE 0x00000000U +/** @} */ +#define SLW_CONTROL__TYPE uint32_t +#define SLW_CONTROL__READ 0x0000013fU +#define SLW_CONTROL__WRITE 0x0000013fU +#define SLW_CONTROL__PRESERVED 0x00000000U +#define SLW_CONTROL__RESET_VALUE 0x00000000U + +#endif /* __SLW_CONTROL_MACRO__ */ + +/** @} end of control */ + +/* macros for BlueprintGlobalNameSpace::SLW_init_low */ +/** + * @defgroup at_apb_slwtimer_regs_core_init_low init_low + * @brief initial count value definitions. + * @{ + */ +#ifndef __SLW_INIT_LOW_MACRO__ +#define __SLW_INIT_LOW_MACRO__ + +/* macros for field init_low */ +/** + * @defgroup at_apb_slwtimer_regs_core_init_low_field init_low_field + * @brief macros for field init_low + * @details lower 32b of the 40b initial count value + * @{ + */ +#define SLW_INIT_LOW__INIT_LOW__SHIFT 0 +#define SLW_INIT_LOW__INIT_LOW__WIDTH 32 +#define SLW_INIT_LOW__INIT_LOW__MASK 0xffffffffU +#define SLW_INIT_LOW__INIT_LOW__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define SLW_INIT_LOW__INIT_LOW__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define SLW_INIT_LOW__INIT_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define SLW_INIT_LOW__INIT_LOW__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define SLW_INIT_LOW__INIT_LOW__RESET_VALUE 0x00000000U +/** @} */ +#define SLW_INIT_LOW__TYPE uint32_t +#define SLW_INIT_LOW__READ 0xffffffffU +#define SLW_INIT_LOW__WRITE 0xffffffffU +#define SLW_INIT_LOW__PRESERVED 0x00000000U +#define SLW_INIT_LOW__RESET_VALUE 0x00000000U + +#endif /* __SLW_INIT_LOW_MACRO__ */ + +/** @} end of init_low */ + +/* macros for BlueprintGlobalNameSpace::SLW_init_high */ +/** + * @defgroup at_apb_slwtimer_regs_core_init_high init_high + * @brief initial count value definitions. + * @{ + */ +#ifndef __SLW_INIT_HIGH_MACRO__ +#define __SLW_INIT_HIGH_MACRO__ + +/* macros for field init_high */ +/** + * @defgroup at_apb_slwtimer_regs_core_init_high_field init_high_field + * @brief macros for field init_high + * @details upper 8b of the 40b initial count value + * @{ + */ +#define SLW_INIT_HIGH__INIT_HIGH__SHIFT 0 +#define SLW_INIT_HIGH__INIT_HIGH__WIDTH 8 +#define SLW_INIT_HIGH__INIT_HIGH__MASK 0x000000ffU +#define SLW_INIT_HIGH__INIT_HIGH__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define SLW_INIT_HIGH__INIT_HIGH__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define SLW_INIT_HIGH__INIT_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SLW_INIT_HIGH__INIT_HIGH__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SLW_INIT_HIGH__INIT_HIGH__RESET_VALUE 0x00000000U +/** @} */ +#define SLW_INIT_HIGH__TYPE uint32_t +#define SLW_INIT_HIGH__READ 0x000000ffU +#define SLW_INIT_HIGH__WRITE 0x000000ffU +#define SLW_INIT_HIGH__PRESERVED 0x00000000U +#define SLW_INIT_HIGH__RESET_VALUE 0x00000000U + +#endif /* __SLW_INIT_HIGH_MACRO__ */ + +/** @} end of init_high */ + +/* macros for BlueprintGlobalNameSpace::SLW_cnt_low */ +/** + * @defgroup at_apb_slwtimer_regs_core_cnt_low cnt_low + * @brief current count value definitions. + * @{ + */ +#ifndef __SLW_CNT_LOW_MACRO__ +#define __SLW_CNT_LOW_MACRO__ + +/* macros for field cnt_low */ +/** + * @defgroup at_apb_slwtimer_regs_core_cnt_low_field cnt_low_field + * @brief macros for field cnt_low + * @details lower 32b of the 40b current count value + * @{ + */ +#define SLW_CNT_LOW__CNT_LOW__SHIFT 0 +#define SLW_CNT_LOW__CNT_LOW__WIDTH 32 +#define SLW_CNT_LOW__CNT_LOW__MASK 0xffffffffU +#define SLW_CNT_LOW__CNT_LOW__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define SLW_CNT_LOW__CNT_LOW__RESET_VALUE 0x00000000U +/** @} */ +#define SLW_CNT_LOW__TYPE uint32_t +#define SLW_CNT_LOW__READ 0xffffffffU +#define SLW_CNT_LOW__PRESERVED 0x00000000U +#define SLW_CNT_LOW__RESET_VALUE 0x00000000U + +#endif /* __SLW_CNT_LOW_MACRO__ */ + +/** @} end of cnt_low */ + +/* macros for BlueprintGlobalNameSpace::SLW_cnt_high */ +/** + * @defgroup at_apb_slwtimer_regs_core_cnt_high cnt_high + * @brief current count value definitions. + * @{ + */ +#ifndef __SLW_CNT_HIGH_MACRO__ +#define __SLW_CNT_HIGH_MACRO__ + +/* macros for field cnt_high */ +/** + * @defgroup at_apb_slwtimer_regs_core_cnt_high_field cnt_high_field + * @brief macros for field cnt_high + * @details upper 8b of the 40b current count value + * @{ + */ +#define SLW_CNT_HIGH__CNT_HIGH__SHIFT 0 +#define SLW_CNT_HIGH__CNT_HIGH__WIDTH 8 +#define SLW_CNT_HIGH__CNT_HIGH__MASK 0x000000ffU +#define SLW_CNT_HIGH__CNT_HIGH__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define SLW_CNT_HIGH__CNT_HIGH__RESET_VALUE 0x00000000U +/** @} */ +#define SLW_CNT_HIGH__TYPE uint32_t +#define SLW_CNT_HIGH__READ 0x000000ffU +#define SLW_CNT_HIGH__PRESERVED 0x00000000U +#define SLW_CNT_HIGH__RESET_VALUE 0x00000000U + +#endif /* __SLW_CNT_HIGH_MACRO__ */ + +/** @} end of cnt_high */ + +/* macros for BlueprintGlobalNameSpace::SLW_thres0_low */ +/** + * @defgroup at_apb_slwtimer_regs_core_thres0_low thres0_low + * @brief threshold 0 value definitions. + * @{ + */ +#ifndef __SLW_THRES0_LOW_MACRO__ +#define __SLW_THRES0_LOW_MACRO__ + +/* macros for field thres0_low */ +/** + * @defgroup at_apb_slwtimer_regs_core_thres0_low_field thres0_low_field + * @brief macros for field thres0_low + * @details lower 32b of the 40b threshold 0 value; when counter decrements from one above to this value, an optional interrupt triggers + * @{ + */ +#define SLW_THRES0_LOW__THRES0_LOW__SHIFT 0 +#define SLW_THRES0_LOW__THRES0_LOW__WIDTH 32 +#define SLW_THRES0_LOW__THRES0_LOW__MASK 0xffffffffU +#define SLW_THRES0_LOW__THRES0_LOW__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define SLW_THRES0_LOW__THRES0_LOW__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define SLW_THRES0_LOW__THRES0_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define SLW_THRES0_LOW__THRES0_LOW__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define SLW_THRES0_LOW__THRES0_LOW__RESET_VALUE 0x00000000U +/** @} */ +#define SLW_THRES0_LOW__TYPE uint32_t +#define SLW_THRES0_LOW__READ 0xffffffffU +#define SLW_THRES0_LOW__WRITE 0xffffffffU +#define SLW_THRES0_LOW__PRESERVED 0x00000000U +#define SLW_THRES0_LOW__RESET_VALUE 0x00000000U + +#endif /* __SLW_THRES0_LOW_MACRO__ */ + +/** @} end of thres0_low */ + +/* macros for BlueprintGlobalNameSpace::SLW_thres0_high */ +/** + * @defgroup at_apb_slwtimer_regs_core_thres0_high thres0_high + * @brief threshold 0 value definitions. + * @{ + */ +#ifndef __SLW_THRES0_HIGH_MACRO__ +#define __SLW_THRES0_HIGH_MACRO__ + +/* macros for field thres0_high */ +/** + * @defgroup at_apb_slwtimer_regs_core_thres0_high_field thres0_high_field + * @brief macros for field thres0_high + * @details upper 8b of the 40b theshold 0 value + * @{ + */ +#define SLW_THRES0_HIGH__THRES0_HIGH__SHIFT 0 +#define SLW_THRES0_HIGH__THRES0_HIGH__WIDTH 8 +#define SLW_THRES0_HIGH__THRES0_HIGH__MASK 0x000000ffU +#define SLW_THRES0_HIGH__THRES0_HIGH__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define SLW_THRES0_HIGH__THRES0_HIGH__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SLW_THRES0_HIGH__THRES0_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SLW_THRES0_HIGH__THRES0_HIGH__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SLW_THRES0_HIGH__THRES0_HIGH__RESET_VALUE 0x00000000U +/** @} */ +#define SLW_THRES0_HIGH__TYPE uint32_t +#define SLW_THRES0_HIGH__READ 0x000000ffU +#define SLW_THRES0_HIGH__WRITE 0x000000ffU +#define SLW_THRES0_HIGH__PRESERVED 0x00000000U +#define SLW_THRES0_HIGH__RESET_VALUE 0x00000000U + +#endif /* __SLW_THRES0_HIGH_MACRO__ */ + +/** @} end of thres0_high */ + +/* macros for BlueprintGlobalNameSpace::SLW_thres1_low */ +/** + * @defgroup at_apb_slwtimer_regs_core_thres1_low thres1_low + * @brief threshold 1 value definitions. + * @{ + */ +#ifndef __SLW_THRES1_LOW_MACRO__ +#define __SLW_THRES1_LOW_MACRO__ + +/* macros for field thres1_low */ +/** + * @defgroup at_apb_slwtimer_regs_core_thres1_low_field thres1_low_field + * @brief macros for field thres1_low + * @details lower 32b of the 40b threshold 1 value; when counter decrements from one above to this value, an optional interrupt triggers + * @{ + */ +#define SLW_THRES1_LOW__THRES1_LOW__SHIFT 0 +#define SLW_THRES1_LOW__THRES1_LOW__WIDTH 32 +#define SLW_THRES1_LOW__THRES1_LOW__MASK 0xffffffffU +#define SLW_THRES1_LOW__THRES1_LOW__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define SLW_THRES1_LOW__THRES1_LOW__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define SLW_THRES1_LOW__THRES1_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define SLW_THRES1_LOW__THRES1_LOW__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define SLW_THRES1_LOW__THRES1_LOW__RESET_VALUE 0x00000000U +/** @} */ +#define SLW_THRES1_LOW__TYPE uint32_t +#define SLW_THRES1_LOW__READ 0xffffffffU +#define SLW_THRES1_LOW__WRITE 0xffffffffU +#define SLW_THRES1_LOW__PRESERVED 0x00000000U +#define SLW_THRES1_LOW__RESET_VALUE 0x00000000U + +#endif /* __SLW_THRES1_LOW_MACRO__ */ + +/** @} end of thres1_low */ + +/* macros for BlueprintGlobalNameSpace::SLW_thres1_high */ +/** + * @defgroup at_apb_slwtimer_regs_core_thres1_high thres1_high + * @brief threshold 1 value definitions. + * @{ + */ +#ifndef __SLW_THRES1_HIGH_MACRO__ +#define __SLW_THRES1_HIGH_MACRO__ + +/* macros for field thres1_high */ +/** + * @defgroup at_apb_slwtimer_regs_core_thres1_high_field thres1_high_field + * @brief macros for field thres1_high + * @details upper 8b of the 40b theshold 1 value + * @{ + */ +#define SLW_THRES1_HIGH__THRES1_HIGH__SHIFT 0 +#define SLW_THRES1_HIGH__THRES1_HIGH__WIDTH 8 +#define SLW_THRES1_HIGH__THRES1_HIGH__MASK 0x000000ffU +#define SLW_THRES1_HIGH__THRES1_HIGH__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define SLW_THRES1_HIGH__THRES1_HIGH__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SLW_THRES1_HIGH__THRES1_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SLW_THRES1_HIGH__THRES1_HIGH__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SLW_THRES1_HIGH__THRES1_HIGH__RESET_VALUE 0x00000000U +/** @} */ +#define SLW_THRES1_HIGH__TYPE uint32_t +#define SLW_THRES1_HIGH__READ 0x000000ffU +#define SLW_THRES1_HIGH__WRITE 0x000000ffU +#define SLW_THRES1_HIGH__PRESERVED 0x00000000U +#define SLW_THRES1_HIGH__RESET_VALUE 0x00000000U + +#endif /* __SLW_THRES1_HIGH_MACRO__ */ + +/** @} end of thres1_high */ + +/* macros for BlueprintGlobalNameSpace::SLW_thres2_low */ +/** + * @defgroup at_apb_slwtimer_regs_core_thres2_low thres2_low + * @brief threshold 2 value definitions. + * @{ + */ +#ifndef __SLW_THRES2_LOW_MACRO__ +#define __SLW_THRES2_LOW_MACRO__ + +/* macros for field thres2_low */ +/** + * @defgroup at_apb_slwtimer_regs_core_thres2_low_field thres2_low_field + * @brief macros for field thres2_low + * @details lower 32b of the 40b threshold 2 value; when counter decrements from one above to this value, an optional interrupt triggers + * @{ + */ +#define SLW_THRES2_LOW__THRES2_LOW__SHIFT 0 +#define SLW_THRES2_LOW__THRES2_LOW__WIDTH 32 +#define SLW_THRES2_LOW__THRES2_LOW__MASK 0xffffffffU +#define SLW_THRES2_LOW__THRES2_LOW__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define SLW_THRES2_LOW__THRES2_LOW__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define SLW_THRES2_LOW__THRES2_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define SLW_THRES2_LOW__THRES2_LOW__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define SLW_THRES2_LOW__THRES2_LOW__RESET_VALUE 0x00000000U +/** @} */ +#define SLW_THRES2_LOW__TYPE uint32_t +#define SLW_THRES2_LOW__READ 0xffffffffU +#define SLW_THRES2_LOW__WRITE 0xffffffffU +#define SLW_THRES2_LOW__PRESERVED 0x00000000U +#define SLW_THRES2_LOW__RESET_VALUE 0x00000000U + +#endif /* __SLW_THRES2_LOW_MACRO__ */ + +/** @} end of thres2_low */ + +/* macros for BlueprintGlobalNameSpace::SLW_thres2_high */ +/** + * @defgroup at_apb_slwtimer_regs_core_thres2_high thres2_high + * @brief threshold 2 value definitions. + * @{ + */ +#ifndef __SLW_THRES2_HIGH_MACRO__ +#define __SLW_THRES2_HIGH_MACRO__ + +/* macros for field thres2_high */ +/** + * @defgroup at_apb_slwtimer_regs_core_thres2_high_field thres2_high_field + * @brief macros for field thres2_high + * @details upper 8b of the 40b theshold 2 value + * @{ + */ +#define SLW_THRES2_HIGH__THRES2_HIGH__SHIFT 0 +#define SLW_THRES2_HIGH__THRES2_HIGH__WIDTH 8 +#define SLW_THRES2_HIGH__THRES2_HIGH__MASK 0x000000ffU +#define SLW_THRES2_HIGH__THRES2_HIGH__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define SLW_THRES2_HIGH__THRES2_HIGH__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SLW_THRES2_HIGH__THRES2_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SLW_THRES2_HIGH__THRES2_HIGH__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SLW_THRES2_HIGH__THRES2_HIGH__RESET_VALUE 0x00000000U +/** @} */ +#define SLW_THRES2_HIGH__TYPE uint32_t +#define SLW_THRES2_HIGH__READ 0x000000ffU +#define SLW_THRES2_HIGH__WRITE 0x000000ffU +#define SLW_THRES2_HIGH__PRESERVED 0x00000000U +#define SLW_THRES2_HIGH__RESET_VALUE 0x00000000U + +#endif /* __SLW_THRES2_HIGH_MACRO__ */ + +/** @} end of thres2_high */ + +/* macros for BlueprintGlobalNameSpace::SLW_status */ +/** + * @defgroup at_apb_slwtimer_regs_core_status status + * @brief status information definitions. + * @{ + */ +#ifndef __SLW_STATUS_MACRO__ +#define __SLW_STATUS_MACRO__ + +/* macros for field op_running */ +/** + * @defgroup at_apb_slwtimer_regs_core_op_running_field op_running_field + * @brief macros for field op_running + * @details the operation (either load or clear) is still running; handoff to 32kHz domain takes time + * @{ + */ +#define SLW_STATUS__OP_RUNNING__SHIFT 0 +#define SLW_STATUS__OP_RUNNING__WIDTH 1 +#define SLW_STATUS__OP_RUNNING__MASK 0x00000001U +#define SLW_STATUS__OP_RUNNING__READ(src) ((uint32_t)(src) & 0x00000001U) +#define SLW_STATUS__OP_RUNNING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SLW_STATUS__OP_RUNNING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SLW_STATUS__OP_RUNNING__RESET_VALUE 0x00000000U +/** @} */ +#define SLW_STATUS__TYPE uint32_t +#define SLW_STATUS__READ 0x00000001U +#define SLW_STATUS__PRESERVED 0x00000000U +#define SLW_STATUS__RESET_VALUE 0x00000000U + +#endif /* __SLW_STATUS_MACRO__ */ + +/** @} end of status */ + +/* macros for BlueprintGlobalNameSpace::SLW_interrupt_status */ +/** + * @defgroup at_apb_slwtimer_regs_core_interrupt_status interrupt_status + * @brief interrupt status definitions. + * @{ + */ +#ifndef __SLW_INTERRUPT_STATUS_MACRO__ +#define __SLW_INTERRUPT_STATUS_MACRO__ + +/* macros for field expired */ +/** + * @defgroup at_apb_slwtimer_regs_core_expired_field expired_field + * @brief macros for field expired + * @details counter transitioned from 1 to 0 + * @{ + */ +#define SLW_INTERRUPT_STATUS__EXPIRED__SHIFT 0 +#define SLW_INTERRUPT_STATUS__EXPIRED__WIDTH 1 +#define SLW_INTERRUPT_STATUS__EXPIRED__MASK 0x00000001U +#define SLW_INTERRUPT_STATUS__EXPIRED__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SLW_INTERRUPT_STATUS__EXPIRED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SLW_INTERRUPT_STATUS__EXPIRED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SLW_INTERRUPT_STATUS__EXPIRED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hit_thres0 */ +/** + * @defgroup at_apb_slwtimer_regs_core_hit_thres0_field hit_thres0_field + * @brief macros for field hit_thres0 + * @details threshold 0 interrupt triggered + * @{ + */ +#define SLW_INTERRUPT_STATUS__HIT_THRES0__SHIFT 1 +#define SLW_INTERRUPT_STATUS__HIT_THRES0__WIDTH 1 +#define SLW_INTERRUPT_STATUS__HIT_THRES0__MASK 0x00000002U +#define SLW_INTERRUPT_STATUS__HIT_THRES0__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define SLW_INTERRUPT_STATUS__HIT_THRES0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SLW_INTERRUPT_STATUS__HIT_THRES0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SLW_INTERRUPT_STATUS__HIT_THRES0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hit_thres1 */ +/** + * @defgroup at_apb_slwtimer_regs_core_hit_thres1_field hit_thres1_field + * @brief macros for field hit_thres1 + * @details threshold 1 interrupt triggered + * @{ + */ +#define SLW_INTERRUPT_STATUS__HIT_THRES1__SHIFT 2 +#define SLW_INTERRUPT_STATUS__HIT_THRES1__WIDTH 1 +#define SLW_INTERRUPT_STATUS__HIT_THRES1__MASK 0x00000004U +#define SLW_INTERRUPT_STATUS__HIT_THRES1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define SLW_INTERRUPT_STATUS__HIT_THRES1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define SLW_INTERRUPT_STATUS__HIT_THRES1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define SLW_INTERRUPT_STATUS__HIT_THRES1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hit_thres2 */ +/** + * @defgroup at_apb_slwtimer_regs_core_hit_thres2_field hit_thres2_field + * @brief macros for field hit_thres2 + * @details threshold 2 interrupt triggered + * @{ + */ +#define SLW_INTERRUPT_STATUS__HIT_THRES2__SHIFT 3 +#define SLW_INTERRUPT_STATUS__HIT_THRES2__WIDTH 1 +#define SLW_INTERRUPT_STATUS__HIT_THRES2__MASK 0x00000008U +#define SLW_INTERRUPT_STATUS__HIT_THRES2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define SLW_INTERRUPT_STATUS__HIT_THRES2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define SLW_INTERRUPT_STATUS__HIT_THRES2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define SLW_INTERRUPT_STATUS__HIT_THRES2__RESET_VALUE 0x00000000U +/** @} */ +#define SLW_INTERRUPT_STATUS__TYPE uint32_t +#define SLW_INTERRUPT_STATUS__READ 0x0000000fU +#define SLW_INTERRUPT_STATUS__PRESERVED 0x00000000U +#define SLW_INTERRUPT_STATUS__RESET_VALUE 0x00000000U + +#endif /* __SLW_INTERRUPT_STATUS_MACRO__ */ + +/** @} end of interrupt_status */ + +/* macros for BlueprintGlobalNameSpace::SLW_interrupt_mask */ +/** + * @defgroup at_apb_slwtimer_regs_core_interrupt_mask interrupt_mask + * @brief interrupt mask definitions. + * @{ + */ +#ifndef __SLW_INTERRUPT_MASK_MACRO__ +#define __SLW_INTERRUPT_MASK_MACRO__ + +/* macros for field passthru_expired */ +/** + * @defgroup at_apb_slwtimer_regs_core_passthru_expired_field passthru_expired_field + * @brief macros for field passthru_expired + * @details 1=allow counter expiring to be OR'd into core interrupt + * @{ + */ +#define SLW_INTERRUPT_MASK__PASSTHRU_EXPIRED__SHIFT 0 +#define SLW_INTERRUPT_MASK__PASSTHRU_EXPIRED__WIDTH 1 +#define SLW_INTERRUPT_MASK__PASSTHRU_EXPIRED__MASK 0x00000001U +#define SLW_INTERRUPT_MASK__PASSTHRU_EXPIRED__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SLW_INTERRUPT_MASK__PASSTHRU_EXPIRED__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SLW_INTERRUPT_MASK__PASSTHRU_EXPIRED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SLW_INTERRUPT_MASK__PASSTHRU_EXPIRED__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SLW_INTERRUPT_MASK__PASSTHRU_EXPIRED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SLW_INTERRUPT_MASK__PASSTHRU_EXPIRED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SLW_INTERRUPT_MASK__PASSTHRU_EXPIRED__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field passthru_hit_thres0 */ +/** + * @defgroup at_apb_slwtimer_regs_core_passthru_hit_thres0_field passthru_hit_thres0_field + * @brief macros for field passthru_hit_thres0 + * @details 1=allow hit_thres0 to be OR'd into core interrupt + * @{ + */ +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES0__SHIFT 1 +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES0__WIDTH 1 +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES0__MASK 0x00000002U +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES0__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES0__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES0__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field passthru_hit_thres1 */ +/** + * @defgroup at_apb_slwtimer_regs_core_passthru_hit_thres1_field passthru_hit_thres1_field + * @brief macros for field passthru_hit_thres1 + * @details 1=allow hit_thres1 to be OR'd into core interrupt + * @{ + */ +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES1__SHIFT 2 +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES1__WIDTH 1 +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES1__MASK 0x00000004U +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES1__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES1__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field passthru_hit_thres2 */ +/** + * @defgroup at_apb_slwtimer_regs_core_passthru_hit_thres2_field passthru_hit_thres2_field + * @brief macros for field passthru_hit_thres2 + * @details 1=allow hit_thres2 to be OR'd into core interrupt + * @{ + */ +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES2__SHIFT 3 +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES2__WIDTH 1 +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES2__MASK 0x00000008U +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES2__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define SLW_INTERRUPT_MASK__PASSTHRU_HIT_THRES2__RESET_VALUE 0x00000001U +/** @} */ +#define SLW_INTERRUPT_MASK__TYPE uint32_t +#define SLW_INTERRUPT_MASK__READ 0x0000000fU +#define SLW_INTERRUPT_MASK__WRITE 0x0000000fU +#define SLW_INTERRUPT_MASK__PRESERVED 0x00000000U +#define SLW_INTERRUPT_MASK__RESET_VALUE 0x0000000fU + +#endif /* __SLW_INTERRUPT_MASK_MACRO__ */ + +/** @} end of interrupt_mask */ + +/* macros for BlueprintGlobalNameSpace::SLW_core_id */ +/** + * @defgroup at_apb_slwtimer_regs_core_core_id core_id + * @brief core ID definitions. + * @{ + */ +#ifndef __SLW_CORE_ID_MACRO__ +#define __SLW_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_slwtimer_regs_core_id_field id_field + * @brief macros for field id + * @details 'STMR' in hex + * @{ + */ +#define SLW_CORE_ID__ID__SHIFT 0 +#define SLW_CORE_ID__ID__WIDTH 32 +#define SLW_CORE_ID__ID__MASK 0xffffffffU +#define SLW_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define SLW_CORE_ID__ID__RESET_VALUE 0x53544d52U +/** @} */ +#define SLW_CORE_ID__TYPE uint32_t +#define SLW_CORE_ID__READ 0xffffffffU +#define SLW_CORE_ID__PRESERVED 0x00000000U +#define SLW_CORE_ID__RESET_VALUE 0x53544d52U + +#endif /* __SLW_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of AT_APB_SLWTIMER_REGS_CORE */ +#endif /* __REG_AT_APB_SLWTIMER_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_apb_spi_regs_core_macro.h b/ATM33xx-5/include/reg/at_apb_spi_regs_core_macro.h new file mode 100644 index 0000000..95c3f4c --- /dev/null +++ b/ATM33xx-5/include/reg/at_apb_spi_regs_core_macro.h @@ -0,0 +1,1574 @@ +/* */ +/* File: at_apb_spi_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_apb_spi_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_APB_SPI_REGS_CORE_H__ +#define __REG_AT_APB_SPI_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_APB_SPI_REGS_CORE at_apb_spi_regs_core + * @ingroup AT_REG + * @brief at_apb_spi_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::SPI_ctrl */ +/** + * @defgroup at_apb_spi_regs_core_ctrl ctrl + * @brief SPI Control Register definitions. + * @{ + */ +#ifndef __SPI_CTRL_MACRO__ +#define __SPI_CTRL_MACRO__ + +/* macros for field mstr */ +/** + * @defgroup at_apb_spi_regs_core_mstr_field mstr_field + * @brief macros for field mstr + * @details 1=master interface 0=slave interface + * @{ + */ +#define SPI_CTRL__MSTR__SHIFT 0 +#define SPI_CTRL__MSTR__WIDTH 1 +#define SPI_CTRL__MSTR__MASK 0x00000001U +#define SPI_CTRL__MSTR__READ(src) ((uint32_t)(src) & 0x00000001U) +#define SPI_CTRL__MSTR__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define SPI_CTRL__MSTR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SPI_CTRL__MSTR__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define SPI_CTRL__MSTR__SET(dst) (dst) = ((dst) & ~0x00000001U) | (uint32_t)(1) +#define SPI_CTRL__MSTR__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (uint32_t)(0) +#define SPI_CTRL__MSTR__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field cpha */ +/** + * @defgroup at_apb_spi_regs_core_cpha_field cpha_field + * @brief macros for field cpha + * @details spi clock phase 0=leading edge sample, trailing edge toggle 1=leading edge toggle, trailing edge sample + * @{ + */ +#define SPI_CTRL__CPHA__SHIFT 1 +#define SPI_CTRL__CPHA__WIDTH 1 +#define SPI_CTRL__CPHA__MASK 0x00000002U +#define SPI_CTRL__CPHA__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define SPI_CTRL__CPHA__WRITE(src) (((uint32_t)(src) << 1) & 0x00000002U) +#define SPI_CTRL__CPHA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define SPI_CTRL__CPHA__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define SPI_CTRL__CPHA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SPI_CTRL__CPHA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SPI_CTRL__CPHA__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cpol */ +/** + * @defgroup at_apb_spi_regs_core_cpol_field cpol_field + * @brief macros for field cpol + * @details spi clock polarity 0=spi clock low in idle; cs high 1=spi clock high in idle; cs high + * @{ + */ +#define SPI_CTRL__CPOL__SHIFT 2 +#define SPI_CTRL__CPOL__WIDTH 1 +#define SPI_CTRL__CPOL__MASK 0x00000004U +#define SPI_CTRL__CPOL__READ(src) (((uint32_t)(src) & 0x00000004U) >> 2) +#define SPI_CTRL__CPOL__WRITE(src) (((uint32_t)(src) << 2) & 0x00000004U) +#define SPI_CTRL__CPOL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define SPI_CTRL__CPOL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define SPI_CTRL__CPOL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define SPI_CTRL__CPOL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define SPI_CTRL__CPOL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field s_rd_opcode */ +/** + * @defgroup at_apb_spi_regs_core_s_rd_opcode_field s_rd_opcode_field + * @brief macros for field s_rd_opcode + * @details slave read opcode + * @{ + */ +#define SPI_CTRL__S_RD_OPCODE__SHIFT 3 +#define SPI_CTRL__S_RD_OPCODE__WIDTH 8 +#define SPI_CTRL__S_RD_OPCODE__MASK 0x000007f8U +#define SPI_CTRL__S_RD_OPCODE__READ(src) (((uint32_t)(src) & 0x000007f8U) >> 3) +#define SPI_CTRL__S_RD_OPCODE__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x000007f8U) +#define SPI_CTRL__S_RD_OPCODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007f8U) | (((uint32_t)(src) <<\ + 3) & 0x000007f8U) +#define SPI_CTRL__S_RD_OPCODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x000007f8U))) +#define SPI_CTRL__S_RD_OPCODE__RESET_VALUE 0x00000060U +/** @} */ + +/* macros for field s_wr_opcode */ +/** + * @defgroup at_apb_spi_regs_core_s_wr_opcode_field s_wr_opcode_field + * @brief macros for field s_wr_opcode + * @details slave write opcode + * @{ + */ +#define SPI_CTRL__S_WR_OPCODE__SHIFT 11 +#define SPI_CTRL__S_WR_OPCODE__WIDTH 8 +#define SPI_CTRL__S_WR_OPCODE__MASK 0x0007f800U +#define SPI_CTRL__S_WR_OPCODE__READ(src) \ + (((uint32_t)(src)\ + & 0x0007f800U) >> 11) +#define SPI_CTRL__S_WR_OPCODE__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x0007f800U) +#define SPI_CTRL__S_WR_OPCODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007f800U) | (((uint32_t)(src) <<\ + 11) & 0x0007f800U) +#define SPI_CTRL__S_WR_OPCODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x0007f800U))) +#define SPI_CTRL__S_WR_OPCODE__RESET_VALUE 0x00000020U +/** @} */ + +/* macros for field spi3wire_en */ +/** + * @defgroup at_apb_spi_regs_core_spi3wire_en_field spi3wire_en_field + * @brief macros for field spi3wire_en + * @details 1=enable 3-wire spi transactions, mosi pad becomes bi-directional 0=default 4-wire spi transactions + * @{ + */ +#define SPI_CTRL__SPI3WIRE_EN__SHIFT 19 +#define SPI_CTRL__SPI3WIRE_EN__WIDTH 1 +#define SPI_CTRL__SPI3WIRE_EN__MASK 0x00080000U +#define SPI_CTRL__SPI3WIRE_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define SPI_CTRL__SPI3WIRE_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define SPI_CTRL__SPI3WIRE_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define SPI_CTRL__SPI3WIRE_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define SPI_CTRL__SPI3WIRE_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define SPI_CTRL__SPI3WIRE_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define SPI_CTRL__SPI3WIRE_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dma_mode */ +/** + * @defgroup at_apb_spi_regs_core_dma_mode_field dma_mode_field + * @brief macros for field dma_mode + * @details 1 = dma controls spi core + * @{ + */ +#define SPI_CTRL__DMA_MODE__SHIFT 31 +#define SPI_CTRL__DMA_MODE__WIDTH 1 +#define SPI_CTRL__DMA_MODE__MASK 0x80000000U +#define SPI_CTRL__DMA_MODE__READ(src) (((uint32_t)(src) & 0x80000000U) >> 31) +#define SPI_CTRL__DMA_MODE__WRITE(src) (((uint32_t)(src) << 31) & 0x80000000U) +#define SPI_CTRL__DMA_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define SPI_CTRL__DMA_MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define SPI_CTRL__DMA_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define SPI_CTRL__DMA_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define SPI_CTRL__DMA_MODE__RESET_VALUE 0x00000000U +/** @} */ +#define SPI_CTRL__TYPE uint32_t +#define SPI_CTRL__READ 0x800fffffU +#define SPI_CTRL__WRITE 0x800fffffU +#define SPI_CTRL__PRESERVED 0x00000000U +#define SPI_CTRL__RESET_VALUE 0x00010301U + +#endif /* __SPI_CTRL_MACRO__ */ + +/** @} end of ctrl */ + +/* macros for BlueprintGlobalNameSpace::SPI_transaction_setup */ +/** + * @defgroup at_apb_spi_regs_core_transaction_setup transaction_setup + * @brief transaction setup definitions. + * @{ + */ +#ifndef __SPI_TRANSACTION_SETUP_MACRO__ +#define __SPI_TRANSACTION_SETUP_MACRO__ + +/* macros for field start */ +/** + * @defgroup at_apb_spi_regs_core_start_field start_field + * @brief macros for field start + * @details Master FSM needs to see low to high transition to start; not auto cleared + * @{ + */ +#define SPI_TRANSACTION_SETUP__START__SHIFT 0 +#define SPI_TRANSACTION_SETUP__START__WIDTH 1 +#define SPI_TRANSACTION_SETUP__START__MASK 0x00000001U +#define SPI_TRANSACTION_SETUP__START__READ(src) ((uint32_t)(src) & 0x00000001U) +#define SPI_TRANSACTION_SETUP__START__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SPI_TRANSACTION_SETUP__START__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SPI_TRANSACTION_SETUP__START__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SPI_TRANSACTION_SETUP__START__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SPI_TRANSACTION_SETUP__START__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SPI_TRANSACTION_SETUP__START__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field num_data_bytes */ +/** + * @defgroup at_apb_spi_regs_core_num_data_bytes_field num_data_bytes_field + * @brief macros for field num_data_bytes + * @details Master data; don't add 1 for opcode + * @{ + */ +#define SPI_TRANSACTION_SETUP__NUM_DATA_BYTES__SHIFT 1 +#define SPI_TRANSACTION_SETUP__NUM_DATA_BYTES__WIDTH 4 +#define SPI_TRANSACTION_SETUP__NUM_DATA_BYTES__MASK 0x0000001eU +#define SPI_TRANSACTION_SETUP__NUM_DATA_BYTES__READ(src) \ + (((uint32_t)(src)\ + & 0x0000001eU) >> 1) +#define SPI_TRANSACTION_SETUP__NUM_DATA_BYTES__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x0000001eU) +#define SPI_TRANSACTION_SETUP__NUM_DATA_BYTES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001eU) | (((uint32_t)(src) <<\ + 1) & 0x0000001eU) +#define SPI_TRANSACTION_SETUP__NUM_DATA_BYTES__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x0000001eU))) +#define SPI_TRANSACTION_SETUP__NUM_DATA_BYTES__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rwb */ +/** + * @defgroup at_apb_spi_regs_core_rwb_field rwb_field + * @brief macros for field rwb + * @details 1=read 0=write; note it's possibly redundant with opcode + * @{ + */ +#define SPI_TRANSACTION_SETUP__RWB__SHIFT 5 +#define SPI_TRANSACTION_SETUP__RWB__WIDTH 1 +#define SPI_TRANSACTION_SETUP__RWB__MASK 0x00000020U +#define SPI_TRANSACTION_SETUP__RWB__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define SPI_TRANSACTION_SETUP__RWB__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define SPI_TRANSACTION_SETUP__RWB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define SPI_TRANSACTION_SETUP__RWB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define SPI_TRANSACTION_SETUP__RWB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define SPI_TRANSACTION_SETUP__RWB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define SPI_TRANSACTION_SETUP__RWB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clkdiv */ +/** + * @defgroup at_apb_spi_regs_core_clkdiv_field clkdiv_field + * @brief macros for field clkdiv + * @details freq_sclk = f_pclk/(2*(clkdiv+1)) + * @{ + */ +#define SPI_TRANSACTION_SETUP__CLKDIV__SHIFT 6 +#define SPI_TRANSACTION_SETUP__CLKDIV__WIDTH 10 +#define SPI_TRANSACTION_SETUP__CLKDIV__MASK 0x0000ffc0U +#define SPI_TRANSACTION_SETUP__CLKDIV__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ffc0U) >> 6) +#define SPI_TRANSACTION_SETUP__CLKDIV__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x0000ffc0U) +#define SPI_TRANSACTION_SETUP__CLKDIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffc0U) | (((uint32_t)(src) <<\ + 6) & 0x0000ffc0U) +#define SPI_TRANSACTION_SETUP__CLKDIV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x0000ffc0U))) +#define SPI_TRANSACTION_SETUP__CLKDIV__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field opcode */ +/** + * @defgroup at_apb_spi_regs_core_opcode_field opcode_field + * @brief macros for field opcode + * @details opcode + * @{ + */ +#define SPI_TRANSACTION_SETUP__OPCODE__SHIFT 16 +#define SPI_TRANSACTION_SETUP__OPCODE__WIDTH 8 +#define SPI_TRANSACTION_SETUP__OPCODE__MASK 0x00ff0000U +#define SPI_TRANSACTION_SETUP__OPCODE__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SPI_TRANSACTION_SETUP__OPCODE__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SPI_TRANSACTION_SETUP__OPCODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SPI_TRANSACTION_SETUP__OPCODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SPI_TRANSACTION_SETUP__OPCODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field loopback */ +/** + * @defgroup at_apb_spi_regs_core_loopback_field loopback_field + * @brief macros for field loopback + * @details if 1, mosi is internally connected to miso + * @{ + */ +#define SPI_TRANSACTION_SETUP__LOOPBACK__SHIFT 24 +#define SPI_TRANSACTION_SETUP__LOOPBACK__WIDTH 1 +#define SPI_TRANSACTION_SETUP__LOOPBACK__MASK 0x01000000U +#define SPI_TRANSACTION_SETUP__LOOPBACK__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SPI_TRANSACTION_SETUP__LOOPBACK__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SPI_TRANSACTION_SETUP__LOOPBACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SPI_TRANSACTION_SETUP__LOOPBACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SPI_TRANSACTION_SETUP__LOOPBACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SPI_TRANSACTION_SETUP__LOOPBACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SPI_TRANSACTION_SETUP__LOOPBACK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field csn_stays_low */ +/** + * @defgroup at_apb_spi_regs_core_csn_stays_low_field csn_stays_low_field + * @brief macros for field csn_stays_low + * @details at end of transaction, leave csn low + * @{ + */ +#define SPI_TRANSACTION_SETUP__CSN_STAYS_LOW__SHIFT 25 +#define SPI_TRANSACTION_SETUP__CSN_STAYS_LOW__WIDTH 1 +#define SPI_TRANSACTION_SETUP__CSN_STAYS_LOW__MASK 0x02000000U +#define SPI_TRANSACTION_SETUP__CSN_STAYS_LOW__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define SPI_TRANSACTION_SETUP__CSN_STAYS_LOW__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define SPI_TRANSACTION_SETUP__CSN_STAYS_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define SPI_TRANSACTION_SETUP__CSN_STAYS_LOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define SPI_TRANSACTION_SETUP__CSN_STAYS_LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define SPI_TRANSACTION_SETUP__CSN_STAYS_LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define SPI_TRANSACTION_SETUP__CSN_STAYS_LOW__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dummy_cycles */ +/** + * @defgroup at_apb_spi_regs_core_dummy_cycles_field dummy_cycles_field + * @brief macros for field dummy_cycles + * @details number of extra shift cycles to help with turn-around + * @{ + */ +#define SPI_TRANSACTION_SETUP__DUMMY_CYCLES__SHIFT 26 +#define SPI_TRANSACTION_SETUP__DUMMY_CYCLES__WIDTH 4 +#define SPI_TRANSACTION_SETUP__DUMMY_CYCLES__MASK 0x3c000000U +#define SPI_TRANSACTION_SETUP__DUMMY_CYCLES__READ(src) \ + (((uint32_t)(src)\ + & 0x3c000000U) >> 26) +#define SPI_TRANSACTION_SETUP__DUMMY_CYCLES__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x3c000000U) +#define SPI_TRANSACTION_SETUP__DUMMY_CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3c000000U) | (((uint32_t)(src) <<\ + 26) & 0x3c000000U) +#define SPI_TRANSACTION_SETUP__DUMMY_CYCLES__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x3c000000U))) +#define SPI_TRANSACTION_SETUP__DUMMY_CYCLES__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field invert_mosi */ +/** + * @defgroup at_apb_spi_regs_core_invert_mosi_field invert_mosi_field + * @brief macros for field invert_mosi + * @details invert mosi; keep static during entire spi transaction + * @{ + */ +#define SPI_TRANSACTION_SETUP__INVERT_MOSI__SHIFT 30 +#define SPI_TRANSACTION_SETUP__INVERT_MOSI__WIDTH 1 +#define SPI_TRANSACTION_SETUP__INVERT_MOSI__MASK 0x40000000U +#define SPI_TRANSACTION_SETUP__INVERT_MOSI__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define SPI_TRANSACTION_SETUP__INVERT_MOSI__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define SPI_TRANSACTION_SETUP__INVERT_MOSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define SPI_TRANSACTION_SETUP__INVERT_MOSI__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define SPI_TRANSACTION_SETUP__INVERT_MOSI__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define SPI_TRANSACTION_SETUP__INVERT_MOSI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define SPI_TRANSACTION_SETUP__INVERT_MOSI__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field csn_bubble */ +/** + * @defgroup at_apb_spi_regs_core_csn_bubble_field csn_bubble_field + * @brief macros for field csn_bubble + * @details introduce a delay between spi_csn falling and first bit on mosi + * @{ + */ +#define SPI_TRANSACTION_SETUP__CSN_BUBBLE__SHIFT 31 +#define SPI_TRANSACTION_SETUP__CSN_BUBBLE__WIDTH 1 +#define SPI_TRANSACTION_SETUP__CSN_BUBBLE__MASK 0x80000000U +#define SPI_TRANSACTION_SETUP__CSN_BUBBLE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define SPI_TRANSACTION_SETUP__CSN_BUBBLE__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define SPI_TRANSACTION_SETUP__CSN_BUBBLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define SPI_TRANSACTION_SETUP__CSN_BUBBLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define SPI_TRANSACTION_SETUP__CSN_BUBBLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define SPI_TRANSACTION_SETUP__CSN_BUBBLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define SPI_TRANSACTION_SETUP__CSN_BUBBLE__RESET_VALUE 0x00000000U +/** @} */ +#define SPI_TRANSACTION_SETUP__TYPE uint32_t +#define SPI_TRANSACTION_SETUP__READ 0xffffffffU +#define SPI_TRANSACTION_SETUP__WRITE 0xffffffffU +#define SPI_TRANSACTION_SETUP__PRESERVED 0x00000000U +#define SPI_TRANSACTION_SETUP__RESET_VALUE 0x00000000U + +#endif /* __SPI_TRANSACTION_SETUP_MACRO__ */ + +/** @} end of transaction_setup */ + +/* macros for BlueprintGlobalNameSpace::SPI_transaction_setup_dma */ +/** + * @defgroup at_apb_spi_regs_core_transaction_setup_dma transaction_setup_dma + * @brief transaction setup by DMA definitions. + * @{ + */ +#ifndef __SPI_TRANSACTION_SETUP_DMA_MACRO__ +#define __SPI_TRANSACTION_SETUP_DMA_MACRO__ + +/* macros for field start */ +/** + * @defgroup at_apb_spi_regs_core_start_field start_field + * @brief macros for field start + * @details Master FSM needs to see low to high transition to start; auto cleared + * @{ + */ +#define SPI_TRANSACTION_SETUP_DMA__START__SHIFT 0 +#define SPI_TRANSACTION_SETUP_DMA__START__WIDTH 1 +#define SPI_TRANSACTION_SETUP_DMA__START__MASK 0x00000001U +#define SPI_TRANSACTION_SETUP_DMA__START__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SPI_TRANSACTION_SETUP_DMA__START__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SPI_TRANSACTION_SETUP_DMA__START__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SPI_TRANSACTION_SETUP_DMA__START__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SPI_TRANSACTION_SETUP_DMA__START__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SPI_TRANSACTION_SETUP_DMA__START__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SPI_TRANSACTION_SETUP_DMA__START__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field num_data_bytes */ +/** + * @defgroup at_apb_spi_regs_core_num_data_bytes_field num_data_bytes_field + * @brief macros for field num_data_bytes + * @details Master data; don't add 1 for opcode + * @{ + */ +#define SPI_TRANSACTION_SETUP_DMA__NUM_DATA_BYTES__SHIFT 1 +#define SPI_TRANSACTION_SETUP_DMA__NUM_DATA_BYTES__WIDTH 4 +#define SPI_TRANSACTION_SETUP_DMA__NUM_DATA_BYTES__MASK 0x0000001eU +#define SPI_TRANSACTION_SETUP_DMA__NUM_DATA_BYTES__READ(src) \ + (((uint32_t)(src)\ + & 0x0000001eU) >> 1) +#define SPI_TRANSACTION_SETUP_DMA__NUM_DATA_BYTES__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x0000001eU) +#define SPI_TRANSACTION_SETUP_DMA__NUM_DATA_BYTES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001eU) | (((uint32_t)(src) <<\ + 1) & 0x0000001eU) +#define SPI_TRANSACTION_SETUP_DMA__NUM_DATA_BYTES__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x0000001eU))) +#define SPI_TRANSACTION_SETUP_DMA__NUM_DATA_BYTES__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rwb */ +/** + * @defgroup at_apb_spi_regs_core_rwb_field rwb_field + * @brief macros for field rwb + * @details 1=read 0=write; note it's possibly redundant with opcode + * @{ + */ +#define SPI_TRANSACTION_SETUP_DMA__RWB__SHIFT 5 +#define SPI_TRANSACTION_SETUP_DMA__RWB__WIDTH 1 +#define SPI_TRANSACTION_SETUP_DMA__RWB__MASK 0x00000020U +#define SPI_TRANSACTION_SETUP_DMA__RWB__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define SPI_TRANSACTION_SETUP_DMA__RWB__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define SPI_TRANSACTION_SETUP_DMA__RWB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define SPI_TRANSACTION_SETUP_DMA__RWB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define SPI_TRANSACTION_SETUP_DMA__RWB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define SPI_TRANSACTION_SETUP_DMA__RWB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define SPI_TRANSACTION_SETUP_DMA__RWB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field csn_stays_low */ +/** + * @defgroup at_apb_spi_regs_core_csn_stays_low_field csn_stays_low_field + * @brief macros for field csn_stays_low + * @details at end of transaction, leave csn low + * @{ + */ +#define SPI_TRANSACTION_SETUP_DMA__CSN_STAYS_LOW__SHIFT 25 +#define SPI_TRANSACTION_SETUP_DMA__CSN_STAYS_LOW__WIDTH 1 +#define SPI_TRANSACTION_SETUP_DMA__CSN_STAYS_LOW__MASK 0x02000000U +#define SPI_TRANSACTION_SETUP_DMA__CSN_STAYS_LOW__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define SPI_TRANSACTION_SETUP_DMA__CSN_STAYS_LOW__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define SPI_TRANSACTION_SETUP_DMA__CSN_STAYS_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define SPI_TRANSACTION_SETUP_DMA__CSN_STAYS_LOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define SPI_TRANSACTION_SETUP_DMA__CSN_STAYS_LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define SPI_TRANSACTION_SETUP_DMA__CSN_STAYS_LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define SPI_TRANSACTION_SETUP_DMA__CSN_STAYS_LOW__RESET_VALUE 0x00000000U +/** @} */ +#define SPI_TRANSACTION_SETUP_DMA__TYPE uint32_t +#define SPI_TRANSACTION_SETUP_DMA__READ 0x0200003fU +#define SPI_TRANSACTION_SETUP_DMA__WRITE 0x0200003fU +#define SPI_TRANSACTION_SETUP_DMA__PRESERVED 0x00000000U +#define SPI_TRANSACTION_SETUP_DMA__RESET_VALUE 0x00000000U + +#endif /* __SPI_TRANSACTION_SETUP_DMA_MACRO__ */ + +/** @} end of transaction_setup_dma */ + +/* macros for BlueprintGlobalNameSpace::SPI_transaction_status */ +/** + * @defgroup at_apb_spi_regs_core_transaction_status transaction_status + * @brief transaction status definitions. + * @{ + */ +#ifndef __SPI_TRANSACTION_STATUS_MACRO__ +#define __SPI_TRANSACTION_STATUS_MACRO__ + +/* macros for field done */ +/** + * @defgroup at_apb_spi_regs_core_done_field done_field + * @brief macros for field done + * @details 1=indicate master or slave read/write transaction is done + * @{ + */ +#define SPI_TRANSACTION_STATUS__DONE__SHIFT 0 +#define SPI_TRANSACTION_STATUS__DONE__WIDTH 1 +#define SPI_TRANSACTION_STATUS__DONE__MASK 0x00000001U +#define SPI_TRANSACTION_STATUS__DONE__READ(src) ((uint32_t)(src) & 0x00000001U) +#define SPI_TRANSACTION_STATUS__DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SPI_TRANSACTION_STATUS__DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SPI_TRANSACTION_STATUS__DONE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field running */ +/** + * @defgroup at_apb_spi_regs_core_running_field running_field + * @brief macros for field running + * @details 1=indicate master or slave running based on which interface selected by 'mstr' bit + * @{ + */ +#define SPI_TRANSACTION_STATUS__RUNNING__SHIFT 1 +#define SPI_TRANSACTION_STATUS__RUNNING__WIDTH 1 +#define SPI_TRANSACTION_STATUS__RUNNING__MASK 0x00000002U +#define SPI_TRANSACTION_STATUS__RUNNING__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define SPI_TRANSACTION_STATUS__RUNNING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SPI_TRANSACTION_STATUS__RUNNING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SPI_TRANSACTION_STATUS__RUNNING__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field opcode_status */ +/** + * @defgroup at_apb_spi_regs_core_opcode_status_field opcode_status_field + * @brief macros for field opcode_status + * @details master or slave opcode status + * @{ + */ +#define SPI_TRANSACTION_STATUS__OPCODE_STATUS__SHIFT 8 +#define SPI_TRANSACTION_STATUS__OPCODE_STATUS__WIDTH 8 +#define SPI_TRANSACTION_STATUS__OPCODE_STATUS__MASK 0x0000ff00U +#define SPI_TRANSACTION_STATUS__OPCODE_STATUS__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SPI_TRANSACTION_STATUS__OPCODE_STATUS__RESET_VALUE 0x00000000U +/** @} */ +#define SPI_TRANSACTION_STATUS__TYPE uint32_t +#define SPI_TRANSACTION_STATUS__READ 0x0000ff03U +#define SPI_TRANSACTION_STATUS__PRESERVED 0x00000000U +#define SPI_TRANSACTION_STATUS__RESET_VALUE 0x00000000U + +#endif /* __SPI_TRANSACTION_STATUS_MACRO__ */ + +/** @} end of transaction_status */ + +/* macros for BlueprintGlobalNameSpace::SPI_data_bytes_lower */ +/** + * @defgroup at_apb_spi_regs_core_data_bytes_lower data_bytes_lower + * @brief master: preload if write; postread if read; readback data will change if num_data_bytes changes post done slave: stores read/write address definitions. + * @{ + */ +#ifndef __SPI_DATA_BYTES_LOWER_MACRO__ +#define __SPI_DATA_BYTES_LOWER_MACRO__ + +/* macros for field byte0 */ +/** + * @defgroup at_apb_spi_regs_core_byte0_field byte0_field + * @brief macros for field byte0 + * @details data byte0 + * @{ + */ +#define SPI_DATA_BYTES_LOWER__BYTE0__SHIFT 0 +#define SPI_DATA_BYTES_LOWER__BYTE0__WIDTH 8 +#define SPI_DATA_BYTES_LOWER__BYTE0__MASK 0x000000ffU +#define SPI_DATA_BYTES_LOWER__BYTE0__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define SPI_DATA_BYTES_LOWER__BYTE0__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define SPI_DATA_BYTES_LOWER__BYTE0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SPI_DATA_BYTES_LOWER__BYTE0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SPI_DATA_BYTES_LOWER__BYTE0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte1 */ +/** + * @defgroup at_apb_spi_regs_core_byte1_field byte1_field + * @brief macros for field byte1 + * @details data byte1 + * @{ + */ +#define SPI_DATA_BYTES_LOWER__BYTE1__SHIFT 8 +#define SPI_DATA_BYTES_LOWER__BYTE1__WIDTH 8 +#define SPI_DATA_BYTES_LOWER__BYTE1__MASK 0x0000ff00U +#define SPI_DATA_BYTES_LOWER__BYTE1__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SPI_DATA_BYTES_LOWER__BYTE1__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SPI_DATA_BYTES_LOWER__BYTE1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SPI_DATA_BYTES_LOWER__BYTE1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SPI_DATA_BYTES_LOWER__BYTE1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte2 */ +/** + * @defgroup at_apb_spi_regs_core_byte2_field byte2_field + * @brief macros for field byte2 + * @details data byte2 + * @{ + */ +#define SPI_DATA_BYTES_LOWER__BYTE2__SHIFT 16 +#define SPI_DATA_BYTES_LOWER__BYTE2__WIDTH 8 +#define SPI_DATA_BYTES_LOWER__BYTE2__MASK 0x00ff0000U +#define SPI_DATA_BYTES_LOWER__BYTE2__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SPI_DATA_BYTES_LOWER__BYTE2__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SPI_DATA_BYTES_LOWER__BYTE2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SPI_DATA_BYTES_LOWER__BYTE2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SPI_DATA_BYTES_LOWER__BYTE2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte3 */ +/** + * @defgroup at_apb_spi_regs_core_byte3_field byte3_field + * @brief macros for field byte3 + * @details data byte3 + * @{ + */ +#define SPI_DATA_BYTES_LOWER__BYTE3__SHIFT 24 +#define SPI_DATA_BYTES_LOWER__BYTE3__WIDTH 8 +#define SPI_DATA_BYTES_LOWER__BYTE3__MASK 0xff000000U +#define SPI_DATA_BYTES_LOWER__BYTE3__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SPI_DATA_BYTES_LOWER__BYTE3__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SPI_DATA_BYTES_LOWER__BYTE3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SPI_DATA_BYTES_LOWER__BYTE3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SPI_DATA_BYTES_LOWER__BYTE3__RESET_VALUE 0x00000000U +/** @} */ +#define SPI_DATA_BYTES_LOWER__TYPE uint32_t +#define SPI_DATA_BYTES_LOWER__READ 0xffffffffU +#define SPI_DATA_BYTES_LOWER__WRITE 0xffffffffU +#define SPI_DATA_BYTES_LOWER__PRESERVED 0x00000000U +#define SPI_DATA_BYTES_LOWER__RESET_VALUE 0x00000000U + +#endif /* __SPI_DATA_BYTES_LOWER_MACRO__ */ + +/** @} end of data_bytes_lower */ + +/* macros for BlueprintGlobalNameSpace::SPI_data_bytes_upper */ +/** + * @defgroup at_apb_spi_regs_core_data_bytes_upper data_bytes_upper + * @brief master: preload if write; postread if read; readback data will change if num_data_bytes changes post done slave: stores write data; preload read data definitions. + * @{ + */ +#ifndef __SPI_DATA_BYTES_UPPER_MACRO__ +#define __SPI_DATA_BYTES_UPPER_MACRO__ + +/* macros for field byte4 */ +/** + * @defgroup at_apb_spi_regs_core_byte4_field byte4_field + * @brief macros for field byte4 + * @details data byte4 + * @{ + */ +#define SPI_DATA_BYTES_UPPER__BYTE4__SHIFT 0 +#define SPI_DATA_BYTES_UPPER__BYTE4__WIDTH 8 +#define SPI_DATA_BYTES_UPPER__BYTE4__MASK 0x000000ffU +#define SPI_DATA_BYTES_UPPER__BYTE4__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define SPI_DATA_BYTES_UPPER__BYTE4__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define SPI_DATA_BYTES_UPPER__BYTE4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SPI_DATA_BYTES_UPPER__BYTE4__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SPI_DATA_BYTES_UPPER__BYTE4__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte5 */ +/** + * @defgroup at_apb_spi_regs_core_byte5_field byte5_field + * @brief macros for field byte5 + * @details data byte5 + * @{ + */ +#define SPI_DATA_BYTES_UPPER__BYTE5__SHIFT 8 +#define SPI_DATA_BYTES_UPPER__BYTE5__WIDTH 8 +#define SPI_DATA_BYTES_UPPER__BYTE5__MASK 0x0000ff00U +#define SPI_DATA_BYTES_UPPER__BYTE5__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SPI_DATA_BYTES_UPPER__BYTE5__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SPI_DATA_BYTES_UPPER__BYTE5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SPI_DATA_BYTES_UPPER__BYTE5__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SPI_DATA_BYTES_UPPER__BYTE5__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte6 */ +/** + * @defgroup at_apb_spi_regs_core_byte6_field byte6_field + * @brief macros for field byte6 + * @details data byte6 + * @{ + */ +#define SPI_DATA_BYTES_UPPER__BYTE6__SHIFT 16 +#define SPI_DATA_BYTES_UPPER__BYTE6__WIDTH 8 +#define SPI_DATA_BYTES_UPPER__BYTE6__MASK 0x00ff0000U +#define SPI_DATA_BYTES_UPPER__BYTE6__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SPI_DATA_BYTES_UPPER__BYTE6__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define SPI_DATA_BYTES_UPPER__BYTE6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define SPI_DATA_BYTES_UPPER__BYTE6__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define SPI_DATA_BYTES_UPPER__BYTE6__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byte7 */ +/** + * @defgroup at_apb_spi_regs_core_byte7_field byte7_field + * @brief macros for field byte7 + * @details data byte7 + * @{ + */ +#define SPI_DATA_BYTES_UPPER__BYTE7__SHIFT 24 +#define SPI_DATA_BYTES_UPPER__BYTE7__WIDTH 8 +#define SPI_DATA_BYTES_UPPER__BYTE7__MASK 0xff000000U +#define SPI_DATA_BYTES_UPPER__BYTE7__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define SPI_DATA_BYTES_UPPER__BYTE7__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define SPI_DATA_BYTES_UPPER__BYTE7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define SPI_DATA_BYTES_UPPER__BYTE7__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define SPI_DATA_BYTES_UPPER__BYTE7__RESET_VALUE 0x00000000U +/** @} */ +#define SPI_DATA_BYTES_UPPER__TYPE uint32_t +#define SPI_DATA_BYTES_UPPER__READ 0xffffffffU +#define SPI_DATA_BYTES_UPPER__WRITE 0xffffffffU +#define SPI_DATA_BYTES_UPPER__PRESERVED 0x00000000U +#define SPI_DATA_BYTES_UPPER__RESET_VALUE 0x00000000U + +#endif /* __SPI_DATA_BYTES_UPPER_MACRO__ */ + +/** @} end of data_bytes_upper */ + +/* macros for BlueprintGlobalNameSpace::SPI_interrupt_mask */ +/** + * @defgroup at_apb_spi_regs_core_interrupt_mask interrupt_mask + * @brief interrupt mask definitions. + * @{ + */ +#ifndef __SPI_INTERRUPT_MASK_MACRO__ +#define __SPI_INTERRUPT_MASK_MACRO__ + +/* macros for field passthru0 */ +/** + * @defgroup at_apb_spi_regs_core_passthru0_field passthru0_field + * @brief macros for field passthru0 + * @details 1=allow interrupt0 to be OR'ed into core interrupt + * @{ + */ +#define SPI_INTERRUPT_MASK__PASSTHRU0__SHIFT 0 +#define SPI_INTERRUPT_MASK__PASSTHRU0__WIDTH 1 +#define SPI_INTERRUPT_MASK__PASSTHRU0__MASK 0x00000001U +#define SPI_INTERRUPT_MASK__PASSTHRU0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SPI_INTERRUPT_MASK__PASSTHRU0__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SPI_INTERRUPT_MASK__PASSTHRU0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SPI_INTERRUPT_MASK__PASSTHRU0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SPI_INTERRUPT_MASK__PASSTHRU0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SPI_INTERRUPT_MASK__PASSTHRU0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SPI_INTERRUPT_MASK__PASSTHRU0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field passthru1 */ +/** + * @defgroup at_apb_spi_regs_core_passthru1_field passthru1_field + * @brief macros for field passthru1 + * @details 1=allow interrupt1 to be OR'ed into core interrupt + * @{ + */ +#define SPI_INTERRUPT_MASK__PASSTHRU1__SHIFT 1 +#define SPI_INTERRUPT_MASK__PASSTHRU1__WIDTH 1 +#define SPI_INTERRUPT_MASK__PASSTHRU1__MASK 0x00000002U +#define SPI_INTERRUPT_MASK__PASSTHRU1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define SPI_INTERRUPT_MASK__PASSTHRU1__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define SPI_INTERRUPT_MASK__PASSTHRU1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define SPI_INTERRUPT_MASK__PASSTHRU1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define SPI_INTERRUPT_MASK__PASSTHRU1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SPI_INTERRUPT_MASK__PASSTHRU1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SPI_INTERRUPT_MASK__PASSTHRU1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field passthru2 */ +/** + * @defgroup at_apb_spi_regs_core_passthru2_field passthru2_field + * @brief macros for field passthru2 + * @details 1=allow interrupt2 to be OR'ed into core interrupt + * @{ + */ +#define SPI_INTERRUPT_MASK__PASSTHRU2__SHIFT 2 +#define SPI_INTERRUPT_MASK__PASSTHRU2__WIDTH 1 +#define SPI_INTERRUPT_MASK__PASSTHRU2__MASK 0x00000004U +#define SPI_INTERRUPT_MASK__PASSTHRU2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define SPI_INTERRUPT_MASK__PASSTHRU2__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define SPI_INTERRUPT_MASK__PASSTHRU2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define SPI_INTERRUPT_MASK__PASSTHRU2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define SPI_INTERRUPT_MASK__PASSTHRU2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define SPI_INTERRUPT_MASK__PASSTHRU2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define SPI_INTERRUPT_MASK__PASSTHRU2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field passthru3 */ +/** + * @defgroup at_apb_spi_regs_core_passthru3_field passthru3_field + * @brief macros for field passthru3 + * @details 1=allow interrupt3 to be OR'ed into core interrupt + * @{ + */ +#define SPI_INTERRUPT_MASK__PASSTHRU3__SHIFT 3 +#define SPI_INTERRUPT_MASK__PASSTHRU3__WIDTH 1 +#define SPI_INTERRUPT_MASK__PASSTHRU3__MASK 0x00000008U +#define SPI_INTERRUPT_MASK__PASSTHRU3__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define SPI_INTERRUPT_MASK__PASSTHRU3__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define SPI_INTERRUPT_MASK__PASSTHRU3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define SPI_INTERRUPT_MASK__PASSTHRU3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define SPI_INTERRUPT_MASK__PASSTHRU3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define SPI_INTERRUPT_MASK__PASSTHRU3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define SPI_INTERRUPT_MASK__PASSTHRU3__RESET_VALUE 0x00000000U +/** @} */ +#define SPI_INTERRUPT_MASK__TYPE uint32_t +#define SPI_INTERRUPT_MASK__READ 0x0000000fU +#define SPI_INTERRUPT_MASK__WRITE 0x0000000fU +#define SPI_INTERRUPT_MASK__PRESERVED 0x00000000U +#define SPI_INTERRUPT_MASK__RESET_VALUE 0x00000000U + +#endif /* __SPI_INTERRUPT_MASK_MACRO__ */ + +/** @} end of interrupt_mask */ + +/* macros for BlueprintGlobalNameSpace::SPI_interrupt_status */ +/** + * @defgroup at_apb_spi_regs_core_interrupt_status interrupt_status + * @brief interrupt status definitions. + * @{ + */ +#ifndef __SPI_INTERRUPT_STATUS_MACRO__ +#define __SPI_INTERRUPT_STATUS_MACRO__ + +/* macros for field interrupt0 */ +/** + * @defgroup at_apb_spi_regs_core_interrupt0_field interrupt0_field + * @brief macros for field interrupt0 + * @details from master, transaction done; independent of mask + * @{ + */ +#define SPI_INTERRUPT_STATUS__INTERRUPT0__SHIFT 0 +#define SPI_INTERRUPT_STATUS__INTERRUPT0__WIDTH 1 +#define SPI_INTERRUPT_STATUS__INTERRUPT0__MASK 0x00000001U +#define SPI_INTERRUPT_STATUS__INTERRUPT0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SPI_INTERRUPT_STATUS__INTERRUPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SPI_INTERRUPT_STATUS__INTERRUPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SPI_INTERRUPT_STATUS__INTERRUPT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field interrupt1 */ +/** + * @defgroup at_apb_spi_regs_core_interrupt1_field interrupt1_field + * @brief macros for field interrupt1 + * @details from slave, transaction done capture; independent of mask + * @{ + */ +#define SPI_INTERRUPT_STATUS__INTERRUPT1__SHIFT 1 +#define SPI_INTERRUPT_STATUS__INTERRUPT1__WIDTH 1 +#define SPI_INTERRUPT_STATUS__INTERRUPT1__MASK 0x00000002U +#define SPI_INTERRUPT_STATUS__INTERRUPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define SPI_INTERRUPT_STATUS__INTERRUPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SPI_INTERRUPT_STATUS__INTERRUPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SPI_INTERRUPT_STATUS__INTERRUPT1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field interrupt2 */ +/** + * @defgroup at_apb_spi_regs_core_interrupt2_field interrupt2_field + * @brief macros for field interrupt2 + * @details from slave, error unknown command; independent of mask + * @{ + */ +#define SPI_INTERRUPT_STATUS__INTERRUPT2__SHIFT 2 +#define SPI_INTERRUPT_STATUS__INTERRUPT2__WIDTH 1 +#define SPI_INTERRUPT_STATUS__INTERRUPT2__MASK 0x00000004U +#define SPI_INTERRUPT_STATUS__INTERRUPT2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define SPI_INTERRUPT_STATUS__INTERRUPT2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define SPI_INTERRUPT_STATUS__INTERRUPT2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define SPI_INTERRUPT_STATUS__INTERRUPT2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field interrupt3 */ +/** + * @defgroup at_apb_spi_regs_core_interrupt3_field interrupt3_field + * @brief macros for field interrupt3 + * @details from slave, error read-data invalid; independent of mask + * @{ + */ +#define SPI_INTERRUPT_STATUS__INTERRUPT3__SHIFT 3 +#define SPI_INTERRUPT_STATUS__INTERRUPT3__WIDTH 1 +#define SPI_INTERRUPT_STATUS__INTERRUPT3__MASK 0x00000008U +#define SPI_INTERRUPT_STATUS__INTERRUPT3__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define SPI_INTERRUPT_STATUS__INTERRUPT3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define SPI_INTERRUPT_STATUS__INTERRUPT3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define SPI_INTERRUPT_STATUS__INTERRUPT3__RESET_VALUE 0x00000000U +/** @} */ +#define SPI_INTERRUPT_STATUS__TYPE uint32_t +#define SPI_INTERRUPT_STATUS__READ 0x0000000fU +#define SPI_INTERRUPT_STATUS__PRESERVED 0x00000000U +#define SPI_INTERRUPT_STATUS__RESET_VALUE 0x00000000U + +#endif /* __SPI_INTERRUPT_STATUS_MACRO__ */ + +/** @} end of interrupt_status */ + +/* macros for BlueprintGlobalNameSpace::SPI_set_interrupt */ +/** + * @defgroup at_apb_spi_regs_core_set_interrupt set_interrupt + * @brief interrupt set definitions. + * @{ + */ +#ifndef __SPI_SET_INTERRUPT_MACRO__ +#define __SPI_SET_INTERRUPT_MACRO__ + +/* macros for field set_interrupt0 */ +/** + * @defgroup at_apb_spi_regs_core_set_interrupt0_field set_interrupt0_field + * @brief macros for field set_interrupt0 + * @details set interrupt0; not auto cleared + * @{ + */ +#define SPI_SET_INTERRUPT__SET_INTERRUPT0__SHIFT 0 +#define SPI_SET_INTERRUPT__SET_INTERRUPT0__WIDTH 1 +#define SPI_SET_INTERRUPT__SET_INTERRUPT0__MASK 0x00000001U +#define SPI_SET_INTERRUPT__SET_INTERRUPT0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SPI_SET_INTERRUPT__SET_INTERRUPT0__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SPI_SET_INTERRUPT__SET_INTERRUPT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SPI_SET_INTERRUPT__SET_INTERRUPT0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SPI_SET_INTERRUPT__SET_INTERRUPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SPI_SET_INTERRUPT__SET_INTERRUPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SPI_SET_INTERRUPT__SET_INTERRUPT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field set_interrupt1 */ +/** + * @defgroup at_apb_spi_regs_core_set_interrupt1_field set_interrupt1_field + * @brief macros for field set_interrupt1 + * @details set interrupt1; not auto cleared + * @{ + */ +#define SPI_SET_INTERRUPT__SET_INTERRUPT1__SHIFT 1 +#define SPI_SET_INTERRUPT__SET_INTERRUPT1__WIDTH 1 +#define SPI_SET_INTERRUPT__SET_INTERRUPT1__MASK 0x00000002U +#define SPI_SET_INTERRUPT__SET_INTERRUPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define SPI_SET_INTERRUPT__SET_INTERRUPT1__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define SPI_SET_INTERRUPT__SET_INTERRUPT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define SPI_SET_INTERRUPT__SET_INTERRUPT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define SPI_SET_INTERRUPT__SET_INTERRUPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SPI_SET_INTERRUPT__SET_INTERRUPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SPI_SET_INTERRUPT__SET_INTERRUPT1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field set_interrupt2 */ +/** + * @defgroup at_apb_spi_regs_core_set_interrupt2_field set_interrupt2_field + * @brief macros for field set_interrupt2 + * @details set interrupt2; not auto cleared + * @{ + */ +#define SPI_SET_INTERRUPT__SET_INTERRUPT2__SHIFT 2 +#define SPI_SET_INTERRUPT__SET_INTERRUPT2__WIDTH 1 +#define SPI_SET_INTERRUPT__SET_INTERRUPT2__MASK 0x00000004U +#define SPI_SET_INTERRUPT__SET_INTERRUPT2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define SPI_SET_INTERRUPT__SET_INTERRUPT2__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define SPI_SET_INTERRUPT__SET_INTERRUPT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define SPI_SET_INTERRUPT__SET_INTERRUPT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define SPI_SET_INTERRUPT__SET_INTERRUPT2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define SPI_SET_INTERRUPT__SET_INTERRUPT2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define SPI_SET_INTERRUPT__SET_INTERRUPT2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field set_interrupt3 */ +/** + * @defgroup at_apb_spi_regs_core_set_interrupt3_field set_interrupt3_field + * @brief macros for field set_interrupt3 + * @details set interrupt3; not auto cleared + * @{ + */ +#define SPI_SET_INTERRUPT__SET_INTERRUPT3__SHIFT 3 +#define SPI_SET_INTERRUPT__SET_INTERRUPT3__WIDTH 1 +#define SPI_SET_INTERRUPT__SET_INTERRUPT3__MASK 0x00000008U +#define SPI_SET_INTERRUPT__SET_INTERRUPT3__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define SPI_SET_INTERRUPT__SET_INTERRUPT3__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define SPI_SET_INTERRUPT__SET_INTERRUPT3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define SPI_SET_INTERRUPT__SET_INTERRUPT3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define SPI_SET_INTERRUPT__SET_INTERRUPT3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define SPI_SET_INTERRUPT__SET_INTERRUPT3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define SPI_SET_INTERRUPT__SET_INTERRUPT3__RESET_VALUE 0x00000000U +/** @} */ +#define SPI_SET_INTERRUPT__TYPE uint32_t +#define SPI_SET_INTERRUPT__READ 0x0000000fU +#define SPI_SET_INTERRUPT__WRITE 0x0000000fU +#define SPI_SET_INTERRUPT__PRESERVED 0x00000000U +#define SPI_SET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __SPI_SET_INTERRUPT_MACRO__ */ + +/** @} end of set_interrupt */ + +/* macros for BlueprintGlobalNameSpace::SPI_reset_interrupt */ +/** + * @defgroup at_apb_spi_regs_core_reset_interrupt reset_interrupt + * @brief interrupt clear definitions. + * @{ + */ +#ifndef __SPI_RESET_INTERRUPT_MACRO__ +#define __SPI_RESET_INTERRUPT_MACRO__ + +/* macros for field reset_interrupt0 */ +/** + * @defgroup at_apb_spi_regs_core_reset_interrupt0_field reset_interrupt0_field + * @brief macros for field reset_interrupt0 + * @details clear interrupt0; not auto cleared + * @{ + */ +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT0__SHIFT 0 +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT0__WIDTH 1 +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT0__MASK 0x00000001U +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT0__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reset_interrupt1 */ +/** + * @defgroup at_apb_spi_regs_core_reset_interrupt1_field reset_interrupt1_field + * @brief macros for field reset_interrupt1 + * @details clear interrupt1; not auto cleared + * @{ + */ +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT1__SHIFT 1 +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT1__WIDTH 1 +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT1__MASK 0x00000002U +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT1__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reset_interrupt2 */ +/** + * @defgroup at_apb_spi_regs_core_reset_interrupt2_field reset_interrupt2_field + * @brief macros for field reset_interrupt2 + * @details clear interrupt2; not auto cleared + * @{ + */ +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT2__SHIFT 2 +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT2__WIDTH 1 +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT2__MASK 0x00000004U +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT2__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reset_interrupt3 */ +/** + * @defgroup at_apb_spi_regs_core_reset_interrupt3_field reset_interrupt3_field + * @brief macros for field reset_interrupt3 + * @details clear interrupt3; not auto cleared + * @{ + */ +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT3__SHIFT 3 +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT3__WIDTH 1 +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT3__MASK 0x00000008U +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT3__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT3__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define SPI_RESET_INTERRUPT__RESET_INTERRUPT3__RESET_VALUE 0x00000000U +/** @} */ +#define SPI_RESET_INTERRUPT__TYPE uint32_t +#define SPI_RESET_INTERRUPT__READ 0x0000000fU +#define SPI_RESET_INTERRUPT__WRITE 0x0000000fU +#define SPI_RESET_INTERRUPT__PRESERVED 0x00000000U +#define SPI_RESET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __SPI_RESET_INTERRUPT_MACRO__ */ + +/** @} end of reset_interrupt */ + +/* macros for BlueprintGlobalNameSpace::SPI_core_id */ +/** + * @defgroup at_apb_spi_regs_core_core_id core_id + * @brief core ID definitions. + * @{ + */ +#ifndef __SPI_CORE_ID_MACRO__ +#define __SPI_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_spi_regs_core_id_field id_field + * @brief macros for field id + * @details SPI in ASCII + * @{ + */ +#define SPI_CORE_ID__ID__SHIFT 0 +#define SPI_CORE_ID__ID__WIDTH 32 +#define SPI_CORE_ID__ID__MASK 0xffffffffU +#define SPI_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define SPI_CORE_ID__ID__RESET_VALUE 0x53504920U +/** @} */ +#define SPI_CORE_ID__TYPE uint32_t +#define SPI_CORE_ID__READ 0xffffffffU +#define SPI_CORE_ID__PRESERVED 0x00000000U +#define SPI_CORE_ID__RESET_VALUE 0x53504920U + +#endif /* __SPI_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of AT_APB_SPI_REGS_CORE */ +#endif /* __REG_AT_APB_SPI_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_apb_swd_regs_core_macro.h b/ATM33xx-5/include/reg/at_apb_swd_regs_core_macro.h new file mode 100644 index 0000000..a2f4653 --- /dev/null +++ b/ATM33xx-5/include/reg/at_apb_swd_regs_core_macro.h @@ -0,0 +1,1238 @@ +/* */ +/* File: at_apb_swd_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_apb_swd_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_APB_SWD_REGS_CORE_H__ +#define __REG_AT_APB_SWD_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_APB_SWD_REGS_CORE at_apb_swd_regs_core + * @ingroup AT_REG + * @brief at_apb_swd_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::SWD_dap_addr_ctrl */ +/** + * @defgroup at_apb_swd_regs_core_dap_addr_ctrl dap_addr_ctrl + * @brief Contains register fields associated with dap_addr_ctrl. definitions. + * @{ + */ +#ifndef __SWD_DAP_ADDR_CTRL_MACRO__ +#define __SWD_DAP_ADDR_CTRL_MACRO__ + +/* macros for field dap_addr */ +/** + * @defgroup at_apb_swd_regs_core_dap_addr_field dap_addr_field + * @brief macros for field dap_addr + * @{ + */ +#define SWD_DAP_ADDR_CTRL__DAP_ADDR__SHIFT 0 +#define SWD_DAP_ADDR_CTRL__DAP_ADDR__WIDTH 2 +#define SWD_DAP_ADDR_CTRL__DAP_ADDR__MASK 0x00000003U +#define SWD_DAP_ADDR_CTRL__DAP_ADDR__READ(src) ((uint32_t)(src) & 0x00000003U) +#define SWD_DAP_ADDR_CTRL__DAP_ADDR__WRITE(src) ((uint32_t)(src) & 0x00000003U) +#define SWD_DAP_ADDR_CTRL__DAP_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define SWD_DAP_ADDR_CTRL__DAP_ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define SWD_DAP_ADDR_CTRL__DAP_ADDR__RESET_VALUE 0x00000000U +/** @} */ +#define SWD_DAP_ADDR_CTRL__TYPE uint32_t +#define SWD_DAP_ADDR_CTRL__READ 0x00000003U +#define SWD_DAP_ADDR_CTRL__WRITE 0x00000003U +#define SWD_DAP_ADDR_CTRL__PRESERVED 0x00000000U +#define SWD_DAP_ADDR_CTRL__RESET_VALUE 0x00000000U + +#endif /* __SWD_DAP_ADDR_CTRL_MACRO__ */ + +/** @} end of dap_addr_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SWD_dap_wdata_ctrl */ +/** + * @defgroup at_apb_swd_regs_core_dap_wdata_ctrl dap_wdata_ctrl + * @brief Contains register fields associated with dap_wdata_ctrl. definitions. + * @{ + */ +#ifndef __SWD_DAP_WDATA_CTRL_MACRO__ +#define __SWD_DAP_WDATA_CTRL_MACRO__ + +/* macros for field dap_wdata */ +/** + * @defgroup at_apb_swd_regs_core_dap_wdata_field dap_wdata_field + * @brief macros for field dap_wdata + * @{ + */ +#define SWD_DAP_WDATA_CTRL__DAP_WDATA__SHIFT 0 +#define SWD_DAP_WDATA_CTRL__DAP_WDATA__WIDTH 32 +#define SWD_DAP_WDATA_CTRL__DAP_WDATA__MASK 0xffffffffU +#define SWD_DAP_WDATA_CTRL__DAP_WDATA__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define SWD_DAP_WDATA_CTRL__DAP_WDATA__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define SWD_DAP_WDATA_CTRL__DAP_WDATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define SWD_DAP_WDATA_CTRL__DAP_WDATA__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define SWD_DAP_WDATA_CTRL__DAP_WDATA__RESET_VALUE 0x00000000U +/** @} */ +#define SWD_DAP_WDATA_CTRL__TYPE uint32_t +#define SWD_DAP_WDATA_CTRL__READ 0xffffffffU +#define SWD_DAP_WDATA_CTRL__WRITE 0xffffffffU +#define SWD_DAP_WDATA_CTRL__PRESERVED 0x00000000U +#define SWD_DAP_WDATA_CTRL__RESET_VALUE 0x00000000U + +#endif /* __SWD_DAP_WDATA_CTRL_MACRO__ */ + +/** @} end of dap_wdata_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SWD_swd_clk_div_ctrl */ +/** + * @defgroup at_apb_swd_regs_core_swd_clk_div_ctrl swd_clk_div_ctrl + * @brief Contains register fields associated with swd_clk_div_ctrl. definitions. + * @{ + */ +#ifndef __SWD_SWD_CLK_DIV_CTRL_MACRO__ +#define __SWD_SWD_CLK_DIV_CTRL_MACRO__ + +/* macros for field swd_clk_div */ +/** + * @defgroup at_apb_swd_regs_core_swd_clk_div_field swd_clk_div_field + * @brief macros for field swd_clk_div + * @details clock divider = 2^(swd_clk_div) + * @{ + */ +#define SWD_SWD_CLK_DIV_CTRL__SWD_CLK_DIV__SHIFT 0 +#define SWD_SWD_CLK_DIV_CTRL__SWD_CLK_DIV__WIDTH 3 +#define SWD_SWD_CLK_DIV_CTRL__SWD_CLK_DIV__MASK 0x00000007U +#define SWD_SWD_CLK_DIV_CTRL__SWD_CLK_DIV__READ(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define SWD_SWD_CLK_DIV_CTRL__SWD_CLK_DIV__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define SWD_SWD_CLK_DIV_CTRL__SWD_CLK_DIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define SWD_SWD_CLK_DIV_CTRL__SWD_CLK_DIV__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define SWD_SWD_CLK_DIV_CTRL__SWD_CLK_DIV__RESET_VALUE 0x00000003U +/** @} */ +#define SWD_SWD_CLK_DIV_CTRL__TYPE uint32_t +#define SWD_SWD_CLK_DIV_CTRL__READ 0x00000007U +#define SWD_SWD_CLK_DIV_CTRL__WRITE 0x00000007U +#define SWD_SWD_CLK_DIV_CTRL__PRESERVED 0x00000000U +#define SWD_SWD_CLK_DIV_CTRL__RESET_VALUE 0x00000003U + +#endif /* __SWD_SWD_CLK_DIV_CTRL_MACRO__ */ + +/** @} end of swd_clk_div_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SWD_pattern_upper_ctrl */ +/** + * @defgroup at_apb_swd_regs_core_pattern_upper_ctrl pattern_upper_ctrl + * @brief Contains register fields associated with pattern_upper_ctrl. definitions. + * @{ + */ +#ifndef __SWD_PATTERN_UPPER_CTRL_MACRO__ +#define __SWD_PATTERN_UPPER_CTRL_MACRO__ + +/* macros for field pattern */ +/** + * @defgroup at_apb_swd_regs_core_pattern_field pattern_field + * @brief macros for field pattern + * @details pattern to switch from jtag to swd , lsb is shifted out first + * @{ + */ +#define SWD_PATTERN_UPPER_CTRL__PATTERN__SHIFT 0 +#define SWD_PATTERN_UPPER_CTRL__PATTERN__WIDTH 32 +#define SWD_PATTERN_UPPER_CTRL__PATTERN__MASK 0xffffffffU +#define SWD_PATTERN_UPPER_CTRL__PATTERN__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define SWD_PATTERN_UPPER_CTRL__PATTERN__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define SWD_PATTERN_UPPER_CTRL__PATTERN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define SWD_PATTERN_UPPER_CTRL__PATTERN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define SWD_PATTERN_UPPER_CTRL__PATTERN__RESET_VALUE 0xffffffffU +/** @} */ +#define SWD_PATTERN_UPPER_CTRL__TYPE uint32_t +#define SWD_PATTERN_UPPER_CTRL__READ 0xffffffffU +#define SWD_PATTERN_UPPER_CTRL__WRITE 0xffffffffU +#define SWD_PATTERN_UPPER_CTRL__PRESERVED 0x00000000U +#define SWD_PATTERN_UPPER_CTRL__RESET_VALUE 0xffffffffU + +#endif /* __SWD_PATTERN_UPPER_CTRL_MACRO__ */ + +/** @} end of pattern_upper_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SWD_pattern_lower_ctrl */ +/** + * @defgroup at_apb_swd_regs_core_pattern_lower_ctrl pattern_lower_ctrl + * @brief Contains register fields associated with pattern_lower_ctrl. definitions. + * @{ + */ +#ifndef __SWD_PATTERN_LOWER_CTRL_MACRO__ +#define __SWD_PATTERN_LOWER_CTRL_MACRO__ + +/* macros for field pattern */ +/** + * @defgroup at_apb_swd_regs_core_pattern_field pattern_field + * @brief macros for field pattern + * @details pattern to switch from jtag to swd , lsb is shifted out first + * @{ + */ +#define SWD_PATTERN_LOWER_CTRL__PATTERN__SHIFT 0 +#define SWD_PATTERN_LOWER_CTRL__PATTERN__WIDTH 32 +#define SWD_PATTERN_LOWER_CTRL__PATTERN__MASK 0xffffffffU +#define SWD_PATTERN_LOWER_CTRL__PATTERN__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define SWD_PATTERN_LOWER_CTRL__PATTERN__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define SWD_PATTERN_LOWER_CTRL__PATTERN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define SWD_PATTERN_LOWER_CTRL__PATTERN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define SWD_PATTERN_LOWER_CTRL__PATTERN__RESET_VALUE 0xffffffffU +/** @} */ +#define SWD_PATTERN_LOWER_CTRL__TYPE uint32_t +#define SWD_PATTERN_LOWER_CTRL__READ 0xffffffffU +#define SWD_PATTERN_LOWER_CTRL__WRITE 0xffffffffU +#define SWD_PATTERN_LOWER_CTRL__PRESERVED 0x00000000U +#define SWD_PATTERN_LOWER_CTRL__RESET_VALUE 0xffffffffU + +#endif /* __SWD_PATTERN_LOWER_CTRL_MACRO__ */ + +/** @} end of pattern_lower_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SWD_tail_dur */ +/** + * @defgroup at_apb_swd_regs_core_tail_dur tail_dur + * @brief Contains register fields associated with tail_dur. definitions. + * @{ + */ +#ifndef __SWD_TAIL_DUR_MACRO__ +#define __SWD_TAIL_DUR_MACRO__ + +/* macros for field count */ +/** + * @defgroup at_apb_swd_regs_core_count_field count_field + * @brief macros for field count + * @details exact number of extra cycles after a packet. 0 means no tail. must be at least 5 cycles after a DAP packet + * @{ + */ +#define SWD_TAIL_DUR__COUNT__SHIFT 0 +#define SWD_TAIL_DUR__COUNT__WIDTH 4 +#define SWD_TAIL_DUR__COUNT__MASK 0x0000000fU +#define SWD_TAIL_DUR__COUNT__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define SWD_TAIL_DUR__COUNT__WRITE(src) ((uint32_t)(src) & 0x0000000fU) +#define SWD_TAIL_DUR__COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define SWD_TAIL_DUR__COUNT__VERIFY(src) (!(((uint32_t)(src) & ~0x0000000fU))) +#define SWD_TAIL_DUR__COUNT__RESET_VALUE 0x00000005U +/** @} */ +#define SWD_TAIL_DUR__TYPE uint32_t +#define SWD_TAIL_DUR__READ 0x0000000fU +#define SWD_TAIL_DUR__WRITE 0x0000000fU +#define SWD_TAIL_DUR__PRESERVED 0x00000000U +#define SWD_TAIL_DUR__RESET_VALUE 0x00000005U + +#endif /* __SWD_TAIL_DUR_MACRO__ */ + +/** @} end of tail_dur */ + +/* macros for BlueprintGlobalNameSpace::SWD_pattern_dur */ +/** + * @defgroup at_apb_swd_regs_core_pattern_dur pattern_dur + * @brief Contains register fields associated with pattern_dur. definitions. + * @{ + */ +#ifndef __SWD_PATTERN_DUR_MACRO__ +#define __SWD_PATTERN_DUR_MACRO__ + +/* macros for field count */ +/** + * @defgroup at_apb_swd_regs_core_count_field count_field + * @brief macros for field count + * @details number cycles to drive the pattern MSB first is count + 1. e.g. 64 cycles by default + * @{ + */ +#define SWD_PATTERN_DUR__COUNT__SHIFT 0 +#define SWD_PATTERN_DUR__COUNT__WIDTH 8 +#define SWD_PATTERN_DUR__COUNT__MASK 0x000000ffU +#define SWD_PATTERN_DUR__COUNT__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define SWD_PATTERN_DUR__COUNT__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define SWD_PATTERN_DUR__COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SWD_PATTERN_DUR__COUNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SWD_PATTERN_DUR__COUNT__RESET_VALUE 0x0000003fU +/** @} */ +#define SWD_PATTERN_DUR__TYPE uint32_t +#define SWD_PATTERN_DUR__READ 0x000000ffU +#define SWD_PATTERN_DUR__WRITE 0x000000ffU +#define SWD_PATTERN_DUR__PRESERVED 0x00000000U +#define SWD_PATTERN_DUR__RESET_VALUE 0x0000003fU + +#endif /* __SWD_PATTERN_DUR_MACRO__ */ + +/** @} end of pattern_dur */ + +/* macros for BlueprintGlobalNameSpace::SWD_dap_bridge_status */ +/** + * @defgroup at_apb_swd_regs_core_dap_bridge_status dap_bridge_status + * @brief Contains register fields associated with dap_bridge_status. definitions. + * @{ + */ +#ifndef __SWD_DAP_BRIDGE_STATUS_MACRO__ +#define __SWD_DAP_BRIDGE_STATUS_MACRO__ + +/* macros for field busy */ +/** + * @defgroup at_apb_swd_regs_core_busy_field busy_field + * @brief macros for field busy + * @{ + */ +#define SWD_DAP_BRIDGE_STATUS__BUSY__SHIFT 0 +#define SWD_DAP_BRIDGE_STATUS__BUSY__WIDTH 1 +#define SWD_DAP_BRIDGE_STATUS__BUSY__MASK 0x00000001U +#define SWD_DAP_BRIDGE_STATUS__BUSY__READ(src) ((uint32_t)(src) & 0x00000001U) +#define SWD_DAP_BRIDGE_STATUS__BUSY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SWD_DAP_BRIDGE_STATUS__BUSY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SWD_DAP_BRIDGE_STATUS__BUSY__RESET_VALUE 0x00000000U +/** @} */ +#define SWD_DAP_BRIDGE_STATUS__TYPE uint32_t +#define SWD_DAP_BRIDGE_STATUS__READ 0x00000001U +#define SWD_DAP_BRIDGE_STATUS__PRESERVED 0x00000000U +#define SWD_DAP_BRIDGE_STATUS__RESET_VALUE 0x00000000U + +#endif /* __SWD_DAP_BRIDGE_STATUS_MACRO__ */ + +/** @} end of dap_bridge_status */ + +/* macros for BlueprintGlobalNameSpace::SWD_dap_resp_status */ +/** + * @defgroup at_apb_swd_regs_core_dap_resp_status dap_resp_status + * @brief Contains register fields associated with dap_resp_status. definitions. + * @{ + */ +#ifndef __SWD_DAP_RESP_STATUS_MACRO__ +#define __SWD_DAP_RESP_STATUS_MACRO__ + +/* macros for field dap_resp */ +/** + * @defgroup at_apb_swd_regs_core_dap_resp_field dap_resp_field + * @brief macros for field dap_resp + * @{ + */ +#define SWD_DAP_RESP_STATUS__DAP_RESP__SHIFT 0 +#define SWD_DAP_RESP_STATUS__DAP_RESP__WIDTH 3 +#define SWD_DAP_RESP_STATUS__DAP_RESP__MASK 0x00000007U +#define SWD_DAP_RESP_STATUS__DAP_RESP__READ(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define SWD_DAP_RESP_STATUS__DAP_RESP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field par_err */ +/** + * @defgroup at_apb_swd_regs_core_par_err_field par_err_field + * @brief macros for field par_err + * @details 1= RDATA has parity error, 0= otherwise + * @{ + */ +#define SWD_DAP_RESP_STATUS__PAR_ERR__SHIFT 3 +#define SWD_DAP_RESP_STATUS__PAR_ERR__WIDTH 1 +#define SWD_DAP_RESP_STATUS__PAR_ERR__MASK 0x00000008U +#define SWD_DAP_RESP_STATUS__PAR_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define SWD_DAP_RESP_STATUS__PAR_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define SWD_DAP_RESP_STATUS__PAR_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define SWD_DAP_RESP_STATUS__PAR_ERR__RESET_VALUE 0x00000000U +/** @} */ +#define SWD_DAP_RESP_STATUS__TYPE uint32_t +#define SWD_DAP_RESP_STATUS__READ 0x0000000fU +#define SWD_DAP_RESP_STATUS__PRESERVED 0x00000000U +#define SWD_DAP_RESP_STATUS__RESET_VALUE 0x00000000U + +#endif /* __SWD_DAP_RESP_STATUS_MACRO__ */ + +/** @} end of dap_resp_status */ + +/* macros for BlueprintGlobalNameSpace::SWD_RW_ctrl */ +/** + * @defgroup at_apb_swd_regs_core_RW_ctrl RW_ctrl + * @brief Contains register fields associated with RW_ctrl. definitions. + * @{ + */ +#ifndef __SWD_RW_CTRL_MACRO__ +#define __SWD_RW_CTRL_MACRO__ + +/* macros for field RnW */ +/** + * @defgroup at_apb_swd_regs_core_RnW_field RnW_field + * @brief macros for field RnW + * @details 1 for Read, 0 for Write + * @{ + */ +#define SWD_RW_CTRL__RNW__SHIFT 0 +#define SWD_RW_CTRL__RNW__WIDTH 1 +#define SWD_RW_CTRL__RNW__MASK 0x00000001U +#define SWD_RW_CTRL__RNW__READ(src) ((uint32_t)(src) & 0x00000001U) +#define SWD_RW_CTRL__RNW__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define SWD_RW_CTRL__RNW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SWD_RW_CTRL__RNW__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define SWD_RW_CTRL__RNW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SWD_RW_CTRL__RNW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SWD_RW_CTRL__RNW__RESET_VALUE 0x00000000U +/** @} */ +#define SWD_RW_CTRL__TYPE uint32_t +#define SWD_RW_CTRL__READ 0x00000001U +#define SWD_RW_CTRL__WRITE 0x00000001U +#define SWD_RW_CTRL__PRESERVED 0x00000000U +#define SWD_RW_CTRL__RESET_VALUE 0x00000000U + +#endif /* __SWD_RW_CTRL_MACRO__ */ + +/** @} end of RW_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SWD_apndp_ctrl */ +/** + * @defgroup at_apb_swd_regs_core_apndp_ctrl apndp_ctrl + * @brief Contains register fields associated with apndp_ctrl. definitions. + * @{ + */ +#ifndef __SWD_APNDP_CTRL_MACRO__ +#define __SWD_APNDP_CTRL_MACRO__ + +/* macros for field APnDP */ +/** + * @defgroup at_apb_swd_regs_core_APnDP_field APnDP_field + * @brief macros for field APnDP + * @details 0 for DPACC, 1 for APACC + * @{ + */ +#define SWD_APNDP_CTRL__APNDP__SHIFT 0 +#define SWD_APNDP_CTRL__APNDP__WIDTH 1 +#define SWD_APNDP_CTRL__APNDP__MASK 0x00000001U +#define SWD_APNDP_CTRL__APNDP__READ(src) ((uint32_t)(src) & 0x00000001U) +#define SWD_APNDP_CTRL__APNDP__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define SWD_APNDP_CTRL__APNDP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SWD_APNDP_CTRL__APNDP__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SWD_APNDP_CTRL__APNDP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SWD_APNDP_CTRL__APNDP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SWD_APNDP_CTRL__APNDP__RESET_VALUE 0x00000000U +/** @} */ +#define SWD_APNDP_CTRL__TYPE uint32_t +#define SWD_APNDP_CTRL__READ 0x00000001U +#define SWD_APNDP_CTRL__WRITE 0x00000001U +#define SWD_APNDP_CTRL__PRESERVED 0x00000000U +#define SWD_APNDP_CTRL__RESET_VALUE 0x00000000U + +#endif /* __SWD_APNDP_CTRL_MACRO__ */ + +/** @} end of apndp_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SWD_trigger_ctrl */ +/** + * @defgroup at_apb_swd_regs_core_trigger_ctrl trigger_ctrl + * @brief Contains register fields associated with trigger_ctrl. definitions. + * @{ + */ +#ifndef __SWD_TRIGGER_CTRL_MACRO__ +#define __SWD_TRIGGER_CTRL_MACRO__ + +/* macros for field go_packet */ +/** + * @defgroup at_apb_swd_regs_core_go_packet_field go_packet_field + * @brief macros for field go_packet + * @details 1 to start a dap packet , not self-resetting. This trigger does not start a DAP reset. See go_pattern to for DAP reset. + * @{ + */ +#define SWD_TRIGGER_CTRL__GO_PACKET__SHIFT 0 +#define SWD_TRIGGER_CTRL__GO_PACKET__WIDTH 1 +#define SWD_TRIGGER_CTRL__GO_PACKET__MASK 0x00000001U +#define SWD_TRIGGER_CTRL__GO_PACKET__READ(src) ((uint32_t)(src) & 0x00000001U) +#define SWD_TRIGGER_CTRL__GO_PACKET__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define SWD_TRIGGER_CTRL__GO_PACKET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SWD_TRIGGER_CTRL__GO_PACKET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SWD_TRIGGER_CTRL__GO_PACKET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SWD_TRIGGER_CTRL__GO_PACKET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SWD_TRIGGER_CTRL__GO_PACKET__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field go_pattern */ +/** + * @defgroup at_apb_swd_regs_core_go_pattern_field go_pattern_field + * @brief macros for field go_pattern + * @details 1 to start resetting by sending a pattern of bits as prescribed by pattern_upper_ctrl and pattern_lower_ctrl. The length of the pattern is set by pattern_dur. not self-resetting. The reset pattern is to bring the target DAP to an inital state. + * @{ + */ +#define SWD_TRIGGER_CTRL__GO_PATTERN__SHIFT 2 +#define SWD_TRIGGER_CTRL__GO_PATTERN__WIDTH 1 +#define SWD_TRIGGER_CTRL__GO_PATTERN__MASK 0x00000004U +#define SWD_TRIGGER_CTRL__GO_PATTERN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define SWD_TRIGGER_CTRL__GO_PATTERN__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define SWD_TRIGGER_CTRL__GO_PATTERN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define SWD_TRIGGER_CTRL__GO_PATTERN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define SWD_TRIGGER_CTRL__GO_PATTERN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define SWD_TRIGGER_CTRL__GO_PATTERN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define SWD_TRIGGER_CTRL__GO_PATTERN__RESET_VALUE 0x00000000U +/** @} */ +#define SWD_TRIGGER_CTRL__TYPE uint32_t +#define SWD_TRIGGER_CTRL__READ 0x00000005U +#define SWD_TRIGGER_CTRL__WRITE 0x00000005U +#define SWD_TRIGGER_CTRL__PRESERVED 0x00000000U +#define SWD_TRIGGER_CTRL__RESET_VALUE 0x00000000U + +#endif /* __SWD_TRIGGER_CTRL_MACRO__ */ + +/** @} end of trigger_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SWD_dap_rdata */ +/** + * @defgroup at_apb_swd_regs_core_dap_rdata dap_rdata + * @brief Contains register fields associated with dap_rdata. definitions. + * @{ + */ +#ifndef __SWD_DAP_RDATA_MACRO__ +#define __SWD_DAP_RDATA_MACRO__ + +/* macros for field dap_rdata */ +/** + * @defgroup at_apb_swd_regs_core_dap_rdata_field dap_rdata_field + * @brief macros for field dap_rdata + * @{ + */ +#define SWD_DAP_RDATA__DAP_RDATA__SHIFT 0 +#define SWD_DAP_RDATA__DAP_RDATA__WIDTH 32 +#define SWD_DAP_RDATA__DAP_RDATA__MASK 0xffffffffU +#define SWD_DAP_RDATA__DAP_RDATA__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define SWD_DAP_RDATA__DAP_RDATA__RESET_VALUE 0x00000000U +/** @} */ +#define SWD_DAP_RDATA__TYPE uint32_t +#define SWD_DAP_RDATA__READ 0xffffffffU +#define SWD_DAP_RDATA__PRESERVED 0x00000000U +#define SWD_DAP_RDATA__RESET_VALUE 0x00000000U + +#endif /* __SWD_DAP_RDATA_MACRO__ */ + +/** @} end of dap_rdata */ + +/* macros for BlueprintGlobalNameSpace::SWD_interrupt_mask */ +/** + * @defgroup at_apb_swd_regs_core_interrupt_mask interrupt_mask + * @brief Contains register fields associated with interrupt_mask. definitions. + * @{ + */ +#ifndef __SWD_INTERRUPT_MASK_MACRO__ +#define __SWD_INTERRUPT_MASK_MACRO__ + +/* macros for field passthru0 */ +/** + * @defgroup at_apb_swd_regs_core_passthru0_field passthru0_field + * @brief macros for field passthru0 + * @details 1=allow interrupt0 (read done) to be OR'ed into core interrupt + * @{ + */ +#define SWD_INTERRUPT_MASK__PASSTHRU0__SHIFT 0 +#define SWD_INTERRUPT_MASK__PASSTHRU0__WIDTH 1 +#define SWD_INTERRUPT_MASK__PASSTHRU0__MASK 0x00000001U +#define SWD_INTERRUPT_MASK__PASSTHRU0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWD_INTERRUPT_MASK__PASSTHRU0__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWD_INTERRUPT_MASK__PASSTHRU0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SWD_INTERRUPT_MASK__PASSTHRU0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SWD_INTERRUPT_MASK__PASSTHRU0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SWD_INTERRUPT_MASK__PASSTHRU0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SWD_INTERRUPT_MASK__PASSTHRU0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field passthru1 */ +/** + * @defgroup at_apb_swd_regs_core_passthru1_field passthru1_field + * @brief macros for field passthru1 + * @details 1=allow interrupt1 (par err on readback data) to be OR'ed into core interrupt + * @{ + */ +#define SWD_INTERRUPT_MASK__PASSTHRU1__SHIFT 1 +#define SWD_INTERRUPT_MASK__PASSTHRU1__WIDTH 1 +#define SWD_INTERRUPT_MASK__PASSTHRU1__MASK 0x00000002U +#define SWD_INTERRUPT_MASK__PASSTHRU1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define SWD_INTERRUPT_MASK__PASSTHRU1__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define SWD_INTERRUPT_MASK__PASSTHRU1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define SWD_INTERRUPT_MASK__PASSTHRU1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define SWD_INTERRUPT_MASK__PASSTHRU1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SWD_INTERRUPT_MASK__PASSTHRU1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SWD_INTERRUPT_MASK__PASSTHRU1__RESET_VALUE 0x00000000U +/** @} */ +#define SWD_INTERRUPT_MASK__TYPE uint32_t +#define SWD_INTERRUPT_MASK__READ 0x00000003U +#define SWD_INTERRUPT_MASK__WRITE 0x00000003U +#define SWD_INTERRUPT_MASK__PRESERVED 0x00000000U +#define SWD_INTERRUPT_MASK__RESET_VALUE 0x00000000U + +#endif /* __SWD_INTERRUPT_MASK_MACRO__ */ + +/** @} end of interrupt_mask */ + +/* macros for BlueprintGlobalNameSpace::SWD_interrupt_status */ +/** + * @defgroup at_apb_swd_regs_core_interrupt_status interrupt_status + * @brief Contains register fields associated with interrupt_status. definitions. + * @{ + */ +#ifndef __SWD_INTERRUPT_STATUS_MACRO__ +#define __SWD_INTERRUPT_STATUS_MACRO__ + +/* macros for field interrupt0 */ +/** + * @defgroup at_apb_swd_regs_core_interrupt0_field interrupt0_field + * @brief macros for field interrupt0 + * @details saw a rising edge on done; independent of mask + * @{ + */ +#define SWD_INTERRUPT_STATUS__INTERRUPT0__SHIFT 0 +#define SWD_INTERRUPT_STATUS__INTERRUPT0__WIDTH 1 +#define SWD_INTERRUPT_STATUS__INTERRUPT0__MASK 0x00000001U +#define SWD_INTERRUPT_STATUS__INTERRUPT0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWD_INTERRUPT_STATUS__INTERRUPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SWD_INTERRUPT_STATUS__INTERRUPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SWD_INTERRUPT_STATUS__INTERRUPT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field interrupt1 */ +/** + * @defgroup at_apb_swd_regs_core_interrupt1_field interrupt1_field + * @brief macros for field interrupt1 + * @details saw a rising edge on par_err; independent of mask + * @{ + */ +#define SWD_INTERRUPT_STATUS__INTERRUPT1__SHIFT 1 +#define SWD_INTERRUPT_STATUS__INTERRUPT1__WIDTH 1 +#define SWD_INTERRUPT_STATUS__INTERRUPT1__MASK 0x00000002U +#define SWD_INTERRUPT_STATUS__INTERRUPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define SWD_INTERRUPT_STATUS__INTERRUPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SWD_INTERRUPT_STATUS__INTERRUPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SWD_INTERRUPT_STATUS__INTERRUPT1__RESET_VALUE 0x00000000U +/** @} */ +#define SWD_INTERRUPT_STATUS__TYPE uint32_t +#define SWD_INTERRUPT_STATUS__READ 0x00000003U +#define SWD_INTERRUPT_STATUS__PRESERVED 0x00000000U +#define SWD_INTERRUPT_STATUS__RESET_VALUE 0x00000000U + +#endif /* __SWD_INTERRUPT_STATUS_MACRO__ */ + +/** @} end of interrupt_status */ + +/* macros for BlueprintGlobalNameSpace::SWD_set_interrupt */ +/** + * @defgroup at_apb_swd_regs_core_set_interrupt set_interrupt + * @brief not auto cleared definitions. + * @{ + */ +#ifndef __SWD_SET_INTERRUPT_MACRO__ +#define __SWD_SET_INTERRUPT_MACRO__ + +/* macros for field set_interrupt0 */ +/** + * @defgroup at_apb_swd_regs_core_set_interrupt0_field set_interrupt0_field + * @brief macros for field set_interrupt0 + * @details set interrupt 0 + * @{ + */ +#define SWD_SET_INTERRUPT__SET_INTERRUPT0__SHIFT 0 +#define SWD_SET_INTERRUPT__SET_INTERRUPT0__WIDTH 1 +#define SWD_SET_INTERRUPT__SET_INTERRUPT0__MASK 0x00000001U +#define SWD_SET_INTERRUPT__SET_INTERRUPT0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWD_SET_INTERRUPT__SET_INTERRUPT0__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWD_SET_INTERRUPT__SET_INTERRUPT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SWD_SET_INTERRUPT__SET_INTERRUPT0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SWD_SET_INTERRUPT__SET_INTERRUPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SWD_SET_INTERRUPT__SET_INTERRUPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SWD_SET_INTERRUPT__SET_INTERRUPT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field set_interrupt1 */ +/** + * @defgroup at_apb_swd_regs_core_set_interrupt1_field set_interrupt1_field + * @brief macros for field set_interrupt1 + * @details set interrupt 1 + * @{ + */ +#define SWD_SET_INTERRUPT__SET_INTERRUPT1__SHIFT 1 +#define SWD_SET_INTERRUPT__SET_INTERRUPT1__WIDTH 1 +#define SWD_SET_INTERRUPT__SET_INTERRUPT1__MASK 0x00000002U +#define SWD_SET_INTERRUPT__SET_INTERRUPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define SWD_SET_INTERRUPT__SET_INTERRUPT1__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define SWD_SET_INTERRUPT__SET_INTERRUPT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define SWD_SET_INTERRUPT__SET_INTERRUPT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define SWD_SET_INTERRUPT__SET_INTERRUPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SWD_SET_INTERRUPT__SET_INTERRUPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SWD_SET_INTERRUPT__SET_INTERRUPT1__RESET_VALUE 0x00000000U +/** @} */ +#define SWD_SET_INTERRUPT__TYPE uint32_t +#define SWD_SET_INTERRUPT__READ 0x00000003U +#define SWD_SET_INTERRUPT__WRITE 0x00000003U +#define SWD_SET_INTERRUPT__PRESERVED 0x00000000U +#define SWD_SET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __SWD_SET_INTERRUPT_MACRO__ */ + +/** @} end of set_interrupt */ + +/* macros for BlueprintGlobalNameSpace::SWD_reset_interrupt */ +/** + * @defgroup at_apb_swd_regs_core_reset_interrupt reset_interrupt + * @brief not auto cleared definitions. + * @{ + */ +#ifndef __SWD_RESET_INTERRUPT_MACRO__ +#define __SWD_RESET_INTERRUPT_MACRO__ + +/* macros for field reset_interrupt0 */ +/** + * @defgroup at_apb_swd_regs_core_reset_interrupt0_field reset_interrupt0_field + * @brief macros for field reset_interrupt0 + * @details reset interrupt 0 + * @{ + */ +#define SWD_RESET_INTERRUPT__RESET_INTERRUPT0__SHIFT 0 +#define SWD_RESET_INTERRUPT__RESET_INTERRUPT0__WIDTH 1 +#define SWD_RESET_INTERRUPT__RESET_INTERRUPT0__MASK 0x00000001U +#define SWD_RESET_INTERRUPT__RESET_INTERRUPT0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWD_RESET_INTERRUPT__RESET_INTERRUPT0__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWD_RESET_INTERRUPT__RESET_INTERRUPT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SWD_RESET_INTERRUPT__RESET_INTERRUPT0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SWD_RESET_INTERRUPT__RESET_INTERRUPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SWD_RESET_INTERRUPT__RESET_INTERRUPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SWD_RESET_INTERRUPT__RESET_INTERRUPT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reset_interrupt1 */ +/** + * @defgroup at_apb_swd_regs_core_reset_interrupt1_field reset_interrupt1_field + * @brief macros for field reset_interrupt1 + * @details reset interrupt 1 + * @{ + */ +#define SWD_RESET_INTERRUPT__RESET_INTERRUPT1__SHIFT 1 +#define SWD_RESET_INTERRUPT__RESET_INTERRUPT1__WIDTH 1 +#define SWD_RESET_INTERRUPT__RESET_INTERRUPT1__MASK 0x00000002U +#define SWD_RESET_INTERRUPT__RESET_INTERRUPT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define SWD_RESET_INTERRUPT__RESET_INTERRUPT1__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define SWD_RESET_INTERRUPT__RESET_INTERRUPT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define SWD_RESET_INTERRUPT__RESET_INTERRUPT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define SWD_RESET_INTERRUPT__RESET_INTERRUPT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SWD_RESET_INTERRUPT__RESET_INTERRUPT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SWD_RESET_INTERRUPT__RESET_INTERRUPT1__RESET_VALUE 0x00000000U +/** @} */ +#define SWD_RESET_INTERRUPT__TYPE uint32_t +#define SWD_RESET_INTERRUPT__READ 0x00000003U +#define SWD_RESET_INTERRUPT__WRITE 0x00000003U +#define SWD_RESET_INTERRUPT__PRESERVED 0x00000000U +#define SWD_RESET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __SWD_RESET_INTERRUPT_MACRO__ */ + +/** @} end of reset_interrupt */ + +/* macros for BlueprintGlobalNameSpace::SWD_dtop_bypass_ctrl */ +/** + * @defgroup at_apb_swd_regs_core_dtop_bypass_ctrl dtop_bypass_ctrl + * @brief Contains register fields associated with dtop_bypass_ctrl. definitions. + * @{ + */ +#ifndef __SWD_DTOP_BYPASS_CTRL_MACRO__ +#define __SWD_DTOP_BYPASS_CTRL_MACRO__ + +/* macros for field hw_own */ +/** + * @defgroup at_apb_swd_regs_core_hw_own_field hw_own_field + * @brief macros for field hw_own + * @details 1 to indicate hw own and sw control is disabled + * @{ + */ +#define SWD_DTOP_BYPASS_CTRL__HW_OWN__SHIFT 0 +#define SWD_DTOP_BYPASS_CTRL__HW_OWN__WIDTH 1 +#define SWD_DTOP_BYPASS_CTRL__HW_OWN__MASK 0x00000001U +#define SWD_DTOP_BYPASS_CTRL__HW_OWN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define SWD_DTOP_BYPASS_CTRL__HW_OWN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWD_DTOP_BYPASS_CTRL__HW_OWN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SWD_DTOP_BYPASS_CTRL__HW_OWN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SWD_DTOP_BYPASS_CTRL__HW_OWN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SWD_DTOP_BYPASS_CTRL__HW_OWN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SWD_DTOP_BYPASS_CTRL__HW_OWN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field byp_rd */ +/** + * @defgroup at_apb_swd_regs_core_byp_rd_field byp_rd_field + * @brief macros for field byp_rd + * @details 1 to bypass read modify write + * @{ + */ +#define SWD_DTOP_BYPASS_CTRL__BYP_RD__SHIFT 1 +#define SWD_DTOP_BYPASS_CTRL__BYP_RD__WIDTH 1 +#define SWD_DTOP_BYPASS_CTRL__BYP_RD__MASK 0x00000002U +#define SWD_DTOP_BYPASS_CTRL__BYP_RD__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define SWD_DTOP_BYPASS_CTRL__BYP_RD__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define SWD_DTOP_BYPASS_CTRL__BYP_RD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define SWD_DTOP_BYPASS_CTRL__BYP_RD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define SWD_DTOP_BYPASS_CTRL__BYP_RD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SWD_DTOP_BYPASS_CTRL__BYP_RD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SWD_DTOP_BYPASS_CTRL__BYP_RD__RESET_VALUE 0x00000000U +/** @} */ +#define SWD_DTOP_BYPASS_CTRL__TYPE uint32_t +#define SWD_DTOP_BYPASS_CTRL__READ 0x00000003U +#define SWD_DTOP_BYPASS_CTRL__WRITE 0x00000003U +#define SWD_DTOP_BYPASS_CTRL__PRESERVED 0x00000000U +#define SWD_DTOP_BYPASS_CTRL__RESET_VALUE 0x00000000U + +#endif /* __SWD_DTOP_BYPASS_CTRL_MACRO__ */ + +/** @} end of dtop_bypass_ctrl */ + +/* macros for BlueprintGlobalNameSpace::SWD_dtop_bypass_stat */ +/** + * @defgroup at_apb_swd_regs_core_dtop_bypass_stat dtop_bypass_stat + * @brief Contains register fields associated with dtop_bypass_stat. definitions. + * @{ + */ +#ifndef __SWD_DTOP_BYPASS_STAT_MACRO__ +#define __SWD_DTOP_BYPASS_STAT_MACRO__ + +/* macros for field mode */ +/** + * @defgroup at_apb_swd_regs_core_mode_field mode_field + * @brief macros for field mode + * @details 1 if fpga is in dtop_bypass mode (built with FPGA_DTOP_BYP defined) + * @{ + */ +#define SWD_DTOP_BYPASS_STAT__MODE__SHIFT 0 +#define SWD_DTOP_BYPASS_STAT__MODE__WIDTH 1 +#define SWD_DTOP_BYPASS_STAT__MODE__MASK 0x00000001U +#define SWD_DTOP_BYPASS_STAT__MODE__READ(src) ((uint32_t)(src) & 0x00000001U) +#define SWD_DTOP_BYPASS_STAT__MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SWD_DTOP_BYPASS_STAT__MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SWD_DTOP_BYPASS_STAT__MODE__RESET_VALUE 0x00000000U +/** @} */ +#define SWD_DTOP_BYPASS_STAT__TYPE uint32_t +#define SWD_DTOP_BYPASS_STAT__READ 0x00000001U +#define SWD_DTOP_BYPASS_STAT__PRESERVED 0x00000000U +#define SWD_DTOP_BYPASS_STAT__RESET_VALUE 0x00000000U + +#endif /* __SWD_DTOP_BYPASS_STAT_MACRO__ */ + +/** @} end of dtop_bypass_stat */ + +/* macros for BlueprintGlobalNameSpace::SWD_dtop_bypass_gpo */ +/** + * @defgroup at_apb_swd_regs_core_dtop_bypass_gpo dtop_bypass_gpo + * @brief Contains register fields associated with dtop_bypass_gpo. definitions. + * @{ + */ +#ifndef __SWD_DTOP_BYPASS_GPO_MACRO__ +#define __SWD_DTOP_BYPASS_GPO_MACRO__ + +/* macros for field gpo */ +/** + * @defgroup at_apb_swd_regs_core_gpo_field gpo_field + * @brief macros for field gpo + * @details 1 selects ext clock as source in DTOP_BYPASS, 0 selects internal pll. + * @{ + */ +#define SWD_DTOP_BYPASS_GPO__GPO__SHIFT 0 +#define SWD_DTOP_BYPASS_GPO__GPO__WIDTH 16 +#define SWD_DTOP_BYPASS_GPO__GPO__MASK 0x0000ffffU +#define SWD_DTOP_BYPASS_GPO__GPO__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define SWD_DTOP_BYPASS_GPO__GPO__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define SWD_DTOP_BYPASS_GPO__GPO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define SWD_DTOP_BYPASS_GPO__GPO__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000ffffU))) +#define SWD_DTOP_BYPASS_GPO__GPO__RESET_VALUE 0x00000000U +/** @} */ +#define SWD_DTOP_BYPASS_GPO__TYPE uint32_t +#define SWD_DTOP_BYPASS_GPO__READ 0x0000ffffU +#define SWD_DTOP_BYPASS_GPO__WRITE 0x0000ffffU +#define SWD_DTOP_BYPASS_GPO__PRESERVED 0x00000000U +#define SWD_DTOP_BYPASS_GPO__RESET_VALUE 0x00000000U + +#endif /* __SWD_DTOP_BYPASS_GPO_MACRO__ */ + +/** @} end of dtop_bypass_gpo */ + +/* macros for BlueprintGlobalNameSpace::SWD_dtop_bypass_rif_mode_cntl */ +/** + * @defgroup at_apb_swd_regs_core_dtop_bypass_rif_mode_cntl dtop_bypass_rif_mode_cntl + * @brief Contains register fields associated with dtop_bypass_rif_mode_cntl. definitions. + * @{ + */ +#ifndef __SWD_DTOP_BYPASS_RIF_MODE_CNTL_MACRO__ +#define __SWD_DTOP_BYPASS_RIF_MODE_CNTL_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_apb_swd_regs_core_addr_field addr_field + * @brief macros for field addr + * @details rif mode control address. + * @{ + */ +#define SWD_DTOP_BYPASS_RIF_MODE_CNTL__ADDR__SHIFT 0 +#define SWD_DTOP_BYPASS_RIF_MODE_CNTL__ADDR__WIDTH 32 +#define SWD_DTOP_BYPASS_RIF_MODE_CNTL__ADDR__MASK 0xffffffffU +#define SWD_DTOP_BYPASS_RIF_MODE_CNTL__ADDR__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define SWD_DTOP_BYPASS_RIF_MODE_CNTL__ADDR__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define SWD_DTOP_BYPASS_RIF_MODE_CNTL__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define SWD_DTOP_BYPASS_RIF_MODE_CNTL__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define SWD_DTOP_BYPASS_RIF_MODE_CNTL__ADDR__RESET_VALUE 0x500040acU +/** @} */ +#define SWD_DTOP_BYPASS_RIF_MODE_CNTL__TYPE uint32_t +#define SWD_DTOP_BYPASS_RIF_MODE_CNTL__READ 0xffffffffU +#define SWD_DTOP_BYPASS_RIF_MODE_CNTL__WRITE 0xffffffffU +#define SWD_DTOP_BYPASS_RIF_MODE_CNTL__PRESERVED 0x00000000U +#define SWD_DTOP_BYPASS_RIF_MODE_CNTL__RESET_VALUE 0x500040acU + +#endif /* __SWD_DTOP_BYPASS_RIF_MODE_CNTL_MACRO__ */ + +/** @} end of dtop_bypass_rif_mode_cntl */ + +/* macros for BlueprintGlobalNameSpace::SWD_dtop_bypass_rif_cal_cntl */ +/** + * @defgroup at_apb_swd_regs_core_dtop_bypass_rif_cal_cntl dtop_bypass_rif_cal_cntl + * @brief Contains register fields associated with dtop_bypass_rif_cal_cntl. definitions. + * @{ + */ +#ifndef __SWD_DTOP_BYPASS_RIF_CAL_CNTL_MACRO__ +#define __SWD_DTOP_BYPASS_RIF_CAL_CNTL_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_apb_swd_regs_core_addr_field addr_field + * @brief macros for field addr + * @details rif cal control address. + * @{ + */ +#define SWD_DTOP_BYPASS_RIF_CAL_CNTL__ADDR__SHIFT 0 +#define SWD_DTOP_BYPASS_RIF_CAL_CNTL__ADDR__WIDTH 32 +#define SWD_DTOP_BYPASS_RIF_CAL_CNTL__ADDR__MASK 0xffffffffU +#define SWD_DTOP_BYPASS_RIF_CAL_CNTL__ADDR__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define SWD_DTOP_BYPASS_RIF_CAL_CNTL__ADDR__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define SWD_DTOP_BYPASS_RIF_CAL_CNTL__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define SWD_DTOP_BYPASS_RIF_CAL_CNTL__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define SWD_DTOP_BYPASS_RIF_CAL_CNTL__ADDR__RESET_VALUE 0x500040b0U +/** @} */ +#define SWD_DTOP_BYPASS_RIF_CAL_CNTL__TYPE uint32_t +#define SWD_DTOP_BYPASS_RIF_CAL_CNTL__READ 0xffffffffU +#define SWD_DTOP_BYPASS_RIF_CAL_CNTL__WRITE 0xffffffffU +#define SWD_DTOP_BYPASS_RIF_CAL_CNTL__PRESERVED 0x00000000U +#define SWD_DTOP_BYPASS_RIF_CAL_CNTL__RESET_VALUE 0x500040b0U + +#endif /* __SWD_DTOP_BYPASS_RIF_CAL_CNTL_MACRO__ */ + +/** @} end of dtop_bypass_rif_cal_cntl */ + +/* macros for BlueprintGlobalNameSpace::SWD_dtop_bypass_rif_rxdc7 */ +/** + * @defgroup at_apb_swd_regs_core_dtop_bypass_rif_rxdc7 dtop_bypass_rif_rxdc7 + * @brief Contains register fields associated with dtop_bypass_rif_rxdc7. definitions. + * @{ + */ +#ifndef __SWD_DTOP_BYPASS_RIF_RXDC7_MACRO__ +#define __SWD_DTOP_BYPASS_RIF_RXDC7_MACRO__ + +/* macros for field addr */ +/** + * @defgroup at_apb_swd_regs_core_addr_field addr_field + * @brief macros for field addr + * @details rif rxdc7 address. + * @{ + */ +#define SWD_DTOP_BYPASS_RIF_RXDC7__ADDR__SHIFT 0 +#define SWD_DTOP_BYPASS_RIF_RXDC7__ADDR__WIDTH 32 +#define SWD_DTOP_BYPASS_RIF_RXDC7__ADDR__MASK 0xffffffffU +#define SWD_DTOP_BYPASS_RIF_RXDC7__ADDR__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define SWD_DTOP_BYPASS_RIF_RXDC7__ADDR__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define SWD_DTOP_BYPASS_RIF_RXDC7__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define SWD_DTOP_BYPASS_RIF_RXDC7__ADDR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define SWD_DTOP_BYPASS_RIF_RXDC7__ADDR__RESET_VALUE 0x50004090U +/** @} */ +#define SWD_DTOP_BYPASS_RIF_RXDC7__TYPE uint32_t +#define SWD_DTOP_BYPASS_RIF_RXDC7__READ 0xffffffffU +#define SWD_DTOP_BYPASS_RIF_RXDC7__WRITE 0xffffffffU +#define SWD_DTOP_BYPASS_RIF_RXDC7__PRESERVED 0x00000000U +#define SWD_DTOP_BYPASS_RIF_RXDC7__RESET_VALUE 0x50004090U + +#endif /* __SWD_DTOP_BYPASS_RIF_RXDC7_MACRO__ */ + +/** @} end of dtop_bypass_rif_rxdc7 */ + +/* macros for BlueprintGlobalNameSpace::SWD_core_id */ +/** + * @defgroup at_apb_swd_regs_core_core_id core_id + * @brief Contains register fields associated with core_id. definitions. + * @{ + */ +#ifndef __SWD_CORE_ID_MACRO__ +#define __SWD_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_swd_regs_core_id_field id_field + * @brief macros for field id + * @details SWD in ASCII + * @{ + */ +#define SWD_CORE_ID__ID__SHIFT 0 +#define SWD_CORE_ID__ID__WIDTH 32 +#define SWD_CORE_ID__ID__MASK 0xffffffffU +#define SWD_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define SWD_CORE_ID__ID__RESET_VALUE 0x53574420U +/** @} */ +#define SWD_CORE_ID__TYPE uint32_t +#define SWD_CORE_ID__READ 0xffffffffU +#define SWD_CORE_ID__PRESERVED 0x00000000U +#define SWD_CORE_ID__RESET_VALUE 0x53574420U + +#endif /* __SWD_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of AT_APB_SWD_REGS_CORE */ +#endif /* __REG_AT_APB_SWD_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_apb_trng_regs_core_macro.h b/ATM33xx-5/include/reg/at_apb_trng_regs_core_macro.h new file mode 100644 index 0000000..ba4284b --- /dev/null +++ b/ATM33xx-5/include/reg/at_apb_trng_regs_core_macro.h @@ -0,0 +1,571 @@ +/* */ +/* File: at_apb_trng_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_apb_trng_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_APB_TRNG_REGS_CORE_H__ +#define __REG_AT_APB_TRNG_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_APB_TRNG_REGS_CORE at_apb_trng_regs_core + * @ingroup AT_REG + * @brief at_apb_trng_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::TRNG_control */ +/** + * @defgroup at_apb_trng_regs_core_control control + * @brief Contains register fields associated with control. definitions. + * @{ + */ +#ifndef __TRNG_CONTROL_MACRO__ +#define __TRNG_CONTROL_MACRO__ + +/* macros for field go */ +/** + * @defgroup at_apb_trng_regs_core_go_field go_field + * @brief macros for field go + * @details start the process of generating a true random number ; not self reseting + * @{ + */ +#define TRNG_CONTROL__GO__SHIFT 0 +#define TRNG_CONTROL__GO__WIDTH 1 +#define TRNG_CONTROL__GO__MASK 0x00000001U +#define TRNG_CONTROL__GO__READ(src) ((uint32_t)(src) & 0x00000001U) +#define TRNG_CONTROL__GO__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define TRNG_CONTROL__GO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define TRNG_CONTROL__GO__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define TRNG_CONTROL__GO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define TRNG_CONTROL__GO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define TRNG_CONTROL__GO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adc_capture_edge */ +/** + * @defgroup at_apb_trng_regs_core_adc_capture_edge_field adc_capture_edge_field + * @brief macros for field adc_capture_edge + * @details 0 = rising edge; 1 = falling edge + * @{ + */ +#define TRNG_CONTROL__ADC_CAPTURE_EDGE__SHIFT 1 +#define TRNG_CONTROL__ADC_CAPTURE_EDGE__WIDTH 1 +#define TRNG_CONTROL__ADC_CAPTURE_EDGE__MASK 0x00000002U +#define TRNG_CONTROL__ADC_CAPTURE_EDGE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define TRNG_CONTROL__ADC_CAPTURE_EDGE__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define TRNG_CONTROL__ADC_CAPTURE_EDGE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define TRNG_CONTROL__ADC_CAPTURE_EDGE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define TRNG_CONTROL__ADC_CAPTURE_EDGE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define TRNG_CONTROL__ADC_CAPTURE_EDGE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define TRNG_CONTROL__ADC_CAPTURE_EDGE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field lsb_source */ +/** + * @defgroup at_apb_trng_regs_core_lsb_source_field lsb_source_field + * @brief macros for field lsb_source + * @details 0 = rif.rif_i[0]; 1 = radio.adc_i[0] + * @{ + */ +#define TRNG_CONTROL__LSB_SOURCE__SHIFT 2 +#define TRNG_CONTROL__LSB_SOURCE__WIDTH 1 +#define TRNG_CONTROL__LSB_SOURCE__MASK 0x00000004U +#define TRNG_CONTROL__LSB_SOURCE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define TRNG_CONTROL__LSB_SOURCE__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define TRNG_CONTROL__LSB_SOURCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define TRNG_CONTROL__LSB_SOURCE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define TRNG_CONTROL__LSB_SOURCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define TRNG_CONTROL__LSB_SOURCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define TRNG_CONTROL__LSB_SOURCE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field radio_gain_override */ +/** + * @defgroup at_apb_trng_regs_core_radio_gain_override_field radio_gain_override_field + * @brief macros for field radio_gain_override + * @{ + */ +#define TRNG_CONTROL__RADIO_GAIN_OVERRIDE__SHIFT 3 +#define TRNG_CONTROL__RADIO_GAIN_OVERRIDE__WIDTH 1 +#define TRNG_CONTROL__RADIO_GAIN_OVERRIDE__MASK 0x00000008U +#define TRNG_CONTROL__RADIO_GAIN_OVERRIDE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define TRNG_CONTROL__RADIO_GAIN_OVERRIDE__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define TRNG_CONTROL__RADIO_GAIN_OVERRIDE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define TRNG_CONTROL__RADIO_GAIN_OVERRIDE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define TRNG_CONTROL__RADIO_GAIN_OVERRIDE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define TRNG_CONTROL__RADIO_GAIN_OVERRIDE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define TRNG_CONTROL__RADIO_GAIN_OVERRIDE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field launch_on_radio_up */ +/** + * @defgroup at_apb_trng_regs_core_launch_on_radio_up_field launch_on_radio_up_field + * @brief macros for field launch_on_radio_up + * @details when radio is first coming back from power down mode, generate automatically (without software intervension) a new random number; this core will assert the radio gain override pin, wait 50usec, and then start the bit gathering process + * @{ + */ +#define TRNG_CONTROL__LAUNCH_ON_RADIO_UP__SHIFT 4 +#define TRNG_CONTROL__LAUNCH_ON_RADIO_UP__WIDTH 1 +#define TRNG_CONTROL__LAUNCH_ON_RADIO_UP__MASK 0x00000010U +#define TRNG_CONTROL__LAUNCH_ON_RADIO_UP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define TRNG_CONTROL__LAUNCH_ON_RADIO_UP__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define TRNG_CONTROL__LAUNCH_ON_RADIO_UP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define TRNG_CONTROL__LAUNCH_ON_RADIO_UP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define TRNG_CONTROL__LAUNCH_ON_RADIO_UP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define TRNG_CONTROL__LAUNCH_ON_RADIO_UP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define TRNG_CONTROL__LAUNCH_ON_RADIO_UP__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field block_force_radio_into_trng_mode */ +/** + * @defgroup at_apb_trng_regs_core_block_force_radio_into_trng_mode_field block_force_radio_into_trng_mode_field + * @brief macros for field block_force_radio_into_trng_mode + * @{ + */ +#define TRNG_CONTROL__BLOCK_FORCE_RADIO_INTO_TRNG_MODE__SHIFT 5 +#define TRNG_CONTROL__BLOCK_FORCE_RADIO_INTO_TRNG_MODE__WIDTH 1 +#define TRNG_CONTROL__BLOCK_FORCE_RADIO_INTO_TRNG_MODE__MASK 0x00000020U +#define TRNG_CONTROL__BLOCK_FORCE_RADIO_INTO_TRNG_MODE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define TRNG_CONTROL__BLOCK_FORCE_RADIO_INTO_TRNG_MODE__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define TRNG_CONTROL__BLOCK_FORCE_RADIO_INTO_TRNG_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define TRNG_CONTROL__BLOCK_FORCE_RADIO_INTO_TRNG_MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define TRNG_CONTROL__BLOCK_FORCE_RADIO_INTO_TRNG_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define TRNG_CONTROL__BLOCK_FORCE_RADIO_INTO_TRNG_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define TRNG_CONTROL__BLOCK_FORCE_RADIO_INTO_TRNG_MODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field radio_warmup_cnt */ +/** + * @defgroup at_apb_trng_regs_core_radio_warmup_cnt_field radio_warmup_cnt_field + * @brief macros for field radio_warmup_cnt + * @details how long to wait for radio to warmup in clk_mpc cycles + * @{ + */ +#define TRNG_CONTROL__RADIO_WARMUP_CNT__SHIFT 6 +#define TRNG_CONTROL__RADIO_WARMUP_CNT__WIDTH 11 +#define TRNG_CONTROL__RADIO_WARMUP_CNT__MASK 0x0001ffc0U +#define TRNG_CONTROL__RADIO_WARMUP_CNT__READ(src) \ + (((uint32_t)(src)\ + & 0x0001ffc0U) >> 6) +#define TRNG_CONTROL__RADIO_WARMUP_CNT__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x0001ffc0U) +#define TRNG_CONTROL__RADIO_WARMUP_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001ffc0U) | (((uint32_t)(src) <<\ + 6) & 0x0001ffc0U) +#define TRNG_CONTROL__RADIO_WARMUP_CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x0001ffc0U))) +#define TRNG_CONTROL__RADIO_WARMUP_CNT__RESET_VALUE 0x00000400U +/** @} */ +#define TRNG_CONTROL__TYPE uint32_t +#define TRNG_CONTROL__READ 0x0001ffffU +#define TRNG_CONTROL__WRITE 0x0001ffffU +#define TRNG_CONTROL__PRESERVED 0x00000000U +#define TRNG_CONTROL__RESET_VALUE 0x00010010U + +#endif /* __TRNG_CONTROL_MACRO__ */ + +/** @} end of control */ + +/* macros for BlueprintGlobalNameSpace::TRNG_status */ +/** + * @defgroup at_apb_trng_regs_core_status status + * @brief Contains register fields associated with status. definitions. + * @{ + */ +#ifndef __TRNG_STATUS_MACRO__ +#define __TRNG_STATUS_MACRO__ + +/* macros for field running */ +/** + * @defgroup at_apb_trng_regs_core_running_field running_field + * @brief macros for field running + * @details this status is asserted after RADIO warm-up + * @{ + */ +#define TRNG_STATUS__RUNNING__SHIFT 0 +#define TRNG_STATUS__RUNNING__WIDTH 1 +#define TRNG_STATUS__RUNNING__MASK 0x00000001U +#define TRNG_STATUS__RUNNING__READ(src) ((uint32_t)(src) & 0x00000001U) +#define TRNG_STATUS__RUNNING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define TRNG_STATUS__RUNNING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define TRNG_STATUS__RUNNING__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fsm_running */ +/** + * @defgroup at_apb_trng_regs_core_fsm_running_field fsm_running_field + * @brief macros for field fsm_running + * @details this status is asserted when the fsm gets out of ST_IDLE + * @{ + */ +#define TRNG_STATUS__FSM_RUNNING__SHIFT 1 +#define TRNG_STATUS__FSM_RUNNING__WIDTH 1 +#define TRNG_STATUS__FSM_RUNNING__MASK 0x00000002U +#define TRNG_STATUS__FSM_RUNNING__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define TRNG_STATUS__FSM_RUNNING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define TRNG_STATUS__FSM_RUNNING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define TRNG_STATUS__FSM_RUNNING__RESET_VALUE 0x00000000U +/** @} */ +#define TRNG_STATUS__TYPE uint32_t +#define TRNG_STATUS__READ 0x00000003U +#define TRNG_STATUS__PRESERVED 0x00000000U +#define TRNG_STATUS__RESET_VALUE 0x00000000U + +#endif /* __TRNG_STATUS_MACRO__ */ + +/** @} end of status */ + +/* macros for BlueprintGlobalNameSpace::TRNG_interrupt_status */ +/** + * @defgroup at_apb_trng_regs_core_interrupt_status interrupt_status + * @brief Contains register fields associated with interrupt_status. definitions. + * @{ + */ +#ifndef __TRNG_INTERRUPT_STATUS_MACRO__ +#define __TRNG_INTERRUPT_STATUS_MACRO__ + +/* macros for field trng_ready */ +/** + * @defgroup at_apb_trng_regs_core_trng_ready_field trng_ready_field + * @brief macros for field trng_ready + * @{ + */ +#define TRNG_INTERRUPT_STATUS__TRNG_READY__SHIFT 0 +#define TRNG_INTERRUPT_STATUS__TRNG_READY__WIDTH 1 +#define TRNG_INTERRUPT_STATUS__TRNG_READY__MASK 0x00000001U +#define TRNG_INTERRUPT_STATUS__TRNG_READY__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define TRNG_INTERRUPT_STATUS__TRNG_READY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define TRNG_INTERRUPT_STATUS__TRNG_READY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define TRNG_INTERRUPT_STATUS__TRNG_READY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field trng_trouble */ +/** + * @defgroup at_apb_trng_regs_core_trng_trouble_field trng_trouble_field + * @brief macros for field trng_trouble + * @{ + */ +#define TRNG_INTERRUPT_STATUS__TRNG_TROUBLE__SHIFT 1 +#define TRNG_INTERRUPT_STATUS__TRNG_TROUBLE__WIDTH 1 +#define TRNG_INTERRUPT_STATUS__TRNG_TROUBLE__MASK 0x00000002U +#define TRNG_INTERRUPT_STATUS__TRNG_TROUBLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define TRNG_INTERRUPT_STATUS__TRNG_TROUBLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define TRNG_INTERRUPT_STATUS__TRNG_TROUBLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define TRNG_INTERRUPT_STATUS__TRNG_TROUBLE__RESET_VALUE 0x00000000U +/** @} */ +#define TRNG_INTERRUPT_STATUS__TYPE uint32_t +#define TRNG_INTERRUPT_STATUS__READ 0x00000003U +#define TRNG_INTERRUPT_STATUS__PRESERVED 0x00000000U +#define TRNG_INTERRUPT_STATUS__RESET_VALUE 0x00000000U + +#endif /* __TRNG_INTERRUPT_STATUS_MACRO__ */ + +/** @} end of interrupt_status */ + +/* macros for BlueprintGlobalNameSpace::TRNG_interrupt_mask */ +/** + * @defgroup at_apb_trng_regs_core_interrupt_mask interrupt_mask + * @brief Contains register fields associated with interrupt_mask. definitions. + * @{ + */ +#ifndef __TRNG_INTERRUPT_MASK_MACRO__ +#define __TRNG_INTERRUPT_MASK_MACRO__ + +/* macros for field intrpt_mask */ +/** + * @defgroup at_apb_trng_regs_core_intrpt_mask_field intrpt_mask_field + * @brief macros for field intrpt_mask + * @details if nth bit set, the nth interrupt source is allowed to propogate to core's interrupt + * @{ + */ +#define TRNG_INTERRUPT_MASK__INTRPT_MASK__SHIFT 0 +#define TRNG_INTERRUPT_MASK__INTRPT_MASK__WIDTH 2 +#define TRNG_INTERRUPT_MASK__INTRPT_MASK__MASK 0x00000003U +#define TRNG_INTERRUPT_MASK__INTRPT_MASK__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define TRNG_INTERRUPT_MASK__INTRPT_MASK__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define TRNG_INTERRUPT_MASK__INTRPT_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define TRNG_INTERRUPT_MASK__INTRPT_MASK__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define TRNG_INTERRUPT_MASK__INTRPT_MASK__RESET_VALUE 0x00000003U +/** @} */ +#define TRNG_INTERRUPT_MASK__TYPE uint32_t +#define TRNG_INTERRUPT_MASK__READ 0x00000003U +#define TRNG_INTERRUPT_MASK__WRITE 0x00000003U +#define TRNG_INTERRUPT_MASK__PRESERVED 0x00000000U +#define TRNG_INTERRUPT_MASK__RESET_VALUE 0x00000003U + +#endif /* __TRNG_INTERRUPT_MASK_MACRO__ */ + +/** @} end of interrupt_mask */ + +/* macros for BlueprintGlobalNameSpace::TRNG_set_interrupt */ +/** + * @defgroup at_apb_trng_regs_core_set_interrupt set_interrupt + * @brief Contains register fields associated with set_interrupt. definitions. + * @{ + */ +#ifndef __TRNG_SET_INTERRUPT_MACRO__ +#define __TRNG_SET_INTERRUPT_MACRO__ + +/* macros for field intrpt_set */ +/** + * @defgroup at_apb_trng_regs_core_intrpt_set_field intrpt_set_field + * @brief macros for field intrpt_set + * @details not self clearing + * @{ + */ +#define TRNG_SET_INTERRUPT__INTRPT_SET__SHIFT 0 +#define TRNG_SET_INTERRUPT__INTRPT_SET__WIDTH 2 +#define TRNG_SET_INTERRUPT__INTRPT_SET__MASK 0x00000003U +#define TRNG_SET_INTERRUPT__INTRPT_SET__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define TRNG_SET_INTERRUPT__INTRPT_SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define TRNG_SET_INTERRUPT__INTRPT_SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define TRNG_SET_INTERRUPT__INTRPT_SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define TRNG_SET_INTERRUPT__INTRPT_SET__RESET_VALUE 0x00000000U +/** @} */ +#define TRNG_SET_INTERRUPT__TYPE uint32_t +#define TRNG_SET_INTERRUPT__READ 0x00000003U +#define TRNG_SET_INTERRUPT__WRITE 0x00000003U +#define TRNG_SET_INTERRUPT__PRESERVED 0x00000000U +#define TRNG_SET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __TRNG_SET_INTERRUPT_MACRO__ */ + +/** @} end of set_interrupt */ + +/* macros for BlueprintGlobalNameSpace::TRNG_reset_interrupt */ +/** + * @defgroup at_apb_trng_regs_core_reset_interrupt reset_interrupt + * @brief Contains register fields associated with reset_interrupt. definitions. + * @{ + */ +#ifndef __TRNG_RESET_INTERRUPT_MACRO__ +#define __TRNG_RESET_INTERRUPT_MACRO__ + +/* macros for field intrpt_reset */ +/** + * @defgroup at_apb_trng_regs_core_intrpt_reset_field intrpt_reset_field + * @brief macros for field intrpt_reset + * @details not self clearing + * @{ + */ +#define TRNG_RESET_INTERRUPT__INTRPT_RESET__SHIFT 0 +#define TRNG_RESET_INTERRUPT__INTRPT_RESET__WIDTH 2 +#define TRNG_RESET_INTERRUPT__INTRPT_RESET__MASK 0x00000003U +#define TRNG_RESET_INTERRUPT__INTRPT_RESET__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define TRNG_RESET_INTERRUPT__INTRPT_RESET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define TRNG_RESET_INTERRUPT__INTRPT_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define TRNG_RESET_INTERRUPT__INTRPT_RESET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define TRNG_RESET_INTERRUPT__INTRPT_RESET__RESET_VALUE 0x00000000U +/** @} */ +#define TRNG_RESET_INTERRUPT__TYPE uint32_t +#define TRNG_RESET_INTERRUPT__READ 0x00000003U +#define TRNG_RESET_INTERRUPT__WRITE 0x00000003U +#define TRNG_RESET_INTERRUPT__PRESERVED 0x00000000U +#define TRNG_RESET_INTERRUPT__RESET_VALUE 0x00000000U + +#endif /* __TRNG_RESET_INTERRUPT_MACRO__ */ + +/** @} end of reset_interrupt */ + +/* macros for BlueprintGlobalNameSpace::TRNG_trng */ +/** + * @defgroup at_apb_trng_regs_core_trng trng + * @brief Contains register fields associated with trng. definitions. + * @{ + */ +#ifndef __TRNG_TRNG_MACRO__ +#define __TRNG_TRNG_MACRO__ + +/* macros for field val */ +/** + * @defgroup at_apb_trng_regs_core_val_field val_field + * @brief macros for field val + * @details the generated true random number + * @{ + */ +#define TRNG_TRNG__VAL__SHIFT 0 +#define TRNG_TRNG__VAL__WIDTH 32 +#define TRNG_TRNG__VAL__MASK 0xffffffffU +#define TRNG_TRNG__VAL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define TRNG_TRNG__VAL__RESET_VALUE 0x00000000U +/** @} */ +#define TRNG_TRNG__TYPE uint32_t +#define TRNG_TRNG__READ 0xffffffffU +#define TRNG_TRNG__PRESERVED 0x00000000U +#define TRNG_TRNG__RESET_VALUE 0x00000000U + +#endif /* __TRNG_TRNG_MACRO__ */ + +/** @} end of trng */ + +/* macros for BlueprintGlobalNameSpace::TRNG_core_id */ +/** + * @defgroup at_apb_trng_regs_core_core_id core_id + * @brief Contains register fields associated with core_id. definitions. + * @{ + */ +#ifndef __TRNG_CORE_ID_MACRO__ +#define __TRNG_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_trng_regs_core_id_field id_field + * @brief macros for field id + * @details TRNG in ASCII + * @{ + */ +#define TRNG_CORE_ID__ID__SHIFT 0 +#define TRNG_CORE_ID__ID__WIDTH 32 +#define TRNG_CORE_ID__ID__MASK 0xffffffffU +#define TRNG_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define TRNG_CORE_ID__ID__RESET_VALUE 0x54524e47U +/** @} */ +#define TRNG_CORE_ID__TYPE uint32_t +#define TRNG_CORE_ID__READ 0xffffffffU +#define TRNG_CORE_ID__PRESERVED 0x00000000U +#define TRNG_CORE_ID__RESET_VALUE 0x54524e47U + +#endif /* __TRNG_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of AT_APB_TRNG_REGS_CORE */ +#endif /* __REG_AT_APB_TRNG_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_apb_tsmc_nvm_regs_core_macro.h b/ATM33xx-5/include/reg/at_apb_tsmc_nvm_regs_core_macro.h new file mode 100644 index 0000000..0a768d1 --- /dev/null +++ b/ATM33xx-5/include/reg/at_apb_tsmc_nvm_regs_core_macro.h @@ -0,0 +1,1162 @@ +/* */ +/* File: at_apb_tsmc_nvm_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_apb_tsmc_nvm_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_APB_TSMC_NVM_REGS_CORE_H__ +#define __REG_AT_APB_TSMC_NVM_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_APB_TSMC_NVM_REGS_CORE at_apb_tsmc_nvm_regs_core + * @ingroup AT_REG + * @brief at_apb_tsmc_nvm_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::NVM_opmode */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_opmode opmode + * @brief Contains register fields associated with opmode. definitions. + * @{ + */ +#ifndef __NVM_OPMODE_MACRO__ +#define __NVM_OPMODE_MACRO__ + +/* macros for field read */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_read_field read_field + * @brief macros for field read + * @details read opcode + * @{ + */ +#define NVM_OPMODE__READ__SHIFT 0 +#define NVM_OPMODE__READ__WIDTH 1 +#define NVM_OPMODE__READ__MASK 0x00000001U +#define NVM_OPMODE__READ__READ(src) ((uint32_t)(src) & 0x00000001U) +#define NVM_OPMODE__READ__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define NVM_OPMODE__READ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define NVM_OPMODE__READ__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define NVM_OPMODE__READ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define NVM_OPMODE__READ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define NVM_OPMODE__READ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field program */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_program_field program_field + * @brief macros for field program + * @details program opcode + * @{ + */ +#define NVM_OPMODE__PROGRAM__SHIFT 1 +#define NVM_OPMODE__PROGRAM__WIDTH 1 +#define NVM_OPMODE__PROGRAM__MASK 0x00000002U +#define NVM_OPMODE__PROGRAM__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define NVM_OPMODE__PROGRAM__WRITE(src) (((uint32_t)(src) << 1) & 0x00000002U) +#define NVM_OPMODE__PROGRAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define NVM_OPMODE__PROGRAM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define NVM_OPMODE__PROGRAM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define NVM_OPMODE__PROGRAM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define NVM_OPMODE__PROGRAM__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field go */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_go_field go_field + * @brief macros for field go + * @details opcode start when rising edge on 'go' is detected. + * @{ + */ +#define NVM_OPMODE__GO__SHIFT 31 +#define NVM_OPMODE__GO__WIDTH 1 +#define NVM_OPMODE__GO__MASK 0x80000000U +#define NVM_OPMODE__GO__READ(src) (((uint32_t)(src) & 0x80000000U) >> 31) +#define NVM_OPMODE__GO__WRITE(src) (((uint32_t)(src) << 31) & 0x80000000U) +#define NVM_OPMODE__GO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define NVM_OPMODE__GO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define NVM_OPMODE__GO__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define NVM_OPMODE__GO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define NVM_OPMODE__GO__RESET_VALUE 0x00000000U +/** @} */ +#define NVM_OPMODE__TYPE uint32_t +#define NVM_OPMODE__READ 0x80000003U +#define NVM_OPMODE__WRITE 0x80000003U +#define NVM_OPMODE__PRESERVED 0x00000000U +#define NVM_OPMODE__RESET_VALUE 0x00000000U + +#endif /* __NVM_OPMODE_MACRO__ */ + +/** @} end of opmode */ + +/* macros for BlueprintGlobalNameSpace::NVM_ctrl */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_ctrl ctrl + * @brief Contains register fields associated with ctrl. definitions. + * @{ + */ +#ifndef __NVM_CTRL_MACRO__ +#define __NVM_CTRL_MACRO__ + +/* macros for field ser_dout_en */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_ser_dout_en_field ser_dout_en_field + * @brief macros for field ser_dout_en + * @details enable serial data out and allow soft repair during read + * @{ + */ +#define NVM_CTRL__SER_DOUT_EN__SHIFT 0 +#define NVM_CTRL__SER_DOUT_EN__WIDTH 1 +#define NVM_CTRL__SER_DOUT_EN__MASK 0x00000001U +#define NVM_CTRL__SER_DOUT_EN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define NVM_CTRL__SER_DOUT_EN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define NVM_CTRL__SER_DOUT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define NVM_CTRL__SER_DOUT_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define NVM_CTRL__SER_DOUT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define NVM_CTRL__SER_DOUT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define NVM_CTRL__SER_DOUT_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field burst_mode */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_burst_mode_field burst_mode_field + * @brief macros for field burst_mode + * @details burst or single bit programming 1 = serial burst program bits starting at bit 0 up to specified bit number in num_pgm_bit register using specified input data from data0/data1 registers 0 = single program bit specified in num_pgm_bit register programming sets efuse bit to 1 + * @{ + */ +#define NVM_CTRL__BURST_MODE__SHIFT 1 +#define NVM_CTRL__BURST_MODE__WIDTH 1 +#define NVM_CTRL__BURST_MODE__MASK 0x00000002U +#define NVM_CTRL__BURST_MODE__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define NVM_CTRL__BURST_MODE__WRITE(src) (((uint32_t)(src) << 1) & 0x00000002U) +#define NVM_CTRL__BURST_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define NVM_CTRL__BURST_MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define NVM_CTRL__BURST_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define NVM_CTRL__BURST_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define NVM_CTRL__BURST_MODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field num_pgm_bit */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_num_pgm_bit_field num_pgm_bit_field + * @brief macros for field num_pgm_bit + * @details In single mode, specifies bit location to program; actual bit location is (programmed number - 1) ex. to program bit 0; num_pgm_bit=1, to program bit 63; num_pgm_bit=64 In burst mode, program bits location from 0 up to (programmed number - 1). + * @{ + */ +#define NVM_CTRL__NUM_PGM_BIT__SHIFT 2 +#define NVM_CTRL__NUM_PGM_BIT__WIDTH 7 +#define NVM_CTRL__NUM_PGM_BIT__MASK 0x000001fcU +#define NVM_CTRL__NUM_PGM_BIT__READ(src) (((uint32_t)(src) & 0x000001fcU) >> 2) +#define NVM_CTRL__NUM_PGM_BIT__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x000001fcU) +#define NVM_CTRL__NUM_PGM_BIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001fcU) | (((uint32_t)(src) <<\ + 2) & 0x000001fcU) +#define NVM_CTRL__NUM_PGM_BIT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x000001fcU))) +#define NVM_CTRL__NUM_PGM_BIT__RESET_VALUE 0x00000040U +/** @} */ +#define NVM_CTRL__TYPE uint32_t +#define NVM_CTRL__READ 0x000001ffU +#define NVM_CTRL__WRITE 0x000001ffU +#define NVM_CTRL__PRESERVED 0x00000000U +#define NVM_CTRL__RESET_VALUE 0x00000100U + +#endif /* __NVM_CTRL_MACRO__ */ + +/** @} end of ctrl */ + +/* macros for BlueprintGlobalNameSpace::NVM_data0 */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_data0 data0 + * @brief Contains register fields associated with data0. definitions. + * @{ + */ +#ifndef __NVM_DATA0_MACRO__ +#define __NVM_DATA0_MACRO__ + +/* macros for field data0 */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_data0_field data0_field + * @brief macros for field data0 + * @details otp data word-0, can be used for program or read data based on target operation + * @{ + */ +#define NVM_DATA0__DATA0__SHIFT 0 +#define NVM_DATA0__DATA0__WIDTH 32 +#define NVM_DATA0__DATA0__MASK 0xffffffffU +#define NVM_DATA0__DATA0__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define NVM_DATA0__DATA0__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define NVM_DATA0__DATA0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define NVM_DATA0__DATA0__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define NVM_DATA0__DATA0__RESET_VALUE 0x00000000U +/** @} */ +#define NVM_DATA0__TYPE uint32_t +#define NVM_DATA0__READ 0xffffffffU +#define NVM_DATA0__WRITE 0xffffffffU +#define NVM_DATA0__PRESERVED 0x00000000U +#define NVM_DATA0__RESET_VALUE 0x00000000U + +#endif /* __NVM_DATA0_MACRO__ */ + +/** @} end of data0 */ + +/* macros for BlueprintGlobalNameSpace::NVM_data1 */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_data1 data1 + * @brief Contains register fields associated with data1. definitions. + * @{ + */ +#ifndef __NVM_DATA1_MACRO__ +#define __NVM_DATA1_MACRO__ + +/* macros for field data1 */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_data1_field data1_field + * @brief macros for field data1 + * @details otp data word-1, can be used for program or read data based on target operation + * @{ + */ +#define NVM_DATA1__DATA1__SHIFT 0 +#define NVM_DATA1__DATA1__WIDTH 32 +#define NVM_DATA1__DATA1__MASK 0xffffffffU +#define NVM_DATA1__DATA1__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define NVM_DATA1__DATA1__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define NVM_DATA1__DATA1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define NVM_DATA1__DATA1__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define NVM_DATA1__DATA1__RESET_VALUE 0x00000000U +/** @} */ +#define NVM_DATA1__TYPE uint32_t +#define NVM_DATA1__READ 0xffffffffU +#define NVM_DATA1__WRITE 0xffffffffU +#define NVM_DATA1__PRESERVED 0x00000000U +#define NVM_DATA1__RESET_VALUE 0x00000000U + +#endif /* __NVM_DATA1_MACRO__ */ + +/** @} end of data1 */ + +/* macros for BlueprintGlobalNameSpace::NVM_status */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_status status + * @brief Contains register fields associated with status. definitions. + * @{ + */ +#ifndef __NVM_STATUS_MACRO__ +#define __NVM_STATUS_MACRO__ + +/* macros for field read_done */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_read_done_field read_done_field + * @brief macros for field read_done + * @details read done + * @{ + */ +#define NVM_STATUS__READ_DONE__SHIFT 0 +#define NVM_STATUS__READ_DONE__WIDTH 1 +#define NVM_STATUS__READ_DONE__MASK 0x00000001U +#define NVM_STATUS__READ_DONE__READ(src) ((uint32_t)(src) & 0x00000001U) +#define NVM_STATUS__READ_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define NVM_STATUS__READ_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define NVM_STATUS__READ_DONE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field program_done */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_program_done_field program_done_field + * @brief macros for field program_done + * @details programming done + * @{ + */ +#define NVM_STATUS__PROGRAM_DONE__SHIFT 1 +#define NVM_STATUS__PROGRAM_DONE__WIDTH 1 +#define NVM_STATUS__PROGRAM_DONE__MASK 0x00000002U +#define NVM_STATUS__PROGRAM_DONE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define NVM_STATUS__PROGRAM_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define NVM_STATUS__PROGRAM_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define NVM_STATUS__PROGRAM_DONE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field running */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_running_field running_field + * @brief macros for field running + * @details read or program running + * @{ + */ +#define NVM_STATUS__RUNNING__SHIFT 31 +#define NVM_STATUS__RUNNING__WIDTH 1 +#define NVM_STATUS__RUNNING__MASK 0x80000000U +#define NVM_STATUS__RUNNING__READ(src) (((uint32_t)(src) & 0x80000000U) >> 31) +#define NVM_STATUS__RUNNING__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define NVM_STATUS__RUNNING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define NVM_STATUS__RUNNING__RESET_VALUE 0x00000000U +/** @} */ +#define NVM_STATUS__TYPE uint32_t +#define NVM_STATUS__READ 0x80000003U +#define NVM_STATUS__PRESERVED 0x00000000U +#define NVM_STATUS__RESET_VALUE 0x00000000U + +#endif /* __NVM_STATUS_MACRO__ */ + +/** @} end of status */ + +/* macros for BlueprintGlobalNameSpace::NVM_t_sp_vq */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_t_sp_vq t_sp_vq + * @brief VDDQ to CSB setup time into program mode definitions. + * @{ + */ +#ifndef __NVM_T_SP_VQ_MACRO__ +#define __NVM_T_SP_VQ_MACRO__ + +/* macros for field cycles */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_cycles_field cycles_field + * @brief macros for field cycles + * @details want >= 10 nsec; each lsb accounts for 16usec, max when all bits programmed is around 500usec default 16usec based on 16MHz system clock + * @{ + */ +#define NVM_T_SP_VQ__CYCLES__SHIFT 0 +#define NVM_T_SP_VQ__CYCLES__WIDTH 5 +#define NVM_T_SP_VQ__CYCLES__MASK 0x0000001fU +#define NVM_T_SP_VQ__CYCLES__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_SP_VQ__CYCLES__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_SP_VQ__CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define NVM_T_SP_VQ__CYCLES__VERIFY(src) (!(((uint32_t)(src) & ~0x0000001fU))) +#define NVM_T_SP_VQ__CYCLES__RESET_VALUE 0x00000001U +/** @} */ +#define NVM_T_SP_VQ__TYPE uint32_t +#define NVM_T_SP_VQ__READ 0x0000001fU +#define NVM_T_SP_VQ__WRITE 0x0000001fU +#define NVM_T_SP_VQ__PRESERVED 0x00000000U +#define NVM_T_SP_VQ__RESET_VALUE 0x00000001U + +#endif /* __NVM_T_SP_VQ_MACRO__ */ + +/** @} end of t_sp_vq */ + +/* macros for BlueprintGlobalNameSpace::NVM_t_hp_vq */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_t_hp_vq t_hp_vq + * @brief VDDQ to CSB hold time out of program mode definitions. + * @{ + */ +#ifndef __NVM_T_HP_VQ_MACRO__ +#define __NVM_T_HP_VQ_MACRO__ + +/* macros for field cycles */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_cycles_field cycles_field + * @brief macros for field cycles + * @details want >= 10 nsec; actual delay is (programmed number + 1), default based on 16MHz system clock + * @{ + */ +#define NVM_T_HP_VQ__CYCLES__SHIFT 0 +#define NVM_T_HP_VQ__CYCLES__WIDTH 5 +#define NVM_T_HP_VQ__CYCLES__MASK 0x0000001fU +#define NVM_T_HP_VQ__CYCLES__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_HP_VQ__CYCLES__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_HP_VQ__CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define NVM_T_HP_VQ__CYCLES__VERIFY(src) (!(((uint32_t)(src) & ~0x0000001fU))) +#define NVM_T_HP_VQ__CYCLES__RESET_VALUE 0x00000000U +/** @} */ +#define NVM_T_HP_VQ__TYPE uint32_t +#define NVM_T_HP_VQ__READ 0x0000001fU +#define NVM_T_HP_VQ__WRITE 0x0000001fU +#define NVM_T_HP_VQ__PRESERVED 0x00000000U +#define NVM_T_HP_VQ__RESET_VALUE 0x00000000U + +#endif /* __NVM_T_HP_VQ_MACRO__ */ + +/** @} end of t_hp_vq */ + +/* macros for BlueprintGlobalNameSpace::NVM_t_sp_pg */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_t_sp_pg t_sp_pg + * @brief PGM to CSB setup time into program mode definitions. + * @{ + */ +#ifndef __NVM_T_SP_PG_MACRO__ +#define __NVM_T_SP_PG_MACRO__ + +/* macros for field cycles */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_cycles_field cycles_field + * @brief macros for field cycles + * @details want >= 5 nsec; actual delay is (programmed number + 1), default based on 16MHz system clock + * @{ + */ +#define NVM_T_SP_PG__CYCLES__SHIFT 0 +#define NVM_T_SP_PG__CYCLES__WIDTH 5 +#define NVM_T_SP_PG__CYCLES__MASK 0x0000001fU +#define NVM_T_SP_PG__CYCLES__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_SP_PG__CYCLES__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_SP_PG__CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define NVM_T_SP_PG__CYCLES__VERIFY(src) (!(((uint32_t)(src) & ~0x0000001fU))) +#define NVM_T_SP_PG__CYCLES__RESET_VALUE 0x00000000U +/** @} */ +#define NVM_T_SP_PG__TYPE uint32_t +#define NVM_T_SP_PG__READ 0x0000001fU +#define NVM_T_SP_PG__WRITE 0x0000001fU +#define NVM_T_SP_PG__PRESERVED 0x00000000U +#define NVM_T_SP_PG__RESET_VALUE 0x00000000U + +#endif /* __NVM_T_SP_PG_MACRO__ */ + +/** @} end of t_sp_pg */ + +/* macros for BlueprintGlobalNameSpace::NVM_t_hp_pg */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_t_hp_pg t_hp_pg + * @brief PGM to CSB hold time into program mode definitions. + * @{ + */ +#ifndef __NVM_T_HP_PG_MACRO__ +#define __NVM_T_HP_PG_MACRO__ + +/* macros for field cycles */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_cycles_field cycles_field + * @brief macros for field cycles + * @details want >= 5 nsec; actual delay is (programmed number + 1), default based on 16MHz system clock + * @{ + */ +#define NVM_T_HP_PG__CYCLES__SHIFT 0 +#define NVM_T_HP_PG__CYCLES__WIDTH 5 +#define NVM_T_HP_PG__CYCLES__MASK 0x0000001fU +#define NVM_T_HP_PG__CYCLES__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_HP_PG__CYCLES__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_HP_PG__CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define NVM_T_HP_PG__CYCLES__VERIFY(src) (!(((uint32_t)(src) & ~0x0000001fU))) +#define NVM_T_HP_PG__CYCLES__RESET_VALUE 0x00000000U +/** @} */ +#define NVM_T_HP_PG__TYPE uint32_t +#define NVM_T_HP_PG__READ 0x0000001fU +#define NVM_T_HP_PG__WRITE 0x0000001fU +#define NVM_T_HP_PG__PRESERVED 0x00000000U +#define NVM_T_HP_PG__RESET_VALUE 0x00000000U + +#endif /* __NVM_T_HP_PG_MACRO__ */ + +/** @} end of t_hp_pg */ + +/* macros for BlueprintGlobalNameSpace::NVM_t_hp_ck */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_t_hp_ck t_hp_ck + * @brief SCLK to CSB hold time into program mode definitions. + * @{ + */ +#ifndef __NVM_T_HP_CK_MACRO__ +#define __NVM_T_HP_CK_MACRO__ + +/* macros for field cycles */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_cycles_field cycles_field + * @brief macros for field cycles + * @details want >= 31 nsec; actual delay is (programmed number + 1), default based on 16MHz system clock + * @{ + */ +#define NVM_T_HP_CK__CYCLES__SHIFT 0 +#define NVM_T_HP_CK__CYCLES__WIDTH 5 +#define NVM_T_HP_CK__CYCLES__MASK 0x0000001fU +#define NVM_T_HP_CK__CYCLES__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_HP_CK__CYCLES__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_HP_CK__CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define NVM_T_HP_CK__CYCLES__VERIFY(src) (!(((uint32_t)(src) & ~0x0000001fU))) +#define NVM_T_HP_CK__CYCLES__RESET_VALUE 0x00000001U +/** @} */ +#define NVM_T_HP_CK__TYPE uint32_t +#define NVM_T_HP_CK__READ 0x0000001fU +#define NVM_T_HP_CK__WRITE 0x0000001fU +#define NVM_T_HP_CK__PRESERVED 0x00000000U +#define NVM_T_HP_CK__RESET_VALUE 0x00000001U + +#endif /* __NVM_T_HP_CK_MACRO__ */ + +/** @} end of t_hp_ck */ + +/* macros for BlueprintGlobalNameSpace::NVM_t_s_pgm */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_t_s_pgm t_s_pgm + * @brief PGM to SCLK setup time to program bits definitions. + * @{ + */ +#ifndef __NVM_T_S_PGM_MACRO__ +#define __NVM_T_S_PGM_MACRO__ + +/* macros for field cycles */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_cycles_field cycles_field + * @brief macros for field cycles + * @details want >= 8 nsec; actual delay is (programmed number + 1), default based on 16MHz system clock + * @{ + */ +#define NVM_T_S_PGM__CYCLES__SHIFT 0 +#define NVM_T_S_PGM__CYCLES__WIDTH 6 +#define NVM_T_S_PGM__CYCLES__MASK 0x0000003fU +#define NVM_T_S_PGM__CYCLES__READ(src) ((uint32_t)(src) & 0x0000003fU) +#define NVM_T_S_PGM__CYCLES__WRITE(src) ((uint32_t)(src) & 0x0000003fU) +#define NVM_T_S_PGM__CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define NVM_T_S_PGM__CYCLES__VERIFY(src) (!(((uint32_t)(src) & ~0x0000003fU))) +#define NVM_T_S_PGM__CYCLES__RESET_VALUE 0x00000000U +/** @} */ +#define NVM_T_S_PGM__TYPE uint32_t +#define NVM_T_S_PGM__READ 0x0000003fU +#define NVM_T_S_PGM__WRITE 0x0000003fU +#define NVM_T_S_PGM__PRESERVED 0x00000000U +#define NVM_T_S_PGM__RESET_VALUE 0x00000000U + +#endif /* __NVM_T_S_PGM_MACRO__ */ + +/** @} end of t_s_pgm */ + +/* macros for BlueprintGlobalNameSpace::NVM_t_h_pgm */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_t_h_pgm t_h_pgm + * @brief PGM to SCLK hold time to program bits definitions. + * @{ + */ +#ifndef __NVM_T_H_PGM_MACRO__ +#define __NVM_T_H_PGM_MACRO__ + +/* macros for field cycles */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_cycles_field cycles_field + * @brief macros for field cycles + * @details want >= 8 nsec; actual delay is (programmed number + 1), default based on 16MHz system clock + * @{ + */ +#define NVM_T_H_PGM__CYCLES__SHIFT 0 +#define NVM_T_H_PGM__CYCLES__WIDTH 6 +#define NVM_T_H_PGM__CYCLES__MASK 0x0000003fU +#define NVM_T_H_PGM__CYCLES__READ(src) ((uint32_t)(src) & 0x0000003fU) +#define NVM_T_H_PGM__CYCLES__WRITE(src) ((uint32_t)(src) & 0x0000003fU) +#define NVM_T_H_PGM__CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define NVM_T_H_PGM__CYCLES__VERIFY(src) (!(((uint32_t)(src) & ~0x0000003fU))) +#define NVM_T_H_PGM__CYCLES__RESET_VALUE 0x00000000U +/** @} */ +#define NVM_T_H_PGM__TYPE uint32_t +#define NVM_T_H_PGM__READ 0x0000003fU +#define NVM_T_H_PGM__WRITE 0x0000003fU +#define NVM_T_H_PGM__PRESERVED 0x00000000U +#define NVM_T_H_PGM__RESET_VALUE 0x00000000U + +#endif /* __NVM_T_H_PGM_MACRO__ */ + +/** @} end of t_h_pgm */ + +/* macros for BlueprintGlobalNameSpace::NVM_t_ckhp */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_t_ckhp t_ckhp + * @brief SCLK high period for program definitions. + * @{ + */ +#ifndef __NVM_T_CKHP_MACRO__ +#define __NVM_T_CKHP_MACRO__ + +/* macros for field cycles */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_cycles_field cycles_field + * @brief macros for field cycles + * @details want >= 9 usec and <= 11 usec; default for 10 usec actual delay is (programmed number + 1), default based on 16MHz system clock + * @{ + */ +#define NVM_T_CKHP__CYCLES__SHIFT 0 +#define NVM_T_CKHP__CYCLES__WIDTH 11 +#define NVM_T_CKHP__CYCLES__MASK 0x000007ffU +#define NVM_T_CKHP__CYCLES__READ(src) ((uint32_t)(src) & 0x000007ffU) +#define NVM_T_CKHP__CYCLES__WRITE(src) ((uint32_t)(src) & 0x000007ffU) +#define NVM_T_CKHP__CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007ffU) | ((uint32_t)(src) &\ + 0x000007ffU) +#define NVM_T_CKHP__CYCLES__VERIFY(src) (!(((uint32_t)(src) & ~0x000007ffU))) +#define NVM_T_CKHP__CYCLES__RESET_VALUE 0x000000a0U +/** @} */ +#define NVM_T_CKHP__TYPE uint32_t +#define NVM_T_CKHP__READ 0x000007ffU +#define NVM_T_CKHP__WRITE 0x000007ffU +#define NVM_T_CKHP__PRESERVED 0x00000000U +#define NVM_T_CKHP__RESET_VALUE 0x000000a0U + +#endif /* __NVM_T_CKHP_MACRO__ */ + +/** @} end of t_ckhp */ + +/* macros for BlueprintGlobalNameSpace::NVM_t_cklp */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_t_cklp t_cklp + * @brief SCLK low period for program definitions. + * @{ + */ +#ifndef __NVM_T_CKLP_MACRO__ +#define __NVM_T_CKLP_MACRO__ + +/* macros for field cycles */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_cycles_field cycles_field + * @brief macros for field cycles + * @details want >= 10 nsec; actual delay is (programmed number + 1), default based on 16MHz system clock + * @{ + */ +#define NVM_T_CKLP__CYCLES__SHIFT 0 +#define NVM_T_CKLP__CYCLES__WIDTH 5 +#define NVM_T_CKLP__CYCLES__MASK 0x0000001fU +#define NVM_T_CKLP__CYCLES__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_CKLP__CYCLES__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_CKLP__CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define NVM_T_CKLP__CYCLES__VERIFY(src) (!(((uint32_t)(src) & ~0x0000001fU))) +#define NVM_T_CKLP__CYCLES__RESET_VALUE 0x00000000U +/** @} */ +#define NVM_T_CKLP__TYPE uint32_t +#define NVM_T_CKLP__READ 0x0000001fU +#define NVM_T_CKLP__WRITE 0x0000001fU +#define NVM_T_CKLP__PRESERVED 0x00000000U +#define NVM_T_CKLP__RESET_VALUE 0x00000000U + +#endif /* __NVM_T_CKLP_MACRO__ */ + +/** @} end of t_cklp */ + +/* macros for BlueprintGlobalNameSpace::NVM_t_sps_ck */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_t_sps_ck t_sps_ck + * @brief CSB to SCLK hold time out of program mode definitions. + * @{ + */ +#ifndef __NVM_T_SPS_CK_MACRO__ +#define __NVM_T_SPS_CK_MACRO__ + +/* macros for field cycles */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_cycles_field cycles_field + * @brief macros for field cycles + * @details want >= 31 nsec; actual delay is (programmed number + 1), default based on 16MHz system clock + * @{ + */ +#define NVM_T_SPS_CK__CYCLES__SHIFT 0 +#define NVM_T_SPS_CK__CYCLES__WIDTH 5 +#define NVM_T_SPS_CK__CYCLES__MASK 0x0000001fU +#define NVM_T_SPS_CK__CYCLES__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_SPS_CK__CYCLES__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_SPS_CK__CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define NVM_T_SPS_CK__CYCLES__VERIFY(src) (!(((uint32_t)(src) & ~0x0000001fU))) +#define NVM_T_SPS_CK__CYCLES__RESET_VALUE 0x00000001U +/** @} */ +#define NVM_T_SPS_CK__TYPE uint32_t +#define NVM_T_SPS_CK__READ 0x0000001fU +#define NVM_T_SPS_CK__WRITE 0x0000001fU +#define NVM_T_SPS_CK__PRESERVED 0x00000000U +#define NVM_T_SPS_CK__RESET_VALUE 0x00000001U + +#endif /* __NVM_T_SPS_CK_MACRO__ */ + +/** @} end of t_sps_ck */ + +/* macros for BlueprintGlobalNameSpace::NVM_t_sr_ck */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_t_sr_ck t_sr_ck + * @brief SCLK to CSB setup time into read mode definitions. + * @{ + */ +#ifndef __NVM_T_SR_CK_MACRO__ +#define __NVM_T_SR_CK_MACRO__ + +/* macros for field cycles */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_cycles_field cycles_field + * @brief macros for field cycles + * @details want >= 6 nsec; actual delay is (programmed number + 1), default based on 16MHz system clock + * @{ + */ +#define NVM_T_SR_CK__CYCLES__SHIFT 0 +#define NVM_T_SR_CK__CYCLES__WIDTH 5 +#define NVM_T_SR_CK__CYCLES__MASK 0x0000001fU +#define NVM_T_SR_CK__CYCLES__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_SR_CK__CYCLES__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_SR_CK__CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define NVM_T_SR_CK__CYCLES__VERIFY(src) (!(((uint32_t)(src) & ~0x0000001fU))) +#define NVM_T_SR_CK__CYCLES__RESET_VALUE 0x00000000U +/** @} */ +#define NVM_T_SR_CK__TYPE uint32_t +#define NVM_T_SR_CK__READ 0x0000001fU +#define NVM_T_SR_CK__WRITE 0x0000001fU +#define NVM_T_SR_CK__PRESERVED 0x00000000U +#define NVM_T_SR_CK__RESET_VALUE 0x00000000U + +#endif /* __NVM_T_SR_CK_MACRO__ */ + +/** @} end of t_sr_ck */ + +/* macros for BlueprintGlobalNameSpace::NVM_t_hr_ck */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_t_hr_ck t_hr_ck + * @brief SCLK to CSB hold time into read mode definitions. + * @{ + */ +#ifndef __NVM_T_HR_CK_MACRO__ +#define __NVM_T_HR_CK_MACRO__ + +/* macros for field cycles */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_cycles_field cycles_field + * @brief macros for field cycles + * @details want >= 940 nsec; actual delay is (programmed number + 1), default based on 16MHz system clock + * @{ + */ +#define NVM_T_HR_CK__CYCLES__SHIFT 0 +#define NVM_T_HR_CK__CYCLES__WIDTH 10 +#define NVM_T_HR_CK__CYCLES__MASK 0x000003ffU +#define NVM_T_HR_CK__CYCLES__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define NVM_T_HR_CK__CYCLES__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define NVM_T_HR_CK__CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define NVM_T_HR_CK__CYCLES__VERIFY(src) (!(((uint32_t)(src) & ~0x000003ffU))) +#define NVM_T_HR_CK__CYCLES__RESET_VALUE 0x0000000eU +/** @} */ +#define NVM_T_HR_CK__TYPE uint32_t +#define NVM_T_HR_CK__READ 0x000003ffU +#define NVM_T_HR_CK__WRITE 0x000003ffU +#define NVM_T_HR_CK__PRESERVED 0x00000000U +#define NVM_T_HR_CK__RESET_VALUE 0x0000000eU + +#endif /* __NVM_T_HR_CK_MACRO__ */ + +/** @} end of t_hr_ck */ + +/* macros for BlueprintGlobalNameSpace::NVM_t_cklr */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_t_cklr t_cklr + * @brief SCLK low period for read definitions. + * @{ + */ +#ifndef __NVM_T_CKLR_MACRO__ +#define __NVM_T_CKLR_MACRO__ + +/* macros for field cycles */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_cycles_field cycles_field + * @brief macros for field cycles + * @details want >= 10 nsec; actual delay is (programmed number + 1), default based on 16MHz system clock + * @{ + */ +#define NVM_T_CKLR__CYCLES__SHIFT 0 +#define NVM_T_CKLR__CYCLES__WIDTH 5 +#define NVM_T_CKLR__CYCLES__MASK 0x0000001fU +#define NVM_T_CKLR__CYCLES__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_CKLR__CYCLES__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_CKLR__CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define NVM_T_CKLR__CYCLES__VERIFY(src) (!(((uint32_t)(src) & ~0x0000001fU))) +#define NVM_T_CKLR__CYCLES__RESET_VALUE 0x00000000U +/** @} */ +#define NVM_T_CKLR__TYPE uint32_t +#define NVM_T_CKLR__READ 0x0000001fU +#define NVM_T_CKLR__WRITE 0x0000001fU +#define NVM_T_CKLR__PRESERVED 0x00000000U +#define NVM_T_CKLR__RESET_VALUE 0x00000000U + +#endif /* __NVM_T_CKLR_MACRO__ */ + +/** @} end of t_cklr */ + +/* macros for BlueprintGlobalNameSpace::NVM_t_ckhr */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_t_ckhr t_ckhr + * @brief SCLK high period for read definitions. + * @{ + */ +#ifndef __NVM_T_CKHR_MACRO__ +#define __NVM_T_CKHR_MACRO__ + +/* macros for field cycles */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_cycles_field cycles_field + * @brief macros for field cycles + * @details want >= 10 nsec; actual delay is (programmed number + 1), default based on 16MHz system clock + * @{ + */ +#define NVM_T_CKHR__CYCLES__SHIFT 0 +#define NVM_T_CKHR__CYCLES__WIDTH 5 +#define NVM_T_CKHR__CYCLES__MASK 0x0000001fU +#define NVM_T_CKHR__CYCLES__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_CKHR__CYCLES__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_CKHR__CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define NVM_T_CKHR__CYCLES__VERIFY(src) (!(((uint32_t)(src) & ~0x0000001fU))) +#define NVM_T_CKHR__CYCLES__RESET_VALUE 0x00000000U +/** @} */ +#define NVM_T_CKHR__TYPE uint32_t +#define NVM_T_CKHR__READ 0x0000001fU +#define NVM_T_CKHR__WRITE 0x0000001fU +#define NVM_T_CKHR__PRESERVED 0x00000000U +#define NVM_T_CKHR__RESET_VALUE 0x00000000U + +#endif /* __NVM_T_CKHR_MACRO__ */ + +/** @} end of t_ckhr */ + +/* macros for BlueprintGlobalNameSpace::NVM_t_srs_ck */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_t_srs_ck t_srs_ck + * @brief CSB to SCLK hold time out of read mode definitions. + * @{ + */ +#ifndef __NVM_T_SRS_CK_MACRO__ +#define __NVM_T_SRS_CK_MACRO__ + +/* macros for field cycles */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_cycles_field cycles_field + * @brief macros for field cycles + * @details want >= 20 nsec; actual delay is (programmed number + 1), default based on 16MHz system clock + * @{ + */ +#define NVM_T_SRS_CK__CYCLES__SHIFT 0 +#define NVM_T_SRS_CK__CYCLES__WIDTH 5 +#define NVM_T_SRS_CK__CYCLES__MASK 0x0000001fU +#define NVM_T_SRS_CK__CYCLES__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_SRS_CK__CYCLES__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define NVM_T_SRS_CK__CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define NVM_T_SRS_CK__CYCLES__VERIFY(src) (!(((uint32_t)(src) & ~0x0000001fU))) +#define NVM_T_SRS_CK__CYCLES__RESET_VALUE 0x00000000U +/** @} */ +#define NVM_T_SRS_CK__TYPE uint32_t +#define NVM_T_SRS_CK__READ 0x0000001fU +#define NVM_T_SRS_CK__WRITE 0x0000001fU +#define NVM_T_SRS_CK__PRESERVED 0x00000000U +#define NVM_T_SRS_CK__RESET_VALUE 0x00000000U + +#endif /* __NVM_T_SRS_CK_MACRO__ */ + +/** @} end of t_srs_ck */ + +/* macros for BlueprintGlobalNameSpace::NVM_interrupt_status */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_interrupt_status interrupt_status + * @brief Contains register fields associated with interrupt_status. definitions. + * @{ + */ +#ifndef __NVM_INTERRUPT_STATUS_MACRO__ +#define __NVM_INTERRUPT_STATUS_MACRO__ + +/* macros for field intrpt0 */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_intrpt0_field intrpt0_field + * @brief macros for field intrpt0 + * @details saw a rising edge on read or program done; independent of mask + * @{ + */ +#define NVM_INTERRUPT_STATUS__INTRPT0__SHIFT 0 +#define NVM_INTERRUPT_STATUS__INTRPT0__WIDTH 1 +#define NVM_INTERRUPT_STATUS__INTRPT0__MASK 0x00000001U +#define NVM_INTERRUPT_STATUS__INTRPT0__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define NVM_INTERRUPT_STATUS__INTRPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define NVM_INTERRUPT_STATUS__INTRPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define NVM_INTERRUPT_STATUS__INTRPT0__RESET_VALUE 0x00000000U +/** @} */ +#define NVM_INTERRUPT_STATUS__TYPE uint32_t +#define NVM_INTERRUPT_STATUS__READ 0x00000001U +#define NVM_INTERRUPT_STATUS__PRESERVED 0x00000000U +#define NVM_INTERRUPT_STATUS__RESET_VALUE 0x00000000U + +#endif /* __NVM_INTERRUPT_STATUS_MACRO__ */ + +/** @} end of interrupt_status */ + +/* macros for BlueprintGlobalNameSpace::NVM_interrupt_mask */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_interrupt_mask interrupt_mask + * @brief Contains register fields associated with interrupt_mask. definitions. + * @{ + */ +#ifndef __NVM_INTERRUPT_MASK_MACRO__ +#define __NVM_INTERRUPT_MASK_MACRO__ + +/* macros for field intrpt0 */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_intrpt0_field intrpt0_field + * @brief macros for field intrpt0 + * @details 1=allow intrpt0 to be OR'ed into core interrupt + * @{ + */ +#define NVM_INTERRUPT_MASK__INTRPT0__SHIFT 0 +#define NVM_INTERRUPT_MASK__INTRPT0__WIDTH 1 +#define NVM_INTERRUPT_MASK__INTRPT0__MASK 0x00000001U +#define NVM_INTERRUPT_MASK__INTRPT0__READ(src) ((uint32_t)(src) & 0x00000001U) +#define NVM_INTERRUPT_MASK__INTRPT0__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define NVM_INTERRUPT_MASK__INTRPT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define NVM_INTERRUPT_MASK__INTRPT0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define NVM_INTERRUPT_MASK__INTRPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define NVM_INTERRUPT_MASK__INTRPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define NVM_INTERRUPT_MASK__INTRPT0__RESET_VALUE 0x00000000U +/** @} */ +#define NVM_INTERRUPT_MASK__TYPE uint32_t +#define NVM_INTERRUPT_MASK__READ 0x00000001U +#define NVM_INTERRUPT_MASK__WRITE 0x00000001U +#define NVM_INTERRUPT_MASK__PRESERVED 0x00000000U +#define NVM_INTERRUPT_MASK__RESET_VALUE 0x00000000U + +#endif /* __NVM_INTERRUPT_MASK_MACRO__ */ + +/** @} end of interrupt_mask */ + +/* macros for BlueprintGlobalNameSpace::NVM_interrupt_set */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_interrupt_set interrupt_set + * @brief not auto cleared definitions. + * @{ + */ +#ifndef __NVM_INTERRUPT_SET_MACRO__ +#define __NVM_INTERRUPT_SET_MACRO__ + +/* macros for field intrpt0 */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_intrpt0_field intrpt0_field + * @brief macros for field intrpt0 + * @{ + */ +#define NVM_INTERRUPT_SET__INTRPT0__SHIFT 0 +#define NVM_INTERRUPT_SET__INTRPT0__WIDTH 1 +#define NVM_INTERRUPT_SET__INTRPT0__MASK 0x00000001U +#define NVM_INTERRUPT_SET__INTRPT0__READ(src) ((uint32_t)(src) & 0x00000001U) +#define NVM_INTERRUPT_SET__INTRPT0__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define NVM_INTERRUPT_SET__INTRPT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define NVM_INTERRUPT_SET__INTRPT0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define NVM_INTERRUPT_SET__INTRPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define NVM_INTERRUPT_SET__INTRPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define NVM_INTERRUPT_SET__INTRPT0__RESET_VALUE 0x00000000U +/** @} */ +#define NVM_INTERRUPT_SET__TYPE uint32_t +#define NVM_INTERRUPT_SET__READ 0x00000001U +#define NVM_INTERRUPT_SET__WRITE 0x00000001U +#define NVM_INTERRUPT_SET__PRESERVED 0x00000000U +#define NVM_INTERRUPT_SET__RESET_VALUE 0x00000000U + +#endif /* __NVM_INTERRUPT_SET_MACRO__ */ + +/** @} end of interrupt_set */ + +/* macros for BlueprintGlobalNameSpace::NVM_interrupt_reset */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_interrupt_reset interrupt_reset + * @brief not auto cleared definitions. + * @{ + */ +#ifndef __NVM_INTERRUPT_RESET_MACRO__ +#define __NVM_INTERRUPT_RESET_MACRO__ + +/* macros for field intrpt0 */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_intrpt0_field intrpt0_field + * @brief macros for field intrpt0 + * @{ + */ +#define NVM_INTERRUPT_RESET__INTRPT0__SHIFT 0 +#define NVM_INTERRUPT_RESET__INTRPT0__WIDTH 1 +#define NVM_INTERRUPT_RESET__INTRPT0__MASK 0x00000001U +#define NVM_INTERRUPT_RESET__INTRPT0__READ(src) ((uint32_t)(src) & 0x00000001U) +#define NVM_INTERRUPT_RESET__INTRPT0__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define NVM_INTERRUPT_RESET__INTRPT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define NVM_INTERRUPT_RESET__INTRPT0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define NVM_INTERRUPT_RESET__INTRPT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define NVM_INTERRUPT_RESET__INTRPT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define NVM_INTERRUPT_RESET__INTRPT0__RESET_VALUE 0x00000000U +/** @} */ +#define NVM_INTERRUPT_RESET__TYPE uint32_t +#define NVM_INTERRUPT_RESET__READ 0x00000001U +#define NVM_INTERRUPT_RESET__WRITE 0x00000001U +#define NVM_INTERRUPT_RESET__PRESERVED 0x00000000U +#define NVM_INTERRUPT_RESET__RESET_VALUE 0x00000000U + +#endif /* __NVM_INTERRUPT_RESET_MACRO__ */ + +/** @} end of interrupt_reset */ + +/* macros for BlueprintGlobalNameSpace::NVM_core_id */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_core_id core_id + * @brief CORE ID definitions. + * @{ + */ +#ifndef __NVM_CORE_ID_MACRO__ +#define __NVM_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_tsmc_nvm_regs_core_id_field id_field + * @brief macros for field id + * @details NVM in ASCII + * @{ + */ +#define NVM_CORE_ID__ID__SHIFT 0 +#define NVM_CORE_ID__ID__WIDTH 32 +#define NVM_CORE_ID__ID__MASK 0xffffffffU +#define NVM_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define NVM_CORE_ID__ID__RESET_VALUE 0x4e564d20U +/** @} */ +#define NVM_CORE_ID__TYPE uint32_t +#define NVM_CORE_ID__READ 0xffffffffU +#define NVM_CORE_ID__PRESERVED 0x00000000U +#define NVM_CORE_ID__RESET_VALUE 0x4e564d20U + +#endif /* __NVM_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of AT_APB_TSMC_NVM_REGS_CORE */ +#endif /* __REG_AT_APB_TSMC_NVM_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_apb_uart_regs_core_macro.h b/ATM33xx-5/include/reg/at_apb_uart_regs_core_macro.h new file mode 100644 index 0000000..48c7ba9 --- /dev/null +++ b/ATM33xx-5/include/reg/at_apb_uart_regs_core_macro.h @@ -0,0 +1,2486 @@ +/* */ +/* File: at_apb_uart_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_apb_uart_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_APB_UART_REGS_CORE_H__ +#define __REG_AT_APB_UART_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_APB_UART_REGS_CORE at_apb_uart_regs_core + * @ingroup AT_REG + * @brief at_apb_uart_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_DATA */ +/** + * @defgroup at_apb_uart_regs_core_DATA DATA + * @brief Contains register fields associated with DATA. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_DATA_MACRO__ +#define __CMSDK_AT_UART_DATA_MACRO__ + +/* macros for field Data */ +/** + * @defgroup at_apb_uart_regs_core_Data_field Data_field + * @brief macros for field Data + * @details Read Received data. Write Transmit data. + * @{ + */ +#define CMSDK_AT_UART_DATA__DATA__SHIFT 0 +#define CMSDK_AT_UART_DATA__DATA__WIDTH 8 +#define CMSDK_AT_UART_DATA__DATA__MASK 0x000000ffU +#define CMSDK_AT_UART_DATA_Pos CMSDK_AT_UART_DATA__DATA__SHIFT +#define CMSDK_AT_UART_DATA_Msk CMSDK_AT_UART_DATA__DATA__MASK +#define CMSDK_UART_DATA_Pos CMSDK_AT_UART_DATA__DATA__SHIFT +#define CMSDK_UART_DATA_Msk CMSDK_AT_UART_DATA__DATA__MASK +#define CMSDK_AT_UART_DATA__DATA__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define CMSDK_AT_UART_DATA__DATA__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define CMSDK_AT_UART_DATA__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define CMSDK_AT_UART_DATA__DATA__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define CMSDK_AT_UART_DATA__DATA__RESET_VALUE 0x00000000U +/** @} */ +#define CMSDK_AT_UART_DATA__TYPE uint32_t +#define CMSDK_AT_UART_DATA__READ 0x000000ffU +#define CMSDK_AT_UART_DATA__WRITE 0x000000ffU +#define CMSDK_AT_UART_DATA__PRESERVED 0x00000000U +#define CMSDK_AT_UART_DATA__RESET_VALUE 0x00000000U + +#endif /* __CMSDK_AT_UART_DATA_MACRO__ */ + +/** @} end of DATA */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_STATE */ +/** + * @defgroup at_apb_uart_regs_core_STATE STATE + * @brief Contains register fields associated with STATE. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_STATE_MACRO__ +#define __CMSDK_AT_UART_STATE_MACRO__ + +/* macros for field tx_buf_full */ +/** + * @defgroup at_apb_uart_regs_core_tx_buf_full_field tx_buf_full_field + * @brief macros for field tx_buf_full + * @details TX buffer full, read-only. + * @{ + */ +#define CMSDK_AT_UART_STATE__TXBF__SHIFT 0 +#define CMSDK_AT_UART_STATE__TXBF__WIDTH 1 +#define CMSDK_AT_UART_STATE__TXBF__MASK 0x00000001U +#define CMSDK_AT_UART_STATE_TXBF_Pos CMSDK_AT_UART_STATE__TXBF__SHIFT +#define CMSDK_AT_UART_STATE_TXBF_Msk CMSDK_AT_UART_STATE__TXBF__MASK +#define CMSDK_UART_STATE_TXBF_Pos CMSDK_AT_UART_STATE__TXBF__SHIFT +#define CMSDK_UART_STATE_TXBF_Msk CMSDK_AT_UART_STATE__TXBF__MASK +#define CMSDK_AT_UART_STATE__TXBF__READ(src) ((uint32_t)(src) & 0x00000001U) +#define CMSDK_AT_UART_STATE__TXBF__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define CMSDK_AT_UART_STATE__TXBF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define CMSDK_AT_UART_STATE__TXBF__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define CMSDK_AT_UART_STATE__TXBF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define CMSDK_AT_UART_STATE__TXBF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define CMSDK_AT_UART_STATE__TXBF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_buf_full */ +/** + * @defgroup at_apb_uart_regs_core_rx_buf_full_field rx_buf_full_field + * @brief macros for field rx_buf_full + * @details 1=RX buffer is not empty, 0= RX buffer is empty read-only. + * @{ + */ +#define CMSDK_AT_UART_STATE__RXBF__SHIFT 1 +#define CMSDK_AT_UART_STATE__RXBF__WIDTH 1 +#define CMSDK_AT_UART_STATE__RXBF__MASK 0x00000002U +#define CMSDK_AT_UART_STATE_RXBF_Pos CMSDK_AT_UART_STATE__RXBF__SHIFT +#define CMSDK_AT_UART_STATE_RXBF_Msk CMSDK_AT_UART_STATE__RXBF__MASK +#define CMSDK_UART_STATE_RXBF_Pos CMSDK_AT_UART_STATE__RXBF__SHIFT +#define CMSDK_UART_STATE_RXBF_Msk CMSDK_AT_UART_STATE__RXBF__MASK +#define CMSDK_AT_UART_STATE__RXBF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define CMSDK_AT_UART_STATE__RXBF__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define CMSDK_AT_UART_STATE__RXBF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define CMSDK_AT_UART_STATE__RXBF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define CMSDK_AT_UART_STATE__RXBF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define CMSDK_AT_UART_STATE__RXBF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define CMSDK_AT_UART_STATE__RXBF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tx_overrun */ +/** + * @defgroup at_apb_uart_regs_core_tx_overrun_field tx_overrun_field + * @brief macros for field tx_overrun + * @details TX buffer overrun, write 1 to clear. + * @{ + */ +#define CMSDK_AT_UART_STATE__TXOR__SHIFT 2 +#define CMSDK_AT_UART_STATE__TXOR__WIDTH 1 +#define CMSDK_AT_UART_STATE__TXOR__MASK 0x00000004U +#define CMSDK_AT_UART_STATE_TXOR_Pos CMSDK_AT_UART_STATE__TXOR__SHIFT +#define CMSDK_AT_UART_STATE_TXOR_Msk CMSDK_AT_UART_STATE__TXOR__MASK +#define CMSDK_UART_STATE_TXOR_Pos CMSDK_AT_UART_STATE__TXOR__SHIFT +#define CMSDK_UART_STATE_TXOR_Msk CMSDK_AT_UART_STATE__TXOR__MASK +#define CMSDK_AT_UART_STATE__TXOR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define CMSDK_AT_UART_STATE__TXOR__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define CMSDK_AT_UART_STATE__TXOR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define CMSDK_AT_UART_STATE__TXOR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define CMSDK_AT_UART_STATE__TXOR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define CMSDK_AT_UART_STATE__TXOR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define CMSDK_AT_UART_STATE__TXOR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_overrun */ +/** + * @defgroup at_apb_uart_regs_core_rx_overrun_field rx_overrun_field + * @brief macros for field rx_overrun + * @details RX buffer overrun, write 1 to clear. + * @{ + */ +#define CMSDK_AT_UART_STATE__RXOR__SHIFT 3 +#define CMSDK_AT_UART_STATE__RXOR__WIDTH 1 +#define CMSDK_AT_UART_STATE__RXOR__MASK 0x00000008U +#define CMSDK_AT_UART_STATE_RXOR_Pos CMSDK_AT_UART_STATE__RXOR__SHIFT +#define CMSDK_AT_UART_STATE_RXOR_Msk CMSDK_AT_UART_STATE__RXOR__MASK +#define CMSDK_UART_STATE_RXOR_Pos CMSDK_AT_UART_STATE__RXOR__SHIFT +#define CMSDK_UART_STATE_RXOR_Msk CMSDK_AT_UART_STATE__RXOR__MASK +#define CMSDK_AT_UART_STATE__RXOR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define CMSDK_AT_UART_STATE__RXOR__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define CMSDK_AT_UART_STATE__RXOR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define CMSDK_AT_UART_STATE__RXOR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define CMSDK_AT_UART_STATE__RXOR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define CMSDK_AT_UART_STATE__RXOR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define CMSDK_AT_UART_STATE__RXOR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nUARTRTS */ +/** + * @defgroup at_apb_uart_regs_core_nUARTRTS_field nUARTRTS_field + * @brief macros for field nUARTRTS + * @details current status of nUARTRTS (Read only) // (Atmosic) + * @{ + */ +#define CMSDK_AT_UART_STATE__NRTS__SHIFT 4 +#define CMSDK_AT_UART_STATE__NRTS__WIDTH 1 +#define CMSDK_AT_UART_STATE__NRTS__MASK 0x00000010U +#define CMSDK_AT_UART_STATE_NRTS_Pos CMSDK_AT_UART_STATE__NRTS__SHIFT +#define CMSDK_AT_UART_STATE_NRTS_Msk CMSDK_AT_UART_STATE__NRTS__MASK +#define CMSDK_UART_STATE_NRTS_Pos CMSDK_AT_UART_STATE__NRTS__SHIFT +#define CMSDK_UART_STATE_NRTS_Msk CMSDK_AT_UART_STATE__NRTS__MASK +#define CMSDK_AT_UART_STATE__NRTS__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define CMSDK_AT_UART_STATE__NRTS__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define CMSDK_AT_UART_STATE__NRTS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define CMSDK_AT_UART_STATE__NRTS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define CMSDK_AT_UART_STATE__NRTS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define CMSDK_AT_UART_STATE__NRTS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define CMSDK_AT_UART_STATE__NRTS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nUARTCTS */ +/** + * @defgroup at_apb_uart_regs_core_nUARTCTS_field nUARTCTS_field + * @brief macros for field nUARTCTS + * @details current status of nUARTCTS (Read only) // (Atmosic) + * @{ + */ +#define CMSDK_AT_UART_STATE__NCTS__SHIFT 5 +#define CMSDK_AT_UART_STATE__NCTS__WIDTH 1 +#define CMSDK_AT_UART_STATE__NCTS__MASK 0x00000020U +#define CMSDK_AT_UART_STATE_NCTS_Pos CMSDK_AT_UART_STATE__NCTS__SHIFT +#define CMSDK_AT_UART_STATE_NCTS_Msk CMSDK_AT_UART_STATE__NCTS__MASK +#define CMSDK_UART_STATE_NCTS_Pos CMSDK_AT_UART_STATE__NCTS__SHIFT +#define CMSDK_UART_STATE_NCTS_Msk CMSDK_AT_UART_STATE__NCTS__MASK +#define CMSDK_AT_UART_STATE__NCTS__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define CMSDK_AT_UART_STATE__NCTS__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define CMSDK_AT_UART_STATE__NCTS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define CMSDK_AT_UART_STATE__NCTS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define CMSDK_AT_UART_STATE__NCTS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define CMSDK_AT_UART_STATE__NCTS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define CMSDK_AT_UART_STATE__NCTS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field stop_bit_err */ +/** + * @defgroup at_apb_uart_regs_core_stop_bit_err_field stop_bit_err_field + * @brief macros for field stop_bit_err + * @details 1=stop_bit err (Read only) // (Atmosic) + * @{ + */ +#define CMSDK_AT_UART_STATE__STOP_BIT_ERR__SHIFT 6 +#define CMSDK_AT_UART_STATE__STOP_BIT_ERR__WIDTH 1 +#define CMSDK_AT_UART_STATE__STOP_BIT_ERR__MASK 0x00000040U +#define CMSDK_AT_UART_STATE_STOP_BIT_ERR_Pos \ + CMSDK_AT_UART_STATE__STOP_BIT_ERR__SHIFT +#define CMSDK_AT_UART_STATE_STOP_BIT_ERR_Msk \ + CMSDK_AT_UART_STATE__STOP_BIT_ERR__MASK +#define CMSDK_UART_STATE_STOP_BIT_ERR_Pos \ + CMSDK_AT_UART_STATE__STOP_BIT_ERR__SHIFT +#define CMSDK_UART_STATE_STOP_BIT_ERR_Msk \ + CMSDK_AT_UART_STATE__STOP_BIT_ERR__MASK +#define CMSDK_AT_UART_STATE__STOP_BIT_ERR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define CMSDK_AT_UART_STATE__STOP_BIT_ERR__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define CMSDK_AT_UART_STATE__STOP_BIT_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define CMSDK_AT_UART_STATE__STOP_BIT_ERR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define CMSDK_AT_UART_STATE__STOP_BIT_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define CMSDK_AT_UART_STATE__STOP_BIT_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define CMSDK_AT_UART_STATE__STOP_BIT_ERR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tx_idle */ +/** + * @defgroup at_apb_uart_regs_core_tx_idle_field tx_idle_field + * @brief macros for field tx_idle + * @details 1=tx state is idle (Read only) // (Atmosic) + * @{ + */ +#define CMSDK_AT_UART_STATE__TX_IDLE__SHIFT 7 +#define CMSDK_AT_UART_STATE__TX_IDLE__WIDTH 1 +#define CMSDK_AT_UART_STATE__TX_IDLE__MASK 0x00000080U +#define CMSDK_AT_UART_STATE_TX_IDLE_Pos CMSDK_AT_UART_STATE__TX_IDLE__SHIFT +#define CMSDK_AT_UART_STATE_TX_IDLE_Msk CMSDK_AT_UART_STATE__TX_IDLE__MASK +#define CMSDK_UART_STATE_TX_IDLE_Pos CMSDK_AT_UART_STATE__TX_IDLE__SHIFT +#define CMSDK_UART_STATE_TX_IDLE_Msk CMSDK_AT_UART_STATE__TX_IDLE__MASK +#define CMSDK_AT_UART_STATE__TX_IDLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define CMSDK_AT_UART_STATE__TX_IDLE__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define CMSDK_AT_UART_STATE__TX_IDLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define CMSDK_AT_UART_STATE__TX_IDLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define CMSDK_AT_UART_STATE__TX_IDLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define CMSDK_AT_UART_STATE__TX_IDLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define CMSDK_AT_UART_STATE__TX_IDLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tx_locked_stat */ +/** + * @defgroup at_apb_uart_regs_core_tx_locked_stat_field tx_locked_stat_field + * @brief macros for field tx_locked_stat + * @details 1=(Sticky) indicates whether tx is locked. Once locked, it remains locked until a system reset. (Read only) // (Atmosic) + * @{ + */ +#define CMSDK_AT_UART_STATE__TX_LOCKED_STAT__SHIFT 8 +#define CMSDK_AT_UART_STATE__TX_LOCKED_STAT__WIDTH 1 +#define CMSDK_AT_UART_STATE__TX_LOCKED_STAT__MASK 0x00000100U +#define CMSDK_AT_UART_STATE_TX_LOCKED_STAT_Pos \ + CMSDK_AT_UART_STATE__TX_LOCKED_STAT__SHIFT +#define CMSDK_AT_UART_STATE_TX_LOCKED_STAT_Msk \ + CMSDK_AT_UART_STATE__TX_LOCKED_STAT__MASK +#define CMSDK_UART_STATE_TX_LOCKED_STAT_Pos \ + CMSDK_AT_UART_STATE__TX_LOCKED_STAT__SHIFT +#define CMSDK_UART_STATE_TX_LOCKED_STAT_Msk \ + CMSDK_AT_UART_STATE__TX_LOCKED_STAT__MASK +#define CMSDK_AT_UART_STATE__TX_LOCKED_STAT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define CMSDK_AT_UART_STATE__TX_LOCKED_STAT__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define CMSDK_AT_UART_STATE__TX_LOCKED_STAT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define CMSDK_AT_UART_STATE__TX_LOCKED_STAT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define CMSDK_AT_UART_STATE__TX_LOCKED_STAT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define CMSDK_AT_UART_STATE__TX_LOCKED_STAT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define CMSDK_AT_UART_STATE__TX_LOCKED_STAT__RESET_VALUE 0x00000000U +/** @} */ +#define CMSDK_AT_UART_STATE__TYPE uint32_t +#define CMSDK_AT_UART_STATE__READ 0x000001ffU +#define CMSDK_AT_UART_STATE__WRITE 0x000001ffU +#define CMSDK_AT_UART_STATE__PRESERVED 0x00000000U +#define CMSDK_AT_UART_STATE__RESET_VALUE 0x00000000U + +#endif /* __CMSDK_AT_UART_STATE_MACRO__ */ + +/** @} end of STATE */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_CTRL */ +/** + * @defgroup at_apb_uart_regs_core_CTRL CTRL + * @brief Contains register fields associated with CTRL. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_CTRL_MACRO__ +#define __CMSDK_AT_UART_CTRL_MACRO__ + +/* macros for field TxEn */ +/** + * @defgroup at_apb_uart_regs_core_TxEn_field TxEn_field + * @brief macros for field TxEn + * @details TX enable. + * @{ + */ +#define CMSDK_AT_UART_CTRL__TXEN__SHIFT 0 +#define CMSDK_AT_UART_CTRL__TXEN__WIDTH 1 +#define CMSDK_AT_UART_CTRL__TXEN__MASK 0x00000001U +#define CMSDK_AT_UART_CTRL_TXEN_Pos CMSDK_AT_UART_CTRL__TXEN__SHIFT +#define CMSDK_AT_UART_CTRL_TXEN_Msk CMSDK_AT_UART_CTRL__TXEN__MASK +#define CMSDK_UART_CTRL_TXEN_Pos CMSDK_AT_UART_CTRL__TXEN__SHIFT +#define CMSDK_UART_CTRL_TXEN_Msk CMSDK_AT_UART_CTRL__TXEN__MASK +#define CMSDK_AT_UART_CTRL__TXEN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define CMSDK_AT_UART_CTRL__TXEN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define CMSDK_AT_UART_CTRL__TXEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define CMSDK_AT_UART_CTRL__TXEN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define CMSDK_AT_UART_CTRL__TXEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define CMSDK_AT_UART_CTRL__TXEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define CMSDK_AT_UART_CTRL__TXEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field RxEn */ +/** + * @defgroup at_apb_uart_regs_core_RxEn_field RxEn_field + * @brief macros for field RxEn + * @details RX enable. + * @{ + */ +#define CMSDK_AT_UART_CTRL__RXEN__SHIFT 1 +#define CMSDK_AT_UART_CTRL__RXEN__WIDTH 1 +#define CMSDK_AT_UART_CTRL__RXEN__MASK 0x00000002U +#define CMSDK_AT_UART_CTRL_RXEN_Pos CMSDK_AT_UART_CTRL__RXEN__SHIFT +#define CMSDK_AT_UART_CTRL_RXEN_Msk CMSDK_AT_UART_CTRL__RXEN__MASK +#define CMSDK_UART_CTRL_RXEN_Pos CMSDK_AT_UART_CTRL__RXEN__SHIFT +#define CMSDK_UART_CTRL_RXEN_Msk CMSDK_AT_UART_CTRL__RXEN__MASK +#define CMSDK_AT_UART_CTRL__RXEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define CMSDK_AT_UART_CTRL__RXEN__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define CMSDK_AT_UART_CTRL__RXEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define CMSDK_AT_UART_CTRL__RXEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define CMSDK_AT_UART_CTRL__RXEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define CMSDK_AT_UART_CTRL__RXEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define CMSDK_AT_UART_CTRL__RXEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field TxIntEn */ +/** + * @defgroup at_apb_uart_regs_core_TxIntEn_field TxIntEn_field + * @brief macros for field TxIntEn + * @details TX interrupt enable. + * @{ + */ +#define CMSDK_AT_UART_CTRL__TXIRQEN__SHIFT 2 +#define CMSDK_AT_UART_CTRL__TXIRQEN__WIDTH 1 +#define CMSDK_AT_UART_CTRL__TXIRQEN__MASK 0x00000004U +#define CMSDK_AT_UART_CTRL_TXIRQEN_Pos CMSDK_AT_UART_CTRL__TXIRQEN__SHIFT +#define CMSDK_AT_UART_CTRL_TXIRQEN_Msk CMSDK_AT_UART_CTRL__TXIRQEN__MASK +#define CMSDK_UART_CTRL_TXIRQEN_Pos CMSDK_AT_UART_CTRL__TXIRQEN__SHIFT +#define CMSDK_UART_CTRL_TXIRQEN_Msk CMSDK_AT_UART_CTRL__TXIRQEN__MASK +#define CMSDK_AT_UART_CTRL__TXIRQEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define CMSDK_AT_UART_CTRL__TXIRQEN__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define CMSDK_AT_UART_CTRL__TXIRQEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define CMSDK_AT_UART_CTRL__TXIRQEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define CMSDK_AT_UART_CTRL__TXIRQEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define CMSDK_AT_UART_CTRL__TXIRQEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define CMSDK_AT_UART_CTRL__TXIRQEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field RxIntEn */ +/** + * @defgroup at_apb_uart_regs_core_RxIntEn_field RxIntEn_field + * @brief macros for field RxIntEn + * @details RX interrupt enable. + * @{ + */ +#define CMSDK_AT_UART_CTRL__RXIRQEN__SHIFT 3 +#define CMSDK_AT_UART_CTRL__RXIRQEN__WIDTH 1 +#define CMSDK_AT_UART_CTRL__RXIRQEN__MASK 0x00000008U +#define CMSDK_AT_UART_CTRL_RXIRQEN_Pos CMSDK_AT_UART_CTRL__RXIRQEN__SHIFT +#define CMSDK_AT_UART_CTRL_RXIRQEN_Msk CMSDK_AT_UART_CTRL__RXIRQEN__MASK +#define CMSDK_UART_CTRL_RXIRQEN_Pos CMSDK_AT_UART_CTRL__RXIRQEN__SHIFT +#define CMSDK_UART_CTRL_RXIRQEN_Msk CMSDK_AT_UART_CTRL__RXIRQEN__MASK +#define CMSDK_AT_UART_CTRL__RXIRQEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define CMSDK_AT_UART_CTRL__RXIRQEN__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define CMSDK_AT_UART_CTRL__RXIRQEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define CMSDK_AT_UART_CTRL__RXIRQEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define CMSDK_AT_UART_CTRL__RXIRQEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define CMSDK_AT_UART_CTRL__RXIRQEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define CMSDK_AT_UART_CTRL__RXIRQEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tx_overrun_int_en */ +/** + * @defgroup at_apb_uart_regs_core_tx_overrun_int_en_field tx_overrun_int_en_field + * @brief macros for field tx_overrun_int_en + * @details TX overrun interrupt enable. + * @{ + */ +#define CMSDK_AT_UART_CTRL__TXORIRQEN__SHIFT 4 +#define CMSDK_AT_UART_CTRL__TXORIRQEN__WIDTH 1 +#define CMSDK_AT_UART_CTRL__TXORIRQEN__MASK 0x00000010U +#define CMSDK_AT_UART_CTRL_TXORIRQEN_Pos CMSDK_AT_UART_CTRL__TXORIRQEN__SHIFT +#define CMSDK_AT_UART_CTRL_TXORIRQEN_Msk CMSDK_AT_UART_CTRL__TXORIRQEN__MASK +#define CMSDK_UART_CTRL_TXORIRQEN_Pos CMSDK_AT_UART_CTRL__TXORIRQEN__SHIFT +#define CMSDK_UART_CTRL_TXORIRQEN_Msk CMSDK_AT_UART_CTRL__TXORIRQEN__MASK +#define CMSDK_AT_UART_CTRL__TXORIRQEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define CMSDK_AT_UART_CTRL__TXORIRQEN__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define CMSDK_AT_UART_CTRL__TXORIRQEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define CMSDK_AT_UART_CTRL__TXORIRQEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define CMSDK_AT_UART_CTRL__TXORIRQEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define CMSDK_AT_UART_CTRL__TXORIRQEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define CMSDK_AT_UART_CTRL__TXORIRQEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_overrun_int_en */ +/** + * @defgroup at_apb_uart_regs_core_rx_overrun_int_en_field rx_overrun_int_en_field + * @brief macros for field rx_overrun_int_en + * @details RX overrun interrupt enable. + * @{ + */ +#define CMSDK_AT_UART_CTRL__RXORIRQEN__SHIFT 5 +#define CMSDK_AT_UART_CTRL__RXORIRQEN__WIDTH 1 +#define CMSDK_AT_UART_CTRL__RXORIRQEN__MASK 0x00000020U +#define CMSDK_AT_UART_CTRL_RXORIRQEN_Pos CMSDK_AT_UART_CTRL__RXORIRQEN__SHIFT +#define CMSDK_AT_UART_CTRL_RXORIRQEN_Msk CMSDK_AT_UART_CTRL__RXORIRQEN__MASK +#define CMSDK_UART_CTRL_RXORIRQEN_Pos CMSDK_AT_UART_CTRL__RXORIRQEN__SHIFT +#define CMSDK_UART_CTRL_RXORIRQEN_Msk CMSDK_AT_UART_CTRL__RXORIRQEN__MASK +#define CMSDK_AT_UART_CTRL__RXORIRQEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define CMSDK_AT_UART_CTRL__RXORIRQEN__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define CMSDK_AT_UART_CTRL__RXORIRQEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define CMSDK_AT_UART_CTRL__RXORIRQEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define CMSDK_AT_UART_CTRL__RXORIRQEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define CMSDK_AT_UART_CTRL__RXORIRQEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define CMSDK_AT_UART_CTRL__RXORIRQEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hs_testmode */ +/** + * @defgroup at_apb_uart_regs_core_hs_testmode_field hs_testmode_field + * @brief macros for field hs_testmode + * @details High-speed test mode for TX only. + * @{ + */ +#define CMSDK_AT_UART_CTRL__HSTM__SHIFT 6 +#define CMSDK_AT_UART_CTRL__HSTM__WIDTH 1 +#define CMSDK_AT_UART_CTRL__HSTM__MASK 0x00000040U +#define CMSDK_AT_UART_CTRL_HSTM_Pos CMSDK_AT_UART_CTRL__HSTM__SHIFT +#define CMSDK_AT_UART_CTRL_HSTM_Msk CMSDK_AT_UART_CTRL__HSTM__MASK +#define CMSDK_UART_CTRL_HSTM_Pos CMSDK_AT_UART_CTRL__HSTM__SHIFT +#define CMSDK_UART_CTRL_HSTM_Msk CMSDK_AT_UART_CTRL__HSTM__MASK +#define CMSDK_AT_UART_CTRL__HSTM__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define CMSDK_AT_UART_CTRL__HSTM__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define CMSDK_AT_UART_CTRL__HSTM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define CMSDK_AT_UART_CTRL__HSTM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define CMSDK_AT_UART_CTRL__HSTM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define CMSDK_AT_UART_CTRL__HSTM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define CMSDK_AT_UART_CTRL__HSTM__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dma_mode_tx */ +/** + * @defgroup at_apb_uart_regs_core_dma_mode_tx_field dma_mode_tx_field + * @brief macros for field dma_mode_tx + * @details 1= dma can fill the tx fifo and the tx_intr is cleared when full or done. + * @{ + */ +#define CMSDK_AT_UART_CTRL__DMAMTX__SHIFT 7 +#define CMSDK_AT_UART_CTRL__DMAMTX__WIDTH 1 +#define CMSDK_AT_UART_CTRL__DMAMTX__MASK 0x00000080U +#define CMSDK_AT_UART_CTRL_DMAMTX_Pos CMSDK_AT_UART_CTRL__DMAMTX__SHIFT +#define CMSDK_AT_UART_CTRL_DMAMTX_Msk CMSDK_AT_UART_CTRL__DMAMTX__MASK +#define CMSDK_UART_CTRL_DMAMTX_Pos CMSDK_AT_UART_CTRL__DMAMTX__SHIFT +#define CMSDK_UART_CTRL_DMAMTX_Msk CMSDK_AT_UART_CTRL__DMAMTX__MASK +#define CMSDK_AT_UART_CTRL__DMAMTX__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define CMSDK_AT_UART_CTRL__DMAMTX__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define CMSDK_AT_UART_CTRL__DMAMTX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define CMSDK_AT_UART_CTRL__DMAMTX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define CMSDK_AT_UART_CTRL__DMAMTX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define CMSDK_AT_UART_CTRL__DMAMTX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define CMSDK_AT_UART_CTRL__DMAMTX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dma_mode_rx */ +/** + * @defgroup at_apb_uart_regs_core_dma_mode_rx_field dma_mode_rx_field + * @brief macros for field dma_mode_rx + * @details 1= dma can drain the rx fifo and the rx_intr is cleared when empty + * @{ + */ +#define CMSDK_AT_UART_CTRL__DMAMRX__SHIFT 8 +#define CMSDK_AT_UART_CTRL__DMAMRX__WIDTH 1 +#define CMSDK_AT_UART_CTRL__DMAMRX__MASK 0x00000100U +#define CMSDK_AT_UART_CTRL_DMAMRX_Pos CMSDK_AT_UART_CTRL__DMAMRX__SHIFT +#define CMSDK_AT_UART_CTRL_DMAMRX_Msk CMSDK_AT_UART_CTRL__DMAMRX__MASK +#define CMSDK_UART_CTRL_DMAMRX_Pos CMSDK_AT_UART_CTRL__DMAMRX__SHIFT +#define CMSDK_UART_CTRL_DMAMRX_Msk CMSDK_AT_UART_CTRL__DMAMRX__MASK +#define CMSDK_AT_UART_CTRL__DMAMRX__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define CMSDK_AT_UART_CTRL__DMAMRX__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define CMSDK_AT_UART_CTRL__DMAMRX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define CMSDK_AT_UART_CTRL__DMAMRX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define CMSDK_AT_UART_CTRL__DMAMRX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define CMSDK_AT_UART_CTRL__DMAMRX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define CMSDK_AT_UART_CTRL__DMAMRX__RESET_VALUE 0x00000000U +/** @} */ +#define CMSDK_AT_UART_CTRL__TYPE uint32_t +#define CMSDK_AT_UART_CTRL__READ 0x000001ffU +#define CMSDK_AT_UART_CTRL__WRITE 0x000001ffU +#define CMSDK_AT_UART_CTRL__PRESERVED 0x00000000U +#define CMSDK_AT_UART_CTRL__RESET_VALUE 0x00000000U + +#endif /* __CMSDK_AT_UART_CTRL_MACRO__ */ + +/** @} end of CTRL */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_INTSTATUS_CLEAR */ +/** + * @defgroup at_apb_uart_regs_core_INTSTATUS_CLEAR INTSTATUS_CLEAR + * @brief Contains register fields associated with INTSTATUS_CLEAR. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_INTSTATUS_MACRO__ +#define __CMSDK_AT_UART_INTSTATUS_MACRO__ + +/* macros for field txintr */ +/** + * @defgroup at_apb_uart_regs_core_txintr_field txintr_field + * @brief macros for field txintr + * @details TX interrupt. Write 1 to clear. + * @{ + */ +#define CMSDK_AT_UART_INTSTATUS__TXIRQ__SHIFT 0 +#define CMSDK_AT_UART_INTSTATUS__TXIRQ__WIDTH 1 +#define CMSDK_AT_UART_INTSTATUS__TXIRQ__MASK 0x00000001U +#define CMSDK_AT_UART_INTSTATUS_TXIRQ_Pos CMSDK_AT_UART_INTSTATUS__TXIRQ__SHIFT +#define CMSDK_AT_UART_INTSTATUS_TXIRQ_Msk CMSDK_AT_UART_INTSTATUS__TXIRQ__MASK +#define CMSDK_UART_INTSTATUS_TXIRQ_Pos CMSDK_AT_UART_INTSTATUS__TXIRQ__SHIFT +#define CMSDK_UART_INTSTATUS_TXIRQ_Msk CMSDK_AT_UART_INTSTATUS__TXIRQ__MASK +#define CMSDK_AT_UART_INTSTATUS__TXIRQ__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CMSDK_AT_UART_INTSTATUS__TXIRQ__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CMSDK_AT_UART_INTSTATUS__TXIRQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define CMSDK_AT_UART_INTSTATUS__TXIRQ__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define CMSDK_AT_UART_INTSTATUS__TXIRQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define CMSDK_AT_UART_INTSTATUS__TXIRQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define CMSDK_AT_UART_INTSTATUS__TXIRQ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rxintr */ +/** + * @defgroup at_apb_uart_regs_core_rxintr_field rxintr_field + * @brief macros for field rxintr + * @details RX interrupt. Write 1 to clear. + * @{ + */ +#define CMSDK_AT_UART_INTSTATUS__RXIRQ__SHIFT 1 +#define CMSDK_AT_UART_INTSTATUS__RXIRQ__WIDTH 1 +#define CMSDK_AT_UART_INTSTATUS__RXIRQ__MASK 0x00000002U +#define CMSDK_AT_UART_INTSTATUS_RXIRQ_Pos CMSDK_AT_UART_INTSTATUS__RXIRQ__SHIFT +#define CMSDK_AT_UART_INTSTATUS_RXIRQ_Msk CMSDK_AT_UART_INTSTATUS__RXIRQ__MASK +#define CMSDK_UART_INTSTATUS_RXIRQ_Pos CMSDK_AT_UART_INTSTATUS__RXIRQ__SHIFT +#define CMSDK_UART_INTSTATUS_RXIRQ_Msk CMSDK_AT_UART_INTSTATUS__RXIRQ__MASK +#define CMSDK_AT_UART_INTSTATUS__RXIRQ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define CMSDK_AT_UART_INTSTATUS__RXIRQ__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define CMSDK_AT_UART_INTSTATUS__RXIRQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define CMSDK_AT_UART_INTSTATUS__RXIRQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define CMSDK_AT_UART_INTSTATUS__RXIRQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define CMSDK_AT_UART_INTSTATUS__RXIRQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define CMSDK_AT_UART_INTSTATUS__RXIRQ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tx_overflow_intr */ +/** + * @defgroup at_apb_uart_regs_core_tx_overflow_intr_field tx_overflow_intr_field + * @brief macros for field tx_overflow_intr + * @details TX overrun interrupt. Write 1 to clear. + * @{ + */ +#define CMSDK_AT_UART_INTSTATUS__TXORIRQ__SHIFT 2 +#define CMSDK_AT_UART_INTSTATUS__TXORIRQ__WIDTH 1 +#define CMSDK_AT_UART_INTSTATUS__TXORIRQ__MASK 0x00000004U +#define CMSDK_AT_UART_INTSTATUS_TXORIRQ_Pos \ + CMSDK_AT_UART_INTSTATUS__TXORIRQ__SHIFT +#define CMSDK_AT_UART_INTSTATUS_TXORIRQ_Msk \ + CMSDK_AT_UART_INTSTATUS__TXORIRQ__MASK +#define CMSDK_UART_INTSTATUS_TXORIRQ_Pos \ + CMSDK_AT_UART_INTSTATUS__TXORIRQ__SHIFT +#define CMSDK_UART_INTSTATUS_TXORIRQ_Msk CMSDK_AT_UART_INTSTATUS__TXORIRQ__MASK +#define CMSDK_AT_UART_INTSTATUS__TXORIRQ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define CMSDK_AT_UART_INTSTATUS__TXORIRQ__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define CMSDK_AT_UART_INTSTATUS__TXORIRQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define CMSDK_AT_UART_INTSTATUS__TXORIRQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define CMSDK_AT_UART_INTSTATUS__TXORIRQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define CMSDK_AT_UART_INTSTATUS__TXORIRQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define CMSDK_AT_UART_INTSTATUS__TXORIRQ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_overflow_intr */ +/** + * @defgroup at_apb_uart_regs_core_rx_overflow_intr_field rx_overflow_intr_field + * @brief macros for field rx_overflow_intr + * @details RX overrun interrupt. Write 1 to clear. + * @{ + */ +#define CMSDK_AT_UART_INTSTATUS__RXORIRQ__SHIFT 3 +#define CMSDK_AT_UART_INTSTATUS__RXORIRQ__WIDTH 1 +#define CMSDK_AT_UART_INTSTATUS__RXORIRQ__MASK 0x00000008U +#define CMSDK_AT_UART_INTSTATUS_RXORIRQ_Pos \ + CMSDK_AT_UART_INTSTATUS__RXORIRQ__SHIFT +#define CMSDK_AT_UART_INTSTATUS_RXORIRQ_Msk \ + CMSDK_AT_UART_INTSTATUS__RXORIRQ__MASK +#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos \ + CMSDK_AT_UART_INTSTATUS__RXORIRQ__SHIFT +#define CMSDK_UART_INTSTATUS_RXORIRQ_Msk CMSDK_AT_UART_INTSTATUS__RXORIRQ__MASK +#define CMSDK_AT_UART_INTSTATUS__RXORIRQ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define CMSDK_AT_UART_INTSTATUS__RXORIRQ__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define CMSDK_AT_UART_INTSTATUS__RXORIRQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define CMSDK_AT_UART_INTSTATUS__RXORIRQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define CMSDK_AT_UART_INTSTATUS__RXORIRQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define CMSDK_AT_UART_INTSTATUS__RXORIRQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define CMSDK_AT_UART_INTSTATUS__RXORIRQ__RESET_VALUE 0x00000000U +/** @} */ +#define CMSDK_AT_UART_INTSTATUS__TYPE uint32_t +#define CMSDK_AT_UART_INTSTATUS__READ 0x0000000fU +#define CMSDK_AT_UART_INTSTATUS__WRITE 0x0000000fU +#define CMSDK_AT_UART_INTSTATUS__PRESERVED 0x00000000U +#define CMSDK_AT_UART_INTSTATUS__RESET_VALUE 0x00000000U + +#endif /* __CMSDK_AT_UART_INTSTATUS_MACRO__ */ + +/** @} end of INTSTATUS_CLEAR */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_BAUDDIV */ +/** + * @defgroup at_apb_uart_regs_core_BAUDDIV BAUDDIV + * @brief Contains register fields associated with BAUDDIV. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_BAUDDIV_MACRO__ +#define __CMSDK_AT_UART_BAUDDIV_MACRO__ + +/* macros for field baud_div */ +/** + * @defgroup at_apb_uart_regs_core_baud_div_field baud_div_field + * @brief macros for field baud_div + * @details Baud rate divider. The minimum number is 8. + * @{ + */ +#define CMSDK_AT_UART_BAUDDIV__BAUD_DIV__SHIFT 0 +#define CMSDK_AT_UART_BAUDDIV__BAUD_DIV__WIDTH 20 +#define CMSDK_AT_UART_BAUDDIV__BAUD_DIV__MASK 0x000fffffU +#define CMSDK_AT_UART_BAUDDIV_Pos CMSDK_AT_UART_BAUDDIV__BAUD_DIV__SHIFT +#define CMSDK_AT_UART_BAUDDIV_Msk CMSDK_AT_UART_BAUDDIV__BAUD_DIV__MASK +#define CMSDK_UART_BAUDDIV_Pos CMSDK_AT_UART_BAUDDIV__BAUD_DIV__SHIFT +#define CMSDK_UART_BAUDDIV_Msk CMSDK_AT_UART_BAUDDIV__BAUD_DIV__MASK +#define CMSDK_AT_UART_BAUDDIV__BAUD_DIV__READ(src) \ + ((uint32_t)(src)\ + & 0x000fffffU) +#define CMSDK_AT_UART_BAUDDIV__BAUD_DIV__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000fffffU) +#define CMSDK_AT_UART_BAUDDIV__BAUD_DIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fffffU) | ((uint32_t)(src) &\ + 0x000fffffU) +#define CMSDK_AT_UART_BAUDDIV__BAUD_DIV__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000fffffU))) +#define CMSDK_AT_UART_BAUDDIV__BAUD_DIV__RESET_VALUE 0x00000000U +/** @} */ +#define CMSDK_AT_UART_BAUDDIV__TYPE uint32_t +#define CMSDK_AT_UART_BAUDDIV__READ 0x000fffffU +#define CMSDK_AT_UART_BAUDDIV__WRITE 0x000fffffU +#define CMSDK_AT_UART_BAUDDIV__PRESERVED 0x00000000U +#define CMSDK_AT_UART_BAUDDIV__RESET_VALUE 0x00000000U + +#endif /* __CMSDK_AT_UART_BAUDDIV_MACRO__ */ + +/** @} end of BAUDDIV */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_RX_LWM */ +/** + * @defgroup at_apb_uart_regs_core_RX_LWM RX_LWM + * @brief Contains register fields associated with RX_LWM. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_RX_LWM_MACRO__ +#define __CMSDK_AT_UART_RX_LWM_MACRO__ + +/* macros for field Rx_LWM */ +/** + * @defgroup at_apb_uart_regs_core_Rx_LWM_field Rx_LWM_field + * @brief macros for field Rx_LWM + * @details low water mark of RX FIFO; a trigger is issued when (Atmosic) RX FIFO has waited long enough to have received these many items, starting from the first item. Constraint: ( 1<= RX_LWM <= 14) + * @{ + */ +#define CMSDK_AT_UART_RX_LWM__RX_LWM__SHIFT 0 +#define CMSDK_AT_UART_RX_LWM__RX_LWM__WIDTH 5 +#define CMSDK_AT_UART_RX_LWM__RX_LWM__MASK 0x0000001fU +#define CMSDK_AT_UART_RX_LWM_Pos CMSDK_AT_UART_RX_LWM__RX_LWM__SHIFT +#define CMSDK_AT_UART_RX_LWM_Msk CMSDK_AT_UART_RX_LWM__RX_LWM__MASK +#define CMSDK_UART_RX_LWM_Pos CMSDK_AT_UART_RX_LWM__RX_LWM__SHIFT +#define CMSDK_UART_RX_LWM_Msk CMSDK_AT_UART_RX_LWM__RX_LWM__MASK +#define CMSDK_AT_UART_RX_LWM__RX_LWM__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define CMSDK_AT_UART_RX_LWM__RX_LWM__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define CMSDK_AT_UART_RX_LWM__RX_LWM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define CMSDK_AT_UART_RX_LWM__RX_LWM__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define CMSDK_AT_UART_RX_LWM__RX_LWM__RESET_VALUE 0x00000001U +/** @} */ +#define CMSDK_AT_UART_RX_LWM__TYPE uint32_t +#define CMSDK_AT_UART_RX_LWM__READ 0x0000001fU +#define CMSDK_AT_UART_RX_LWM__WRITE 0x0000001fU +#define CMSDK_AT_UART_RX_LWM__PRESERVED 0x00000000U +#define CMSDK_AT_UART_RX_LWM__RESET_VALUE 0x00000001U + +#endif /* __CMSDK_AT_UART_RX_LWM_MACRO__ */ + +/** @} end of RX_LWM */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_TX_LWM */ +/** + * @defgroup at_apb_uart_regs_core_TX_LWM TX_LWM + * @brief Contains register fields associated with TX_LWM. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_TX_LWM_MACRO__ +#define __CMSDK_AT_UART_TX_LWM_MACRO__ + +/* macros for field Tx_LWM */ +/** + * @defgroup at_apb_uart_regs_core_Tx_LWM_field Tx_LWM_field + * @brief macros for field Tx_LWM + * @details low water mark of TX FIF0; a trigger is issued when (Atmosic) tX FIFO is drained to these many unoccupied slots. Constraint (1<= TX_LWM <= 16) + * @{ + */ +#define CMSDK_AT_UART_TX_LWM__TX_LWM__SHIFT 0 +#define CMSDK_AT_UART_TX_LWM__TX_LWM__WIDTH 5 +#define CMSDK_AT_UART_TX_LWM__TX_LWM__MASK 0x0000001fU +#define CMSDK_AT_UART_TX_LWM_Pos CMSDK_AT_UART_TX_LWM__TX_LWM__SHIFT +#define CMSDK_AT_UART_TX_LWM_Msk CMSDK_AT_UART_TX_LWM__TX_LWM__MASK +#define CMSDK_UART_TX_LWM_Pos CMSDK_AT_UART_TX_LWM__TX_LWM__SHIFT +#define CMSDK_UART_TX_LWM_Msk CMSDK_AT_UART_TX_LWM__TX_LWM__MASK +#define CMSDK_AT_UART_TX_LWM__TX_LWM__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define CMSDK_AT_UART_TX_LWM__TX_LWM__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define CMSDK_AT_UART_TX_LWM__TX_LWM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define CMSDK_AT_UART_TX_LWM__TX_LWM__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define CMSDK_AT_UART_TX_LWM__TX_LWM__RESET_VALUE 0x00000010U +/** @} */ +#define CMSDK_AT_UART_TX_LWM__TYPE uint32_t +#define CMSDK_AT_UART_TX_LWM__READ 0x0000001fU +#define CMSDK_AT_UART_TX_LWM__WRITE 0x0000001fU +#define CMSDK_AT_UART_TX_LWM__PRESERVED 0x00000000U +#define CMSDK_AT_UART_TX_LWM__RESET_VALUE 0x00000010U + +#endif /* __CMSDK_AT_UART_TX_LWM_MACRO__ */ + +/** @} end of TX_LWM */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_RX_FIFO_SPACES */ +/** + * @defgroup at_apb_uart_regs_core_RX_FIFO_SPACES RX_FIFO_SPACES + * @brief Contains register fields associated with RX_FIFO_SPACES. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_RX_FIFO_SPACES_MACRO__ +#define __CMSDK_AT_UART_RX_FIFO_SPACES_MACRO__ + +/* macros for field rx_fifo_spaces */ +/** + * @defgroup at_apb_uart_regs_core_rx_fifo_spaces_field rx_fifo_spaces_field + * @brief macros for field rx_fifo_spaces + * @details number of unoccupied spaces in RX_FIFO (Atmosic) + * @{ + */ +#define CMSDK_AT_UART_RX_FIFO_SPACES__RX_FIFO_SPACES__SHIFT 0 +#define CMSDK_AT_UART_RX_FIFO_SPACES__RX_FIFO_SPACES__WIDTH 5 +#define CMSDK_AT_UART_RX_FIFO_SPACES__RX_FIFO_SPACES__MASK 0x0000001fU +#define CMSDK_AT_UART_RX_FIFO_SPACES_Pos \ + CMSDK_AT_UART_RX_FIFO_SPACES__RX_FIFO_SPACES__SHIFT +#define CMSDK_AT_UART_RX_FIFO_SPACES_Msk \ + CMSDK_AT_UART_RX_FIFO_SPACES__RX_FIFO_SPACES__MASK +#define CMSDK_UART_RX_FIFO_SPACES_Pos \ + CMSDK_AT_UART_RX_FIFO_SPACES__RX_FIFO_SPACES__SHIFT +#define CMSDK_UART_RX_FIFO_SPACES_Msk \ + CMSDK_AT_UART_RX_FIFO_SPACES__RX_FIFO_SPACES__MASK +#define CMSDK_AT_UART_RX_FIFO_SPACES__RX_FIFO_SPACES__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define CMSDK_AT_UART_RX_FIFO_SPACES__RX_FIFO_SPACES__RESET_VALUE 0x00000010U +/** @} */ +#define CMSDK_AT_UART_RX_FIFO_SPACES__TYPE uint32_t +#define CMSDK_AT_UART_RX_FIFO_SPACES__READ 0x0000001fU +#define CMSDK_AT_UART_RX_FIFO_SPACES__PRESERVED 0x00000000U +#define CMSDK_AT_UART_RX_FIFO_SPACES__RESET_VALUE 0x00000010U + +#endif /* __CMSDK_AT_UART_RX_FIFO_SPACES_MACRO__ */ + +/** @} end of RX_FIFO_SPACES */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_TX_FIFO_SPACES */ +/** + * @defgroup at_apb_uart_regs_core_TX_FIFO_SPACES TX_FIFO_SPACES + * @brief Contains register fields associated with TX_FIFO_SPACES. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_TX_FIFO_SPACES_MACRO__ +#define __CMSDK_AT_UART_TX_FIFO_SPACES_MACRO__ + +/* macros for field tx_fifo_spaces */ +/** + * @defgroup at_apb_uart_regs_core_tx_fifo_spaces_field tx_fifo_spaces_field + * @brief macros for field tx_fifo_spaces + * @details number of unoccupied spaces in TX_FIFO (Atmosic) + * @{ + */ +#define CMSDK_AT_UART_TX_FIFO_SPACES__TX_FIFO_SPACES__SHIFT 0 +#define CMSDK_AT_UART_TX_FIFO_SPACES__TX_FIFO_SPACES__WIDTH 5 +#define CMSDK_AT_UART_TX_FIFO_SPACES__TX_FIFO_SPACES__MASK 0x0000001fU +#define CMSDK_AT_UART_TX_FIFO_SPACES_Pos \ + CMSDK_AT_UART_TX_FIFO_SPACES__TX_FIFO_SPACES__SHIFT +#define CMSDK_AT_UART_TX_FIFO_SPACES_Msk \ + CMSDK_AT_UART_TX_FIFO_SPACES__TX_FIFO_SPACES__MASK +#define CMSDK_UART_TX_FIFO_SPACES_Pos \ + CMSDK_AT_UART_TX_FIFO_SPACES__TX_FIFO_SPACES__SHIFT +#define CMSDK_UART_TX_FIFO_SPACES_Msk \ + CMSDK_AT_UART_TX_FIFO_SPACES__TX_FIFO_SPACES__MASK +#define CMSDK_AT_UART_TX_FIFO_SPACES__TX_FIFO_SPACES__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define CMSDK_AT_UART_TX_FIFO_SPACES__TX_FIFO_SPACES__RESET_VALUE 0x00000010U +/** @} */ +#define CMSDK_AT_UART_TX_FIFO_SPACES__TYPE uint32_t +#define CMSDK_AT_UART_TX_FIFO_SPACES__READ 0x0000001fU +#define CMSDK_AT_UART_TX_FIFO_SPACES__PRESERVED 0x00000000U +#define CMSDK_AT_UART_TX_FIFO_SPACES__RESET_VALUE 0x00000010U + +#endif /* __CMSDK_AT_UART_TX_FIFO_SPACES_MACRO__ */ + +/** @} end of TX_FIFO_SPACES */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_HW_FLOW_OVRD */ +/** + * @defgroup at_apb_uart_regs_core_HW_FLOW_OVRD HW_FLOW_OVRD + * @brief Contains register fields associated with HW_FLOW_OVRD. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_HW_FLOW_OVRD_MACRO__ +#define __CMSDK_AT_UART_HW_FLOW_OVRD_MACRO__ + +/* macros for field nRTS_VAL */ +/** + * @defgroup at_apb_uart_regs_core_nRTS_VAL_field nRTS_VAL_field + * @brief macros for field nRTS_VAL + * @details 0(default) = nRTS is asserted to enable external TX; 1= nRTS is deasserted + * @{ + */ +#define CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_VAL__SHIFT 0 +#define CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_VAL__WIDTH 1 +#define CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_VAL__MASK 0x00000001U +#define CMSDK_AT_UART_HW_FLOW_OVRD_NRTS_VAL_Pos \ + CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_VAL__SHIFT +#define CMSDK_AT_UART_HW_FLOW_OVRD_NRTS_VAL_Msk \ + CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_VAL__MASK +#define CMSDK_UART_HW_FLOW_OVRD_NRTS_VAL_Pos \ + CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_VAL__SHIFT +#define CMSDK_UART_HW_FLOW_OVRD_NRTS_VAL_Msk \ + CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_VAL__MASK +#define CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_VAL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_VAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nRTS_OVRD */ +/** + * @defgroup at_apb_uart_regs_core_nRTS_OVRD_field nRTS_OVRD_field + * @brief macros for field nRTS_OVRD + * @details 0= nUARTRTS override override disabled; 1(default)= nUARTRTS override enabled ;(Atmosic) + * @{ + */ +#define CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_OVRD__SHIFT 1 +#define CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_OVRD__WIDTH 1 +#define CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_OVRD__MASK 0x00000002U +#define CMSDK_AT_UART_HW_FLOW_OVRD_NRTS_OVRD_Pos \ + CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_OVRD__SHIFT +#define CMSDK_AT_UART_HW_FLOW_OVRD_NRTS_OVRD_Msk \ + CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_OVRD__MASK +#define CMSDK_UART_HW_FLOW_OVRD_NRTS_OVRD_Pos \ + CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_OVRD__SHIFT +#define CMSDK_UART_HW_FLOW_OVRD_NRTS_OVRD_Msk \ + CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_OVRD__MASK +#define CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_OVRD__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_OVRD__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_OVRD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NRTS_OVRD__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field nCTS_VAL */ +/** + * @defgroup at_apb_uart_regs_core_nCTS_VAL_field nCTS_VAL_field + * @brief macros for field nCTS_VAL + * @details 0(default) = nCTS is asserted to enable TX; 1= nCTS is deasserted + * @{ + */ +#define CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_VAL__SHIFT 2 +#define CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_VAL__WIDTH 1 +#define CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_VAL__MASK 0x00000004U +#define CMSDK_AT_UART_HW_FLOW_OVRD_NCTS_VAL_Pos \ + CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_VAL__SHIFT +#define CMSDK_AT_UART_HW_FLOW_OVRD_NCTS_VAL_Msk \ + CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_VAL__MASK +#define CMSDK_UART_HW_FLOW_OVRD_NCTS_VAL_Pos \ + CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_VAL__SHIFT +#define CMSDK_UART_HW_FLOW_OVRD_NCTS_VAL_Msk \ + CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_VAL__MASK +#define CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nCTS_OVRD */ +/** + * @defgroup at_apb_uart_regs_core_nCTS_OVRD_field nCTS_OVRD_field + * @brief macros for field nCTS_OVRD + * @details 0= nUARTCTS override override disabled; 1(default)= nUARTCTS override enabled (Atmosic) + * @{ + */ +#define CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_OVRD__SHIFT 3 +#define CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_OVRD__WIDTH 1 +#define CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_OVRD__MASK 0x00000008U +#define CMSDK_AT_UART_HW_FLOW_OVRD_NCTS_OVRD_Pos \ + CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_OVRD__SHIFT +#define CMSDK_AT_UART_HW_FLOW_OVRD_NCTS_OVRD_Msk \ + CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_OVRD__MASK +#define CMSDK_UART_HW_FLOW_OVRD_NCTS_OVRD_Pos \ + CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_OVRD__SHIFT +#define CMSDK_UART_HW_FLOW_OVRD_NCTS_OVRD_Msk \ + CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_OVRD__MASK +#define CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_OVRD__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_OVRD__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_OVRD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define CMSDK_AT_UART_HW_FLOW_OVRD__NCTS_OVRD__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field RTS_TRIG_LVL */ +/** + * @defgroup at_apb_uart_regs_core_RTS_TRIG_LVL_field RTS_TRIG_LVL_field + * @brief macros for field RTS_TRIG_LVL + * @details threshold of rx fifo to de-assert nRTS. The value corresponds to the number of open spaces in RX fifo. minimum programmable value is 2. + * @{ + */ +#define CMSDK_AT_UART_HW_FLOW_OVRD__RTS_TRIG_LVL__SHIFT 4 +#define CMSDK_AT_UART_HW_FLOW_OVRD__RTS_TRIG_LVL__WIDTH 3 +#define CMSDK_AT_UART_HW_FLOW_OVRD__RTS_TRIG_LVL__MASK 0x00000070U +#define CMSDK_AT_UART_HW_FLOW_OVRD_RTS_TRIG_LVL_Pos \ + CMSDK_AT_UART_HW_FLOW_OVRD__RTS_TRIG_LVL__SHIFT +#define CMSDK_AT_UART_HW_FLOW_OVRD_RTS_TRIG_LVL_Msk \ + CMSDK_AT_UART_HW_FLOW_OVRD__RTS_TRIG_LVL__MASK +#define CMSDK_UART_HW_FLOW_OVRD_RTS_TRIG_LVL_Pos \ + CMSDK_AT_UART_HW_FLOW_OVRD__RTS_TRIG_LVL__SHIFT +#define CMSDK_UART_HW_FLOW_OVRD_RTS_TRIG_LVL_Msk \ + CMSDK_AT_UART_HW_FLOW_OVRD__RTS_TRIG_LVL__MASK +#define CMSDK_AT_UART_HW_FLOW_OVRD__RTS_TRIG_LVL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000070U) >> 4) +#define CMSDK_AT_UART_HW_FLOW_OVRD__RTS_TRIG_LVL__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000070U) +#define CMSDK_AT_UART_HW_FLOW_OVRD__RTS_TRIG_LVL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((uint32_t)(src) <<\ + 4) & 0x00000070U) +#define CMSDK_AT_UART_HW_FLOW_OVRD__RTS_TRIG_LVL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000070U))) +#define CMSDK_AT_UART_HW_FLOW_OVRD__RTS_TRIG_LVL__RESET_VALUE 0x00000002U +/** @} */ +#define CMSDK_AT_UART_HW_FLOW_OVRD__TYPE uint32_t +#define CMSDK_AT_UART_HW_FLOW_OVRD__READ 0x0000007fU +#define CMSDK_AT_UART_HW_FLOW_OVRD__WRITE 0x0000007fU +#define CMSDK_AT_UART_HW_FLOW_OVRD__PRESERVED 0x00000000U +#define CMSDK_AT_UART_HW_FLOW_OVRD__RESET_VALUE 0x0000002aU + +#endif /* __CMSDK_AT_UART_HW_FLOW_OVRD_MACRO__ */ + +/** @} end of HW_FLOW_OVRD */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_BAUD_RATE_DETECT */ +/** + * @defgroup at_apb_uart_regs_core_BAUD_RATE_DETECT BAUD_RATE_DETECT + * @brief Contains register fields associated with BAUD_RATE_DETECT. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_BAUD_RATE_DETECT_MACRO__ +#define __CMSDK_AT_UART_BAUD_RATE_DETECT_MACRO__ + +/* macros for field brd */ +/** + * @defgroup at_apb_uart_regs_core_brd_field brd_field + * @brief macros for field brd + * @details 1=set by SW, HW treat the next frame/s as baud rate detection byte, cleared by HW once baud rate is detected. 0=normal mode + * @{ + */ +#define CMSDK_AT_UART_BAUD_RATE_DETECT__BRD__SHIFT 0 +#define CMSDK_AT_UART_BAUD_RATE_DETECT__BRD__WIDTH 1 +#define CMSDK_AT_UART_BAUD_RATE_DETECT__BRD__MASK 0x00000001U +#define CMSDK_AT_UART_BAUD_RATE_DETECT_Pos \ + CMSDK_AT_UART_BAUD_RATE_DETECT__BRD__SHIFT +#define CMSDK_AT_UART_BAUD_RATE_DETECT_Msk \ + CMSDK_AT_UART_BAUD_RATE_DETECT__BRD__MASK +#define CMSDK_UART_BAUD_RATE_DETECT_Pos \ + CMSDK_AT_UART_BAUD_RATE_DETECT__BRD__SHIFT +#define CMSDK_UART_BAUD_RATE_DETECT_Msk \ + CMSDK_AT_UART_BAUD_RATE_DETECT__BRD__MASK +#define CMSDK_AT_UART_BAUD_RATE_DETECT__BRD__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CMSDK_AT_UART_BAUD_RATE_DETECT__BRD__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CMSDK_AT_UART_BAUD_RATE_DETECT__BRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define CMSDK_AT_UART_BAUD_RATE_DETECT__BRD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define CMSDK_AT_UART_BAUD_RATE_DETECT__BRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define CMSDK_AT_UART_BAUD_RATE_DETECT__BRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define CMSDK_AT_UART_BAUD_RATE_DETECT__BRD__RESET_VALUE 0x00000000U +/** @} */ +#define CMSDK_AT_UART_BAUD_RATE_DETECT__TYPE uint32_t +#define CMSDK_AT_UART_BAUD_RATE_DETECT__READ 0x00000001U +#define CMSDK_AT_UART_BAUD_RATE_DETECT__WRITE 0x00000001U +#define CMSDK_AT_UART_BAUD_RATE_DETECT__PRESERVED 0x00000000U +#define CMSDK_AT_UART_BAUD_RATE_DETECT__RESET_VALUE 0x00000000U + +#endif /* __CMSDK_AT_UART_BAUD_RATE_DETECT_MACRO__ */ + +/** @} end of BAUD_RATE_DETECT */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_BAUD_DIV_CEIL */ +/** + * @defgroup at_apb_uart_regs_core_BAUD_DIV_CEIL BAUD_DIV_CEIL + * @brief Contains register fields associated with BAUD_DIV_CEIL. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_BAUD_DIV_CEIL_MACRO__ +#define __CMSDK_AT_UART_BAUD_DIV_CEIL_MACRO__ + +/* macros for field bauddiv_ceil */ +/** + * @defgroup at_apb_uart_regs_core_bauddiv_ceil_field bauddiv_ceil_field + * @brief macros for field bauddiv_ceil + * @details sets max reference for baud rate in auto detection. Auto detection restarts if start bit is not detected within this window. + * @{ + */ +#define CMSDK_AT_UART_BAUD_DIV_CEIL__BAUDDIV_CEIL__SHIFT 0 +#define CMSDK_AT_UART_BAUD_DIV_CEIL__BAUDDIV_CEIL__WIDTH 20 +#define CMSDK_AT_UART_BAUD_DIV_CEIL__BAUDDIV_CEIL__MASK 0x000fffffU +#define CMSDK_AT_UART_BAUD_DIV_CEIL_Pos \ + CMSDK_AT_UART_BAUD_DIV_CEIL__BAUDDIV_CEIL__SHIFT +#define CMSDK_AT_UART_BAUD_DIV_CEIL_Msk \ + CMSDK_AT_UART_BAUD_DIV_CEIL__BAUDDIV_CEIL__MASK +#define CMSDK_UART_BAUD_DIV_CEIL_Pos \ + CMSDK_AT_UART_BAUD_DIV_CEIL__BAUDDIV_CEIL__SHIFT +#define CMSDK_UART_BAUD_DIV_CEIL_Msk \ + CMSDK_AT_UART_BAUD_DIV_CEIL__BAUDDIV_CEIL__MASK +#define CMSDK_AT_UART_BAUD_DIV_CEIL__BAUDDIV_CEIL__READ(src) \ + ((uint32_t)(src)\ + & 0x000fffffU) +#define CMSDK_AT_UART_BAUD_DIV_CEIL__BAUDDIV_CEIL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000fffffU) +#define CMSDK_AT_UART_BAUD_DIV_CEIL__BAUDDIV_CEIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fffffU) | ((uint32_t)(src) &\ + 0x000fffffU) +#define CMSDK_AT_UART_BAUD_DIV_CEIL__BAUDDIV_CEIL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000fffffU))) +#define CMSDK_AT_UART_BAUD_DIV_CEIL__BAUDDIV_CEIL__RESET_VALUE 0x000fffffU +/** @} */ +#define CMSDK_AT_UART_BAUD_DIV_CEIL__TYPE uint32_t +#define CMSDK_AT_UART_BAUD_DIV_CEIL__READ 0x000fffffU +#define CMSDK_AT_UART_BAUD_DIV_CEIL__WRITE 0x000fffffU +#define CMSDK_AT_UART_BAUD_DIV_CEIL__PRESERVED 0x00000000U +#define CMSDK_AT_UART_BAUD_DIV_CEIL__RESET_VALUE 0x000fffffU + +#endif /* __CMSDK_AT_UART_BAUD_DIV_CEIL_MACRO__ */ + +/** @} end of BAUD_DIV_CEIL */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_BRD_STAT */ +/** + * @defgroup at_apb_uart_regs_core_BRD_STAT BRD_STAT + * @brief Contains register fields associated with BRD_STAT. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_BRD_STAT_MACRO__ +#define __CMSDK_AT_UART_BRD_STAT_MACRO__ + +/* macros for field on_going */ +/** + * @defgroup at_apb_uart_regs_core_on_going_field on_going_field + * @brief macros for field on_going + * @details auto detection is on going + * @{ + */ +#define CMSDK_AT_UART_BRD_STAT__ON_GOING__SHIFT 0 +#define CMSDK_AT_UART_BRD_STAT__ON_GOING__WIDTH 1 +#define CMSDK_AT_UART_BRD_STAT__ON_GOING__MASK 0x00000001U +#define CMSDK_AT_UART_BRD_STAT_ON_GOING_Pos \ + CMSDK_AT_UART_BRD_STAT__ON_GOING__SHIFT +#define CMSDK_AT_UART_BRD_STAT_ON_GOING_Msk \ + CMSDK_AT_UART_BRD_STAT__ON_GOING__MASK +#define CMSDK_UART_BRD_STAT_ON_GOING_Pos \ + CMSDK_AT_UART_BRD_STAT__ON_GOING__SHIFT +#define CMSDK_UART_BRD_STAT_ON_GOING_Msk CMSDK_AT_UART_BRD_STAT__ON_GOING__MASK +#define CMSDK_AT_UART_BRD_STAT__ON_GOING__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CMSDK_AT_UART_BRD_STAT__ON_GOING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define CMSDK_AT_UART_BRD_STAT__ON_GOING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define CMSDK_AT_UART_BRD_STAT__ON_GOING__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field start_bit_timeout */ +/** + * @defgroup at_apb_uart_regs_core_start_bit_timeout_field start_bit_timeout_field + * @brief macros for field start_bit_timeout + * @details Previous synch bit too long. The calibration restarts after timeout. + * @{ + */ +#define CMSDK_AT_UART_BRD_STAT__START_BIT_TIMEOUT__SHIFT 1 +#define CMSDK_AT_UART_BRD_STAT__START_BIT_TIMEOUT__WIDTH 1 +#define CMSDK_AT_UART_BRD_STAT__START_BIT_TIMEOUT__MASK 0x00000002U +#define CMSDK_AT_UART_BRD_STAT_START_BIT_TIMEOUT_Pos \ + CMSDK_AT_UART_BRD_STAT__START_BIT_TIMEOUT__SHIFT +#define CMSDK_AT_UART_BRD_STAT_START_BIT_TIMEOUT_Msk \ + CMSDK_AT_UART_BRD_STAT__START_BIT_TIMEOUT__MASK +#define CMSDK_UART_BRD_STAT_START_BIT_TIMEOUT_Pos \ + CMSDK_AT_UART_BRD_STAT__START_BIT_TIMEOUT__SHIFT +#define CMSDK_UART_BRD_STAT_START_BIT_TIMEOUT_Msk \ + CMSDK_AT_UART_BRD_STAT__START_BIT_TIMEOUT__MASK +#define CMSDK_AT_UART_BRD_STAT__START_BIT_TIMEOUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define CMSDK_AT_UART_BRD_STAT__START_BIT_TIMEOUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define CMSDK_AT_UART_BRD_STAT__START_BIT_TIMEOUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define CMSDK_AT_UART_BRD_STAT__START_BIT_TIMEOUT__RESET_VALUE 0x00000000U +/** @} */ +#define CMSDK_AT_UART_BRD_STAT__TYPE uint32_t +#define CMSDK_AT_UART_BRD_STAT__READ 0x00000003U +#define CMSDK_AT_UART_BRD_STAT__PRESERVED 0x00000000U +#define CMSDK_AT_UART_BRD_STAT__RESET_VALUE 0x00000000U + +#endif /* __CMSDK_AT_UART_BRD_STAT_MACRO__ */ + +/** @} end of BRD_STAT */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_INTMASK */ +/** + * @defgroup at_apb_uart_regs_core_INTMASK INTMASK + * @brief Contains register fields associated with INTMASK. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_INTMASK_MACRO__ +#define __CMSDK_AT_UART_INTMASK_MACRO__ + +/* macros for field txint_en */ +/** + * @defgroup at_apb_uart_regs_core_txint_en_field txint_en_field + * @brief macros for field txint_en + * @details mask enable for TX interrupt. + * @{ + */ +#define CMSDK_AT_UART_INTMASK__TXINT_EN__SHIFT 0 +#define CMSDK_AT_UART_INTMASK__TXINT_EN__WIDTH 1 +#define CMSDK_AT_UART_INTMASK__TXINT_EN__MASK 0x00000001U +#define CMSDK_AT_UART_INTMASK_TXINT_EN_Pos \ + CMSDK_AT_UART_INTMASK__TXINT_EN__SHIFT +#define CMSDK_AT_UART_INTMASK_TXINT_EN_Msk \ + CMSDK_AT_UART_INTMASK__TXINT_EN__MASK +#define CMSDK_UART_INTMASK_TXINT_EN_Pos CMSDK_AT_UART_INTMASK__TXINT_EN__SHIFT +#define CMSDK_UART_INTMASK_TXINT_EN_Msk CMSDK_AT_UART_INTMASK__TXINT_EN__MASK +#define CMSDK_AT_UART_INTMASK__TXINT_EN__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CMSDK_AT_UART_INTMASK__TXINT_EN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CMSDK_AT_UART_INTMASK__TXINT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define CMSDK_AT_UART_INTMASK__TXINT_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define CMSDK_AT_UART_INTMASK__TXINT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define CMSDK_AT_UART_INTMASK__TXINT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define CMSDK_AT_UART_INTMASK__TXINT_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field rxint_en */ +/** + * @defgroup at_apb_uart_regs_core_rxint_en_field rxint_en_field + * @brief macros for field rxint_en + * @details mask enable for RX interrupt. + * @{ + */ +#define CMSDK_AT_UART_INTMASK__RXINT_EN__SHIFT 1 +#define CMSDK_AT_UART_INTMASK__RXINT_EN__WIDTH 1 +#define CMSDK_AT_UART_INTMASK__RXINT_EN__MASK 0x00000002U +#define CMSDK_AT_UART_INTMASK_RXINT_EN_Pos \ + CMSDK_AT_UART_INTMASK__RXINT_EN__SHIFT +#define CMSDK_AT_UART_INTMASK_RXINT_EN_Msk \ + CMSDK_AT_UART_INTMASK__RXINT_EN__MASK +#define CMSDK_UART_INTMASK_RXINT_EN_Pos CMSDK_AT_UART_INTMASK__RXINT_EN__SHIFT +#define CMSDK_UART_INTMASK_RXINT_EN_Msk CMSDK_AT_UART_INTMASK__RXINT_EN__MASK +#define CMSDK_AT_UART_INTMASK__RXINT_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define CMSDK_AT_UART_INTMASK__RXINT_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define CMSDK_AT_UART_INTMASK__RXINT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define CMSDK_AT_UART_INTMASK__RXINT_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define CMSDK_AT_UART_INTMASK__RXINT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define CMSDK_AT_UART_INTMASK__RXINT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define CMSDK_AT_UART_INTMASK__RXINT_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field tx_overflow_int_en */ +/** + * @defgroup at_apb_uart_regs_core_tx_overflow_int_en_field tx_overflow_int_en_field + * @brief macros for field tx_overflow_int_en + * @details mask enable for TX overflow interrupt. + * @{ + */ +#define CMSDK_AT_UART_INTMASK__TX_OVERFLOW_INT_EN__SHIFT 2 +#define CMSDK_AT_UART_INTMASK__TX_OVERFLOW_INT_EN__WIDTH 1 +#define CMSDK_AT_UART_INTMASK__TX_OVERFLOW_INT_EN__MASK 0x00000004U +#define CMSDK_AT_UART_INTMASK_TX_OVERFLOW_INT_EN_Pos \ + CMSDK_AT_UART_INTMASK__TX_OVERFLOW_INT_EN__SHIFT +#define CMSDK_AT_UART_INTMASK_TX_OVERFLOW_INT_EN_Msk \ + CMSDK_AT_UART_INTMASK__TX_OVERFLOW_INT_EN__MASK +#define CMSDK_UART_INTMASK_TX_OVERFLOW_INT_EN_Pos \ + CMSDK_AT_UART_INTMASK__TX_OVERFLOW_INT_EN__SHIFT +#define CMSDK_UART_INTMASK_TX_OVERFLOW_INT_EN_Msk \ + CMSDK_AT_UART_INTMASK__TX_OVERFLOW_INT_EN__MASK +#define CMSDK_AT_UART_INTMASK__TX_OVERFLOW_INT_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define CMSDK_AT_UART_INTMASK__TX_OVERFLOW_INT_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define CMSDK_AT_UART_INTMASK__TX_OVERFLOW_INT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define CMSDK_AT_UART_INTMASK__TX_OVERFLOW_INT_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define CMSDK_AT_UART_INTMASK__TX_OVERFLOW_INT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define CMSDK_AT_UART_INTMASK__TX_OVERFLOW_INT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define CMSDK_AT_UART_INTMASK__TX_OVERFLOW_INT_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field rx_overflow_int_en */ +/** + * @defgroup at_apb_uart_regs_core_rx_overflow_int_en_field rx_overflow_int_en_field + * @brief macros for field rx_overflow_int_en + * @details mask enable for RX overflow interrupt. + * @{ + */ +#define CMSDK_AT_UART_INTMASK__RX_OVERFLOW_INT_EN__SHIFT 3 +#define CMSDK_AT_UART_INTMASK__RX_OVERFLOW_INT_EN__WIDTH 1 +#define CMSDK_AT_UART_INTMASK__RX_OVERFLOW_INT_EN__MASK 0x00000008U +#define CMSDK_AT_UART_INTMASK_RX_OVERFLOW_INT_EN_Pos \ + CMSDK_AT_UART_INTMASK__RX_OVERFLOW_INT_EN__SHIFT +#define CMSDK_AT_UART_INTMASK_RX_OVERFLOW_INT_EN_Msk \ + CMSDK_AT_UART_INTMASK__RX_OVERFLOW_INT_EN__MASK +#define CMSDK_UART_INTMASK_RX_OVERFLOW_INT_EN_Pos \ + CMSDK_AT_UART_INTMASK__RX_OVERFLOW_INT_EN__SHIFT +#define CMSDK_UART_INTMASK_RX_OVERFLOW_INT_EN_Msk \ + CMSDK_AT_UART_INTMASK__RX_OVERFLOW_INT_EN__MASK +#define CMSDK_AT_UART_INTMASK__RX_OVERFLOW_INT_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define CMSDK_AT_UART_INTMASK__RX_OVERFLOW_INT_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define CMSDK_AT_UART_INTMASK__RX_OVERFLOW_INT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define CMSDK_AT_UART_INTMASK__RX_OVERFLOW_INT_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define CMSDK_AT_UART_INTMASK__RX_OVERFLOW_INT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define CMSDK_AT_UART_INTMASK__RX_OVERFLOW_INT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define CMSDK_AT_UART_INTMASK__RX_OVERFLOW_INT_EN__RESET_VALUE 0x00000001U +/** @} */ +#define CMSDK_AT_UART_INTMASK__TYPE uint32_t +#define CMSDK_AT_UART_INTMASK__READ 0x0000000fU +#define CMSDK_AT_UART_INTMASK__WRITE 0x0000000fU +#define CMSDK_AT_UART_INTMASK__PRESERVED 0x00000000U +#define CMSDK_AT_UART_INTMASK__RESET_VALUE 0x0000000fU + +#endif /* __CMSDK_AT_UART_INTMASK_MACRO__ */ + +/** @} end of INTMASK */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_RX_FIFO_ENTRIES */ +/** + * @defgroup at_apb_uart_regs_core_RX_FIFO_ENTRIES RX_FIFO_ENTRIES + * @brief Contains register fields associated with RX_FIFO_ENTRIES. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_RX_FIFO_ENTRIES_MACRO__ +#define __CMSDK_AT_UART_RX_FIFO_ENTRIES_MACRO__ + +/* macros for field rx_fifo_entries */ +/** + * @defgroup at_apb_uart_regs_core_rx_fifo_entries_field rx_fifo_entries_field + * @brief macros for field rx_fifo_entries + * @details number of occupied spaces in RX_FIFO. DMA reads this value to determine how many reads to do in each round. + * @{ + */ +#define CMSDK_AT_UART_RX_FIFO_ENTRIES__RX_FIFO_ENTRIES__SHIFT 0 +#define CMSDK_AT_UART_RX_FIFO_ENTRIES__RX_FIFO_ENTRIES__WIDTH 5 +#define CMSDK_AT_UART_RX_FIFO_ENTRIES__RX_FIFO_ENTRIES__MASK 0x0000001fU +#define CMSDK_AT_UART_RX_FIFO_ENTRIES_Pos \ + CMSDK_AT_UART_RX_FIFO_ENTRIES__RX_FIFO_ENTRIES__SHIFT +#define CMSDK_AT_UART_RX_FIFO_ENTRIES_Msk \ + CMSDK_AT_UART_RX_FIFO_ENTRIES__RX_FIFO_ENTRIES__MASK +#define CMSDK_UART_RX_FIFO_ENTRIES_Pos \ + CMSDK_AT_UART_RX_FIFO_ENTRIES__RX_FIFO_ENTRIES__SHIFT +#define CMSDK_UART_RX_FIFO_ENTRIES_Msk \ + CMSDK_AT_UART_RX_FIFO_ENTRIES__RX_FIFO_ENTRIES__MASK +#define CMSDK_AT_UART_RX_FIFO_ENTRIES__RX_FIFO_ENTRIES__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define CMSDK_AT_UART_RX_FIFO_ENTRIES__RX_FIFO_ENTRIES__RESET_VALUE 0x00000000U +/** @} */ +#define CMSDK_AT_UART_RX_FIFO_ENTRIES__TYPE uint32_t +#define CMSDK_AT_UART_RX_FIFO_ENTRIES__READ 0x0000001fU +#define CMSDK_AT_UART_RX_FIFO_ENTRIES__PRESERVED 0x00000000U +#define CMSDK_AT_UART_RX_FIFO_ENTRIES__RESET_VALUE 0x00000000U + +#endif /* __CMSDK_AT_UART_RX_FIFO_ENTRIES_MACRO__ */ + +/** @} end of RX_FIFO_ENTRIES */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_INTSTATUS_SET */ +/** + * @defgroup at_apb_uart_regs_core_INTSTATUS_SET INTSTATUS_SET + * @brief Contains register fields associated with INTSTATUS_SET. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_INTSTATUS_SET_MACRO__ +#define __CMSDK_AT_UART_INTSTATUS_SET_MACRO__ + +/* macros for field txintr_set */ +/** + * @defgroup at_apb_uart_regs_core_txintr_set_field txintr_set_field + * @brief macros for field txintr_set + * @details TX interrupt. Write 1 to set. (self-clearing) + * @{ + */ +#define CMSDK_AT_UART_INTSTATUS_SET__TXINTR_SET__SHIFT 0 +#define CMSDK_AT_UART_INTSTATUS_SET__TXINTR_SET__WIDTH 1 +#define CMSDK_AT_UART_INTSTATUS_SET__TXINTR_SET__MASK 0x00000001U +#define CMSDK_AT_UART_INTSTATUS_SET_TXINTR_SET_Pos \ + CMSDK_AT_UART_INTSTATUS_SET__TXINTR_SET__SHIFT +#define CMSDK_AT_UART_INTSTATUS_SET_TXINTR_SET_Msk \ + CMSDK_AT_UART_INTSTATUS_SET__TXINTR_SET__MASK +#define CMSDK_UART_INTSTATUS_SET_TXINTR_SET_Pos \ + CMSDK_AT_UART_INTSTATUS_SET__TXINTR_SET__SHIFT +#define CMSDK_UART_INTSTATUS_SET_TXINTR_SET_Msk \ + CMSDK_AT_UART_INTSTATUS_SET__TXINTR_SET__MASK +#define CMSDK_AT_UART_INTSTATUS_SET__TXINTR_SET__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CMSDK_AT_UART_INTSTATUS_SET__TXINTR_SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define CMSDK_AT_UART_INTSTATUS_SET__TXINTR_SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define CMSDK_AT_UART_INTSTATUS_SET__TXINTR_SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define CMSDK_AT_UART_INTSTATUS_SET__TXINTR_SET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define CMSDK_AT_UART_INTSTATUS_SET__TXINTR_SET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define CMSDK_AT_UART_INTSTATUS_SET__TXINTR_SET__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rxintr_set */ +/** + * @defgroup at_apb_uart_regs_core_rxintr_set_field rxintr_set_field + * @brief macros for field rxintr_set + * @details RX interrupt. Write 1 to set. (self-clearing) + * @{ + */ +#define CMSDK_AT_UART_INTSTATUS_SET__RXINTR_SET__SHIFT 1 +#define CMSDK_AT_UART_INTSTATUS_SET__RXINTR_SET__WIDTH 1 +#define CMSDK_AT_UART_INTSTATUS_SET__RXINTR_SET__MASK 0x00000002U +#define CMSDK_AT_UART_INTSTATUS_SET_RXINTR_SET_Pos \ + CMSDK_AT_UART_INTSTATUS_SET__RXINTR_SET__SHIFT +#define CMSDK_AT_UART_INTSTATUS_SET_RXINTR_SET_Msk \ + CMSDK_AT_UART_INTSTATUS_SET__RXINTR_SET__MASK +#define CMSDK_UART_INTSTATUS_SET_RXINTR_SET_Pos \ + CMSDK_AT_UART_INTSTATUS_SET__RXINTR_SET__SHIFT +#define CMSDK_UART_INTSTATUS_SET_RXINTR_SET_Msk \ + CMSDK_AT_UART_INTSTATUS_SET__RXINTR_SET__MASK +#define CMSDK_AT_UART_INTSTATUS_SET__RXINTR_SET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define CMSDK_AT_UART_INTSTATUS_SET__RXINTR_SET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define CMSDK_AT_UART_INTSTATUS_SET__RXINTR_SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define CMSDK_AT_UART_INTSTATUS_SET__RXINTR_SET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define CMSDK_AT_UART_INTSTATUS_SET__RXINTR_SET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define CMSDK_AT_UART_INTSTATUS_SET__RXINTR_SET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define CMSDK_AT_UART_INTSTATUS_SET__RXINTR_SET__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tx_overflow_intr_set */ +/** + * @defgroup at_apb_uart_regs_core_tx_overflow_intr_set_field tx_overflow_intr_set_field + * @brief macros for field tx_overflow_intr_set + * @details TX overrun interrupt. Write 1 to set. (self-clearing) + * @{ + */ +#define CMSDK_AT_UART_INTSTATUS_SET__TX_OVERFLOW_INTR_SET__SHIFT 2 +#define CMSDK_AT_UART_INTSTATUS_SET__TX_OVERFLOW_INTR_SET__WIDTH 1 +#define CMSDK_AT_UART_INTSTATUS_SET__TX_OVERFLOW_INTR_SET__MASK 0x00000004U +#define CMSDK_AT_UART_INTSTATUS_SET_TX_OVERFLOW_INTR_SET_Pos \ + CMSDK_AT_UART_INTSTATUS_SET__TX_OVERFLOW_INTR_SET__SHIFT +#define CMSDK_AT_UART_INTSTATUS_SET_TX_OVERFLOW_INTR_SET_Msk \ + CMSDK_AT_UART_INTSTATUS_SET__TX_OVERFLOW_INTR_SET__MASK +#define CMSDK_UART_INTSTATUS_SET_TX_OVERFLOW_INTR_SET_Pos \ + CMSDK_AT_UART_INTSTATUS_SET__TX_OVERFLOW_INTR_SET__SHIFT +#define CMSDK_UART_INTSTATUS_SET_TX_OVERFLOW_INTR_SET_Msk \ + CMSDK_AT_UART_INTSTATUS_SET__TX_OVERFLOW_INTR_SET__MASK +#define CMSDK_AT_UART_INTSTATUS_SET__TX_OVERFLOW_INTR_SET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define CMSDK_AT_UART_INTSTATUS_SET__TX_OVERFLOW_INTR_SET__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define CMSDK_AT_UART_INTSTATUS_SET__TX_OVERFLOW_INTR_SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define CMSDK_AT_UART_INTSTATUS_SET__TX_OVERFLOW_INTR_SET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define CMSDK_AT_UART_INTSTATUS_SET__TX_OVERFLOW_INTR_SET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define CMSDK_AT_UART_INTSTATUS_SET__TX_OVERFLOW_INTR_SET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define CMSDK_AT_UART_INTSTATUS_SET__TX_OVERFLOW_INTR_SET__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field rx_overflow_intr_set */ +/** + * @defgroup at_apb_uart_regs_core_rx_overflow_intr_set_field rx_overflow_intr_set_field + * @brief macros for field rx_overflow_intr_set + * @details RX overrun interrupt. Write 1 to set. (self-clearing) + * @{ + */ +#define CMSDK_AT_UART_INTSTATUS_SET__RX_OVERFLOW_INTR_SET__SHIFT 3 +#define CMSDK_AT_UART_INTSTATUS_SET__RX_OVERFLOW_INTR_SET__WIDTH 1 +#define CMSDK_AT_UART_INTSTATUS_SET__RX_OVERFLOW_INTR_SET__MASK 0x00000008U +#define CMSDK_AT_UART_INTSTATUS_SET_RX_OVERFLOW_INTR_SET_Pos \ + CMSDK_AT_UART_INTSTATUS_SET__RX_OVERFLOW_INTR_SET__SHIFT +#define CMSDK_AT_UART_INTSTATUS_SET_RX_OVERFLOW_INTR_SET_Msk \ + CMSDK_AT_UART_INTSTATUS_SET__RX_OVERFLOW_INTR_SET__MASK +#define CMSDK_UART_INTSTATUS_SET_RX_OVERFLOW_INTR_SET_Pos \ + CMSDK_AT_UART_INTSTATUS_SET__RX_OVERFLOW_INTR_SET__SHIFT +#define CMSDK_UART_INTSTATUS_SET_RX_OVERFLOW_INTR_SET_Msk \ + CMSDK_AT_UART_INTSTATUS_SET__RX_OVERFLOW_INTR_SET__MASK +#define CMSDK_AT_UART_INTSTATUS_SET__RX_OVERFLOW_INTR_SET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define CMSDK_AT_UART_INTSTATUS_SET__RX_OVERFLOW_INTR_SET__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define CMSDK_AT_UART_INTSTATUS_SET__RX_OVERFLOW_INTR_SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define CMSDK_AT_UART_INTSTATUS_SET__RX_OVERFLOW_INTR_SET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define CMSDK_AT_UART_INTSTATUS_SET__RX_OVERFLOW_INTR_SET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define CMSDK_AT_UART_INTSTATUS_SET__RX_OVERFLOW_INTR_SET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define CMSDK_AT_UART_INTSTATUS_SET__RX_OVERFLOW_INTR_SET__RESET_VALUE \ + 0x00000000U +/** @} */ +#define CMSDK_AT_UART_INTSTATUS_SET__TYPE uint32_t +#define CMSDK_AT_UART_INTSTATUS_SET__READ 0x0000000fU +#define CMSDK_AT_UART_INTSTATUS_SET__WRITE 0x0000000fU +#define CMSDK_AT_UART_INTSTATUS_SET__PRESERVED 0x00000000U +#define CMSDK_AT_UART_INTSTATUS_SET__RESET_VALUE 0x00000000U + +#endif /* __CMSDK_AT_UART_INTSTATUS_SET_MACRO__ */ + +/** @} end of INTSTATUS_SET */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_PID4 */ +/** + * @defgroup at_apb_uart_regs_core_PID4 PID4 + * @brief Contains register fields associated with PID4. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_PID4_MACRO__ +#define __CMSDK_AT_UART_PID4_MACRO__ + +/* macros for field jep106_c_code */ +/** + * @defgroup at_apb_uart_regs_core_jep106_c_code_field jep106_c_code_field + * @brief macros for field jep106_c_code + * @details jep106_c_code + * @{ + */ +#define CMSDK_AT_UART_PID4__JEP106_C_CODE__SHIFT 0 +#define CMSDK_AT_UART_PID4__JEP106_C_CODE__WIDTH 4 +#define CMSDK_AT_UART_PID4__JEP106_C_CODE__MASK 0x0000000fU +#define CMSDK_AT_UART_PID4_JEP106_C_CODE_Pos \ + CMSDK_AT_UART_PID4__JEP106_C_CODE__SHIFT +#define CMSDK_AT_UART_PID4_JEP106_C_CODE_Msk \ + CMSDK_AT_UART_PID4__JEP106_C_CODE__MASK +#define CMSDK_UART_PID4_JEP106_C_CODE_Pos \ + CMSDK_AT_UART_PID4__JEP106_C_CODE__SHIFT +#define CMSDK_UART_PID4_JEP106_C_CODE_Msk \ + CMSDK_AT_UART_PID4__JEP106_C_CODE__MASK +#define CMSDK_AT_UART_PID4__JEP106_C_CODE__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define CMSDK_AT_UART_PID4__JEP106_C_CODE__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field block_count */ +/** + * @defgroup at_apb_uart_regs_core_block_count_field block_count_field + * @brief macros for field block_count + * @details Block count + * @{ + */ +#define CMSDK_AT_UART_PID4__BLOCK_COUNT__SHIFT 4 +#define CMSDK_AT_UART_PID4__BLOCK_COUNT__WIDTH 4 +#define CMSDK_AT_UART_PID4__BLOCK_COUNT__MASK 0x000000f0U +#define CMSDK_AT_UART_PID4_BLOCK_COUNT_Pos \ + CMSDK_AT_UART_PID4__BLOCK_COUNT__SHIFT +#define CMSDK_AT_UART_PID4_BLOCK_COUNT_Msk \ + CMSDK_AT_UART_PID4__BLOCK_COUNT__MASK +#define CMSDK_UART_PID4_BLOCK_COUNT_Pos CMSDK_AT_UART_PID4__BLOCK_COUNT__SHIFT +#define CMSDK_UART_PID4_BLOCK_COUNT_Msk CMSDK_AT_UART_PID4__BLOCK_COUNT__MASK +#define CMSDK_AT_UART_PID4__BLOCK_COUNT__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define CMSDK_AT_UART_PID4__BLOCK_COUNT__RESET_VALUE 0x00000000U +/** @} */ +#define CMSDK_AT_UART_PID4__TYPE uint32_t +#define CMSDK_AT_UART_PID4__READ 0x000000ffU +#define CMSDK_AT_UART_PID4__PRESERVED 0x00000000U +#define CMSDK_AT_UART_PID4__RESET_VALUE 0x00000004U + +#endif /* __CMSDK_AT_UART_PID4_MACRO__ */ + +/** @} end of PID4 */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_PID5 */ +/** + * @defgroup at_apb_uart_regs_core_PID5 PID5 + * @brief Contains register fields associated with PID5. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_PID5_MACRO__ +#define __CMSDK_AT_UART_PID5_MACRO__ + +/* macros for field pid5 */ +/** + * @defgroup at_apb_uart_regs_core_pid5_field pid5_field + * @brief macros for field pid5 + * @details Peripheral ID Register 5. + * @{ + */ +#define CMSDK_AT_UART_PID5__PID5__SHIFT 0 +#define CMSDK_AT_UART_PID5__PID5__WIDTH 8 +#define CMSDK_AT_UART_PID5__PID5__MASK 0x000000ffU +#define CMSDK_AT_UART_PID5_Pos CMSDK_AT_UART_PID5__PID5__SHIFT +#define CMSDK_AT_UART_PID5_Msk CMSDK_AT_UART_PID5__PID5__MASK +#define CMSDK_UART_PID5_Pos CMSDK_AT_UART_PID5__PID5__SHIFT +#define CMSDK_UART_PID5_Msk CMSDK_AT_UART_PID5__PID5__MASK +#define CMSDK_AT_UART_PID5__PID5__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define CMSDK_AT_UART_PID5__PID5__RESET_VALUE 0x00000000U +/** @} */ +#define CMSDK_AT_UART_PID5__TYPE uint32_t +#define CMSDK_AT_UART_PID5__READ 0x000000ffU +#define CMSDK_AT_UART_PID5__PRESERVED 0x00000000U +#define CMSDK_AT_UART_PID5__RESET_VALUE 0x00000000U + +#endif /* __CMSDK_AT_UART_PID5_MACRO__ */ + +/** @} end of PID5 */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_PID6 */ +/** + * @defgroup at_apb_uart_regs_core_PID6 PID6 + * @brief Contains register fields associated with PID6. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_PID6_MACRO__ +#define __CMSDK_AT_UART_PID6_MACRO__ + +/* macros for field pid6 */ +/** + * @defgroup at_apb_uart_regs_core_pid6_field pid6_field + * @brief macros for field pid6 + * @details Peripheral ID Register 6. + * @{ + */ +#define CMSDK_AT_UART_PID6__PID6__SHIFT 0 +#define CMSDK_AT_UART_PID6__PID6__WIDTH 8 +#define CMSDK_AT_UART_PID6__PID6__MASK 0x000000ffU +#define CMSDK_AT_UART_PID6_Pos CMSDK_AT_UART_PID6__PID6__SHIFT +#define CMSDK_AT_UART_PID6_Msk CMSDK_AT_UART_PID6__PID6__MASK +#define CMSDK_UART_PID6_Pos CMSDK_AT_UART_PID6__PID6__SHIFT +#define CMSDK_UART_PID6_Msk CMSDK_AT_UART_PID6__PID6__MASK +#define CMSDK_AT_UART_PID6__PID6__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define CMSDK_AT_UART_PID6__PID6__RESET_VALUE 0x00000000U +/** @} */ +#define CMSDK_AT_UART_PID6__TYPE uint32_t +#define CMSDK_AT_UART_PID6__READ 0x000000ffU +#define CMSDK_AT_UART_PID6__PRESERVED 0x00000000U +#define CMSDK_AT_UART_PID6__RESET_VALUE 0x00000000U + +#endif /* __CMSDK_AT_UART_PID6_MACRO__ */ + +/** @} end of PID6 */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_PID7 */ +/** + * @defgroup at_apb_uart_regs_core_PID7 PID7 + * @brief Contains register fields associated with PID7. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_PID7_MACRO__ +#define __CMSDK_AT_UART_PID7_MACRO__ + +/* macros for field pid7 */ +/** + * @defgroup at_apb_uart_regs_core_pid7_field pid7_field + * @brief macros for field pid7 + * @details Peripheral ID Register 7. + * @{ + */ +#define CMSDK_AT_UART_PID7__PID7__SHIFT 0 +#define CMSDK_AT_UART_PID7__PID7__WIDTH 8 +#define CMSDK_AT_UART_PID7__PID7__MASK 0x000000ffU +#define CMSDK_AT_UART_PID7_Pos CMSDK_AT_UART_PID7__PID7__SHIFT +#define CMSDK_AT_UART_PID7_Msk CMSDK_AT_UART_PID7__PID7__MASK +#define CMSDK_UART_PID7_Pos CMSDK_AT_UART_PID7__PID7__SHIFT +#define CMSDK_UART_PID7_Msk CMSDK_AT_UART_PID7__PID7__MASK +#define CMSDK_AT_UART_PID7__PID7__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define CMSDK_AT_UART_PID7__PID7__RESET_VALUE 0x00000000U +/** @} */ +#define CMSDK_AT_UART_PID7__TYPE uint32_t +#define CMSDK_AT_UART_PID7__READ 0x000000ffU +#define CMSDK_AT_UART_PID7__PRESERVED 0x00000000U +#define CMSDK_AT_UART_PID7__RESET_VALUE 0x00000000U + +#endif /* __CMSDK_AT_UART_PID7_MACRO__ */ + +/** @} end of PID7 */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_PID0 */ +/** + * @defgroup at_apb_uart_regs_core_PID0 PID0 + * @brief Contains register fields associated with PID0. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_PID0_MACRO__ +#define __CMSDK_AT_UART_PID0_MACRO__ + +/* macros for field part_num */ +/** + * @defgroup at_apb_uart_regs_core_part_num_field part_num_field + * @brief macros for field part_num + * @details Part number[7:0]. + * @{ + */ +#define CMSDK_AT_UART_PID0__PART_NUM__SHIFT 0 +#define CMSDK_AT_UART_PID0__PART_NUM__WIDTH 8 +#define CMSDK_AT_UART_PID0__PART_NUM__MASK 0x000000ffU +#define CMSDK_AT_UART_PID0_Pos CMSDK_AT_UART_PID0__PART_NUM__SHIFT +#define CMSDK_AT_UART_PID0_Msk CMSDK_AT_UART_PID0__PART_NUM__MASK +#define CMSDK_UART_PID0_Pos CMSDK_AT_UART_PID0__PART_NUM__SHIFT +#define CMSDK_UART_PID0_Msk CMSDK_AT_UART_PID0__PART_NUM__MASK +#define CMSDK_AT_UART_PID0__PART_NUM__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define CMSDK_AT_UART_PID0__PART_NUM__RESET_VALUE 0x00000021U +/** @} */ +#define CMSDK_AT_UART_PID0__TYPE uint32_t +#define CMSDK_AT_UART_PID0__READ 0x000000ffU +#define CMSDK_AT_UART_PID0__PRESERVED 0x00000000U +#define CMSDK_AT_UART_PID0__RESET_VALUE 0x00000021U + +#endif /* __CMSDK_AT_UART_PID0_MACRO__ */ + +/** @} end of PID0 */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_PID1 */ +/** + * @defgroup at_apb_uart_regs_core_PID1 PID1 + * @brief Contains register fields associated with PID1. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_PID1_MACRO__ +#define __CMSDK_AT_UART_PID1_MACRO__ + +/* macros for field part_num */ +/** + * @defgroup at_apb_uart_regs_core_part_num_field part_num_field + * @brief macros for field part_num + * @details Part number[11:8]. + * @{ + */ +#define CMSDK_AT_UART_PID1__PART_NUM__SHIFT 0 +#define CMSDK_AT_UART_PID1__PART_NUM__WIDTH 4 +#define CMSDK_AT_UART_PID1__PART_NUM__MASK 0x0000000fU +#define CMSDK_AT_UART_PID1_PART_NUM_Pos CMSDK_AT_UART_PID1__PART_NUM__SHIFT +#define CMSDK_AT_UART_PID1_PART_NUM_Msk CMSDK_AT_UART_PID1__PART_NUM__MASK +#define CMSDK_UART_PID1_PART_NUM_Pos CMSDK_AT_UART_PID1__PART_NUM__SHIFT +#define CMSDK_UART_PID1_PART_NUM_Msk CMSDK_AT_UART_PID1__PART_NUM__MASK +#define CMSDK_AT_UART_PID1__PART_NUM__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define CMSDK_AT_UART_PID1__PART_NUM__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field jep106_id_3_0 */ +/** + * @defgroup at_apb_uart_regs_core_jep106_id_3_0_field jep106_id_3_0_field + * @brief macros for field jep106_id_3_0 + * @details jep106_id_3_0 + * @{ + */ +#define CMSDK_AT_UART_PID1__JEP106_ID_3_0__SHIFT 4 +#define CMSDK_AT_UART_PID1__JEP106_ID_3_0__WIDTH 4 +#define CMSDK_AT_UART_PID1__JEP106_ID_3_0__MASK 0x000000f0U +#define CMSDK_AT_UART_PID1_JEP106_ID_3_0_Pos \ + CMSDK_AT_UART_PID1__JEP106_ID_3_0__SHIFT +#define CMSDK_AT_UART_PID1_JEP106_ID_3_0_Msk \ + CMSDK_AT_UART_PID1__JEP106_ID_3_0__MASK +#define CMSDK_UART_PID1_JEP106_ID_3_0_Pos \ + CMSDK_AT_UART_PID1__JEP106_ID_3_0__SHIFT +#define CMSDK_UART_PID1_JEP106_ID_3_0_Msk \ + CMSDK_AT_UART_PID1__JEP106_ID_3_0__MASK +#define CMSDK_AT_UART_PID1__JEP106_ID_3_0__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define CMSDK_AT_UART_PID1__JEP106_ID_3_0__RESET_VALUE 0x0000000bU +/** @} */ +#define CMSDK_AT_UART_PID1__TYPE uint32_t +#define CMSDK_AT_UART_PID1__READ 0x000000ffU +#define CMSDK_AT_UART_PID1__PRESERVED 0x00000000U +#define CMSDK_AT_UART_PID1__RESET_VALUE 0x000000b8U + +#endif /* __CMSDK_AT_UART_PID1_MACRO__ */ + +/** @} end of PID1 */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_PID2 */ +/** + * @defgroup at_apb_uart_regs_core_PID2 PID2 + * @brief Contains register fields associated with PID2. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_PID2_MACRO__ +#define __CMSDK_AT_UART_PID2_MACRO__ + +/* macros for field jep106_id_6_4 */ +/** + * @defgroup at_apb_uart_regs_core_jep106_id_6_4_field jep106_id_6_4_field + * @brief macros for field jep106_id_6_4 + * @details jep106_id_6_4 + * @{ + */ +#define CMSDK_AT_UART_PID2__JEP106_ID_6_4__SHIFT 0 +#define CMSDK_AT_UART_PID2__JEP106_ID_6_4__WIDTH 3 +#define CMSDK_AT_UART_PID2__JEP106_ID_6_4__MASK 0x00000007U +#define CMSDK_AT_UART_PID2_JEP106_ID_6_4_Pos \ + CMSDK_AT_UART_PID2__JEP106_ID_6_4__SHIFT +#define CMSDK_AT_UART_PID2_JEP106_ID_6_4_Msk \ + CMSDK_AT_UART_PID2__JEP106_ID_6_4__MASK +#define CMSDK_UART_PID2_JEP106_ID_6_4_Pos \ + CMSDK_AT_UART_PID2__JEP106_ID_6_4__SHIFT +#define CMSDK_UART_PID2_JEP106_ID_6_4_Msk \ + CMSDK_AT_UART_PID2__JEP106_ID_6_4__MASK +#define CMSDK_AT_UART_PID2__JEP106_ID_6_4__READ(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define CMSDK_AT_UART_PID2__JEP106_ID_6_4__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field jedec_used */ +/** + * @defgroup at_apb_uart_regs_core_jedec_used_field jedec_used_field + * @brief macros for field jedec_used + * @details jedec_used + * @{ + */ +#define CMSDK_AT_UART_PID2__JEDEC_USED__SHIFT 3 +#define CMSDK_AT_UART_PID2__JEDEC_USED__WIDTH 1 +#define CMSDK_AT_UART_PID2__JEDEC_USED__MASK 0x00000008U +#define CMSDK_AT_UART_PID2_JEDEC_USED_Pos CMSDK_AT_UART_PID2__JEDEC_USED__SHIFT +#define CMSDK_AT_UART_PID2_JEDEC_USED_Msk CMSDK_AT_UART_PID2__JEDEC_USED__MASK +#define CMSDK_UART_PID2_JEDEC_USED_Pos CMSDK_AT_UART_PID2__JEDEC_USED__SHIFT +#define CMSDK_UART_PID2_JEDEC_USED_Msk CMSDK_AT_UART_PID2__JEDEC_USED__MASK +#define CMSDK_AT_UART_PID2__JEDEC_USED__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define CMSDK_AT_UART_PID2__JEDEC_USED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define CMSDK_AT_UART_PID2__JEDEC_USED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define CMSDK_AT_UART_PID2__JEDEC_USED__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field rev */ +/** + * @defgroup at_apb_uart_regs_core_rev_field rev_field + * @brief macros for field rev + * @details Revision + * @{ + */ +#define CMSDK_AT_UART_PID2__REV__SHIFT 4 +#define CMSDK_AT_UART_PID2__REV__WIDTH 4 +#define CMSDK_AT_UART_PID2__REV__MASK 0x000000f0U +#define CMSDK_AT_UART_PID2_REV_Pos CMSDK_AT_UART_PID2__REV__SHIFT +#define CMSDK_AT_UART_PID2_REV_Msk CMSDK_AT_UART_PID2__REV__MASK +#define CMSDK_UART_PID2_REV_Pos CMSDK_AT_UART_PID2__REV__SHIFT +#define CMSDK_UART_PID2_REV_Msk CMSDK_AT_UART_PID2__REV__MASK +#define CMSDK_AT_UART_PID2__REV__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define CMSDK_AT_UART_PID2__REV__RESET_VALUE 0x00000001U +/** @} */ +#define CMSDK_AT_UART_PID2__TYPE uint32_t +#define CMSDK_AT_UART_PID2__READ 0x000000ffU +#define CMSDK_AT_UART_PID2__PRESERVED 0x00000000U +#define CMSDK_AT_UART_PID2__RESET_VALUE 0x0000001bU + +#endif /* __CMSDK_AT_UART_PID2_MACRO__ */ + +/** @} end of PID2 */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_PID3 */ +/** + * @defgroup at_apb_uart_regs_core_PID3 PID3 + * @brief Contains register fields associated with PID3. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_PID3_MACRO__ +#define __CMSDK_AT_UART_PID3_MACRO__ + +/* macros for field mod_num */ +/** + * @defgroup at_apb_uart_regs_core_mod_num_field mod_num_field + * @brief macros for field mod_num + * @details modification number. + * @{ + */ +#define CMSDK_AT_UART_PID3__MOD_NUM__SHIFT 0 +#define CMSDK_AT_UART_PID3__MOD_NUM__WIDTH 4 +#define CMSDK_AT_UART_PID3__MOD_NUM__MASK 0x0000000fU +#define CMSDK_AT_UART_PID3_MOD_NUM_Pos CMSDK_AT_UART_PID3__MOD_NUM__SHIFT +#define CMSDK_AT_UART_PID3_MOD_NUM_Msk CMSDK_AT_UART_PID3__MOD_NUM__MASK +#define CMSDK_UART_PID3_MOD_NUM_Pos CMSDK_AT_UART_PID3__MOD_NUM__SHIFT +#define CMSDK_UART_PID3_MOD_NUM_Msk CMSDK_AT_UART_PID3__MOD_NUM__MASK +#define CMSDK_AT_UART_PID3__MOD_NUM__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define CMSDK_AT_UART_PID3__MOD_NUM__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ecorevnum */ +/** + * @defgroup at_apb_uart_regs_core_ecorevnum_field ecorevnum_field + * @brief macros for field ecorevnum + * @details ECO revision number. + * @{ + */ +#define CMSDK_AT_UART_PID3__ECOREVNUM__SHIFT 4 +#define CMSDK_AT_UART_PID3__ECOREVNUM__WIDTH 4 +#define CMSDK_AT_UART_PID3__ECOREVNUM__MASK 0x000000f0U +#define CMSDK_AT_UART_PID3_ECOREVNUM_Pos CMSDK_AT_UART_PID3__ECOREVNUM__SHIFT +#define CMSDK_AT_UART_PID3_ECOREVNUM_Msk CMSDK_AT_UART_PID3__ECOREVNUM__MASK +#define CMSDK_UART_PID3_ECOREVNUM_Pos CMSDK_AT_UART_PID3__ECOREVNUM__SHIFT +#define CMSDK_UART_PID3_ECOREVNUM_Msk CMSDK_AT_UART_PID3__ECOREVNUM__MASK +#define CMSDK_AT_UART_PID3__ECOREVNUM__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define CMSDK_AT_UART_PID3__ECOREVNUM__RESET_VALUE 0x00000000U +/** @} */ +#define CMSDK_AT_UART_PID3__TYPE uint32_t +#define CMSDK_AT_UART_PID3__READ 0x000000ffU +#define CMSDK_AT_UART_PID3__PRESERVED 0x00000000U +#define CMSDK_AT_UART_PID3__RESET_VALUE 0x00000000U + +#endif /* __CMSDK_AT_UART_PID3_MACRO__ */ + +/** @} end of PID3 */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_CID0 */ +/** + * @defgroup at_apb_uart_regs_core_CID0 CID0 + * @brief Contains register fields associated with CID0. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_CID0_MACRO__ +#define __CMSDK_AT_UART_CID0_MACRO__ + +/* macros for field cid0 */ +/** + * @defgroup at_apb_uart_regs_core_cid0_field cid0_field + * @brief macros for field cid0 + * @details Component ID Register 0 + * @{ + */ +#define CMSDK_AT_UART_CID0__CID0__SHIFT 0 +#define CMSDK_AT_UART_CID0__CID0__WIDTH 8 +#define CMSDK_AT_UART_CID0__CID0__MASK 0x000000ffU +#define CMSDK_AT_UART_CID0_Pos CMSDK_AT_UART_CID0__CID0__SHIFT +#define CMSDK_AT_UART_CID0_Msk CMSDK_AT_UART_CID0__CID0__MASK +#define CMSDK_UART_CID0_Pos CMSDK_AT_UART_CID0__CID0__SHIFT +#define CMSDK_UART_CID0_Msk CMSDK_AT_UART_CID0__CID0__MASK +#define CMSDK_AT_UART_CID0__CID0__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define CMSDK_AT_UART_CID0__CID0__RESET_VALUE 0x0000000dU +/** @} */ +#define CMSDK_AT_UART_CID0__TYPE uint32_t +#define CMSDK_AT_UART_CID0__READ 0x000000ffU +#define CMSDK_AT_UART_CID0__PRESERVED 0x00000000U +#define CMSDK_AT_UART_CID0__RESET_VALUE 0x0000000dU + +#endif /* __CMSDK_AT_UART_CID0_MACRO__ */ + +/** @} end of CID0 */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_CID1 */ +/** + * @defgroup at_apb_uart_regs_core_CID1 CID1 + * @brief Contains register fields associated with CID1. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_CID1_MACRO__ +#define __CMSDK_AT_UART_CID1_MACRO__ + +/* macros for field cid1 */ +/** + * @defgroup at_apb_uart_regs_core_cid1_field cid1_field + * @brief macros for field cid1 + * @details Component ID Register 1 + * @{ + */ +#define CMSDK_AT_UART_CID1__CID1__SHIFT 0 +#define CMSDK_AT_UART_CID1__CID1__WIDTH 8 +#define CMSDK_AT_UART_CID1__CID1__MASK 0x000000ffU +#define CMSDK_AT_UART_CID1_Pos CMSDK_AT_UART_CID1__CID1__SHIFT +#define CMSDK_AT_UART_CID1_Msk CMSDK_AT_UART_CID1__CID1__MASK +#define CMSDK_UART_CID1_Pos CMSDK_AT_UART_CID1__CID1__SHIFT +#define CMSDK_UART_CID1_Msk CMSDK_AT_UART_CID1__CID1__MASK +#define CMSDK_AT_UART_CID1__CID1__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define CMSDK_AT_UART_CID1__CID1__RESET_VALUE 0x000000f0U +/** @} */ +#define CMSDK_AT_UART_CID1__TYPE uint32_t +#define CMSDK_AT_UART_CID1__READ 0x000000ffU +#define CMSDK_AT_UART_CID1__PRESERVED 0x00000000U +#define CMSDK_AT_UART_CID1__RESET_VALUE 0x000000f0U + +#endif /* __CMSDK_AT_UART_CID1_MACRO__ */ + +/** @} end of CID1 */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_CID2 */ +/** + * @defgroup at_apb_uart_regs_core_CID2 CID2 + * @brief Contains register fields associated with CID2. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_CID2_MACRO__ +#define __CMSDK_AT_UART_CID2_MACRO__ + +/* macros for field cid2 */ +/** + * @defgroup at_apb_uart_regs_core_cid2_field cid2_field + * @brief macros for field cid2 + * @details Component ID Register 2 + * @{ + */ +#define CMSDK_AT_UART_CID2__CID2__SHIFT 0 +#define CMSDK_AT_UART_CID2__CID2__WIDTH 8 +#define CMSDK_AT_UART_CID2__CID2__MASK 0x000000ffU +#define CMSDK_AT_UART_CID2_Pos CMSDK_AT_UART_CID2__CID2__SHIFT +#define CMSDK_AT_UART_CID2_Msk CMSDK_AT_UART_CID2__CID2__MASK +#define CMSDK_UART_CID2_Pos CMSDK_AT_UART_CID2__CID2__SHIFT +#define CMSDK_UART_CID2_Msk CMSDK_AT_UART_CID2__CID2__MASK +#define CMSDK_AT_UART_CID2__CID2__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define CMSDK_AT_UART_CID2__CID2__RESET_VALUE 0x00000005U +/** @} */ +#define CMSDK_AT_UART_CID2__TYPE uint32_t +#define CMSDK_AT_UART_CID2__READ 0x000000ffU +#define CMSDK_AT_UART_CID2__PRESERVED 0x00000000U +#define CMSDK_AT_UART_CID2__RESET_VALUE 0x00000005U + +#endif /* __CMSDK_AT_UART_CID2_MACRO__ */ + +/** @} end of CID2 */ + +/* macros for BlueprintGlobalNameSpace::CMSDK_AT_UART_CID3 */ +/** + * @defgroup at_apb_uart_regs_core_CID3 CID3 + * @brief Contains register fields associated with CID3. definitions. + * @{ + */ +#ifndef __CMSDK_AT_UART_CID3_MACRO__ +#define __CMSDK_AT_UART_CID3_MACRO__ + +/* macros for field cid3 */ +/** + * @defgroup at_apb_uart_regs_core_cid3_field cid3_field + * @brief macros for field cid3 + * @details Component ID Register 3 + * @{ + */ +#define CMSDK_AT_UART_CID3__CID3__SHIFT 0 +#define CMSDK_AT_UART_CID3__CID3__WIDTH 8 +#define CMSDK_AT_UART_CID3__CID3__MASK 0x000000ffU +#define CMSDK_AT_UART_CID3_Pos CMSDK_AT_UART_CID3__CID3__SHIFT +#define CMSDK_AT_UART_CID3_Msk CMSDK_AT_UART_CID3__CID3__MASK +#define CMSDK_UART_CID3_Pos CMSDK_AT_UART_CID3__CID3__SHIFT +#define CMSDK_UART_CID3_Msk CMSDK_AT_UART_CID3__CID3__MASK +#define CMSDK_AT_UART_CID3__CID3__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define CMSDK_AT_UART_CID3__CID3__RESET_VALUE 0x000000b1U +/** @} */ +#define CMSDK_AT_UART_CID3__TYPE uint32_t +#define CMSDK_AT_UART_CID3__READ 0x000000ffU +#define CMSDK_AT_UART_CID3__PRESERVED 0x00000000U +#define CMSDK_AT_UART_CID3__RESET_VALUE 0x000000b1U + +#endif /* __CMSDK_AT_UART_CID3_MACRO__ */ + +/** @} end of CID3 */ + +/** @} end of AT_APB_UART_REGS_CORE */ +#endif /* __REG_AT_APB_UART_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_apb_wrpr_pins_regs_core_macro.h b/ATM33xx-5/include/reg/at_apb_wrpr_pins_regs_core_macro.h new file mode 100644 index 0000000..f112192 --- /dev/null +++ b/ATM33xx-5/include/reg/at_apb_wrpr_pins_regs_core_macro.h @@ -0,0 +1,5911 @@ +/* */ +/* File: at_apb_wrpr_pins_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_apb_wrpr_pins_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_APB_WRPR_PINS_REGS_CORE_H__ +#define __REG_AT_APB_WRPR_PINS_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_APB_WRPR_PINS_REGS_CORE at_apb_wrpr_pins_regs_core + * @ingroup AT_REG + * @brief at_apb_wrpr_pins_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_apb0_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_apb0_ctrl apb0_ctrl + * @brief Contains register fields associated with apb0_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_APB0_CTRL_MACRO__ +#define __WRPRPINS_APB0_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRPINS_APB0_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRPINS_APB0_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRPINS_APB0_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRPINS_APB0_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB0_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB0_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_APB0_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_APB0_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_APB0_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_APB0_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRPINS_APB0_CTRL__SRESET__SHIFT 1 +#define WRPRPINS_APB0_CTRL__SRESET__WIDTH 1 +#define WRPRPINS_APB0_CTRL__SRESET__MASK 0x00000002U +#define WRPRPINS_APB0_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRPINS_APB0_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRPINS_APB0_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRPINS_APB0_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRPINS_APB0_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRPINS_APB0_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRPINS_APB0_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRPINS_APB0_CTRL__CLK_SEL__SHIFT 2 +#define WRPRPINS_APB0_CTRL__CLK_SEL__WIDTH 1 +#define WRPRPINS_APB0_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRPINS_APB0_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRPINS_APB0_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRPINS_APB0_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRPINS_APB0_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRPINS_APB0_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRPINS_APB0_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRPINS_APB0_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_APB0_CTRL__TYPE uint32_t +#define WRPRPINS_APB0_CTRL__READ 0x00000007U +#define WRPRPINS_APB0_CTRL__WRITE 0x00000007U +#define WRPRPINS_APB0_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_APB0_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRPINS_APB0_CTRL_MACRO__ */ + +/** @} end of apb0_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_apb1_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_apb1_ctrl apb1_ctrl + * @brief Contains register fields associated with apb1_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_APB1_CTRL_MACRO__ +#define __WRPRPINS_APB1_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRPINS_APB1_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRPINS_APB1_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRPINS_APB1_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRPINS_APB1_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB1_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB1_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_APB1_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_APB1_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_APB1_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_APB1_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRPINS_APB1_CTRL__SRESET__SHIFT 1 +#define WRPRPINS_APB1_CTRL__SRESET__WIDTH 1 +#define WRPRPINS_APB1_CTRL__SRESET__MASK 0x00000002U +#define WRPRPINS_APB1_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRPINS_APB1_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRPINS_APB1_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRPINS_APB1_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRPINS_APB1_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRPINS_APB1_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRPINS_APB1_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRPINS_APB1_CTRL__CLK_SEL__SHIFT 2 +#define WRPRPINS_APB1_CTRL__CLK_SEL__WIDTH 1 +#define WRPRPINS_APB1_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRPINS_APB1_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRPINS_APB1_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRPINS_APB1_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRPINS_APB1_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRPINS_APB1_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRPINS_APB1_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRPINS_APB1_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_APB1_CTRL__TYPE uint32_t +#define WRPRPINS_APB1_CTRL__READ 0x00000007U +#define WRPRPINS_APB1_CTRL__WRITE 0x00000007U +#define WRPRPINS_APB1_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_APB1_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRPINS_APB1_CTRL_MACRO__ */ + +/** @} end of apb1_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_apb2_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_apb2_ctrl apb2_ctrl + * @brief Contains register fields associated with apb2_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_APB2_CTRL_MACRO__ +#define __WRPRPINS_APB2_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRPINS_APB2_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRPINS_APB2_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRPINS_APB2_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRPINS_APB2_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB2_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB2_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_APB2_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_APB2_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_APB2_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_APB2_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRPINS_APB2_CTRL__SRESET__SHIFT 1 +#define WRPRPINS_APB2_CTRL__SRESET__WIDTH 1 +#define WRPRPINS_APB2_CTRL__SRESET__MASK 0x00000002U +#define WRPRPINS_APB2_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRPINS_APB2_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRPINS_APB2_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRPINS_APB2_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRPINS_APB2_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRPINS_APB2_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRPINS_APB2_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRPINS_APB2_CTRL__CLK_SEL__SHIFT 2 +#define WRPRPINS_APB2_CTRL__CLK_SEL__WIDTH 1 +#define WRPRPINS_APB2_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRPINS_APB2_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRPINS_APB2_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRPINS_APB2_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRPINS_APB2_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRPINS_APB2_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRPINS_APB2_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRPINS_APB2_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_APB2_CTRL__TYPE uint32_t +#define WRPRPINS_APB2_CTRL__READ 0x00000007U +#define WRPRPINS_APB2_CTRL__WRITE 0x00000007U +#define WRPRPINS_APB2_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_APB2_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRPINS_APB2_CTRL_MACRO__ */ + +/** @} end of apb2_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_apb3_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_apb3_ctrl apb3_ctrl + * @brief Contains register fields associated with apb3_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_APB3_CTRL_MACRO__ +#define __WRPRPINS_APB3_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRPINS_APB3_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRPINS_APB3_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRPINS_APB3_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRPINS_APB3_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB3_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB3_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_APB3_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_APB3_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_APB3_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_APB3_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRPINS_APB3_CTRL__SRESET__SHIFT 1 +#define WRPRPINS_APB3_CTRL__SRESET__WIDTH 1 +#define WRPRPINS_APB3_CTRL__SRESET__MASK 0x00000002U +#define WRPRPINS_APB3_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRPINS_APB3_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRPINS_APB3_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRPINS_APB3_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRPINS_APB3_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRPINS_APB3_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRPINS_APB3_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRPINS_APB3_CTRL__CLK_SEL__SHIFT 2 +#define WRPRPINS_APB3_CTRL__CLK_SEL__WIDTH 1 +#define WRPRPINS_APB3_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRPINS_APB3_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRPINS_APB3_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRPINS_APB3_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRPINS_APB3_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRPINS_APB3_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRPINS_APB3_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRPINS_APB3_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_APB3_CTRL__TYPE uint32_t +#define WRPRPINS_APB3_CTRL__READ 0x00000007U +#define WRPRPINS_APB3_CTRL__WRITE 0x00000007U +#define WRPRPINS_APB3_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_APB3_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRPINS_APB3_CTRL_MACRO__ */ + +/** @} end of apb3_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_apb4_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_apb4_ctrl apb4_ctrl + * @brief Contains register fields associated with apb4_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_APB4_CTRL_MACRO__ +#define __WRPRPINS_APB4_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRPINS_APB4_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRPINS_APB4_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRPINS_APB4_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRPINS_APB4_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB4_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB4_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_APB4_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_APB4_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_APB4_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_APB4_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRPINS_APB4_CTRL__SRESET__SHIFT 1 +#define WRPRPINS_APB4_CTRL__SRESET__WIDTH 1 +#define WRPRPINS_APB4_CTRL__SRESET__MASK 0x00000002U +#define WRPRPINS_APB4_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRPINS_APB4_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRPINS_APB4_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRPINS_APB4_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRPINS_APB4_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRPINS_APB4_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRPINS_APB4_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRPINS_APB4_CTRL__CLK_SEL__SHIFT 2 +#define WRPRPINS_APB4_CTRL__CLK_SEL__WIDTH 1 +#define WRPRPINS_APB4_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRPINS_APB4_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRPINS_APB4_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRPINS_APB4_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRPINS_APB4_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRPINS_APB4_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRPINS_APB4_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRPINS_APB4_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_APB4_CTRL__TYPE uint32_t +#define WRPRPINS_APB4_CTRL__READ 0x00000007U +#define WRPRPINS_APB4_CTRL__WRITE 0x00000007U +#define WRPRPINS_APB4_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_APB4_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRPINS_APB4_CTRL_MACRO__ */ + +/** @} end of apb4_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_apb5_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_apb5_ctrl apb5_ctrl + * @brief Contains register fields associated with apb5_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_APB5_CTRL_MACRO__ +#define __WRPRPINS_APB5_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRPINS_APB5_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRPINS_APB5_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRPINS_APB5_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRPINS_APB5_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB5_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB5_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_APB5_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_APB5_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_APB5_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_APB5_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRPINS_APB5_CTRL__SRESET__SHIFT 1 +#define WRPRPINS_APB5_CTRL__SRESET__WIDTH 1 +#define WRPRPINS_APB5_CTRL__SRESET__MASK 0x00000002U +#define WRPRPINS_APB5_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRPINS_APB5_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRPINS_APB5_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRPINS_APB5_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRPINS_APB5_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRPINS_APB5_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRPINS_APB5_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRPINS_APB5_CTRL__CLK_SEL__SHIFT 2 +#define WRPRPINS_APB5_CTRL__CLK_SEL__WIDTH 1 +#define WRPRPINS_APB5_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRPINS_APB5_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRPINS_APB5_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRPINS_APB5_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRPINS_APB5_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRPINS_APB5_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRPINS_APB5_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRPINS_APB5_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_APB5_CTRL__TYPE uint32_t +#define WRPRPINS_APB5_CTRL__READ 0x00000007U +#define WRPRPINS_APB5_CTRL__WRITE 0x00000007U +#define WRPRPINS_APB5_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_APB5_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRPINS_APB5_CTRL_MACRO__ */ + +/** @} end of apb5_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_apb6_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_apb6_ctrl apb6_ctrl + * @brief Contains register fields associated with apb6_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_APB6_CTRL_MACRO__ +#define __WRPRPINS_APB6_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRPINS_APB6_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRPINS_APB6_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRPINS_APB6_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRPINS_APB6_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB6_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB6_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_APB6_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_APB6_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_APB6_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_APB6_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRPINS_APB6_CTRL__SRESET__SHIFT 1 +#define WRPRPINS_APB6_CTRL__SRESET__WIDTH 1 +#define WRPRPINS_APB6_CTRL__SRESET__MASK 0x00000002U +#define WRPRPINS_APB6_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRPINS_APB6_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRPINS_APB6_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRPINS_APB6_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRPINS_APB6_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRPINS_APB6_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRPINS_APB6_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRPINS_APB6_CTRL__CLK_SEL__SHIFT 2 +#define WRPRPINS_APB6_CTRL__CLK_SEL__WIDTH 1 +#define WRPRPINS_APB6_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRPINS_APB6_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRPINS_APB6_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRPINS_APB6_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRPINS_APB6_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRPINS_APB6_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRPINS_APB6_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRPINS_APB6_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_APB6_CTRL__TYPE uint32_t +#define WRPRPINS_APB6_CTRL__READ 0x00000007U +#define WRPRPINS_APB6_CTRL__WRITE 0x00000007U +#define WRPRPINS_APB6_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_APB6_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRPINS_APB6_CTRL_MACRO__ */ + +/** @} end of apb6_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_apb7_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_apb7_ctrl apb7_ctrl + * @brief Contains register fields associated with apb7_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_APB7_CTRL_MACRO__ +#define __WRPRPINS_APB7_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRPINS_APB7_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRPINS_APB7_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRPINS_APB7_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRPINS_APB7_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB7_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB7_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_APB7_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_APB7_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_APB7_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_APB7_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRPINS_APB7_CTRL__SRESET__SHIFT 1 +#define WRPRPINS_APB7_CTRL__SRESET__WIDTH 1 +#define WRPRPINS_APB7_CTRL__SRESET__MASK 0x00000002U +#define WRPRPINS_APB7_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRPINS_APB7_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRPINS_APB7_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRPINS_APB7_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRPINS_APB7_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRPINS_APB7_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRPINS_APB7_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRPINS_APB7_CTRL__CLK_SEL__SHIFT 2 +#define WRPRPINS_APB7_CTRL__CLK_SEL__WIDTH 1 +#define WRPRPINS_APB7_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRPINS_APB7_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRPINS_APB7_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRPINS_APB7_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRPINS_APB7_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRPINS_APB7_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRPINS_APB7_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRPINS_APB7_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_APB7_CTRL__TYPE uint32_t +#define WRPRPINS_APB7_CTRL__READ 0x00000007U +#define WRPRPINS_APB7_CTRL__WRITE 0x00000007U +#define WRPRPINS_APB7_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_APB7_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRPINS_APB7_CTRL_MACRO__ */ + +/** @} end of apb7_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_apb8_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_apb8_ctrl apb8_ctrl + * @brief Contains register fields associated with apb8_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_APB8_CTRL_MACRO__ +#define __WRPRPINS_APB8_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRPINS_APB8_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRPINS_APB8_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRPINS_APB8_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRPINS_APB8_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB8_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB8_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_APB8_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_APB8_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_APB8_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_APB8_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRPINS_APB8_CTRL__SRESET__SHIFT 1 +#define WRPRPINS_APB8_CTRL__SRESET__WIDTH 1 +#define WRPRPINS_APB8_CTRL__SRESET__MASK 0x00000002U +#define WRPRPINS_APB8_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRPINS_APB8_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRPINS_APB8_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRPINS_APB8_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRPINS_APB8_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRPINS_APB8_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRPINS_APB8_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRPINS_APB8_CTRL__CLK_SEL__SHIFT 2 +#define WRPRPINS_APB8_CTRL__CLK_SEL__WIDTH 1 +#define WRPRPINS_APB8_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRPINS_APB8_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRPINS_APB8_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRPINS_APB8_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRPINS_APB8_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRPINS_APB8_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRPINS_APB8_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRPINS_APB8_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_APB8_CTRL__TYPE uint32_t +#define WRPRPINS_APB8_CTRL__READ 0x00000007U +#define WRPRPINS_APB8_CTRL__WRITE 0x00000007U +#define WRPRPINS_APB8_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_APB8_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRPINS_APB8_CTRL_MACRO__ */ + +/** @} end of apb8_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_apb9_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_apb9_ctrl apb9_ctrl + * @brief Contains register fields associated with apb9_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_APB9_CTRL_MACRO__ +#define __WRPRPINS_APB9_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRPINS_APB9_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRPINS_APB9_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRPINS_APB9_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRPINS_APB9_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB9_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB9_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_APB9_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_APB9_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_APB9_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_APB9_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRPINS_APB9_CTRL__SRESET__SHIFT 1 +#define WRPRPINS_APB9_CTRL__SRESET__WIDTH 1 +#define WRPRPINS_APB9_CTRL__SRESET__MASK 0x00000002U +#define WRPRPINS_APB9_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRPINS_APB9_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRPINS_APB9_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRPINS_APB9_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRPINS_APB9_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRPINS_APB9_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRPINS_APB9_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRPINS_APB9_CTRL__CLK_SEL__SHIFT 2 +#define WRPRPINS_APB9_CTRL__CLK_SEL__WIDTH 1 +#define WRPRPINS_APB9_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRPINS_APB9_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRPINS_APB9_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRPINS_APB9_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRPINS_APB9_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRPINS_APB9_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRPINS_APB9_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRPINS_APB9_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_APB9_CTRL__TYPE uint32_t +#define WRPRPINS_APB9_CTRL__READ 0x00000007U +#define WRPRPINS_APB9_CTRL__WRITE 0x00000007U +#define WRPRPINS_APB9_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_APB9_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRPINS_APB9_CTRL_MACRO__ */ + +/** @} end of apb9_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_apb10_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_apb10_ctrl apb10_ctrl + * @brief Contains register fields associated with apb10_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_APB10_CTRL_MACRO__ +#define __WRPRPINS_APB10_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRPINS_APB10_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRPINS_APB10_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRPINS_APB10_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRPINS_APB10_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB10_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB10_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_APB10_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_APB10_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_APB10_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_APB10_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRPINS_APB10_CTRL__SRESET__SHIFT 1 +#define WRPRPINS_APB10_CTRL__SRESET__WIDTH 1 +#define WRPRPINS_APB10_CTRL__SRESET__MASK 0x00000002U +#define WRPRPINS_APB10_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRPINS_APB10_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRPINS_APB10_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRPINS_APB10_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRPINS_APB10_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRPINS_APB10_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRPINS_APB10_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRPINS_APB10_CTRL__CLK_SEL__SHIFT 2 +#define WRPRPINS_APB10_CTRL__CLK_SEL__WIDTH 1 +#define WRPRPINS_APB10_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRPINS_APB10_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRPINS_APB10_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRPINS_APB10_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRPINS_APB10_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRPINS_APB10_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRPINS_APB10_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRPINS_APB10_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_APB10_CTRL__TYPE uint32_t +#define WRPRPINS_APB10_CTRL__READ 0x00000007U +#define WRPRPINS_APB10_CTRL__WRITE 0x00000007U +#define WRPRPINS_APB10_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_APB10_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRPINS_APB10_CTRL_MACRO__ */ + +/** @} end of apb10_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_apb11_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_apb11_ctrl apb11_ctrl + * @brief Contains register fields associated with apb11_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_APB11_CTRL_MACRO__ +#define __WRPRPINS_APB11_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRPINS_APB11_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRPINS_APB11_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRPINS_APB11_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRPINS_APB11_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB11_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB11_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_APB11_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_APB11_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_APB11_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_APB11_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRPINS_APB11_CTRL__SRESET__SHIFT 1 +#define WRPRPINS_APB11_CTRL__SRESET__WIDTH 1 +#define WRPRPINS_APB11_CTRL__SRESET__MASK 0x00000002U +#define WRPRPINS_APB11_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRPINS_APB11_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRPINS_APB11_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRPINS_APB11_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRPINS_APB11_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRPINS_APB11_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRPINS_APB11_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRPINS_APB11_CTRL__CLK_SEL__SHIFT 2 +#define WRPRPINS_APB11_CTRL__CLK_SEL__WIDTH 1 +#define WRPRPINS_APB11_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRPINS_APB11_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRPINS_APB11_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRPINS_APB11_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRPINS_APB11_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRPINS_APB11_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRPINS_APB11_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRPINS_APB11_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_APB11_CTRL__TYPE uint32_t +#define WRPRPINS_APB11_CTRL__READ 0x00000007U +#define WRPRPINS_APB11_CTRL__WRITE 0x00000007U +#define WRPRPINS_APB11_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_APB11_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRPINS_APB11_CTRL_MACRO__ */ + +/** @} end of apb11_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_apb12_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_apb12_ctrl apb12_ctrl + * @brief Contains register fields associated with apb12_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_APB12_CTRL_MACRO__ +#define __WRPRPINS_APB12_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRPINS_APB12_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRPINS_APB12_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRPINS_APB12_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRPINS_APB12_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB12_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB12_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_APB12_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_APB12_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_APB12_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_APB12_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRPINS_APB12_CTRL__SRESET__SHIFT 1 +#define WRPRPINS_APB12_CTRL__SRESET__WIDTH 1 +#define WRPRPINS_APB12_CTRL__SRESET__MASK 0x00000002U +#define WRPRPINS_APB12_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRPINS_APB12_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRPINS_APB12_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRPINS_APB12_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRPINS_APB12_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRPINS_APB12_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRPINS_APB12_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRPINS_APB12_CTRL__CLK_SEL__SHIFT 2 +#define WRPRPINS_APB12_CTRL__CLK_SEL__WIDTH 1 +#define WRPRPINS_APB12_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRPINS_APB12_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRPINS_APB12_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRPINS_APB12_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRPINS_APB12_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRPINS_APB12_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRPINS_APB12_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRPINS_APB12_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_APB12_CTRL__TYPE uint32_t +#define WRPRPINS_APB12_CTRL__READ 0x00000007U +#define WRPRPINS_APB12_CTRL__WRITE 0x00000007U +#define WRPRPINS_APB12_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_APB12_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRPINS_APB12_CTRL_MACRO__ */ + +/** @} end of apb12_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_apb13_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_apb13_ctrl apb13_ctrl + * @brief Contains register fields associated with apb13_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_APB13_CTRL_MACRO__ +#define __WRPRPINS_APB13_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRPINS_APB13_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRPINS_APB13_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRPINS_APB13_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRPINS_APB13_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB13_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB13_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_APB13_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_APB13_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_APB13_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_APB13_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRPINS_APB13_CTRL__SRESET__SHIFT 1 +#define WRPRPINS_APB13_CTRL__SRESET__WIDTH 1 +#define WRPRPINS_APB13_CTRL__SRESET__MASK 0x00000002U +#define WRPRPINS_APB13_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRPINS_APB13_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRPINS_APB13_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRPINS_APB13_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRPINS_APB13_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRPINS_APB13_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRPINS_APB13_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRPINS_APB13_CTRL__CLK_SEL__SHIFT 2 +#define WRPRPINS_APB13_CTRL__CLK_SEL__WIDTH 1 +#define WRPRPINS_APB13_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRPINS_APB13_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRPINS_APB13_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRPINS_APB13_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRPINS_APB13_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRPINS_APB13_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRPINS_APB13_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRPINS_APB13_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_APB13_CTRL__TYPE uint32_t +#define WRPRPINS_APB13_CTRL__READ 0x00000007U +#define WRPRPINS_APB13_CTRL__WRITE 0x00000007U +#define WRPRPINS_APB13_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_APB13_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRPINS_APB13_CTRL_MACRO__ */ + +/** @} end of apb13_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_apb14_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_apb14_ctrl apb14_ctrl + * @brief Contains register fields associated with apb14_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_APB14_CTRL_MACRO__ +#define __WRPRPINS_APB14_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRPINS_APB14_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRPINS_APB14_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRPINS_APB14_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRPINS_APB14_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB14_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB14_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_APB14_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_APB14_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_APB14_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_APB14_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRPINS_APB14_CTRL__SRESET__SHIFT 1 +#define WRPRPINS_APB14_CTRL__SRESET__WIDTH 1 +#define WRPRPINS_APB14_CTRL__SRESET__MASK 0x00000002U +#define WRPRPINS_APB14_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRPINS_APB14_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRPINS_APB14_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRPINS_APB14_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRPINS_APB14_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRPINS_APB14_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRPINS_APB14_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRPINS_APB14_CTRL__CLK_SEL__SHIFT 2 +#define WRPRPINS_APB14_CTRL__CLK_SEL__WIDTH 1 +#define WRPRPINS_APB14_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRPINS_APB14_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRPINS_APB14_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRPINS_APB14_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRPINS_APB14_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRPINS_APB14_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRPINS_APB14_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRPINS_APB14_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_APB14_CTRL__TYPE uint32_t +#define WRPRPINS_APB14_CTRL__READ 0x00000007U +#define WRPRPINS_APB14_CTRL__WRITE 0x00000007U +#define WRPRPINS_APB14_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_APB14_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRPINS_APB14_CTRL_MACRO__ */ + +/** @} end of apb14_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_apb15_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_apb15_ctrl apb15_ctrl + * @brief Contains register fields associated with apb15_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_APB15_CTRL_MACRO__ +#define __WRPRPINS_APB15_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRPINS_APB15_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRPINS_APB15_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRPINS_APB15_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRPINS_APB15_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB15_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_APB15_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_APB15_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_APB15_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_APB15_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_APB15_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRPINS_APB15_CTRL__SRESET__SHIFT 1 +#define WRPRPINS_APB15_CTRL__SRESET__WIDTH 1 +#define WRPRPINS_APB15_CTRL__SRESET__MASK 0x00000002U +#define WRPRPINS_APB15_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRPINS_APB15_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRPINS_APB15_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRPINS_APB15_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRPINS_APB15_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRPINS_APB15_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRPINS_APB15_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRPINS_APB15_CTRL__CLK_SEL__SHIFT 2 +#define WRPRPINS_APB15_CTRL__CLK_SEL__WIDTH 1 +#define WRPRPINS_APB15_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRPINS_APB15_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRPINS_APB15_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRPINS_APB15_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRPINS_APB15_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRPINS_APB15_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRPINS_APB15_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRPINS_APB15_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_APB15_CTRL__TYPE uint32_t +#define WRPRPINS_APB15_CTRL__READ 0x00000007U +#define WRPRPINS_APB15_CTRL__WRITE 0x00000007U +#define WRPRPINS_APB15_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_APB15_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRPINS_APB15_CTRL_MACRO__ */ + +/** @} end of apb15_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_clk_hpc_pin_out_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_hpc_pin_out_ctrl clk_hpc_pin_out_ctrl + * @brief Contains register fields associated with clk_hpc_pin_out_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_CLK_HPC_PIN_OUT_CTRL_MACRO__ +#define __WRPRPINS_CLK_HPC_PIN_OUT_CTRL_MACRO__ + +/* macros for field clk_hpc_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_hpc_sel_field clk_hpc_sel_field + * @brief macros for field clk_hpc_sel + * @{ + */ +#define WRPRPINS_CLK_HPC_PIN_OUT_CTRL__CLK_HPC_SEL__SHIFT 0 +#define WRPRPINS_CLK_HPC_PIN_OUT_CTRL__CLK_HPC_SEL__WIDTH 2 +#define WRPRPINS_CLK_HPC_PIN_OUT_CTRL__CLK_HPC_SEL__MASK 0x00000003U +#define WRPRPINS_CLK_HPC_PIN_OUT_CTRL__CLK_HPC_SEL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define WRPRPINS_CLK_HPC_PIN_OUT_CTRL__CLK_HPC_SEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define WRPRPINS_CLK_HPC_PIN_OUT_CTRL__CLK_HPC_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define WRPRPINS_CLK_HPC_PIN_OUT_CTRL__CLK_HPC_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define WRPRPINS_CLK_HPC_PIN_OUT_CTRL__CLK_HPC_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_CLK_HPC_PIN_OUT_CTRL__TYPE uint32_t +#define WRPRPINS_CLK_HPC_PIN_OUT_CTRL__READ 0x00000003U +#define WRPRPINS_CLK_HPC_PIN_OUT_CTRL__WRITE 0x00000003U +#define WRPRPINS_CLK_HPC_PIN_OUT_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_CLK_HPC_PIN_OUT_CTRL__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_CLK_HPC_PIN_OUT_CTRL_MACRO__ */ + +/** @} end of clk_hpc_pin_out_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_clk_mpc_pin_out_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_mpc_pin_out_ctrl clk_mpc_pin_out_ctrl + * @brief Contains register fields associated with clk_mpc_pin_out_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_CLK_MPC_PIN_OUT_CTRL_MACRO__ +#define __WRPRPINS_CLK_MPC_PIN_OUT_CTRL_MACRO__ + +/* macros for field clk_mpc_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_mpc_sel_field clk_mpc_sel_field + * @brief macros for field clk_mpc_sel + * @{ + */ +#define WRPRPINS_CLK_MPC_PIN_OUT_CTRL__CLK_MPC_SEL__SHIFT 0 +#define WRPRPINS_CLK_MPC_PIN_OUT_CTRL__CLK_MPC_SEL__WIDTH 2 +#define WRPRPINS_CLK_MPC_PIN_OUT_CTRL__CLK_MPC_SEL__MASK 0x00000003U +#define WRPRPINS_CLK_MPC_PIN_OUT_CTRL__CLK_MPC_SEL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define WRPRPINS_CLK_MPC_PIN_OUT_CTRL__CLK_MPC_SEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define WRPRPINS_CLK_MPC_PIN_OUT_CTRL__CLK_MPC_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define WRPRPINS_CLK_MPC_PIN_OUT_CTRL__CLK_MPC_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define WRPRPINS_CLK_MPC_PIN_OUT_CTRL__CLK_MPC_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_CLK_MPC_PIN_OUT_CTRL__TYPE uint32_t +#define WRPRPINS_CLK_MPC_PIN_OUT_CTRL__READ 0x00000003U +#define WRPRPINS_CLK_MPC_PIN_OUT_CTRL__WRITE 0x00000003U +#define WRPRPINS_CLK_MPC_PIN_OUT_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_CLK_MPC_PIN_OUT_CTRL__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_CLK_MPC_PIN_OUT_CTRL_MACRO__ */ + +/** @} end of clk_mpc_pin_out_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_clk_lpc_pin_out_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_lpc_pin_out_ctrl clk_lpc_pin_out_ctrl + * @brief Contains register fields associated with clk_lpc_pin_out_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_CLK_LPC_PIN_OUT_CTRL_MACRO__ +#define __WRPRPINS_CLK_LPC_PIN_OUT_CTRL_MACRO__ + +/* macros for field clk_lpc_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_clk_lpc_sel_field clk_lpc_sel_field + * @brief macros for field clk_lpc_sel + * @{ + */ +#define WRPRPINS_CLK_LPC_PIN_OUT_CTRL__CLK_LPC_SEL__SHIFT 0 +#define WRPRPINS_CLK_LPC_PIN_OUT_CTRL__CLK_LPC_SEL__WIDTH 1 +#define WRPRPINS_CLK_LPC_PIN_OUT_CTRL__CLK_LPC_SEL__MASK 0x00000001U +#define WRPRPINS_CLK_LPC_PIN_OUT_CTRL__CLK_LPC_SEL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_CLK_LPC_PIN_OUT_CTRL__CLK_LPC_SEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_CLK_LPC_PIN_OUT_CTRL__CLK_LPC_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_CLK_LPC_PIN_OUT_CTRL__CLK_LPC_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_CLK_LPC_PIN_OUT_CTRL__CLK_LPC_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_CLK_LPC_PIN_OUT_CTRL__CLK_LPC_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_CLK_LPC_PIN_OUT_CTRL__CLK_LPC_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_CLK_LPC_PIN_OUT_CTRL__TYPE uint32_t +#define WRPRPINS_CLK_LPC_PIN_OUT_CTRL__READ 0x00000001U +#define WRPRPINS_CLK_LPC_PIN_OUT_CTRL__WRITE 0x00000001U +#define WRPRPINS_CLK_LPC_PIN_OUT_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_CLK_LPC_PIN_OUT_CTRL__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_CLK_LPC_PIN_OUT_CTRL_MACRO__ */ + +/** @} end of clk_lpc_pin_out_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_dbg_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_dbg_ctrl dbg_ctrl + * @brief Contains register fields associated with dbg_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_DBG_CTRL_MACRO__ +#define __WRPRPINS_DBG_CTRL_MACRO__ + +/* macros for field dbg_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_dbg_sel_field dbg_sel_field + * @brief macros for field dbg_sel + * @{ + */ +#define WRPRPINS_DBG_CTRL__DBG_SEL__SHIFT 0 +#define WRPRPINS_DBG_CTRL__DBG_SEL__WIDTH 4 +#define WRPRPINS_DBG_CTRL__DBG_SEL__MASK 0x0000000fU +#define WRPRPINS_DBG_CTRL__DBG_SEL__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define WRPRPINS_DBG_CTRL__DBG_SEL__WRITE(src) ((uint32_t)(src) & 0x0000000fU) +#define WRPRPINS_DBG_CTRL__DBG_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define WRPRPINS_DBG_CTRL__DBG_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define WRPRPINS_DBG_CTRL__DBG_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dbg_shft */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_dbg_shft_field dbg_shft_field + * @brief macros for field dbg_shft + * @{ + */ +#define WRPRPINS_DBG_CTRL__DBG_SHFT__SHIFT 4 +#define WRPRPINS_DBG_CTRL__DBG_SHFT__WIDTH 3 +#define WRPRPINS_DBG_CTRL__DBG_SHFT__MASK 0x00000070U +#define WRPRPINS_DBG_CTRL__DBG_SHFT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000070U) >> 4) +#define WRPRPINS_DBG_CTRL__DBG_SHFT__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000070U) +#define WRPRPINS_DBG_CTRL__DBG_SHFT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((uint32_t)(src) <<\ + 4) & 0x00000070U) +#define WRPRPINS_DBG_CTRL__DBG_SHFT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000070U))) +#define WRPRPINS_DBG_CTRL__DBG_SHFT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dbg_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_dbg_enable_field dbg_enable_field + * @brief macros for field dbg_enable + * @{ + */ +#define WRPRPINS_DBG_CTRL__DBG_ENABLE__SHIFT 7 +#define WRPRPINS_DBG_CTRL__DBG_ENABLE__WIDTH 1 +#define WRPRPINS_DBG_CTRL__DBG_ENABLE__MASK 0x00000080U +#define WRPRPINS_DBG_CTRL__DBG_ENABLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define WRPRPINS_DBG_CTRL__DBG_ENABLE__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define WRPRPINS_DBG_CTRL__DBG_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define WRPRPINS_DBG_CTRL__DBG_ENABLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define WRPRPINS_DBG_CTRL__DBG_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define WRPRPINS_DBG_CTRL__DBG_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define WRPRPINS_DBG_CTRL__DBG_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field em_block_wdata */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_em_block_wdata_field em_block_wdata_field + * @brief macros for field em_block_wdata + * @details not intended to be used; helps with cpf isolation issues + * @{ + */ +#define WRPRPINS_DBG_CTRL__EM_BLOCK_WDATA__SHIFT 8 +#define WRPRPINS_DBG_CTRL__EM_BLOCK_WDATA__WIDTH 1 +#define WRPRPINS_DBG_CTRL__EM_BLOCK_WDATA__MASK 0x00000100U +#define WRPRPINS_DBG_CTRL__EM_BLOCK_WDATA__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define WRPRPINS_DBG_CTRL__EM_BLOCK_WDATA__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define WRPRPINS_DBG_CTRL__EM_BLOCK_WDATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define WRPRPINS_DBG_CTRL__EM_BLOCK_WDATA__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define WRPRPINS_DBG_CTRL__EM_BLOCK_WDATA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define WRPRPINS_DBG_CTRL__EM_BLOCK_WDATA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define WRPRPINS_DBG_CTRL__EM_BLOCK_WDATA__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field em_block_addr */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_em_block_addr_field em_block_addr_field + * @brief macros for field em_block_addr + * @details not intended to be used; helps with cpf isolation issues + * @{ + */ +#define WRPRPINS_DBG_CTRL__EM_BLOCK_ADDR__SHIFT 9 +#define WRPRPINS_DBG_CTRL__EM_BLOCK_ADDR__WIDTH 1 +#define WRPRPINS_DBG_CTRL__EM_BLOCK_ADDR__MASK 0x00000200U +#define WRPRPINS_DBG_CTRL__EM_BLOCK_ADDR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define WRPRPINS_DBG_CTRL__EM_BLOCK_ADDR__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define WRPRPINS_DBG_CTRL__EM_BLOCK_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define WRPRPINS_DBG_CTRL__EM_BLOCK_ADDR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define WRPRPINS_DBG_CTRL__EM_BLOCK_ADDR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define WRPRPINS_DBG_CTRL__EM_BLOCK_ADDR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define WRPRPINS_DBG_CTRL__EM_BLOCK_ADDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sse200_certdisableext */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sse200_certdisableext_field sse200_certdisableext_field + * @brief macros for field sse200_certdisableext + * @{ + */ +#define WRPRPINS_DBG_CTRL__SSE200_CERTDISABLEEXT__SHIFT 10 +#define WRPRPINS_DBG_CTRL__SSE200_CERTDISABLEEXT__WIDTH 1 +#define WRPRPINS_DBG_CTRL__SSE200_CERTDISABLEEXT__MASK 0x00000400U +#define WRPRPINS_DBG_CTRL__SSE200_CERTDISABLEEXT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define WRPRPINS_DBG_CTRL__SSE200_CERTDISABLEEXT__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define WRPRPINS_DBG_CTRL__SSE200_CERTDISABLEEXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define WRPRPINS_DBG_CTRL__SSE200_CERTDISABLEEXT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define WRPRPINS_DBG_CTRL__SSE200_CERTDISABLEEXT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define WRPRPINS_DBG_CTRL__SSE200_CERTDISABLEEXT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define WRPRPINS_DBG_CTRL__SSE200_CERTDISABLEEXT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sse200_niden_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sse200_niden_sel_field sse200_niden_sel_field + * @brief macros for field sse200_niden_sel + * @{ + */ +#define WRPRPINS_DBG_CTRL__SSE200_NIDEN_SEL__SHIFT 11 +#define WRPRPINS_DBG_CTRL__SSE200_NIDEN_SEL__WIDTH 1 +#define WRPRPINS_DBG_CTRL__SSE200_NIDEN_SEL__MASK 0x00000800U +#define WRPRPINS_DBG_CTRL__SSE200_NIDEN_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define WRPRPINS_DBG_CTRL__SSE200_NIDEN_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define WRPRPINS_DBG_CTRL__SSE200_NIDEN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define WRPRPINS_DBG_CTRL__SSE200_NIDEN_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define WRPRPINS_DBG_CTRL__SSE200_NIDEN_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define WRPRPINS_DBG_CTRL__SSE200_NIDEN_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define WRPRPINS_DBG_CTRL__SSE200_NIDEN_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sse200_dbgen_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sse200_dbgen_sel_field sse200_dbgen_sel_field + * @brief macros for field sse200_dbgen_sel + * @{ + */ +#define WRPRPINS_DBG_CTRL__SSE200_DBGEN_SEL__SHIFT 12 +#define WRPRPINS_DBG_CTRL__SSE200_DBGEN_SEL__WIDTH 1 +#define WRPRPINS_DBG_CTRL__SSE200_DBGEN_SEL__MASK 0x00001000U +#define WRPRPINS_DBG_CTRL__SSE200_DBGEN_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define WRPRPINS_DBG_CTRL__SSE200_DBGEN_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define WRPRPINS_DBG_CTRL__SSE200_DBGEN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define WRPRPINS_DBG_CTRL__SSE200_DBGEN_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define WRPRPINS_DBG_CTRL__SSE200_DBGEN_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define WRPRPINS_DBG_CTRL__SSE200_DBGEN_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define WRPRPINS_DBG_CTRL__SSE200_DBGEN_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sse200_exp_mpc_g_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sse200_exp_mpc_g_sel_field sse200_exp_mpc_g_sel_field + * @brief macros for field sse200_exp_mpc_g_sel + * @{ + */ +#define WRPRPINS_DBG_CTRL__SSE200_EXP_MPC_G_SEL__SHIFT 13 +#define WRPRPINS_DBG_CTRL__SSE200_EXP_MPC_G_SEL__WIDTH 1 +#define WRPRPINS_DBG_CTRL__SSE200_EXP_MPC_G_SEL__MASK 0x00002000U +#define WRPRPINS_DBG_CTRL__SSE200_EXP_MPC_G_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define WRPRPINS_DBG_CTRL__SSE200_EXP_MPC_G_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define WRPRPINS_DBG_CTRL__SSE200_EXP_MPC_G_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define WRPRPINS_DBG_CTRL__SSE200_EXP_MPC_G_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define WRPRPINS_DBG_CTRL__SSE200_EXP_MPC_G_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define WRPRPINS_DBG_CTRL__SSE200_EXP_MPC_G_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define WRPRPINS_DBG_CTRL__SSE200_EXP_MPC_G_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sse200_sysfclkqactive */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sse200_sysfclkqactive_field sse200_sysfclkqactive_field + * @brief macros for field sse200_sysfclkqactive + * @{ + */ +#define WRPRPINS_DBG_CTRL__SSE200_SYSFCLKQACTIVE__SHIFT 14 +#define WRPRPINS_DBG_CTRL__SSE200_SYSFCLKQACTIVE__WIDTH 1 +#define WRPRPINS_DBG_CTRL__SSE200_SYSFCLKQACTIVE__MASK 0x00004000U +#define WRPRPINS_DBG_CTRL__SSE200_SYSFCLKQACTIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define WRPRPINS_DBG_CTRL__SSE200_SYSFCLKQACTIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define WRPRPINS_DBG_CTRL__SSE200_SYSFCLKQACTIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define WRPRPINS_DBG_CTRL__SSE200_SYSFCLKQACTIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define WRPRPINS_DBG_CTRL__SSE200_SYSFCLKQACTIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define WRPRPINS_DBG_CTRL__SSE200_SYSFCLKQACTIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define WRPRPINS_DBG_CTRL__SSE200_SYSFCLKQACTIVE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field sse200_expclkreq_in */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sse200_expclkreq_in_field sse200_expclkreq_in_field + * @brief macros for field sse200_expclkreq_in + * @{ + */ +#define WRPRPINS_DBG_CTRL__SSE200_EXPCLKREQ_IN__SHIFT 15 +#define WRPRPINS_DBG_CTRL__SSE200_EXPCLKREQ_IN__WIDTH 1 +#define WRPRPINS_DBG_CTRL__SSE200_EXPCLKREQ_IN__MASK 0x00008000U +#define WRPRPINS_DBG_CTRL__SSE200_EXPCLKREQ_IN__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define WRPRPINS_DBG_CTRL__SSE200_EXPCLKREQ_IN__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define WRPRPINS_DBG_CTRL__SSE200_EXPCLKREQ_IN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define WRPRPINS_DBG_CTRL__SSE200_EXPCLKREQ_IN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define WRPRPINS_DBG_CTRL__SSE200_EXPCLKREQ_IN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define WRPRPINS_DBG_CTRL__SSE200_EXPCLKREQ_IN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define WRPRPINS_DBG_CTRL__SSE200_EXPCLKREQ_IN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field sse200_exp_nmi */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sse200_exp_nmi_field sse200_exp_nmi_field + * @brief macros for field sse200_exp_nmi + * @{ + */ +#define WRPRPINS_DBG_CTRL__SSE200_EXP_NMI__SHIFT 16 +#define WRPRPINS_DBG_CTRL__SSE200_EXP_NMI__WIDTH 1 +#define WRPRPINS_DBG_CTRL__SSE200_EXP_NMI__MASK 0x00010000U +#define WRPRPINS_DBG_CTRL__SSE200_EXP_NMI__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define WRPRPINS_DBG_CTRL__SSE200_EXP_NMI__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define WRPRPINS_DBG_CTRL__SSE200_EXP_NMI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define WRPRPINS_DBG_CTRL__SSE200_EXP_NMI__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define WRPRPINS_DBG_CTRL__SSE200_EXP_NMI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define WRPRPINS_DBG_CTRL__SSE200_EXP_NMI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define WRPRPINS_DBG_CTRL__SSE200_EXP_NMI__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sse200_mstexp1_clk_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sse200_mstexp1_clk_enable_field sse200_mstexp1_clk_enable_field + * @brief macros for field sse200_mstexp1_clk_enable + * @{ + */ +#define WRPRPINS_DBG_CTRL__SSE200_MSTEXP1_CLK_ENABLE__SHIFT 17 +#define WRPRPINS_DBG_CTRL__SSE200_MSTEXP1_CLK_ENABLE__WIDTH 1 +#define WRPRPINS_DBG_CTRL__SSE200_MSTEXP1_CLK_ENABLE__MASK 0x00020000U +#define WRPRPINS_DBG_CTRL__SSE200_MSTEXP1_CLK_ENABLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define WRPRPINS_DBG_CTRL__SSE200_MSTEXP1_CLK_ENABLE__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define WRPRPINS_DBG_CTRL__SSE200_MSTEXP1_CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define WRPRPINS_DBG_CTRL__SSE200_MSTEXP1_CLK_ENABLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define WRPRPINS_DBG_CTRL__SSE200_MSTEXP1_CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define WRPRPINS_DBG_CTRL__SSE200_MSTEXP1_CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define WRPRPINS_DBG_CTRL__SSE200_MSTEXP1_CLK_ENABLE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field sse200_mstexp0_clk_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sse200_mstexp0_clk_enable_field sse200_mstexp0_clk_enable_field + * @brief macros for field sse200_mstexp0_clk_enable + * @{ + */ +#define WRPRPINS_DBG_CTRL__SSE200_MSTEXP0_CLK_ENABLE__SHIFT 18 +#define WRPRPINS_DBG_CTRL__SSE200_MSTEXP0_CLK_ENABLE__WIDTH 1 +#define WRPRPINS_DBG_CTRL__SSE200_MSTEXP0_CLK_ENABLE__MASK 0x00040000U +#define WRPRPINS_DBG_CTRL__SSE200_MSTEXP0_CLK_ENABLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define WRPRPINS_DBG_CTRL__SSE200_MSTEXP0_CLK_ENABLE__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define WRPRPINS_DBG_CTRL__SSE200_MSTEXP0_CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define WRPRPINS_DBG_CTRL__SSE200_MSTEXP0_CLK_ENABLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define WRPRPINS_DBG_CTRL__SSE200_MSTEXP0_CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define WRPRPINS_DBG_CTRL__SSE200_MSTEXP0_CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define WRPRPINS_DBG_CTRL__SSE200_MSTEXP0_CLK_ENABLE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field trigger_soc_rst */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_trigger_soc_rst_field trigger_soc_rst_field + * @brief macros for field trigger_soc_rst + * @{ + */ +#define WRPRPINS_DBG_CTRL__TRIGGER_SOC_RST__SHIFT 19 +#define WRPRPINS_DBG_CTRL__TRIGGER_SOC_RST__WIDTH 1 +#define WRPRPINS_DBG_CTRL__TRIGGER_SOC_RST__MASK 0x00080000U +#define WRPRPINS_DBG_CTRL__TRIGGER_SOC_RST__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define WRPRPINS_DBG_CTRL__TRIGGER_SOC_RST__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define WRPRPINS_DBG_CTRL__TRIGGER_SOC_RST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define WRPRPINS_DBG_CTRL__TRIGGER_SOC_RST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define WRPRPINS_DBG_CTRL__TRIGGER_SOC_RST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define WRPRPINS_DBG_CTRL__TRIGGER_SOC_RST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define WRPRPINS_DBG_CTRL__TRIGGER_SOC_RST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field trace_is_ddr */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_trace_is_ddr_field trace_is_ddr_field + * @brief macros for field trace_is_ddr + * @{ + */ +#define WRPRPINS_DBG_CTRL__TRACE_IS_DDR__SHIFT 20 +#define WRPRPINS_DBG_CTRL__TRACE_IS_DDR__WIDTH 1 +#define WRPRPINS_DBG_CTRL__TRACE_IS_DDR__MASK 0x00100000U +#define WRPRPINS_DBG_CTRL__TRACE_IS_DDR__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define WRPRPINS_DBG_CTRL__TRACE_IS_DDR__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define WRPRPINS_DBG_CTRL__TRACE_IS_DDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define WRPRPINS_DBG_CTRL__TRACE_IS_DDR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define WRPRPINS_DBG_CTRL__TRACE_IS_DDR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define WRPRPINS_DBG_CTRL__TRACE_IS_DDR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define WRPRPINS_DBG_CTRL__TRACE_IS_DDR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dbg_skip_6x6_holes */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_dbg_skip_6x6_holes_field dbg_skip_6x6_holes_field + * @brief macros for field dbg_skip_6x6_holes + * @{ + */ +#define WRPRPINS_DBG_CTRL__DBG_SKIP_6X6_HOLES__SHIFT 21 +#define WRPRPINS_DBG_CTRL__DBG_SKIP_6X6_HOLES__WIDTH 1 +#define WRPRPINS_DBG_CTRL__DBG_SKIP_6X6_HOLES__MASK 0x00200000U +#define WRPRPINS_DBG_CTRL__DBG_SKIP_6X6_HOLES__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define WRPRPINS_DBG_CTRL__DBG_SKIP_6X6_HOLES__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define WRPRPINS_DBG_CTRL__DBG_SKIP_6X6_HOLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define WRPRPINS_DBG_CTRL__DBG_SKIP_6X6_HOLES__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define WRPRPINS_DBG_CTRL__DBG_SKIP_6X6_HOLES__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define WRPRPINS_DBG_CTRL__DBG_SKIP_6X6_HOLES__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define WRPRPINS_DBG_CTRL__DBG_SKIP_6X6_HOLES__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dbg_cg */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_dbg_cg_field dbg_cg_field + * @brief macros for field dbg_cg + * @{ + */ +#define WRPRPINS_DBG_CTRL__DBG_CG__SHIFT 22 +#define WRPRPINS_DBG_CTRL__DBG_CG__WIDTH 1 +#define WRPRPINS_DBG_CTRL__DBG_CG__MASK 0x00400000U +#define WRPRPINS_DBG_CTRL__DBG_CG__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define WRPRPINS_DBG_CTRL__DBG_CG__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define WRPRPINS_DBG_CTRL__DBG_CG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define WRPRPINS_DBG_CTRL__DBG_CG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define WRPRPINS_DBG_CTRL__DBG_CG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define WRPRPINS_DBG_CTRL__DBG_CG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define WRPRPINS_DBG_CTRL__DBG_CG__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_DBG_CTRL__TYPE uint32_t +#define WRPRPINS_DBG_CTRL__READ 0x007fffffU +#define WRPRPINS_DBG_CTRL__WRITE 0x007fffffU +#define WRPRPINS_DBG_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_DBG_CTRL__RESET_VALUE 0x0006c000U + +#endif /* __WRPRPINS_DBG_CTRL_MACRO__ */ + +/** @} end of dbg_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_psel_A */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_psel_A psel_A + * @brief Contains register fields associated with psel_A. definitions. + * @{ + */ +#ifndef __WRPRPINS_PSEL_A_MACRO__ +#define __WRPRPINS_PSEL_A_MACRO__ + +/* macros for field p0_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p0_sel_field p0_sel_field + * @brief macros for field p0_sel + * @details by default P0 is SWDCLK + * @{ + */ +#define WRPRPINS_PSEL_A__P0_SEL__SHIFT 0 +#define WRPRPINS_PSEL_A__P0_SEL__WIDTH 8 +#define WRPRPINS_PSEL_A__P0_SEL__MASK 0x000000ffU +#define WRPRPINS_PSEL_A__P0_SEL__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define WRPRPINS_PSEL_A__P0_SEL__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define WRPRPINS_PSEL_A__P0_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define WRPRPINS_PSEL_A__P0_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define WRPRPINS_PSEL_A__P0_SEL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field p1_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p1_sel_field p1_sel_field + * @brief macros for field p1_sel + * @details by default P1 is SWDIO + * @{ + */ +#define WRPRPINS_PSEL_A__P1_SEL__SHIFT 8 +#define WRPRPINS_PSEL_A__P1_SEL__WIDTH 8 +#define WRPRPINS_PSEL_A__P1_SEL__MASK 0x0000ff00U +#define WRPRPINS_PSEL_A__P1_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define WRPRPINS_PSEL_A__P1_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define WRPRPINS_PSEL_A__P1_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define WRPRPINS_PSEL_A__P1_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define WRPRPINS_PSEL_A__P1_SEL__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field p2_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p2_sel_field p2_sel_field + * @brief macros for field p2_sel + * @{ + */ +#define WRPRPINS_PSEL_A__P2_SEL__SHIFT 16 +#define WRPRPINS_PSEL_A__P2_SEL__WIDTH 8 +#define WRPRPINS_PSEL_A__P2_SEL__MASK 0x00ff0000U +#define WRPRPINS_PSEL_A__P2_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define WRPRPINS_PSEL_A__P2_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define WRPRPINS_PSEL_A__P2_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define WRPRPINS_PSEL_A__P2_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define WRPRPINS_PSEL_A__P2_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p3_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p3_sel_field p3_sel_field + * @brief macros for field p3_sel + * @{ + */ +#define WRPRPINS_PSEL_A__P3_SEL__SHIFT 24 +#define WRPRPINS_PSEL_A__P3_SEL__WIDTH 8 +#define WRPRPINS_PSEL_A__P3_SEL__MASK 0xff000000U +#define WRPRPINS_PSEL_A__P3_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define WRPRPINS_PSEL_A__P3_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define WRPRPINS_PSEL_A__P3_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define WRPRPINS_PSEL_A__P3_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define WRPRPINS_PSEL_A__P3_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_PSEL_A__TYPE uint32_t +#define WRPRPINS_PSEL_A__READ 0xffffffffU +#define WRPRPINS_PSEL_A__WRITE 0xffffffffU +#define WRPRPINS_PSEL_A__PRESERVED 0x00000000U +#define WRPRPINS_PSEL_A__RESET_VALUE 0x00000201U + +#endif /* __WRPRPINS_PSEL_A_MACRO__ */ + +/** @} end of psel_A */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_psel_B */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_psel_B psel_B + * @brief Contains register fields associated with psel_B. definitions. + * @{ + */ +#ifndef __WRPRPINS_PSEL_B_MACRO__ +#define __WRPRPINS_PSEL_B_MACRO__ + +/* macros for field p4_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p4_sel_field p4_sel_field + * @brief macros for field p4_sel + * @{ + */ +#define WRPRPINS_PSEL_B__P4_SEL__SHIFT 0 +#define WRPRPINS_PSEL_B__P4_SEL__WIDTH 8 +#define WRPRPINS_PSEL_B__P4_SEL__MASK 0x000000ffU +#define WRPRPINS_PSEL_B__P4_SEL__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define WRPRPINS_PSEL_B__P4_SEL__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define WRPRPINS_PSEL_B__P4_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define WRPRPINS_PSEL_B__P4_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define WRPRPINS_PSEL_B__P4_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p5_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p5_sel_field p5_sel_field + * @brief macros for field p5_sel + * @{ + */ +#define WRPRPINS_PSEL_B__P5_SEL__SHIFT 8 +#define WRPRPINS_PSEL_B__P5_SEL__WIDTH 8 +#define WRPRPINS_PSEL_B__P5_SEL__MASK 0x0000ff00U +#define WRPRPINS_PSEL_B__P5_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define WRPRPINS_PSEL_B__P5_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define WRPRPINS_PSEL_B__P5_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define WRPRPINS_PSEL_B__P5_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define WRPRPINS_PSEL_B__P5_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p6_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p6_sel_field p6_sel_field + * @brief macros for field p6_sel + * @{ + */ +#define WRPRPINS_PSEL_B__P6_SEL__SHIFT 16 +#define WRPRPINS_PSEL_B__P6_SEL__WIDTH 8 +#define WRPRPINS_PSEL_B__P6_SEL__MASK 0x00ff0000U +#define WRPRPINS_PSEL_B__P6_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define WRPRPINS_PSEL_B__P6_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define WRPRPINS_PSEL_B__P6_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define WRPRPINS_PSEL_B__P6_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define WRPRPINS_PSEL_B__P6_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p7_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p7_sel_field p7_sel_field + * @brief macros for field p7_sel + * @{ + */ +#define WRPRPINS_PSEL_B__P7_SEL__SHIFT 24 +#define WRPRPINS_PSEL_B__P7_SEL__WIDTH 8 +#define WRPRPINS_PSEL_B__P7_SEL__MASK 0xff000000U +#define WRPRPINS_PSEL_B__P7_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define WRPRPINS_PSEL_B__P7_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define WRPRPINS_PSEL_B__P7_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define WRPRPINS_PSEL_B__P7_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define WRPRPINS_PSEL_B__P7_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_PSEL_B__TYPE uint32_t +#define WRPRPINS_PSEL_B__READ 0xffffffffU +#define WRPRPINS_PSEL_B__WRITE 0xffffffffU +#define WRPRPINS_PSEL_B__PRESERVED 0x00000000U +#define WRPRPINS_PSEL_B__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_PSEL_B_MACRO__ */ + +/** @} end of psel_B */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_psel_C */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_psel_C psel_C + * @brief Contains register fields associated with psel_C. definitions. + * @{ + */ +#ifndef __WRPRPINS_PSEL_C_MACRO__ +#define __WRPRPINS_PSEL_C_MACRO__ + +/* macros for field p8_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p8_sel_field p8_sel_field + * @brief macros for field p8_sel + * @{ + */ +#define WRPRPINS_PSEL_C__P8_SEL__SHIFT 0 +#define WRPRPINS_PSEL_C__P8_SEL__WIDTH 8 +#define WRPRPINS_PSEL_C__P8_SEL__MASK 0x000000ffU +#define WRPRPINS_PSEL_C__P8_SEL__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define WRPRPINS_PSEL_C__P8_SEL__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define WRPRPINS_PSEL_C__P8_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define WRPRPINS_PSEL_C__P8_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define WRPRPINS_PSEL_C__P8_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p9_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p9_sel_field p9_sel_field + * @brief macros for field p9_sel + * @{ + */ +#define WRPRPINS_PSEL_C__P9_SEL__SHIFT 8 +#define WRPRPINS_PSEL_C__P9_SEL__WIDTH 8 +#define WRPRPINS_PSEL_C__P9_SEL__MASK 0x0000ff00U +#define WRPRPINS_PSEL_C__P9_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define WRPRPINS_PSEL_C__P9_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define WRPRPINS_PSEL_C__P9_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define WRPRPINS_PSEL_C__P9_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define WRPRPINS_PSEL_C__P9_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p10_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p10_sel_field p10_sel_field + * @brief macros for field p10_sel + * @{ + */ +#define WRPRPINS_PSEL_C__P10_SEL__SHIFT 16 +#define WRPRPINS_PSEL_C__P10_SEL__WIDTH 8 +#define WRPRPINS_PSEL_C__P10_SEL__MASK 0x00ff0000U +#define WRPRPINS_PSEL_C__P10_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define WRPRPINS_PSEL_C__P10_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define WRPRPINS_PSEL_C__P10_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define WRPRPINS_PSEL_C__P10_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define WRPRPINS_PSEL_C__P10_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p11_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p11_sel_field p11_sel_field + * @brief macros for field p11_sel + * @{ + */ +#define WRPRPINS_PSEL_C__P11_SEL__SHIFT 24 +#define WRPRPINS_PSEL_C__P11_SEL__WIDTH 8 +#define WRPRPINS_PSEL_C__P11_SEL__MASK 0xff000000U +#define WRPRPINS_PSEL_C__P11_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define WRPRPINS_PSEL_C__P11_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define WRPRPINS_PSEL_C__P11_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define WRPRPINS_PSEL_C__P11_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define WRPRPINS_PSEL_C__P11_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_PSEL_C__TYPE uint32_t +#define WRPRPINS_PSEL_C__READ 0xffffffffU +#define WRPRPINS_PSEL_C__WRITE 0xffffffffU +#define WRPRPINS_PSEL_C__PRESERVED 0x00000000U +#define WRPRPINS_PSEL_C__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_PSEL_C_MACRO__ */ + +/** @} end of psel_C */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_psel_D */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_psel_D psel_D + * @brief Contains register fields associated with psel_D. definitions. + * @{ + */ +#ifndef __WRPRPINS_PSEL_D_MACRO__ +#define __WRPRPINS_PSEL_D_MACRO__ + +/* macros for field p12_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p12_sel_field p12_sel_field + * @brief macros for field p12_sel + * @{ + */ +#define WRPRPINS_PSEL_D__P12_SEL__SHIFT 0 +#define WRPRPINS_PSEL_D__P12_SEL__WIDTH 8 +#define WRPRPINS_PSEL_D__P12_SEL__MASK 0x000000ffU +#define WRPRPINS_PSEL_D__P12_SEL__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define WRPRPINS_PSEL_D__P12_SEL__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define WRPRPINS_PSEL_D__P12_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define WRPRPINS_PSEL_D__P12_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define WRPRPINS_PSEL_D__P12_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p13_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p13_sel_field p13_sel_field + * @brief macros for field p13_sel + * @{ + */ +#define WRPRPINS_PSEL_D__P13_SEL__SHIFT 8 +#define WRPRPINS_PSEL_D__P13_SEL__WIDTH 8 +#define WRPRPINS_PSEL_D__P13_SEL__MASK 0x0000ff00U +#define WRPRPINS_PSEL_D__P13_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define WRPRPINS_PSEL_D__P13_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define WRPRPINS_PSEL_D__P13_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define WRPRPINS_PSEL_D__P13_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define WRPRPINS_PSEL_D__P13_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p14_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p14_sel_field p14_sel_field + * @brief macros for field p14_sel + * @{ + */ +#define WRPRPINS_PSEL_D__P14_SEL__SHIFT 16 +#define WRPRPINS_PSEL_D__P14_SEL__WIDTH 8 +#define WRPRPINS_PSEL_D__P14_SEL__MASK 0x00ff0000U +#define WRPRPINS_PSEL_D__P14_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define WRPRPINS_PSEL_D__P14_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define WRPRPINS_PSEL_D__P14_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define WRPRPINS_PSEL_D__P14_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define WRPRPINS_PSEL_D__P14_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p15_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p15_sel_field p15_sel_field + * @brief macros for field p15_sel + * @{ + */ +#define WRPRPINS_PSEL_D__P15_SEL__SHIFT 24 +#define WRPRPINS_PSEL_D__P15_SEL__WIDTH 8 +#define WRPRPINS_PSEL_D__P15_SEL__MASK 0xff000000U +#define WRPRPINS_PSEL_D__P15_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define WRPRPINS_PSEL_D__P15_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define WRPRPINS_PSEL_D__P15_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define WRPRPINS_PSEL_D__P15_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define WRPRPINS_PSEL_D__P15_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_PSEL_D__TYPE uint32_t +#define WRPRPINS_PSEL_D__READ 0xffffffffU +#define WRPRPINS_PSEL_D__WRITE 0xffffffffU +#define WRPRPINS_PSEL_D__PRESERVED 0x00000000U +#define WRPRPINS_PSEL_D__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_PSEL_D_MACRO__ */ + +/** @} end of psel_D */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_psel_E */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_psel_E psel_E + * @brief Contains register fields associated with psel_E. definitions. + * @{ + */ +#ifndef __WRPRPINS_PSEL_E_MACRO__ +#define __WRPRPINS_PSEL_E_MACRO__ + +/* macros for field p16_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p16_sel_field p16_sel_field + * @brief macros for field p16_sel + * @{ + */ +#define WRPRPINS_PSEL_E__P16_SEL__SHIFT 0 +#define WRPRPINS_PSEL_E__P16_SEL__WIDTH 8 +#define WRPRPINS_PSEL_E__P16_SEL__MASK 0x000000ffU +#define WRPRPINS_PSEL_E__P16_SEL__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define WRPRPINS_PSEL_E__P16_SEL__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define WRPRPINS_PSEL_E__P16_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define WRPRPINS_PSEL_E__P16_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define WRPRPINS_PSEL_E__P16_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p17_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p17_sel_field p17_sel_field + * @brief macros for field p17_sel + * @{ + */ +#define WRPRPINS_PSEL_E__P17_SEL__SHIFT 8 +#define WRPRPINS_PSEL_E__P17_SEL__WIDTH 8 +#define WRPRPINS_PSEL_E__P17_SEL__MASK 0x0000ff00U +#define WRPRPINS_PSEL_E__P17_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define WRPRPINS_PSEL_E__P17_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define WRPRPINS_PSEL_E__P17_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define WRPRPINS_PSEL_E__P17_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define WRPRPINS_PSEL_E__P17_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p18_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p18_sel_field p18_sel_field + * @brief macros for field p18_sel + * @{ + */ +#define WRPRPINS_PSEL_E__P18_SEL__SHIFT 16 +#define WRPRPINS_PSEL_E__P18_SEL__WIDTH 8 +#define WRPRPINS_PSEL_E__P18_SEL__MASK 0x00ff0000U +#define WRPRPINS_PSEL_E__P18_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define WRPRPINS_PSEL_E__P18_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define WRPRPINS_PSEL_E__P18_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define WRPRPINS_PSEL_E__P18_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define WRPRPINS_PSEL_E__P18_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p19_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p19_sel_field p19_sel_field + * @brief macros for field p19_sel + * @{ + */ +#define WRPRPINS_PSEL_E__P19_SEL__SHIFT 24 +#define WRPRPINS_PSEL_E__P19_SEL__WIDTH 8 +#define WRPRPINS_PSEL_E__P19_SEL__MASK 0xff000000U +#define WRPRPINS_PSEL_E__P19_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define WRPRPINS_PSEL_E__P19_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define WRPRPINS_PSEL_E__P19_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define WRPRPINS_PSEL_E__P19_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define WRPRPINS_PSEL_E__P19_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_PSEL_E__TYPE uint32_t +#define WRPRPINS_PSEL_E__READ 0xffffffffU +#define WRPRPINS_PSEL_E__WRITE 0xffffffffU +#define WRPRPINS_PSEL_E__PRESERVED 0x00000000U +#define WRPRPINS_PSEL_E__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_PSEL_E_MACRO__ */ + +/** @} end of psel_E */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_psel_F */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_psel_F psel_F + * @brief Contains register fields associated with psel_F. definitions. + * @{ + */ +#ifndef __WRPRPINS_PSEL_F_MACRO__ +#define __WRPRPINS_PSEL_F_MACRO__ + +/* macros for field p20_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p20_sel_field p20_sel_field + * @brief macros for field p20_sel + * @{ + */ +#define WRPRPINS_PSEL_F__P20_SEL__SHIFT 0 +#define WRPRPINS_PSEL_F__P20_SEL__WIDTH 8 +#define WRPRPINS_PSEL_F__P20_SEL__MASK 0x000000ffU +#define WRPRPINS_PSEL_F__P20_SEL__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define WRPRPINS_PSEL_F__P20_SEL__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define WRPRPINS_PSEL_F__P20_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define WRPRPINS_PSEL_F__P20_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define WRPRPINS_PSEL_F__P20_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p21_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p21_sel_field p21_sel_field + * @brief macros for field p21_sel + * @{ + */ +#define WRPRPINS_PSEL_F__P21_SEL__SHIFT 8 +#define WRPRPINS_PSEL_F__P21_SEL__WIDTH 8 +#define WRPRPINS_PSEL_F__P21_SEL__MASK 0x0000ff00U +#define WRPRPINS_PSEL_F__P21_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define WRPRPINS_PSEL_F__P21_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define WRPRPINS_PSEL_F__P21_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define WRPRPINS_PSEL_F__P21_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define WRPRPINS_PSEL_F__P21_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p22_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p22_sel_field p22_sel_field + * @brief macros for field p22_sel + * @{ + */ +#define WRPRPINS_PSEL_F__P22_SEL__SHIFT 16 +#define WRPRPINS_PSEL_F__P22_SEL__WIDTH 8 +#define WRPRPINS_PSEL_F__P22_SEL__MASK 0x00ff0000U +#define WRPRPINS_PSEL_F__P22_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define WRPRPINS_PSEL_F__P22_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define WRPRPINS_PSEL_F__P22_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define WRPRPINS_PSEL_F__P22_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define WRPRPINS_PSEL_F__P22_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p23_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p23_sel_field p23_sel_field + * @brief macros for field p23_sel + * @{ + */ +#define WRPRPINS_PSEL_F__P23_SEL__SHIFT 24 +#define WRPRPINS_PSEL_F__P23_SEL__WIDTH 8 +#define WRPRPINS_PSEL_F__P23_SEL__MASK 0xff000000U +#define WRPRPINS_PSEL_F__P23_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define WRPRPINS_PSEL_F__P23_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define WRPRPINS_PSEL_F__P23_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define WRPRPINS_PSEL_F__P23_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define WRPRPINS_PSEL_F__P23_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_PSEL_F__TYPE uint32_t +#define WRPRPINS_PSEL_F__READ 0xffffffffU +#define WRPRPINS_PSEL_F__WRITE 0xffffffffU +#define WRPRPINS_PSEL_F__PRESERVED 0x00000000U +#define WRPRPINS_PSEL_F__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_PSEL_F_MACRO__ */ + +/** @} end of psel_F */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_psel_G */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_psel_G psel_G + * @brief Contains register fields associated with psel_G. definitions. + * @{ + */ +#ifndef __WRPRPINS_PSEL_G_MACRO__ +#define __WRPRPINS_PSEL_G_MACRO__ + +/* macros for field p24_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p24_sel_field p24_sel_field + * @brief macros for field p24_sel + * @{ + */ +#define WRPRPINS_PSEL_G__P24_SEL__SHIFT 0 +#define WRPRPINS_PSEL_G__P24_SEL__WIDTH 8 +#define WRPRPINS_PSEL_G__P24_SEL__MASK 0x000000ffU +#define WRPRPINS_PSEL_G__P24_SEL__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define WRPRPINS_PSEL_G__P24_SEL__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define WRPRPINS_PSEL_G__P24_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define WRPRPINS_PSEL_G__P24_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define WRPRPINS_PSEL_G__P24_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p25_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p25_sel_field p25_sel_field + * @brief macros for field p25_sel + * @{ + */ +#define WRPRPINS_PSEL_G__P25_SEL__SHIFT 8 +#define WRPRPINS_PSEL_G__P25_SEL__WIDTH 8 +#define WRPRPINS_PSEL_G__P25_SEL__MASK 0x0000ff00U +#define WRPRPINS_PSEL_G__P25_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define WRPRPINS_PSEL_G__P25_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define WRPRPINS_PSEL_G__P25_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define WRPRPINS_PSEL_G__P25_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define WRPRPINS_PSEL_G__P25_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p26_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p26_sel_field p26_sel_field + * @brief macros for field p26_sel + * @{ + */ +#define WRPRPINS_PSEL_G__P26_SEL__SHIFT 16 +#define WRPRPINS_PSEL_G__P26_SEL__WIDTH 8 +#define WRPRPINS_PSEL_G__P26_SEL__MASK 0x00ff0000U +#define WRPRPINS_PSEL_G__P26_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define WRPRPINS_PSEL_G__P26_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define WRPRPINS_PSEL_G__P26_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define WRPRPINS_PSEL_G__P26_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define WRPRPINS_PSEL_G__P26_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p27_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p27_sel_field p27_sel_field + * @brief macros for field p27_sel + * @{ + */ +#define WRPRPINS_PSEL_G__P27_SEL__SHIFT 24 +#define WRPRPINS_PSEL_G__P27_SEL__WIDTH 8 +#define WRPRPINS_PSEL_G__P27_SEL__MASK 0xff000000U +#define WRPRPINS_PSEL_G__P27_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define WRPRPINS_PSEL_G__P27_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define WRPRPINS_PSEL_G__P27_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define WRPRPINS_PSEL_G__P27_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define WRPRPINS_PSEL_G__P27_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_PSEL_G__TYPE uint32_t +#define WRPRPINS_PSEL_G__READ 0xffffffffU +#define WRPRPINS_PSEL_G__WRITE 0xffffffffU +#define WRPRPINS_PSEL_G__PRESERVED 0x00000000U +#define WRPRPINS_PSEL_G__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_PSEL_G_MACRO__ */ + +/** @} end of psel_G */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_psel_H */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_psel_H psel_H + * @brief Contains register fields associated with psel_H. definitions. + * @{ + */ +#ifndef __WRPRPINS_PSEL_H_MACRO__ +#define __WRPRPINS_PSEL_H_MACRO__ + +/* macros for field p28_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p28_sel_field p28_sel_field + * @brief macros for field p28_sel + * @{ + */ +#define WRPRPINS_PSEL_H__P28_SEL__SHIFT 0 +#define WRPRPINS_PSEL_H__P28_SEL__WIDTH 8 +#define WRPRPINS_PSEL_H__P28_SEL__MASK 0x000000ffU +#define WRPRPINS_PSEL_H__P28_SEL__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define WRPRPINS_PSEL_H__P28_SEL__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define WRPRPINS_PSEL_H__P28_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define WRPRPINS_PSEL_H__P28_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define WRPRPINS_PSEL_H__P28_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p29_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p29_sel_field p29_sel_field + * @brief macros for field p29_sel + * @{ + */ +#define WRPRPINS_PSEL_H__P29_SEL__SHIFT 8 +#define WRPRPINS_PSEL_H__P29_SEL__WIDTH 8 +#define WRPRPINS_PSEL_H__P29_SEL__MASK 0x0000ff00U +#define WRPRPINS_PSEL_H__P29_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define WRPRPINS_PSEL_H__P29_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define WRPRPINS_PSEL_H__P29_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define WRPRPINS_PSEL_H__P29_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define WRPRPINS_PSEL_H__P29_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field p30_sel */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_p30_sel_field p30_sel_field + * @brief macros for field p30_sel + * @{ + */ +#define WRPRPINS_PSEL_H__P30_SEL__SHIFT 16 +#define WRPRPINS_PSEL_H__P30_SEL__WIDTH 8 +#define WRPRPINS_PSEL_H__P30_SEL__MASK 0x00ff0000U +#define WRPRPINS_PSEL_H__P30_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define WRPRPINS_PSEL_H__P30_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define WRPRPINS_PSEL_H__P30_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define WRPRPINS_PSEL_H__P30_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define WRPRPINS_PSEL_H__P30_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_PSEL_H__TYPE uint32_t +#define WRPRPINS_PSEL_H__READ 0x00ffffffU +#define WRPRPINS_PSEL_H__WRITE 0x00ffffffU +#define WRPRPINS_PSEL_H__PRESERVED 0x00000000U +#define WRPRPINS_PSEL_H__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_PSEL_H_MACRO__ */ + +/** @} end of psel_H */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_psel_I */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_psel_I psel_I + * @brief Contains register fields associated with psel_I. definitions. + * @{ + */ +#ifndef __WRPRPINS_PSEL_I_MACRO__ +#define __WRPRPINS_PSEL_I_MACRO__ + +/* macros for field atb_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_atb_enable_field atb_enable_field + * @brief macros for field atb_enable + * @{ + */ +#define WRPRPINS_PSEL_I__ATB_ENABLE__SHIFT 0 +#define WRPRPINS_PSEL_I__ATB_ENABLE__WIDTH 5 +#define WRPRPINS_PSEL_I__ATB_ENABLE__MASK 0x0000001fU +#define WRPRPINS_PSEL_I__ATB_ENABLE__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define WRPRPINS_PSEL_I__ATB_ENABLE__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define WRPRPINS_PSEL_I__ATB_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define WRPRPINS_PSEL_I__ATB_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define WRPRPINS_PSEL_I__ATB_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field jtag_interface */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_jtag_interface_field jtag_interface_field + * @brief macros for field jtag_interface + * @{ + */ +#define WRPRPINS_PSEL_I__JTAG_INTERFACE__SHIFT 16 +#define WRPRPINS_PSEL_I__JTAG_INTERFACE__WIDTH 1 +#define WRPRPINS_PSEL_I__JTAG_INTERFACE__MASK 0x00010000U +#define WRPRPINS_PSEL_I__JTAG_INTERFACE__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define WRPRPINS_PSEL_I__JTAG_INTERFACE__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define WRPRPINS_PSEL_I__JTAG_INTERFACE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define WRPRPINS_PSEL_I__JTAG_INTERFACE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define WRPRPINS_PSEL_I__JTAG_INTERFACE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define WRPRPINS_PSEL_I__JTAG_INTERFACE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define WRPRPINS_PSEL_I__JTAG_INTERFACE__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_PSEL_I__TYPE uint32_t +#define WRPRPINS_PSEL_I__READ 0x0001001fU +#define WRPRPINS_PSEL_I__WRITE 0x0001001fU +#define WRPRPINS_PSEL_I__PRESERVED 0x00000000U +#define WRPRPINS_PSEL_I__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_PSEL_I_MACRO__ */ + +/** @} end of psel_I */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_pupd_ovrd */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_pupd_ovrd pupd_ovrd + * @brief pin 0-31 pull up/down override control definitions. + * @{ + */ +#ifndef __WRPRPINS_PUPD_OVRD_MACRO__ +#define __WRPRPINS_PUPD_OVRD_MACRO__ + +/* macros for field pin */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_pin_field pin_field + * @brief macros for field pin + * @details when set, overrides pull-up/pull-down from periphery + * @{ + */ +#define WRPRPINS_PUPD_OVRD__PIN__SHIFT 0 +#define WRPRPINS_PUPD_OVRD__PIN__WIDTH 31 +#define WRPRPINS_PUPD_OVRD__PIN__MASK 0x7fffffffU +#define WRPRPINS_PUPD_OVRD__PIN__READ(src) ((uint32_t)(src) & 0x7fffffffU) +#define WRPRPINS_PUPD_OVRD__PIN__WRITE(src) ((uint32_t)(src) & 0x7fffffffU) +#define WRPRPINS_PUPD_OVRD__PIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7fffffffU) | ((uint32_t)(src) &\ + 0x7fffffffU) +#define WRPRPINS_PUPD_OVRD__PIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x7fffffffU))) +#define WRPRPINS_PUPD_OVRD__PIN__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_PUPD_OVRD__TYPE uint32_t +#define WRPRPINS_PUPD_OVRD__READ 0x7fffffffU +#define WRPRPINS_PUPD_OVRD__WRITE 0x7fffffffU +#define WRPRPINS_PUPD_OVRD__PRESERVED 0x00000000U +#define WRPRPINS_PUPD_OVRD__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_PUPD_OVRD_MACRO__ */ + +/** @} end of pupd_ovrd */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_pupd_ovrd_val */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_pupd_ovrd_val pupd_ovrd_val + * @brief pin 0-31 pull up/down override value definitions. + * @{ + */ +#ifndef __WRPRPINS_PUPD_OVRD_VAL_MACRO__ +#define __WRPRPINS_PUPD_OVRD_VAL_MACRO__ + +/* macros for field pin */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_pin_field pin_field + * @brief macros for field pin + * @details pull-up/pull_down override value when pupd_ovrd is set: 1= pull-up override 0= pull-down override + * @{ + */ +#define WRPRPINS_PUPD_OVRD_VAL__PIN__SHIFT 0 +#define WRPRPINS_PUPD_OVRD_VAL__PIN__WIDTH 31 +#define WRPRPINS_PUPD_OVRD_VAL__PIN__MASK 0x7fffffffU +#define WRPRPINS_PUPD_OVRD_VAL__PIN__READ(src) ((uint32_t)(src) & 0x7fffffffU) +#define WRPRPINS_PUPD_OVRD_VAL__PIN__WRITE(src) ((uint32_t)(src) & 0x7fffffffU) +#define WRPRPINS_PUPD_OVRD_VAL__PIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7fffffffU) | ((uint32_t)(src) &\ + 0x7fffffffU) +#define WRPRPINS_PUPD_OVRD_VAL__PIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x7fffffffU))) +#define WRPRPINS_PUPD_OVRD_VAL__PIN__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_PUPD_OVRD_VAL__TYPE uint32_t +#define WRPRPINS_PUPD_OVRD_VAL__READ 0x7fffffffU +#define WRPRPINS_PUPD_OVRD_VAL__WRITE 0x7fffffffU +#define WRPRPINS_PUPD_OVRD_VAL__PRESERVED 0x00000000U +#define WRPRPINS_PUPD_OVRD_VAL__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_PUPD_OVRD_VAL_MACRO__ */ + +/** @} end of pupd_ovrd_val */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_remap */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_remap remap + * @brief Contains register fields associated with remap. definitions. + * @{ + */ +#ifndef __WRPRPINS_REMAP_MACRO__ +#define __WRPRPINS_REMAP_MACRO__ + +/* macros for field qspi_drop */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_qspi_drop_field qspi_drop_field + * @brief macros for field qspi_drop + * @details drops the at_ahb_qspi address start from 0x10000000 to 0x0. No change in range. + * @{ + */ +#define WRPRPINS_REMAP__QSPI_DROP__SHIFT 0 +#define WRPRPINS_REMAP__QSPI_DROP__WIDTH 1 +#define WRPRPINS_REMAP__QSPI_DROP__MASK 0x00000001U +#define WRPRPINS_REMAP__QSPI_DROP__READ(src) ((uint32_t)(src) & 0x00000001U) +#define WRPRPINS_REMAP__QSPI_DROP__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define WRPRPINS_REMAP__QSPI_DROP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_REMAP__QSPI_DROP__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_REMAP__QSPI_DROP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_REMAP__QSPI_DROP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_REMAP__QSPI_DROP__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_REMAP__TYPE uint32_t +#define WRPRPINS_REMAP__READ 0x00000001U +#define WRPRPINS_REMAP__WRITE 0x00000001U +#define WRPRPINS_REMAP__PRESERVED 0x00000000U +#define WRPRPINS_REMAP__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_REMAP_MACRO__ */ + +/** @} end of remap */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_ahb_interposers */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_ahb_interposers ahb_interposers + * @brief Contains register fields associated with ahb_interposers. definitions. + * @{ + */ +#ifndef __WRPRPINS_AHB_INTERPOSERS_MACRO__ +#define __WRPRPINS_AHB_INTERPOSERS_MACRO__ + +/* macros for field qspi_intp_enable */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_qspi_intp_enable_field qspi_intp_enable_field + * @brief macros for field qspi_intp_enable + * @{ + */ +#define WRPRPINS_AHB_INTERPOSERS__QSPI_INTP_ENABLE__SHIFT 0 +#define WRPRPINS_AHB_INTERPOSERS__QSPI_INTP_ENABLE__WIDTH 1 +#define WRPRPINS_AHB_INTERPOSERS__QSPI_INTP_ENABLE__MASK 0x00000001U +#define WRPRPINS_AHB_INTERPOSERS__QSPI_INTP_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_AHB_INTERPOSERS__QSPI_INTP_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_AHB_INTERPOSERS__QSPI_INTP_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_AHB_INTERPOSERS__QSPI_INTP_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_AHB_INTERPOSERS__QSPI_INTP_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_AHB_INTERPOSERS__QSPI_INTP_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_AHB_INTERPOSERS__QSPI_INTP_ENABLE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field qspi_intp_low_ceiling */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_qspi_intp_low_ceiling_field qspi_intp_low_ceiling_field + * @brief macros for field qspi_intp_low_ceiling + * @{ + */ +#define WRPRPINS_AHB_INTERPOSERS__QSPI_INTP_LOW_CEILING__SHIFT 1 +#define WRPRPINS_AHB_INTERPOSERS__QSPI_INTP_LOW_CEILING__WIDTH 1 +#define WRPRPINS_AHB_INTERPOSERS__QSPI_INTP_LOW_CEILING__MASK 0x00000002U +#define WRPRPINS_AHB_INTERPOSERS__QSPI_INTP_LOW_CEILING__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRPINS_AHB_INTERPOSERS__QSPI_INTP_LOW_CEILING__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRPINS_AHB_INTERPOSERS__QSPI_INTP_LOW_CEILING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRPINS_AHB_INTERPOSERS__QSPI_INTP_LOW_CEILING__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRPINS_AHB_INTERPOSERS__QSPI_INTP_LOW_CEILING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRPINS_AHB_INTERPOSERS__QSPI_INTP_LOW_CEILING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRPINS_AHB_INTERPOSERS__QSPI_INTP_LOW_CEILING__RESET_VALUE \ + 0x00000000U +/** @} */ +#define WRPRPINS_AHB_INTERPOSERS__TYPE uint32_t +#define WRPRPINS_AHB_INTERPOSERS__READ 0x00000003U +#define WRPRPINS_AHB_INTERPOSERS__WRITE 0x00000003U +#define WRPRPINS_AHB_INTERPOSERS__PRESERVED 0x00000000U +#define WRPRPINS_AHB_INTERPOSERS__RESET_VALUE 0x00000001U + +#endif /* __WRPRPINS_AHB_INTERPOSERS_MACRO__ */ + +/** @} end of ahb_interposers */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_scratchpad_A */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_scratchpad_A scratchpad_A + * @brief Contains register fields associated with scratchpad_A. definitions. + * @{ + */ +#ifndef __WRPRPINS_SCRATCHPAD_A_MACRO__ +#define __WRPRPINS_SCRATCHPAD_A_MACRO__ + +/* macros for field misc */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_misc_field misc_field + * @brief macros for field misc + * @details mostly likely will be used to inject random seed in sim + * @{ + */ +#define WRPRPINS_SCRATCHPAD_A__MISC__SHIFT 0 +#define WRPRPINS_SCRATCHPAD_A__MISC__WIDTH 32 +#define WRPRPINS_SCRATCHPAD_A__MISC__MASK 0xffffffffU +#define WRPRPINS_SCRATCHPAD_A__MISC__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define WRPRPINS_SCRATCHPAD_A__MISC__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define WRPRPINS_SCRATCHPAD_A__MISC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_SCRATCHPAD_A__MISC__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_SCRATCHPAD_A__MISC__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_SCRATCHPAD_A__TYPE uint32_t +#define WRPRPINS_SCRATCHPAD_A__READ 0xffffffffU +#define WRPRPINS_SCRATCHPAD_A__WRITE 0xffffffffU +#define WRPRPINS_SCRATCHPAD_A__PRESERVED 0x00000000U +#define WRPRPINS_SCRATCHPAD_A__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_SCRATCHPAD_A_MACRO__ */ + +/** @} end of scratchpad_A */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_scratchpad_B */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_scratchpad_B scratchpad_B + * @brief Contains register fields associated with scratchpad_B. definitions. + * @{ + */ +#ifndef __WRPRPINS_SCRATCHPAD_B_MACRO__ +#define __WRPRPINS_SCRATCHPAD_B_MACRO__ + +/* macros for field misc */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_misc_field misc_field + * @brief macros for field misc + * @details mostly likely will be used to inject random seed in sim + * @{ + */ +#define WRPRPINS_SCRATCHPAD_B__MISC__SHIFT 0 +#define WRPRPINS_SCRATCHPAD_B__MISC__WIDTH 32 +#define WRPRPINS_SCRATCHPAD_B__MISC__MASK 0xffffffffU +#define WRPRPINS_SCRATCHPAD_B__MISC__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define WRPRPINS_SCRATCHPAD_B__MISC__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define WRPRPINS_SCRATCHPAD_B__MISC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_SCRATCHPAD_B__MISC__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_SCRATCHPAD_B__MISC__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_SCRATCHPAD_B__TYPE uint32_t +#define WRPRPINS_SCRATCHPAD_B__READ 0xffffffffU +#define WRPRPINS_SCRATCHPAD_B__WRITE 0xffffffffU +#define WRPRPINS_SCRATCHPAD_B__PRESERVED 0x00000000U +#define WRPRPINS_SCRATCHPAD_B__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_SCRATCHPAD_B_MACRO__ */ + +/** @} end of scratchpad_B */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_scratchpad_C */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_scratchpad_C scratchpad_C + * @brief Contains register fields associated with scratchpad_C. definitions. + * @{ + */ +#ifndef __WRPRPINS_SCRATCHPAD_C_MACRO__ +#define __WRPRPINS_SCRATCHPAD_C_MACRO__ + +/* macros for field misc */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_misc_field misc_field + * @brief macros for field misc + * @details mostly likely will be used to inject random seed in sim + * @{ + */ +#define WRPRPINS_SCRATCHPAD_C__MISC__SHIFT 0 +#define WRPRPINS_SCRATCHPAD_C__MISC__WIDTH 32 +#define WRPRPINS_SCRATCHPAD_C__MISC__MASK 0xffffffffU +#define WRPRPINS_SCRATCHPAD_C__MISC__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define WRPRPINS_SCRATCHPAD_C__MISC__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define WRPRPINS_SCRATCHPAD_C__MISC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_SCRATCHPAD_C__MISC__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_SCRATCHPAD_C__MISC__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_SCRATCHPAD_C__TYPE uint32_t +#define WRPRPINS_SCRATCHPAD_C__READ 0xffffffffU +#define WRPRPINS_SCRATCHPAD_C__WRITE 0xffffffffU +#define WRPRPINS_SCRATCHPAD_C__PRESERVED 0x00000000U +#define WRPRPINS_SCRATCHPAD_C__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_SCRATCHPAD_C_MACRO__ */ + +/** @} end of scratchpad_C */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_scratchpad_D */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_scratchpad_D scratchpad_D + * @brief Contains register fields associated with scratchpad_D. definitions. + * @{ + */ +#ifndef __WRPRPINS_SCRATCHPAD_D_MACRO__ +#define __WRPRPINS_SCRATCHPAD_D_MACRO__ + +/* macros for field misc */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_misc_field misc_field + * @brief macros for field misc + * @details mostly likely will be used to inject random seed in sim + * @{ + */ +#define WRPRPINS_SCRATCHPAD_D__MISC__SHIFT 0 +#define WRPRPINS_SCRATCHPAD_D__MISC__WIDTH 32 +#define WRPRPINS_SCRATCHPAD_D__MISC__MASK 0xffffffffU +#define WRPRPINS_SCRATCHPAD_D__MISC__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define WRPRPINS_SCRATCHPAD_D__MISC__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define WRPRPINS_SCRATCHPAD_D__MISC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_SCRATCHPAD_D__MISC__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_SCRATCHPAD_D__MISC__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_SCRATCHPAD_D__TYPE uint32_t +#define WRPRPINS_SCRATCHPAD_D__READ 0xffffffffU +#define WRPRPINS_SCRATCHPAD_D__WRITE 0xffffffffU +#define WRPRPINS_SCRATCHPAD_D__PRESERVED 0x00000000U +#define WRPRPINS_SCRATCHPAD_D__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_SCRATCHPAD_D_MACRO__ */ + +/** @} end of scratchpad_D */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_write_protection0 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_write_protection0 rram_write_protection0 + * @brief Contains register fields associated with rram_write_protection0. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_WRITE_PROTECTION0_MACRO__ +#define __WRPRPINS_RRAM_WRITE_PROTECTION0_MACRO__ + +/* macros for field disable_bits */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_disable_bits_field disable_bits_field + * @brief macros for field disable_bits + * @details if a bit is set, invalidates any writes to corresponding to 2kB block + * @{ + */ +#define WRPRPINS_RRAM_WRITE_PROTECTION0__DISABLE_BITS__SHIFT 0 +#define WRPRPINS_RRAM_WRITE_PROTECTION0__DISABLE_BITS__WIDTH 32 +#define WRPRPINS_RRAM_WRITE_PROTECTION0__DISABLE_BITS__MASK 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION0__DISABLE_BITS__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION0__DISABLE_BITS__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION0__DISABLE_BITS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION0__DISABLE_BITS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_RRAM_WRITE_PROTECTION0__DISABLE_BITS__RESET_VALUE 0xffffffffU +/** @} */ +#define WRPRPINS_RRAM_WRITE_PROTECTION0__TYPE uint32_t +#define WRPRPINS_RRAM_WRITE_PROTECTION0__READ 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION0__WRITE 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION0__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_WRITE_PROTECTION0__RESET_VALUE 0xffffffffU + +#endif /* __WRPRPINS_RRAM_WRITE_PROTECTION0_MACRO__ */ + +/** @} end of rram_write_protection0 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_write_protection1 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_write_protection1 rram_write_protection1 + * @brief Contains register fields associated with rram_write_protection1. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_WRITE_PROTECTION1_MACRO__ +#define __WRPRPINS_RRAM_WRITE_PROTECTION1_MACRO__ + +/* macros for field disable_bits */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_disable_bits_field disable_bits_field + * @brief macros for field disable_bits + * @{ + */ +#define WRPRPINS_RRAM_WRITE_PROTECTION1__DISABLE_BITS__SHIFT 0 +#define WRPRPINS_RRAM_WRITE_PROTECTION1__DISABLE_BITS__WIDTH 32 +#define WRPRPINS_RRAM_WRITE_PROTECTION1__DISABLE_BITS__MASK 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION1__DISABLE_BITS__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION1__DISABLE_BITS__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION1__DISABLE_BITS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION1__DISABLE_BITS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_RRAM_WRITE_PROTECTION1__DISABLE_BITS__RESET_VALUE 0xffffffffU +/** @} */ +#define WRPRPINS_RRAM_WRITE_PROTECTION1__TYPE uint32_t +#define WRPRPINS_RRAM_WRITE_PROTECTION1__READ 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION1__WRITE 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION1__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_WRITE_PROTECTION1__RESET_VALUE 0xffffffffU + +#endif /* __WRPRPINS_RRAM_WRITE_PROTECTION1_MACRO__ */ + +/** @} end of rram_write_protection1 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_write_protection2 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_write_protection2 rram_write_protection2 + * @brief Contains register fields associated with rram_write_protection2. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_WRITE_PROTECTION2_MACRO__ +#define __WRPRPINS_RRAM_WRITE_PROTECTION2_MACRO__ + +/* macros for field disable_bits */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_disable_bits_field disable_bits_field + * @brief macros for field disable_bits + * @{ + */ +#define WRPRPINS_RRAM_WRITE_PROTECTION2__DISABLE_BITS__SHIFT 0 +#define WRPRPINS_RRAM_WRITE_PROTECTION2__DISABLE_BITS__WIDTH 32 +#define WRPRPINS_RRAM_WRITE_PROTECTION2__DISABLE_BITS__MASK 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION2__DISABLE_BITS__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION2__DISABLE_BITS__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION2__DISABLE_BITS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION2__DISABLE_BITS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_RRAM_WRITE_PROTECTION2__DISABLE_BITS__RESET_VALUE 0xffffffffU +/** @} */ +#define WRPRPINS_RRAM_WRITE_PROTECTION2__TYPE uint32_t +#define WRPRPINS_RRAM_WRITE_PROTECTION2__READ 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION2__WRITE 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION2__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_WRITE_PROTECTION2__RESET_VALUE 0xffffffffU + +#endif /* __WRPRPINS_RRAM_WRITE_PROTECTION2_MACRO__ */ + +/** @} end of rram_write_protection2 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_write_protection3 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_write_protection3 rram_write_protection3 + * @brief Contains register fields associated with rram_write_protection3. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_WRITE_PROTECTION3_MACRO__ +#define __WRPRPINS_RRAM_WRITE_PROTECTION3_MACRO__ + +/* macros for field disable_bits */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_disable_bits_field disable_bits_field + * @brief macros for field disable_bits + * @{ + */ +#define WRPRPINS_RRAM_WRITE_PROTECTION3__DISABLE_BITS__SHIFT 0 +#define WRPRPINS_RRAM_WRITE_PROTECTION3__DISABLE_BITS__WIDTH 32 +#define WRPRPINS_RRAM_WRITE_PROTECTION3__DISABLE_BITS__MASK 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION3__DISABLE_BITS__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION3__DISABLE_BITS__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION3__DISABLE_BITS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION3__DISABLE_BITS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_RRAM_WRITE_PROTECTION3__DISABLE_BITS__RESET_VALUE 0xffffffffU +/** @} */ +#define WRPRPINS_RRAM_WRITE_PROTECTION3__TYPE uint32_t +#define WRPRPINS_RRAM_WRITE_PROTECTION3__READ 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION3__WRITE 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION3__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_WRITE_PROTECTION3__RESET_VALUE 0xffffffffU + +#endif /* __WRPRPINS_RRAM_WRITE_PROTECTION3_MACRO__ */ + +/** @} end of rram_write_protection3 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_write_protection4 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_write_protection4 rram_write_protection4 + * @brief Contains register fields associated with rram_write_protection4. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_WRITE_PROTECTION4_MACRO__ +#define __WRPRPINS_RRAM_WRITE_PROTECTION4_MACRO__ + +/* macros for field disable_bits */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_disable_bits_field disable_bits_field + * @brief macros for field disable_bits + * @{ + */ +#define WRPRPINS_RRAM_WRITE_PROTECTION4__DISABLE_BITS__SHIFT 0 +#define WRPRPINS_RRAM_WRITE_PROTECTION4__DISABLE_BITS__WIDTH 32 +#define WRPRPINS_RRAM_WRITE_PROTECTION4__DISABLE_BITS__MASK 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION4__DISABLE_BITS__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION4__DISABLE_BITS__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION4__DISABLE_BITS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION4__DISABLE_BITS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_RRAM_WRITE_PROTECTION4__DISABLE_BITS__RESET_VALUE 0xffffffffU +/** @} */ +#define WRPRPINS_RRAM_WRITE_PROTECTION4__TYPE uint32_t +#define WRPRPINS_RRAM_WRITE_PROTECTION4__READ 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION4__WRITE 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION4__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_WRITE_PROTECTION4__RESET_VALUE 0xffffffffU + +#endif /* __WRPRPINS_RRAM_WRITE_PROTECTION4_MACRO__ */ + +/** @} end of rram_write_protection4 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_write_protection5 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_write_protection5 rram_write_protection5 + * @brief Contains register fields associated with rram_write_protection5. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_WRITE_PROTECTION5_MACRO__ +#define __WRPRPINS_RRAM_WRITE_PROTECTION5_MACRO__ + +/* macros for field disable_bits */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_disable_bits_field disable_bits_field + * @brief macros for field disable_bits + * @{ + */ +#define WRPRPINS_RRAM_WRITE_PROTECTION5__DISABLE_BITS__SHIFT 0 +#define WRPRPINS_RRAM_WRITE_PROTECTION5__DISABLE_BITS__WIDTH 32 +#define WRPRPINS_RRAM_WRITE_PROTECTION5__DISABLE_BITS__MASK 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION5__DISABLE_BITS__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION5__DISABLE_BITS__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION5__DISABLE_BITS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION5__DISABLE_BITS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_RRAM_WRITE_PROTECTION5__DISABLE_BITS__RESET_VALUE 0xffffffffU +/** @} */ +#define WRPRPINS_RRAM_WRITE_PROTECTION5__TYPE uint32_t +#define WRPRPINS_RRAM_WRITE_PROTECTION5__READ 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION5__WRITE 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION5__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_WRITE_PROTECTION5__RESET_VALUE 0xffffffffU + +#endif /* __WRPRPINS_RRAM_WRITE_PROTECTION5_MACRO__ */ + +/** @} end of rram_write_protection5 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_write_protection6 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_write_protection6 rram_write_protection6 + * @brief Contains register fields associated with rram_write_protection6. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_WRITE_PROTECTION6_MACRO__ +#define __WRPRPINS_RRAM_WRITE_PROTECTION6_MACRO__ + +/* macros for field disable_bits */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_disable_bits_field disable_bits_field + * @brief macros for field disable_bits + * @{ + */ +#define WRPRPINS_RRAM_WRITE_PROTECTION6__DISABLE_BITS__SHIFT 0 +#define WRPRPINS_RRAM_WRITE_PROTECTION6__DISABLE_BITS__WIDTH 32 +#define WRPRPINS_RRAM_WRITE_PROTECTION6__DISABLE_BITS__MASK 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION6__DISABLE_BITS__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION6__DISABLE_BITS__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION6__DISABLE_BITS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION6__DISABLE_BITS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_RRAM_WRITE_PROTECTION6__DISABLE_BITS__RESET_VALUE 0xffffffffU +/** @} */ +#define WRPRPINS_RRAM_WRITE_PROTECTION6__TYPE uint32_t +#define WRPRPINS_RRAM_WRITE_PROTECTION6__READ 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION6__WRITE 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION6__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_WRITE_PROTECTION6__RESET_VALUE 0xffffffffU + +#endif /* __WRPRPINS_RRAM_WRITE_PROTECTION6_MACRO__ */ + +/** @} end of rram_write_protection6 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_write_protection7 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_write_protection7 rram_write_protection7 + * @brief Contains register fields associated with rram_write_protection7. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_WRITE_PROTECTION7_MACRO__ +#define __WRPRPINS_RRAM_WRITE_PROTECTION7_MACRO__ + +/* macros for field disable_bits */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_disable_bits_field disable_bits_field + * @brief macros for field disable_bits + * @{ + */ +#define WRPRPINS_RRAM_WRITE_PROTECTION7__DISABLE_BITS__SHIFT 0 +#define WRPRPINS_RRAM_WRITE_PROTECTION7__DISABLE_BITS__WIDTH 32 +#define WRPRPINS_RRAM_WRITE_PROTECTION7__DISABLE_BITS__MASK 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION7__DISABLE_BITS__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION7__DISABLE_BITS__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION7__DISABLE_BITS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_RRAM_WRITE_PROTECTION7__DISABLE_BITS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_RRAM_WRITE_PROTECTION7__DISABLE_BITS__RESET_VALUE 0xffffffffU +/** @} */ +#define WRPRPINS_RRAM_WRITE_PROTECTION7__TYPE uint32_t +#define WRPRPINS_RRAM_WRITE_PROTECTION7__READ 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION7__WRITE 0xffffffffU +#define WRPRPINS_RRAM_WRITE_PROTECTION7__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_WRITE_PROTECTION7__RESET_VALUE 0xffffffffU + +#endif /* __WRPRPINS_RRAM_WRITE_PROTECTION7_MACRO__ */ + +/** @} end of rram_write_protection7 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_sticky_write_protection0 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_sticky_write_protection0 rram_sticky_write_protection0 + * @brief Contains register fields associated with rram_sticky_write_protection0. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION0_MACRO__ +#define __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION0_MACRO__ + +/* macros for field set */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_set_field set_field + * @brief macros for field set + * @details if a bit is set, invalidates any writes to the corresponding 2kB block, can only revert with cpu reset + * @{ + */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION0__SET__SHIFT 0 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION0__SET__WIDTH 32 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION0__SET__MASK 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION0__SET__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION0__SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION0__SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION0__SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION0__SET__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION0__TYPE uint32_t +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION0__READ 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION0__WRITE 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION0__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION0__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION0_MACRO__ */ + +/** @} end of rram_sticky_write_protection0 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_sticky_write_protection1 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_sticky_write_protection1 rram_sticky_write_protection1 + * @brief Contains register fields associated with rram_sticky_write_protection1. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION1_MACRO__ +#define __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION1_MACRO__ + +/* macros for field set */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_set_field set_field + * @brief macros for field set + * @{ + */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION1__SET__SHIFT 0 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION1__SET__WIDTH 32 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION1__SET__MASK 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION1__SET__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION1__SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION1__SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION1__SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION1__SET__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION1__TYPE uint32_t +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION1__READ 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION1__WRITE 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION1__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION1__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION1_MACRO__ */ + +/** @} end of rram_sticky_write_protection1 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_sticky_write_protection2 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_sticky_write_protection2 rram_sticky_write_protection2 + * @brief Contains register fields associated with rram_sticky_write_protection2. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION2_MACRO__ +#define __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION2_MACRO__ + +/* macros for field set */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_set_field set_field + * @brief macros for field set + * @{ + */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION2__SET__SHIFT 0 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION2__SET__WIDTH 32 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION2__SET__MASK 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION2__SET__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION2__SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION2__SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION2__SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION2__SET__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION2__TYPE uint32_t +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION2__READ 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION2__WRITE 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION2__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION2__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION2_MACRO__ */ + +/** @} end of rram_sticky_write_protection2 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_sticky_write_protection3 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_sticky_write_protection3 rram_sticky_write_protection3 + * @brief Contains register fields associated with rram_sticky_write_protection3. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION3_MACRO__ +#define __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION3_MACRO__ + +/* macros for field set */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_set_field set_field + * @brief macros for field set + * @{ + */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION3__SET__SHIFT 0 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION3__SET__WIDTH 32 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION3__SET__MASK 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION3__SET__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION3__SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION3__SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION3__SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION3__SET__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION3__TYPE uint32_t +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION3__READ 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION3__WRITE 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION3__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION3__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION3_MACRO__ */ + +/** @} end of rram_sticky_write_protection3 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_sticky_write_protection4 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_sticky_write_protection4 rram_sticky_write_protection4 + * @brief Contains register fields associated with rram_sticky_write_protection4. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION4_MACRO__ +#define __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION4_MACRO__ + +/* macros for field set */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_set_field set_field + * @brief macros for field set + * @{ + */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION4__SET__SHIFT 0 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION4__SET__WIDTH 32 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION4__SET__MASK 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION4__SET__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION4__SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION4__SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION4__SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION4__SET__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION4__TYPE uint32_t +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION4__READ 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION4__WRITE 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION4__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION4__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION4_MACRO__ */ + +/** @} end of rram_sticky_write_protection4 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_sticky_write_protection5 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_sticky_write_protection5 rram_sticky_write_protection5 + * @brief Contains register fields associated with rram_sticky_write_protection5. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION5_MACRO__ +#define __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION5_MACRO__ + +/* macros for field set */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_set_field set_field + * @brief macros for field set + * @{ + */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION5__SET__SHIFT 0 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION5__SET__WIDTH 32 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION5__SET__MASK 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION5__SET__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION5__SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION5__SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION5__SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION5__SET__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION5__TYPE uint32_t +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION5__READ 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION5__WRITE 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION5__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION5__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION5_MACRO__ */ + +/** @} end of rram_sticky_write_protection5 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_sticky_write_protection6 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_sticky_write_protection6 rram_sticky_write_protection6 + * @brief Contains register fields associated with rram_sticky_write_protection6. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION6_MACRO__ +#define __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION6_MACRO__ + +/* macros for field set */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_set_field set_field + * @brief macros for field set + * @{ + */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION6__SET__SHIFT 0 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION6__SET__WIDTH 32 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION6__SET__MASK 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION6__SET__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION6__SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION6__SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION6__SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION6__SET__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION6__TYPE uint32_t +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION6__READ 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION6__WRITE 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION6__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION6__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION6_MACRO__ */ + +/** @} end of rram_sticky_write_protection6 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_sticky_write_protection7 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_sticky_write_protection7 rram_sticky_write_protection7 + * @brief Contains register fields associated with rram_sticky_write_protection7. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION7_MACRO__ +#define __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION7_MACRO__ + +/* macros for field set */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_set_field set_field + * @brief macros for field set + * @{ + */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION7__SET__SHIFT 0 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION7__SET__WIDTH 32 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION7__SET__MASK 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION7__SET__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION7__SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION7__SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION7__SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION7__SET__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION7__TYPE uint32_t +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION7__READ 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION7__WRITE 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION7__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION7__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION7_MACRO__ */ + +/** @} end of rram_sticky_write_protection7 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_sticky_write_protection_status0 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_sticky_write_protection_status0 rram_sticky_write_protection_status0 + * @brief Contains register fields associated with rram_sticky_write_protection_status0. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS0_MACRO__ +#define __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS0_MACRO__ + +/* macros for field val */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_val_field val_field + * @brief macros for field val + * @details if read back value is 1, then the sticky bit has been set + * @{ + */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS0__VAL__SHIFT 0 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS0__VAL__WIDTH 32 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS0__VAL__MASK 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS0__VAL__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS0__VAL__RESET_VALUE \ + 0x00000000U +/** @} */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS0__TYPE uint32_t +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS0__READ 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS0__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS0__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS0_MACRO__ */ + +/** @} end of rram_sticky_write_protection_status0 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_sticky_write_protection_status1 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_sticky_write_protection_status1 rram_sticky_write_protection_status1 + * @brief Contains register fields associated with rram_sticky_write_protection_status1. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS1_MACRO__ +#define __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS1_MACRO__ + +/* macros for field val */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_val_field val_field + * @brief macros for field val + * @{ + */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS1__VAL__SHIFT 0 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS1__VAL__WIDTH 32 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS1__VAL__MASK 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS1__VAL__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS1__VAL__RESET_VALUE \ + 0x00000000U +/** @} */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS1__TYPE uint32_t +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS1__READ 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS1__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS1__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS1_MACRO__ */ + +/** @} end of rram_sticky_write_protection_status1 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_sticky_write_protection_status2 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_sticky_write_protection_status2 rram_sticky_write_protection_status2 + * @brief Contains register fields associated with rram_sticky_write_protection_status2. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS2_MACRO__ +#define __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS2_MACRO__ + +/* macros for field val */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_val_field val_field + * @brief macros for field val + * @{ + */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS2__VAL__SHIFT 0 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS2__VAL__WIDTH 32 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS2__VAL__MASK 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS2__VAL__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS2__VAL__RESET_VALUE \ + 0x00000000U +/** @} */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS2__TYPE uint32_t +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS2__READ 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS2__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS2__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS2_MACRO__ */ + +/** @} end of rram_sticky_write_protection_status2 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_sticky_write_protection_status3 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_sticky_write_protection_status3 rram_sticky_write_protection_status3 + * @brief Contains register fields associated with rram_sticky_write_protection_status3. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS3_MACRO__ +#define __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS3_MACRO__ + +/* macros for field val */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_val_field val_field + * @brief macros for field val + * @{ + */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS3__VAL__SHIFT 0 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS3__VAL__WIDTH 32 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS3__VAL__MASK 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS3__VAL__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS3__VAL__RESET_VALUE \ + 0x00000000U +/** @} */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS3__TYPE uint32_t +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS3__READ 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS3__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS3__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS3_MACRO__ */ + +/** @} end of rram_sticky_write_protection_status3 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_sticky_write_protection_status4 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_sticky_write_protection_status4 rram_sticky_write_protection_status4 + * @brief Contains register fields associated with rram_sticky_write_protection_status4. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS4_MACRO__ +#define __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS4_MACRO__ + +/* macros for field val */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_val_field val_field + * @brief macros for field val + * @{ + */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS4__VAL__SHIFT 0 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS4__VAL__WIDTH 32 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS4__VAL__MASK 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS4__VAL__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS4__VAL__RESET_VALUE \ + 0x00000000U +/** @} */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS4__TYPE uint32_t +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS4__READ 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS4__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS4__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS4_MACRO__ */ + +/** @} end of rram_sticky_write_protection_status4 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_sticky_write_protection_status5 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_sticky_write_protection_status5 rram_sticky_write_protection_status5 + * @brief Contains register fields associated with rram_sticky_write_protection_status5. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS5_MACRO__ +#define __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS5_MACRO__ + +/* macros for field val */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_val_field val_field + * @brief macros for field val + * @{ + */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS5__VAL__SHIFT 0 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS5__VAL__WIDTH 32 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS5__VAL__MASK 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS5__VAL__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS5__VAL__RESET_VALUE \ + 0x00000000U +/** @} */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS5__TYPE uint32_t +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS5__READ 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS5__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS5__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS5_MACRO__ */ + +/** @} end of rram_sticky_write_protection_status5 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_sticky_write_protection_status6 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_sticky_write_protection_status6 rram_sticky_write_protection_status6 + * @brief Contains register fields associated with rram_sticky_write_protection_status6. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS6_MACRO__ +#define __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS6_MACRO__ + +/* macros for field val */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_val_field val_field + * @brief macros for field val + * @{ + */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS6__VAL__SHIFT 0 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS6__VAL__WIDTH 32 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS6__VAL__MASK 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS6__VAL__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS6__VAL__RESET_VALUE \ + 0x00000000U +/** @} */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS6__TYPE uint32_t +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS6__READ 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS6__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS6__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS6_MACRO__ */ + +/** @} end of rram_sticky_write_protection_status6 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_sticky_write_protection_status7 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_sticky_write_protection_status7 rram_sticky_write_protection_status7 + * @brief Contains register fields associated with rram_sticky_write_protection_status7. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS7_MACRO__ +#define __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS7_MACRO__ + +/* macros for field val */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_val_field val_field + * @brief macros for field val + * @{ + */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS7__VAL__SHIFT 0 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS7__VAL__WIDTH 32 +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS7__VAL__MASK 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS7__VAL__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS7__VAL__RESET_VALUE \ + 0x00000000U +/** @} */ +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS7__TYPE uint32_t +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS7__READ 0xffffffffU +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS7__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS7__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_RRAM_STICKY_WRITE_PROTECTION_STATUS7_MACRO__ */ + +/** @} end of rram_sticky_write_protection_status7 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_sticky_read_protection0 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_sticky_read_protection0 rram_sticky_read_protection0 + * @brief Contains register fields associated with rram_sticky_read_protection0. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_STICKY_READ_PROTECTION0_MACRO__ +#define __WRPRPINS_RRAM_STICKY_READ_PROTECTION0_MACRO__ + +/* macros for field set */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_set_field set_field + * @brief macros for field set + * @details if a bit is set, invalidates any reads to the corresponding 2kB block, can only revert with cpu reset + * @{ + */ +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION0__SET__SHIFT 0 +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION0__SET__WIDTH 32 +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION0__SET__MASK 0xffffffffU +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION0__SET__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION0__SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION0__SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION0__SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION0__SET__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION0__TYPE uint32_t +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION0__READ 0xffffffffU +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION0__WRITE 0xffffffffU +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION0__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION0__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_RRAM_STICKY_READ_PROTECTION0_MACRO__ */ + +/** @} end of rram_sticky_read_protection0 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_rram_sticky_read_protection_status0 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rram_sticky_read_protection_status0 rram_sticky_read_protection_status0 + * @brief Contains register fields associated with rram_sticky_read_protection_status0. definitions. + * @{ + */ +#ifndef __WRPRPINS_RRAM_STICKY_READ_PROTECTION_STATUS0_MACRO__ +#define __WRPRPINS_RRAM_STICKY_READ_PROTECTION_STATUS0_MACRO__ + +/* macros for field val */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_val_field val_field + * @brief macros for field val + * @details if read back value is 1, then the sticky bit has been set + * @{ + */ +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION_STATUS0__VAL__SHIFT 0 +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION_STATUS0__VAL__WIDTH 32 +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION_STATUS0__VAL__MASK 0xffffffffU +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION_STATUS0__VAL__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION_STATUS0__VAL__RESET_VALUE \ + 0x00000000U +/** @} */ +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION_STATUS0__TYPE uint32_t +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION_STATUS0__READ 0xffffffffU +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION_STATUS0__PRESERVED 0x00000000U +#define WRPRPINS_RRAM_STICKY_READ_PROTECTION_STATUS0__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_RRAM_STICKY_READ_PROTECTION_STATUS0_MACRO__ */ + +/** @} end of rram_sticky_read_protection_status0 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_prot_bits_set0 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_prot_bits_set0 prot_bits_set0 + * @brief Contains register fields associated with prot_bits_set0. definitions. + * @{ + */ +#ifndef __WRPRPINS_PROT_BITS_SET0_MACRO__ +#define __WRPRPINS_PROT_BITS_SET0_MACRO__ + +/* macros for field rom_read_locks_set */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rom_read_locks_set_field rom_read_locks_set_field + * @brief macros for field rom_read_locks_set + * @details These bits go on to set sticky bits that lock up rom read. Each bit maps to one 2kB sector. Not self clearing + * @{ + */ +#define WRPRPINS_PROT_BITS_SET0__ROM_READ_LOCKS_SET__SHIFT 0 +#define WRPRPINS_PROT_BITS_SET0__ROM_READ_LOCKS_SET__WIDTH 32 +#define WRPRPINS_PROT_BITS_SET0__ROM_READ_LOCKS_SET__MASK 0xffffffffU +#define WRPRPINS_PROT_BITS_SET0__ROM_READ_LOCKS_SET__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_PROT_BITS_SET0__ROM_READ_LOCKS_SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_PROT_BITS_SET0__ROM_READ_LOCKS_SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_PROT_BITS_SET0__ROM_READ_LOCKS_SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_PROT_BITS_SET0__ROM_READ_LOCKS_SET__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_PROT_BITS_SET0__TYPE uint32_t +#define WRPRPINS_PROT_BITS_SET0__READ 0xffffffffU +#define WRPRPINS_PROT_BITS_SET0__WRITE 0xffffffffU +#define WRPRPINS_PROT_BITS_SET0__PRESERVED 0x00000000U +#define WRPRPINS_PROT_BITS_SET0__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_PROT_BITS_SET0_MACRO__ */ + +/** @} end of prot_bits_set0 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_prot_bits_set1 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_prot_bits_set1 prot_bits_set1 + * @brief Not self-clearing definitions. + * @{ + */ +#ifndef __WRPRPINS_PROT_BITS_SET1_MACRO__ +#define __WRPRPINS_PROT_BITS_SET1_MACRO__ + +/* macros for field uart0_lock_set */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_uart0_lock_set_field uart0_lock_set_field + * @brief macros for field uart0_lock_set + * @details sets sticky bit disabling uart0_tx. + * @{ + */ +#define WRPRPINS_PROT_BITS_SET1__UART0_LOCK_SET__SHIFT 0 +#define WRPRPINS_PROT_BITS_SET1__UART0_LOCK_SET__WIDTH 1 +#define WRPRPINS_PROT_BITS_SET1__UART0_LOCK_SET__MASK 0x00000001U +#define WRPRPINS_PROT_BITS_SET1__UART0_LOCK_SET__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_PROT_BITS_SET1__UART0_LOCK_SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_PROT_BITS_SET1__UART0_LOCK_SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_PROT_BITS_SET1__UART0_LOCK_SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_PROT_BITS_SET1__UART0_LOCK_SET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_PROT_BITS_SET1__UART0_LOCK_SET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_PROT_BITS_SET1__UART0_LOCK_SET__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field uart1_lock_set */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_uart1_lock_set_field uart1_lock_set_field + * @brief macros for field uart1_lock_set + * @details sets sticky bit disabling uart1_tx. + * @{ + */ +#define WRPRPINS_PROT_BITS_SET1__UART1_LOCK_SET__SHIFT 1 +#define WRPRPINS_PROT_BITS_SET1__UART1_LOCK_SET__WIDTH 1 +#define WRPRPINS_PROT_BITS_SET1__UART1_LOCK_SET__MASK 0x00000002U +#define WRPRPINS_PROT_BITS_SET1__UART1_LOCK_SET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRPINS_PROT_BITS_SET1__UART1_LOCK_SET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRPINS_PROT_BITS_SET1__UART1_LOCK_SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRPINS_PROT_BITS_SET1__UART1_LOCK_SET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRPINS_PROT_BITS_SET1__UART1_LOCK_SET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRPINS_PROT_BITS_SET1__UART1_LOCK_SET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRPINS_PROT_BITS_SET1__UART1_LOCK_SET__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field apb_qspi_lock_set */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_apb_qspi_lock_set_field apb_qspi_lock_set_field + * @brief macros for field apb_qspi_lock_set + * @details sets sticky bit disabling APB cores accessing qspi. + * @{ + */ +#define WRPRPINS_PROT_BITS_SET1__APB_QSPI_LOCK_SET__SHIFT 2 +#define WRPRPINS_PROT_BITS_SET1__APB_QSPI_LOCK_SET__WIDTH 1 +#define WRPRPINS_PROT_BITS_SET1__APB_QSPI_LOCK_SET__MASK 0x00000004U +#define WRPRPINS_PROT_BITS_SET1__APB_QSPI_LOCK_SET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRPINS_PROT_BITS_SET1__APB_QSPI_LOCK_SET__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRPINS_PROT_BITS_SET1__APB_QSPI_LOCK_SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRPINS_PROT_BITS_SET1__APB_QSPI_LOCK_SET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRPINS_PROT_BITS_SET1__APB_QSPI_LOCK_SET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRPINS_PROT_BITS_SET1__APB_QSPI_LOCK_SET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRPINS_PROT_BITS_SET1__APB_QSPI_LOCK_SET__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field apb_shub_lock_set */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_apb_shub_lock_set_field apb_shub_lock_set_field + * @brief macros for field apb_shub_lock_set + * @details sets sticky bit disabling the update of write address range. + * @{ + */ +#define WRPRPINS_PROT_BITS_SET1__APB_SHUB_LOCK_SET__SHIFT 3 +#define WRPRPINS_PROT_BITS_SET1__APB_SHUB_LOCK_SET__WIDTH 1 +#define WRPRPINS_PROT_BITS_SET1__APB_SHUB_LOCK_SET__MASK 0x00000008U +#define WRPRPINS_PROT_BITS_SET1__APB_SHUB_LOCK_SET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define WRPRPINS_PROT_BITS_SET1__APB_SHUB_LOCK_SET__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define WRPRPINS_PROT_BITS_SET1__APB_SHUB_LOCK_SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define WRPRPINS_PROT_BITS_SET1__APB_SHUB_LOCK_SET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define WRPRPINS_PROT_BITS_SET1__APB_SHUB_LOCK_SET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define WRPRPINS_PROT_BITS_SET1__APB_SHUB_LOCK_SET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define WRPRPINS_PROT_BITS_SET1__APB_SHUB_LOCK_SET__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field suppress_rom_patch */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_suppress_rom_patch_field suppress_rom_patch_field + * @brief macros for field suppress_rom_patch + * @details sets sticky bit preventing ROM patches from being applied + * @{ + */ +#define WRPRPINS_PROT_BITS_SET1__SUPPRESS_ROM_PATCH__SHIFT 4 +#define WRPRPINS_PROT_BITS_SET1__SUPPRESS_ROM_PATCH__WIDTH 1 +#define WRPRPINS_PROT_BITS_SET1__SUPPRESS_ROM_PATCH__MASK 0x00000010U +#define WRPRPINS_PROT_BITS_SET1__SUPPRESS_ROM_PATCH__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define WRPRPINS_PROT_BITS_SET1__SUPPRESS_ROM_PATCH__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define WRPRPINS_PROT_BITS_SET1__SUPPRESS_ROM_PATCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define WRPRPINS_PROT_BITS_SET1__SUPPRESS_ROM_PATCH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define WRPRPINS_PROT_BITS_SET1__SUPPRESS_ROM_PATCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define WRPRPINS_PROT_BITS_SET1__SUPPRESS_ROM_PATCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define WRPRPINS_PROT_BITS_SET1__SUPPRESS_ROM_PATCH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field suppress_otp_writes */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_suppress_otp_writes_field suppress_otp_writes_field + * @brief macros for field suppress_otp_writes + * @details sets sticky bit preventing OTP writes + * @{ + */ +#define WRPRPINS_PROT_BITS_SET1__SUPPRESS_OTP_WRITES__SHIFT 5 +#define WRPRPINS_PROT_BITS_SET1__SUPPRESS_OTP_WRITES__WIDTH 1 +#define WRPRPINS_PROT_BITS_SET1__SUPPRESS_OTP_WRITES__MASK 0x00000020U +#define WRPRPINS_PROT_BITS_SET1__SUPPRESS_OTP_WRITES__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define WRPRPINS_PROT_BITS_SET1__SUPPRESS_OTP_WRITES__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define WRPRPINS_PROT_BITS_SET1__SUPPRESS_OTP_WRITES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define WRPRPINS_PROT_BITS_SET1__SUPPRESS_OTP_WRITES__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define WRPRPINS_PROT_BITS_SET1__SUPPRESS_OTP_WRITES__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define WRPRPINS_PROT_BITS_SET1__SUPPRESS_OTP_WRITES__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define WRPRPINS_PROT_BITS_SET1__SUPPRESS_OTP_WRITES__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_PROT_BITS_SET1__TYPE uint32_t +#define WRPRPINS_PROT_BITS_SET1__READ 0x0000003fU +#define WRPRPINS_PROT_BITS_SET1__WRITE 0x0000003fU +#define WRPRPINS_PROT_BITS_SET1__PRESERVED 0x00000000U +#define WRPRPINS_PROT_BITS_SET1__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_PROT_BITS_SET1_MACRO__ */ + +/** @} end of prot_bits_set1 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_prot_bits_stat0 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_prot_bits_stat0 prot_bits_stat0 + * @brief Contains register fields associated with prot_bits_stat0. definitions. + * @{ + */ +#ifndef __WRPRPINS_PROT_BITS_STAT0_MACRO__ +#define __WRPRPINS_PROT_BITS_STAT0_MACRO__ + +/* macros for field rom_read_locks_stat */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_rom_read_locks_stat_field rom_read_locks_stat_field + * @brief macros for field rom_read_locks_stat + * @details sticky bits that lock up rom read. Each bit maps to one 2kB sector. Not self clearing + * @{ + */ +#define WRPRPINS_PROT_BITS_STAT0__ROM_READ_LOCKS_STAT__SHIFT 0 +#define WRPRPINS_PROT_BITS_STAT0__ROM_READ_LOCKS_STAT__WIDTH 32 +#define WRPRPINS_PROT_BITS_STAT0__ROM_READ_LOCKS_STAT__MASK 0xffffffffU +#define WRPRPINS_PROT_BITS_STAT0__ROM_READ_LOCKS_STAT__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_PROT_BITS_STAT0__ROM_READ_LOCKS_STAT__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_PROT_BITS_STAT0__TYPE uint32_t +#define WRPRPINS_PROT_BITS_STAT0__READ 0xffffffffU +#define WRPRPINS_PROT_BITS_STAT0__PRESERVED 0x00000000U +#define WRPRPINS_PROT_BITS_STAT0__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_PROT_BITS_STAT0_MACRO__ */ + +/** @} end of prot_bits_stat0 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_prot_bits_stat1 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_prot_bits_stat1 prot_bits_stat1 + * @brief Not self-clearing definitions. + * @{ + */ +#ifndef __WRPRPINS_PROT_BITS_STAT1_MACRO__ +#define __WRPRPINS_PROT_BITS_STAT1_MACRO__ + +/* macros for field uart0_lock_stat */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_uart0_lock_stat_field uart0_lock_stat_field + * @brief macros for field uart0_lock_stat + * @details sticky bit disabling uart0_tx. + * @{ + */ +#define WRPRPINS_PROT_BITS_STAT1__UART0_LOCK_STAT__SHIFT 0 +#define WRPRPINS_PROT_BITS_STAT1__UART0_LOCK_STAT__WIDTH 1 +#define WRPRPINS_PROT_BITS_STAT1__UART0_LOCK_STAT__MASK 0x00000001U +#define WRPRPINS_PROT_BITS_STAT1__UART0_LOCK_STAT__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_PROT_BITS_STAT1__UART0_LOCK_STAT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_PROT_BITS_STAT1__UART0_LOCK_STAT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_PROT_BITS_STAT1__UART0_LOCK_STAT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field uart1_lock_stat */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_uart1_lock_stat_field uart1_lock_stat_field + * @brief macros for field uart1_lock_stat + * @details sticky bit disabling uart1_tx. + * @{ + */ +#define WRPRPINS_PROT_BITS_STAT1__UART1_LOCK_STAT__SHIFT 1 +#define WRPRPINS_PROT_BITS_STAT1__UART1_LOCK_STAT__WIDTH 1 +#define WRPRPINS_PROT_BITS_STAT1__UART1_LOCK_STAT__MASK 0x00000002U +#define WRPRPINS_PROT_BITS_STAT1__UART1_LOCK_STAT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRPINS_PROT_BITS_STAT1__UART1_LOCK_STAT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRPINS_PROT_BITS_STAT1__UART1_LOCK_STAT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRPINS_PROT_BITS_STAT1__UART1_LOCK_STAT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field apb_qspi_lock_stat */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_apb_qspi_lock_stat_field apb_qspi_lock_stat_field + * @brief macros for field apb_qspi_lock_stat + * @details sticky bit disabling APB cores accessing qspi. + * @{ + */ +#define WRPRPINS_PROT_BITS_STAT1__APB_QSPI_LOCK_STAT__SHIFT 2 +#define WRPRPINS_PROT_BITS_STAT1__APB_QSPI_LOCK_STAT__WIDTH 1 +#define WRPRPINS_PROT_BITS_STAT1__APB_QSPI_LOCK_STAT__MASK 0x00000004U +#define WRPRPINS_PROT_BITS_STAT1__APB_QSPI_LOCK_STAT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRPINS_PROT_BITS_STAT1__APB_QSPI_LOCK_STAT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRPINS_PROT_BITS_STAT1__APB_QSPI_LOCK_STAT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRPINS_PROT_BITS_STAT1__APB_QSPI_LOCK_STAT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field apb_shub_lock_stat */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_apb_shub_lock_stat_field apb_shub_lock_stat_field + * @brief macros for field apb_shub_lock_stat + * @details sticky bit disabling shub write address range. + * @{ + */ +#define WRPRPINS_PROT_BITS_STAT1__APB_SHUB_LOCK_STAT__SHIFT 3 +#define WRPRPINS_PROT_BITS_STAT1__APB_SHUB_LOCK_STAT__WIDTH 1 +#define WRPRPINS_PROT_BITS_STAT1__APB_SHUB_LOCK_STAT__MASK 0x00000008U +#define WRPRPINS_PROT_BITS_STAT1__APB_SHUB_LOCK_STAT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define WRPRPINS_PROT_BITS_STAT1__APB_SHUB_LOCK_STAT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define WRPRPINS_PROT_BITS_STAT1__APB_SHUB_LOCK_STAT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define WRPRPINS_PROT_BITS_STAT1__APB_SHUB_LOCK_STAT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field suppress_rom_patch_stat */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_suppress_rom_patch_stat_field suppress_rom_patch_stat_field + * @brief macros for field suppress_rom_patch_stat + * @details sticky bit preventing ROM patches from being applied + * @{ + */ +#define WRPRPINS_PROT_BITS_STAT1__SUPPRESS_ROM_PATCH_STAT__SHIFT 4 +#define WRPRPINS_PROT_BITS_STAT1__SUPPRESS_ROM_PATCH_STAT__WIDTH 1 +#define WRPRPINS_PROT_BITS_STAT1__SUPPRESS_ROM_PATCH_STAT__MASK 0x00000010U +#define WRPRPINS_PROT_BITS_STAT1__SUPPRESS_ROM_PATCH_STAT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define WRPRPINS_PROT_BITS_STAT1__SUPPRESS_ROM_PATCH_STAT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define WRPRPINS_PROT_BITS_STAT1__SUPPRESS_ROM_PATCH_STAT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define WRPRPINS_PROT_BITS_STAT1__SUPPRESS_ROM_PATCH_STAT__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field suppress_otp_writes_stat */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_suppress_otp_writes_stat_field suppress_otp_writes_stat_field + * @brief macros for field suppress_otp_writes_stat + * @details sticky bit preventing OTP writes + * @{ + */ +#define WRPRPINS_PROT_BITS_STAT1__SUPPRESS_OTP_WRITES_STAT__SHIFT 5 +#define WRPRPINS_PROT_BITS_STAT1__SUPPRESS_OTP_WRITES_STAT__WIDTH 1 +#define WRPRPINS_PROT_BITS_STAT1__SUPPRESS_OTP_WRITES_STAT__MASK 0x00000020U +#define WRPRPINS_PROT_BITS_STAT1__SUPPRESS_OTP_WRITES_STAT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define WRPRPINS_PROT_BITS_STAT1__SUPPRESS_OTP_WRITES_STAT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define WRPRPINS_PROT_BITS_STAT1__SUPPRESS_OTP_WRITES_STAT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define WRPRPINS_PROT_BITS_STAT1__SUPPRESS_OTP_WRITES_STAT__RESET_VALUE \ + 0x00000000U +/** @} */ +#define WRPRPINS_PROT_BITS_STAT1__TYPE uint32_t +#define WRPRPINS_PROT_BITS_STAT1__READ 0x0000003fU +#define WRPRPINS_PROT_BITS_STAT1__PRESERVED 0x00000000U +#define WRPRPINS_PROT_BITS_STAT1__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_PROT_BITS_STAT1_MACRO__ */ + +/** @} end of prot_bits_stat1 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_qspi_sticky_write_protection0 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_qspi_sticky_write_protection0 qspi_sticky_write_protection0 + * @brief Contains register fields associated with qspi_sticky_write_protection0. definitions. + * @{ + */ +#ifndef __WRPRPINS_QSPI_STICKY_WRITE_PROTECTION0_MACRO__ +#define __WRPRPINS_QSPI_STICKY_WRITE_PROTECTION0_MACRO__ + +/* macros for field set */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_set_field set_field + * @brief macros for field set + * @details if a bit is set, invalidates any writes to the corresponding 2kB block, can only revert with cpu reset + * @{ + */ +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION0__SET__SHIFT 0 +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION0__SET__WIDTH 32 +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION0__SET__MASK 0xffffffffU +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION0__SET__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION0__SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION0__SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION0__SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION0__SET__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION0__TYPE uint32_t +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION0__READ 0xffffffffU +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION0__WRITE 0xffffffffU +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION0__PRESERVED 0x00000000U +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION0__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_QSPI_STICKY_WRITE_PROTECTION0_MACRO__ */ + +/** @} end of qspi_sticky_write_protection0 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_qspi_sticky_write_protection1 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_qspi_sticky_write_protection1 qspi_sticky_write_protection1 + * @brief Contains register fields associated with qspi_sticky_write_protection1. definitions. + * @{ + */ +#ifndef __WRPRPINS_QSPI_STICKY_WRITE_PROTECTION1_MACRO__ +#define __WRPRPINS_QSPI_STICKY_WRITE_PROTECTION1_MACRO__ + +/* macros for field set */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_set_field set_field + * @brief macros for field set + * @{ + */ +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION1__SET__SHIFT 0 +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION1__SET__WIDTH 32 +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION1__SET__MASK 0xffffffffU +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION1__SET__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION1__SET__WRITE(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION1__SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION1__SET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION1__SET__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION1__TYPE uint32_t +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION1__READ 0xffffffffU +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION1__WRITE 0xffffffffU +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION1__PRESERVED 0x00000000U +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION1__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_QSPI_STICKY_WRITE_PROTECTION1_MACRO__ */ + +/** @} end of qspi_sticky_write_protection1 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_qspi_sticky_write_protection_status0 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_qspi_sticky_write_protection_status0 qspi_sticky_write_protection_status0 + * @brief Contains register fields associated with qspi_sticky_write_protection_status0. definitions. + * @{ + */ +#ifndef __WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS0_MACRO__ +#define __WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS0_MACRO__ + +/* macros for field val */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_val_field val_field + * @brief macros for field val + * @details if read back value is 1, then the sticky bit has been set + * @{ + */ +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS0__VAL__SHIFT 0 +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS0__VAL__WIDTH 32 +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS0__VAL__MASK 0xffffffffU +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS0__VAL__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS0__VAL__RESET_VALUE \ + 0x00000000U +/** @} */ +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS0__TYPE uint32_t +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS0__READ 0xffffffffU +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS0__PRESERVED 0x00000000U +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS0__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS0_MACRO__ */ + +/** @} end of qspi_sticky_write_protection_status0 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_qspi_sticky_write_protection_status1 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_qspi_sticky_write_protection_status1 qspi_sticky_write_protection_status1 + * @brief Contains register fields associated with qspi_sticky_write_protection_status1. definitions. + * @{ + */ +#ifndef __WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS1_MACRO__ +#define __WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS1_MACRO__ + +/* macros for field val */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_val_field val_field + * @brief macros for field val + * @{ + */ +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS1__VAL__SHIFT 0 +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS1__VAL__WIDTH 32 +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS1__VAL__MASK 0xffffffffU +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS1__VAL__READ(src) \ + ((uint32_t)(src)\ + & 0xffffffffU) +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS1__VAL__RESET_VALUE \ + 0x00000000U +/** @} */ +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS1__TYPE uint32_t +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS1__READ 0xffffffffU +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS1__PRESERVED 0x00000000U +#define WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS1__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_QSPI_STICKY_WRITE_PROTECTION_STATUS1_MACRO__ */ + +/** @} end of qspi_sticky_write_protection_status1 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_pdsn */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_pdsn pdsn + * @brief pin drive strength definitions. + * @{ + */ +#ifndef __WRPRPINS_PDSN_MACRO__ +#define __WRPRPINS_PDSN_MACRO__ + +/* macros for field is_high */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_is_high_field is_high_field + * @brief macros for field is_high + * @details 0=high drive stength/lower impedance 1=low drive strength/higher impedance + * @{ + */ +#define WRPRPINS_PDSN__IS_HIGH__SHIFT 0 +#define WRPRPINS_PDSN__IS_HIGH__WIDTH 31 +#define WRPRPINS_PDSN__IS_HIGH__MASK 0x7fffffffU +#define WRPRPINS_PDSN__IS_HIGH__READ(src) ((uint32_t)(src) & 0x7fffffffU) +#define WRPRPINS_PDSN__IS_HIGH__WRITE(src) ((uint32_t)(src) & 0x7fffffffU) +#define WRPRPINS_PDSN__IS_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7fffffffU) | ((uint32_t)(src) &\ + 0x7fffffffU) +#define WRPRPINS_PDSN__IS_HIGH__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x7fffffffU))) +#define WRPRPINS_PDSN__IS_HIGH__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_PDSN__TYPE uint32_t +#define WRPRPINS_PDSN__READ 0x7fffffffU +#define WRPRPINS_PDSN__WRITE 0x7fffffffU +#define WRPRPINS_PDSN__PRESERVED 0x00000000U +#define WRPRPINS_PDSN__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_PDSN_MACRO__ */ + +/** @} end of pdsn */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_calCountRC */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_calCountRC calCountRC + * @brief Contains register fields associated with calCountRC. definitions. + * @{ + */ +#ifndef __WRPRPINS_CALCOUNTRC_MACRO__ +#define __WRPRPINS_CALCOUNTRC_MACRO__ + +/* macros for field val */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_val_field val_field + * @brief macros for field val + * @{ + */ +#define WRPRPINS_CALCOUNTRC__VAL__SHIFT 0 +#define WRPRPINS_CALCOUNTRC__VAL__WIDTH 23 +#define WRPRPINS_CALCOUNTRC__VAL__MASK 0x007fffffU +#define WRPRPINS_CALCOUNTRC__VAL__READ(src) ((uint32_t)(src) & 0x007fffffU) +#define WRPRPINS_CALCOUNTRC__VAL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_CALCOUNTRC__TYPE uint32_t +#define WRPRPINS_CALCOUNTRC__READ 0x007fffffU +#define WRPRPINS_CALCOUNTRC__PRESERVED 0x00000000U +#define WRPRPINS_CALCOUNTRC__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_CALCOUNTRC_MACRO__ */ + +/** @} end of calCountRC */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_secure_debug_ctrl */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_secure_debug_ctrl secure_debug_ctrl + * @brief Contains register fields associated with secure_debug_ctrl. definitions. + * @{ + */ +#ifndef __WRPRPINS_SECURE_DEBUG_CTRL_MACRO__ +#define __WRPRPINS_SECURE_DEBUG_CTRL_MACRO__ + +/* macros for field soft_disabled */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_soft_disabled_field soft_disabled_field + * @brief macros for field soft_disabled + * @details if sticky_disabled is 0, SW can write 0 to enable SWD interface. Read value reflects the state of the secure debug FSM. + * @{ + */ +#define WRPRPINS_SECURE_DEBUG_CTRL__SOFT_DISABLED__SHIFT 0 +#define WRPRPINS_SECURE_DEBUG_CTRL__SOFT_DISABLED__WIDTH 1 +#define WRPRPINS_SECURE_DEBUG_CTRL__SOFT_DISABLED__MASK 0x00000001U +#define WRPRPINS_SECURE_DEBUG_CTRL__SOFT_DISABLED__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_SECURE_DEBUG_CTRL__SOFT_DISABLED__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRPINS_SECURE_DEBUG_CTRL__SOFT_DISABLED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRPINS_SECURE_DEBUG_CTRL__SOFT_DISABLED__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRPINS_SECURE_DEBUG_CTRL__SOFT_DISABLED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRPINS_SECURE_DEBUG_CTRL__SOFT_DISABLED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRPINS_SECURE_DEBUG_CTRL__SOFT_DISABLED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sticky_disabled */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sticky_disabled_field sticky_disabled_field + * @brief macros for field sticky_disabled + * @details software writes 1 during bootload time to disable SWD interface. Read value reflects the state of the secure debug FSM. + * @{ + */ +#define WRPRPINS_SECURE_DEBUG_CTRL__STICKY_DISABLED__SHIFT 1 +#define WRPRPINS_SECURE_DEBUG_CTRL__STICKY_DISABLED__WIDTH 1 +#define WRPRPINS_SECURE_DEBUG_CTRL__STICKY_DISABLED__MASK 0x00000002U +#define WRPRPINS_SECURE_DEBUG_CTRL__STICKY_DISABLED__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRPINS_SECURE_DEBUG_CTRL__STICKY_DISABLED__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRPINS_SECURE_DEBUG_CTRL__STICKY_DISABLED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRPINS_SECURE_DEBUG_CTRL__STICKY_DISABLED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRPINS_SECURE_DEBUG_CTRL__STICKY_DISABLED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRPINS_SECURE_DEBUG_CTRL__STICKY_DISABLED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRPINS_SECURE_DEBUG_CTRL__STICKY_DISABLED__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_SECURE_DEBUG_CTRL__TYPE uint32_t +#define WRPRPINS_SECURE_DEBUG_CTRL__READ 0x00000003U +#define WRPRPINS_SECURE_DEBUG_CTRL__WRITE 0x00000003U +#define WRPRPINS_SECURE_DEBUG_CTRL__PRESERVED 0x00000000U +#define WRPRPINS_SECURE_DEBUG_CTRL__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_SECURE_DEBUG_CTRL_MACRO__ */ + +/** @} end of secure_debug_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_secure_debug_stat */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_secure_debug_stat secure_debug_stat + * @brief Contains register fields associated with secure_debug_stat. definitions. + * @{ + */ +#ifndef __WRPRPINS_SECURE_DEBUG_STAT_MACRO__ +#define __WRPRPINS_SECURE_DEBUG_STAT_MACRO__ + +/* macros for field sec_dbg_fsm */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_sec_dbg_fsm_field sec_dbg_fsm_field + * @brief macros for field sec_dbg_fsm + * @details state of secure debug FSM. + * @{ + */ +#define WRPRPINS_SECURE_DEBUG_STAT__SEC_DBG_FSM__SHIFT 0 +#define WRPRPINS_SECURE_DEBUG_STAT__SEC_DBG_FSM__WIDTH 3 +#define WRPRPINS_SECURE_DEBUG_STAT__SEC_DBG_FSM__MASK 0x00000007U +#define WRPRPINS_SECURE_DEBUG_STAT__SEC_DBG_FSM__READ(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define WRPRPINS_SECURE_DEBUG_STAT__SEC_DBG_FSM__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_SECURE_DEBUG_STAT__TYPE uint32_t +#define WRPRPINS_SECURE_DEBUG_STAT__READ 0x00000007U +#define WRPRPINS_SECURE_DEBUG_STAT__PRESERVED 0x00000000U +#define WRPRPINS_SECURE_DEBUG_STAT__RESET_VALUE 0x00000000U + +#endif /* __WRPRPINS_SECURE_DEBUG_STAT_MACRO__ */ + +/** @} end of secure_debug_stat */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_chipid1 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_chipid1 chipid1 + * @brief Contains register fields associated with chipid1. definitions. + * @{ + */ +#ifndef __WRPRPINS_CHIPID1_MACRO__ +#define __WRPRPINS_CHIPID1_MACRO__ + +/* macros for field char3 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_char3_field char3_field + * @brief macros for field char3 + * @details i + * @{ + */ +#define WRPRPINS_CHIPID1__CHAR3__SHIFT 0 +#define WRPRPINS_CHIPID1__CHAR3__WIDTH 8 +#define WRPRPINS_CHIPID1__CHAR3__MASK 0x000000ffU +#define WRPRPINS_CHIPID1__CHAR3__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define WRPRPINS_CHIPID1__CHAR3__RESET_VALUE 0x00000069U +/** @} */ + +/* macros for field char2 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_char2_field char2_field + * @brief macros for field char2 + * @details r + * @{ + */ +#define WRPRPINS_CHIPID1__CHAR2__SHIFT 8 +#define WRPRPINS_CHIPID1__CHAR2__WIDTH 8 +#define WRPRPINS_CHIPID1__CHAR2__MASK 0x0000ff00U +#define WRPRPINS_CHIPID1__CHAR2__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define WRPRPINS_CHIPID1__CHAR2__RESET_VALUE 0x00000072U +/** @} */ + +/* macros for field char1 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_char1_field char1_field + * @brief macros for field char1 + * @details a + * @{ + */ +#define WRPRPINS_CHIPID1__CHAR1__SHIFT 16 +#define WRPRPINS_CHIPID1__CHAR1__WIDTH 8 +#define WRPRPINS_CHIPID1__CHAR1__MASK 0x00ff0000U +#define WRPRPINS_CHIPID1__CHAR1__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define WRPRPINS_CHIPID1__CHAR1__RESET_VALUE 0x00000061U +/** @} */ + +/* macros for field char0 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_char0_field char0_field + * @brief macros for field char0 + * @details P + * @{ + */ +#define WRPRPINS_CHIPID1__CHAR0__SHIFT 24 +#define WRPRPINS_CHIPID1__CHAR0__WIDTH 8 +#define WRPRPINS_CHIPID1__CHAR0__MASK 0xff000000U +#define WRPRPINS_CHIPID1__CHAR0__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define WRPRPINS_CHIPID1__CHAR0__RESET_VALUE 0x00000050U +/** @} */ +#define WRPRPINS_CHIPID1__TYPE uint32_t +#define WRPRPINS_CHIPID1__READ 0xffffffffU +#define WRPRPINS_CHIPID1__PRESERVED 0x00000000U +#define WRPRPINS_CHIPID1__RESET_VALUE 0x50617269U + +#endif /* __WRPRPINS_CHIPID1_MACRO__ */ + +/** @} end of chipid1 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_chipid2 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_chipid2 chipid2 + * @brief Contains register fields associated with chipid2. definitions. + * @{ + */ +#ifndef __WRPRPINS_CHIPID2_MACRO__ +#define __WRPRPINS_CHIPID2_MACRO__ + +/* macros for field char7 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_char7_field char7_field + * @brief macros for field char7 + * @details nul + * @{ + */ +#define WRPRPINS_CHIPID2__CHAR7__SHIFT 0 +#define WRPRPINS_CHIPID2__CHAR7__WIDTH 8 +#define WRPRPINS_CHIPID2__CHAR7__MASK 0x000000ffU +#define WRPRPINS_CHIPID2__CHAR7__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define WRPRPINS_CHIPID2__CHAR7__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field char6 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_char6_field char6_field + * @brief macros for field char6 + * @details nul + * @{ + */ +#define WRPRPINS_CHIPID2__CHAR6__SHIFT 8 +#define WRPRPINS_CHIPID2__CHAR6__WIDTH 8 +#define WRPRPINS_CHIPID2__CHAR6__MASK 0x0000ff00U +#define WRPRPINS_CHIPID2__CHAR6__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define WRPRPINS_CHIPID2__CHAR6__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field char5 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_char5_field char5_field + * @brief macros for field char5 + * @details nul + * @{ + */ +#define WRPRPINS_CHIPID2__CHAR5__SHIFT 16 +#define WRPRPINS_CHIPID2__CHAR5__WIDTH 8 +#define WRPRPINS_CHIPID2__CHAR5__MASK 0x00ff0000U +#define WRPRPINS_CHIPID2__CHAR5__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define WRPRPINS_CHIPID2__CHAR5__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field char4 */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_char4_field char4_field + * @brief macros for field char4 + * @details s + * @{ + */ +#define WRPRPINS_CHIPID2__CHAR4__SHIFT 24 +#define WRPRPINS_CHIPID2__CHAR4__WIDTH 8 +#define WRPRPINS_CHIPID2__CHAR4__MASK 0xff000000U +#define WRPRPINS_CHIPID2__CHAR4__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define WRPRPINS_CHIPID2__CHAR4__RESET_VALUE 0x00000073U +/** @} */ +#define WRPRPINS_CHIPID2__TYPE uint32_t +#define WRPRPINS_CHIPID2__READ 0xffffffffU +#define WRPRPINS_CHIPID2__PRESERVED 0x00000000U +#define WRPRPINS_CHIPID2__RESET_VALUE 0x73000000U + +#endif /* __WRPRPINS_CHIPID2_MACRO__ */ + +/** @} end of chipid2 */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_chiprev */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_chiprev chiprev + * @brief Contains register fields associated with chiprev. definitions. + * @{ + */ +#ifndef __WRPRPINS_CHIPREV_MACRO__ +#define __WRPRPINS_CHIPREV_MACRO__ + +/* macros for field minor */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_minor_field minor_field + * @brief macros for field minor + * @{ + */ +#define WRPRPINS_CHIPREV__MINOR__SHIFT 0 +#define WRPRPINS_CHIPREV__MINOR__WIDTH 8 +#define WRPRPINS_CHIPREV__MINOR__MASK 0x000000ffU +#define WRPRPINS_CHIPREV__MINOR__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define WRPRPINS_CHIPREV__MINOR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field major */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_major_field major_field + * @brief macros for field major + * @{ + */ +#define WRPRPINS_CHIPREV__MAJOR__SHIFT 8 +#define WRPRPINS_CHIPREV__MAJOR__WIDTH 8 +#define WRPRPINS_CHIPREV__MAJOR__MASK 0x0000ff00U +#define WRPRPINS_CHIPREV__MAJOR__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define WRPRPINS_CHIPREV__MAJOR__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field running_off_32khz_xtal */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_running_off_32khz_xtal_field running_off_32khz_xtal_field + * @brief macros for field running_off_32khz_xtal + * @{ + */ +#define WRPRPINS_CHIPREV__RUNNING_OFF_32KHZ_XTAL__SHIFT 16 +#define WRPRPINS_CHIPREV__RUNNING_OFF_32KHZ_XTAL__WIDTH 1 +#define WRPRPINS_CHIPREV__RUNNING_OFF_32KHZ_XTAL__MASK 0x00010000U +#define WRPRPINS_CHIPREV__RUNNING_OFF_32KHZ_XTAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define WRPRPINS_CHIPREV__RUNNING_OFF_32KHZ_XTAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define WRPRPINS_CHIPREV__RUNNING_OFF_32KHZ_XTAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define WRPRPINS_CHIPREV__RUNNING_OFF_32KHZ_XTAL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRPINS_CHIPREV__TYPE uint32_t +#define WRPRPINS_CHIPREV__READ 0x0001ffffU +#define WRPRPINS_CHIPREV__PRESERVED 0x00000000U +#define WRPRPINS_CHIPREV__RESET_VALUE 0x00000100U + +#endif /* __WRPRPINS_CHIPREV_MACRO__ */ + +/** @} end of chiprev */ + +/* macros for BlueprintGlobalNameSpace::WRPRPINS_core_id */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_core_id core_id + * @brief Contains register fields associated with core_id. definitions. + * @{ + */ +#ifndef __WRPRPINS_CORE_ID_MACRO__ +#define __WRPRPINS_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_wrpr_pins_regs_core_id_field id_field + * @brief macros for field id + * @details WRPR in ASCII + * @{ + */ +#define WRPRPINS_CORE_ID__ID__SHIFT 0 +#define WRPRPINS_CORE_ID__ID__WIDTH 32 +#define WRPRPINS_CORE_ID__ID__MASK 0xffffffffU +#define WRPRPINS_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define WRPRPINS_CORE_ID__ID__RESET_VALUE 0x57525052U +/** @} */ +#define WRPRPINS_CORE_ID__TYPE uint32_t +#define WRPRPINS_CORE_ID__READ 0xffffffffU +#define WRPRPINS_CORE_ID__PRESERVED 0x00000000U +#define WRPRPINS_CORE_ID__RESET_VALUE 0x57525052U + +#endif /* __WRPRPINS_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of AT_APB_WRPR_PINS_REGS_CORE */ +#endif /* __REG_AT_APB_WRPR_PINS_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_apb_wrpr_short_regs_core_macro.h b/ATM33xx-5/include/reg/at_apb_wrpr_short_regs_core_macro.h new file mode 100644 index 0000000..a817ff6 --- /dev/null +++ b/ATM33xx-5/include/reg/at_apb_wrpr_short_regs_core_macro.h @@ -0,0 +1,1854 @@ +/* */ +/* File: at_apb_wrpr_short_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_apb_wrpr_short_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_APB_WRPR_SHORT_REGS_CORE_H__ +#define __REG_AT_APB_WRPR_SHORT_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_APB_WRPR_SHORT_REGS_CORE at_apb_wrpr_short_regs_core + * @ingroup AT_REG + * @brief at_apb_wrpr_short_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::WRPRSHORT_apb0_ctrl */ +/** + * @defgroup at_apb_wrpr_short_regs_core_apb0_ctrl apb0_ctrl + * @brief Contains register fields associated with apb0_ctrl. definitions. + * @{ + */ +#ifndef __WRPRSHORT_APB0_CTRL_MACRO__ +#define __WRPRSHORT_APB0_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRSHORT_APB0_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRSHORT_APB0_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRSHORT_APB0_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRSHORT_APB0_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB0_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB0_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRSHORT_APB0_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRSHORT_APB0_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRSHORT_APB0_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRSHORT_APB0_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_short_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRSHORT_APB0_CTRL__SRESET__SHIFT 1 +#define WRPRSHORT_APB0_CTRL__SRESET__WIDTH 1 +#define WRPRSHORT_APB0_CTRL__SRESET__MASK 0x00000002U +#define WRPRSHORT_APB0_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRSHORT_APB0_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRSHORT_APB0_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRSHORT_APB0_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRSHORT_APB0_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRSHORT_APB0_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRSHORT_APB0_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRSHORT_APB0_CTRL__CLK_SEL__SHIFT 2 +#define WRPRSHORT_APB0_CTRL__CLK_SEL__WIDTH 1 +#define WRPRSHORT_APB0_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRSHORT_APB0_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRSHORT_APB0_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRSHORT_APB0_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRSHORT_APB0_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRSHORT_APB0_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRSHORT_APB0_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRSHORT_APB0_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRSHORT_APB0_CTRL__TYPE uint32_t +#define WRPRSHORT_APB0_CTRL__READ 0x00000007U +#define WRPRSHORT_APB0_CTRL__WRITE 0x00000007U +#define WRPRSHORT_APB0_CTRL__PRESERVED 0x00000000U +#define WRPRSHORT_APB0_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRSHORT_APB0_CTRL_MACRO__ */ + +/** @} end of apb0_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRSHORT_apb1_ctrl */ +/** + * @defgroup at_apb_wrpr_short_regs_core_apb1_ctrl apb1_ctrl + * @brief Contains register fields associated with apb1_ctrl. definitions. + * @{ + */ +#ifndef __WRPRSHORT_APB1_CTRL_MACRO__ +#define __WRPRSHORT_APB1_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRSHORT_APB1_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRSHORT_APB1_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRSHORT_APB1_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRSHORT_APB1_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB1_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB1_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRSHORT_APB1_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRSHORT_APB1_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRSHORT_APB1_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRSHORT_APB1_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_short_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRSHORT_APB1_CTRL__SRESET__SHIFT 1 +#define WRPRSHORT_APB1_CTRL__SRESET__WIDTH 1 +#define WRPRSHORT_APB1_CTRL__SRESET__MASK 0x00000002U +#define WRPRSHORT_APB1_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRSHORT_APB1_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRSHORT_APB1_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRSHORT_APB1_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRSHORT_APB1_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRSHORT_APB1_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRSHORT_APB1_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRSHORT_APB1_CTRL__CLK_SEL__SHIFT 2 +#define WRPRSHORT_APB1_CTRL__CLK_SEL__WIDTH 1 +#define WRPRSHORT_APB1_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRSHORT_APB1_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRSHORT_APB1_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRSHORT_APB1_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRSHORT_APB1_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRSHORT_APB1_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRSHORT_APB1_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRSHORT_APB1_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRSHORT_APB1_CTRL__TYPE uint32_t +#define WRPRSHORT_APB1_CTRL__READ 0x00000007U +#define WRPRSHORT_APB1_CTRL__WRITE 0x00000007U +#define WRPRSHORT_APB1_CTRL__PRESERVED 0x00000000U +#define WRPRSHORT_APB1_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRSHORT_APB1_CTRL_MACRO__ */ + +/** @} end of apb1_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRSHORT_apb2_ctrl */ +/** + * @defgroup at_apb_wrpr_short_regs_core_apb2_ctrl apb2_ctrl + * @brief Contains register fields associated with apb2_ctrl. definitions. + * @{ + */ +#ifndef __WRPRSHORT_APB2_CTRL_MACRO__ +#define __WRPRSHORT_APB2_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRSHORT_APB2_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRSHORT_APB2_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRSHORT_APB2_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRSHORT_APB2_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB2_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB2_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRSHORT_APB2_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRSHORT_APB2_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRSHORT_APB2_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRSHORT_APB2_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_short_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRSHORT_APB2_CTRL__SRESET__SHIFT 1 +#define WRPRSHORT_APB2_CTRL__SRESET__WIDTH 1 +#define WRPRSHORT_APB2_CTRL__SRESET__MASK 0x00000002U +#define WRPRSHORT_APB2_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRSHORT_APB2_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRSHORT_APB2_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRSHORT_APB2_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRSHORT_APB2_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRSHORT_APB2_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRSHORT_APB2_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRSHORT_APB2_CTRL__CLK_SEL__SHIFT 2 +#define WRPRSHORT_APB2_CTRL__CLK_SEL__WIDTH 1 +#define WRPRSHORT_APB2_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRSHORT_APB2_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRSHORT_APB2_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRSHORT_APB2_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRSHORT_APB2_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRSHORT_APB2_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRSHORT_APB2_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRSHORT_APB2_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRSHORT_APB2_CTRL__TYPE uint32_t +#define WRPRSHORT_APB2_CTRL__READ 0x00000007U +#define WRPRSHORT_APB2_CTRL__WRITE 0x00000007U +#define WRPRSHORT_APB2_CTRL__PRESERVED 0x00000000U +#define WRPRSHORT_APB2_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRSHORT_APB2_CTRL_MACRO__ */ + +/** @} end of apb2_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRSHORT_apb3_ctrl */ +/** + * @defgroup at_apb_wrpr_short_regs_core_apb3_ctrl apb3_ctrl + * @brief Contains register fields associated with apb3_ctrl. definitions. + * @{ + */ +#ifndef __WRPRSHORT_APB3_CTRL_MACRO__ +#define __WRPRSHORT_APB3_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRSHORT_APB3_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRSHORT_APB3_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRSHORT_APB3_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRSHORT_APB3_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB3_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB3_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRSHORT_APB3_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRSHORT_APB3_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRSHORT_APB3_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRSHORT_APB3_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_short_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRSHORT_APB3_CTRL__SRESET__SHIFT 1 +#define WRPRSHORT_APB3_CTRL__SRESET__WIDTH 1 +#define WRPRSHORT_APB3_CTRL__SRESET__MASK 0x00000002U +#define WRPRSHORT_APB3_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRSHORT_APB3_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRSHORT_APB3_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRSHORT_APB3_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRSHORT_APB3_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRSHORT_APB3_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRSHORT_APB3_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRSHORT_APB3_CTRL__CLK_SEL__SHIFT 2 +#define WRPRSHORT_APB3_CTRL__CLK_SEL__WIDTH 1 +#define WRPRSHORT_APB3_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRSHORT_APB3_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRSHORT_APB3_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRSHORT_APB3_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRSHORT_APB3_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRSHORT_APB3_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRSHORT_APB3_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRSHORT_APB3_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRSHORT_APB3_CTRL__TYPE uint32_t +#define WRPRSHORT_APB3_CTRL__READ 0x00000007U +#define WRPRSHORT_APB3_CTRL__WRITE 0x00000007U +#define WRPRSHORT_APB3_CTRL__PRESERVED 0x00000000U +#define WRPRSHORT_APB3_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRSHORT_APB3_CTRL_MACRO__ */ + +/** @} end of apb3_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRSHORT_apb4_ctrl */ +/** + * @defgroup at_apb_wrpr_short_regs_core_apb4_ctrl apb4_ctrl + * @brief Contains register fields associated with apb4_ctrl. definitions. + * @{ + */ +#ifndef __WRPRSHORT_APB4_CTRL_MACRO__ +#define __WRPRSHORT_APB4_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRSHORT_APB4_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRSHORT_APB4_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRSHORT_APB4_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRSHORT_APB4_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB4_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB4_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRSHORT_APB4_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRSHORT_APB4_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRSHORT_APB4_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRSHORT_APB4_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_short_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRSHORT_APB4_CTRL__SRESET__SHIFT 1 +#define WRPRSHORT_APB4_CTRL__SRESET__WIDTH 1 +#define WRPRSHORT_APB4_CTRL__SRESET__MASK 0x00000002U +#define WRPRSHORT_APB4_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRSHORT_APB4_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRSHORT_APB4_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRSHORT_APB4_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRSHORT_APB4_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRSHORT_APB4_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRSHORT_APB4_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRSHORT_APB4_CTRL__CLK_SEL__SHIFT 2 +#define WRPRSHORT_APB4_CTRL__CLK_SEL__WIDTH 1 +#define WRPRSHORT_APB4_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRSHORT_APB4_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRSHORT_APB4_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRSHORT_APB4_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRSHORT_APB4_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRSHORT_APB4_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRSHORT_APB4_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRSHORT_APB4_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRSHORT_APB4_CTRL__TYPE uint32_t +#define WRPRSHORT_APB4_CTRL__READ 0x00000007U +#define WRPRSHORT_APB4_CTRL__WRITE 0x00000007U +#define WRPRSHORT_APB4_CTRL__PRESERVED 0x00000000U +#define WRPRSHORT_APB4_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRSHORT_APB4_CTRL_MACRO__ */ + +/** @} end of apb4_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRSHORT_apb5_ctrl */ +/** + * @defgroup at_apb_wrpr_short_regs_core_apb5_ctrl apb5_ctrl + * @brief Contains register fields associated with apb5_ctrl. definitions. + * @{ + */ +#ifndef __WRPRSHORT_APB5_CTRL_MACRO__ +#define __WRPRSHORT_APB5_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRSHORT_APB5_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRSHORT_APB5_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRSHORT_APB5_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRSHORT_APB5_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB5_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB5_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRSHORT_APB5_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRSHORT_APB5_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRSHORT_APB5_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRSHORT_APB5_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_short_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRSHORT_APB5_CTRL__SRESET__SHIFT 1 +#define WRPRSHORT_APB5_CTRL__SRESET__WIDTH 1 +#define WRPRSHORT_APB5_CTRL__SRESET__MASK 0x00000002U +#define WRPRSHORT_APB5_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRSHORT_APB5_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRSHORT_APB5_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRSHORT_APB5_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRSHORT_APB5_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRSHORT_APB5_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRSHORT_APB5_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRSHORT_APB5_CTRL__CLK_SEL__SHIFT 2 +#define WRPRSHORT_APB5_CTRL__CLK_SEL__WIDTH 1 +#define WRPRSHORT_APB5_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRSHORT_APB5_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRSHORT_APB5_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRSHORT_APB5_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRSHORT_APB5_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRSHORT_APB5_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRSHORT_APB5_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRSHORT_APB5_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRSHORT_APB5_CTRL__TYPE uint32_t +#define WRPRSHORT_APB5_CTRL__READ 0x00000007U +#define WRPRSHORT_APB5_CTRL__WRITE 0x00000007U +#define WRPRSHORT_APB5_CTRL__PRESERVED 0x00000000U +#define WRPRSHORT_APB5_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRSHORT_APB5_CTRL_MACRO__ */ + +/** @} end of apb5_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRSHORT_apb6_ctrl */ +/** + * @defgroup at_apb_wrpr_short_regs_core_apb6_ctrl apb6_ctrl + * @brief Contains register fields associated with apb6_ctrl. definitions. + * @{ + */ +#ifndef __WRPRSHORT_APB6_CTRL_MACRO__ +#define __WRPRSHORT_APB6_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRSHORT_APB6_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRSHORT_APB6_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRSHORT_APB6_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRSHORT_APB6_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB6_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB6_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRSHORT_APB6_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRSHORT_APB6_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRSHORT_APB6_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRSHORT_APB6_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_short_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRSHORT_APB6_CTRL__SRESET__SHIFT 1 +#define WRPRSHORT_APB6_CTRL__SRESET__WIDTH 1 +#define WRPRSHORT_APB6_CTRL__SRESET__MASK 0x00000002U +#define WRPRSHORT_APB6_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRSHORT_APB6_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRSHORT_APB6_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRSHORT_APB6_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRSHORT_APB6_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRSHORT_APB6_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRSHORT_APB6_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRSHORT_APB6_CTRL__CLK_SEL__SHIFT 2 +#define WRPRSHORT_APB6_CTRL__CLK_SEL__WIDTH 1 +#define WRPRSHORT_APB6_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRSHORT_APB6_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRSHORT_APB6_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRSHORT_APB6_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRSHORT_APB6_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRSHORT_APB6_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRSHORT_APB6_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRSHORT_APB6_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRSHORT_APB6_CTRL__TYPE uint32_t +#define WRPRSHORT_APB6_CTRL__READ 0x00000007U +#define WRPRSHORT_APB6_CTRL__WRITE 0x00000007U +#define WRPRSHORT_APB6_CTRL__PRESERVED 0x00000000U +#define WRPRSHORT_APB6_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRSHORT_APB6_CTRL_MACRO__ */ + +/** @} end of apb6_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRSHORT_apb7_ctrl */ +/** + * @defgroup at_apb_wrpr_short_regs_core_apb7_ctrl apb7_ctrl + * @brief Contains register fields associated with apb7_ctrl. definitions. + * @{ + */ +#ifndef __WRPRSHORT_APB7_CTRL_MACRO__ +#define __WRPRSHORT_APB7_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRSHORT_APB7_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRSHORT_APB7_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRSHORT_APB7_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRSHORT_APB7_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB7_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB7_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRSHORT_APB7_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRSHORT_APB7_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRSHORT_APB7_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRSHORT_APB7_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_short_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRSHORT_APB7_CTRL__SRESET__SHIFT 1 +#define WRPRSHORT_APB7_CTRL__SRESET__WIDTH 1 +#define WRPRSHORT_APB7_CTRL__SRESET__MASK 0x00000002U +#define WRPRSHORT_APB7_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRSHORT_APB7_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRSHORT_APB7_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRSHORT_APB7_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRSHORT_APB7_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRSHORT_APB7_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRSHORT_APB7_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRSHORT_APB7_CTRL__CLK_SEL__SHIFT 2 +#define WRPRSHORT_APB7_CTRL__CLK_SEL__WIDTH 1 +#define WRPRSHORT_APB7_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRSHORT_APB7_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRSHORT_APB7_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRSHORT_APB7_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRSHORT_APB7_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRSHORT_APB7_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRSHORT_APB7_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRSHORT_APB7_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRSHORT_APB7_CTRL__TYPE uint32_t +#define WRPRSHORT_APB7_CTRL__READ 0x00000007U +#define WRPRSHORT_APB7_CTRL__WRITE 0x00000007U +#define WRPRSHORT_APB7_CTRL__PRESERVED 0x00000000U +#define WRPRSHORT_APB7_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRSHORT_APB7_CTRL_MACRO__ */ + +/** @} end of apb7_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRSHORT_apb8_ctrl */ +/** + * @defgroup at_apb_wrpr_short_regs_core_apb8_ctrl apb8_ctrl + * @brief Contains register fields associated with apb8_ctrl. definitions. + * @{ + */ +#ifndef __WRPRSHORT_APB8_CTRL_MACRO__ +#define __WRPRSHORT_APB8_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRSHORT_APB8_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRSHORT_APB8_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRSHORT_APB8_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRSHORT_APB8_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB8_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB8_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRSHORT_APB8_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRSHORT_APB8_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRSHORT_APB8_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRSHORT_APB8_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_short_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRSHORT_APB8_CTRL__SRESET__SHIFT 1 +#define WRPRSHORT_APB8_CTRL__SRESET__WIDTH 1 +#define WRPRSHORT_APB8_CTRL__SRESET__MASK 0x00000002U +#define WRPRSHORT_APB8_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRSHORT_APB8_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRSHORT_APB8_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRSHORT_APB8_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRSHORT_APB8_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRSHORT_APB8_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRSHORT_APB8_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRSHORT_APB8_CTRL__CLK_SEL__SHIFT 2 +#define WRPRSHORT_APB8_CTRL__CLK_SEL__WIDTH 1 +#define WRPRSHORT_APB8_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRSHORT_APB8_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRSHORT_APB8_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRSHORT_APB8_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRSHORT_APB8_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRSHORT_APB8_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRSHORT_APB8_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRSHORT_APB8_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRSHORT_APB8_CTRL__TYPE uint32_t +#define WRPRSHORT_APB8_CTRL__READ 0x00000007U +#define WRPRSHORT_APB8_CTRL__WRITE 0x00000007U +#define WRPRSHORT_APB8_CTRL__PRESERVED 0x00000000U +#define WRPRSHORT_APB8_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRSHORT_APB8_CTRL_MACRO__ */ + +/** @} end of apb8_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRSHORT_apb9_ctrl */ +/** + * @defgroup at_apb_wrpr_short_regs_core_apb9_ctrl apb9_ctrl + * @brief Contains register fields associated with apb9_ctrl. definitions. + * @{ + */ +#ifndef __WRPRSHORT_APB9_CTRL_MACRO__ +#define __WRPRSHORT_APB9_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRSHORT_APB9_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRSHORT_APB9_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRSHORT_APB9_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRSHORT_APB9_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB9_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB9_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRSHORT_APB9_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRSHORT_APB9_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRSHORT_APB9_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRSHORT_APB9_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_short_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRSHORT_APB9_CTRL__SRESET__SHIFT 1 +#define WRPRSHORT_APB9_CTRL__SRESET__WIDTH 1 +#define WRPRSHORT_APB9_CTRL__SRESET__MASK 0x00000002U +#define WRPRSHORT_APB9_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRSHORT_APB9_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRSHORT_APB9_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRSHORT_APB9_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRSHORT_APB9_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRSHORT_APB9_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRSHORT_APB9_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRSHORT_APB9_CTRL__CLK_SEL__SHIFT 2 +#define WRPRSHORT_APB9_CTRL__CLK_SEL__WIDTH 1 +#define WRPRSHORT_APB9_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRSHORT_APB9_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRSHORT_APB9_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRSHORT_APB9_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRSHORT_APB9_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRSHORT_APB9_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRSHORT_APB9_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRSHORT_APB9_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRSHORT_APB9_CTRL__TYPE uint32_t +#define WRPRSHORT_APB9_CTRL__READ 0x00000007U +#define WRPRSHORT_APB9_CTRL__WRITE 0x00000007U +#define WRPRSHORT_APB9_CTRL__PRESERVED 0x00000000U +#define WRPRSHORT_APB9_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRSHORT_APB9_CTRL_MACRO__ */ + +/** @} end of apb9_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRSHORT_apb10_ctrl */ +/** + * @defgroup at_apb_wrpr_short_regs_core_apb10_ctrl apb10_ctrl + * @brief Contains register fields associated with apb10_ctrl. definitions. + * @{ + */ +#ifndef __WRPRSHORT_APB10_CTRL_MACRO__ +#define __WRPRSHORT_APB10_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRSHORT_APB10_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRSHORT_APB10_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRSHORT_APB10_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRSHORT_APB10_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB10_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB10_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRSHORT_APB10_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRSHORT_APB10_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRSHORT_APB10_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRSHORT_APB10_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_short_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRSHORT_APB10_CTRL__SRESET__SHIFT 1 +#define WRPRSHORT_APB10_CTRL__SRESET__WIDTH 1 +#define WRPRSHORT_APB10_CTRL__SRESET__MASK 0x00000002U +#define WRPRSHORT_APB10_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRSHORT_APB10_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRSHORT_APB10_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRSHORT_APB10_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRSHORT_APB10_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRSHORT_APB10_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRSHORT_APB10_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRSHORT_APB10_CTRL__CLK_SEL__SHIFT 2 +#define WRPRSHORT_APB10_CTRL__CLK_SEL__WIDTH 1 +#define WRPRSHORT_APB10_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRSHORT_APB10_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRSHORT_APB10_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRSHORT_APB10_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRSHORT_APB10_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRSHORT_APB10_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRSHORT_APB10_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRSHORT_APB10_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRSHORT_APB10_CTRL__TYPE uint32_t +#define WRPRSHORT_APB10_CTRL__READ 0x00000007U +#define WRPRSHORT_APB10_CTRL__WRITE 0x00000007U +#define WRPRSHORT_APB10_CTRL__PRESERVED 0x00000000U +#define WRPRSHORT_APB10_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRSHORT_APB10_CTRL_MACRO__ */ + +/** @} end of apb10_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRSHORT_apb11_ctrl */ +/** + * @defgroup at_apb_wrpr_short_regs_core_apb11_ctrl apb11_ctrl + * @brief Contains register fields associated with apb11_ctrl. definitions. + * @{ + */ +#ifndef __WRPRSHORT_APB11_CTRL_MACRO__ +#define __WRPRSHORT_APB11_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRSHORT_APB11_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRSHORT_APB11_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRSHORT_APB11_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRSHORT_APB11_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB11_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB11_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRSHORT_APB11_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRSHORT_APB11_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRSHORT_APB11_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRSHORT_APB11_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_short_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRSHORT_APB11_CTRL__SRESET__SHIFT 1 +#define WRPRSHORT_APB11_CTRL__SRESET__WIDTH 1 +#define WRPRSHORT_APB11_CTRL__SRESET__MASK 0x00000002U +#define WRPRSHORT_APB11_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRSHORT_APB11_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRSHORT_APB11_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRSHORT_APB11_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRSHORT_APB11_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRSHORT_APB11_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRSHORT_APB11_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRSHORT_APB11_CTRL__CLK_SEL__SHIFT 2 +#define WRPRSHORT_APB11_CTRL__CLK_SEL__WIDTH 1 +#define WRPRSHORT_APB11_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRSHORT_APB11_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRSHORT_APB11_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRSHORT_APB11_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRSHORT_APB11_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRSHORT_APB11_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRSHORT_APB11_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRSHORT_APB11_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRSHORT_APB11_CTRL__TYPE uint32_t +#define WRPRSHORT_APB11_CTRL__READ 0x00000007U +#define WRPRSHORT_APB11_CTRL__WRITE 0x00000007U +#define WRPRSHORT_APB11_CTRL__PRESERVED 0x00000000U +#define WRPRSHORT_APB11_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRSHORT_APB11_CTRL_MACRO__ */ + +/** @} end of apb11_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRSHORT_apb12_ctrl */ +/** + * @defgroup at_apb_wrpr_short_regs_core_apb12_ctrl apb12_ctrl + * @brief Contains register fields associated with apb12_ctrl. definitions. + * @{ + */ +#ifndef __WRPRSHORT_APB12_CTRL_MACRO__ +#define __WRPRSHORT_APB12_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRSHORT_APB12_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRSHORT_APB12_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRSHORT_APB12_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRSHORT_APB12_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB12_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB12_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRSHORT_APB12_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRSHORT_APB12_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRSHORT_APB12_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRSHORT_APB12_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_short_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRSHORT_APB12_CTRL__SRESET__SHIFT 1 +#define WRPRSHORT_APB12_CTRL__SRESET__WIDTH 1 +#define WRPRSHORT_APB12_CTRL__SRESET__MASK 0x00000002U +#define WRPRSHORT_APB12_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRSHORT_APB12_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRSHORT_APB12_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRSHORT_APB12_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRSHORT_APB12_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRSHORT_APB12_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRSHORT_APB12_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRSHORT_APB12_CTRL__CLK_SEL__SHIFT 2 +#define WRPRSHORT_APB12_CTRL__CLK_SEL__WIDTH 1 +#define WRPRSHORT_APB12_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRSHORT_APB12_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRSHORT_APB12_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRSHORT_APB12_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRSHORT_APB12_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRSHORT_APB12_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRSHORT_APB12_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRSHORT_APB12_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRSHORT_APB12_CTRL__TYPE uint32_t +#define WRPRSHORT_APB12_CTRL__READ 0x00000007U +#define WRPRSHORT_APB12_CTRL__WRITE 0x00000007U +#define WRPRSHORT_APB12_CTRL__PRESERVED 0x00000000U +#define WRPRSHORT_APB12_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRSHORT_APB12_CTRL_MACRO__ */ + +/** @} end of apb12_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRSHORT_apb13_ctrl */ +/** + * @defgroup at_apb_wrpr_short_regs_core_apb13_ctrl apb13_ctrl + * @brief Contains register fields associated with apb13_ctrl. definitions. + * @{ + */ +#ifndef __WRPRSHORT_APB13_CTRL_MACRO__ +#define __WRPRSHORT_APB13_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRSHORT_APB13_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRSHORT_APB13_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRSHORT_APB13_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRSHORT_APB13_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB13_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB13_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRSHORT_APB13_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRSHORT_APB13_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRSHORT_APB13_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRSHORT_APB13_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_short_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRSHORT_APB13_CTRL__SRESET__SHIFT 1 +#define WRPRSHORT_APB13_CTRL__SRESET__WIDTH 1 +#define WRPRSHORT_APB13_CTRL__SRESET__MASK 0x00000002U +#define WRPRSHORT_APB13_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRSHORT_APB13_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRSHORT_APB13_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRSHORT_APB13_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRSHORT_APB13_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRSHORT_APB13_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRSHORT_APB13_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRSHORT_APB13_CTRL__CLK_SEL__SHIFT 2 +#define WRPRSHORT_APB13_CTRL__CLK_SEL__WIDTH 1 +#define WRPRSHORT_APB13_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRSHORT_APB13_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRSHORT_APB13_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRSHORT_APB13_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRSHORT_APB13_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRSHORT_APB13_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRSHORT_APB13_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRSHORT_APB13_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRSHORT_APB13_CTRL__TYPE uint32_t +#define WRPRSHORT_APB13_CTRL__READ 0x00000007U +#define WRPRSHORT_APB13_CTRL__WRITE 0x00000007U +#define WRPRSHORT_APB13_CTRL__PRESERVED 0x00000000U +#define WRPRSHORT_APB13_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRSHORT_APB13_CTRL_MACRO__ */ + +/** @} end of apb13_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRSHORT_apb14_ctrl */ +/** + * @defgroup at_apb_wrpr_short_regs_core_apb14_ctrl apb14_ctrl + * @brief Contains register fields associated with apb14_ctrl. definitions. + * @{ + */ +#ifndef __WRPRSHORT_APB14_CTRL_MACRO__ +#define __WRPRSHORT_APB14_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRSHORT_APB14_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRSHORT_APB14_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRSHORT_APB14_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRSHORT_APB14_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB14_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB14_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRSHORT_APB14_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRSHORT_APB14_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRSHORT_APB14_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRSHORT_APB14_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_short_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRSHORT_APB14_CTRL__SRESET__SHIFT 1 +#define WRPRSHORT_APB14_CTRL__SRESET__WIDTH 1 +#define WRPRSHORT_APB14_CTRL__SRESET__MASK 0x00000002U +#define WRPRSHORT_APB14_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRSHORT_APB14_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRSHORT_APB14_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRSHORT_APB14_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRSHORT_APB14_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRSHORT_APB14_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRSHORT_APB14_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRSHORT_APB14_CTRL__CLK_SEL__SHIFT 2 +#define WRPRSHORT_APB14_CTRL__CLK_SEL__WIDTH 1 +#define WRPRSHORT_APB14_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRSHORT_APB14_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRSHORT_APB14_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRSHORT_APB14_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRSHORT_APB14_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRSHORT_APB14_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRSHORT_APB14_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRSHORT_APB14_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRSHORT_APB14_CTRL__TYPE uint32_t +#define WRPRSHORT_APB14_CTRL__READ 0x00000007U +#define WRPRSHORT_APB14_CTRL__WRITE 0x00000007U +#define WRPRSHORT_APB14_CTRL__PRESERVED 0x00000000U +#define WRPRSHORT_APB14_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRSHORT_APB14_CTRL_MACRO__ */ + +/** @} end of apb14_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRSHORT_apb15_ctrl */ +/** + * @defgroup at_apb_wrpr_short_regs_core_apb15_ctrl apb15_ctrl + * @brief Contains register fields associated with apb15_ctrl. definitions. + * @{ + */ +#ifndef __WRPRSHORT_APB15_CTRL_MACRO__ +#define __WRPRSHORT_APB15_CTRL_MACRO__ + +/* macros for field clk_enable */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_enable_field clk_enable_field + * @brief macros for field clk_enable + * @{ + */ +#define WRPRSHORT_APB15_CTRL__CLK_ENABLE__SHIFT 0 +#define WRPRSHORT_APB15_CTRL__CLK_ENABLE__WIDTH 1 +#define WRPRSHORT_APB15_CTRL__CLK_ENABLE__MASK 0x00000001U +#define WRPRSHORT_APB15_CTRL__CLK_ENABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB15_CTRL__CLK_ENABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WRPRSHORT_APB15_CTRL__CLK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WRPRSHORT_APB15_CTRL__CLK_ENABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WRPRSHORT_APB15_CTRL__CLK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WRPRSHORT_APB15_CTRL__CLK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WRPRSHORT_APB15_CTRL__CLK_ENABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sreset */ +/** + * @defgroup at_apb_wrpr_short_regs_core_sreset_field sreset_field + * @brief macros for field sreset + * @{ + */ +#define WRPRSHORT_APB15_CTRL__SRESET__SHIFT 1 +#define WRPRSHORT_APB15_CTRL__SRESET__WIDTH 1 +#define WRPRSHORT_APB15_CTRL__SRESET__MASK 0x00000002U +#define WRPRSHORT_APB15_CTRL__SRESET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WRPRSHORT_APB15_CTRL__SRESET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WRPRSHORT_APB15_CTRL__SRESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WRPRSHORT_APB15_CTRL__SRESET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WRPRSHORT_APB15_CTRL__SRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WRPRSHORT_APB15_CTRL__SRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WRPRSHORT_APB15_CTRL__SRESET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clk_sel */ +/** + * @defgroup at_apb_wrpr_short_regs_core_clk_sel_field clk_sel_field + * @brief macros for field clk_sel + * @details [0]=PCLK [1]=PCLK_ALT + * @{ + */ +#define WRPRSHORT_APB15_CTRL__CLK_SEL__SHIFT 2 +#define WRPRSHORT_APB15_CTRL__CLK_SEL__WIDTH 1 +#define WRPRSHORT_APB15_CTRL__CLK_SEL__MASK 0x00000004U +#define WRPRSHORT_APB15_CTRL__CLK_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WRPRSHORT_APB15_CTRL__CLK_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WRPRSHORT_APB15_CTRL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WRPRSHORT_APB15_CTRL__CLK_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WRPRSHORT_APB15_CTRL__CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WRPRSHORT_APB15_CTRL__CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WRPRSHORT_APB15_CTRL__CLK_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define WRPRSHORT_APB15_CTRL__TYPE uint32_t +#define WRPRSHORT_APB15_CTRL__READ 0x00000007U +#define WRPRSHORT_APB15_CTRL__WRITE 0x00000007U +#define WRPRSHORT_APB15_CTRL__PRESERVED 0x00000000U +#define WRPRSHORT_APB15_CTRL__RESET_VALUE 0x00000002U + +#endif /* __WRPRSHORT_APB15_CTRL_MACRO__ */ + +/** @} end of apb15_ctrl */ + +/* macros for BlueprintGlobalNameSpace::WRPRSHORT_core_id */ +/** + * @defgroup at_apb_wrpr_short_regs_core_core_id core_id + * @brief Contains register fields associated with core_id. definitions. + * @{ + */ +#ifndef __WRPRSHORT_CORE_ID_MACRO__ +#define __WRPRSHORT_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_apb_wrpr_short_regs_core_id_field id_field + * @brief macros for field id + * @details WRPR in ASCII + * @{ + */ +#define WRPRSHORT_CORE_ID__ID__SHIFT 0 +#define WRPRSHORT_CORE_ID__ID__WIDTH 32 +#define WRPRSHORT_CORE_ID__ID__MASK 0xffffffffU +#define WRPRSHORT_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define WRPRSHORT_CORE_ID__ID__RESET_VALUE 0x57525052U +/** @} */ +#define WRPRSHORT_CORE_ID__TYPE uint32_t +#define WRPRSHORT_CORE_ID__READ 0xffffffffU +#define WRPRSHORT_CORE_ID__PRESERVED 0x00000000U +#define WRPRSHORT_CORE_ID__RESET_VALUE 0x57525052U + +#endif /* __WRPRSHORT_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of AT_APB_WRPR_SHORT_REGS_CORE */ +#endif /* __REG_AT_APB_WRPR_SHORT_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_clkrstgen.h b/ATM33xx-5/include/reg/at_clkrstgen.h new file mode 100644 index 0000000..f6c7a8d --- /dev/null +++ b/ATM33xx-5/include/reg/at_clkrstgen.h @@ -0,0 +1,485 @@ +/** + ****************************************************************************** + * + * @file at_clkrstgen.h + * + * @brief System clock + * + * Copyright (C) Atmosic 2020-2023 + * + ****************************************************************************** + */ + +#pragma once + +#include +#include +#include "base_addr.h" +#include "at_apb_clkrstgen_regs_core_macro.h" +#include "at_wrpr.h" +#include "at_apb_pseq_regs_core_macro.h" + +#define CLUSTER_SEL__SLOW 1 +#define CLUSTER_SEL__DOUBLER 2 +#define CLUSTER_SEL__PLL 4 +#define CLUSTER_SEL__PLL_DIV2 8 + +#ifndef __CLKRSTGEN_GET_STATIC_INLINE +#define __CLKRSTGEN_GET_STATIC_INLINE __STATIC_INLINE +#endif + +__CLKRSTGEN_GET_STATIC_INLINE uint32_t +at_clkrstgen_pll_freq(void) +{ + uint32_t pll = CMSDK_CLKRSTGEN_NONSECURE->PLL_CTRL; + if (!CLKRSTGEN_PLL_CTRL__PLL_ENABLE__READ(pll)) { + return (16000000); + } + + uint32_t pseq_pll; + WRPR_CTRL_PUSH(CMSDK_PSEQ_NONSECURE, WRPR_CTRL__CLK_ENABLE) { + pseq_pll = CMSDK_PSEQ_NONSECURE->PLL; + } WRPR_CTRL_POP(); + return ((16000000 * PSEQ_PLL__DIVFB__READ(pseq_pll)) >> + PSEQ_PLL__DIV2OUT__READ(pseq_pll)); +} + +__CLKRSTGEN_GET_STATIC_INLINE uint32_t +at_clkrstgen_slow_freq(uint32_t bp_ctrl) +{ + uint8_t slow = CLKRSTGEN_CLK_BP_CTRL__SLOW_CLUSTER_SEL__READ(bp_ctrl); + switch (slow) { + case 1: return (8000000); + case 3: return (4000000); + case 2: return (2000000); + case 6: return (1000000); + case 7: return (500000); + default: break; + } + return (16000000); +} + +__CLKRSTGEN_GET_STATIC_INLINE uint32_t +at_clkrstgen_bp_from_ctrl(void) +{ + uint32_t bp_ctrl = CMSDK_CLKRSTGEN_NONSECURE->CLK_BP_CTRL; + uint8_t cluster = CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__READ(bp_ctrl); + if (!cluster) { // clk16x + goto sixteen_mhz; + } + if (cluster & CLUSTER_SEL__SLOW) { + return (at_clkrstgen_slow_freq(bp_ctrl)); + } + if (cluster & CLUSTER_SEL__DOUBLER) { + if (!CLKRSTGEN_CLK_BP_CTRL__DOUBLER_CLUSTER_SEL__READ(bp_ctrl)) { + goto sixteen_mhz; + } + return (32000000); + } + if (cluster & CLUSTER_SEL__PLL) { + if (!CLKRSTGEN_CLK_BP_CTRL__PLL_CLUSTER_SEL__READ(bp_ctrl)) { + goto sixteen_mhz; + } + return (at_clkrstgen_pll_freq()); + } + if (cluster & CLUSTER_SEL__PLL_DIV2) { + if (!CLKRSTGEN_CLK_BP_CTRL__PLL_DIV2_CLUSTER_SEL__READ(bp_ctrl)) { + goto sixteen_mhz; + } + uint32_t freq = at_clkrstgen_pll_freq() / 2; + return ((freq == 32000000) ? 32000001 : freq); + } + +sixteen_mhz: + return (16000000); +} + +__CLKRSTGEN_GET_STATIC_INLINE uint32_t +at_clkrstgen_fpga_bp_from_ctrl(uint32_t index) +{ + uint32_t bp_ctrl = CMSDK_CLKRSTGEN_NONSECURE->CLK_BP_CTRL; + uint8_t cluster = CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__READ(bp_ctrl); + uint32_t pll_freq = (index == 5) ? 16000000 : 48000000; + if (!cluster) { // clk16x + goto sixteen_mhz; + } + if (cluster & CLUSTER_SEL__SLOW) { + return (at_clkrstgen_slow_freq(bp_ctrl)); + } + if (cluster & CLUSTER_SEL__DOUBLER) { + if (!CLKRSTGEN_CLK_BP_CTRL__DOUBLER_CLUSTER_SEL__READ(bp_ctrl)) { + goto sixteen_mhz; + } + return (32000000); + } + if (cluster & CLUSTER_SEL__PLL) { + if (!CLKRSTGEN_CLK_BP_CTRL__PLL_CLUSTER_SEL__READ(bp_ctrl)) { + goto sixteen_mhz; + } + return (pll_freq); + } + if (cluster & CLUSTER_SEL__PLL_DIV2) { + if (!CLKRSTGEN_CLK_BP_CTRL__PLL_DIV2_CLUSTER_SEL__READ(bp_ctrl)) { + goto sixteen_mhz; + } + return (pll_freq / 2); + } + +sixteen_mhz: + return (16000000); +} + +__CLKRSTGEN_GET_STATIC_INLINE uint32_t +at_clkrstgen_get_bp(void) +{ + uint32_t config = CMSDK_CLKRSTGEN_NONSECURE->CONFIGURATION; + uint32_t index = CLKRSTGEN_CONFIGURATION__INDEX__READ(config); + switch (index) { + case 0: return (at_clkrstgen_bp_from_ctrl()); + case 1: + case 3: + case 5: return (at_clkrstgen_fpga_bp_from_ctrl(index)); + default: break; + } + return (16000000); +} + +#ifndef __CLKRSTGEN_SET_STATIC_INLINE +#define __CLKRSTGEN_SET_STATIC_INLINE __STATIC_INLINE +#endif + +__CLKRSTGEN_SET_STATIC_INLINE void +at_clkrstgen_set_clk16x(bool commit) +{ + if (!commit) { + return; + } + + // Sequence designed to avoid BP glitches and dropouts + CMSDK_CLKRSTGEN_NONSECURE->CLK_BP_CTRL &= + CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__MASK; + while (CMSDK_CLKRSTGEN_NONSECURE->CLK_BP_CTRL_STAT & + ~CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__MASK) { + __ASM volatile ("yield"); + } + CMSDK_CLKRSTGEN_NONSECURE->CLK_BP_CTRL = 0; +} + +__CLKRSTGEN_SET_STATIC_INLINE void +at_clkrstgen_set_slow(uint8_t sel, bool set, bool commit) +{ + if (set) { + // Get off SLOW before changing it + at_clkrstgen_set_clk16x(CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__READ( + CMSDK_CLKRSTGEN_NONSECURE->CLK_BP_CTRL) & CLUSTER_SEL__SLOW); + + CLKRSTGEN_CLK_BP_CTRL__SLOW_CLUSTER_SEL__MODIFY( + CMSDK_CLKRSTGEN_NONSECURE->CLK_BP_CTRL, sel); + } + if (!commit) { + return; + } + + // To prevent multiple bit transitions, take everything back to zero + at_clkrstgen_set_clk16x(CMSDK_CLKRSTGEN_NONSECURE->CLK_BP_CTRL_STAT); + + CMSDK_CLKRSTGEN_NONSECURE->CLK_BP_CTRL = + CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__WRITE(CLUSTER_SEL__SLOW) | + CLKRSTGEN_CLK_BP_CTRL__SLOW_CLUSTER_SEL__WRITE(sel); +} + +__CLKRSTGEN_SET_STATIC_INLINE uint32_t +at_clkrstgen_get_lpc(void) +{ + uint32_t rt = CMSDK_PSEQ_NONSECURE->CURRENT_REAL_TIME; + for (;;) { + uint32_t rt1 = CMSDK_PSEQ_NONSECURE->CURRENT_REAL_TIME; + if (rt == rt1) { + break; + } + rt = rt1; + } + + return (rt); +} + +__CLKRSTGEN_SET_STATIC_INLINE void +at_clkrstgen_set_doubler(bool set, bool commit) +{ + if (CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__READ( + CMSDK_CLKRSTGEN_NONSECURE->CLK_BP_CTRL) & CLUSTER_SEL__DOUBLER) { + // Already running off doubler + return; + } + + if (set) { + WRPR_CTRL_PUSH(CMSDK_PSEQ_NONSECURE, WRPR_CTRL__CLK_ENABLE) { + // Make sure xtal is stable + while (!PSEQ_RADIO_STATUS__XTAL_STABLE__READ( + CMSDK_PSEQ_NONSECURE->RADIO_STATUS)) { + __ASM volatile ("yield"); + } + + // Enable HPC + PSEQ_XTAL_BITS1__CLKHPC_EN__SET(CMSDK_PSEQ_NONSECURE->XTAL_BITS1); + + // Stash HPC_EN time for split set/commit invocations + CMSDK_WRPR0_NONSECURE->SCRATCHPAD_A = at_clkrstgen_get_lpc(); + } WRPR_CTRL_POP(); + } + if (!commit) { + return; + } + + // To prevent multiple bit transitions, take everything back to zero + at_clkrstgen_set_clk16x(CMSDK_CLKRSTGEN_NONSECURE->CLK_BP_CTRL_STAT); + + WRPR_CTRL_PUSH(CMSDK_PSEQ_NONSECURE, WRPR_CTRL__CLK_ENABLE) { + uint32_t then = CMSDK_WRPR0_NONSECURE->SCRATCHPAD_A; + while (at_clkrstgen_get_lpc() - then < 2) { + __ASM volatile ("yield"); + } + } WRPR_CTRL_POP(); + + // Then select doubler + CMSDK_CLKRSTGEN_NONSECURE->CLK_BP_CTRL = + CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__WRITE(CLUSTER_SEL__DOUBLER) | + CLKRSTGEN_CLK_BP_CTRL__DOUBLER_CLUSTER_SEL__MASK; +} + +__CLKRSTGEN_SET_STATIC_INLINE void +at_clkrstgen_enable_pll(uint8_t sel, bool div2, bool set, bool commit) +{ + if (set) { + // Get off PLL before changing it + at_clkrstgen_set_clk16x(CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__READ( + CMSDK_CLKRSTGEN_NONSECURE->CLK_BP_CTRL) & (CLUSTER_SEL__PLL | + CLUSTER_SEL__PLL_DIV2)); + + if (CMSDK_CLKRSTGEN_NONSECURE->CLKSYNC) { + CLKRSTGEN_CLKSYNC__CLK16_SRC__MODIFY( + CMSDK_CLKRSTGEN_NONSECURE->CLKSYNC, 0); + CMSDK_CLKRSTGEN_NONSECURE->PLL_CTRL = 0; + CMSDK_CLKRSTGEN_NONSECURE->CLKSYNC = 0; + } + + WRPR_CTRL_PUSH(CMSDK_PSEQ_NONSECURE, WRPR_CTRL__CLK_ENABLE) { + // Make sure xtal is stable + while (!PSEQ_RADIO_STATUS__XTAL_STABLE__READ( + CMSDK_PSEQ_NONSECURE->RADIO_STATUS)) { + __ASM volatile ("yield"); + } + + // Configure PLL + uint32_t pll = CMSDK_PSEQ_NONSECURE->PLL; + PSEQ_PLL__DIVACCESS__SET(pll); + PSEQ_PLL__DIVREF__MODIFY(pll, 1); + PSEQ_PLL__DIVFB__MODIFY(pll, sel); + PSEQ_PLL__DIVOUT__MODIFY(pll, 1); + PSEQ_PLL__DIV2OUT__MODIFY(pll, div2 ? 1 : 0); + CMSDK_PSEQ_NONSECURE->PLL = pll; + } WRPR_CTRL_POP(); + + // Enable PLL + CMSDK_CLKRSTGEN_NONSECURE->PLL_CTRL = + CLKRSTGEN_PLL_CTRL__PLL_ENABLE__MASK; + } + if (!commit) { + return; + } + + while (!CLKRSTGEN_CONFIGURATION__PLL_READY__READ( + CMSDK_CLKRSTGEN_NONSECURE->CONFIGURATION)) { + __ASM volatile ("yield"); + } + + CMSDK_CLKRSTGEN_NONSECURE->CLKSYNC = + CLKRSTGEN_CLKSYNC__DIV_VAL__WRITE(sel >> (div2 ? 1 : 0)) | + CLKRSTGEN_CLKSYNC__CLK16_SRC__MASK; +} + +#ifdef UNSUPPORTED_64_DIV_2 +__CLKRSTGEN_SET_STATIC_INLINE void +at_clkrstgen_set_pll_div2(uint8_t sel, bool set, bool commit) +{ + at_clkrstgen_enable_pll(sel, false, set, commit); + if (!commit) { + return; + } + + // To prevent multiple bit transitions, take everything back to zero + at_clkrstgen_set_clk16x(CMSDK_CLKRSTGEN_NONSECURE->CLK_BP_CTRL_STAT); + + // Then select PLL/2 + CMSDK_CLKRSTGEN_NONSECURE->CLK_BP_CTRL = + CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__WRITE(CLUSTER_SEL__PLL_DIV2) | + CLKRSTGEN_CLK_BP_CTRL__PLL_DIV2_CLUSTER_SEL__MASK; +} +#endif + +__CLKRSTGEN_SET_STATIC_INLINE void +at_clkrstgen_set_pll(uint8_t sel, bool set, bool commit) +{ + at_clkrstgen_enable_pll(sel, false, set, commit); + if (!commit) { + return; + } + + // To prevent multiple bit transitions, take everything back to zero + at_clkrstgen_set_clk16x(CMSDK_CLKRSTGEN_NONSECURE->CLK_BP_CTRL_STAT); + + // Then select PLL + CMSDK_CLKRSTGEN_NONSECURE->CLK_BP_CTRL = + CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__WRITE(CLUSTER_SEL__PLL) | + CLKRSTGEN_CLK_BP_CTRL__PLL_CLUSTER_SEL__MASK; +} + +__CLKRSTGEN_SET_STATIC_INLINE void +at_clkrstgen_set_div2_pll(uint8_t sel, bool set, bool commit) +{ + at_clkrstgen_enable_pll(sel, true, set, commit); + if (!commit) { + return; + } + + // To prevent multiple bit transitions, take everything back to zero + at_clkrstgen_set_clk16x(CMSDK_CLKRSTGEN_NONSECURE->CLK_BP_CTRL_STAT); + + // Then select PLL + CMSDK_CLKRSTGEN_NONSECURE->CLK_BP_CTRL = + CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__WRITE(CLUSTER_SEL__PLL) | + CLKRSTGEN_CLK_BP_CTRL__PLL_CLUSTER_SEL__MASK; +} + +__CLKRSTGEN_SET_STATIC_INLINE void +at_clkrstgen_asic_set_bp_hint(uint32_t freq, bool set, bool commit) +{ +#ifdef __ICCARM__ + if (freq <= 500000) { + at_clkrstgen_set_slow(7, set, commit); + } else if (freq <= 1000000) { + at_clkrstgen_set_slow(6, set, commit); + } else if (freq <= 2000000) { + at_clkrstgen_set_slow(2, set, commit); + } else if (freq <= 4000000) { + at_clkrstgen_set_slow(3, set, commit); + } else if (freq <= 8000000) { + at_clkrstgen_set_slow(1, set, commit); + } else if (freq <= 16000000) { + at_clkrstgen_set_clk16x(commit); + } else if (freq <= 32000000) { + at_clkrstgen_set_div2_pll(4, set, commit); +#ifdef UNSUPPORTED_64_DIV_2 + } else if (freq == 32000001) { + at_clkrstgen_set_pll_div2(4, set, commit); +#endif + } else if (freq <= 48000000) { + at_clkrstgen_set_pll(3, set, commit); + } else /* 64MHz */ { + at_clkrstgen_set_pll(4, set, commit); + } +#else // __ICCARM__ + switch (freq) { + case 0 ... 500000: at_clkrstgen_set_slow(7, set, commit); break; + case 500001 ... 1000000: at_clkrstgen_set_slow(6, set, commit); break; + case 1000001 ... 2000000: at_clkrstgen_set_slow(2, set, commit); break; + case 2000001 ... 4000000: at_clkrstgen_set_slow(3, set, commit); break; + case 4000001 ... 8000000: at_clkrstgen_set_slow(1, set, commit); break; + case 8000001 ... 16000000: at_clkrstgen_set_clk16x(commit); break; + case 16000001 ... 32000000: at_clkrstgen_set_div2_pll(4, set, commit); break; + case 32000001: +#ifdef UNSUPPORTED_64_DIV_2 + at_clkrstgen_set_pll_div2(4, set, commit); break; +#endif + case 32000002 ... 48000000: at_clkrstgen_set_pll(3, set, commit); break; + default: /* 64MHz */ at_clkrstgen_set_pll(4, set, commit); break; + } +#endif // __ICCARM__ + + if (!commit) { + return; + } + + uint32_t clk_bp_ctrl = CMSDK_CLKRSTGEN_NONSECURE->CLK_BP_CTRL; + + // Disable PLL when not needed + if (!(CLKRSTGEN_CLK_BP_CTRL__CLUSTER_SEL__READ(clk_bp_ctrl) & + (CLUSTER_SEL__PLL | CLUSTER_SEL__PLL_DIV2))) { + CLKRSTGEN_CLKSYNC__CLK16_SRC__MODIFY( + CMSDK_CLKRSTGEN_NONSECURE->CLKSYNC, 0); + CMSDK_CLKRSTGEN_NONSECURE->PLL_CTRL = 0; + CMSDK_CLKRSTGEN_NONSECURE->CLKSYNC = 0; + } + + // Disable HPC when not needed + if (!CLKRSTGEN_CLK_BP_CTRL__DOUBLER_CLUSTER_SEL__READ(clk_bp_ctrl)) { + WRPR_CTRL_PUSH(CMSDK_PSEQ_NONSECURE, WRPR_CTRL__CLK_ENABLE) { + PSEQ_XTAL_BITS1__CLKHPC_EN__CLR(CMSDK_PSEQ_NONSECURE->XTAL_BITS1); + } WRPR_CTRL_POP(); + } +} + +__CLKRSTGEN_SET_STATIC_INLINE void +at_clkrstgen_fpga_set_bp(uint32_t index, uint32_t freq, bool set, bool commit) +{ +#ifdef __ICCARM__ + if (freq <= 500000) { + at_clkrstgen_set_slow(7, set, commit); + } else if (freq <= 1000000) { + at_clkrstgen_set_slow(6, set, commit); + } else if (freq <= 2000000) { + at_clkrstgen_set_slow(2, set, commit); + } else if (freq <= 4000000) { + at_clkrstgen_set_slow(3, set, commit); + } else if (freq <= 8000000) { + at_clkrstgen_set_slow(1, set, commit); + } else if (freq <= 16000000) { + at_clkrstgen_set_clk16x(commit); + } else if (freq <= 32000000) { + at_clkrstgen_set_doubler(set, commit); + } else /* 48MHz */ { + if (index != 5) { + at_clkrstgen_set_pll(0, set, commit); + } else { + at_clkrstgen_set_doubler(set, commit); + } + } +#else + switch (freq) { + case 0 ... 500000: at_clkrstgen_set_slow(7, set, commit); break; + case 500001 ... 1000000: at_clkrstgen_set_slow(6, set, commit); break; + case 1000001 ... 2000000: at_clkrstgen_set_slow(2, set, commit); break; + case 2000001 ... 4000000: at_clkrstgen_set_slow(3, set, commit); break; + case 4000001 ... 8000000: at_clkrstgen_set_slow(1, set, commit); break; + case 8000001 ... 16000000: at_clkrstgen_set_clk16x(commit); break; + default: /* 48MHz */ + if (index != 5) { + at_clkrstgen_set_pll(0, set, commit); + break; + } + // Fall through + case 16000001 ... 32000000: + at_clkrstgen_set_doubler(set, commit); break; + } +#endif +} + +__CLKRSTGEN_SET_STATIC_INLINE void +at_clkrstgen_set_bp_hint(uint32_t freq, bool set, bool commit) +{ + uint32_t config = CMSDK_CLKRSTGEN_NONSECURE->CONFIGURATION; + uint32_t index = CLKRSTGEN_CONFIGURATION__INDEX__READ(config); + switch (index) { + case 0: at_clkrstgen_asic_set_bp_hint(freq, set, commit); break; + case 1: + case 3: + case 5: at_clkrstgen_fpga_set_bp(index, freq, set, commit); break; + default: break; + } +} + +__CLKRSTGEN_SET_STATIC_INLINE void +at_clkrstgen_set_bp(uint32_t freq) +{ + at_clkrstgen_set_bp_hint(freq, true, true); +} diff --git a/ATM33xx-5/include/reg/at_i2s_regs_core_macro.h b/ATM33xx-5/include/reg/at_i2s_regs_core_macro.h new file mode 100644 index 0000000..495c5de --- /dev/null +++ b/ATM33xx-5/include/reg/at_i2s_regs_core_macro.h @@ -0,0 +1,5591 @@ +/* */ +/* File: at_i2s_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_i2s_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_I2S_REGS_CORE_H__ +#define __REG_AT_I2S_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_I2S_REGS_CORE at_i2s_regs_core + * @ingroup AT_REG + * @brief at_i2s_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_ctrl0 */ +/** + * @defgroup at_i2s_regs_core_i2s_ctrl0 i2s_ctrl0 + * @brief Contains register fields associated with i2s_ctrl0. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_CTRL0_MACRO__ +#define __ATI2S_I2S_CTRL0_MACRO__ + +/* macros for field sck_nedge_ws_rx */ +/** + * @defgroup at_i2s_regs_core_sck_nedge_ws_rx_field sck_nedge_ws_rx_field + * @brief macros for field sck_nedge_ws_rx + * @details 1 = drive/latch rx ws on negative edge of sck, 0 = drive/latch rx ws on positive edge of sck + * @{ + */ +#define ATI2S_I2S_CTRL0__SCK_NEDGE_WS_RX__SHIFT 0 +#define ATI2S_I2S_CTRL0__SCK_NEDGE_WS_RX__WIDTH 1 +#define ATI2S_I2S_CTRL0__SCK_NEDGE_WS_RX__MASK 0x00000001U +#define ATI2S_I2S_CTRL0__SCK_NEDGE_WS_RX__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_WS_RX__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_WS_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_WS_RX__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_WS_RX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_WS_RX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_WS_RX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sck_nedge_ws_tx */ +/** + * @defgroup at_i2s_regs_core_sck_nedge_ws_tx_field sck_nedge_ws_tx_field + * @brief macros for field sck_nedge_ws_tx + * @details 1 = drive/latch tx ws on negative edge of sck, 0 = drive/latch tx ws on positive edge of sck + * @{ + */ +#define ATI2S_I2S_CTRL0__SCK_NEDGE_WS_TX__SHIFT 1 +#define ATI2S_I2S_CTRL0__SCK_NEDGE_WS_TX__WIDTH 1 +#define ATI2S_I2S_CTRL0__SCK_NEDGE_WS_TX__MASK 0x00000002U +#define ATI2S_I2S_CTRL0__SCK_NEDGE_WS_TX__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_WS_TX__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_WS_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_WS_TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_WS_TX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_WS_TX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_WS_TX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field src_snk_en */ +/** + * @defgroup at_i2s_regs_core_src_snk_en_field src_snk_en_field + * @brief macros for field src_snk_en + * @details Enable tranceiver tx or rx or both After it's enabled, first data valid assertion initiates tx and first ws deassertion initiates rx 0 = i2s disabled 1 = source serial data 2 = sink serial data 3 = source serial data and sink serial data + * @{ + */ +#define ATI2S_I2S_CTRL0__SRC_SNK_EN__SHIFT 2 +#define ATI2S_I2S_CTRL0__SRC_SNK_EN__WIDTH 2 +#define ATI2S_I2S_CTRL0__SRC_SNK_EN__MASK 0x0000000cU +#define ATI2S_I2S_CTRL0__SRC_SNK_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x0000000cU) >> 2) +#define ATI2S_I2S_CTRL0__SRC_SNK_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000000cU) +#define ATI2S_I2S_CTRL0__SRC_SNK_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((uint32_t)(src) <<\ + 2) & 0x0000000cU) +#define ATI2S_I2S_CTRL0__SRC_SNK_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000000cU))) +#define ATI2S_I2S_CTRL0__SRC_SNK_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field src_snk */ +/** + * @defgroup at_i2s_regs_core_src_snk_field src_snk_field + * @brief macros for field src_snk + * @details 0 = pcm (pdm2pcm processed data is transmitted), 1 = ahb (data in memory 0 is transmitted or data is received and stored in memory 0), 2 = ahb (data in memory 1 is transmitted or data is received and stored in memory 1) this is mainly used for rx to tx loop back simulation and eimulation + * @{ + */ +#define ATI2S_I2S_CTRL0__SRC_SNK__SHIFT 4 +#define ATI2S_I2S_CTRL0__SRC_SNK__WIDTH 2 +#define ATI2S_I2S_CTRL0__SRC_SNK__MASK 0x00000030U +#define ATI2S_I2S_CTRL0__SRC_SNK__READ(src) \ + (((uint32_t)(src)\ + & 0x00000030U) >> 4) +#define ATI2S_I2S_CTRL0__SRC_SNK__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000030U) +#define ATI2S_I2S_CTRL0__SRC_SNK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((uint32_t)(src) <<\ + 4) & 0x00000030U) +#define ATI2S_I2S_CTRL0__SRC_SNK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000030U))) +#define ATI2S_I2S_CTRL0__SRC_SNK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mstr_sckws_rx */ +/** + * @defgroup at_i2s_regs_core_mstr_sckws_rx_field mstr_sckws_rx_field + * @brief macros for field mstr_sckws_rx + * @details 0 = slave sck and ws, 1 = master sck and ws + * @{ + */ +#define ATI2S_I2S_CTRL0__MSTR_SCKWS_RX__SHIFT 6 +#define ATI2S_I2S_CTRL0__MSTR_SCKWS_RX__WIDTH 1 +#define ATI2S_I2S_CTRL0__MSTR_SCKWS_RX__MASK 0x00000040U +#define ATI2S_I2S_CTRL0__MSTR_SCKWS_RX__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define ATI2S_I2S_CTRL0__MSTR_SCKWS_RX__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define ATI2S_I2S_CTRL0__MSTR_SCKWS_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define ATI2S_I2S_CTRL0__MSTR_SCKWS_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define ATI2S_I2S_CTRL0__MSTR_SCKWS_RX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define ATI2S_I2S_CTRL0__MSTR_SCKWS_RX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define ATI2S_I2S_CTRL0__MSTR_SCKWS_RX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mstr_sckws_tx */ +/** + * @defgroup at_i2s_regs_core_mstr_sckws_tx_field mstr_sckws_tx_field + * @brief macros for field mstr_sckws_tx + * @details 0 = slave sck and ws, 1 = master sck and ws + * @{ + */ +#define ATI2S_I2S_CTRL0__MSTR_SCKWS_TX__SHIFT 7 +#define ATI2S_I2S_CTRL0__MSTR_SCKWS_TX__WIDTH 1 +#define ATI2S_I2S_CTRL0__MSTR_SCKWS_TX__MASK 0x00000080U +#define ATI2S_I2S_CTRL0__MSTR_SCKWS_TX__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define ATI2S_I2S_CTRL0__MSTR_SCKWS_TX__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define ATI2S_I2S_CTRL0__MSTR_SCKWS_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define ATI2S_I2S_CTRL0__MSTR_SCKWS_TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define ATI2S_I2S_CTRL0__MSTR_SCKWS_TX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define ATI2S_I2S_CTRL0__MSTR_SCKWS_TX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define ATI2S_I2S_CTRL0__MSTR_SCKWS_TX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field src_cnt */ +/** + * @defgroup at_i2s_regs_core_src_cnt_field src_cnt_field + * @brief macros for field src_cnt + * @details number of sources for i2s + * @{ + */ +#define ATI2S_I2S_CTRL0__SRC_CNT__SHIFT 8 +#define ATI2S_I2S_CTRL0__SRC_CNT__WIDTH 3 +#define ATI2S_I2S_CTRL0__SRC_CNT__MASK 0x00000700U +#define ATI2S_I2S_CTRL0__SRC_CNT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000700U) >> 8) +#define ATI2S_I2S_CTRL0__SRC_CNT__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000700U) +#define ATI2S_I2S_CTRL0__SRC_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((uint32_t)(src) <<\ + 8) & 0x00000700U) +#define ATI2S_I2S_CTRL0__SRC_CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000700U))) +#define ATI2S_I2S_CTRL0__SRC_CNT__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field snk_cnt */ +/** + * @defgroup at_i2s_regs_core_snk_cnt_field snk_cnt_field + * @brief macros for field snk_cnt + * @details number of sinks for i2s + * @{ + */ +#define ATI2S_I2S_CTRL0__SNK_CNT__SHIFT 11 +#define ATI2S_I2S_CTRL0__SNK_CNT__WIDTH 3 +#define ATI2S_I2S_CTRL0__SNK_CNT__MASK 0x00003800U +#define ATI2S_I2S_CTRL0__SNK_CNT__READ(src) \ + (((uint32_t)(src)\ + & 0x00003800U) >> 11) +#define ATI2S_I2S_CTRL0__SNK_CNT__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00003800U) +#define ATI2S_I2S_CTRL0__SNK_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((uint32_t)(src) <<\ + 11) & 0x00003800U) +#define ATI2S_I2S_CTRL0__SNK_CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00003800U))) +#define ATI2S_I2S_CTRL0__SNK_CNT__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field sck_init_cnt */ +/** + * @defgroup at_i2s_regs_core_sck_init_cnt_field sck_init_cnt_field + * @brief macros for field sck_init_cnt + * @details initial number of sck before going to transmit or receive state + * @{ + */ +#define ATI2S_I2S_CTRL0__SCK_INIT_CNT__SHIFT 16 +#define ATI2S_I2S_CTRL0__SCK_INIT_CNT__WIDTH 8 +#define ATI2S_I2S_CTRL0__SCK_INIT_CNT__MASK 0x00ff0000U +#define ATI2S_I2S_CTRL0__SCK_INIT_CNT__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define ATI2S_I2S_CTRL0__SCK_INIT_CNT__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define ATI2S_I2S_CTRL0__SCK_INIT_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define ATI2S_I2S_CTRL0__SCK_INIT_CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define ATI2S_I2S_CTRL0__SCK_INIT_CNT__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field dma_en */ +/** + * @defgroup at_i2s_regs_core_dma_en_field dma_en_field + * @brief macros for field dma_en + * @details dma is enabled to access ping pong buffer + * @{ + */ +#define ATI2S_I2S_CTRL0__DMA_EN__SHIFT 24 +#define ATI2S_I2S_CTRL0__DMA_EN__WIDTH 1 +#define ATI2S_I2S_CTRL0__DMA_EN__MASK 0x01000000U +#define ATI2S_I2S_CTRL0__DMA_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define ATI2S_I2S_CTRL0__DMA_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define ATI2S_I2S_CTRL0__DMA_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define ATI2S_I2S_CTRL0__DMA_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define ATI2S_I2S_CTRL0__DMA_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define ATI2S_I2S_CTRL0__DMA_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define ATI2S_I2S_CTRL0__DMA_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ws_init_rx */ +/** + * @defgroup at_i2s_regs_core_ws_init_rx_field ws_init_rx_field + * @brief macros for field ws_init_rx + * @details 0 = word select is deasserted at the starting half of justieid mode 1 = word select is asserted at the starting half of justieid mode this applies to right or left justified mode, ws_init should be set to 1 for PCM mode + * @{ + */ +#define ATI2S_I2S_CTRL0__WS_INIT_RX__SHIFT 25 +#define ATI2S_I2S_CTRL0__WS_INIT_RX__WIDTH 1 +#define ATI2S_I2S_CTRL0__WS_INIT_RX__MASK 0x02000000U +#define ATI2S_I2S_CTRL0__WS_INIT_RX__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define ATI2S_I2S_CTRL0__WS_INIT_RX__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define ATI2S_I2S_CTRL0__WS_INIT_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define ATI2S_I2S_CTRL0__WS_INIT_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define ATI2S_I2S_CTRL0__WS_INIT_RX__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define ATI2S_I2S_CTRL0__WS_INIT_RX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define ATI2S_I2S_CTRL0__WS_INIT_RX__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ws_init_tx */ +/** + * @defgroup at_i2s_regs_core_ws_init_tx_field ws_init_tx_field + * @brief macros for field ws_init_tx + * @details 0 = word select is deasserted at the starting half of justieid mode 1 = word select is asserted at the starting half of justieid mode this applies to right or left justified mode, ws_init should be set to 1 for PCM mode + * @{ + */ +#define ATI2S_I2S_CTRL0__WS_INIT_TX__SHIFT 26 +#define ATI2S_I2S_CTRL0__WS_INIT_TX__WIDTH 1 +#define ATI2S_I2S_CTRL0__WS_INIT_TX__MASK 0x04000000U +#define ATI2S_I2S_CTRL0__WS_INIT_TX__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define ATI2S_I2S_CTRL0__WS_INIT_TX__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define ATI2S_I2S_CTRL0__WS_INIT_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define ATI2S_I2S_CTRL0__WS_INIT_TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define ATI2S_I2S_CTRL0__WS_INIT_TX__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define ATI2S_I2S_CTRL0__WS_INIT_TX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define ATI2S_I2S_CTRL0__WS_INIT_TX__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field sck_nedge_sd_rx */ +/** + * @defgroup at_i2s_regs_core_sck_nedge_sd_rx_field sck_nedge_sd_rx_field + * @brief macros for field sck_nedge_sd_rx + * @details 1 = drive/latch rx sd on negative edge of sck, 0 = drive/latch rx sd on positive edge of sck + * @{ + */ +#define ATI2S_I2S_CTRL0__SCK_NEDGE_SD_RX__SHIFT 27 +#define ATI2S_I2S_CTRL0__SCK_NEDGE_SD_RX__WIDTH 1 +#define ATI2S_I2S_CTRL0__SCK_NEDGE_SD_RX__MASK 0x08000000U +#define ATI2S_I2S_CTRL0__SCK_NEDGE_SD_RX__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_SD_RX__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_SD_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_SD_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_SD_RX__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_SD_RX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_SD_RX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sck_nedge_sd_tx */ +/** + * @defgroup at_i2s_regs_core_sck_nedge_sd_tx_field sck_nedge_sd_tx_field + * @brief macros for field sck_nedge_sd_tx + * @details 1 = drive/latch tx sd on negative edge of sck, 0 = drive/latch tx sd on positive edge of sck + * @{ + */ +#define ATI2S_I2S_CTRL0__SCK_NEDGE_SD_TX__SHIFT 28 +#define ATI2S_I2S_CTRL0__SCK_NEDGE_SD_TX__WIDTH 1 +#define ATI2S_I2S_CTRL0__SCK_NEDGE_SD_TX__MASK 0x10000000U +#define ATI2S_I2S_CTRL0__SCK_NEDGE_SD_TX__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_SD_TX__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_SD_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_SD_TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_SD_TX__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_SD_TX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define ATI2S_I2S_CTRL0__SCK_NEDGE_SD_TX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ws_nedge_st_rx */ +/** + * @defgroup at_i2s_regs_core_ws_nedge_st_rx_field ws_nedge_st_rx_field + * @brief macros for field ws_nedge_st_rx + * @details 1 = rx starts on negative edge of ws + * @{ + */ +#define ATI2S_I2S_CTRL0__WS_NEDGE_ST_RX__SHIFT 29 +#define ATI2S_I2S_CTRL0__WS_NEDGE_ST_RX__WIDTH 1 +#define ATI2S_I2S_CTRL0__WS_NEDGE_ST_RX__MASK 0x20000000U +#define ATI2S_I2S_CTRL0__WS_NEDGE_ST_RX__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define ATI2S_I2S_CTRL0__WS_NEDGE_ST_RX__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define ATI2S_I2S_CTRL0__WS_NEDGE_ST_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define ATI2S_I2S_CTRL0__WS_NEDGE_ST_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define ATI2S_I2S_CTRL0__WS_NEDGE_ST_RX__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define ATI2S_I2S_CTRL0__WS_NEDGE_ST_RX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define ATI2S_I2S_CTRL0__WS_NEDGE_ST_RX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ws_nedge_st_tx */ +/** + * @defgroup at_i2s_regs_core_ws_nedge_st_tx_field ws_nedge_st_tx_field + * @brief macros for field ws_nedge_st_tx + * @details 1 = tx starts on negative edge of ws + * @{ + */ +#define ATI2S_I2S_CTRL0__WS_NEDGE_ST_TX__SHIFT 30 +#define ATI2S_I2S_CTRL0__WS_NEDGE_ST_TX__WIDTH 1 +#define ATI2S_I2S_CTRL0__WS_NEDGE_ST_TX__MASK 0x40000000U +#define ATI2S_I2S_CTRL0__WS_NEDGE_ST_TX__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define ATI2S_I2S_CTRL0__WS_NEDGE_ST_TX__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define ATI2S_I2S_CTRL0__WS_NEDGE_ST_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define ATI2S_I2S_CTRL0__WS_NEDGE_ST_TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define ATI2S_I2S_CTRL0__WS_NEDGE_ST_TX__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define ATI2S_I2S_CTRL0__WS_NEDGE_ST_TX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define ATI2S_I2S_CTRL0__WS_NEDGE_ST_TX__RESET_VALUE 0x00000000U +/** @} */ +#define ATI2S_I2S_CTRL0__TYPE uint32_t +#define ATI2S_I2S_CTRL0__READ 0x7fff3fffU +#define ATI2S_I2S_CTRL0__WRITE 0x7fff3fffU +#define ATI2S_I2S_CTRL0__PRESERVED 0x00000000U +#define ATI2S_I2S_CTRL0__RESET_VALUE 0x06100900U + +#endif /* __ATI2S_I2S_CTRL0_MACRO__ */ + +/** @} end of i2s_ctrl0 */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_ctrl1_tx */ +/** + * @defgroup at_i2s_regs_core_i2s_ctrl1_tx i2s_ctrl1_tx + * @brief Contains register fields associated with i2s_ctrl1_tx. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_CTRL1_TX_MACRO__ +#define __ATI2S_I2S_CTRL1_TX_MACRO__ + +/* macros for field ck2sck_rt */ +/** + * @defgroup at_i2s_regs_core_ck2sck_rt_field ck2sck_rt_field + * @brief macros for field ck2sck_rt + * @details clock to serial clock ratio - number of clocks per serial clock period + * @{ + */ +#define ATI2S_I2S_CTRL1_TX__CK2SCK_RT__SHIFT 0 +#define ATI2S_I2S_CTRL1_TX__CK2SCK_RT__WIDTH 16 +#define ATI2S_I2S_CTRL1_TX__CK2SCK_RT__MASK 0x0000ffffU +#define ATI2S_I2S_CTRL1_TX__CK2SCK_RT__READ(src) \ + ((uint32_t)(src)\ + & 0x0000ffffU) +#define ATI2S_I2S_CTRL1_TX__CK2SCK_RT__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000ffffU) +#define ATI2S_I2S_CTRL1_TX__CK2SCK_RT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATI2S_I2S_CTRL1_TX__CK2SCK_RT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000ffffU))) +#define ATI2S_I2S_CTRL1_TX__CK2SCK_RT__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field sck2ws_rt */ +/** + * @defgroup at_i2s_regs_core_sck2ws_rt_field sck2ws_rt_field + * @brief macros for field sck2ws_rt + * @details serial clock to word select ratio - number of serial clock per word select period + * @{ + */ +#define ATI2S_I2S_CTRL1_TX__SCK2WS_RT__SHIFT 16 +#define ATI2S_I2S_CTRL1_TX__SCK2WS_RT__WIDTH 16 +#define ATI2S_I2S_CTRL1_TX__SCK2WS_RT__MASK 0xffff0000U +#define ATI2S_I2S_CTRL1_TX__SCK2WS_RT__READ(src) \ + (((uint32_t)(src)\ + & 0xffff0000U) >> 16) +#define ATI2S_I2S_CTRL1_TX__SCK2WS_RT__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0xffff0000U) +#define ATI2S_I2S_CTRL1_TX__SCK2WS_RT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define ATI2S_I2S_CTRL1_TX__SCK2WS_RT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define ATI2S_I2S_CTRL1_TX__SCK2WS_RT__RESET_VALUE 0x00000020U +/** @} */ +#define ATI2S_I2S_CTRL1_TX__TYPE uint32_t +#define ATI2S_I2S_CTRL1_TX__READ 0xffffffffU +#define ATI2S_I2S_CTRL1_TX__WRITE 0xffffffffU +#define ATI2S_I2S_CTRL1_TX__PRESERVED 0x00000000U +#define ATI2S_I2S_CTRL1_TX__RESET_VALUE 0x00200010U + +#endif /* __ATI2S_I2S_CTRL1_TX_MACRO__ */ + +/** @} end of i2s_ctrl1_tx */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_ctrl1_rx */ +/** + * @defgroup at_i2s_regs_core_i2s_ctrl1_rx i2s_ctrl1_rx + * @brief Contains register fields associated with i2s_ctrl1_rx. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_CTRL1_RX_MACRO__ +#define __ATI2S_I2S_CTRL1_RX_MACRO__ + +/* macros for field ck2sck_rt */ +/** + * @defgroup at_i2s_regs_core_ck2sck_rt_field ck2sck_rt_field + * @brief macros for field ck2sck_rt + * @details clock to serial clock ratio - number of clocks per serial clock period + * @{ + */ +#define ATI2S_I2S_CTRL1_RX__CK2SCK_RT__SHIFT 0 +#define ATI2S_I2S_CTRL1_RX__CK2SCK_RT__WIDTH 16 +#define ATI2S_I2S_CTRL1_RX__CK2SCK_RT__MASK 0x0000ffffU +#define ATI2S_I2S_CTRL1_RX__CK2SCK_RT__READ(src) \ + ((uint32_t)(src)\ + & 0x0000ffffU) +#define ATI2S_I2S_CTRL1_RX__CK2SCK_RT__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000ffffU) +#define ATI2S_I2S_CTRL1_RX__CK2SCK_RT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATI2S_I2S_CTRL1_RX__CK2SCK_RT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000ffffU))) +#define ATI2S_I2S_CTRL1_RX__CK2SCK_RT__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field sck2ws_rt */ +/** + * @defgroup at_i2s_regs_core_sck2ws_rt_field sck2ws_rt_field + * @brief macros for field sck2ws_rt + * @details serial clock to word select ratio - number of serial clock per word select period + * @{ + */ +#define ATI2S_I2S_CTRL1_RX__SCK2WS_RT__SHIFT 16 +#define ATI2S_I2S_CTRL1_RX__SCK2WS_RT__WIDTH 16 +#define ATI2S_I2S_CTRL1_RX__SCK2WS_RT__MASK 0xffff0000U +#define ATI2S_I2S_CTRL1_RX__SCK2WS_RT__READ(src) \ + (((uint32_t)(src)\ + & 0xffff0000U) >> 16) +#define ATI2S_I2S_CTRL1_RX__SCK2WS_RT__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0xffff0000U) +#define ATI2S_I2S_CTRL1_RX__SCK2WS_RT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define ATI2S_I2S_CTRL1_RX__SCK2WS_RT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define ATI2S_I2S_CTRL1_RX__SCK2WS_RT__RESET_VALUE 0x00000020U +/** @} */ +#define ATI2S_I2S_CTRL1_RX__TYPE uint32_t +#define ATI2S_I2S_CTRL1_RX__READ 0xffffffffU +#define ATI2S_I2S_CTRL1_RX__WRITE 0xffffffffU +#define ATI2S_I2S_CTRL1_RX__PRESERVED 0x00000000U +#define ATI2S_I2S_CTRL1_RX__RESET_VALUE 0x00200010U + +#endif /* __ATI2S_I2S_CTRL1_RX_MACRO__ */ + +/** @} end of i2s_ctrl1_rx */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_ctrl2_tx */ +/** + * @defgroup at_i2s_regs_core_i2s_ctrl2_tx i2s_ctrl2_tx + * @brief Contains register fields associated with i2s_ctrl2_tx. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_CTRL2_TX_MACRO__ +#define __ATI2S_I2S_CTRL2_TX_MACRO__ + +/* macros for field wssd_md */ +/** + * @defgroup at_i2s_regs_core_wssd_md_field wssd_md_field + * @brief macros for field wssd_md + * @details word select serial data mode - specify the behavior of word select and serial data 0 = PCM mode, 1 = left justfied I2S, 2 = right justified I2S + * @{ + */ +#define ATI2S_I2S_CTRL2_TX__WSSD_MD__SHIFT 0 +#define ATI2S_I2S_CTRL2_TX__WSSD_MD__WIDTH 4 +#define ATI2S_I2S_CTRL2_TX__WSSD_MD__MASK 0x0000000fU +#define ATI2S_I2S_CTRL2_TX__WSSD_MD__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define ATI2S_I2S_CTRL2_TX__WSSD_MD__WRITE(src) ((uint32_t)(src) & 0x0000000fU) +#define ATI2S_I2S_CTRL2_TX__WSSD_MD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define ATI2S_I2S_CTRL2_TX__WSSD_MD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define ATI2S_I2S_CTRL2_TX__WSSD_MD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sd_offst */ +/** + * @defgroup at_i2s_regs_core_sd_offst_field sd_offst_field + * @brief macros for field sd_offst + * @details number of cycles after word select edge to wait before driving serial data - valid range is [0:15] + * @{ + */ +#define ATI2S_I2S_CTRL2_TX__SD_OFFST__SHIFT 4 +#define ATI2S_I2S_CTRL2_TX__SD_OFFST__WIDTH 4 +#define ATI2S_I2S_CTRL2_TX__SD_OFFST__MASK 0x000000f0U +#define ATI2S_I2S_CTRL2_TX__SD_OFFST__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define ATI2S_I2S_CTRL2_TX__SD_OFFST__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x000000f0U) +#define ATI2S_I2S_CTRL2_TX__SD_OFFST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define ATI2S_I2S_CTRL2_TX__SD_OFFST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define ATI2S_I2S_CTRL2_TX__SD_OFFST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sdw */ +/** + * @defgroup at_i2s_regs_core_sdw_field sdw_field + * @brief macros for field sdw + * @details width of valid serial data - additioanl bits in a word beyond the width are either padded for tx or discarded for rx valid range is [1:32] + * @{ + */ +#define ATI2S_I2S_CTRL2_TX__SDW__SHIFT 8 +#define ATI2S_I2S_CTRL2_TX__SDW__WIDTH 6 +#define ATI2S_I2S_CTRL2_TX__SDW__MASK 0x00003f00U +#define ATI2S_I2S_CTRL2_TX__SDW__READ(src) \ + (((uint32_t)(src)\ + & 0x00003f00U) >> 8) +#define ATI2S_I2S_CTRL2_TX__SDW__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00003f00U) +#define ATI2S_I2S_CTRL2_TX__SDW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((uint32_t)(src) <<\ + 8) & 0x00003f00U) +#define ATI2S_I2S_CTRL2_TX__SDW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00003f00U))) +#define ATI2S_I2S_CTRL2_TX__SDW__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field pb_cnt */ +/** + * @defgroup at_i2s_regs_core_pb_cnt_field pb_cnt_field + * @brief macros for field pb_cnt + * @details number of zero padding bits - used in right justified mode. + * @{ + */ +#define ATI2S_I2S_CTRL2_TX__PB_CNT__SHIFT 16 +#define ATI2S_I2S_CTRL2_TX__PB_CNT__WIDTH 6 +#define ATI2S_I2S_CTRL2_TX__PB_CNT__MASK 0x003f0000U +#define ATI2S_I2S_CTRL2_TX__PB_CNT__READ(src) \ + (((uint32_t)(src)\ + & 0x003f0000U) >> 16) +#define ATI2S_I2S_CTRL2_TX__PB_CNT__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x003f0000U) +#define ATI2S_I2S_CTRL2_TX__PB_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((uint32_t)(src) <<\ + 16) & 0x003f0000U) +#define ATI2S_I2S_CTRL2_TX__PB_CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x003f0000U))) +#define ATI2S_I2S_CTRL2_TX__PB_CNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field vld_extd_cnt */ +/** + * @defgroup at_i2s_regs_core_vld_extd_cnt_field vld_extd_cnt_field + * @brief macros for field vld_extd_cnt + * @details cycle count to extend vld to ensure it is latched by slow backplane clock + * @{ + */ +#define ATI2S_I2S_CTRL2_TX__VLD_EXTD_CNT__SHIFT 24 +#define ATI2S_I2S_CTRL2_TX__VLD_EXTD_CNT__WIDTH 8 +#define ATI2S_I2S_CTRL2_TX__VLD_EXTD_CNT__MASK 0xff000000U +#define ATI2S_I2S_CTRL2_TX__VLD_EXTD_CNT__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define ATI2S_I2S_CTRL2_TX__VLD_EXTD_CNT__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define ATI2S_I2S_CTRL2_TX__VLD_EXTD_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define ATI2S_I2S_CTRL2_TX__VLD_EXTD_CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define ATI2S_I2S_CTRL2_TX__VLD_EXTD_CNT__RESET_VALUE 0x00000040U +/** @} */ +#define ATI2S_I2S_CTRL2_TX__TYPE uint32_t +#define ATI2S_I2S_CTRL2_TX__READ 0xff3f3fffU +#define ATI2S_I2S_CTRL2_TX__WRITE 0xff3f3fffU +#define ATI2S_I2S_CTRL2_TX__PRESERVED 0x00000000U +#define ATI2S_I2S_CTRL2_TX__RESET_VALUE 0x40001000U + +#endif /* __ATI2S_I2S_CTRL2_TX_MACRO__ */ + +/** @} end of i2s_ctrl2_tx */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_ctrl2_rx */ +/** + * @defgroup at_i2s_regs_core_i2s_ctrl2_rx i2s_ctrl2_rx + * @brief Contains register fields associated with i2s_ctrl2_rx. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_CTRL2_RX_MACRO__ +#define __ATI2S_I2S_CTRL2_RX_MACRO__ + +/* macros for field wssd_md */ +/** + * @defgroup at_i2s_regs_core_wssd_md_field wssd_md_field + * @brief macros for field wssd_md + * @details word select serial data mode - specify the behavior of word select and serial data 0 = PCM mode, 1 = left justfied I2S, 2 = right justified I2S + * @{ + */ +#define ATI2S_I2S_CTRL2_RX__WSSD_MD__SHIFT 0 +#define ATI2S_I2S_CTRL2_RX__WSSD_MD__WIDTH 4 +#define ATI2S_I2S_CTRL2_RX__WSSD_MD__MASK 0x0000000fU +#define ATI2S_I2S_CTRL2_RX__WSSD_MD__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define ATI2S_I2S_CTRL2_RX__WSSD_MD__WRITE(src) ((uint32_t)(src) & 0x0000000fU) +#define ATI2S_I2S_CTRL2_RX__WSSD_MD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define ATI2S_I2S_CTRL2_RX__WSSD_MD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define ATI2S_I2S_CTRL2_RX__WSSD_MD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sd_offst */ +/** + * @defgroup at_i2s_regs_core_sd_offst_field sd_offst_field + * @brief macros for field sd_offst + * @details number of cycles after word select edge to wait before driving serial data - valid range is [0:15] + * @{ + */ +#define ATI2S_I2S_CTRL2_RX__SD_OFFST__SHIFT 4 +#define ATI2S_I2S_CTRL2_RX__SD_OFFST__WIDTH 4 +#define ATI2S_I2S_CTRL2_RX__SD_OFFST__MASK 0x000000f0U +#define ATI2S_I2S_CTRL2_RX__SD_OFFST__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define ATI2S_I2S_CTRL2_RX__SD_OFFST__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x000000f0U) +#define ATI2S_I2S_CTRL2_RX__SD_OFFST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define ATI2S_I2S_CTRL2_RX__SD_OFFST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define ATI2S_I2S_CTRL2_RX__SD_OFFST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sdw */ +/** + * @defgroup at_i2s_regs_core_sdw_field sdw_field + * @brief macros for field sdw + * @details width of valid serial data - additioanl bits in a word beyond the width are either padded for tx or discarded for rx valid range is [1:32] + * @{ + */ +#define ATI2S_I2S_CTRL2_RX__SDW__SHIFT 8 +#define ATI2S_I2S_CTRL2_RX__SDW__WIDTH 6 +#define ATI2S_I2S_CTRL2_RX__SDW__MASK 0x00003f00U +#define ATI2S_I2S_CTRL2_RX__SDW__READ(src) \ + (((uint32_t)(src)\ + & 0x00003f00U) >> 8) +#define ATI2S_I2S_CTRL2_RX__SDW__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00003f00U) +#define ATI2S_I2S_CTRL2_RX__SDW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((uint32_t)(src) <<\ + 8) & 0x00003f00U) +#define ATI2S_I2S_CTRL2_RX__SDW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00003f00U))) +#define ATI2S_I2S_CTRL2_RX__SDW__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field pb_cnt */ +/** + * @defgroup at_i2s_regs_core_pb_cnt_field pb_cnt_field + * @brief macros for field pb_cnt + * @details number of zero padding bits - used in right justified mode. + * @{ + */ +#define ATI2S_I2S_CTRL2_RX__PB_CNT__SHIFT 16 +#define ATI2S_I2S_CTRL2_RX__PB_CNT__WIDTH 6 +#define ATI2S_I2S_CTRL2_RX__PB_CNT__MASK 0x003f0000U +#define ATI2S_I2S_CTRL2_RX__PB_CNT__READ(src) \ + (((uint32_t)(src)\ + & 0x003f0000U) >> 16) +#define ATI2S_I2S_CTRL2_RX__PB_CNT__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x003f0000U) +#define ATI2S_I2S_CTRL2_RX__PB_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((uint32_t)(src) <<\ + 16) & 0x003f0000U) +#define ATI2S_I2S_CTRL2_RX__PB_CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x003f0000U))) +#define ATI2S_I2S_CTRL2_RX__PB_CNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field vld_extd_cnt */ +/** + * @defgroup at_i2s_regs_core_vld_extd_cnt_field vld_extd_cnt_field + * @brief macros for field vld_extd_cnt + * @details cycle count to extend vld to ensure it is latched by slow backplane clock + * @{ + */ +#define ATI2S_I2S_CTRL2_RX__VLD_EXTD_CNT__SHIFT 24 +#define ATI2S_I2S_CTRL2_RX__VLD_EXTD_CNT__WIDTH 8 +#define ATI2S_I2S_CTRL2_RX__VLD_EXTD_CNT__MASK 0xff000000U +#define ATI2S_I2S_CTRL2_RX__VLD_EXTD_CNT__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define ATI2S_I2S_CTRL2_RX__VLD_EXTD_CNT__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define ATI2S_I2S_CTRL2_RX__VLD_EXTD_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define ATI2S_I2S_CTRL2_RX__VLD_EXTD_CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define ATI2S_I2S_CTRL2_RX__VLD_EXTD_CNT__RESET_VALUE 0x00000040U +/** @} */ +#define ATI2S_I2S_CTRL2_RX__TYPE uint32_t +#define ATI2S_I2S_CTRL2_RX__READ 0xff3f3fffU +#define ATI2S_I2S_CTRL2_RX__WRITE 0xff3f3fffU +#define ATI2S_I2S_CTRL2_RX__PRESERVED 0x00000000U +#define ATI2S_I2S_CTRL2_RX__RESET_VALUE 0x40001000U + +#endif /* __ATI2S_I2S_CTRL2_RX_MACRO__ */ + +/** @} end of i2s_ctrl2_rx */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_ctrl3 */ +/** + * @defgroup at_i2s_regs_core_i2s_ctrl3 i2s_ctrl3 + * @brief Contains register fields associated with i2s_ctrl3. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_CTRL3_MACRO__ +#define __ATI2S_I2S_CTRL3_MACRO__ + +/* macros for field swp_smpl */ +/** + * @defgroup at_i2s_regs_core_swp_smpl_field swp_smpl_field + * @brief macros for field swp_smpl + * @details swap packed samples in pingpong buffer location default: former samples uses lsb bits and later samples uses msb bits applies to 16bit samples only + * @{ + */ +#define ATI2S_I2S_CTRL3__SWP_SMPL__SHIFT 0 +#define ATI2S_I2S_CTRL3__SWP_SMPL__WIDTH 1 +#define ATI2S_I2S_CTRL3__SWP_SMPL__MASK 0x00000001U +#define ATI2S_I2S_CTRL3__SWP_SMPL__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATI2S_I2S_CTRL3__SWP_SMPL__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define ATI2S_I2S_CTRL3__SWP_SMPL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATI2S_I2S_CTRL3__SWP_SMPL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define ATI2S_I2S_CTRL3__SWP_SMPL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATI2S_I2S_CTRL3__SWP_SMPL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATI2S_I2S_CTRL3__SWP_SMPL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pck_smpl */ +/** + * @defgroup at_i2s_regs_core_pck_smpl_field pck_smpl_field + * @brief macros for field pck_smpl + * @details pack samples in ping-pong buffer default: samples are stored unpacked applies to 20/24 bit samples only + * @{ + */ +#define ATI2S_I2S_CTRL3__PCK_SMPL__SHIFT 1 +#define ATI2S_I2S_CTRL3__PCK_SMPL__WIDTH 1 +#define ATI2S_I2S_CTRL3__PCK_SMPL__MASK 0x00000002U +#define ATI2S_I2S_CTRL3__PCK_SMPL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define ATI2S_I2S_CTRL3__PCK_SMPL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define ATI2S_I2S_CTRL3__PCK_SMPL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define ATI2S_I2S_CTRL3__PCK_SMPL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define ATI2S_I2S_CTRL3__PCK_SMPL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATI2S_I2S_CTRL3__PCK_SMPL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATI2S_I2S_CTRL3__PCK_SMPL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field use_msb_smpl */ +/** + * @defgroup at_i2s_regs_core_use_msb_smpl_field use_msb_smpl_field + * @brief macros for field use_msb_smpl + * @details use msb of the samples + * @{ + */ +#define ATI2S_I2S_CTRL3__USE_MSB_SMPL__SHIFT 2 +#define ATI2S_I2S_CTRL3__USE_MSB_SMPL__WIDTH 1 +#define ATI2S_I2S_CTRL3__USE_MSB_SMPL__MASK 0x00000004U +#define ATI2S_I2S_CTRL3__USE_MSB_SMPL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define ATI2S_I2S_CTRL3__USE_MSB_SMPL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define ATI2S_I2S_CTRL3__USE_MSB_SMPL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define ATI2S_I2S_CTRL3__USE_MSB_SMPL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define ATI2S_I2S_CTRL3__USE_MSB_SMPL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define ATI2S_I2S_CTRL3__USE_MSB_SMPL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define ATI2S_I2S_CTRL3__USE_MSB_SMPL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field phs_idx */ +/** + * @defgroup at_i2s_regs_core_phs_idx_field phs_idx_field + * @brief macros for field phs_idx + * @details index into the coefficient table + * @{ + */ +#define ATI2S_I2S_CTRL3__PHS_IDX__SHIFT 8 +#define ATI2S_I2S_CTRL3__PHS_IDX__WIDTH 8 +#define ATI2S_I2S_CTRL3__PHS_IDX__MASK 0x0000ff00U +#define ATI2S_I2S_CTRL3__PHS_IDX__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define ATI2S_I2S_CTRL3__PHS_IDX__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define ATI2S_I2S_CTRL3__PHS_IDX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define ATI2S_I2S_CTRL3__PHS_IDX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define ATI2S_I2S_CTRL3__PHS_IDX__RESET_VALUE 0x0000007fU +/** @} */ + +/* macros for field phs_idx_add */ +/** + * @defgroup at_i2s_regs_core_phs_idx_add_field phs_idx_add_field + * @brief macros for field phs_idx_add + * @details index into the coefficient table for insert sample + * @{ + */ +#define ATI2S_I2S_CTRL3__PHS_IDX_ADD__SHIFT 16 +#define ATI2S_I2S_CTRL3__PHS_IDX_ADD__WIDTH 8 +#define ATI2S_I2S_CTRL3__PHS_IDX_ADD__MASK 0x00ff0000U +#define ATI2S_I2S_CTRL3__PHS_IDX_ADD__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define ATI2S_I2S_CTRL3__PHS_IDX_ADD__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define ATI2S_I2S_CTRL3__PHS_IDX_ADD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define ATI2S_I2S_CTRL3__PHS_IDX_ADD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define ATI2S_I2S_CTRL3__PHS_IDX_ADD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrp_use_msb_smpl */ +/** + * @defgroup at_i2s_regs_core_intrp_use_msb_smpl_field intrp_use_msb_smpl_field + * @brief macros for field intrp_use_msb_smpl + * @details Use top 24 bit of 32 bit sample for tx interpolator + * @{ + */ +#define ATI2S_I2S_CTRL3__INTRP_USE_MSB_SMPL__SHIFT 24 +#define ATI2S_I2S_CTRL3__INTRP_USE_MSB_SMPL__WIDTH 1 +#define ATI2S_I2S_CTRL3__INTRP_USE_MSB_SMPL__MASK 0x01000000U +#define ATI2S_I2S_CTRL3__INTRP_USE_MSB_SMPL__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define ATI2S_I2S_CTRL3__INTRP_USE_MSB_SMPL__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define ATI2S_I2S_CTRL3__INTRP_USE_MSB_SMPL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define ATI2S_I2S_CTRL3__INTRP_USE_MSB_SMPL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define ATI2S_I2S_CTRL3__INTRP_USE_MSB_SMPL__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define ATI2S_I2S_CTRL3__INTRP_USE_MSB_SMPL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define ATI2S_I2S_CTRL3__INTRP_USE_MSB_SMPL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrp_byp */ +/** + * @defgroup at_i2s_regs_core_intrp_byp_field intrp_byp_field + * @brief macros for field intrp_byp + * @details bypass interpolator for cfo correction for tx + * @{ + */ +#define ATI2S_I2S_CTRL3__INTRP_BYP__SHIFT 31 +#define ATI2S_I2S_CTRL3__INTRP_BYP__WIDTH 1 +#define ATI2S_I2S_CTRL3__INTRP_BYP__MASK 0x80000000U +#define ATI2S_I2S_CTRL3__INTRP_BYP__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define ATI2S_I2S_CTRL3__INTRP_BYP__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define ATI2S_I2S_CTRL3__INTRP_BYP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define ATI2S_I2S_CTRL3__INTRP_BYP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define ATI2S_I2S_CTRL3__INTRP_BYP__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define ATI2S_I2S_CTRL3__INTRP_BYP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define ATI2S_I2S_CTRL3__INTRP_BYP__RESET_VALUE 0x00000001U +/** @} */ +#define ATI2S_I2S_CTRL3__TYPE uint32_t +#define ATI2S_I2S_CTRL3__READ 0x81ffff07U +#define ATI2S_I2S_CTRL3__WRITE 0x81ffff07U +#define ATI2S_I2S_CTRL3__PRESERVED 0x00000000U +#define ATI2S_I2S_CTRL3__RESET_VALUE 0x80007f04U + +#endif /* __ATI2S_I2S_CTRL3_MACRO__ */ + +/** @} end of i2s_ctrl3 */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_ctrl4 */ +/** + * @defgroup at_i2s_regs_core_i2s_ctrl4 i2s_ctrl4 + * @brief Contains register fields associated with i2s_ctrl4. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_CTRL4_MACRO__ +#define __ATI2S_I2S_CTRL4_MACRO__ + +/* macros for field swp_smpl */ +/** + * @defgroup at_i2s_regs_core_swp_smpl_field swp_smpl_field + * @brief macros for field swp_smpl + * @details swap packed samples in pingpong buffer location default: former samples uses lsb bits and later samples uses msb bits applies to 16bit samples only + * @{ + */ +#define ATI2S_I2S_CTRL4__SWP_SMPL__SHIFT 0 +#define ATI2S_I2S_CTRL4__SWP_SMPL__WIDTH 1 +#define ATI2S_I2S_CTRL4__SWP_SMPL__MASK 0x00000001U +#define ATI2S_I2S_CTRL4__SWP_SMPL__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATI2S_I2S_CTRL4__SWP_SMPL__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define ATI2S_I2S_CTRL4__SWP_SMPL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATI2S_I2S_CTRL4__SWP_SMPL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define ATI2S_I2S_CTRL4__SWP_SMPL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATI2S_I2S_CTRL4__SWP_SMPL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATI2S_I2S_CTRL4__SWP_SMPL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pck_smpl */ +/** + * @defgroup at_i2s_regs_core_pck_smpl_field pck_smpl_field + * @brief macros for field pck_smpl + * @details pack samples in ping-pong buffer default: samples are stored unpacked applies to 20/24 bit samples only + * @{ + */ +#define ATI2S_I2S_CTRL4__PCK_SMPL__SHIFT 1 +#define ATI2S_I2S_CTRL4__PCK_SMPL__WIDTH 1 +#define ATI2S_I2S_CTRL4__PCK_SMPL__MASK 0x00000002U +#define ATI2S_I2S_CTRL4__PCK_SMPL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define ATI2S_I2S_CTRL4__PCK_SMPL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define ATI2S_I2S_CTRL4__PCK_SMPL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define ATI2S_I2S_CTRL4__PCK_SMPL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define ATI2S_I2S_CTRL4__PCK_SMPL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATI2S_I2S_CTRL4__PCK_SMPL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATI2S_I2S_CTRL4__PCK_SMPL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field use_msb_smpl */ +/** + * @defgroup at_i2s_regs_core_use_msb_smpl_field use_msb_smpl_field + * @brief macros for field use_msb_smpl + * @details use msb of the samples + * @{ + */ +#define ATI2S_I2S_CTRL4__USE_MSB_SMPL__SHIFT 2 +#define ATI2S_I2S_CTRL4__USE_MSB_SMPL__WIDTH 1 +#define ATI2S_I2S_CTRL4__USE_MSB_SMPL__MASK 0x00000004U +#define ATI2S_I2S_CTRL4__USE_MSB_SMPL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define ATI2S_I2S_CTRL4__USE_MSB_SMPL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define ATI2S_I2S_CTRL4__USE_MSB_SMPL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define ATI2S_I2S_CTRL4__USE_MSB_SMPL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define ATI2S_I2S_CTRL4__USE_MSB_SMPL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define ATI2S_I2S_CTRL4__USE_MSB_SMPL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define ATI2S_I2S_CTRL4__USE_MSB_SMPL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field phs_idx */ +/** + * @defgroup at_i2s_regs_core_phs_idx_field phs_idx_field + * @brief macros for field phs_idx + * @details index into the coefficient table + * @{ + */ +#define ATI2S_I2S_CTRL4__PHS_IDX__SHIFT 8 +#define ATI2S_I2S_CTRL4__PHS_IDX__WIDTH 8 +#define ATI2S_I2S_CTRL4__PHS_IDX__MASK 0x0000ff00U +#define ATI2S_I2S_CTRL4__PHS_IDX__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define ATI2S_I2S_CTRL4__PHS_IDX__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define ATI2S_I2S_CTRL4__PHS_IDX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define ATI2S_I2S_CTRL4__PHS_IDX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define ATI2S_I2S_CTRL4__PHS_IDX__RESET_VALUE 0x0000007fU +/** @} */ + +/* macros for field phs_idx_add */ +/** + * @defgroup at_i2s_regs_core_phs_idx_add_field phs_idx_add_field + * @brief macros for field phs_idx_add + * @details index into the coefficient table for insert sample + * @{ + */ +#define ATI2S_I2S_CTRL4__PHS_IDX_ADD__SHIFT 16 +#define ATI2S_I2S_CTRL4__PHS_IDX_ADD__WIDTH 8 +#define ATI2S_I2S_CTRL4__PHS_IDX_ADD__MASK 0x00ff0000U +#define ATI2S_I2S_CTRL4__PHS_IDX_ADD__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define ATI2S_I2S_CTRL4__PHS_IDX_ADD__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define ATI2S_I2S_CTRL4__PHS_IDX_ADD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define ATI2S_I2S_CTRL4__PHS_IDX_ADD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define ATI2S_I2S_CTRL4__PHS_IDX_ADD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrp_use_msb_smpl */ +/** + * @defgroup at_i2s_regs_core_intrp_use_msb_smpl_field intrp_use_msb_smpl_field + * @brief macros for field intrp_use_msb_smpl + * @details Use top 24 bit of 32 bit sample for rx interpolator + * @{ + */ +#define ATI2S_I2S_CTRL4__INTRP_USE_MSB_SMPL__SHIFT 24 +#define ATI2S_I2S_CTRL4__INTRP_USE_MSB_SMPL__WIDTH 1 +#define ATI2S_I2S_CTRL4__INTRP_USE_MSB_SMPL__MASK 0x01000000U +#define ATI2S_I2S_CTRL4__INTRP_USE_MSB_SMPL__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define ATI2S_I2S_CTRL4__INTRP_USE_MSB_SMPL__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define ATI2S_I2S_CTRL4__INTRP_USE_MSB_SMPL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define ATI2S_I2S_CTRL4__INTRP_USE_MSB_SMPL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define ATI2S_I2S_CTRL4__INTRP_USE_MSB_SMPL__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define ATI2S_I2S_CTRL4__INTRP_USE_MSB_SMPL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define ATI2S_I2S_CTRL4__INTRP_USE_MSB_SMPL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrp_byp */ +/** + * @defgroup at_i2s_regs_core_intrp_byp_field intrp_byp_field + * @brief macros for field intrp_byp + * @details bypass interpolator for cfo correction for rx + * @{ + */ +#define ATI2S_I2S_CTRL4__INTRP_BYP__SHIFT 31 +#define ATI2S_I2S_CTRL4__INTRP_BYP__WIDTH 1 +#define ATI2S_I2S_CTRL4__INTRP_BYP__MASK 0x80000000U +#define ATI2S_I2S_CTRL4__INTRP_BYP__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define ATI2S_I2S_CTRL4__INTRP_BYP__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define ATI2S_I2S_CTRL4__INTRP_BYP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define ATI2S_I2S_CTRL4__INTRP_BYP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define ATI2S_I2S_CTRL4__INTRP_BYP__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define ATI2S_I2S_CTRL4__INTRP_BYP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define ATI2S_I2S_CTRL4__INTRP_BYP__RESET_VALUE 0x00000001U +/** @} */ +#define ATI2S_I2S_CTRL4__TYPE uint32_t +#define ATI2S_I2S_CTRL4__READ 0x81ffff07U +#define ATI2S_I2S_CTRL4__WRITE 0x81ffff07U +#define ATI2S_I2S_CTRL4__PRESERVED 0x00000000U +#define ATI2S_I2S_CTRL4__RESET_VALUE 0x80007f00U + +#endif /* __ATI2S_I2S_CTRL4_MACRO__ */ + +/** @} end of i2s_ctrl4 */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_ctrl5_tx */ +/** + * @defgroup at_i2s_regs_core_i2s_ctrl5_tx i2s_ctrl5_tx + * @brief Contains register fields associated with i2s_ctrl5_tx. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_CTRL5_TX_MACRO__ +#define __ATI2S_I2S_CTRL5_TX_MACRO__ + +/* macros for field frq_drft_corr_en */ +/** + * @defgroup at_i2s_regs_core_frq_drft_corr_en_field frq_drft_corr_en_field + * @brief macros for field frq_drft_corr_en + * @details 0 = do not enable freq drift correction 1 = enable freq drift correction + * @{ + */ +#define ATI2S_I2S_CTRL5_TX__FRQ_DRFT_CORR_EN__SHIFT 0 +#define ATI2S_I2S_CTRL5_TX__FRQ_DRFT_CORR_EN__WIDTH 1 +#define ATI2S_I2S_CTRL5_TX__FRQ_DRFT_CORR_EN__MASK 0x00000001U +#define ATI2S_I2S_CTRL5_TX__FRQ_DRFT_CORR_EN__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define ATI2S_I2S_CTRL5_TX__FRQ_DRFT_CORR_EN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define ATI2S_I2S_CTRL5_TX__FRQ_DRFT_CORR_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATI2S_I2S_CTRL5_TX__FRQ_DRFT_CORR_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define ATI2S_I2S_CTRL5_TX__FRQ_DRFT_CORR_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATI2S_I2S_CTRL5_TX__FRQ_DRFT_CORR_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATI2S_I2S_CTRL5_TX__FRQ_DRFT_CORR_EN__RESET_VALUE 0x00000000U +/** @} */ +#define ATI2S_I2S_CTRL5_TX__TYPE uint32_t +#define ATI2S_I2S_CTRL5_TX__READ 0x00000001U +#define ATI2S_I2S_CTRL5_TX__WRITE 0x00000001U +#define ATI2S_I2S_CTRL5_TX__PRESERVED 0x00000000U +#define ATI2S_I2S_CTRL5_TX__RESET_VALUE 0x00000000U + +#endif /* __ATI2S_I2S_CTRL5_TX_MACRO__ */ + +/** @} end of i2s_ctrl5_tx */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_ctrl5_rx */ +/** + * @defgroup at_i2s_regs_core_i2s_ctrl5_rx i2s_ctrl5_rx + * @brief Contains register fields associated with i2s_ctrl5_rx. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_CTRL5_RX_MACRO__ +#define __ATI2S_I2S_CTRL5_RX_MACRO__ + +/* macros for field frq_drft_corr_en */ +/** + * @defgroup at_i2s_regs_core_frq_drft_corr_en_field frq_drft_corr_en_field + * @brief macros for field frq_drft_corr_en + * @details 0 = do not enable freq drift correction 1 = enable freq drift correction + * @{ + */ +#define ATI2S_I2S_CTRL5_RX__FRQ_DRFT_CORR_EN__SHIFT 0 +#define ATI2S_I2S_CTRL5_RX__FRQ_DRFT_CORR_EN__WIDTH 1 +#define ATI2S_I2S_CTRL5_RX__FRQ_DRFT_CORR_EN__MASK 0x00000001U +#define ATI2S_I2S_CTRL5_RX__FRQ_DRFT_CORR_EN__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define ATI2S_I2S_CTRL5_RX__FRQ_DRFT_CORR_EN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define ATI2S_I2S_CTRL5_RX__FRQ_DRFT_CORR_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATI2S_I2S_CTRL5_RX__FRQ_DRFT_CORR_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define ATI2S_I2S_CTRL5_RX__FRQ_DRFT_CORR_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATI2S_I2S_CTRL5_RX__FRQ_DRFT_CORR_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATI2S_I2S_CTRL5_RX__FRQ_DRFT_CORR_EN__RESET_VALUE 0x00000000U +/** @} */ +#define ATI2S_I2S_CTRL5_RX__TYPE uint32_t +#define ATI2S_I2S_CTRL5_RX__READ 0x00000001U +#define ATI2S_I2S_CTRL5_RX__WRITE 0x00000001U +#define ATI2S_I2S_CTRL5_RX__PRESERVED 0x00000000U +#define ATI2S_I2S_CTRL5_RX__RESET_VALUE 0x00000000U + +#endif /* __ATI2S_I2S_CTRL5_RX_MACRO__ */ + +/** @} end of i2s_ctrl5_rx */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_intrp_ctrl */ +/** + * @defgroup at_i2s_regs_core_i2s_intrp_ctrl i2s_intrp_ctrl + * @brief Contains register fields associated with i2s_intrp_ctrl. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_INTRP_CTRL_MACRO__ +#define __ATI2S_I2S_INTRP_CTRL_MACRO__ + +/* macros for field tx_skp_smpl */ +/** + * @defgroup at_i2s_regs_core_tx_skp_smpl_field tx_skp_smpl_field + * @brief macros for field tx_skp_smpl + * @details skip one sample to accomodate frequecy drift + * @{ + */ +#define ATI2S_I2S_INTRP_CTRL__TX_SKP_SMPL__SHIFT 0 +#define ATI2S_I2S_INTRP_CTRL__TX_SKP_SMPL__WIDTH 1 +#define ATI2S_I2S_INTRP_CTRL__TX_SKP_SMPL__MASK 0x00000001U +#define ATI2S_I2S_INTRP_CTRL__TX_SKP_SMPL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define ATI2S_I2S_INTRP_CTRL__TX_SKP_SMPL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define ATI2S_I2S_INTRP_CTRL__TX_SKP_SMPL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATI2S_I2S_INTRP_CTRL__TX_SKP_SMPL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define ATI2S_I2S_INTRP_CTRL__TX_SKP_SMPL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATI2S_I2S_INTRP_CTRL__TX_SKP_SMPL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATI2S_I2S_INTRP_CTRL__TX_SKP_SMPL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tx_add_smpl */ +/** + * @defgroup at_i2s_regs_core_tx_add_smpl_field tx_add_smpl_field + * @brief macros for field tx_add_smpl + * @details insert one sample to accomodate frequecy drift + * @{ + */ +#define ATI2S_I2S_INTRP_CTRL__TX_ADD_SMPL__SHIFT 1 +#define ATI2S_I2S_INTRP_CTRL__TX_ADD_SMPL__WIDTH 1 +#define ATI2S_I2S_INTRP_CTRL__TX_ADD_SMPL__MASK 0x00000002U +#define ATI2S_I2S_INTRP_CTRL__TX_ADD_SMPL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define ATI2S_I2S_INTRP_CTRL__TX_ADD_SMPL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define ATI2S_I2S_INTRP_CTRL__TX_ADD_SMPL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define ATI2S_I2S_INTRP_CTRL__TX_ADD_SMPL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define ATI2S_I2S_INTRP_CTRL__TX_ADD_SMPL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATI2S_I2S_INTRP_CTRL__TX_ADD_SMPL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATI2S_I2S_INTRP_CTRL__TX_ADD_SMPL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_skp_smpl */ +/** + * @defgroup at_i2s_regs_core_rx_skp_smpl_field rx_skp_smpl_field + * @brief macros for field rx_skp_smpl + * @details skip one sample to accomodate frequecy drift + * @{ + */ +#define ATI2S_I2S_INTRP_CTRL__RX_SKP_SMPL__SHIFT 2 +#define ATI2S_I2S_INTRP_CTRL__RX_SKP_SMPL__WIDTH 1 +#define ATI2S_I2S_INTRP_CTRL__RX_SKP_SMPL__MASK 0x00000004U +#define ATI2S_I2S_INTRP_CTRL__RX_SKP_SMPL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define ATI2S_I2S_INTRP_CTRL__RX_SKP_SMPL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define ATI2S_I2S_INTRP_CTRL__RX_SKP_SMPL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define ATI2S_I2S_INTRP_CTRL__RX_SKP_SMPL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define ATI2S_I2S_INTRP_CTRL__RX_SKP_SMPL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define ATI2S_I2S_INTRP_CTRL__RX_SKP_SMPL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define ATI2S_I2S_INTRP_CTRL__RX_SKP_SMPL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_add_smpl */ +/** + * @defgroup at_i2s_regs_core_rx_add_smpl_field rx_add_smpl_field + * @brief macros for field rx_add_smpl + * @details insert one sample to accomodate frequecy drift + * @{ + */ +#define ATI2S_I2S_INTRP_CTRL__RX_ADD_SMPL__SHIFT 3 +#define ATI2S_I2S_INTRP_CTRL__RX_ADD_SMPL__WIDTH 1 +#define ATI2S_I2S_INTRP_CTRL__RX_ADD_SMPL__MASK 0x00000008U +#define ATI2S_I2S_INTRP_CTRL__RX_ADD_SMPL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define ATI2S_I2S_INTRP_CTRL__RX_ADD_SMPL__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define ATI2S_I2S_INTRP_CTRL__RX_ADD_SMPL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define ATI2S_I2S_INTRP_CTRL__RX_ADD_SMPL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define ATI2S_I2S_INTRP_CTRL__RX_ADD_SMPL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define ATI2S_I2S_INTRP_CTRL__RX_ADD_SMPL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define ATI2S_I2S_INTRP_CTRL__RX_ADD_SMPL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tx_updt_phs_idx */ +/** + * @defgroup at_i2s_regs_core_tx_updt_phs_idx_field tx_updt_phs_idx_field + * @brief macros for field tx_updt_phs_idx + * @details latch the phase index for tx interpolator + * @{ + */ +#define ATI2S_I2S_INTRP_CTRL__TX_UPDT_PHS_IDX__SHIFT 4 +#define ATI2S_I2S_INTRP_CTRL__TX_UPDT_PHS_IDX__WIDTH 1 +#define ATI2S_I2S_INTRP_CTRL__TX_UPDT_PHS_IDX__MASK 0x00000010U +#define ATI2S_I2S_INTRP_CTRL__TX_UPDT_PHS_IDX__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define ATI2S_I2S_INTRP_CTRL__TX_UPDT_PHS_IDX__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define ATI2S_I2S_INTRP_CTRL__TX_UPDT_PHS_IDX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define ATI2S_I2S_INTRP_CTRL__TX_UPDT_PHS_IDX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define ATI2S_I2S_INTRP_CTRL__TX_UPDT_PHS_IDX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define ATI2S_I2S_INTRP_CTRL__TX_UPDT_PHS_IDX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define ATI2S_I2S_INTRP_CTRL__TX_UPDT_PHS_IDX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_updt_phs_idx */ +/** + * @defgroup at_i2s_regs_core_rx_updt_phs_idx_field rx_updt_phs_idx_field + * @brief macros for field rx_updt_phs_idx + * @details latch the phase index for rx interpolator + * @{ + */ +#define ATI2S_I2S_INTRP_CTRL__RX_UPDT_PHS_IDX__SHIFT 5 +#define ATI2S_I2S_INTRP_CTRL__RX_UPDT_PHS_IDX__WIDTH 1 +#define ATI2S_I2S_INTRP_CTRL__RX_UPDT_PHS_IDX__MASK 0x00000020U +#define ATI2S_I2S_INTRP_CTRL__RX_UPDT_PHS_IDX__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define ATI2S_I2S_INTRP_CTRL__RX_UPDT_PHS_IDX__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define ATI2S_I2S_INTRP_CTRL__RX_UPDT_PHS_IDX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define ATI2S_I2S_INTRP_CTRL__RX_UPDT_PHS_IDX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define ATI2S_I2S_INTRP_CTRL__RX_UPDT_PHS_IDX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define ATI2S_I2S_INTRP_CTRL__RX_UPDT_PHS_IDX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define ATI2S_I2S_INTRP_CTRL__RX_UPDT_PHS_IDX__RESET_VALUE 0x00000000U +/** @} */ +#define ATI2S_I2S_INTRP_CTRL__TYPE uint32_t +#define ATI2S_I2S_INTRP_CTRL__READ 0x0000003fU +#define ATI2S_I2S_INTRP_CTRL__WRITE 0x0000003fU +#define ATI2S_I2S_INTRP_CTRL__PRESERVED 0x00000000U +#define ATI2S_I2S_INTRP_CTRL__RESET_VALUE 0x00000000U + +#endif /* __ATI2S_I2S_INTRP_CTRL_MACRO__ */ + +/** @} end of i2s_intrp_ctrl */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_pp1_rdata */ +/** + * @defgroup at_i2s_regs_core_i2s_pp1_rdata i2s_pp1_rdata + * @brief Contains register fields associated with i2s_pp1_rdata. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_PP1_RDATA_MACRO__ +#define __ATI2S_I2S_PP1_RDATA_MACRO__ + +/* macros for field val */ +/** + * @defgroup at_i2s_regs_core_val_field val_field + * @brief macros for field val + * @details read data at the top of ping pong set 1 buffer 3 + * @{ + */ +#define ATI2S_I2S_PP1_RDATA__VAL__SHIFT 0 +#define ATI2S_I2S_PP1_RDATA__VAL__WIDTH 32 +#define ATI2S_I2S_PP1_RDATA__VAL__MASK 0xffffffffU +#define ATI2S_I2S_PP1_RDATA__VAL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATI2S_I2S_PP1_RDATA__VAL__RESET_VALUE 0x00000000U +/** @} */ +#define ATI2S_I2S_PP1_RDATA__TYPE uint32_t +#define ATI2S_I2S_PP1_RDATA__READ 0xffffffffU +#define ATI2S_I2S_PP1_RDATA__PRESERVED 0x00000000U +#define ATI2S_I2S_PP1_RDATA__RESET_VALUE 0x00000000U + +#endif /* __ATI2S_I2S_PP1_RDATA_MACRO__ */ + +/** @} end of i2s_pp1_rdata */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_pp0_wdata */ +/** + * @defgroup at_i2s_regs_core_i2s_pp0_wdata i2s_pp0_wdata + * @brief Contains register fields associated with i2s_pp0_wdata. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_PP0_WDATA_MACRO__ +#define __ATI2S_I2S_PP0_WDATA_MACRO__ + +/* macros for field val */ +/** + * @defgroup at_i2s_regs_core_val_field val_field + * @brief macros for field val + * @details write data at the bottom of ping pong set 0 buffer 3 + * @{ + */ +#define ATI2S_I2S_PP0_WDATA__VAL__SHIFT 0 +#define ATI2S_I2S_PP0_WDATA__VAL__WIDTH 32 +#define ATI2S_I2S_PP0_WDATA__VAL__MASK 0xffffffffU +#define ATI2S_I2S_PP0_WDATA__VAL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATI2S_I2S_PP0_WDATA__VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATI2S_I2S_PP0_WDATA__VAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define ATI2S_I2S_PP0_WDATA__VAL__RESET_VALUE 0x00000000U +/** @} */ +#define ATI2S_I2S_PP0_WDATA__TYPE uint32_t +#define ATI2S_I2S_PP0_WDATA__WRITE 0x00000000U +#define ATI2S_I2S_PP0_WDATA__PRESERVED 0x00000000U +#define ATI2S_I2S_PP0_WDATA__RESET_VALUE 0x00000000U + +#endif /* __ATI2S_I2S_PP0_WDATA_MACRO__ */ + +/** @} end of i2s_pp0_wdata */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_pp1_ctrl */ +/** + * @defgroup at_i2s_regs_core_i2s_pp1_ctrl i2s_pp1_ctrl + * @brief Contains register fields associated with i2s_pp1_ctrl. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_PP1_CTRL_MACRO__ +#define __ATI2S_I2S_PP1_CTRL_MACRO__ + +/* macros for field thrshld */ +/** + * @defgroup at_i2s_regs_core_thrshld_field thrshld_field + * @brief macros for field thrshld + * @details number of available words that are empty and can be filled + * @{ + */ +#define ATI2S_I2S_PP1_CTRL__THRSHLD__SHIFT 0 +#define ATI2S_I2S_PP1_CTRL__THRSHLD__WIDTH 7 +#define ATI2S_I2S_PP1_CTRL__THRSHLD__MASK 0x0000007fU +#define ATI2S_I2S_PP1_CTRL__THRSHLD__READ(src) ((uint32_t)(src) & 0x0000007fU) +#define ATI2S_I2S_PP1_CTRL__THRSHLD__WRITE(src) ((uint32_t)(src) & 0x0000007fU) +#define ATI2S_I2S_PP1_CTRL__THRSHLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define ATI2S_I2S_PP1_CTRL__THRSHLD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000007fU))) +#define ATI2S_I2S_PP1_CTRL__THRSHLD__RESET_VALUE 0x00000008U +/** @} */ +#define ATI2S_I2S_PP1_CTRL__TYPE uint32_t +#define ATI2S_I2S_PP1_CTRL__READ 0x0000007fU +#define ATI2S_I2S_PP1_CTRL__WRITE 0x0000007fU +#define ATI2S_I2S_PP1_CTRL__PRESERVED 0x00000000U +#define ATI2S_I2S_PP1_CTRL__RESET_VALUE 0x00000008U + +#endif /* __ATI2S_I2S_PP1_CTRL_MACRO__ */ + +/** @} end of i2s_pp1_ctrl */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_pp0_ctrl */ +/** + * @defgroup at_i2s_regs_core_i2s_pp0_ctrl i2s_pp0_ctrl + * @brief Contains register fields associated with i2s_pp0_ctrl. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_PP0_CTRL_MACRO__ +#define __ATI2S_I2S_PP0_CTRL_MACRO__ + +/* macros for field thrshld */ +/** + * @defgroup at_i2s_regs_core_thrshld_field thrshld_field + * @brief macros for field thrshld + * @details number of available words that are empty and can be filled + * @{ + */ +#define ATI2S_I2S_PP0_CTRL__THRSHLD__SHIFT 0 +#define ATI2S_I2S_PP0_CTRL__THRSHLD__WIDTH 7 +#define ATI2S_I2S_PP0_CTRL__THRSHLD__MASK 0x0000007fU +#define ATI2S_I2S_PP0_CTRL__THRSHLD__READ(src) ((uint32_t)(src) & 0x0000007fU) +#define ATI2S_I2S_PP0_CTRL__THRSHLD__WRITE(src) ((uint32_t)(src) & 0x0000007fU) +#define ATI2S_I2S_PP0_CTRL__THRSHLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define ATI2S_I2S_PP0_CTRL__THRSHLD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000007fU))) +#define ATI2S_I2S_PP0_CTRL__THRSHLD__RESET_VALUE 0x00000008U +/** @} */ +#define ATI2S_I2S_PP0_CTRL__TYPE uint32_t +#define ATI2S_I2S_PP0_CTRL__READ 0x0000007fU +#define ATI2S_I2S_PP0_CTRL__WRITE 0x0000007fU +#define ATI2S_I2S_PP0_CTRL__PRESERVED 0x00000000U +#define ATI2S_I2S_PP0_CTRL__RESET_VALUE 0x00000008U + +#endif /* __ATI2S_I2S_PP0_CTRL_MACRO__ */ + +/** @} end of i2s_pp0_ctrl */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_irq0 */ +/** + * @defgroup at_i2s_regs_core_i2s_irq0 i2s_irq0 + * @brief Contains register fields associated with i2s_irq0. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_IRQ0_MACRO__ +#define __ATI2S_I2S_IRQ0_MACRO__ + +/* macros for field pp0_fl */ +/** + * @defgroup at_i2s_regs_core_pp0_fl_field pp0_fl_field + * @brief macros for field pp0_fl + * @details ping pong set 0 buffer 0 full + * @{ + */ +#define ATI2S_I2S_IRQ0__PP0_FL__SHIFT 0 +#define ATI2S_I2S_IRQ0__PP0_FL__WIDTH 1 +#define ATI2S_I2S_IRQ0__PP0_FL__MASK 0x00000001U +#define ATI2S_I2S_IRQ0__PP0_FL__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATI2S_I2S_IRQ0__PP0_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATI2S_I2S_IRQ0__PP0_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATI2S_I2S_IRQ0__PP0_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp1_fl */ +/** + * @defgroup at_i2s_regs_core_pp1_fl_field pp1_fl_field + * @brief macros for field pp1_fl + * @details ping pong set 0 buffer 1 full + * @{ + */ +#define ATI2S_I2S_IRQ0__PP1_FL__SHIFT 1 +#define ATI2S_I2S_IRQ0__PP1_FL__WIDTH 1 +#define ATI2S_I2S_IRQ0__PP1_FL__MASK 0x00000002U +#define ATI2S_I2S_IRQ0__PP1_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define ATI2S_I2S_IRQ0__PP1_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATI2S_I2S_IRQ0__PP1_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATI2S_I2S_IRQ0__PP1_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp2_fl */ +/** + * @defgroup at_i2s_regs_core_pp2_fl_field pp2_fl_field + * @brief macros for field pp2_fl + * @details ping pong set 0 buffer 2 full + * @{ + */ +#define ATI2S_I2S_IRQ0__PP2_FL__SHIFT 2 +#define ATI2S_I2S_IRQ0__PP2_FL__WIDTH 1 +#define ATI2S_I2S_IRQ0__PP2_FL__MASK 0x00000004U +#define ATI2S_I2S_IRQ0__PP2_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define ATI2S_I2S_IRQ0__PP2_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define ATI2S_I2S_IRQ0__PP2_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define ATI2S_I2S_IRQ0__PP2_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp3_fl */ +/** + * @defgroup at_i2s_regs_core_pp3_fl_field pp3_fl_field + * @brief macros for field pp3_fl + * @details ping pong set 0 buffer 3 full + * @{ + */ +#define ATI2S_I2S_IRQ0__PP3_FL__SHIFT 3 +#define ATI2S_I2S_IRQ0__PP3_FL__WIDTH 1 +#define ATI2S_I2S_IRQ0__PP3_FL__MASK 0x00000008U +#define ATI2S_I2S_IRQ0__PP3_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define ATI2S_I2S_IRQ0__PP3_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define ATI2S_I2S_IRQ0__PP3_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define ATI2S_I2S_IRQ0__PP3_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp0_of */ +/** + * @defgroup at_i2s_regs_core_pp0_of_field pp0_of_field + * @brief macros for field pp0_of + * @details ping pong set 0 buffer 0 over flow + * @{ + */ +#define ATI2S_I2S_IRQ0__PP0_OF__SHIFT 4 +#define ATI2S_I2S_IRQ0__PP0_OF__WIDTH 1 +#define ATI2S_I2S_IRQ0__PP0_OF__MASK 0x00000010U +#define ATI2S_I2S_IRQ0__PP0_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define ATI2S_I2S_IRQ0__PP0_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define ATI2S_I2S_IRQ0__PP0_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define ATI2S_I2S_IRQ0__PP0_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp1_of */ +/** + * @defgroup at_i2s_regs_core_pp1_of_field pp1_of_field + * @brief macros for field pp1_of + * @details ping pong set 0 buffer 1 over flow + * @{ + */ +#define ATI2S_I2S_IRQ0__PP1_OF__SHIFT 5 +#define ATI2S_I2S_IRQ0__PP1_OF__WIDTH 1 +#define ATI2S_I2S_IRQ0__PP1_OF__MASK 0x00000020U +#define ATI2S_I2S_IRQ0__PP1_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define ATI2S_I2S_IRQ0__PP1_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define ATI2S_I2S_IRQ0__PP1_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define ATI2S_I2S_IRQ0__PP1_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp2_of */ +/** + * @defgroup at_i2s_regs_core_pp2_of_field pp2_of_field + * @brief macros for field pp2_of + * @details ping pong set 0 buffer 2 over flow + * @{ + */ +#define ATI2S_I2S_IRQ0__PP2_OF__SHIFT 6 +#define ATI2S_I2S_IRQ0__PP2_OF__WIDTH 1 +#define ATI2S_I2S_IRQ0__PP2_OF__MASK 0x00000040U +#define ATI2S_I2S_IRQ0__PP2_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define ATI2S_I2S_IRQ0__PP2_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define ATI2S_I2S_IRQ0__PP2_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define ATI2S_I2S_IRQ0__PP2_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp3_of */ +/** + * @defgroup at_i2s_regs_core_pp3_of_field pp3_of_field + * @brief macros for field pp3_of + * @details ping pong set 0 buffer 3 over flow + * @{ + */ +#define ATI2S_I2S_IRQ0__PP3_OF__SHIFT 7 +#define ATI2S_I2S_IRQ0__PP3_OF__WIDTH 1 +#define ATI2S_I2S_IRQ0__PP3_OF__MASK 0x00000080U +#define ATI2S_I2S_IRQ0__PP3_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define ATI2S_I2S_IRQ0__PP3_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define ATI2S_I2S_IRQ0__PP3_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define ATI2S_I2S_IRQ0__PP3_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp0_uf */ +/** + * @defgroup at_i2s_regs_core_pp0_uf_field pp0_uf_field + * @brief macros for field pp0_uf + * @details ping pong set 0 buffer 0 under flow + * @{ + */ +#define ATI2S_I2S_IRQ0__PP0_UF__SHIFT 8 +#define ATI2S_I2S_IRQ0__PP0_UF__WIDTH 1 +#define ATI2S_I2S_IRQ0__PP0_UF__MASK 0x00000100U +#define ATI2S_I2S_IRQ0__PP0_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define ATI2S_I2S_IRQ0__PP0_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define ATI2S_I2S_IRQ0__PP0_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define ATI2S_I2S_IRQ0__PP0_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp1_uf */ +/** + * @defgroup at_i2s_regs_core_pp1_uf_field pp1_uf_field + * @brief macros for field pp1_uf + * @details ping pong set 0 buffer 1 under flow + * @{ + */ +#define ATI2S_I2S_IRQ0__PP1_UF__SHIFT 9 +#define ATI2S_I2S_IRQ0__PP1_UF__WIDTH 1 +#define ATI2S_I2S_IRQ0__PP1_UF__MASK 0x00000200U +#define ATI2S_I2S_IRQ0__PP1_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define ATI2S_I2S_IRQ0__PP1_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define ATI2S_I2S_IRQ0__PP1_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define ATI2S_I2S_IRQ0__PP1_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp2_uf */ +/** + * @defgroup at_i2s_regs_core_pp2_uf_field pp2_uf_field + * @brief macros for field pp2_uf + * @details ping pong set 0 buffer 2 under flow + * @{ + */ +#define ATI2S_I2S_IRQ0__PP2_UF__SHIFT 10 +#define ATI2S_I2S_IRQ0__PP2_UF__WIDTH 1 +#define ATI2S_I2S_IRQ0__PP2_UF__MASK 0x00000400U +#define ATI2S_I2S_IRQ0__PP2_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define ATI2S_I2S_IRQ0__PP2_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define ATI2S_I2S_IRQ0__PP2_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define ATI2S_I2S_IRQ0__PP2_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp3_uf */ +/** + * @defgroup at_i2s_regs_core_pp3_uf_field pp3_uf_field + * @brief macros for field pp3_uf + * @details ping pong set 0 buffer 3 under flow + * @{ + */ +#define ATI2S_I2S_IRQ0__PP3_UF__SHIFT 11 +#define ATI2S_I2S_IRQ0__PP3_UF__WIDTH 1 +#define ATI2S_I2S_IRQ0__PP3_UF__MASK 0x00000800U +#define ATI2S_I2S_IRQ0__PP3_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define ATI2S_I2S_IRQ0__PP3_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define ATI2S_I2S_IRQ0__PP3_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define ATI2S_I2S_IRQ0__PP3_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp_ep_thrshld */ +/** + * @defgroup at_i2s_regs_core_pp_ep_thrshld_field pp_ep_thrshld_field + * @brief macros for field pp_ep_thrshld + * @details ping pong buffer empty threshold hit + * @{ + */ +#define ATI2S_I2S_IRQ0__PP_EP_THRSHLD__SHIFT 12 +#define ATI2S_I2S_IRQ0__PP_EP_THRSHLD__WIDTH 1 +#define ATI2S_I2S_IRQ0__PP_EP_THRSHLD__MASK 0x00001000U +#define ATI2S_I2S_IRQ0__PP_EP_THRSHLD__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define ATI2S_I2S_IRQ0__PP_EP_THRSHLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define ATI2S_I2S_IRQ0__PP_EP_THRSHLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define ATI2S_I2S_IRQ0__PP_EP_THRSHLD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrp_dout_vld */ +/** + * @defgroup at_i2s_regs_core_intrp_dout_vld_field intrp_dout_vld_field + * @brief macros for field intrp_dout_vld + * @details interpolator data valid + * @{ + */ +#define ATI2S_I2S_IRQ0__INTRP_DOUT_VLD__SHIFT 13 +#define ATI2S_I2S_IRQ0__INTRP_DOUT_VLD__WIDTH 1 +#define ATI2S_I2S_IRQ0__INTRP_DOUT_VLD__MASK 0x00002000U +#define ATI2S_I2S_IRQ0__INTRP_DOUT_VLD__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define ATI2S_I2S_IRQ0__INTRP_DOUT_VLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define ATI2S_I2S_IRQ0__INTRP_DOUT_VLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define ATI2S_I2S_IRQ0__INTRP_DOUT_VLD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pdm_ufof */ +/** + * @defgroup at_i2s_regs_core_pdm_ufof_field pdm_ufof_field + * @brief macros for field pdm_ufof + * @details pdm underflow or overflow + * @{ + */ +#define ATI2S_I2S_IRQ0__PDM_UFOF__SHIFT 31 +#define ATI2S_I2S_IRQ0__PDM_UFOF__WIDTH 1 +#define ATI2S_I2S_IRQ0__PDM_UFOF__MASK 0x80000000U +#define ATI2S_I2S_IRQ0__PDM_UFOF__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define ATI2S_I2S_IRQ0__PDM_UFOF__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define ATI2S_I2S_IRQ0__PDM_UFOF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define ATI2S_I2S_IRQ0__PDM_UFOF__RESET_VALUE 0x00000000U +/** @} */ +#define ATI2S_I2S_IRQ0__TYPE uint32_t +#define ATI2S_I2S_IRQ0__READ 0x80003fffU +#define ATI2S_I2S_IRQ0__PRESERVED 0x00000000U +#define ATI2S_I2S_IRQ0__RESET_VALUE 0x00000000U + +#endif /* __ATI2S_I2S_IRQ0_MACRO__ */ + +/** @} end of i2s_irq0 */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_irqm0 */ +/** + * @defgroup at_i2s_regs_core_i2s_irqm0 i2s_irqm0 + * @brief Contains register fields associated with i2s_irqm0. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_IRQM0_MACRO__ +#define __ATI2S_I2S_IRQM0_MACRO__ + +/* macros for field pp0_fl */ +/** + * @defgroup at_i2s_regs_core_pp0_fl_field pp0_fl_field + * @brief macros for field pp0_fl + * @details ping pong set 0 buffer 0 full mask + * @{ + */ +#define ATI2S_I2S_IRQM0__PP0_FL__SHIFT 0 +#define ATI2S_I2S_IRQM0__PP0_FL__WIDTH 1 +#define ATI2S_I2S_IRQM0__PP0_FL__MASK 0x00000001U +#define ATI2S_I2S_IRQM0__PP0_FL__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATI2S_I2S_IRQM0__PP0_FL__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define ATI2S_I2S_IRQM0__PP0_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATI2S_I2S_IRQM0__PP0_FL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define ATI2S_I2S_IRQM0__PP0_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATI2S_I2S_IRQM0__PP0_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATI2S_I2S_IRQM0__PP0_FL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp1_fl */ +/** + * @defgroup at_i2s_regs_core_pp1_fl_field pp1_fl_field + * @brief macros for field pp1_fl + * @details ping pong set 0 buffer 1 full mask + * @{ + */ +#define ATI2S_I2S_IRQM0__PP1_FL__SHIFT 1 +#define ATI2S_I2S_IRQM0__PP1_FL__WIDTH 1 +#define ATI2S_I2S_IRQM0__PP1_FL__MASK 0x00000002U +#define ATI2S_I2S_IRQM0__PP1_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define ATI2S_I2S_IRQM0__PP1_FL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define ATI2S_I2S_IRQM0__PP1_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define ATI2S_I2S_IRQM0__PP1_FL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define ATI2S_I2S_IRQM0__PP1_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATI2S_I2S_IRQM0__PP1_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATI2S_I2S_IRQM0__PP1_FL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp2_fl */ +/** + * @defgroup at_i2s_regs_core_pp2_fl_field pp2_fl_field + * @brief macros for field pp2_fl + * @details ping pong set 0 buffer 2 full mask + * @{ + */ +#define ATI2S_I2S_IRQM0__PP2_FL__SHIFT 2 +#define ATI2S_I2S_IRQM0__PP2_FL__WIDTH 1 +#define ATI2S_I2S_IRQM0__PP2_FL__MASK 0x00000004U +#define ATI2S_I2S_IRQM0__PP2_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define ATI2S_I2S_IRQM0__PP2_FL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define ATI2S_I2S_IRQM0__PP2_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define ATI2S_I2S_IRQM0__PP2_FL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define ATI2S_I2S_IRQM0__PP2_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define ATI2S_I2S_IRQM0__PP2_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define ATI2S_I2S_IRQM0__PP2_FL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp3_fl */ +/** + * @defgroup at_i2s_regs_core_pp3_fl_field pp3_fl_field + * @brief macros for field pp3_fl + * @details ping pong set 0 buffer 3 full mask + * @{ + */ +#define ATI2S_I2S_IRQM0__PP3_FL__SHIFT 3 +#define ATI2S_I2S_IRQM0__PP3_FL__WIDTH 1 +#define ATI2S_I2S_IRQM0__PP3_FL__MASK 0x00000008U +#define ATI2S_I2S_IRQM0__PP3_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define ATI2S_I2S_IRQM0__PP3_FL__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define ATI2S_I2S_IRQM0__PP3_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define ATI2S_I2S_IRQM0__PP3_FL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define ATI2S_I2S_IRQM0__PP3_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define ATI2S_I2S_IRQM0__PP3_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define ATI2S_I2S_IRQM0__PP3_FL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp0_of */ +/** + * @defgroup at_i2s_regs_core_pp0_of_field pp0_of_field + * @brief macros for field pp0_of + * @details ping pong set 0 buffer 0 over flow mask + * @{ + */ +#define ATI2S_I2S_IRQM0__PP0_OF__SHIFT 4 +#define ATI2S_I2S_IRQM0__PP0_OF__WIDTH 1 +#define ATI2S_I2S_IRQM0__PP0_OF__MASK 0x00000010U +#define ATI2S_I2S_IRQM0__PP0_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define ATI2S_I2S_IRQM0__PP0_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define ATI2S_I2S_IRQM0__PP0_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define ATI2S_I2S_IRQM0__PP0_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define ATI2S_I2S_IRQM0__PP0_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define ATI2S_I2S_IRQM0__PP0_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define ATI2S_I2S_IRQM0__PP0_OF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp1_of */ +/** + * @defgroup at_i2s_regs_core_pp1_of_field pp1_of_field + * @brief macros for field pp1_of + * @details ping pong set 0 buffer 1 over flow mask + * @{ + */ +#define ATI2S_I2S_IRQM0__PP1_OF__SHIFT 5 +#define ATI2S_I2S_IRQM0__PP1_OF__WIDTH 1 +#define ATI2S_I2S_IRQM0__PP1_OF__MASK 0x00000020U +#define ATI2S_I2S_IRQM0__PP1_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define ATI2S_I2S_IRQM0__PP1_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define ATI2S_I2S_IRQM0__PP1_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define ATI2S_I2S_IRQM0__PP1_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define ATI2S_I2S_IRQM0__PP1_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define ATI2S_I2S_IRQM0__PP1_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define ATI2S_I2S_IRQM0__PP1_OF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp2_of */ +/** + * @defgroup at_i2s_regs_core_pp2_of_field pp2_of_field + * @brief macros for field pp2_of + * @details ping pong set 0 buffer 2 over flow mask + * @{ + */ +#define ATI2S_I2S_IRQM0__PP2_OF__SHIFT 6 +#define ATI2S_I2S_IRQM0__PP2_OF__WIDTH 1 +#define ATI2S_I2S_IRQM0__PP2_OF__MASK 0x00000040U +#define ATI2S_I2S_IRQM0__PP2_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define ATI2S_I2S_IRQM0__PP2_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define ATI2S_I2S_IRQM0__PP2_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define ATI2S_I2S_IRQM0__PP2_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define ATI2S_I2S_IRQM0__PP2_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define ATI2S_I2S_IRQM0__PP2_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define ATI2S_I2S_IRQM0__PP2_OF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp3_of */ +/** + * @defgroup at_i2s_regs_core_pp3_of_field pp3_of_field + * @brief macros for field pp3_of + * @details ping pong set 0 buffer 3 over flow mask + * @{ + */ +#define ATI2S_I2S_IRQM0__PP3_OF__SHIFT 7 +#define ATI2S_I2S_IRQM0__PP3_OF__WIDTH 1 +#define ATI2S_I2S_IRQM0__PP3_OF__MASK 0x00000080U +#define ATI2S_I2S_IRQM0__PP3_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define ATI2S_I2S_IRQM0__PP3_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define ATI2S_I2S_IRQM0__PP3_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define ATI2S_I2S_IRQM0__PP3_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define ATI2S_I2S_IRQM0__PP3_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define ATI2S_I2S_IRQM0__PP3_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define ATI2S_I2S_IRQM0__PP3_OF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp0_uf */ +/** + * @defgroup at_i2s_regs_core_pp0_uf_field pp0_uf_field + * @brief macros for field pp0_uf + * @details ping pong set 0 buffer 0 under flow mask + * @{ + */ +#define ATI2S_I2S_IRQM0__PP0_UF__SHIFT 8 +#define ATI2S_I2S_IRQM0__PP0_UF__WIDTH 1 +#define ATI2S_I2S_IRQM0__PP0_UF__MASK 0x00000100U +#define ATI2S_I2S_IRQM0__PP0_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define ATI2S_I2S_IRQM0__PP0_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define ATI2S_I2S_IRQM0__PP0_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define ATI2S_I2S_IRQM0__PP0_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define ATI2S_I2S_IRQM0__PP0_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define ATI2S_I2S_IRQM0__PP0_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define ATI2S_I2S_IRQM0__PP0_UF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp1_uf */ +/** + * @defgroup at_i2s_regs_core_pp1_uf_field pp1_uf_field + * @brief macros for field pp1_uf + * @details ping pong set 0 buffer 1 under flow mask + * @{ + */ +#define ATI2S_I2S_IRQM0__PP1_UF__SHIFT 9 +#define ATI2S_I2S_IRQM0__PP1_UF__WIDTH 1 +#define ATI2S_I2S_IRQM0__PP1_UF__MASK 0x00000200U +#define ATI2S_I2S_IRQM0__PP1_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define ATI2S_I2S_IRQM0__PP1_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define ATI2S_I2S_IRQM0__PP1_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define ATI2S_I2S_IRQM0__PP1_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define ATI2S_I2S_IRQM0__PP1_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define ATI2S_I2S_IRQM0__PP1_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define ATI2S_I2S_IRQM0__PP1_UF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp2_uf */ +/** + * @defgroup at_i2s_regs_core_pp2_uf_field pp2_uf_field + * @brief macros for field pp2_uf + * @details ping pong set 0 buffer 2 under flow mask + * @{ + */ +#define ATI2S_I2S_IRQM0__PP2_UF__SHIFT 10 +#define ATI2S_I2S_IRQM0__PP2_UF__WIDTH 1 +#define ATI2S_I2S_IRQM0__PP2_UF__MASK 0x00000400U +#define ATI2S_I2S_IRQM0__PP2_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define ATI2S_I2S_IRQM0__PP2_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define ATI2S_I2S_IRQM0__PP2_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define ATI2S_I2S_IRQM0__PP2_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define ATI2S_I2S_IRQM0__PP2_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define ATI2S_I2S_IRQM0__PP2_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define ATI2S_I2S_IRQM0__PP2_UF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp3_uf */ +/** + * @defgroup at_i2s_regs_core_pp3_uf_field pp3_uf_field + * @brief macros for field pp3_uf + * @details ping pong set 0 buffer 3 under flow mask + * @{ + */ +#define ATI2S_I2S_IRQM0__PP3_UF__SHIFT 11 +#define ATI2S_I2S_IRQM0__PP3_UF__WIDTH 1 +#define ATI2S_I2S_IRQM0__PP3_UF__MASK 0x00000800U +#define ATI2S_I2S_IRQM0__PP3_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define ATI2S_I2S_IRQM0__PP3_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define ATI2S_I2S_IRQM0__PP3_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define ATI2S_I2S_IRQM0__PP3_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define ATI2S_I2S_IRQM0__PP3_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define ATI2S_I2S_IRQM0__PP3_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define ATI2S_I2S_IRQM0__PP3_UF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp_ep_thrshld */ +/** + * @defgroup at_i2s_regs_core_pp_ep_thrshld_field pp_ep_thrshld_field + * @brief macros for field pp_ep_thrshld + * @details ping pong buffer empty threshold hit mask + * @{ + */ +#define ATI2S_I2S_IRQM0__PP_EP_THRSHLD__SHIFT 12 +#define ATI2S_I2S_IRQM0__PP_EP_THRSHLD__WIDTH 1 +#define ATI2S_I2S_IRQM0__PP_EP_THRSHLD__MASK 0x00001000U +#define ATI2S_I2S_IRQM0__PP_EP_THRSHLD__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define ATI2S_I2S_IRQM0__PP_EP_THRSHLD__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define ATI2S_I2S_IRQM0__PP_EP_THRSHLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define ATI2S_I2S_IRQM0__PP_EP_THRSHLD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define ATI2S_I2S_IRQM0__PP_EP_THRSHLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define ATI2S_I2S_IRQM0__PP_EP_THRSHLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define ATI2S_I2S_IRQM0__PP_EP_THRSHLD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrp_dout_vld */ +/** + * @defgroup at_i2s_regs_core_intrp_dout_vld_field intrp_dout_vld_field + * @brief macros for field intrp_dout_vld + * @details interpolator data valid mask + * @{ + */ +#define ATI2S_I2S_IRQM0__INTRP_DOUT_VLD__SHIFT 13 +#define ATI2S_I2S_IRQM0__INTRP_DOUT_VLD__WIDTH 1 +#define ATI2S_I2S_IRQM0__INTRP_DOUT_VLD__MASK 0x00002000U +#define ATI2S_I2S_IRQM0__INTRP_DOUT_VLD__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define ATI2S_I2S_IRQM0__INTRP_DOUT_VLD__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define ATI2S_I2S_IRQM0__INTRP_DOUT_VLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define ATI2S_I2S_IRQM0__INTRP_DOUT_VLD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define ATI2S_I2S_IRQM0__INTRP_DOUT_VLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define ATI2S_I2S_IRQM0__INTRP_DOUT_VLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define ATI2S_I2S_IRQM0__INTRP_DOUT_VLD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pdm_ufof */ +/** + * @defgroup at_i2s_regs_core_pdm_ufof_field pdm_ufof_field + * @brief macros for field pdm_ufof + * @details pdm underflow or overflow + * @{ + */ +#define ATI2S_I2S_IRQM0__PDM_UFOF__SHIFT 31 +#define ATI2S_I2S_IRQM0__PDM_UFOF__WIDTH 1 +#define ATI2S_I2S_IRQM0__PDM_UFOF__MASK 0x80000000U +#define ATI2S_I2S_IRQM0__PDM_UFOF__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define ATI2S_I2S_IRQM0__PDM_UFOF__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define ATI2S_I2S_IRQM0__PDM_UFOF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define ATI2S_I2S_IRQM0__PDM_UFOF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define ATI2S_I2S_IRQM0__PDM_UFOF__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define ATI2S_I2S_IRQM0__PDM_UFOF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define ATI2S_I2S_IRQM0__PDM_UFOF__RESET_VALUE 0x00000000U +/** @} */ +#define ATI2S_I2S_IRQM0__TYPE uint32_t +#define ATI2S_I2S_IRQM0__READ 0x80003fffU +#define ATI2S_I2S_IRQM0__WRITE 0x80003fffU +#define ATI2S_I2S_IRQM0__PRESERVED 0x00000000U +#define ATI2S_I2S_IRQM0__RESET_VALUE 0x00000fffU + +#endif /* __ATI2S_I2S_IRQM0_MACRO__ */ + +/** @} end of i2s_irqm0 */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_irqs0 */ +/** + * @defgroup at_i2s_regs_core_i2s_irqs0 i2s_irqs0 + * @brief Contains register fields associated with i2s_irqs0. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_IRQS0_MACRO__ +#define __ATI2S_I2S_IRQS0_MACRO__ + +/* macros for field pp0_fl */ +/** + * @defgroup at_i2s_regs_core_pp0_fl_field pp0_fl_field + * @brief macros for field pp0_fl + * @details ping pong set 0 buffer 0 full set + * @{ + */ +#define ATI2S_I2S_IRQS0__PP0_FL__SHIFT 0 +#define ATI2S_I2S_IRQS0__PP0_FL__WIDTH 1 +#define ATI2S_I2S_IRQS0__PP0_FL__MASK 0x00000001U +#define ATI2S_I2S_IRQS0__PP0_FL__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATI2S_I2S_IRQS0__PP0_FL__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define ATI2S_I2S_IRQS0__PP0_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATI2S_I2S_IRQS0__PP0_FL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define ATI2S_I2S_IRQS0__PP0_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATI2S_I2S_IRQS0__PP0_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATI2S_I2S_IRQS0__PP0_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp1_fl */ +/** + * @defgroup at_i2s_regs_core_pp1_fl_field pp1_fl_field + * @brief macros for field pp1_fl + * @details ping pong set 0 buffer 1 full set + * @{ + */ +#define ATI2S_I2S_IRQS0__PP1_FL__SHIFT 1 +#define ATI2S_I2S_IRQS0__PP1_FL__WIDTH 1 +#define ATI2S_I2S_IRQS0__PP1_FL__MASK 0x00000002U +#define ATI2S_I2S_IRQS0__PP1_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define ATI2S_I2S_IRQS0__PP1_FL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define ATI2S_I2S_IRQS0__PP1_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define ATI2S_I2S_IRQS0__PP1_FL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define ATI2S_I2S_IRQS0__PP1_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATI2S_I2S_IRQS0__PP1_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATI2S_I2S_IRQS0__PP1_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp2_fl */ +/** + * @defgroup at_i2s_regs_core_pp2_fl_field pp2_fl_field + * @brief macros for field pp2_fl + * @details ping pong set 0 buffer 2 full set + * @{ + */ +#define ATI2S_I2S_IRQS0__PP2_FL__SHIFT 2 +#define ATI2S_I2S_IRQS0__PP2_FL__WIDTH 1 +#define ATI2S_I2S_IRQS0__PP2_FL__MASK 0x00000004U +#define ATI2S_I2S_IRQS0__PP2_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define ATI2S_I2S_IRQS0__PP2_FL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define ATI2S_I2S_IRQS0__PP2_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define ATI2S_I2S_IRQS0__PP2_FL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define ATI2S_I2S_IRQS0__PP2_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define ATI2S_I2S_IRQS0__PP2_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define ATI2S_I2S_IRQS0__PP2_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp3_fl */ +/** + * @defgroup at_i2s_regs_core_pp3_fl_field pp3_fl_field + * @brief macros for field pp3_fl + * @details ping pong set 0 buffer 3 full set + * @{ + */ +#define ATI2S_I2S_IRQS0__PP3_FL__SHIFT 3 +#define ATI2S_I2S_IRQS0__PP3_FL__WIDTH 1 +#define ATI2S_I2S_IRQS0__PP3_FL__MASK 0x00000008U +#define ATI2S_I2S_IRQS0__PP3_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define ATI2S_I2S_IRQS0__PP3_FL__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define ATI2S_I2S_IRQS0__PP3_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define ATI2S_I2S_IRQS0__PP3_FL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define ATI2S_I2S_IRQS0__PP3_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define ATI2S_I2S_IRQS0__PP3_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define ATI2S_I2S_IRQS0__PP3_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp0_of */ +/** + * @defgroup at_i2s_regs_core_pp0_of_field pp0_of_field + * @brief macros for field pp0_of + * @details ping pong set 0 buffer 0 over flow set + * @{ + */ +#define ATI2S_I2S_IRQS0__PP0_OF__SHIFT 4 +#define ATI2S_I2S_IRQS0__PP0_OF__WIDTH 1 +#define ATI2S_I2S_IRQS0__PP0_OF__MASK 0x00000010U +#define ATI2S_I2S_IRQS0__PP0_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define ATI2S_I2S_IRQS0__PP0_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define ATI2S_I2S_IRQS0__PP0_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define ATI2S_I2S_IRQS0__PP0_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define ATI2S_I2S_IRQS0__PP0_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define ATI2S_I2S_IRQS0__PP0_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define ATI2S_I2S_IRQS0__PP0_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp1_of */ +/** + * @defgroup at_i2s_regs_core_pp1_of_field pp1_of_field + * @brief macros for field pp1_of + * @details ping pong set 0 buffer 1 over flow set + * @{ + */ +#define ATI2S_I2S_IRQS0__PP1_OF__SHIFT 5 +#define ATI2S_I2S_IRQS0__PP1_OF__WIDTH 1 +#define ATI2S_I2S_IRQS0__PP1_OF__MASK 0x00000020U +#define ATI2S_I2S_IRQS0__PP1_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define ATI2S_I2S_IRQS0__PP1_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define ATI2S_I2S_IRQS0__PP1_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define ATI2S_I2S_IRQS0__PP1_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define ATI2S_I2S_IRQS0__PP1_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define ATI2S_I2S_IRQS0__PP1_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define ATI2S_I2S_IRQS0__PP1_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp2_of */ +/** + * @defgroup at_i2s_regs_core_pp2_of_field pp2_of_field + * @brief macros for field pp2_of + * @details ping pong set 0 buffer 2 over flow set + * @{ + */ +#define ATI2S_I2S_IRQS0__PP2_OF__SHIFT 6 +#define ATI2S_I2S_IRQS0__PP2_OF__WIDTH 1 +#define ATI2S_I2S_IRQS0__PP2_OF__MASK 0x00000040U +#define ATI2S_I2S_IRQS0__PP2_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define ATI2S_I2S_IRQS0__PP2_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define ATI2S_I2S_IRQS0__PP2_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define ATI2S_I2S_IRQS0__PP2_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define ATI2S_I2S_IRQS0__PP2_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define ATI2S_I2S_IRQS0__PP2_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define ATI2S_I2S_IRQS0__PP2_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp3_of */ +/** + * @defgroup at_i2s_regs_core_pp3_of_field pp3_of_field + * @brief macros for field pp3_of + * @details ping pong set 0 buffer 3 over flow set + * @{ + */ +#define ATI2S_I2S_IRQS0__PP3_OF__SHIFT 7 +#define ATI2S_I2S_IRQS0__PP3_OF__WIDTH 1 +#define ATI2S_I2S_IRQS0__PP3_OF__MASK 0x00000080U +#define ATI2S_I2S_IRQS0__PP3_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define ATI2S_I2S_IRQS0__PP3_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define ATI2S_I2S_IRQS0__PP3_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define ATI2S_I2S_IRQS0__PP3_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define ATI2S_I2S_IRQS0__PP3_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define ATI2S_I2S_IRQS0__PP3_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define ATI2S_I2S_IRQS0__PP3_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp0_uf */ +/** + * @defgroup at_i2s_regs_core_pp0_uf_field pp0_uf_field + * @brief macros for field pp0_uf + * @details ping pong set 0 buffer 0 under flow set + * @{ + */ +#define ATI2S_I2S_IRQS0__PP0_UF__SHIFT 8 +#define ATI2S_I2S_IRQS0__PP0_UF__WIDTH 1 +#define ATI2S_I2S_IRQS0__PP0_UF__MASK 0x00000100U +#define ATI2S_I2S_IRQS0__PP0_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define ATI2S_I2S_IRQS0__PP0_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define ATI2S_I2S_IRQS0__PP0_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define ATI2S_I2S_IRQS0__PP0_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define ATI2S_I2S_IRQS0__PP0_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define ATI2S_I2S_IRQS0__PP0_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define ATI2S_I2S_IRQS0__PP0_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp1_uf */ +/** + * @defgroup at_i2s_regs_core_pp1_uf_field pp1_uf_field + * @brief macros for field pp1_uf + * @details ping pong set 0 buffer 1 under flow set + * @{ + */ +#define ATI2S_I2S_IRQS0__PP1_UF__SHIFT 9 +#define ATI2S_I2S_IRQS0__PP1_UF__WIDTH 1 +#define ATI2S_I2S_IRQS0__PP1_UF__MASK 0x00000200U +#define ATI2S_I2S_IRQS0__PP1_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define ATI2S_I2S_IRQS0__PP1_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define ATI2S_I2S_IRQS0__PP1_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define ATI2S_I2S_IRQS0__PP1_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define ATI2S_I2S_IRQS0__PP1_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define ATI2S_I2S_IRQS0__PP1_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define ATI2S_I2S_IRQS0__PP1_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp2_uf */ +/** + * @defgroup at_i2s_regs_core_pp2_uf_field pp2_uf_field + * @brief macros for field pp2_uf + * @details ping pong set 0 buffer 2 under flow set + * @{ + */ +#define ATI2S_I2S_IRQS0__PP2_UF__SHIFT 10 +#define ATI2S_I2S_IRQS0__PP2_UF__WIDTH 1 +#define ATI2S_I2S_IRQS0__PP2_UF__MASK 0x00000400U +#define ATI2S_I2S_IRQS0__PP2_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define ATI2S_I2S_IRQS0__PP2_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define ATI2S_I2S_IRQS0__PP2_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define ATI2S_I2S_IRQS0__PP2_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define ATI2S_I2S_IRQS0__PP2_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define ATI2S_I2S_IRQS0__PP2_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define ATI2S_I2S_IRQS0__PP2_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp3_uf */ +/** + * @defgroup at_i2s_regs_core_pp3_uf_field pp3_uf_field + * @brief macros for field pp3_uf + * @details ping pong set 0 buffer 3 under flow set + * @{ + */ +#define ATI2S_I2S_IRQS0__PP3_UF__SHIFT 11 +#define ATI2S_I2S_IRQS0__PP3_UF__WIDTH 1 +#define ATI2S_I2S_IRQS0__PP3_UF__MASK 0x00000800U +#define ATI2S_I2S_IRQS0__PP3_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define ATI2S_I2S_IRQS0__PP3_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define ATI2S_I2S_IRQS0__PP3_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define ATI2S_I2S_IRQS0__PP3_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define ATI2S_I2S_IRQS0__PP3_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define ATI2S_I2S_IRQS0__PP3_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define ATI2S_I2S_IRQS0__PP3_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp_ep_thrshld */ +/** + * @defgroup at_i2s_regs_core_pp_ep_thrshld_field pp_ep_thrshld_field + * @brief macros for field pp_ep_thrshld + * @details ping pong buffer empty threshold hit set + * @{ + */ +#define ATI2S_I2S_IRQS0__PP_EP_THRSHLD__SHIFT 12 +#define ATI2S_I2S_IRQS0__PP_EP_THRSHLD__WIDTH 1 +#define ATI2S_I2S_IRQS0__PP_EP_THRSHLD__MASK 0x00001000U +#define ATI2S_I2S_IRQS0__PP_EP_THRSHLD__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define ATI2S_I2S_IRQS0__PP_EP_THRSHLD__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define ATI2S_I2S_IRQS0__PP_EP_THRSHLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define ATI2S_I2S_IRQS0__PP_EP_THRSHLD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define ATI2S_I2S_IRQS0__PP_EP_THRSHLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define ATI2S_I2S_IRQS0__PP_EP_THRSHLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define ATI2S_I2S_IRQS0__PP_EP_THRSHLD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrp_dout_vld */ +/** + * @defgroup at_i2s_regs_core_intrp_dout_vld_field intrp_dout_vld_field + * @brief macros for field intrp_dout_vld + * @details interpolator data valid set + * @{ + */ +#define ATI2S_I2S_IRQS0__INTRP_DOUT_VLD__SHIFT 13 +#define ATI2S_I2S_IRQS0__INTRP_DOUT_VLD__WIDTH 1 +#define ATI2S_I2S_IRQS0__INTRP_DOUT_VLD__MASK 0x00002000U +#define ATI2S_I2S_IRQS0__INTRP_DOUT_VLD__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define ATI2S_I2S_IRQS0__INTRP_DOUT_VLD__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define ATI2S_I2S_IRQS0__INTRP_DOUT_VLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define ATI2S_I2S_IRQS0__INTRP_DOUT_VLD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define ATI2S_I2S_IRQS0__INTRP_DOUT_VLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define ATI2S_I2S_IRQS0__INTRP_DOUT_VLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define ATI2S_I2S_IRQS0__INTRP_DOUT_VLD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pdm_ufof */ +/** + * @defgroup at_i2s_regs_core_pdm_ufof_field pdm_ufof_field + * @brief macros for field pdm_ufof + * @details pdm underflow or overflow + * @{ + */ +#define ATI2S_I2S_IRQS0__PDM_UFOF__SHIFT 31 +#define ATI2S_I2S_IRQS0__PDM_UFOF__WIDTH 1 +#define ATI2S_I2S_IRQS0__PDM_UFOF__MASK 0x80000000U +#define ATI2S_I2S_IRQS0__PDM_UFOF__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define ATI2S_I2S_IRQS0__PDM_UFOF__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define ATI2S_I2S_IRQS0__PDM_UFOF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define ATI2S_I2S_IRQS0__PDM_UFOF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define ATI2S_I2S_IRQS0__PDM_UFOF__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define ATI2S_I2S_IRQS0__PDM_UFOF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define ATI2S_I2S_IRQS0__PDM_UFOF__RESET_VALUE 0x00000000U +/** @} */ +#define ATI2S_I2S_IRQS0__TYPE uint32_t +#define ATI2S_I2S_IRQS0__READ 0x80003fffU +#define ATI2S_I2S_IRQS0__WRITE 0x80003fffU +#define ATI2S_I2S_IRQS0__PRESERVED 0x00000000U +#define ATI2S_I2S_IRQS0__RESET_VALUE 0x00000000U + +#endif /* __ATI2S_I2S_IRQS0_MACRO__ */ + +/** @} end of i2s_irqs0 */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_irqc0 */ +/** + * @defgroup at_i2s_regs_core_i2s_irqc0 i2s_irqc0 + * @brief Contains register fields associated with i2s_irqc0. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_IRQC0_MACRO__ +#define __ATI2S_I2S_IRQC0_MACRO__ + +/* macros for field pp0_fl */ +/** + * @defgroup at_i2s_regs_core_pp0_fl_field pp0_fl_field + * @brief macros for field pp0_fl + * @details ping pong set 0 buffer 0 full clear + * @{ + */ +#define ATI2S_I2S_IRQC0__PP0_FL__SHIFT 0 +#define ATI2S_I2S_IRQC0__PP0_FL__WIDTH 1 +#define ATI2S_I2S_IRQC0__PP0_FL__MASK 0x00000001U +#define ATI2S_I2S_IRQC0__PP0_FL__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATI2S_I2S_IRQC0__PP0_FL__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define ATI2S_I2S_IRQC0__PP0_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATI2S_I2S_IRQC0__PP0_FL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define ATI2S_I2S_IRQC0__PP0_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATI2S_I2S_IRQC0__PP0_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATI2S_I2S_IRQC0__PP0_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp1_fl */ +/** + * @defgroup at_i2s_regs_core_pp1_fl_field pp1_fl_field + * @brief macros for field pp1_fl + * @details ping pong set 0 buffer 1 full clear + * @{ + */ +#define ATI2S_I2S_IRQC0__PP1_FL__SHIFT 1 +#define ATI2S_I2S_IRQC0__PP1_FL__WIDTH 1 +#define ATI2S_I2S_IRQC0__PP1_FL__MASK 0x00000002U +#define ATI2S_I2S_IRQC0__PP1_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define ATI2S_I2S_IRQC0__PP1_FL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define ATI2S_I2S_IRQC0__PP1_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define ATI2S_I2S_IRQC0__PP1_FL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define ATI2S_I2S_IRQC0__PP1_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATI2S_I2S_IRQC0__PP1_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATI2S_I2S_IRQC0__PP1_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp2_fl */ +/** + * @defgroup at_i2s_regs_core_pp2_fl_field pp2_fl_field + * @brief macros for field pp2_fl + * @details ping pong set 0 buffer 2 full clear + * @{ + */ +#define ATI2S_I2S_IRQC0__PP2_FL__SHIFT 2 +#define ATI2S_I2S_IRQC0__PP2_FL__WIDTH 1 +#define ATI2S_I2S_IRQC0__PP2_FL__MASK 0x00000004U +#define ATI2S_I2S_IRQC0__PP2_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define ATI2S_I2S_IRQC0__PP2_FL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define ATI2S_I2S_IRQC0__PP2_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define ATI2S_I2S_IRQC0__PP2_FL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define ATI2S_I2S_IRQC0__PP2_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define ATI2S_I2S_IRQC0__PP2_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define ATI2S_I2S_IRQC0__PP2_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp3_fl */ +/** + * @defgroup at_i2s_regs_core_pp3_fl_field pp3_fl_field + * @brief macros for field pp3_fl + * @details ping pong set 0 buffer 3 full clear + * @{ + */ +#define ATI2S_I2S_IRQC0__PP3_FL__SHIFT 3 +#define ATI2S_I2S_IRQC0__PP3_FL__WIDTH 1 +#define ATI2S_I2S_IRQC0__PP3_FL__MASK 0x00000008U +#define ATI2S_I2S_IRQC0__PP3_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define ATI2S_I2S_IRQC0__PP3_FL__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define ATI2S_I2S_IRQC0__PP3_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define ATI2S_I2S_IRQC0__PP3_FL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define ATI2S_I2S_IRQC0__PP3_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define ATI2S_I2S_IRQC0__PP3_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define ATI2S_I2S_IRQC0__PP3_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp0_of */ +/** + * @defgroup at_i2s_regs_core_pp0_of_field pp0_of_field + * @brief macros for field pp0_of + * @details ping pong set 0 buffer 0 over flow clear + * @{ + */ +#define ATI2S_I2S_IRQC0__PP0_OF__SHIFT 4 +#define ATI2S_I2S_IRQC0__PP0_OF__WIDTH 1 +#define ATI2S_I2S_IRQC0__PP0_OF__MASK 0x00000010U +#define ATI2S_I2S_IRQC0__PP0_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define ATI2S_I2S_IRQC0__PP0_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define ATI2S_I2S_IRQC0__PP0_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define ATI2S_I2S_IRQC0__PP0_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define ATI2S_I2S_IRQC0__PP0_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define ATI2S_I2S_IRQC0__PP0_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define ATI2S_I2S_IRQC0__PP0_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp1_of */ +/** + * @defgroup at_i2s_regs_core_pp1_of_field pp1_of_field + * @brief macros for field pp1_of + * @details ping pong set 0 buffer 1 over flow clear + * @{ + */ +#define ATI2S_I2S_IRQC0__PP1_OF__SHIFT 5 +#define ATI2S_I2S_IRQC0__PP1_OF__WIDTH 1 +#define ATI2S_I2S_IRQC0__PP1_OF__MASK 0x00000020U +#define ATI2S_I2S_IRQC0__PP1_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define ATI2S_I2S_IRQC0__PP1_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define ATI2S_I2S_IRQC0__PP1_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define ATI2S_I2S_IRQC0__PP1_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define ATI2S_I2S_IRQC0__PP1_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define ATI2S_I2S_IRQC0__PP1_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define ATI2S_I2S_IRQC0__PP1_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp2_of */ +/** + * @defgroup at_i2s_regs_core_pp2_of_field pp2_of_field + * @brief macros for field pp2_of + * @details ping pong set 0 buffer 2 over flow clear + * @{ + */ +#define ATI2S_I2S_IRQC0__PP2_OF__SHIFT 6 +#define ATI2S_I2S_IRQC0__PP2_OF__WIDTH 1 +#define ATI2S_I2S_IRQC0__PP2_OF__MASK 0x00000040U +#define ATI2S_I2S_IRQC0__PP2_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define ATI2S_I2S_IRQC0__PP2_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define ATI2S_I2S_IRQC0__PP2_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define ATI2S_I2S_IRQC0__PP2_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define ATI2S_I2S_IRQC0__PP2_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define ATI2S_I2S_IRQC0__PP2_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define ATI2S_I2S_IRQC0__PP2_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp3_of */ +/** + * @defgroup at_i2s_regs_core_pp3_of_field pp3_of_field + * @brief macros for field pp3_of + * @details ping pong set 0 buffer 3 over flow clear + * @{ + */ +#define ATI2S_I2S_IRQC0__PP3_OF__SHIFT 7 +#define ATI2S_I2S_IRQC0__PP3_OF__WIDTH 1 +#define ATI2S_I2S_IRQC0__PP3_OF__MASK 0x00000080U +#define ATI2S_I2S_IRQC0__PP3_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define ATI2S_I2S_IRQC0__PP3_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define ATI2S_I2S_IRQC0__PP3_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define ATI2S_I2S_IRQC0__PP3_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define ATI2S_I2S_IRQC0__PP3_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define ATI2S_I2S_IRQC0__PP3_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define ATI2S_I2S_IRQC0__PP3_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp0_uf */ +/** + * @defgroup at_i2s_regs_core_pp0_uf_field pp0_uf_field + * @brief macros for field pp0_uf + * @details ping pong set 0 buffer 0 under flow clear + * @{ + */ +#define ATI2S_I2S_IRQC0__PP0_UF__SHIFT 8 +#define ATI2S_I2S_IRQC0__PP0_UF__WIDTH 1 +#define ATI2S_I2S_IRQC0__PP0_UF__MASK 0x00000100U +#define ATI2S_I2S_IRQC0__PP0_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define ATI2S_I2S_IRQC0__PP0_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define ATI2S_I2S_IRQC0__PP0_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define ATI2S_I2S_IRQC0__PP0_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define ATI2S_I2S_IRQC0__PP0_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define ATI2S_I2S_IRQC0__PP0_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define ATI2S_I2S_IRQC0__PP0_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp1_uf */ +/** + * @defgroup at_i2s_regs_core_pp1_uf_field pp1_uf_field + * @brief macros for field pp1_uf + * @details ping pong set 0 buffer 1 under flow clear + * @{ + */ +#define ATI2S_I2S_IRQC0__PP1_UF__SHIFT 9 +#define ATI2S_I2S_IRQC0__PP1_UF__WIDTH 1 +#define ATI2S_I2S_IRQC0__PP1_UF__MASK 0x00000200U +#define ATI2S_I2S_IRQC0__PP1_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define ATI2S_I2S_IRQC0__PP1_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define ATI2S_I2S_IRQC0__PP1_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define ATI2S_I2S_IRQC0__PP1_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define ATI2S_I2S_IRQC0__PP1_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define ATI2S_I2S_IRQC0__PP1_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define ATI2S_I2S_IRQC0__PP1_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp2_uf */ +/** + * @defgroup at_i2s_regs_core_pp2_uf_field pp2_uf_field + * @brief macros for field pp2_uf + * @details ping pong set 0 buffer 2 under flow clear + * @{ + */ +#define ATI2S_I2S_IRQC0__PP2_UF__SHIFT 10 +#define ATI2S_I2S_IRQC0__PP2_UF__WIDTH 1 +#define ATI2S_I2S_IRQC0__PP2_UF__MASK 0x00000400U +#define ATI2S_I2S_IRQC0__PP2_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define ATI2S_I2S_IRQC0__PP2_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define ATI2S_I2S_IRQC0__PP2_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define ATI2S_I2S_IRQC0__PP2_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define ATI2S_I2S_IRQC0__PP2_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define ATI2S_I2S_IRQC0__PP2_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define ATI2S_I2S_IRQC0__PP2_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp3_uf */ +/** + * @defgroup at_i2s_regs_core_pp3_uf_field pp3_uf_field + * @brief macros for field pp3_uf + * @details ping pong set 0 buffer 3 under flow clear + * @{ + */ +#define ATI2S_I2S_IRQC0__PP3_UF__SHIFT 11 +#define ATI2S_I2S_IRQC0__PP3_UF__WIDTH 1 +#define ATI2S_I2S_IRQC0__PP3_UF__MASK 0x00000800U +#define ATI2S_I2S_IRQC0__PP3_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define ATI2S_I2S_IRQC0__PP3_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define ATI2S_I2S_IRQC0__PP3_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define ATI2S_I2S_IRQC0__PP3_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define ATI2S_I2S_IRQC0__PP3_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define ATI2S_I2S_IRQC0__PP3_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define ATI2S_I2S_IRQC0__PP3_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp_ep_thrshld */ +/** + * @defgroup at_i2s_regs_core_pp_ep_thrshld_field pp_ep_thrshld_field + * @brief macros for field pp_ep_thrshld + * @details ping pong buffer empty threshold hit clear + * @{ + */ +#define ATI2S_I2S_IRQC0__PP_EP_THRSHLD__SHIFT 12 +#define ATI2S_I2S_IRQC0__PP_EP_THRSHLD__WIDTH 1 +#define ATI2S_I2S_IRQC0__PP_EP_THRSHLD__MASK 0x00001000U +#define ATI2S_I2S_IRQC0__PP_EP_THRSHLD__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define ATI2S_I2S_IRQC0__PP_EP_THRSHLD__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define ATI2S_I2S_IRQC0__PP_EP_THRSHLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define ATI2S_I2S_IRQC0__PP_EP_THRSHLD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define ATI2S_I2S_IRQC0__PP_EP_THRSHLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define ATI2S_I2S_IRQC0__PP_EP_THRSHLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define ATI2S_I2S_IRQC0__PP_EP_THRSHLD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrp_dout_vld */ +/** + * @defgroup at_i2s_regs_core_intrp_dout_vld_field intrp_dout_vld_field + * @brief macros for field intrp_dout_vld + * @details interpolator data valid clear + * @{ + */ +#define ATI2S_I2S_IRQC0__INTRP_DOUT_VLD__SHIFT 13 +#define ATI2S_I2S_IRQC0__INTRP_DOUT_VLD__WIDTH 1 +#define ATI2S_I2S_IRQC0__INTRP_DOUT_VLD__MASK 0x00002000U +#define ATI2S_I2S_IRQC0__INTRP_DOUT_VLD__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define ATI2S_I2S_IRQC0__INTRP_DOUT_VLD__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define ATI2S_I2S_IRQC0__INTRP_DOUT_VLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define ATI2S_I2S_IRQC0__INTRP_DOUT_VLD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define ATI2S_I2S_IRQC0__INTRP_DOUT_VLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define ATI2S_I2S_IRQC0__INTRP_DOUT_VLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define ATI2S_I2S_IRQC0__INTRP_DOUT_VLD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pdm_ufof */ +/** + * @defgroup at_i2s_regs_core_pdm_ufof_field pdm_ufof_field + * @brief macros for field pdm_ufof + * @details pdm underflow or overflow + * @{ + */ +#define ATI2S_I2S_IRQC0__PDM_UFOF__SHIFT 31 +#define ATI2S_I2S_IRQC0__PDM_UFOF__WIDTH 1 +#define ATI2S_I2S_IRQC0__PDM_UFOF__MASK 0x80000000U +#define ATI2S_I2S_IRQC0__PDM_UFOF__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define ATI2S_I2S_IRQC0__PDM_UFOF__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define ATI2S_I2S_IRQC0__PDM_UFOF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define ATI2S_I2S_IRQC0__PDM_UFOF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define ATI2S_I2S_IRQC0__PDM_UFOF__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define ATI2S_I2S_IRQC0__PDM_UFOF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define ATI2S_I2S_IRQC0__PDM_UFOF__RESET_VALUE 0x00000000U +/** @} */ +#define ATI2S_I2S_IRQC0__TYPE uint32_t +#define ATI2S_I2S_IRQC0__READ 0x80003fffU +#define ATI2S_I2S_IRQC0__WRITE 0x80003fffU +#define ATI2S_I2S_IRQC0__PRESERVED 0x00000000U +#define ATI2S_I2S_IRQC0__RESET_VALUE 0x00000000U + +#endif /* __ATI2S_I2S_IRQC0_MACRO__ */ + +/** @} end of i2s_irqc0 */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_irq1 */ +/** + * @defgroup at_i2s_regs_core_i2s_irq1 i2s_irq1 + * @brief Contains register fields associated with i2s_irq1. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_IRQ1_MACRO__ +#define __ATI2S_I2S_IRQ1_MACRO__ + +/* macros for field pp0_fl */ +/** + * @defgroup at_i2s_regs_core_pp0_fl_field pp0_fl_field + * @brief macros for field pp0_fl + * @details ping pong set 1 buffer 0 full + * @{ + */ +#define ATI2S_I2S_IRQ1__PP0_FL__SHIFT 0 +#define ATI2S_I2S_IRQ1__PP0_FL__WIDTH 1 +#define ATI2S_I2S_IRQ1__PP0_FL__MASK 0x00000001U +#define ATI2S_I2S_IRQ1__PP0_FL__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATI2S_I2S_IRQ1__PP0_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATI2S_I2S_IRQ1__PP0_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATI2S_I2S_IRQ1__PP0_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp1_fl */ +/** + * @defgroup at_i2s_regs_core_pp1_fl_field pp1_fl_field + * @brief macros for field pp1_fl + * @details ping pong set 1 buffer 1 full + * @{ + */ +#define ATI2S_I2S_IRQ1__PP1_FL__SHIFT 1 +#define ATI2S_I2S_IRQ1__PP1_FL__WIDTH 1 +#define ATI2S_I2S_IRQ1__PP1_FL__MASK 0x00000002U +#define ATI2S_I2S_IRQ1__PP1_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define ATI2S_I2S_IRQ1__PP1_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATI2S_I2S_IRQ1__PP1_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATI2S_I2S_IRQ1__PP1_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp2_fl */ +/** + * @defgroup at_i2s_regs_core_pp2_fl_field pp2_fl_field + * @brief macros for field pp2_fl + * @details ping pong set 1 buffer 2 full + * @{ + */ +#define ATI2S_I2S_IRQ1__PP2_FL__SHIFT 2 +#define ATI2S_I2S_IRQ1__PP2_FL__WIDTH 1 +#define ATI2S_I2S_IRQ1__PP2_FL__MASK 0x00000004U +#define ATI2S_I2S_IRQ1__PP2_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define ATI2S_I2S_IRQ1__PP2_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define ATI2S_I2S_IRQ1__PP2_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define ATI2S_I2S_IRQ1__PP2_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp3_fl */ +/** + * @defgroup at_i2s_regs_core_pp3_fl_field pp3_fl_field + * @brief macros for field pp3_fl + * @details ping pong set 1 buffer 3 full + * @{ + */ +#define ATI2S_I2S_IRQ1__PP3_FL__SHIFT 3 +#define ATI2S_I2S_IRQ1__PP3_FL__WIDTH 1 +#define ATI2S_I2S_IRQ1__PP3_FL__MASK 0x00000008U +#define ATI2S_I2S_IRQ1__PP3_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define ATI2S_I2S_IRQ1__PP3_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define ATI2S_I2S_IRQ1__PP3_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define ATI2S_I2S_IRQ1__PP3_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp0_of */ +/** + * @defgroup at_i2s_regs_core_pp0_of_field pp0_of_field + * @brief macros for field pp0_of + * @details ping pong set 1 buffer 0 over flow + * @{ + */ +#define ATI2S_I2S_IRQ1__PP0_OF__SHIFT 4 +#define ATI2S_I2S_IRQ1__PP0_OF__WIDTH 1 +#define ATI2S_I2S_IRQ1__PP0_OF__MASK 0x00000010U +#define ATI2S_I2S_IRQ1__PP0_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define ATI2S_I2S_IRQ1__PP0_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define ATI2S_I2S_IRQ1__PP0_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define ATI2S_I2S_IRQ1__PP0_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp1_of */ +/** + * @defgroup at_i2s_regs_core_pp1_of_field pp1_of_field + * @brief macros for field pp1_of + * @details ping pong set 1 buffer 1 over flow + * @{ + */ +#define ATI2S_I2S_IRQ1__PP1_OF__SHIFT 5 +#define ATI2S_I2S_IRQ1__PP1_OF__WIDTH 1 +#define ATI2S_I2S_IRQ1__PP1_OF__MASK 0x00000020U +#define ATI2S_I2S_IRQ1__PP1_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define ATI2S_I2S_IRQ1__PP1_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define ATI2S_I2S_IRQ1__PP1_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define ATI2S_I2S_IRQ1__PP1_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp2_of */ +/** + * @defgroup at_i2s_regs_core_pp2_of_field pp2_of_field + * @brief macros for field pp2_of + * @details ping pong set 1 buffer 2 over flow + * @{ + */ +#define ATI2S_I2S_IRQ1__PP2_OF__SHIFT 6 +#define ATI2S_I2S_IRQ1__PP2_OF__WIDTH 1 +#define ATI2S_I2S_IRQ1__PP2_OF__MASK 0x00000040U +#define ATI2S_I2S_IRQ1__PP2_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define ATI2S_I2S_IRQ1__PP2_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define ATI2S_I2S_IRQ1__PP2_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define ATI2S_I2S_IRQ1__PP2_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp3_of */ +/** + * @defgroup at_i2s_regs_core_pp3_of_field pp3_of_field + * @brief macros for field pp3_of + * @details ping pong set 1 buffer 3 over flow + * @{ + */ +#define ATI2S_I2S_IRQ1__PP3_OF__SHIFT 7 +#define ATI2S_I2S_IRQ1__PP3_OF__WIDTH 1 +#define ATI2S_I2S_IRQ1__PP3_OF__MASK 0x00000080U +#define ATI2S_I2S_IRQ1__PP3_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define ATI2S_I2S_IRQ1__PP3_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define ATI2S_I2S_IRQ1__PP3_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define ATI2S_I2S_IRQ1__PP3_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp0_uf */ +/** + * @defgroup at_i2s_regs_core_pp0_uf_field pp0_uf_field + * @brief macros for field pp0_uf + * @details ping pong set 1 buffer 0 under flow + * @{ + */ +#define ATI2S_I2S_IRQ1__PP0_UF__SHIFT 8 +#define ATI2S_I2S_IRQ1__PP0_UF__WIDTH 1 +#define ATI2S_I2S_IRQ1__PP0_UF__MASK 0x00000100U +#define ATI2S_I2S_IRQ1__PP0_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define ATI2S_I2S_IRQ1__PP0_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define ATI2S_I2S_IRQ1__PP0_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define ATI2S_I2S_IRQ1__PP0_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp1_uf */ +/** + * @defgroup at_i2s_regs_core_pp1_uf_field pp1_uf_field + * @brief macros for field pp1_uf + * @details ping pong set 1 buffer 1 under flow + * @{ + */ +#define ATI2S_I2S_IRQ1__PP1_UF__SHIFT 9 +#define ATI2S_I2S_IRQ1__PP1_UF__WIDTH 1 +#define ATI2S_I2S_IRQ1__PP1_UF__MASK 0x00000200U +#define ATI2S_I2S_IRQ1__PP1_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define ATI2S_I2S_IRQ1__PP1_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define ATI2S_I2S_IRQ1__PP1_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define ATI2S_I2S_IRQ1__PP1_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp2_uf */ +/** + * @defgroup at_i2s_regs_core_pp2_uf_field pp2_uf_field + * @brief macros for field pp2_uf + * @details ping pong set 1 buffer 2 under flow + * @{ + */ +#define ATI2S_I2S_IRQ1__PP2_UF__SHIFT 10 +#define ATI2S_I2S_IRQ1__PP2_UF__WIDTH 1 +#define ATI2S_I2S_IRQ1__PP2_UF__MASK 0x00000400U +#define ATI2S_I2S_IRQ1__PP2_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define ATI2S_I2S_IRQ1__PP2_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define ATI2S_I2S_IRQ1__PP2_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define ATI2S_I2S_IRQ1__PP2_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp3_uf */ +/** + * @defgroup at_i2s_regs_core_pp3_uf_field pp3_uf_field + * @brief macros for field pp3_uf + * @details ping pong set 1 buffer 3 under flow + * @{ + */ +#define ATI2S_I2S_IRQ1__PP3_UF__SHIFT 11 +#define ATI2S_I2S_IRQ1__PP3_UF__WIDTH 1 +#define ATI2S_I2S_IRQ1__PP3_UF__MASK 0x00000800U +#define ATI2S_I2S_IRQ1__PP3_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define ATI2S_I2S_IRQ1__PP3_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define ATI2S_I2S_IRQ1__PP3_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define ATI2S_I2S_IRQ1__PP3_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp_ep_thrshld */ +/** + * @defgroup at_i2s_regs_core_pp_ep_thrshld_field pp_ep_thrshld_field + * @brief macros for field pp_ep_thrshld + * @details ping pong buffer empty threshold hit + * @{ + */ +#define ATI2S_I2S_IRQ1__PP_EP_THRSHLD__SHIFT 12 +#define ATI2S_I2S_IRQ1__PP_EP_THRSHLD__WIDTH 1 +#define ATI2S_I2S_IRQ1__PP_EP_THRSHLD__MASK 0x00001000U +#define ATI2S_I2S_IRQ1__PP_EP_THRSHLD__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define ATI2S_I2S_IRQ1__PP_EP_THRSHLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define ATI2S_I2S_IRQ1__PP_EP_THRSHLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define ATI2S_I2S_IRQ1__PP_EP_THRSHLD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrp_dout_vld */ +/** + * @defgroup at_i2s_regs_core_intrp_dout_vld_field intrp_dout_vld_field + * @brief macros for field intrp_dout_vld + * @details interpolator data valid + * @{ + */ +#define ATI2S_I2S_IRQ1__INTRP_DOUT_VLD__SHIFT 13 +#define ATI2S_I2S_IRQ1__INTRP_DOUT_VLD__WIDTH 1 +#define ATI2S_I2S_IRQ1__INTRP_DOUT_VLD__MASK 0x00002000U +#define ATI2S_I2S_IRQ1__INTRP_DOUT_VLD__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define ATI2S_I2S_IRQ1__INTRP_DOUT_VLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define ATI2S_I2S_IRQ1__INTRP_DOUT_VLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define ATI2S_I2S_IRQ1__INTRP_DOUT_VLD__RESET_VALUE 0x00000000U +/** @} */ +#define ATI2S_I2S_IRQ1__TYPE uint32_t +#define ATI2S_I2S_IRQ1__READ 0x00003fffU +#define ATI2S_I2S_IRQ1__PRESERVED 0x00000000U +#define ATI2S_I2S_IRQ1__RESET_VALUE 0x00000000U + +#endif /* __ATI2S_I2S_IRQ1_MACRO__ */ + +/** @} end of i2s_irq1 */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_irqm1 */ +/** + * @defgroup at_i2s_regs_core_i2s_irqm1 i2s_irqm1 + * @brief Contains register fields associated with i2s_irqm1. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_IRQM1_MACRO__ +#define __ATI2S_I2S_IRQM1_MACRO__ + +/* macros for field pp0_fl */ +/** + * @defgroup at_i2s_regs_core_pp0_fl_field pp0_fl_field + * @brief macros for field pp0_fl + * @details ping pong set 1 buffer 0 full mask + * @{ + */ +#define ATI2S_I2S_IRQM1__PP0_FL__SHIFT 0 +#define ATI2S_I2S_IRQM1__PP0_FL__WIDTH 1 +#define ATI2S_I2S_IRQM1__PP0_FL__MASK 0x00000001U +#define ATI2S_I2S_IRQM1__PP0_FL__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATI2S_I2S_IRQM1__PP0_FL__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define ATI2S_I2S_IRQM1__PP0_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATI2S_I2S_IRQM1__PP0_FL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define ATI2S_I2S_IRQM1__PP0_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATI2S_I2S_IRQM1__PP0_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATI2S_I2S_IRQM1__PP0_FL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp1_fl */ +/** + * @defgroup at_i2s_regs_core_pp1_fl_field pp1_fl_field + * @brief macros for field pp1_fl + * @details ping pong set 1 buffer 1 full mask + * @{ + */ +#define ATI2S_I2S_IRQM1__PP1_FL__SHIFT 1 +#define ATI2S_I2S_IRQM1__PP1_FL__WIDTH 1 +#define ATI2S_I2S_IRQM1__PP1_FL__MASK 0x00000002U +#define ATI2S_I2S_IRQM1__PP1_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define ATI2S_I2S_IRQM1__PP1_FL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define ATI2S_I2S_IRQM1__PP1_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define ATI2S_I2S_IRQM1__PP1_FL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define ATI2S_I2S_IRQM1__PP1_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATI2S_I2S_IRQM1__PP1_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATI2S_I2S_IRQM1__PP1_FL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp2_fl */ +/** + * @defgroup at_i2s_regs_core_pp2_fl_field pp2_fl_field + * @brief macros for field pp2_fl + * @details ping pong set 1 buffer 2 full mask + * @{ + */ +#define ATI2S_I2S_IRQM1__PP2_FL__SHIFT 2 +#define ATI2S_I2S_IRQM1__PP2_FL__WIDTH 1 +#define ATI2S_I2S_IRQM1__PP2_FL__MASK 0x00000004U +#define ATI2S_I2S_IRQM1__PP2_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define ATI2S_I2S_IRQM1__PP2_FL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define ATI2S_I2S_IRQM1__PP2_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define ATI2S_I2S_IRQM1__PP2_FL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define ATI2S_I2S_IRQM1__PP2_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define ATI2S_I2S_IRQM1__PP2_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define ATI2S_I2S_IRQM1__PP2_FL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp3_fl */ +/** + * @defgroup at_i2s_regs_core_pp3_fl_field pp3_fl_field + * @brief macros for field pp3_fl + * @details ping pong set 1 buffer 3 full mask + * @{ + */ +#define ATI2S_I2S_IRQM1__PP3_FL__SHIFT 3 +#define ATI2S_I2S_IRQM1__PP3_FL__WIDTH 1 +#define ATI2S_I2S_IRQM1__PP3_FL__MASK 0x00000008U +#define ATI2S_I2S_IRQM1__PP3_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define ATI2S_I2S_IRQM1__PP3_FL__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define ATI2S_I2S_IRQM1__PP3_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define ATI2S_I2S_IRQM1__PP3_FL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define ATI2S_I2S_IRQM1__PP3_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define ATI2S_I2S_IRQM1__PP3_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define ATI2S_I2S_IRQM1__PP3_FL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp0_of */ +/** + * @defgroup at_i2s_regs_core_pp0_of_field pp0_of_field + * @brief macros for field pp0_of + * @details ping pong set 1 buffer 0 over flow mask + * @{ + */ +#define ATI2S_I2S_IRQM1__PP0_OF__SHIFT 4 +#define ATI2S_I2S_IRQM1__PP0_OF__WIDTH 1 +#define ATI2S_I2S_IRQM1__PP0_OF__MASK 0x00000010U +#define ATI2S_I2S_IRQM1__PP0_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define ATI2S_I2S_IRQM1__PP0_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define ATI2S_I2S_IRQM1__PP0_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define ATI2S_I2S_IRQM1__PP0_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define ATI2S_I2S_IRQM1__PP0_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define ATI2S_I2S_IRQM1__PP0_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define ATI2S_I2S_IRQM1__PP0_OF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp1_of */ +/** + * @defgroup at_i2s_regs_core_pp1_of_field pp1_of_field + * @brief macros for field pp1_of + * @details ping pong set 1 buffer 1 over flow mask + * @{ + */ +#define ATI2S_I2S_IRQM1__PP1_OF__SHIFT 5 +#define ATI2S_I2S_IRQM1__PP1_OF__WIDTH 1 +#define ATI2S_I2S_IRQM1__PP1_OF__MASK 0x00000020U +#define ATI2S_I2S_IRQM1__PP1_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define ATI2S_I2S_IRQM1__PP1_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define ATI2S_I2S_IRQM1__PP1_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define ATI2S_I2S_IRQM1__PP1_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define ATI2S_I2S_IRQM1__PP1_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define ATI2S_I2S_IRQM1__PP1_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define ATI2S_I2S_IRQM1__PP1_OF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp2_of */ +/** + * @defgroup at_i2s_regs_core_pp2_of_field pp2_of_field + * @brief macros for field pp2_of + * @details ping pong set 1 buffer 2 over flow mask + * @{ + */ +#define ATI2S_I2S_IRQM1__PP2_OF__SHIFT 6 +#define ATI2S_I2S_IRQM1__PP2_OF__WIDTH 1 +#define ATI2S_I2S_IRQM1__PP2_OF__MASK 0x00000040U +#define ATI2S_I2S_IRQM1__PP2_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define ATI2S_I2S_IRQM1__PP2_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define ATI2S_I2S_IRQM1__PP2_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define ATI2S_I2S_IRQM1__PP2_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define ATI2S_I2S_IRQM1__PP2_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define ATI2S_I2S_IRQM1__PP2_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define ATI2S_I2S_IRQM1__PP2_OF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp3_of */ +/** + * @defgroup at_i2s_regs_core_pp3_of_field pp3_of_field + * @brief macros for field pp3_of + * @details ping pong set 1 buffer 3 over flow mask + * @{ + */ +#define ATI2S_I2S_IRQM1__PP3_OF__SHIFT 7 +#define ATI2S_I2S_IRQM1__PP3_OF__WIDTH 1 +#define ATI2S_I2S_IRQM1__PP3_OF__MASK 0x00000080U +#define ATI2S_I2S_IRQM1__PP3_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define ATI2S_I2S_IRQM1__PP3_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define ATI2S_I2S_IRQM1__PP3_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define ATI2S_I2S_IRQM1__PP3_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define ATI2S_I2S_IRQM1__PP3_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define ATI2S_I2S_IRQM1__PP3_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define ATI2S_I2S_IRQM1__PP3_OF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp0_uf */ +/** + * @defgroup at_i2s_regs_core_pp0_uf_field pp0_uf_field + * @brief macros for field pp0_uf + * @details ping pong set 1 buffer 0 under flow mask + * @{ + */ +#define ATI2S_I2S_IRQM1__PP0_UF__SHIFT 8 +#define ATI2S_I2S_IRQM1__PP0_UF__WIDTH 1 +#define ATI2S_I2S_IRQM1__PP0_UF__MASK 0x00000100U +#define ATI2S_I2S_IRQM1__PP0_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define ATI2S_I2S_IRQM1__PP0_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define ATI2S_I2S_IRQM1__PP0_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define ATI2S_I2S_IRQM1__PP0_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define ATI2S_I2S_IRQM1__PP0_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define ATI2S_I2S_IRQM1__PP0_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define ATI2S_I2S_IRQM1__PP0_UF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp1_uf */ +/** + * @defgroup at_i2s_regs_core_pp1_uf_field pp1_uf_field + * @brief macros for field pp1_uf + * @details ping pong set 1 buffer 1 under flow mask + * @{ + */ +#define ATI2S_I2S_IRQM1__PP1_UF__SHIFT 9 +#define ATI2S_I2S_IRQM1__PP1_UF__WIDTH 1 +#define ATI2S_I2S_IRQM1__PP1_UF__MASK 0x00000200U +#define ATI2S_I2S_IRQM1__PP1_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define ATI2S_I2S_IRQM1__PP1_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define ATI2S_I2S_IRQM1__PP1_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define ATI2S_I2S_IRQM1__PP1_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define ATI2S_I2S_IRQM1__PP1_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define ATI2S_I2S_IRQM1__PP1_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define ATI2S_I2S_IRQM1__PP1_UF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp2_uf */ +/** + * @defgroup at_i2s_regs_core_pp2_uf_field pp2_uf_field + * @brief macros for field pp2_uf + * @details ping pong set 1 buffer 2 under flow mask + * @{ + */ +#define ATI2S_I2S_IRQM1__PP2_UF__SHIFT 10 +#define ATI2S_I2S_IRQM1__PP2_UF__WIDTH 1 +#define ATI2S_I2S_IRQM1__PP2_UF__MASK 0x00000400U +#define ATI2S_I2S_IRQM1__PP2_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define ATI2S_I2S_IRQM1__PP2_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define ATI2S_I2S_IRQM1__PP2_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define ATI2S_I2S_IRQM1__PP2_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define ATI2S_I2S_IRQM1__PP2_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define ATI2S_I2S_IRQM1__PP2_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define ATI2S_I2S_IRQM1__PP2_UF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp3_uf */ +/** + * @defgroup at_i2s_regs_core_pp3_uf_field pp3_uf_field + * @brief macros for field pp3_uf + * @details ping pong set 1 buffer 3 under flow mask + * @{ + */ +#define ATI2S_I2S_IRQM1__PP3_UF__SHIFT 11 +#define ATI2S_I2S_IRQM1__PP3_UF__WIDTH 1 +#define ATI2S_I2S_IRQM1__PP3_UF__MASK 0x00000800U +#define ATI2S_I2S_IRQM1__PP3_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define ATI2S_I2S_IRQM1__PP3_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define ATI2S_I2S_IRQM1__PP3_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define ATI2S_I2S_IRQM1__PP3_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define ATI2S_I2S_IRQM1__PP3_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define ATI2S_I2S_IRQM1__PP3_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define ATI2S_I2S_IRQM1__PP3_UF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pp_ep_thrshld */ +/** + * @defgroup at_i2s_regs_core_pp_ep_thrshld_field pp_ep_thrshld_field + * @brief macros for field pp_ep_thrshld + * @details ping pong buffer empty threshold hit mask + * @{ + */ +#define ATI2S_I2S_IRQM1__PP_EP_THRSHLD__SHIFT 12 +#define ATI2S_I2S_IRQM1__PP_EP_THRSHLD__WIDTH 1 +#define ATI2S_I2S_IRQM1__PP_EP_THRSHLD__MASK 0x00001000U +#define ATI2S_I2S_IRQM1__PP_EP_THRSHLD__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define ATI2S_I2S_IRQM1__PP_EP_THRSHLD__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define ATI2S_I2S_IRQM1__PP_EP_THRSHLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define ATI2S_I2S_IRQM1__PP_EP_THRSHLD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define ATI2S_I2S_IRQM1__PP_EP_THRSHLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define ATI2S_I2S_IRQM1__PP_EP_THRSHLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define ATI2S_I2S_IRQM1__PP_EP_THRSHLD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrp_dout_vld */ +/** + * @defgroup at_i2s_regs_core_intrp_dout_vld_field intrp_dout_vld_field + * @brief macros for field intrp_dout_vld + * @details interpolator data valid mask + * @{ + */ +#define ATI2S_I2S_IRQM1__INTRP_DOUT_VLD__SHIFT 13 +#define ATI2S_I2S_IRQM1__INTRP_DOUT_VLD__WIDTH 1 +#define ATI2S_I2S_IRQM1__INTRP_DOUT_VLD__MASK 0x00002000U +#define ATI2S_I2S_IRQM1__INTRP_DOUT_VLD__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define ATI2S_I2S_IRQM1__INTRP_DOUT_VLD__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define ATI2S_I2S_IRQM1__INTRP_DOUT_VLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define ATI2S_I2S_IRQM1__INTRP_DOUT_VLD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define ATI2S_I2S_IRQM1__INTRP_DOUT_VLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define ATI2S_I2S_IRQM1__INTRP_DOUT_VLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define ATI2S_I2S_IRQM1__INTRP_DOUT_VLD__RESET_VALUE 0x00000000U +/** @} */ +#define ATI2S_I2S_IRQM1__TYPE uint32_t +#define ATI2S_I2S_IRQM1__READ 0x00003fffU +#define ATI2S_I2S_IRQM1__WRITE 0x00003fffU +#define ATI2S_I2S_IRQM1__PRESERVED 0x00000000U +#define ATI2S_I2S_IRQM1__RESET_VALUE 0x00000fffU + +#endif /* __ATI2S_I2S_IRQM1_MACRO__ */ + +/** @} end of i2s_irqm1 */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_irqs1 */ +/** + * @defgroup at_i2s_regs_core_i2s_irqs1 i2s_irqs1 + * @brief Contains register fields associated with i2s_irqs1. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_IRQS1_MACRO__ +#define __ATI2S_I2S_IRQS1_MACRO__ + +/* macros for field pp0_fl */ +/** + * @defgroup at_i2s_regs_core_pp0_fl_field pp0_fl_field + * @brief macros for field pp0_fl + * @details ping pong set 1 buffer 0 full set + * @{ + */ +#define ATI2S_I2S_IRQS1__PP0_FL__SHIFT 0 +#define ATI2S_I2S_IRQS1__PP0_FL__WIDTH 1 +#define ATI2S_I2S_IRQS1__PP0_FL__MASK 0x00000001U +#define ATI2S_I2S_IRQS1__PP0_FL__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATI2S_I2S_IRQS1__PP0_FL__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define ATI2S_I2S_IRQS1__PP0_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATI2S_I2S_IRQS1__PP0_FL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define ATI2S_I2S_IRQS1__PP0_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATI2S_I2S_IRQS1__PP0_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATI2S_I2S_IRQS1__PP0_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp1_fl */ +/** + * @defgroup at_i2s_regs_core_pp1_fl_field pp1_fl_field + * @brief macros for field pp1_fl + * @details ping pong set 1 buffer 1 full set + * @{ + */ +#define ATI2S_I2S_IRQS1__PP1_FL__SHIFT 1 +#define ATI2S_I2S_IRQS1__PP1_FL__WIDTH 1 +#define ATI2S_I2S_IRQS1__PP1_FL__MASK 0x00000002U +#define ATI2S_I2S_IRQS1__PP1_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define ATI2S_I2S_IRQS1__PP1_FL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define ATI2S_I2S_IRQS1__PP1_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define ATI2S_I2S_IRQS1__PP1_FL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define ATI2S_I2S_IRQS1__PP1_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATI2S_I2S_IRQS1__PP1_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATI2S_I2S_IRQS1__PP1_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp2_fl */ +/** + * @defgroup at_i2s_regs_core_pp2_fl_field pp2_fl_field + * @brief macros for field pp2_fl + * @details ping pong set 1 buffer 2 full set + * @{ + */ +#define ATI2S_I2S_IRQS1__PP2_FL__SHIFT 2 +#define ATI2S_I2S_IRQS1__PP2_FL__WIDTH 1 +#define ATI2S_I2S_IRQS1__PP2_FL__MASK 0x00000004U +#define ATI2S_I2S_IRQS1__PP2_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define ATI2S_I2S_IRQS1__PP2_FL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define ATI2S_I2S_IRQS1__PP2_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define ATI2S_I2S_IRQS1__PP2_FL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define ATI2S_I2S_IRQS1__PP2_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define ATI2S_I2S_IRQS1__PP2_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define ATI2S_I2S_IRQS1__PP2_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp3_fl */ +/** + * @defgroup at_i2s_regs_core_pp3_fl_field pp3_fl_field + * @brief macros for field pp3_fl + * @details ping pong set 1 buffer 3 full set + * @{ + */ +#define ATI2S_I2S_IRQS1__PP3_FL__SHIFT 3 +#define ATI2S_I2S_IRQS1__PP3_FL__WIDTH 1 +#define ATI2S_I2S_IRQS1__PP3_FL__MASK 0x00000008U +#define ATI2S_I2S_IRQS1__PP3_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define ATI2S_I2S_IRQS1__PP3_FL__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define ATI2S_I2S_IRQS1__PP3_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define ATI2S_I2S_IRQS1__PP3_FL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define ATI2S_I2S_IRQS1__PP3_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define ATI2S_I2S_IRQS1__PP3_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define ATI2S_I2S_IRQS1__PP3_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp0_of */ +/** + * @defgroup at_i2s_regs_core_pp0_of_field pp0_of_field + * @brief macros for field pp0_of + * @details ping pong set 1 buffer 0 over flow set + * @{ + */ +#define ATI2S_I2S_IRQS1__PP0_OF__SHIFT 4 +#define ATI2S_I2S_IRQS1__PP0_OF__WIDTH 1 +#define ATI2S_I2S_IRQS1__PP0_OF__MASK 0x00000010U +#define ATI2S_I2S_IRQS1__PP0_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define ATI2S_I2S_IRQS1__PP0_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define ATI2S_I2S_IRQS1__PP0_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define ATI2S_I2S_IRQS1__PP0_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define ATI2S_I2S_IRQS1__PP0_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define ATI2S_I2S_IRQS1__PP0_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define ATI2S_I2S_IRQS1__PP0_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp1_of */ +/** + * @defgroup at_i2s_regs_core_pp1_of_field pp1_of_field + * @brief macros for field pp1_of + * @details ping pong set 1 buffer 1 over flow set + * @{ + */ +#define ATI2S_I2S_IRQS1__PP1_OF__SHIFT 5 +#define ATI2S_I2S_IRQS1__PP1_OF__WIDTH 1 +#define ATI2S_I2S_IRQS1__PP1_OF__MASK 0x00000020U +#define ATI2S_I2S_IRQS1__PP1_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define ATI2S_I2S_IRQS1__PP1_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define ATI2S_I2S_IRQS1__PP1_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define ATI2S_I2S_IRQS1__PP1_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define ATI2S_I2S_IRQS1__PP1_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define ATI2S_I2S_IRQS1__PP1_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define ATI2S_I2S_IRQS1__PP1_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp2_of */ +/** + * @defgroup at_i2s_regs_core_pp2_of_field pp2_of_field + * @brief macros for field pp2_of + * @details ping pong set 1 buffer 2 over flow set + * @{ + */ +#define ATI2S_I2S_IRQS1__PP2_OF__SHIFT 6 +#define ATI2S_I2S_IRQS1__PP2_OF__WIDTH 1 +#define ATI2S_I2S_IRQS1__PP2_OF__MASK 0x00000040U +#define ATI2S_I2S_IRQS1__PP2_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define ATI2S_I2S_IRQS1__PP2_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define ATI2S_I2S_IRQS1__PP2_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define ATI2S_I2S_IRQS1__PP2_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define ATI2S_I2S_IRQS1__PP2_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define ATI2S_I2S_IRQS1__PP2_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define ATI2S_I2S_IRQS1__PP2_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp3_of */ +/** + * @defgroup at_i2s_regs_core_pp3_of_field pp3_of_field + * @brief macros for field pp3_of + * @details ping pong set 1 buffer 3 over flow set + * @{ + */ +#define ATI2S_I2S_IRQS1__PP3_OF__SHIFT 7 +#define ATI2S_I2S_IRQS1__PP3_OF__WIDTH 1 +#define ATI2S_I2S_IRQS1__PP3_OF__MASK 0x00000080U +#define ATI2S_I2S_IRQS1__PP3_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define ATI2S_I2S_IRQS1__PP3_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define ATI2S_I2S_IRQS1__PP3_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define ATI2S_I2S_IRQS1__PP3_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define ATI2S_I2S_IRQS1__PP3_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define ATI2S_I2S_IRQS1__PP3_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define ATI2S_I2S_IRQS1__PP3_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp0_uf */ +/** + * @defgroup at_i2s_regs_core_pp0_uf_field pp0_uf_field + * @brief macros for field pp0_uf + * @details ping pong set 1 buffer 0 under flow set + * @{ + */ +#define ATI2S_I2S_IRQS1__PP0_UF__SHIFT 8 +#define ATI2S_I2S_IRQS1__PP0_UF__WIDTH 1 +#define ATI2S_I2S_IRQS1__PP0_UF__MASK 0x00000100U +#define ATI2S_I2S_IRQS1__PP0_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define ATI2S_I2S_IRQS1__PP0_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define ATI2S_I2S_IRQS1__PP0_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define ATI2S_I2S_IRQS1__PP0_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define ATI2S_I2S_IRQS1__PP0_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define ATI2S_I2S_IRQS1__PP0_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define ATI2S_I2S_IRQS1__PP0_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp1_uf */ +/** + * @defgroup at_i2s_regs_core_pp1_uf_field pp1_uf_field + * @brief macros for field pp1_uf + * @details ping pong set 1 buffer 1 under flow set + * @{ + */ +#define ATI2S_I2S_IRQS1__PP1_UF__SHIFT 9 +#define ATI2S_I2S_IRQS1__PP1_UF__WIDTH 1 +#define ATI2S_I2S_IRQS1__PP1_UF__MASK 0x00000200U +#define ATI2S_I2S_IRQS1__PP1_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define ATI2S_I2S_IRQS1__PP1_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define ATI2S_I2S_IRQS1__PP1_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define ATI2S_I2S_IRQS1__PP1_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define ATI2S_I2S_IRQS1__PP1_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define ATI2S_I2S_IRQS1__PP1_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define ATI2S_I2S_IRQS1__PP1_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp2_uf */ +/** + * @defgroup at_i2s_regs_core_pp2_uf_field pp2_uf_field + * @brief macros for field pp2_uf + * @details ping pong set 1 buffer 2 under flow set + * @{ + */ +#define ATI2S_I2S_IRQS1__PP2_UF__SHIFT 10 +#define ATI2S_I2S_IRQS1__PP2_UF__WIDTH 1 +#define ATI2S_I2S_IRQS1__PP2_UF__MASK 0x00000400U +#define ATI2S_I2S_IRQS1__PP2_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define ATI2S_I2S_IRQS1__PP2_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define ATI2S_I2S_IRQS1__PP2_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define ATI2S_I2S_IRQS1__PP2_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define ATI2S_I2S_IRQS1__PP2_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define ATI2S_I2S_IRQS1__PP2_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define ATI2S_I2S_IRQS1__PP2_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp3_uf */ +/** + * @defgroup at_i2s_regs_core_pp3_uf_field pp3_uf_field + * @brief macros for field pp3_uf + * @details ping pong set 1 buffer 3 under flow set + * @{ + */ +#define ATI2S_I2S_IRQS1__PP3_UF__SHIFT 11 +#define ATI2S_I2S_IRQS1__PP3_UF__WIDTH 1 +#define ATI2S_I2S_IRQS1__PP3_UF__MASK 0x00000800U +#define ATI2S_I2S_IRQS1__PP3_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define ATI2S_I2S_IRQS1__PP3_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define ATI2S_I2S_IRQS1__PP3_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define ATI2S_I2S_IRQS1__PP3_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define ATI2S_I2S_IRQS1__PP3_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define ATI2S_I2S_IRQS1__PP3_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define ATI2S_I2S_IRQS1__PP3_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp_ep_thrshld */ +/** + * @defgroup at_i2s_regs_core_pp_ep_thrshld_field pp_ep_thrshld_field + * @brief macros for field pp_ep_thrshld + * @details ping pong buffer empty threshold hit set + * @{ + */ +#define ATI2S_I2S_IRQS1__PP_EP_THRSHLD__SHIFT 12 +#define ATI2S_I2S_IRQS1__PP_EP_THRSHLD__WIDTH 1 +#define ATI2S_I2S_IRQS1__PP_EP_THRSHLD__MASK 0x00001000U +#define ATI2S_I2S_IRQS1__PP_EP_THRSHLD__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define ATI2S_I2S_IRQS1__PP_EP_THRSHLD__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define ATI2S_I2S_IRQS1__PP_EP_THRSHLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define ATI2S_I2S_IRQS1__PP_EP_THRSHLD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define ATI2S_I2S_IRQS1__PP_EP_THRSHLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define ATI2S_I2S_IRQS1__PP_EP_THRSHLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define ATI2S_I2S_IRQS1__PP_EP_THRSHLD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrp_dout_vld */ +/** + * @defgroup at_i2s_regs_core_intrp_dout_vld_field intrp_dout_vld_field + * @brief macros for field intrp_dout_vld + * @details interpolator data valid set + * @{ + */ +#define ATI2S_I2S_IRQS1__INTRP_DOUT_VLD__SHIFT 13 +#define ATI2S_I2S_IRQS1__INTRP_DOUT_VLD__WIDTH 1 +#define ATI2S_I2S_IRQS1__INTRP_DOUT_VLD__MASK 0x00002000U +#define ATI2S_I2S_IRQS1__INTRP_DOUT_VLD__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define ATI2S_I2S_IRQS1__INTRP_DOUT_VLD__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define ATI2S_I2S_IRQS1__INTRP_DOUT_VLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define ATI2S_I2S_IRQS1__INTRP_DOUT_VLD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define ATI2S_I2S_IRQS1__INTRP_DOUT_VLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define ATI2S_I2S_IRQS1__INTRP_DOUT_VLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define ATI2S_I2S_IRQS1__INTRP_DOUT_VLD__RESET_VALUE 0x00000000U +/** @} */ +#define ATI2S_I2S_IRQS1__TYPE uint32_t +#define ATI2S_I2S_IRQS1__READ 0x00003fffU +#define ATI2S_I2S_IRQS1__WRITE 0x00003fffU +#define ATI2S_I2S_IRQS1__PRESERVED 0x00000000U +#define ATI2S_I2S_IRQS1__RESET_VALUE 0x00000000U + +#endif /* __ATI2S_I2S_IRQS1_MACRO__ */ + +/** @} end of i2s_irqs1 */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_irqc1 */ +/** + * @defgroup at_i2s_regs_core_i2s_irqc1 i2s_irqc1 + * @brief Contains register fields associated with i2s_irqc1. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_IRQC1_MACRO__ +#define __ATI2S_I2S_IRQC1_MACRO__ + +/* macros for field pp0_fl */ +/** + * @defgroup at_i2s_regs_core_pp0_fl_field pp0_fl_field + * @brief macros for field pp0_fl + * @details ping pong set 1 buffer 0 full clear + * @{ + */ +#define ATI2S_I2S_IRQC1__PP0_FL__SHIFT 0 +#define ATI2S_I2S_IRQC1__PP0_FL__WIDTH 1 +#define ATI2S_I2S_IRQC1__PP0_FL__MASK 0x00000001U +#define ATI2S_I2S_IRQC1__PP0_FL__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATI2S_I2S_IRQC1__PP0_FL__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define ATI2S_I2S_IRQC1__PP0_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATI2S_I2S_IRQC1__PP0_FL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define ATI2S_I2S_IRQC1__PP0_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATI2S_I2S_IRQC1__PP0_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATI2S_I2S_IRQC1__PP0_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp1_fl */ +/** + * @defgroup at_i2s_regs_core_pp1_fl_field pp1_fl_field + * @brief macros for field pp1_fl + * @details ping pong set 1 buffer 1 full clear + * @{ + */ +#define ATI2S_I2S_IRQC1__PP1_FL__SHIFT 1 +#define ATI2S_I2S_IRQC1__PP1_FL__WIDTH 1 +#define ATI2S_I2S_IRQC1__PP1_FL__MASK 0x00000002U +#define ATI2S_I2S_IRQC1__PP1_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define ATI2S_I2S_IRQC1__PP1_FL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define ATI2S_I2S_IRQC1__PP1_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define ATI2S_I2S_IRQC1__PP1_FL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define ATI2S_I2S_IRQC1__PP1_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATI2S_I2S_IRQC1__PP1_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATI2S_I2S_IRQC1__PP1_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp2_fl */ +/** + * @defgroup at_i2s_regs_core_pp2_fl_field pp2_fl_field + * @brief macros for field pp2_fl + * @details ping pong set 1 buffer 2 full clear + * @{ + */ +#define ATI2S_I2S_IRQC1__PP2_FL__SHIFT 2 +#define ATI2S_I2S_IRQC1__PP2_FL__WIDTH 1 +#define ATI2S_I2S_IRQC1__PP2_FL__MASK 0x00000004U +#define ATI2S_I2S_IRQC1__PP2_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define ATI2S_I2S_IRQC1__PP2_FL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define ATI2S_I2S_IRQC1__PP2_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define ATI2S_I2S_IRQC1__PP2_FL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define ATI2S_I2S_IRQC1__PP2_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define ATI2S_I2S_IRQC1__PP2_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define ATI2S_I2S_IRQC1__PP2_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp3_fl */ +/** + * @defgroup at_i2s_regs_core_pp3_fl_field pp3_fl_field + * @brief macros for field pp3_fl + * @details ping pong set 1 buffer 3 full clear + * @{ + */ +#define ATI2S_I2S_IRQC1__PP3_FL__SHIFT 3 +#define ATI2S_I2S_IRQC1__PP3_FL__WIDTH 1 +#define ATI2S_I2S_IRQC1__PP3_FL__MASK 0x00000008U +#define ATI2S_I2S_IRQC1__PP3_FL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define ATI2S_I2S_IRQC1__PP3_FL__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define ATI2S_I2S_IRQC1__PP3_FL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define ATI2S_I2S_IRQC1__PP3_FL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define ATI2S_I2S_IRQC1__PP3_FL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define ATI2S_I2S_IRQC1__PP3_FL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define ATI2S_I2S_IRQC1__PP3_FL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp0_of */ +/** + * @defgroup at_i2s_regs_core_pp0_of_field pp0_of_field + * @brief macros for field pp0_of + * @details ping pong set 1 buffer 0 over flow clear + * @{ + */ +#define ATI2S_I2S_IRQC1__PP0_OF__SHIFT 4 +#define ATI2S_I2S_IRQC1__PP0_OF__WIDTH 1 +#define ATI2S_I2S_IRQC1__PP0_OF__MASK 0x00000010U +#define ATI2S_I2S_IRQC1__PP0_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define ATI2S_I2S_IRQC1__PP0_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define ATI2S_I2S_IRQC1__PP0_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define ATI2S_I2S_IRQC1__PP0_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define ATI2S_I2S_IRQC1__PP0_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define ATI2S_I2S_IRQC1__PP0_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define ATI2S_I2S_IRQC1__PP0_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp1_of */ +/** + * @defgroup at_i2s_regs_core_pp1_of_field pp1_of_field + * @brief macros for field pp1_of + * @details ping pong set 1 buffer 1 over flow clear + * @{ + */ +#define ATI2S_I2S_IRQC1__PP1_OF__SHIFT 5 +#define ATI2S_I2S_IRQC1__PP1_OF__WIDTH 1 +#define ATI2S_I2S_IRQC1__PP1_OF__MASK 0x00000020U +#define ATI2S_I2S_IRQC1__PP1_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define ATI2S_I2S_IRQC1__PP1_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define ATI2S_I2S_IRQC1__PP1_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define ATI2S_I2S_IRQC1__PP1_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define ATI2S_I2S_IRQC1__PP1_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define ATI2S_I2S_IRQC1__PP1_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define ATI2S_I2S_IRQC1__PP1_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp2_of */ +/** + * @defgroup at_i2s_regs_core_pp2_of_field pp2_of_field + * @brief macros for field pp2_of + * @details ping pong set 1 buffer 2 over flow clear + * @{ + */ +#define ATI2S_I2S_IRQC1__PP2_OF__SHIFT 6 +#define ATI2S_I2S_IRQC1__PP2_OF__WIDTH 1 +#define ATI2S_I2S_IRQC1__PP2_OF__MASK 0x00000040U +#define ATI2S_I2S_IRQC1__PP2_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define ATI2S_I2S_IRQC1__PP2_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define ATI2S_I2S_IRQC1__PP2_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define ATI2S_I2S_IRQC1__PP2_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define ATI2S_I2S_IRQC1__PP2_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define ATI2S_I2S_IRQC1__PP2_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define ATI2S_I2S_IRQC1__PP2_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp3_of */ +/** + * @defgroup at_i2s_regs_core_pp3_of_field pp3_of_field + * @brief macros for field pp3_of + * @details ping pong set 1 buffer 3 over flow clear + * @{ + */ +#define ATI2S_I2S_IRQC1__PP3_OF__SHIFT 7 +#define ATI2S_I2S_IRQC1__PP3_OF__WIDTH 1 +#define ATI2S_I2S_IRQC1__PP3_OF__MASK 0x00000080U +#define ATI2S_I2S_IRQC1__PP3_OF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define ATI2S_I2S_IRQC1__PP3_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define ATI2S_I2S_IRQC1__PP3_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define ATI2S_I2S_IRQC1__PP3_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define ATI2S_I2S_IRQC1__PP3_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define ATI2S_I2S_IRQC1__PP3_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define ATI2S_I2S_IRQC1__PP3_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp0_uf */ +/** + * @defgroup at_i2s_regs_core_pp0_uf_field pp0_uf_field + * @brief macros for field pp0_uf + * @details ping pong set 1 buffer 0 under flow clear + * @{ + */ +#define ATI2S_I2S_IRQC1__PP0_UF__SHIFT 8 +#define ATI2S_I2S_IRQC1__PP0_UF__WIDTH 1 +#define ATI2S_I2S_IRQC1__PP0_UF__MASK 0x00000100U +#define ATI2S_I2S_IRQC1__PP0_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define ATI2S_I2S_IRQC1__PP0_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define ATI2S_I2S_IRQC1__PP0_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define ATI2S_I2S_IRQC1__PP0_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define ATI2S_I2S_IRQC1__PP0_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define ATI2S_I2S_IRQC1__PP0_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define ATI2S_I2S_IRQC1__PP0_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp1_uf */ +/** + * @defgroup at_i2s_regs_core_pp1_uf_field pp1_uf_field + * @brief macros for field pp1_uf + * @details ping pong set 1 buffer 1 under flow clear + * @{ + */ +#define ATI2S_I2S_IRQC1__PP1_UF__SHIFT 9 +#define ATI2S_I2S_IRQC1__PP1_UF__WIDTH 1 +#define ATI2S_I2S_IRQC1__PP1_UF__MASK 0x00000200U +#define ATI2S_I2S_IRQC1__PP1_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define ATI2S_I2S_IRQC1__PP1_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define ATI2S_I2S_IRQC1__PP1_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define ATI2S_I2S_IRQC1__PP1_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define ATI2S_I2S_IRQC1__PP1_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define ATI2S_I2S_IRQC1__PP1_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define ATI2S_I2S_IRQC1__PP1_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp2_uf */ +/** + * @defgroup at_i2s_regs_core_pp2_uf_field pp2_uf_field + * @brief macros for field pp2_uf + * @details ping pong set 1 buffer 2 under flow clear + * @{ + */ +#define ATI2S_I2S_IRQC1__PP2_UF__SHIFT 10 +#define ATI2S_I2S_IRQC1__PP2_UF__WIDTH 1 +#define ATI2S_I2S_IRQC1__PP2_UF__MASK 0x00000400U +#define ATI2S_I2S_IRQC1__PP2_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define ATI2S_I2S_IRQC1__PP2_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define ATI2S_I2S_IRQC1__PP2_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define ATI2S_I2S_IRQC1__PP2_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define ATI2S_I2S_IRQC1__PP2_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define ATI2S_I2S_IRQC1__PP2_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define ATI2S_I2S_IRQC1__PP2_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp3_uf */ +/** + * @defgroup at_i2s_regs_core_pp3_uf_field pp3_uf_field + * @brief macros for field pp3_uf + * @details ping pong set 1 buffer 3 under flow clear + * @{ + */ +#define ATI2S_I2S_IRQC1__PP3_UF__SHIFT 11 +#define ATI2S_I2S_IRQC1__PP3_UF__WIDTH 1 +#define ATI2S_I2S_IRQC1__PP3_UF__MASK 0x00000800U +#define ATI2S_I2S_IRQC1__PP3_UF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define ATI2S_I2S_IRQC1__PP3_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define ATI2S_I2S_IRQC1__PP3_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define ATI2S_I2S_IRQC1__PP3_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define ATI2S_I2S_IRQC1__PP3_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define ATI2S_I2S_IRQC1__PP3_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define ATI2S_I2S_IRQC1__PP3_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pp_ep_thrshld */ +/** + * @defgroup at_i2s_regs_core_pp_ep_thrshld_field pp_ep_thrshld_field + * @brief macros for field pp_ep_thrshld + * @details ping pong buffer empty threshold hit clear + * @{ + */ +#define ATI2S_I2S_IRQC1__PP_EP_THRSHLD__SHIFT 12 +#define ATI2S_I2S_IRQC1__PP_EP_THRSHLD__WIDTH 1 +#define ATI2S_I2S_IRQC1__PP_EP_THRSHLD__MASK 0x00001000U +#define ATI2S_I2S_IRQC1__PP_EP_THRSHLD__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define ATI2S_I2S_IRQC1__PP_EP_THRSHLD__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define ATI2S_I2S_IRQC1__PP_EP_THRSHLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define ATI2S_I2S_IRQC1__PP_EP_THRSHLD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define ATI2S_I2S_IRQC1__PP_EP_THRSHLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define ATI2S_I2S_IRQC1__PP_EP_THRSHLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define ATI2S_I2S_IRQC1__PP_EP_THRSHLD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field intrp_dout_vld */ +/** + * @defgroup at_i2s_regs_core_intrp_dout_vld_field intrp_dout_vld_field + * @brief macros for field intrp_dout_vld + * @details interpolator data valid clear + * @{ + */ +#define ATI2S_I2S_IRQC1__INTRP_DOUT_VLD__SHIFT 13 +#define ATI2S_I2S_IRQC1__INTRP_DOUT_VLD__WIDTH 1 +#define ATI2S_I2S_IRQC1__INTRP_DOUT_VLD__MASK 0x00002000U +#define ATI2S_I2S_IRQC1__INTRP_DOUT_VLD__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define ATI2S_I2S_IRQC1__INTRP_DOUT_VLD__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define ATI2S_I2S_IRQC1__INTRP_DOUT_VLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define ATI2S_I2S_IRQC1__INTRP_DOUT_VLD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define ATI2S_I2S_IRQC1__INTRP_DOUT_VLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define ATI2S_I2S_IRQC1__INTRP_DOUT_VLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define ATI2S_I2S_IRQC1__INTRP_DOUT_VLD__RESET_VALUE 0x00000000U +/** @} */ +#define ATI2S_I2S_IRQC1__TYPE uint32_t +#define ATI2S_I2S_IRQC1__READ 0x00003fffU +#define ATI2S_I2S_IRQC1__WRITE 0x00003fffU +#define ATI2S_I2S_IRQC1__PRESERVED 0x00000000U +#define ATI2S_I2S_IRQC1__RESET_VALUE 0x00000000U + +#endif /* __ATI2S_I2S_IRQC1_MACRO__ */ + +/** @} end of i2s_irqc1 */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_buffer_depth */ +/** + * @defgroup at_i2s_regs_core_buffer_depth buffer_depth + * @brief Contains register fields associated with buffer_depth. definitions. + * @{ + */ +#ifndef __ATI2S_BUFFER_DEPTH_MACRO__ +#define __ATI2S_BUFFER_DEPTH_MACRO__ + +/* macros for field depth */ +/** + * @defgroup at_i2s_regs_core_depth_field depth_field + * @brief macros for field depth + * @details one buffer depth + * @{ + */ +#define ATI2S_BUFFER_DEPTH__DEPTH__SHIFT 0 +#define ATI2S_BUFFER_DEPTH__DEPTH__WIDTH 5 +#define ATI2S_BUFFER_DEPTH__DEPTH__MASK 0x0000001fU +#define ATI2S_BUFFER_DEPTH__DEPTH__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define ATI2S_BUFFER_DEPTH__DEPTH__RESET_VALUE 0x00000010U +/** @} */ +#define ATI2S_BUFFER_DEPTH__TYPE uint32_t +#define ATI2S_BUFFER_DEPTH__READ 0x0000001fU +#define ATI2S_BUFFER_DEPTH__PRESERVED 0x00000000U +#define ATI2S_BUFFER_DEPTH__RESET_VALUE 0x00000010U + +#endif /* __ATI2S_BUFFER_DEPTH_MACRO__ */ + +/** @} end of buffer_depth */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_pp_st */ +/** + * @defgroup at_i2s_regs_core_pp_st pp_st + * @brief Contains register fields associated with pp_st. definitions. + * @{ + */ +#ifndef __ATI2S_PP_ST_MACRO__ +#define __ATI2S_PP_ST_MACRO__ + +/* macros for field pp0_ep_cnt */ +/** + * @defgroup at_i2s_regs_core_pp0_ep_cnt_field pp0_ep_cnt_field + * @brief macros for field pp0_ep_cnt + * @details number of empty slot in ping poing set 0. + * @{ + */ +#define ATI2S_PP_ST__PP0_EP_CNT__SHIFT 0 +#define ATI2S_PP_ST__PP0_EP_CNT__WIDTH 6 +#define ATI2S_PP_ST__PP0_EP_CNT__MASK 0x0000003fU +#define ATI2S_PP_ST__PP0_EP_CNT__READ(src) ((uint32_t)(src) & 0x0000003fU) +#define ATI2S_PP_ST__PP0_EP_CNT__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field pp1_ep_cnt */ +/** + * @defgroup at_i2s_regs_core_pp1_ep_cnt_field pp1_ep_cnt_field + * @brief macros for field pp1_ep_cnt + * @details number of empty slot in ping poing set 1. + * @{ + */ +#define ATI2S_PP_ST__PP1_EP_CNT__SHIFT 8 +#define ATI2S_PP_ST__PP1_EP_CNT__WIDTH 6 +#define ATI2S_PP_ST__PP1_EP_CNT__MASK 0x00003f00U +#define ATI2S_PP_ST__PP1_EP_CNT__READ(src) \ + (((uint32_t)(src)\ + & 0x00003f00U) >> 8) +#define ATI2S_PP_ST__PP1_EP_CNT__RESET_VALUE 0x00000010U +/** @} */ +#define ATI2S_PP_ST__TYPE uint32_t +#define ATI2S_PP_ST__READ 0x00003f3fU +#define ATI2S_PP_ST__PRESERVED 0x00000000U +#define ATI2S_PP_ST__RESET_VALUE 0x00001010U + +#endif /* __ATI2S_PP_ST_MACRO__ */ + +/** @} end of pp_st */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_spare */ +/** + * @defgroup at_i2s_regs_core_i2s_spare i2s_spare + * @brief Contains register fields associated with i2s_spare. definitions. + * @{ + */ +#ifndef __ATI2S_I2S_SPARE_MACRO__ +#define __ATI2S_I2S_SPARE_MACRO__ + +/* macros for field val */ +/** + * @defgroup at_i2s_regs_core_val_field val_field + * @brief macros for field val + * @details spare bits + * @{ + */ +#define ATI2S_I2S_SPARE__VAL__SHIFT 0 +#define ATI2S_I2S_SPARE__VAL__WIDTH 32 +#define ATI2S_I2S_SPARE__VAL__MASK 0xffffffffU +#define ATI2S_I2S_SPARE__VAL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATI2S_I2S_SPARE__VAL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATI2S_I2S_SPARE__VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATI2S_I2S_SPARE__VAL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATI2S_I2S_SPARE__VAL__RESET_VALUE 0x00000000U +/** @} */ +#define ATI2S_I2S_SPARE__TYPE uint32_t +#define ATI2S_I2S_SPARE__READ 0xffffffffU +#define ATI2S_I2S_SPARE__WRITE 0xffffffffU +#define ATI2S_I2S_SPARE__PRESERVED 0x00000000U +#define ATI2S_I2S_SPARE__RESET_VALUE 0x00000000U + +#endif /* __ATI2S_I2S_SPARE_MACRO__ */ + +/** @} end of i2s_spare */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_i2s_dbg */ +/** + * @defgroup at_i2s_regs_core_i2s_dbg i2s_dbg + * @brief Expose debug signals on mdm_out definitions. + * @{ + */ +#ifndef __ATI2S_I2S_DBG_MACRO__ +#define __ATI2S_I2S_DBG_MACRO__ + +/* macros for field sel */ +/** + * @defgroup at_i2s_regs_core_sel_field sel_field + * @brief macros for field sel + * @details 0123456 + * @{ + */ +#define ATI2S_I2S_DBG__SEL__SHIFT 0 +#define ATI2S_I2S_DBG__SEL__WIDTH 6 +#define ATI2S_I2S_DBG__SEL__MASK 0x0000003fU +#define ATI2S_I2S_DBG__SEL__READ(src) ((uint32_t)(src) & 0x0000003fU) +#define ATI2S_I2S_DBG__SEL__WRITE(src) ((uint32_t)(src) & 0x0000003fU) +#define ATI2S_I2S_DBG__SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define ATI2S_I2S_DBG__SEL__VERIFY(src) (!(((uint32_t)(src) & ~0x0000003fU))) +#define ATI2S_I2S_DBG__SEL__RESET_VALUE 0x00000000U +/** @} */ +#define ATI2S_I2S_DBG__TYPE uint32_t +#define ATI2S_I2S_DBG__READ 0x0000003fU +#define ATI2S_I2S_DBG__WRITE 0x0000003fU +#define ATI2S_I2S_DBG__PRESERVED 0x00000000U +#define ATI2S_I2S_DBG__RESET_VALUE 0x00000000U + +#endif /* __ATI2S_I2S_DBG_MACRO__ */ + +/** @} end of i2s_dbg */ + +/* macros for BlueprintGlobalNameSpace::ATI2S_id */ +/** + * @defgroup at_i2s_regs_core_id id + * @brief Contains register fields associated with id. definitions. + * @{ + */ +#ifndef __ATI2S_ID_MACRO__ +#define __ATI2S_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_i2s_regs_core_id_field id_field + * @brief macros for field id + * @details 'I2S' in ASCII + * @{ + */ +#define ATI2S_ID__ID__SHIFT 0 +#define ATI2S_ID__ID__WIDTH 32 +#define ATI2S_ID__ID__MASK 0xffffffffU +#define ATI2S_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATI2S_ID__ID__RESET_VALUE 0x49325320U +/** @} */ +#define ATI2S_ID__TYPE uint32_t +#define ATI2S_ID__READ 0xffffffffU +#define ATI2S_ID__PRESERVED 0x00000000U +#define ATI2S_ID__RESET_VALUE 0x49325320U + +#endif /* __ATI2S_ID_MACRO__ */ + +/** @} end of id */ + +/** @} end of AT_I2S_REGS_CORE */ +#endif /* __REG_AT_I2S_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_lc_regs_core_macro.h b/ATM33xx-5/include/reg/at_lc_regs_core_macro.h new file mode 100644 index 0000000..fc39034 --- /dev/null +++ b/ATM33xx-5/include/reg/at_lc_regs_core_macro.h @@ -0,0 +1,8108 @@ +/* */ +/* File: at_lc_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic at_lc_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_AT_LC_REGS_CORE_H__ +#define __REG_AT_LC_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup AT_LC_REGS_CORE at_lc_regs_core + * @ingroup AT_REG + * @brief at_lc_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_ctrl0 */ +/** + * @defgroup at_lc_regs_core_lc_ctrl0 lc_ctrl0 + * @brief Contains register fields associated with lc_ctrl0. definitions. + * @{ + */ +#ifndef __ATLC_LC_CTRL0_MACRO__ +#define __ATLC_LC_CTRL0_MACRO__ + +/* macros for field at_lc_md */ +/** + * @defgroup at_lc_regs_core_at_lc_md_field at_lc_md_field + * @brief macros for field at_lc_md + * @details 1 = use atmosic lc, 0 = use ceva lc + * @{ + */ +#define ATLC_LC_CTRL0__AT_LC_MD__SHIFT 0 +#define ATLC_LC_CTRL0__AT_LC_MD__WIDTH 1 +#define ATLC_LC_CTRL0__AT_LC_MD__MASK 0x00000001U +#define ATLC_LC_CTRL0__AT_LC_MD__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATLC_LC_CTRL0__AT_LC_MD__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define ATLC_LC_CTRL0__AT_LC_MD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATLC_LC_CTRL0__AT_LC_MD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define ATLC_LC_CTRL0__AT_LC_MD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATLC_LC_CTRL0__AT_LC_MD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATLC_LC_CTRL0__AT_LC_MD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field op_md */ +/** + * @defgroup at_lc_regs_core_op_md_field op_md_field + * @brief macros for field op_md + * @details operation mode 1 = host, 0 = device + * @{ + */ +#define ATLC_LC_CTRL0__OP_MD__SHIFT 1 +#define ATLC_LC_CTRL0__OP_MD__WIDTH 1 +#define ATLC_LC_CTRL0__OP_MD__MASK 0x00000002U +#define ATLC_LC_CTRL0__OP_MD__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define ATLC_LC_CTRL0__OP_MD__WRITE(src) (((uint32_t)(src) << 1) & 0x00000002U) +#define ATLC_LC_CTRL0__OP_MD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define ATLC_LC_CTRL0__OP_MD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define ATLC_LC_CTRL0__OP_MD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATLC_LC_CTRL0__OP_MD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATLC_LC_CTRL0__OP_MD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field flw_md */ +/** + * @defgroup at_lc_regs_core_flw_md_field flw_md_field + * @brief macros for field flw_md + * @details flow cmode 1 = tcp, 0 = udp + * @{ + */ +#define ATLC_LC_CTRL0__FLW_MD__SHIFT 2 +#define ATLC_LC_CTRL0__FLW_MD__WIDTH 1 +#define ATLC_LC_CTRL0__FLW_MD__MASK 0x00000004U +#define ATLC_LC_CTRL0__FLW_MD__READ(src) (((uint32_t)(src) & 0x00000004U) >> 2) +#define ATLC_LC_CTRL0__FLW_MD__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define ATLC_LC_CTRL0__FLW_MD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define ATLC_LC_CTRL0__FLW_MD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define ATLC_LC_CTRL0__FLW_MD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define ATLC_LC_CTRL0__FLW_MD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define ATLC_LC_CTRL0__FLW_MD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pwr_dn */ +/** + * @defgroup at_lc_regs_core_pwr_dn_field pwr_dn_field + * @brief macros for field pwr_dn + * @details power down + * @{ + */ +#define ATLC_LC_CTRL0__PWR_DN__SHIFT 3 +#define ATLC_LC_CTRL0__PWR_DN__WIDTH 1 +#define ATLC_LC_CTRL0__PWR_DN__MASK 0x00000008U +#define ATLC_LC_CTRL0__PWR_DN__READ(src) (((uint32_t)(src) & 0x00000008U) >> 3) +#define ATLC_LC_CTRL0__PWR_DN__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define ATLC_LC_CTRL0__PWR_DN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define ATLC_LC_CTRL0__PWR_DN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define ATLC_LC_CTRL0__PWR_DN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define ATLC_LC_CTRL0__PWR_DN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define ATLC_LC_CTRL0__PWR_DN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rsrvd */ +/** + * @defgroup at_lc_regs_core_rsrvd_field rsrvd_field + * @brief macros for field rsrvd + * @details reserverd + * @{ + */ +#define ATLC_LC_CTRL0__RSRVD__SHIFT 4 +#define ATLC_LC_CTRL0__RSRVD__WIDTH 2 +#define ATLC_LC_CTRL0__RSRVD__MASK 0x00000030U +#define ATLC_LC_CTRL0__RSRVD__READ(src) (((uint32_t)(src) & 0x00000030U) >> 4) +#define ATLC_LC_CTRL0__RSRVD__WRITE(src) (((uint32_t)(src) << 4) & 0x00000030U) +#define ATLC_LC_CTRL0__RSRVD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((uint32_t)(src) <<\ + 4) & 0x00000030U) +#define ATLC_LC_CTRL0__RSRVD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000030U))) +#define ATLC_LC_CTRL0__RSRVD__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field aa_en */ +/** + * @defgroup at_lc_regs_core_aa_en_field aa_en_field + * @brief macros for field aa_en + * @details enable autoacknowledgment + * @{ + */ +#define ATLC_LC_CTRL0__AA_EN__SHIFT 6 +#define ATLC_LC_CTRL0__AA_EN__WIDTH 1 +#define ATLC_LC_CTRL0__AA_EN__MASK 0x00000040U +#define ATLC_LC_CTRL0__AA_EN__READ(src) (((uint32_t)(src) & 0x00000040U) >> 6) +#define ATLC_LC_CTRL0__AA_EN__WRITE(src) (((uint32_t)(src) << 6) & 0x00000040U) +#define ATLC_LC_CTRL0__AA_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define ATLC_LC_CTRL0__AA_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define ATLC_LC_CTRL0__AA_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define ATLC_LC_CTRL0__AA_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define ATLC_LC_CTRL0__AA_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field rt_en */ +/** + * @defgroup at_lc_regs_core_rt_en_field rt_en_field + * @brief macros for field rt_en + * @details enable retransmission + * @{ + */ +#define ATLC_LC_CTRL0__RT_EN__SHIFT 7 +#define ATLC_LC_CTRL0__RT_EN__WIDTH 1 +#define ATLC_LC_CTRL0__RT_EN__MASK 0x00000080U +#define ATLC_LC_CTRL0__RT_EN__READ(src) (((uint32_t)(src) & 0x00000080U) >> 7) +#define ATLC_LC_CTRL0__RT_EN__WRITE(src) (((uint32_t)(src) << 7) & 0x00000080U) +#define ATLC_LC_CTRL0__RT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define ATLC_LC_CTRL0__RT_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define ATLC_LC_CTRL0__RT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define ATLC_LC_CTRL0__RT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define ATLC_LC_CTRL0__RT_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field wht_en */ +/** + * @defgroup at_lc_regs_core_wht_en_field wht_en_field + * @brief macros for field wht_en + * @details enable whitenning + * @{ + */ +#define ATLC_LC_CTRL0__WHT_EN__SHIFT 8 +#define ATLC_LC_CTRL0__WHT_EN__WIDTH 1 +#define ATLC_LC_CTRL0__WHT_EN__MASK 0x00000100U +#define ATLC_LC_CTRL0__WHT_EN__READ(src) (((uint32_t)(src) & 0x00000100U) >> 8) +#define ATLC_LC_CTRL0__WHT_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define ATLC_LC_CTRL0__WHT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define ATLC_LC_CTRL0__WHT_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define ATLC_LC_CTRL0__WHT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define ATLC_LC_CTRL0__WHT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define ATLC_LC_CTRL0__WHT_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field crypt_md */ +/** + * @defgroup at_lc_regs_core_crypt_md_field crypt_md_field + * @brief macros for field crypt_md + * @details crypto mode 000 = no crypto, 001 = ECB, 010 = CBC, 001 = CFG, OFB = 100, 101 = CTR + * @{ + */ +#define ATLC_LC_CTRL0__CRYPT_MD__SHIFT 9 +#define ATLC_LC_CTRL0__CRYPT_MD__WIDTH 3 +#define ATLC_LC_CTRL0__CRYPT_MD__MASK 0x00000e00U +#define ATLC_LC_CTRL0__CRYPT_MD__READ(src) \ + (((uint32_t)(src)\ + & 0x00000e00U) >> 9) +#define ATLC_LC_CTRL0__CRYPT_MD__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000e00U) +#define ATLC_LC_CTRL0__CRYPT_MD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((uint32_t)(src) <<\ + 9) & 0x00000e00U) +#define ATLC_LC_CTRL0__CRYPT_MD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000e00U))) +#define ATLC_LC_CTRL0__CRYPT_MD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sync_en */ +/** + * @defgroup at_lc_regs_core_sync_en_field sync_en_field + * @brief macros for field sync_en + * @details enable sync word 0 and/or sync word 1 + * @{ + */ +#define ATLC_LC_CTRL0__SYNC_EN__SHIFT 12 +#define ATLC_LC_CTRL0__SYNC_EN__WIDTH 2 +#define ATLC_LC_CTRL0__SYNC_EN__MASK 0x00003000U +#define ATLC_LC_CTRL0__SYNC_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00003000U) >> 12) +#define ATLC_LC_CTRL0__SYNC_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00003000U) +#define ATLC_LC_CTRL0__SYNC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((uint32_t)(src) <<\ + 12) & 0x00003000U) +#define ATLC_LC_CTRL0__SYNC_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00003000U))) +#define ATLC_LC_CTRL0__SYNC_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field crc_len */ +/** + * @defgroup at_lc_regs_core_crc_len_field crc_len_field + * @brief macros for field crc_len + * @details crc length in bytes - valid between 0 and 4 + * @{ + */ +#define ATLC_LC_CTRL0__CRC_LEN__SHIFT 16 +#define ATLC_LC_CTRL0__CRC_LEN__WIDTH 3 +#define ATLC_LC_CTRL0__CRC_LEN__MASK 0x00070000U +#define ATLC_LC_CTRL0__CRC_LEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00070000U) >> 16) +#define ATLC_LC_CTRL0__CRC_LEN__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00070000U) +#define ATLC_LC_CTRL0__CRC_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((uint32_t)(src) <<\ + 16) & 0x00070000U) +#define ATLC_LC_CTRL0__CRC_LEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00070000U))) +#define ATLC_LC_CTRL0__CRC_LEN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field addr_len */ +/** + * @defgroup at_lc_regs_core_addr_len_field addr_len_field + * @brief macros for field addr_len + * @details address length in bytes - valid between 0 and 1 + * @{ + */ +#define ATLC_LC_CTRL0__ADDR_LEN__SHIFT 20 +#define ATLC_LC_CTRL0__ADDR_LEN__WIDTH 3 +#define ATLC_LC_CTRL0__ADDR_LEN__MASK 0x00700000U +#define ATLC_LC_CTRL0__ADDR_LEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00700000U) >> 20) +#define ATLC_LC_CTRL0__ADDR_LEN__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00700000U) +#define ATLC_LC_CTRL0__ADDR_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((uint32_t)(src) <<\ + 20) & 0x00700000U) +#define ATLC_LC_CTRL0__ADDR_LEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00700000U))) +#define ATLC_LC_CTRL0__ADDR_LEN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field sync_len */ +/** + * @defgroup at_lc_regs_core_sync_len_field sync_len_field + * @brief macros for field sync_len + * @details sync word length in bytes - valid between 1 and 4 + * @{ + */ +#define ATLC_LC_CTRL0__SYNC_LEN__SHIFT 24 +#define ATLC_LC_CTRL0__SYNC_LEN__WIDTH 3 +#define ATLC_LC_CTRL0__SYNC_LEN__MASK 0x07000000U +#define ATLC_LC_CTRL0__SYNC_LEN__READ(src) \ + (((uint32_t)(src)\ + & 0x07000000U) >> 24) +#define ATLC_LC_CTRL0__SYNC_LEN__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x07000000U) +#define ATLC_LC_CTRL0__SYNC_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((uint32_t)(src) <<\ + 24) & 0x07000000U) +#define ATLC_LC_CTRL0__SYNC_LEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x07000000U))) +#define ATLC_LC_CTRL0__SYNC_LEN__RESET_VALUE 0x00000004U +/** @} */ +#define ATLC_LC_CTRL0__TYPE uint32_t +#define ATLC_LC_CTRL0__READ 0x07773fffU +#define ATLC_LC_CTRL0__WRITE 0x07773fffU +#define ATLC_LC_CTRL0__PRESERVED 0x00000000U +#define ATLC_LC_CTRL0__RESET_VALUE 0x041111d0U + +#endif /* __ATLC_LC_CTRL0_MACRO__ */ + +/** @} end of lc_ctrl0 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_ctrl1 */ +/** + * @defgroup at_lc_regs_core_lc_ctrl1 lc_ctrl1 + * @brief Contains register fields associated with lc_ctrl1. definitions. + * @{ + */ +#ifndef __ATLC_LC_CTRL1_MACRO__ +#define __ATLC_LC_CTRL1_MACRO__ + +/* macros for field pyld_len */ +/** + * @defgroup at_lc_regs_core_pyld_len_field pyld_len_field + * @brief macros for field pyld_len + * @details payload length in bytes used in UDP mode, ignored in TCP mode since it is specified in header + * @{ + */ +#define ATLC_LC_CTRL1__PYLD_LEN__SHIFT 0 +#define ATLC_LC_CTRL1__PYLD_LEN__WIDTH 8 +#define ATLC_LC_CTRL1__PYLD_LEN__MASK 0x000000ffU +#define ATLC_LC_CTRL1__PYLD_LEN__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_LC_CTRL1__PYLD_LEN__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_LC_CTRL1__PYLD_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define ATLC_LC_CTRL1__PYLD_LEN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define ATLC_LC_CTRL1__PYLD_LEN__RESET_VALUE 0x00000020U +/** @} */ + +/* macros for field pyld_len_wdth */ +/** + * @defgroup at_lc_regs_core_pyld_len_wdth_field pyld_len_wdth_field + * @brief macros for field pyld_len_wdth + * @details width of payload length field in the header used in TCP mode [6-8] + * @{ + */ +#define ATLC_LC_CTRL1__PYLD_LEN_WDTH__SHIFT 8 +#define ATLC_LC_CTRL1__PYLD_LEN_WDTH__WIDTH 4 +#define ATLC_LC_CTRL1__PYLD_LEN_WDTH__MASK 0x00000f00U +#define ATLC_LC_CTRL1__PYLD_LEN_WDTH__READ(src) \ + (((uint32_t)(src)\ + & 0x00000f00U) >> 8) +#define ATLC_LC_CTRL1__PYLD_LEN_WDTH__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000f00U) +#define ATLC_LC_CTRL1__PYLD_LEN_WDTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((uint32_t)(src) <<\ + 8) & 0x00000f00U) +#define ATLC_LC_CTRL1__PYLD_LEN_WDTH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000f00U))) +#define ATLC_LC_CTRL1__PYLD_LEN_WDTH__RESET_VALUE 0x00000006U +/** @} */ +#define ATLC_LC_CTRL1__TYPE uint32_t +#define ATLC_LC_CTRL1__READ 0x00000fffU +#define ATLC_LC_CTRL1__WRITE 0x00000fffU +#define ATLC_LC_CTRL1__PRESERVED 0x00000000U +#define ATLC_LC_CTRL1__RESET_VALUE 0x00000620U + +#endif /* __ATLC_LC_CTRL1_MACRO__ */ + +/** @} end of lc_ctrl1 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_ctrl2 */ +/** + * @defgroup at_lc_regs_core_lc_ctrl2 lc_ctrl2 + * @brief Contains register fields associated with lc_ctrl2. definitions. + * @{ + */ +#ifndef __ATLC_LC_CTRL2_MACRO__ +#define __ATLC_LC_CTRL2_MACRO__ + +/* macros for field rx_to */ +/** + * @defgroup at_lc_regs_core_rx_to_field rx_to_field + * @brief macros for field rx_to + * @details receive window timeout in micro seconds + * @{ + */ +#define ATLC_LC_CTRL2__RX_TO__SHIFT 0 +#define ATLC_LC_CTRL2__RX_TO__WIDTH 16 +#define ATLC_LC_CTRL2__RX_TO__MASK 0x0000ffffU +#define ATLC_LC_CTRL2__RX_TO__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_LC_CTRL2__RX_TO__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_LC_CTRL2__RX_TO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_LC_CTRL2__RX_TO__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_LC_CTRL2__RX_TO__RESET_VALUE 0x000000c8U +/** @} */ + +/* macros for field tx_ack_to */ +/** + * @defgroup at_lc_regs_core_tx_ack_to_field tx_ack_to_field + * @brief macros for field tx_ack_to + * @details tx acknowledgment timeout in micro seconds + * @{ + */ +#define ATLC_LC_CTRL2__TX_ACK_TO__SHIFT 16 +#define ATLC_LC_CTRL2__TX_ACK_TO__WIDTH 16 +#define ATLC_LC_CTRL2__TX_ACK_TO__MASK 0xffff0000U +#define ATLC_LC_CTRL2__TX_ACK_TO__READ(src) \ + (((uint32_t)(src)\ + & 0xffff0000U) >> 16) +#define ATLC_LC_CTRL2__TX_ACK_TO__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0xffff0000U) +#define ATLC_LC_CTRL2__TX_ACK_TO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define ATLC_LC_CTRL2__TX_ACK_TO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define ATLC_LC_CTRL2__TX_ACK_TO__RESET_VALUE 0x000000c8U +/** @} */ +#define ATLC_LC_CTRL2__TYPE uint32_t +#define ATLC_LC_CTRL2__READ 0xffffffffU +#define ATLC_LC_CTRL2__WRITE 0xffffffffU +#define ATLC_LC_CTRL2__PRESERVED 0x00000000U +#define ATLC_LC_CTRL2__RESET_VALUE 0x00c800c8U + +#endif /* __ATLC_LC_CTRL2_MACRO__ */ + +/** @} end of lc_ctrl2 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_ctrl3 */ +/** + * @defgroup at_lc_regs_core_lc_ctrl3 lc_ctrl3 + * @brief Contains register fields associated with lc_ctrl3. definitions. + * @{ + */ +#ifndef __ATLC_LC_CTRL3_MACRO__ +#define __ATLC_LC_CTRL3_MACRO__ + +/* macros for field artd */ +/** + * @defgroup at_lc_regs_core_artd_field artd_field + * @brief macros for field artd + * @details auto retransmit delay = 250 us * (artd + 1) + * @{ + */ +#define ATLC_LC_CTRL3__ARTD__SHIFT 0 +#define ATLC_LC_CTRL3__ARTD__WIDTH 4 +#define ATLC_LC_CTRL3__ARTD__MASK 0x0000000fU +#define ATLC_LC_CTRL3__ARTD__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define ATLC_LC_CTRL3__ARTD__WRITE(src) ((uint32_t)(src) & 0x0000000fU) +#define ATLC_LC_CTRL3__ARTD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define ATLC_LC_CTRL3__ARTD__VERIFY(src) (!(((uint32_t)(src) & ~0x0000000fU))) +#define ATLC_LC_CTRL3__ARTD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field artmx */ +/** + * @defgroup at_lc_regs_core_artmx_field artmx_field + * @brief macros for field artmx + * @details auto retransmit count for maximum number of retransmit + * @{ + */ +#define ATLC_LC_CTRL3__ARTMX__SHIFT 4 +#define ATLC_LC_CTRL3__ARTMX__WIDTH 4 +#define ATLC_LC_CTRL3__ARTMX__MASK 0x000000f0U +#define ATLC_LC_CTRL3__ARTMX__READ(src) (((uint32_t)(src) & 0x000000f0U) >> 4) +#define ATLC_LC_CTRL3__ARTMX__WRITE(src) (((uint32_t)(src) << 4) & 0x000000f0U) +#define ATLC_LC_CTRL3__ARTMX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define ATLC_LC_CTRL3__ARTMX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define ATLC_LC_CTRL3__ARTMX__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_LC_CTRL3__TYPE uint32_t +#define ATLC_LC_CTRL3__READ 0x000000ffU +#define ATLC_LC_CTRL3__WRITE 0x000000ffU +#define ATLC_LC_CTRL3__PRESERVED 0x00000000U +#define ATLC_LC_CTRL3__RESET_VALUE 0x00000000U + +#endif /* __ATLC_LC_CTRL3_MACRO__ */ + +/** @} end of lc_ctrl3 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_ctrl4 */ +/** + * @defgroup at_lc_regs_core_lc_ctrl4 lc_ctrl4 + * @brief Contains register fields associated with lc_ctrl4. definitions. + * @{ + */ +#ifndef __ATLC_LC_CTRL4_MACRO__ +#define __ATLC_LC_CTRL4_MACRO__ + +/* macros for field chnl_hp_en */ +/** + * @defgroup at_lc_regs_core_chnl_hp_en_field chnl_hp_en_field + * @brief macros for field chnl_hp_en + * @details enable auto channel hopping + * @{ + */ +#define ATLC_LC_CTRL4__CHNL_HP_EN__SHIFT 0 +#define ATLC_LC_CTRL4__CHNL_HP_EN__WIDTH 1 +#define ATLC_LC_CTRL4__CHNL_HP_EN__MASK 0x00000001U +#define ATLC_LC_CTRL4__CHNL_HP_EN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATLC_LC_CTRL4__CHNL_HP_EN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define ATLC_LC_CTRL4__CHNL_HP_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATLC_LC_CTRL4__CHNL_HP_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define ATLC_LC_CTRL4__CHNL_HP_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATLC_LC_CTRL4__CHNL_HP_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATLC_LC_CTRL4__CHNL_HP_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field chnl_idx */ +/** + * @defgroup at_lc_regs_core_chnl_idx_field chnl_idx_field + * @brief macros for field chnl_idx + * @details F = 2370 + chnl_idx MHz + * @{ + */ +#define ATLC_LC_CTRL4__CHNL_IDX__SHIFT 8 +#define ATLC_LC_CTRL4__CHNL_IDX__WIDTH 7 +#define ATLC_LC_CTRL4__CHNL_IDX__MASK 0x00007f00U +#define ATLC_LC_CTRL4__CHNL_IDX__READ(src) \ + (((uint32_t)(src)\ + & 0x00007f00U) >> 8) +#define ATLC_LC_CTRL4__CHNL_IDX__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00007f00U) +#define ATLC_LC_CTRL4__CHNL_IDX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007f00U) | (((uint32_t)(src) <<\ + 8) & 0x00007f00U) +#define ATLC_LC_CTRL4__CHNL_IDX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00007f00U))) +#define ATLC_LC_CTRL4__CHNL_IDX__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field tx_pwr */ +/** + * @defgroup at_lc_regs_core_tx_pwr_field tx_pwr_field + * @brief macros for field tx_pwr + * @details tx power pass directly to radio + * @{ + */ +#define ATLC_LC_CTRL4__TX_PWR__SHIFT 16 +#define ATLC_LC_CTRL4__TX_PWR__WIDTH 4 +#define ATLC_LC_CTRL4__TX_PWR__MASK 0x000f0000U +#define ATLC_LC_CTRL4__TX_PWR__READ(src) \ + (((uint32_t)(src)\ + & 0x000f0000U) >> 16) +#define ATLC_LC_CTRL4__TX_PWR__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x000f0000U) +#define ATLC_LC_CTRL4__TX_PWR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((uint32_t)(src) <<\ + 16) & 0x000f0000U) +#define ATLC_LC_CTRL4__TX_PWR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x000f0000U))) +#define ATLC_LC_CTRL4__TX_PWR__RESET_VALUE 0x00000001U +/** @} */ +#define ATLC_LC_CTRL4__TYPE uint32_t +#define ATLC_LC_CTRL4__READ 0x000f7f01U +#define ATLC_LC_CTRL4__WRITE 0x000f7f01U +#define ATLC_LC_CTRL4__PRESERVED 0x00000000U +#define ATLC_LC_CTRL4__RESET_VALUE 0x00010100U + +#endif /* __ATLC_LC_CTRL4_MACRO__ */ + +/** @} end of lc_ctrl4 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_ctrl5 */ +/** + * @defgroup at_lc_regs_core_lc_ctrl5 lc_ctrl5 + * @brief Contains register fields associated with lc_ctrl5. definitions. + * @{ + */ +#ifndef __ATLC_LC_CTRL5_MACRO__ +#define __ATLC_LC_CTRL5_MACRO__ + +/* macros for field endianness */ +/** + * @defgroup at_lc_regs_core_endianness_field endianness_field + * @brief macros for field endianness + * @details 0 = lsb of each byte LSB is transmitted first, 1 = msb of each byte MSB is transmitted first + * @{ + */ +#define ATLC_LC_CTRL5__ENDIANNESS__SHIFT 0 +#define ATLC_LC_CTRL5__ENDIANNESS__WIDTH 1 +#define ATLC_LC_CTRL5__ENDIANNESS__MASK 0x00000001U +#define ATLC_LC_CTRL5__ENDIANNESS__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATLC_LC_CTRL5__ENDIANNESS__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define ATLC_LC_CTRL5__ENDIANNESS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATLC_LC_CTRL5__ENDIANNESS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define ATLC_LC_CTRL5__ENDIANNESS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATLC_LC_CTRL5__ENDIANNESS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATLC_LC_CTRL5__ENDIANNESS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sync_wrd_sel */ +/** + * @defgroup at_lc_regs_core_sync_wrd_sel_field sync_wrd_sel_field + * @brief macros for field sync_wrd_sel + * @details 0 = use sync word 0, 1 = use sync word 1 used in UDP mode, ignored in TCP mode since it is specified in header + * @{ + */ +#define ATLC_LC_CTRL5__SYNC_WRD_SEL__SHIFT 1 +#define ATLC_LC_CTRL5__SYNC_WRD_SEL__WIDTH 1 +#define ATLC_LC_CTRL5__SYNC_WRD_SEL__MASK 0x00000002U +#define ATLC_LC_CTRL5__SYNC_WRD_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define ATLC_LC_CTRL5__SYNC_WRD_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define ATLC_LC_CTRL5__SYNC_WRD_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define ATLC_LC_CTRL5__SYNC_WRD_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define ATLC_LC_CTRL5__SYNC_WRD_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATLC_LC_CTRL5__SYNC_WRD_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATLC_LC_CTRL5__SYNC_WRD_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nd_rx */ +/** + * @defgroup at_lc_regs_core_nd_rx_field nd_rx_field + * @brief macros for field nd_rx + * @details node index when address length == 0 + * @{ + */ +#define ATLC_LC_CTRL5__ND_RX__SHIFT 4 +#define ATLC_LC_CTRL5__ND_RX__WIDTH 3 +#define ATLC_LC_CTRL5__ND_RX__MASK 0x00000070U +#define ATLC_LC_CTRL5__ND_RX__READ(src) (((uint32_t)(src) & 0x00000070U) >> 4) +#define ATLC_LC_CTRL5__ND_RX__WRITE(src) (((uint32_t)(src) << 4) & 0x00000070U) +#define ATLC_LC_CTRL5__ND_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((uint32_t)(src) <<\ + 4) & 0x00000070U) +#define ATLC_LC_CTRL5__ND_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000070U))) +#define ATLC_LC_CTRL5__ND_RX__RESET_VALUE 0x00000001U +/** @} */ +#define ATLC_LC_CTRL5__TYPE uint32_t +#define ATLC_LC_CTRL5__READ 0x00000073U +#define ATLC_LC_CTRL5__WRITE 0x00000073U +#define ATLC_LC_CTRL5__PRESERVED 0x00000000U +#define ATLC_LC_CTRL5__RESET_VALUE 0x00000010U + +#endif /* __ATLC_LC_CTRL5_MACRO__ */ + +/** @} end of lc_ctrl5 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_ctrl6 */ +/** + * @defgroup at_lc_regs_core_lc_ctrl6 lc_ctrl6 + * @brief Contains register fields associated with lc_ctrl6. definitions. + * @{ + */ +#ifndef __ATLC_LC_CTRL6_MACRO__ +#define __ATLC_LC_CTRL6_MACRO__ + +/* macros for field clken */ +/** + * @defgroup at_lc_regs_core_clken_field clken_field + * @brief macros for field clken + * @details overwrite the hw controlled clken + * @{ + */ +#define ATLC_LC_CTRL6__CLKEN__SHIFT 0 +#define ATLC_LC_CTRL6__CLKEN__WIDTH 1 +#define ATLC_LC_CTRL6__CLKEN__MASK 0x00000001U +#define ATLC_LC_CTRL6__CLKEN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATLC_LC_CTRL6__CLKEN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define ATLC_LC_CTRL6__CLKEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATLC_LC_CTRL6__CLKEN__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define ATLC_LC_CTRL6__CLKEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATLC_LC_CTRL6__CLKEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATLC_LC_CTRL6__CLKEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field crypt_gclken */ +/** + * @defgroup at_lc_regs_core_crypt_gclken_field crypt_gclken_field + * @brief macros for field crypt_gclken + * @details overwrite the hw controlled crypt_gclken + * @{ + */ +#define ATLC_LC_CTRL6__CRYPT_GCLKEN__SHIFT 1 +#define ATLC_LC_CTRL6__CRYPT_GCLKEN__WIDTH 1 +#define ATLC_LC_CTRL6__CRYPT_GCLKEN__MASK 0x00000002U +#define ATLC_LC_CTRL6__CRYPT_GCLKEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define ATLC_LC_CTRL6__CRYPT_GCLKEN__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define ATLC_LC_CTRL6__CRYPT_GCLKEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define ATLC_LC_CTRL6__CRYPT_GCLKEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define ATLC_LC_CTRL6__CRYPT_GCLKEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATLC_LC_CTRL6__CRYPT_GCLKEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATLC_LC_CTRL6__CRYPT_GCLKEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hgclken */ +/** + * @defgroup at_lc_regs_core_hgclken_field hgclken_field + * @brief macros for field hgclken + * @details overwrite the hw controlled hgclken + * @{ + */ +#define ATLC_LC_CTRL6__HGCLKEN__SHIFT 2 +#define ATLC_LC_CTRL6__HGCLKEN__WIDTH 1 +#define ATLC_LC_CTRL6__HGCLKEN__MASK 0x00000004U +#define ATLC_LC_CTRL6__HGCLKEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define ATLC_LC_CTRL6__HGCLKEN__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define ATLC_LC_CTRL6__HGCLKEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define ATLC_LC_CTRL6__HGCLKEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define ATLC_LC_CTRL6__HGCLKEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define ATLC_LC_CTRL6__HGCLKEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define ATLC_LC_CTRL6__HGCLKEN__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_LC_CTRL6__TYPE uint32_t +#define ATLC_LC_CTRL6__READ 0x00000007U +#define ATLC_LC_CTRL6__WRITE 0x00000007U +#define ATLC_LC_CTRL6__PRESERVED 0x00000000U +#define ATLC_LC_CTRL6__RESET_VALUE 0x00000000U + +#endif /* __ATLC_LC_CTRL6_MACRO__ */ + +/** @} end of lc_ctrl6 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_ctrl7 */ +/** + * @defgroup at_lc_regs_core_lc_ctrl7 lc_ctrl7 + * @brief Contains register fields associated with lc_ctrl7. definitions. + * @{ + */ +#ifndef __ATLC_LC_CTRL7_MACRO__ +#define __ATLC_LC_CTRL7_MACRO__ + +/* macros for field dbg_sel */ +/** + * @defgroup at_lc_regs_core_dbg_sel_field dbg_sel_field + * @brief macros for field dbg_sel + * @details debug bus select + * @{ + */ +#define ATLC_LC_CTRL7__DBG_SEL__SHIFT 0 +#define ATLC_LC_CTRL7__DBG_SEL__WIDTH 4 +#define ATLC_LC_CTRL7__DBG_SEL__MASK 0x0000000fU +#define ATLC_LC_CTRL7__DBG_SEL__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define ATLC_LC_CTRL7__DBG_SEL__WRITE(src) ((uint32_t)(src) & 0x0000000fU) +#define ATLC_LC_CTRL7__DBG_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define ATLC_LC_CTRL7__DBG_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define ATLC_LC_CTRL7__DBG_SEL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_LC_CTRL7__TYPE uint32_t +#define ATLC_LC_CTRL7__READ 0x0000000fU +#define ATLC_LC_CTRL7__WRITE 0x0000000fU +#define ATLC_LC_CTRL7__PRESERVED 0x00000000U +#define ATLC_LC_CTRL7__RESET_VALUE 0x00000000U + +#endif /* __ATLC_LC_CTRL7_MACRO__ */ + +/** @} end of lc_ctrl7 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_ctrl8 */ +/** + * @defgroup at_lc_regs_core_lc_ctrl8 lc_ctrl8 + * @brief Contains register fields associated with lc_ctrl8. definitions. + * @{ + */ +#ifndef __ATLC_LC_CTRL8_MACRO__ +#define __ATLC_LC_CTRL8_MACRO__ + +/* macros for field prtcl */ +/** + * @defgroup at_lc_regs_core_prtcl_field prtcl_field + * @brief macros for field prtcl + * @details 0 => shockburst, 1 => ble, 2 => 15.4 + * @{ + */ +#define ATLC_LC_CTRL8__PRTCL__SHIFT 0 +#define ATLC_LC_CTRL8__PRTCL__WIDTH 4 +#define ATLC_LC_CTRL8__PRTCL__MASK 0x0000000fU +#define ATLC_LC_CTRL8__PRTCL__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define ATLC_LC_CTRL8__PRTCL__WRITE(src) ((uint32_t)(src) & 0x0000000fU) +#define ATLC_LC_CTRL8__PRTCL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define ATLC_LC_CTRL8__PRTCL__VERIFY(src) (!(((uint32_t)(src) & ~0x0000000fU))) +#define ATLC_LC_CTRL8__PRTCL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_LC_CTRL8__TYPE uint32_t +#define ATLC_LC_CTRL8__READ 0x0000000fU +#define ATLC_LC_CTRL8__WRITE 0x0000000fU +#define ATLC_LC_CTRL8__PRESERVED 0x00000000U +#define ATLC_LC_CTRL8__RESET_VALUE 0x00000000U + +#endif /* __ATLC_LC_CTRL8_MACRO__ */ + +/** @} end of lc_ctrl8 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_sb_ctrl0 */ +/** + * @defgroup at_lc_regs_core_lc_sb_ctrl0 lc_sb_ctrl0 + * @brief Contains register fields associated with lc_sb_ctrl0. definitions. + * @{ + */ +#ifndef __ATLC_LC_SB_CTRL0_MACRO__ +#define __ATLC_LC_SB_CTRL0_MACRO__ + +/* macros for field rate */ +/** + * @defgroup at_lc_regs_core_rate_field rate_field + * @brief macros for field rate + * @details 00 = 1 Mbps, 01 = 2 Mbps, 10 = 250 Kbps + * @{ + */ +#define ATLC_LC_SB_CTRL0__RATE__SHIFT 0 +#define ATLC_LC_SB_CTRL0__RATE__WIDTH 4 +#define ATLC_LC_SB_CTRL0__RATE__MASK 0x0000000fU +#define ATLC_LC_SB_CTRL0__RATE__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define ATLC_LC_SB_CTRL0__RATE__WRITE(src) ((uint32_t)(src) & 0x0000000fU) +#define ATLC_LC_SB_CTRL0__RATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define ATLC_LC_SB_CTRL0__RATE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define ATLC_LC_SB_CTRL0__RATE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field phdr_len */ +/** + * @defgroup at_lc_regs_core_phdr_len_field phdr_len_field + * @brief macros for field phdr_len + * @details phy header length in bytes + * @{ + */ +#define ATLC_LC_SB_CTRL0__PHDR_LEN__SHIFT 4 +#define ATLC_LC_SB_CTRL0__PHDR_LEN__WIDTH 4 +#define ATLC_LC_SB_CTRL0__PHDR_LEN__MASK 0x000000f0U +#define ATLC_LC_SB_CTRL0__PHDR_LEN__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define ATLC_LC_SB_CTRL0__PHDR_LEN__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x000000f0U) +#define ATLC_LC_SB_CTRL0__PHDR_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define ATLC_LC_SB_CTRL0__PHDR_LEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define ATLC_LC_SB_CTRL0__PHDR_LEN__RESET_VALUE 0x00000001U +/** @} */ +#define ATLC_LC_SB_CTRL0__TYPE uint32_t +#define ATLC_LC_SB_CTRL0__READ 0x000000ffU +#define ATLC_LC_SB_CTRL0__WRITE 0x000000ffU +#define ATLC_LC_SB_CTRL0__PRESERVED 0x00000000U +#define ATLC_LC_SB_CTRL0__RESET_VALUE 0x00000011U + +#endif /* __ATLC_LC_SB_CTRL0_MACRO__ */ + +/** @} end of lc_sb_ctrl0 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_ble_ctrl0 */ +/** + * @defgroup at_lc_regs_core_lc_ble_ctrl0 lc_ble_ctrl0 + * @brief Contains register fields associated with lc_ble_ctrl0. definitions. + * @{ + */ +#ifndef __ATLC_LC_BLE_CTRL0_MACRO__ +#define __ATLC_LC_BLE_CTRL0_MACRO__ + +/* macros for field rate */ +/** + * @defgroup at_lc_regs_core_rate_field rate_field + * @brief macros for field rate + * @details 0 => 1M, 1 => 2M, 2 => 500K, 3 => 125K + * @{ + */ +#define ATLC_LC_BLE_CTRL0__RATE__SHIFT 0 +#define ATLC_LC_BLE_CTRL0__RATE__WIDTH 4 +#define ATLC_LC_BLE_CTRL0__RATE__MASK 0x0000000fU +#define ATLC_LC_BLE_CTRL0__RATE__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define ATLC_LC_BLE_CTRL0__RATE__WRITE(src) ((uint32_t)(src) & 0x0000000fU) +#define ATLC_LC_BLE_CTRL0__RATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define ATLC_LC_BLE_CTRL0__RATE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define ATLC_LC_BLE_CTRL0__RATE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field phdr_len */ +/** + * @defgroup at_lc_regs_core_phdr_len_field phdr_len_field + * @brief macros for field phdr_len + * @details phy header length in bytes + * @{ + */ +#define ATLC_LC_BLE_CTRL0__PHDR_LEN__SHIFT 4 +#define ATLC_LC_BLE_CTRL0__PHDR_LEN__WIDTH 4 +#define ATLC_LC_BLE_CTRL0__PHDR_LEN__MASK 0x000000f0U +#define ATLC_LC_BLE_CTRL0__PHDR_LEN__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define ATLC_LC_BLE_CTRL0__PHDR_LEN__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x000000f0U) +#define ATLC_LC_BLE_CTRL0__PHDR_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define ATLC_LC_BLE_CTRL0__PHDR_LEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define ATLC_LC_BLE_CTRL0__PHDR_LEN__RESET_VALUE 0x00000001U +/** @} */ +#define ATLC_LC_BLE_CTRL0__TYPE uint32_t +#define ATLC_LC_BLE_CTRL0__READ 0x000000ffU +#define ATLC_LC_BLE_CTRL0__WRITE 0x000000ffU +#define ATLC_LC_BLE_CTRL0__PRESERVED 0x00000000U +#define ATLC_LC_BLE_CTRL0__RESET_VALUE 0x00000010U + +#endif /* __ATLC_LC_BLE_CTRL0_MACRO__ */ + +/** @} end of lc_ble_ctrl0 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_mac_154_ctrl0 */ +/** + * @defgroup at_lc_regs_core_mac_154_ctrl0 mac_154_ctrl0 + * @brief Contains register fields associated with mac_154_ctrl0. definitions. + * @{ + */ +#ifndef __ATLC_MAC_154_CTRL0_MACRO__ +#define __ATLC_MAC_154_CTRL0_MACRO__ + +/* macros for field rate */ +/** + * @defgroup at_lc_regs_core_rate_field rate_field + * @brief macros for field rate + * @details 0 => 1M, 1 => indicate to mdm 2M (bandwidth), rate is 250K + * @{ + */ +#define ATLC_MAC_154_CTRL0__RATE__SHIFT 0 +#define ATLC_MAC_154_CTRL0__RATE__WIDTH 4 +#define ATLC_MAC_154_CTRL0__RATE__MASK 0x0000000fU +#define ATLC_MAC_154_CTRL0__RATE__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define ATLC_MAC_154_CTRL0__RATE__WRITE(src) ((uint32_t)(src) & 0x0000000fU) +#define ATLC_MAC_154_CTRL0__RATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define ATLC_MAC_154_CTRL0__RATE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define ATLC_MAC_154_CTRL0__RATE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field phdr_len */ +/** + * @defgroup at_lc_regs_core_phdr_len_field phdr_len_field + * @brief macros for field phdr_len + * @details phy header length in bytes + * @{ + */ +#define ATLC_MAC_154_CTRL0__PHDR_LEN__SHIFT 4 +#define ATLC_MAC_154_CTRL0__PHDR_LEN__WIDTH 4 +#define ATLC_MAC_154_CTRL0__PHDR_LEN__MASK 0x000000f0U +#define ATLC_MAC_154_CTRL0__PHDR_LEN__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define ATLC_MAC_154_CTRL0__PHDR_LEN__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x000000f0U) +#define ATLC_MAC_154_CTRL0__PHDR_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define ATLC_MAC_154_CTRL0__PHDR_LEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define ATLC_MAC_154_CTRL0__PHDR_LEN__RESET_VALUE 0x00000001U +/** @} */ +#define ATLC_MAC_154_CTRL0__TYPE uint32_t +#define ATLC_MAC_154_CTRL0__READ 0x000000ffU +#define ATLC_MAC_154_CTRL0__WRITE 0x000000ffU +#define ATLC_MAC_154_CTRL0__PRESERVED 0x00000000U +#define ATLC_MAC_154_CTRL0__RESET_VALUE 0x00000011U + +#endif /* __ATLC_MAC_154_CTRL0_MACRO__ */ + +/** @} end of mac_154_ctrl0 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_mdm_ctrl0 */ +/** + * @defgroup at_lc_regs_core_mdm_ctrl0 mdm_ctrl0 + * @brief Contains register fields associated with mdm_ctrl0. definitions. + * @{ + */ +#ifndef __ATLC_MDM_CTRL0_MACRO__ +#define __ATLC_MDM_CTRL0_MACRO__ + +/* macros for field rx_en_low_tm */ +/** + * @defgroup at_lc_regs_core_rx_en_low_tm_field rx_en_low_tm_field + * @brief macros for field rx_en_low_tm + * @details number of 8 MHz clock rx_en need to be deasserted before asserted to look for packet + * @{ + */ +#define ATLC_MDM_CTRL0__RX_EN_LOW_TM__SHIFT 0 +#define ATLC_MDM_CTRL0__RX_EN_LOW_TM__WIDTH 8 +#define ATLC_MDM_CTRL0__RX_EN_LOW_TM__MASK 0x000000ffU +#define ATLC_MDM_CTRL0__RX_EN_LOW_TM__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_MDM_CTRL0__RX_EN_LOW_TM__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define ATLC_MDM_CTRL0__RX_EN_LOW_TM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define ATLC_MDM_CTRL0__RX_EN_LOW_TM__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define ATLC_MDM_CTRL0__RX_EN_LOW_TM__RESET_VALUE 0x00000008U +/** @} */ +#define ATLC_MDM_CTRL0__TYPE uint32_t +#define ATLC_MDM_CTRL0__READ 0x000000ffU +#define ATLC_MDM_CTRL0__WRITE 0x000000ffU +#define ATLC_MDM_CTRL0__PRESERVED 0x00000000U +#define ATLC_MDM_CTRL0__RESET_VALUE 0x00000008U + +#endif /* __ATLC_MDM_CTRL0_MACRO__ */ + +/** @} end of mdm_ctrl0 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_lp_ctrl0 */ +/** + * @defgroup at_lc_regs_core_lc_lp_ctrl0 lc_lp_ctrl0 + * @brief Contains register fields associated with lc_lp_ctrl0. definitions. + * @{ + */ +#ifndef __ATLC_LC_LP_CTRL0_MACRO__ +#define __ATLC_LC_LP_CTRL0_MACRO__ + +/* macros for field osc_slp_en */ +/** + * @defgroup at_lc_regs_core_osc_slp_en_field osc_slp_en_field + * @brief macros for field osc_slp_en + * @details enable oscillator to power down during sleep state + * @{ + */ +#define ATLC_LC_LP_CTRL0__OSC_SLP_EN__SHIFT 0 +#define ATLC_LC_LP_CTRL0__OSC_SLP_EN__WIDTH 1 +#define ATLC_LC_LP_CTRL0__OSC_SLP_EN__MASK 0x00000001U +#define ATLC_LC_LP_CTRL0__OSC_SLP_EN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATLC_LC_LP_CTRL0__OSC_SLP_EN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define ATLC_LC_LP_CTRL0__OSC_SLP_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATLC_LC_LP_CTRL0__OSC_SLP_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define ATLC_LC_LP_CTRL0__OSC_SLP_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATLC_LC_LP_CTRL0__OSC_SLP_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATLC_LC_LP_CTRL0__OSC_SLP_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field radio_slp_en */ +/** + * @defgroup at_lc_regs_core_radio_slp_en_field radio_slp_en_field + * @brief macros for field radio_slp_en + * @details enable radio to power down during sleep state + * @{ + */ +#define ATLC_LC_LP_CTRL0__RADIO_SLP_EN__SHIFT 1 +#define ATLC_LC_LP_CTRL0__RADIO_SLP_EN__WIDTH 1 +#define ATLC_LC_LP_CTRL0__RADIO_SLP_EN__MASK 0x00000002U +#define ATLC_LC_LP_CTRL0__RADIO_SLP_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define ATLC_LC_LP_CTRL0__RADIO_SLP_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define ATLC_LC_LP_CTRL0__RADIO_SLP_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define ATLC_LC_LP_CTRL0__RADIO_SLP_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define ATLC_LC_LP_CTRL0__RADIO_SLP_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATLC_LC_LP_CTRL0__RADIO_SLP_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATLC_LC_LP_CTRL0__RADIO_SLP_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field extwu_dis */ +/** + * @defgroup at_lc_regs_core_extwu_dis_field extwu_dis_field + * @brief macros for field extwu_dis + * @details external wakeup disable + * @{ + */ +#define ATLC_LC_LP_CTRL0__EXTWU_DIS__SHIFT 3 +#define ATLC_LC_LP_CTRL0__EXTWU_DIS__WIDTH 1 +#define ATLC_LC_LP_CTRL0__EXTWU_DIS__MASK 0x00000008U +#define ATLC_LC_LP_CTRL0__EXTWU_DIS__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define ATLC_LC_LP_CTRL0__EXTWU_DIS__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define ATLC_LC_LP_CTRL0__EXTWU_DIS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define ATLC_LC_LP_CTRL0__EXTWU_DIS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define ATLC_LC_LP_CTRL0__EXTWU_DIS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define ATLC_LC_LP_CTRL0__EXTWU_DIS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define ATLC_LC_LP_CTRL0__EXTWU_DIS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field slp */ +/** + * @defgroup at_lc_regs_core_slp_field slp_field + * @brief macros for field slp + * @details go into sleep state + * @{ + */ +#define ATLC_LC_LP_CTRL0__SLP__SHIFT 4 +#define ATLC_LC_LP_CTRL0__SLP__WIDTH 1 +#define ATLC_LC_LP_CTRL0__SLP__MASK 0x00000010U +#define ATLC_LC_LP_CTRL0__SLP__READ(src) (((uint32_t)(src) & 0x00000010U) >> 4) +#define ATLC_LC_LP_CTRL0__SLP__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define ATLC_LC_LP_CTRL0__SLP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define ATLC_LC_LP_CTRL0__SLP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define ATLC_LC_LP_CTRL0__SLP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define ATLC_LC_LP_CTRL0__SLP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define ATLC_LC_LP_CTRL0__SLP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sw_wu_req */ +/** + * @defgroup at_lc_regs_core_sw_wu_req_field sw_wu_req_field + * @brief macros for field sw_wu_req + * @details software wakeup request + * @{ + */ +#define ATLC_LC_LP_CTRL0__SW_WU_REQ__SHIFT 5 +#define ATLC_LC_LP_CTRL0__SW_WU_REQ__WIDTH 1 +#define ATLC_LC_LP_CTRL0__SW_WU_REQ__MASK 0x00000020U +#define ATLC_LC_LP_CTRL0__SW_WU_REQ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define ATLC_LC_LP_CTRL0__SW_WU_REQ__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define ATLC_LC_LP_CTRL0__SW_WU_REQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define ATLC_LC_LP_CTRL0__SW_WU_REQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define ATLC_LC_LP_CTRL0__SW_WU_REQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define ATLC_LC_LP_CTRL0__SW_WU_REQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define ATLC_LC_LP_CTRL0__SW_WU_REQ__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_LC_LP_CTRL0__TYPE uint32_t +#define ATLC_LC_LP_CTRL0__READ 0x0000003bU +#define ATLC_LC_LP_CTRL0__WRITE 0x0000003bU +#define ATLC_LC_LP_CTRL0__PRESERVED 0x00000000U +#define ATLC_LC_LP_CTRL0__RESET_VALUE 0x00000000U + +#endif /* __ATLC_LC_LP_CTRL0_MACRO__ */ + +/** @} end of lc_lp_ctrl0 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_lp_ctrl1 */ +/** + * @defgroup at_lc_regs_core_lc_lp_ctrl1 lc_lp_ctrl1 + * @brief Contains register fields associated with lc_lp_ctrl1. definitions. + * @{ + */ +#ifndef __ATLC_LC_LP_CTRL1_MACRO__ +#define __ATLC_LC_LP_CTRL1_MACRO__ + +/* macros for field wrm */ +/** + * @defgroup at_lc_regs_core_wrm_field wrm_field + * @brief macros for field wrm + * @details radio settling time in low power clock cyle + * @{ + */ +#define ATLC_LC_LP_CTRL1__WRM__SHIFT 0 +#define ATLC_LC_LP_CTRL1__WRM__WIDTH 10 +#define ATLC_LC_LP_CTRL1__WRM__MASK 0x000003ffU +#define ATLC_LC_LP_CTRL1__WRM__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define ATLC_LC_LP_CTRL1__WRM__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define ATLC_LC_LP_CTRL1__WRM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define ATLC_LC_LP_CTRL1__WRM__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define ATLC_LC_LP_CTRL1__WRM__RESET_VALUE 0x00000050U +/** @} */ + +/* macros for field wosc */ +/** + * @defgroup at_lc_regs_core_wosc_field wosc_field + * @brief macros for field wosc + * @details PLL settling time following sleep timer expiration in low power clock cyle + * @{ + */ +#define ATLC_LC_LP_CTRL1__WOSC__SHIFT 10 +#define ATLC_LC_LP_CTRL1__WOSC__WIDTH 11 +#define ATLC_LC_LP_CTRL1__WOSC__MASK 0x001ffc00U +#define ATLC_LC_LP_CTRL1__WOSC__READ(src) \ + (((uint32_t)(src)\ + & 0x001ffc00U) >> 10) +#define ATLC_LC_LP_CTRL1__WOSC__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x001ffc00U) +#define ATLC_LC_LP_CTRL1__WOSC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x001ffc00U) +#define ATLC_LC_LP_CTRL1__WOSC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x001ffc00U))) +#define ATLC_LC_LP_CTRL1__WOSC__RESET_VALUE 0x00000064U +/** @} */ + +/* macros for field wext */ +/** + * @defgroup at_lc_regs_core_wext_field wext_field + * @brief macros for field wext + * @details PLL settling time following external wakeup request in low power clock cyle + * @{ + */ +#define ATLC_LC_LP_CTRL1__WEXT__SHIFT 21 +#define ATLC_LC_LP_CTRL1__WEXT__WIDTH 11 +#define ATLC_LC_LP_CTRL1__WEXT__MASK 0xffe00000U +#define ATLC_LC_LP_CTRL1__WEXT__READ(src) \ + (((uint32_t)(src)\ + & 0xffe00000U) >> 21) +#define ATLC_LC_LP_CTRL1__WEXT__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0xffe00000U) +#define ATLC_LC_LP_CTRL1__WEXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffe00000U) | (((uint32_t)(src) <<\ + 21) & 0xffe00000U) +#define ATLC_LC_LP_CTRL1__WEXT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0xffe00000U))) +#define ATLC_LC_LP_CTRL1__WEXT__RESET_VALUE 0x00000064U +/** @} */ +#define ATLC_LC_LP_CTRL1__TYPE uint32_t +#define ATLC_LC_LP_CTRL1__READ 0xffffffffU +#define ATLC_LC_LP_CTRL1__WRITE 0xffffffffU +#define ATLC_LC_LP_CTRL1__PRESERVED 0x00000000U +#define ATLC_LC_LP_CTRL1__RESET_VALUE 0x0c819050U + +#endif /* __ATLC_LC_LP_CTRL1_MACRO__ */ + +/** @} end of lc_lp_ctrl1 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_lp_ctrl2 */ +/** + * @defgroup at_lc_regs_core_lc_lp_ctrl2 lc_lp_ctrl2 + * @brief Contains register fields associated with lc_lp_ctrl2. definitions. + * @{ + */ +#ifndef __ATLC_LC_LP_CTRL2_MACRO__ +#define __ATLC_LC_LP_CTRL2_MACRO__ + +/* macros for field slp_tm */ +/** + * @defgroup at_lc_regs_core_slp_tm_field slp_tm_field + * @brief macros for field slp_tm + * @details deep sleep time + * @{ + */ +#define ATLC_LC_LP_CTRL2__SLP_TM__SHIFT 0 +#define ATLC_LC_LP_CTRL2__SLP_TM__WIDTH 32 +#define ATLC_LC_LP_CTRL2__SLP_TM__MASK 0xffffffffU +#define ATLC_LC_LP_CTRL2__SLP_TM__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_LC_LP_CTRL2__SLP_TM__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_LC_LP_CTRL2__SLP_TM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_LC_LP_CTRL2__SLP_TM__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define ATLC_LC_LP_CTRL2__SLP_TM__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_LC_LP_CTRL2__TYPE uint32_t +#define ATLC_LC_LP_CTRL2__READ 0xffffffffU +#define ATLC_LC_LP_CTRL2__WRITE 0xffffffffU +#define ATLC_LC_LP_CTRL2__PRESERVED 0x00000000U +#define ATLC_LC_LP_CTRL2__RESET_VALUE 0x00000000U + +#endif /* __ATLC_LC_LP_CTRL2_MACRO__ */ + +/** @} end of lc_lp_ctrl2 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_lp_st0 */ +/** + * @defgroup at_lc_regs_core_lc_lp_st0 lc_lp_st0 + * @brief Contains register fields associated with lc_lp_st0. definitions. + * @{ + */ +#ifndef __ATLC_LC_LP_ST0_MACRO__ +#define __ATLC_LC_LP_ST0_MACRO__ + +/* macros for field slp_cntr */ +/** + * @defgroup at_lc_regs_core_slp_cntr_field slp_cntr_field + * @brief macros for field slp_cntr + * @details deep sleep counter + * @{ + */ +#define ATLC_LC_LP_ST0__SLP_CNTR__SHIFT 0 +#define ATLC_LC_LP_ST0__SLP_CNTR__WIDTH 32 +#define ATLC_LC_LP_ST0__SLP_CNTR__MASK 0xffffffffU +#define ATLC_LC_LP_ST0__SLP_CNTR__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_LC_LP_ST0__SLP_CNTR__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_LC_LP_ST0__TYPE uint32_t +#define ATLC_LC_LP_ST0__READ 0xffffffffU +#define ATLC_LC_LP_ST0__PRESERVED 0x00000000U +#define ATLC_LC_LP_ST0__RESET_VALUE 0x00000000U + +#endif /* __ATLC_LC_LP_ST0_MACRO__ */ + +/** @} end of lc_lp_st0 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_rft_ctrl0 */ +/** + * @defgroup at_lc_regs_core_lc_rft_ctrl0 lc_rft_ctrl0 + * @brief Contains register fields associated with lc_rft_ctrl0. definitions. + * @{ + */ +#ifndef __ATLC_LC_RFT_CTRL0_MACRO__ +#define __ATLC_LC_RFT_CTRL0_MACRO__ + +/* macros for field pyld_typ */ +/** + * @defgroup at_lc_regs_core_pyld_typ_field pyld_typ_field + * @brief macros for field pyld_typ + * @details payload type 0x0 use payload in tx buffer 0x1 replace pyld with prbs9 0x2 replace payload with prbs15 + * @{ + */ +#define ATLC_LC_RFT_CTRL0__PYLD_TYP__SHIFT 0 +#define ATLC_LC_RFT_CTRL0__PYLD_TYP__WIDTH 2 +#define ATLC_LC_RFT_CTRL0__PYLD_TYP__MASK 0x00000003U +#define ATLC_LC_RFT_CTRL0__PYLD_TYP__READ(src) ((uint32_t)(src) & 0x00000003U) +#define ATLC_LC_RFT_CTRL0__PYLD_TYP__WRITE(src) ((uint32_t)(src) & 0x00000003U) +#define ATLC_LC_RFT_CTRL0__PYLD_TYP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define ATLC_LC_RFT_CTRL0__PYLD_TYP__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define ATLC_LC_RFT_CTRL0__PYLD_TYP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_infnt */ +/** + * @defgroup at_lc_regs_core_rx_infnt_field rx_infnt_field + * @brief macros for field rx_infnt + * @details infinite rx window + * @{ + */ +#define ATLC_LC_RFT_CTRL0__RX_INFNT__SHIFT 2 +#define ATLC_LC_RFT_CTRL0__RX_INFNT__WIDTH 1 +#define ATLC_LC_RFT_CTRL0__RX_INFNT__MASK 0x00000004U +#define ATLC_LC_RFT_CTRL0__RX_INFNT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define ATLC_LC_RFT_CTRL0__RX_INFNT__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define ATLC_LC_RFT_CTRL0__RX_INFNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define ATLC_LC_RFT_CTRL0__RX_INFNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define ATLC_LC_RFT_CTRL0__RX_INFNT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define ATLC_LC_RFT_CTRL0__RX_INFNT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define ATLC_LC_RFT_CTRL0__RX_INFNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tx_infnt */ +/** + * @defgroup at_lc_regs_core_tx_infnt_field tx_infnt_field + * @brief macros for field tx_infnt + * @details infinite length payload instead of payload length specified in the header + * @{ + */ +#define ATLC_LC_RFT_CTRL0__TX_INFNT__SHIFT 3 +#define ATLC_LC_RFT_CTRL0__TX_INFNT__WIDTH 1 +#define ATLC_LC_RFT_CTRL0__TX_INFNT__MASK 0x00000008U +#define ATLC_LC_RFT_CTRL0__TX_INFNT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define ATLC_LC_RFT_CTRL0__TX_INFNT__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define ATLC_LC_RFT_CTRL0__TX_INFNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define ATLC_LC_RFT_CTRL0__TX_INFNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define ATLC_LC_RFT_CTRL0__TX_INFNT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define ATLC_LC_RFT_CTRL0__TX_INFNT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define ATLC_LC_RFT_CTRL0__TX_INFNT__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_LC_RFT_CTRL0__TYPE uint32_t +#define ATLC_LC_RFT_CTRL0__READ 0x0000000fU +#define ATLC_LC_RFT_CTRL0__WRITE 0x0000000fU +#define ATLC_LC_RFT_CTRL0__PRESERVED 0x00000000U +#define ATLC_LC_RFT_CTRL0__RESET_VALUE 0x00000000U + +#endif /* __ATLC_LC_RFT_CTRL0_MACRO__ */ + +/** @} end of lc_rft_ctrl0 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_ifg */ +/** + * @defgroup at_lc_regs_core_ifg ifg + * @brief Contains register fields associated with ifg. definitions. + * @{ + */ +#ifndef __ATLC_IFG_MACRO__ +#define __ATLC_IFG_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details interframe gap in micro seconds + * @{ + */ +#define ATLC_IFG__VL__SHIFT 0 +#define ATLC_IFG__VL__WIDTH 8 +#define ATLC_IFG__VL__MASK 0x000000ffU +#define ATLC_IFG__VL__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_IFG__VL__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_IFG__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define ATLC_IFG__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x000000ffU))) +#define ATLC_IFG__VL__RESET_VALUE 0x00000082U +/** @} */ +#define ATLC_IFG__TYPE uint32_t +#define ATLC_IFG__READ 0x000000ffU +#define ATLC_IFG__WRITE 0x000000ffU +#define ATLC_IFG__PRESERVED 0x00000000U +#define ATLC_IFG__RESET_VALUE 0x00000082U + +#endif /* __ATLC_IFG_MACRO__ */ + +/** @} end of ifg */ + +/* macros for BlueprintGlobalNameSpace::ATLC_pthdly_1mbps */ +/** + * @defgroup at_lc_regs_core_pthdly_1mbps pthdly_1mbps + * @brief Contains register fields associated with pthdly_1mbps. definitions. + * @{ + */ +#ifndef __ATLC_PTHDLY_1MBPS_MACRO__ +#define __ATLC_PTHDLY_1MBPS_MACRO__ + +/* macros for field rx */ +/** + * @defgroup at_lc_regs_core_rx_field rx_field + * @brief macros for field rx + * @details rx path delay in micro seconds + * @{ + */ +#define ATLC_PTHDLY_1MBPS__RX__SHIFT 0 +#define ATLC_PTHDLY_1MBPS__RX__WIDTH 8 +#define ATLC_PTHDLY_1MBPS__RX__MASK 0x000000ffU +#define ATLC_PTHDLY_1MBPS__RX__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_PTHDLY_1MBPS__RX__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_PTHDLY_1MBPS__RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define ATLC_PTHDLY_1MBPS__RX__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define ATLC_PTHDLY_1MBPS__RX__RESET_VALUE 0x00000058U +/** @} */ + +/* macros for field tx */ +/** + * @defgroup at_lc_regs_core_tx_field tx_field + * @brief macros for field tx + * @details tx path delay in micro seconds + * @{ + */ +#define ATLC_PTHDLY_1MBPS__TX__SHIFT 8 +#define ATLC_PTHDLY_1MBPS__TX__WIDTH 8 +#define ATLC_PTHDLY_1MBPS__TX__MASK 0x0000ff00U +#define ATLC_PTHDLY_1MBPS__TX__READ(src) (((uint32_t)(src) & 0x0000ff00U) >> 8) +#define ATLC_PTHDLY_1MBPS__TX__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define ATLC_PTHDLY_1MBPS__TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define ATLC_PTHDLY_1MBPS__TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define ATLC_PTHDLY_1MBPS__TX__RESET_VALUE 0x00000032U +/** @} */ +#define ATLC_PTHDLY_1MBPS__TYPE uint32_t +#define ATLC_PTHDLY_1MBPS__READ 0x0000ffffU +#define ATLC_PTHDLY_1MBPS__WRITE 0x0000ffffU +#define ATLC_PTHDLY_1MBPS__PRESERVED 0x00000000U +#define ATLC_PTHDLY_1MBPS__RESET_VALUE 0x00003258U + +#endif /* __ATLC_PTHDLY_1MBPS_MACRO__ */ + +/** @} end of pthdly_1mbps */ + +/* macros for BlueprintGlobalNameSpace::ATLC_pthdly_2mbps */ +/** + * @defgroup at_lc_regs_core_pthdly_2mbps pthdly_2mbps + * @brief Contains register fields associated with pthdly_2mbps. definitions. + * @{ + */ +#ifndef __ATLC_PTHDLY_2MBPS_MACRO__ +#define __ATLC_PTHDLY_2MBPS_MACRO__ + +/* macros for field rx */ +/** + * @defgroup at_lc_regs_core_rx_field rx_field + * @brief macros for field rx + * @details rx path delay in micro seconds + * @{ + */ +#define ATLC_PTHDLY_2MBPS__RX__SHIFT 0 +#define ATLC_PTHDLY_2MBPS__RX__WIDTH 8 +#define ATLC_PTHDLY_2MBPS__RX__MASK 0x000000ffU +#define ATLC_PTHDLY_2MBPS__RX__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_PTHDLY_2MBPS__RX__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_PTHDLY_2MBPS__RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define ATLC_PTHDLY_2MBPS__RX__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define ATLC_PTHDLY_2MBPS__RX__RESET_VALUE 0x00000058U +/** @} */ + +/* macros for field tx */ +/** + * @defgroup at_lc_regs_core_tx_field tx_field + * @brief macros for field tx + * @details tx path delay in micro seconds + * @{ + */ +#define ATLC_PTHDLY_2MBPS__TX__SHIFT 8 +#define ATLC_PTHDLY_2MBPS__TX__WIDTH 8 +#define ATLC_PTHDLY_2MBPS__TX__MASK 0x0000ff00U +#define ATLC_PTHDLY_2MBPS__TX__READ(src) (((uint32_t)(src) & 0x0000ff00U) >> 8) +#define ATLC_PTHDLY_2MBPS__TX__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define ATLC_PTHDLY_2MBPS__TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define ATLC_PTHDLY_2MBPS__TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define ATLC_PTHDLY_2MBPS__TX__RESET_VALUE 0x00000032U +/** @} */ +#define ATLC_PTHDLY_2MBPS__TYPE uint32_t +#define ATLC_PTHDLY_2MBPS__READ 0x0000ffffU +#define ATLC_PTHDLY_2MBPS__WRITE 0x0000ffffU +#define ATLC_PTHDLY_2MBPS__PRESERVED 0x00000000U +#define ATLC_PTHDLY_2MBPS__RESET_VALUE 0x00003258U + +#endif /* __ATLC_PTHDLY_2MBPS_MACRO__ */ + +/** @} end of pthdly_2mbps */ + +/* macros for BlueprintGlobalNameSpace::ATLC_pthdly_250kbps */ +/** + * @defgroup at_lc_regs_core_pthdly_250kbps pthdly_250kbps + * @brief Contains register fields associated with pthdly_250kbps. definitions. + * @{ + */ +#ifndef __ATLC_PTHDLY_250KBPS_MACRO__ +#define __ATLC_PTHDLY_250KBPS_MACRO__ + +/* macros for field rx */ +/** + * @defgroup at_lc_regs_core_rx_field rx_field + * @brief macros for field rx + * @details rx path delay in micro seconds + * @{ + */ +#define ATLC_PTHDLY_250KBPS__RX__SHIFT 0 +#define ATLC_PTHDLY_250KBPS__RX__WIDTH 8 +#define ATLC_PTHDLY_250KBPS__RX__MASK 0x000000ffU +#define ATLC_PTHDLY_250KBPS__RX__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_PTHDLY_250KBPS__RX__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_PTHDLY_250KBPS__RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define ATLC_PTHDLY_250KBPS__RX__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define ATLC_PTHDLY_250KBPS__RX__RESET_VALUE 0x00000058U +/** @} */ + +/* macros for field tx */ +/** + * @defgroup at_lc_regs_core_tx_field tx_field + * @brief macros for field tx + * @details tx path delay in micro seconds + * @{ + */ +#define ATLC_PTHDLY_250KBPS__TX__SHIFT 8 +#define ATLC_PTHDLY_250KBPS__TX__WIDTH 8 +#define ATLC_PTHDLY_250KBPS__TX__MASK 0x0000ff00U +#define ATLC_PTHDLY_250KBPS__TX__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define ATLC_PTHDLY_250KBPS__TX__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define ATLC_PTHDLY_250KBPS__TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define ATLC_PTHDLY_250KBPS__TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define ATLC_PTHDLY_250KBPS__TX__RESET_VALUE 0x00000032U +/** @} */ +#define ATLC_PTHDLY_250KBPS__TYPE uint32_t +#define ATLC_PTHDLY_250KBPS__READ 0x0000ffffU +#define ATLC_PTHDLY_250KBPS__WRITE 0x0000ffffU +#define ATLC_PTHDLY_250KBPS__PRESERVED 0x00000000U +#define ATLC_PTHDLY_250KBPS__RESET_VALUE 0x00003258U + +#endif /* __ATLC_PTHDLY_250KBPS_MACRO__ */ + +/** @} end of pthdly_250kbps */ + +/* macros for BlueprintGlobalNameSpace::ATLC_pwrud_1mbps */ +/** + * @defgroup at_lc_regs_core_pwrud_1mbps pwrud_1mbps + * @brief Contains register fields associated with pwrud_1mbps. definitions. + * @{ + */ +#ifndef __ATLC_PWRUD_1MBPS_MACRO__ +#define __ATLC_PWRUD_1MBPS_MACRO__ + +/* macros for field rx_pwrup */ +/** + * @defgroup at_lc_regs_core_rx_pwrup_field rx_pwrup_field + * @brief macros for field rx_pwrup + * @details rx powerup time in micro seconds + * @{ + */ +#define ATLC_PWRUD_1MBPS__RX_PWRUP__SHIFT 0 +#define ATLC_PWRUD_1MBPS__RX_PWRUP__WIDTH 8 +#define ATLC_PWRUD_1MBPS__RX_PWRUP__MASK 0x000000ffU +#define ATLC_PWRUD_1MBPS__RX_PWRUP__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_PWRUD_1MBPS__RX_PWRUP__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_PWRUD_1MBPS__RX_PWRUP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define ATLC_PWRUD_1MBPS__RX_PWRUP__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define ATLC_PWRUD_1MBPS__RX_PWRUP__RESET_VALUE 0x00000058U +/** @} */ + +/* macros for field tx_pwrup */ +/** + * @defgroup at_lc_regs_core_tx_pwrup_field tx_pwrup_field + * @brief macros for field tx_pwrup + * @details tx powerup time in micro seconds + * @{ + */ +#define ATLC_PWRUD_1MBPS__TX_PWRUP__SHIFT 8 +#define ATLC_PWRUD_1MBPS__TX_PWRUP__WIDTH 8 +#define ATLC_PWRUD_1MBPS__TX_PWRUP__MASK 0x0000ff00U +#define ATLC_PWRUD_1MBPS__TX_PWRUP__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define ATLC_PWRUD_1MBPS__TX_PWRUP__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define ATLC_PWRUD_1MBPS__TX_PWRUP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define ATLC_PWRUD_1MBPS__TX_PWRUP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define ATLC_PWRUD_1MBPS__TX_PWRUP__RESET_VALUE 0x00000032U +/** @} */ + +/* macros for field tx_pwrdn */ +/** + * @defgroup at_lc_regs_core_tx_pwrdn_field tx_pwrdn_field + * @brief macros for field tx_pwrdn + * @details tx powerdn time in micro seconds + * @{ + */ +#define ATLC_PWRUD_1MBPS__TX_PWRDN__SHIFT 16 +#define ATLC_PWRUD_1MBPS__TX_PWRDN__WIDTH 8 +#define ATLC_PWRUD_1MBPS__TX_PWRDN__MASK 0x00ff0000U +#define ATLC_PWRUD_1MBPS__TX_PWRDN__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define ATLC_PWRUD_1MBPS__TX_PWRDN__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define ATLC_PWRUD_1MBPS__TX_PWRDN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define ATLC_PWRUD_1MBPS__TX_PWRDN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define ATLC_PWRUD_1MBPS__TX_PWRDN__RESET_VALUE 0x00000003U +/** @} */ +#define ATLC_PWRUD_1MBPS__TYPE uint32_t +#define ATLC_PWRUD_1MBPS__READ 0x00ffffffU +#define ATLC_PWRUD_1MBPS__WRITE 0x00ffffffU +#define ATLC_PWRUD_1MBPS__PRESERVED 0x00000000U +#define ATLC_PWRUD_1MBPS__RESET_VALUE 0x00033258U + +#endif /* __ATLC_PWRUD_1MBPS_MACRO__ */ + +/** @} end of pwrud_1mbps */ + +/* macros for BlueprintGlobalNameSpace::ATLC_pwrud_2mbps */ +/** + * @defgroup at_lc_regs_core_pwrud_2mbps pwrud_2mbps + * @brief Contains register fields associated with pwrud_2mbps. definitions. + * @{ + */ +#ifndef __ATLC_PWRUD_2MBPS_MACRO__ +#define __ATLC_PWRUD_2MBPS_MACRO__ + +/* macros for field rx_pwrup */ +/** + * @defgroup at_lc_regs_core_rx_pwrup_field rx_pwrup_field + * @brief macros for field rx_pwrup + * @details rx powerup time in micro seconds + * @{ + */ +#define ATLC_PWRUD_2MBPS__RX_PWRUP__SHIFT 0 +#define ATLC_PWRUD_2MBPS__RX_PWRUP__WIDTH 8 +#define ATLC_PWRUD_2MBPS__RX_PWRUP__MASK 0x000000ffU +#define ATLC_PWRUD_2MBPS__RX_PWRUP__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_PWRUD_2MBPS__RX_PWRUP__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_PWRUD_2MBPS__RX_PWRUP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define ATLC_PWRUD_2MBPS__RX_PWRUP__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define ATLC_PWRUD_2MBPS__RX_PWRUP__RESET_VALUE 0x00000058U +/** @} */ + +/* macros for field tx_pwrup */ +/** + * @defgroup at_lc_regs_core_tx_pwrup_field tx_pwrup_field + * @brief macros for field tx_pwrup + * @details tx powerup time in micro seconds + * @{ + */ +#define ATLC_PWRUD_2MBPS__TX_PWRUP__SHIFT 8 +#define ATLC_PWRUD_2MBPS__TX_PWRUP__WIDTH 8 +#define ATLC_PWRUD_2MBPS__TX_PWRUP__MASK 0x0000ff00U +#define ATLC_PWRUD_2MBPS__TX_PWRUP__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define ATLC_PWRUD_2MBPS__TX_PWRUP__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define ATLC_PWRUD_2MBPS__TX_PWRUP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define ATLC_PWRUD_2MBPS__TX_PWRUP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define ATLC_PWRUD_2MBPS__TX_PWRUP__RESET_VALUE 0x00000032U +/** @} */ + +/* macros for field tx_pwrdn */ +/** + * @defgroup at_lc_regs_core_tx_pwrdn_field tx_pwrdn_field + * @brief macros for field tx_pwrdn + * @details tx powerdn time in micro seconds + * @{ + */ +#define ATLC_PWRUD_2MBPS__TX_PWRDN__SHIFT 16 +#define ATLC_PWRUD_2MBPS__TX_PWRDN__WIDTH 8 +#define ATLC_PWRUD_2MBPS__TX_PWRDN__MASK 0x00ff0000U +#define ATLC_PWRUD_2MBPS__TX_PWRDN__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define ATLC_PWRUD_2MBPS__TX_PWRDN__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define ATLC_PWRUD_2MBPS__TX_PWRDN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define ATLC_PWRUD_2MBPS__TX_PWRDN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define ATLC_PWRUD_2MBPS__TX_PWRDN__RESET_VALUE 0x00000003U +/** @} */ +#define ATLC_PWRUD_2MBPS__TYPE uint32_t +#define ATLC_PWRUD_2MBPS__READ 0x00ffffffU +#define ATLC_PWRUD_2MBPS__WRITE 0x00ffffffU +#define ATLC_PWRUD_2MBPS__PRESERVED 0x00000000U +#define ATLC_PWRUD_2MBPS__RESET_VALUE 0x00033258U + +#endif /* __ATLC_PWRUD_2MBPS_MACRO__ */ + +/** @} end of pwrud_2mbps */ + +/* macros for BlueprintGlobalNameSpace::ATLC_pwrud_250kbps */ +/** + * @defgroup at_lc_regs_core_pwrud_250kbps pwrud_250kbps + * @brief Contains register fields associated with pwrud_250kbps. definitions. + * @{ + */ +#ifndef __ATLC_PWRUD_250KBPS_MACRO__ +#define __ATLC_PWRUD_250KBPS_MACRO__ + +/* macros for field rx_pwrup */ +/** + * @defgroup at_lc_regs_core_rx_pwrup_field rx_pwrup_field + * @brief macros for field rx_pwrup + * @details rx powerup time in micro seconds + * @{ + */ +#define ATLC_PWRUD_250KBPS__RX_PWRUP__SHIFT 0 +#define ATLC_PWRUD_250KBPS__RX_PWRUP__WIDTH 8 +#define ATLC_PWRUD_250KBPS__RX_PWRUP__MASK 0x000000ffU +#define ATLC_PWRUD_250KBPS__RX_PWRUP__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_PWRUD_250KBPS__RX_PWRUP__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define ATLC_PWRUD_250KBPS__RX_PWRUP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define ATLC_PWRUD_250KBPS__RX_PWRUP__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define ATLC_PWRUD_250KBPS__RX_PWRUP__RESET_VALUE 0x00000058U +/** @} */ + +/* macros for field tx_pwrup */ +/** + * @defgroup at_lc_regs_core_tx_pwrup_field tx_pwrup_field + * @brief macros for field tx_pwrup + * @details tx powerup time in micro seconds + * @{ + */ +#define ATLC_PWRUD_250KBPS__TX_PWRUP__SHIFT 8 +#define ATLC_PWRUD_250KBPS__TX_PWRUP__WIDTH 8 +#define ATLC_PWRUD_250KBPS__TX_PWRUP__MASK 0x0000ff00U +#define ATLC_PWRUD_250KBPS__TX_PWRUP__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define ATLC_PWRUD_250KBPS__TX_PWRUP__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define ATLC_PWRUD_250KBPS__TX_PWRUP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define ATLC_PWRUD_250KBPS__TX_PWRUP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define ATLC_PWRUD_250KBPS__TX_PWRUP__RESET_VALUE 0x00000032U +/** @} */ + +/* macros for field tx_pwrdn */ +/** + * @defgroup at_lc_regs_core_tx_pwrdn_field tx_pwrdn_field + * @brief macros for field tx_pwrdn + * @details tx powerdn time in micro seconds + * @{ + */ +#define ATLC_PWRUD_250KBPS__TX_PWRDN__SHIFT 16 +#define ATLC_PWRUD_250KBPS__TX_PWRDN__WIDTH 8 +#define ATLC_PWRUD_250KBPS__TX_PWRDN__MASK 0x00ff0000U +#define ATLC_PWRUD_250KBPS__TX_PWRDN__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define ATLC_PWRUD_250KBPS__TX_PWRDN__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define ATLC_PWRUD_250KBPS__TX_PWRDN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define ATLC_PWRUD_250KBPS__TX_PWRDN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define ATLC_PWRUD_250KBPS__TX_PWRDN__RESET_VALUE 0x00000003U +/** @} */ +#define ATLC_PWRUD_250KBPS__TYPE uint32_t +#define ATLC_PWRUD_250KBPS__READ 0x00ffffffU +#define ATLC_PWRUD_250KBPS__WRITE 0x00ffffffU +#define ATLC_PWRUD_250KBPS__PRESERVED 0x00000000U +#define ATLC_PWRUD_250KBPS__RESET_VALUE 0x00033258U + +#endif /* __ATLC_PWRUD_250KBPS_MACRO__ */ + +/** @} end of pwrud_250kbps */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rtx_wait */ +/** + * @defgroup at_lc_regs_core_rtx_wait rtx_wait + * @brief Contains register fields associated with rtx_wait. definitions. + * @{ + */ +#ifndef __ATLC_RTX_WAIT_MACRO__ +#define __ATLC_RTX_WAIT_MACRO__ + +/* macros for field tx_rx */ +/** + * @defgroup at_lc_regs_core_tx_rx_field tx_rx_field + * @brief macros for field tx_rx + * @details tx to rx transition wait time in micro seconds + * @{ + */ +#define ATLC_RTX_WAIT__TX_RX__SHIFT 0 +#define ATLC_RTX_WAIT__TX_RX__WIDTH 8 +#define ATLC_RTX_WAIT__TX_RX__MASK 0x000000ffU +#define ATLC_RTX_WAIT__TX_RX__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_RTX_WAIT__TX_RX__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_RTX_WAIT__TX_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define ATLC_RTX_WAIT__TX_RX__VERIFY(src) (!(((uint32_t)(src) & ~0x000000ffU))) +#define ATLC_RTX_WAIT__TX_RX__RESET_VALUE 0x00000082U +/** @} */ + +/* macros for field rx_tx */ +/** + * @defgroup at_lc_regs_core_rx_tx_field rx_tx_field + * @brief macros for field rx_tx + * @details rx to tx transition wait time in micro seconds + * @{ + */ +#define ATLC_RTX_WAIT__RX_TX__SHIFT 8 +#define ATLC_RTX_WAIT__RX_TX__WIDTH 8 +#define ATLC_RTX_WAIT__RX_TX__MASK 0x0000ff00U +#define ATLC_RTX_WAIT__RX_TX__READ(src) (((uint32_t)(src) & 0x0000ff00U) >> 8) +#define ATLC_RTX_WAIT__RX_TX__WRITE(src) (((uint32_t)(src) << 8) & 0x0000ff00U) +#define ATLC_RTX_WAIT__RX_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define ATLC_RTX_WAIT__RX_TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define ATLC_RTX_WAIT__RX_TX__RESET_VALUE 0x00000082U +/** @} */ +#define ATLC_RTX_WAIT__TYPE uint32_t +#define ATLC_RTX_WAIT__READ 0x0000ffffU +#define ATLC_RTX_WAIT__WRITE 0x0000ffffU +#define ATLC_RTX_WAIT__PRESERVED 0x00000000U +#define ATLC_RTX_WAIT__RESET_VALUE 0x00008282U + +#endif /* __ATLC_RTX_WAIT_MACRO__ */ + +/** @} end of rtx_wait */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_st0 */ +/** + * @defgroup at_lc_regs_core_lc_st0 lc_st0 + * @brief Contains register fields associated with lc_st0. definitions. + * @{ + */ +#ifndef __ATLC_LC_ST0_MACRO__ +#define __ATLC_LC_ST0_MACRO__ + +/* macros for field art_cntr */ +/** + * @defgroup at_lc_regs_core_art_cntr_field art_cntr_field + * @brief macros for field art_cntr + * @details number of auto retransmit + * @{ + */ +#define ATLC_LC_ST0__ART_CNTR__SHIFT 0 +#define ATLC_LC_ST0__ART_CNTR__WIDTH 8 +#define ATLC_LC_ST0__ART_CNTR__MASK 0x000000ffU +#define ATLC_LC_ST0__ART_CNTR__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_LC_ST0__ART_CNTR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field artmx_cntr */ +/** + * @defgroup at_lc_regs_core_artmx_cntr_field artmx_cntr_field + * @brief macros for field artmx_cntr + * @details number of times max auto retransmit is exceeded i.e., packet loss + * @{ + */ +#define ATLC_LC_ST0__ARTMX_CNTR__SHIFT 8 +#define ATLC_LC_ST0__ARTMX_CNTR__WIDTH 8 +#define ATLC_LC_ST0__ARTMX_CNTR__MASK 0x0000ff00U +#define ATLC_LC_ST0__ARTMX_CNTR__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define ATLC_LC_ST0__ARTMX_CNTR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field crc_err_cntr */ +/** + * @defgroup at_lc_regs_core_crc_err_cntr_field crc_err_cntr_field + * @brief macros for field crc_err_cntr + * @details number of crc error packets + * @{ + */ +#define ATLC_LC_ST0__CRC_ERR_CNTR__SHIFT 16 +#define ATLC_LC_ST0__CRC_ERR_CNTR__WIDTH 8 +#define ATLC_LC_ST0__CRC_ERR_CNTR__MASK 0x00ff0000U +#define ATLC_LC_ST0__CRC_ERR_CNTR__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define ATLC_LC_ST0__CRC_ERR_CNTR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tx_ack_to_cntr */ +/** + * @defgroup at_lc_regs_core_tx_ack_to_cntr_field tx_ack_to_cntr_field + * @brief macros for field tx_ack_to_cntr + * @details number of tx acknowledgement time out counter + * @{ + */ +#define ATLC_LC_ST0__TX_ACK_TO_CNTR__SHIFT 24 +#define ATLC_LC_ST0__TX_ACK_TO_CNTR__WIDTH 8 +#define ATLC_LC_ST0__TX_ACK_TO_CNTR__MASK 0xff000000U +#define ATLC_LC_ST0__TX_ACK_TO_CNTR__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define ATLC_LC_ST0__TX_ACK_TO_CNTR__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_LC_ST0__TYPE uint32_t +#define ATLC_LC_ST0__READ 0xffffffffU +#define ATLC_LC_ST0__PRESERVED 0x00000000U +#define ATLC_LC_ST0__RESET_VALUE 0x00000000U + +#endif /* __ATLC_LC_ST0_MACRO__ */ + +/** @} end of lc_st0 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_st0_clr */ +/** + * @defgroup at_lc_regs_core_lc_st0_clr lc_st0_clr + * @brief Contains register fields associated with lc_st0_clr. definitions. + * @{ + */ +#ifndef __ATLC_LC_ST0_CLR_MACRO__ +#define __ATLC_LC_ST0_CLR_MACRO__ + +/* macros for field art_cntr */ +/** + * @defgroup at_lc_regs_core_art_cntr_field art_cntr_field + * @brief macros for field art_cntr + * @details write 1 to clear + * @{ + */ +#define ATLC_LC_ST0_CLR__ART_CNTR__SHIFT 0 +#define ATLC_LC_ST0_CLR__ART_CNTR__WIDTH 1 +#define ATLC_LC_ST0_CLR__ART_CNTR__MASK 0x00000001U +#define ATLC_LC_ST0_CLR__ART_CNTR__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATLC_LC_ST0_CLR__ART_CNTR__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define ATLC_LC_ST0_CLR__ART_CNTR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATLC_LC_ST0_CLR__ART_CNTR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define ATLC_LC_ST0_CLR__ART_CNTR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATLC_LC_ST0_CLR__ART_CNTR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATLC_LC_ST0_CLR__ART_CNTR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field artmx_cntr */ +/** + * @defgroup at_lc_regs_core_artmx_cntr_field artmx_cntr_field + * @brief macros for field artmx_cntr + * @details write 1 to clear + * @{ + */ +#define ATLC_LC_ST0_CLR__ARTMX_CNTR__SHIFT 1 +#define ATLC_LC_ST0_CLR__ARTMX_CNTR__WIDTH 1 +#define ATLC_LC_ST0_CLR__ARTMX_CNTR__MASK 0x00000002U +#define ATLC_LC_ST0_CLR__ARTMX_CNTR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define ATLC_LC_ST0_CLR__ARTMX_CNTR__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define ATLC_LC_ST0_CLR__ARTMX_CNTR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define ATLC_LC_ST0_CLR__ARTMX_CNTR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define ATLC_LC_ST0_CLR__ARTMX_CNTR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATLC_LC_ST0_CLR__ARTMX_CNTR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATLC_LC_ST0_CLR__ARTMX_CNTR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field crc_err_cntr */ +/** + * @defgroup at_lc_regs_core_crc_err_cntr_field crc_err_cntr_field + * @brief macros for field crc_err_cntr + * @details write 1 to clear + * @{ + */ +#define ATLC_LC_ST0_CLR__CRC_ERR_CNTR__SHIFT 2 +#define ATLC_LC_ST0_CLR__CRC_ERR_CNTR__WIDTH 1 +#define ATLC_LC_ST0_CLR__CRC_ERR_CNTR__MASK 0x00000004U +#define ATLC_LC_ST0_CLR__CRC_ERR_CNTR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define ATLC_LC_ST0_CLR__CRC_ERR_CNTR__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define ATLC_LC_ST0_CLR__CRC_ERR_CNTR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define ATLC_LC_ST0_CLR__CRC_ERR_CNTR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define ATLC_LC_ST0_CLR__CRC_ERR_CNTR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define ATLC_LC_ST0_CLR__CRC_ERR_CNTR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define ATLC_LC_ST0_CLR__CRC_ERR_CNTR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tx_ack_to_cntr */ +/** + * @defgroup at_lc_regs_core_tx_ack_to_cntr_field tx_ack_to_cntr_field + * @brief macros for field tx_ack_to_cntr + * @details write 1 to clear + * @{ + */ +#define ATLC_LC_ST0_CLR__TX_ACK_TO_CNTR__SHIFT 3 +#define ATLC_LC_ST0_CLR__TX_ACK_TO_CNTR__WIDTH 1 +#define ATLC_LC_ST0_CLR__TX_ACK_TO_CNTR__MASK 0x00000008U +#define ATLC_LC_ST0_CLR__TX_ACK_TO_CNTR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define ATLC_LC_ST0_CLR__TX_ACK_TO_CNTR__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define ATLC_LC_ST0_CLR__TX_ACK_TO_CNTR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define ATLC_LC_ST0_CLR__TX_ACK_TO_CNTR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define ATLC_LC_ST0_CLR__TX_ACK_TO_CNTR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define ATLC_LC_ST0_CLR__TX_ACK_TO_CNTR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define ATLC_LC_ST0_CLR__TX_ACK_TO_CNTR__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_LC_ST0_CLR__TYPE uint32_t +#define ATLC_LC_ST0_CLR__READ 0x0000000fU +#define ATLC_LC_ST0_CLR__WRITE 0x0000000fU +#define ATLC_LC_ST0_CLR__PRESERVED 0x00000000U +#define ATLC_LC_ST0_CLR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_LC_ST0_CLR_MACRO__ */ + +/** @} end of lc_st0_clr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_st1 */ +/** + * @defgroup at_lc_regs_core_lc_st1 lc_st1 + * @brief Contains register fields associated with lc_st1. definitions. + * @{ + */ +#ifndef __ATLC_LC_ST1_MACRO__ +#define __ATLC_LC_ST1_MACRO__ + +/* macros for field fr_p5us_cntr */ +/** + * @defgroup at_lc_regs_core_fr_p5us_cntr_field fr_p5us_cntr_field + * @brief macros for field fr_p5us_cntr + * @details free running 0.5 micro second counter + * @{ + */ +#define ATLC_LC_ST1__FR_P5US_CNTR__SHIFT 0 +#define ATLC_LC_ST1__FR_P5US_CNTR__WIDTH 16 +#define ATLC_LC_ST1__FR_P5US_CNTR__MASK 0x0000ffffU +#define ATLC_LC_ST1__FR_P5US_CNTR__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_LC_ST1__FR_P5US_CNTR__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_LC_ST1__TYPE uint32_t +#define ATLC_LC_ST1__READ 0x0000ffffU +#define ATLC_LC_ST1__PRESERVED 0x00000000U +#define ATLC_LC_ST1__RESET_VALUE 0x00000000U + +#endif /* __ATLC_LC_ST1_MACRO__ */ + +/** @} end of lc_st1 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_st2 */ +/** + * @defgroup at_lc_regs_core_lc_st2 lc_st2 + * @brief Contains register fields associated with lc_st2. definitions. + * @{ + */ +#ifndef __ATLC_LC_ST2_MACRO__ +#define __ATLC_LC_ST2_MACRO__ + +/* macros for field fr_us_cntr */ +/** + * @defgroup at_lc_regs_core_fr_us_cntr_field fr_us_cntr_field + * @brief macros for field fr_us_cntr + * @details free running micro second counter + * @{ + */ +#define ATLC_LC_ST2__FR_US_CNTR__SHIFT 0 +#define ATLC_LC_ST2__FR_US_CNTR__WIDTH 32 +#define ATLC_LC_ST2__FR_US_CNTR__MASK 0xffffffffU +#define ATLC_LC_ST2__FR_US_CNTR__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_LC_ST2__FR_US_CNTR__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_LC_ST2__TYPE uint32_t +#define ATLC_LC_ST2__READ 0xffffffffU +#define ATLC_LC_ST2__PRESERVED 0x00000000U +#define ATLC_LC_ST2__RESET_VALUE 0x00000000U + +#endif /* __ATLC_LC_ST2_MACRO__ */ + +/** @} end of lc_st2 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_st3 */ +/** + * @defgroup at_lc_regs_core_lc_st3 lc_st3 + * @brief Contains register fields associated with lc_st3. definitions. + * @{ + */ +#ifndef __ATLC_LC_ST3_MACRO__ +#define __ATLC_LC_ST3_MACRO__ + +/* macros for field fr_312p5us_cntr */ +/** + * @defgroup at_lc_regs_core_fr_312p5us_cntr_field fr_312p5us_cntr_field + * @brief macros for field fr_312p5us_cntr + * @details free running 312.5 micro second counter + * @{ + */ +#define ATLC_LC_ST3__FR_312P5US_CNTR__SHIFT 0 +#define ATLC_LC_ST3__FR_312P5US_CNTR__WIDTH 32 +#define ATLC_LC_ST3__FR_312P5US_CNTR__MASK 0xffffffffU +#define ATLC_LC_ST3__FR_312P5US_CNTR__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_LC_ST3__FR_312P5US_CNTR__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_LC_ST3__TYPE uint32_t +#define ATLC_LC_ST3__READ 0xffffffffU +#define ATLC_LC_ST3__PRESERVED 0x00000000U +#define ATLC_LC_ST3__RESET_VALUE 0x00000000U + +#endif /* __ATLC_LC_ST3_MACRO__ */ + +/** @} end of lc_st3 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_st4 */ +/** + * @defgroup at_lc_regs_core_lc_st4 lc_st4 + * @brief Contains register fields associated with lc_st4. definitions. + * @{ + */ +#ifndef __ATLC_LC_ST4_MACRO__ +#define __ATLC_LC_ST4_MACRO__ + +/* macros for field flw_st */ +/** + * @defgroup at_lc_regs_core_flw_st_field flw_st_field + * @brief macros for field flw_st + * @details event flow state machine state + * @{ + */ +#define ATLC_LC_ST4__FLW_ST__SHIFT 0 +#define ATLC_LC_ST4__FLW_ST__WIDTH 8 +#define ATLC_LC_ST4__FLW_ST__MASK 0x000000ffU +#define ATLC_LC_ST4__FLW_ST__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_LC_ST4__FLW_ST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pkt_st */ +/** + * @defgroup at_lc_regs_core_pkt_st_field pkt_st_field + * @brief macros for field pkt_st + * @details packet parser state machine state + * @{ + */ +#define ATLC_LC_ST4__PKT_ST__SHIFT 8 +#define ATLC_LC_ST4__PKT_ST__WIDTH 8 +#define ATLC_LC_ST4__PKT_ST__MASK 0x0000ff00U +#define ATLC_LC_ST4__PKT_ST__READ(src) (((uint32_t)(src) & 0x0000ff00U) >> 8) +#define ATLC_LC_ST4__PKT_ST__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_LC_ST4__TYPE uint32_t +#define ATLC_LC_ST4__READ 0x0000ffffU +#define ATLC_LC_ST4__PRESERVED 0x00000000U +#define ATLC_LC_ST4__RESET_VALUE 0x00000000U + +#endif /* __ATLC_LC_ST4_MACRO__ */ + +/** @} end of lc_st4 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tx_st */ +/** + * @defgroup at_lc_regs_core_tx_st tx_st + * @brief Contains register fields associated with tx_st. definitions. + * @{ + */ +#ifndef __ATLC_TX_ST_MACRO__ +#define __ATLC_TX_ST_MACRO__ + +/* macros for field tm_stmp */ +/** + * @defgroup at_lc_regs_core_tm_stmp_field tm_stmp_field + * @brief macros for field tm_stmp + * @details tx start packet (1st bit of preamble) time stamp in micro seconds + * @{ + */ +#define ATLC_TX_ST__TM_STMP__SHIFT 0 +#define ATLC_TX_ST__TM_STMP__WIDTH 32 +#define ATLC_TX_ST__TM_STMP__MASK 0xffffffffU +#define ATLC_TX_ST__TM_STMP__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_TX_ST__TM_STMP__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_TX_ST__TYPE uint32_t +#define ATLC_TX_ST__READ 0xffffffffU +#define ATLC_TX_ST__PRESERVED 0x00000000U +#define ATLC_TX_ST__RESET_VALUE 0x00000000U + +#endif /* __ATLC_TX_ST_MACRO__ */ + +/** @} end of tx_st */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tx_ed */ +/** + * @defgroup at_lc_regs_core_tx_ed tx_ed + * @brief Contains register fields associated with tx_ed. definitions. + * @{ + */ +#ifndef __ATLC_TX_ED_MACRO__ +#define __ATLC_TX_ED_MACRO__ + +/* macros for field tm_stmp */ +/** + * @defgroup at_lc_regs_core_tm_stmp_field tm_stmp_field + * @brief macros for field tm_stmp + * @details tx end packet (last bit of crc) time stamp in micro seconds + * @{ + */ +#define ATLC_TX_ED__TM_STMP__SHIFT 0 +#define ATLC_TX_ED__TM_STMP__WIDTH 32 +#define ATLC_TX_ED__TM_STMP__MASK 0xffffffffU +#define ATLC_TX_ED__TM_STMP__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_TX_ED__TM_STMP__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_TX_ED__TYPE uint32_t +#define ATLC_TX_ED__READ 0xffffffffU +#define ATLC_TX_ED__PRESERVED 0x00000000U +#define ATLC_TX_ED__RESET_VALUE 0x00000000U + +#endif /* __ATLC_TX_ED_MACRO__ */ + +/** @} end of tx_ed */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rx_st */ +/** + * @defgroup at_lc_regs_core_rx_st rx_st + * @brief Contains register fields associated with rx_st. definitions. + * @{ + */ +#ifndef __ATLC_RX_ST_MACRO__ +#define __ATLC_RX_ST_MACRO__ + +/* macros for field tm_stmp */ +/** + * @defgroup at_lc_regs_core_tm_stmp_field tm_stmp_field + * @brief macros for field tm_stmp + * @details rx start packet (1st bit after access address found) time stamp in micro seconds + * @{ + */ +#define ATLC_RX_ST__TM_STMP__SHIFT 0 +#define ATLC_RX_ST__TM_STMP__WIDTH 32 +#define ATLC_RX_ST__TM_STMP__MASK 0xffffffffU +#define ATLC_RX_ST__TM_STMP__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_RX_ST__TM_STMP__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RX_ST__TYPE uint32_t +#define ATLC_RX_ST__READ 0xffffffffU +#define ATLC_RX_ST__PRESERVED 0x00000000U +#define ATLC_RX_ST__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RX_ST_MACRO__ */ + +/** @} end of rx_st */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rx_ed */ +/** + * @defgroup at_lc_regs_core_rx_ed rx_ed + * @brief Contains register fields associated with rx_ed. definitions. + * @{ + */ +#ifndef __ATLC_RX_ED_MACRO__ +#define __ATLC_RX_ED_MACRO__ + +/* macros for field tm_stmp */ +/** + * @defgroup at_lc_regs_core_tm_stmp_field tm_stmp_field + * @brief macros for field tm_stmp + * @details rx end packet (last bit of crc) time stamp in micro seconds + * @{ + */ +#define ATLC_RX_ED__TM_STMP__SHIFT 0 +#define ATLC_RX_ED__TM_STMP__WIDTH 32 +#define ATLC_RX_ED__TM_STMP__MASK 0xffffffffU +#define ATLC_RX_ED__TM_STMP__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_RX_ED__TM_STMP__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RX_ED__TYPE uint32_t +#define ATLC_RX_ED__READ 0xffffffffU +#define ATLC_RX_ED__PRESERVED 0x00000000U +#define ATLC_RX_ED__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RX_ED_MACRO__ */ + +/** @} end of rx_ed */ + +/* macros for BlueprintGlobalNameSpace::ATLC_wht_ctrl */ +/** + * @defgroup at_lc_regs_core_wht_ctrl wht_ctrl + * @brief Contains register fields associated with wht_ctrl. definitions. + * @{ + */ +#ifndef __ATLC_WHT_CTRL_MACRO__ +#define __ATLC_WHT_CTRL_MACRO__ + +/* macros for field sd */ +/** + * @defgroup at_lc_regs_core_sd_field sd_field + * @brief macros for field sd + * @details initial seed for whitening + * @{ + */ +#define ATLC_WHT_CTRL__SD__SHIFT 0 +#define ATLC_WHT_CTRL__SD__WIDTH 8 +#define ATLC_WHT_CTRL__SD__MASK 0x000000ffU +#define ATLC_WHT_CTRL__SD__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_WHT_CTRL__SD__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_WHT_CTRL__SD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define ATLC_WHT_CTRL__SD__VERIFY(src) (!(((uint32_t)(src) & ~0x000000ffU))) +#define ATLC_WHT_CTRL__SD__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_WHT_CTRL__TYPE uint32_t +#define ATLC_WHT_CTRL__READ 0x000000ffU +#define ATLC_WHT_CTRL__WRITE 0x000000ffU +#define ATLC_WHT_CTRL__PRESERVED 0x00000000U +#define ATLC_WHT_CTRL__RESET_VALUE 0x00000000U + +#endif /* __ATLC_WHT_CTRL_MACRO__ */ + +/** @} end of wht_ctrl */ + +/* macros for BlueprintGlobalNameSpace::ATLC_nd_ctrl */ +/** + * @defgroup at_lc_regs_core_nd_ctrl nd_ctrl + * @brief Contains register fields associated with nd_ctrl. definitions. + * @{ + */ +#ifndef __ATLC_ND_CTRL_MACRO__ +#define __ATLC_ND_CTRL_MACRO__ + +/* macros for field nd0_en */ +/** + * @defgroup at_lc_regs_core_nd0_en_field nd0_en_field + * @brief macros for field nd0_en + * @details enable receive node 0 + * @{ + */ +#define ATLC_ND_CTRL__ND0_EN__SHIFT 0 +#define ATLC_ND_CTRL__ND0_EN__WIDTH 1 +#define ATLC_ND_CTRL__ND0_EN__MASK 0x00000001U +#define ATLC_ND_CTRL__ND0_EN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATLC_ND_CTRL__ND0_EN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define ATLC_ND_CTRL__ND0_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATLC_ND_CTRL__ND0_EN__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define ATLC_ND_CTRL__ND0_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATLC_ND_CTRL__ND0_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATLC_ND_CTRL__ND0_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nd1_en */ +/** + * @defgroup at_lc_regs_core_nd1_en_field nd1_en_field + * @brief macros for field nd1_en + * @details enable receive node 1 + * @{ + */ +#define ATLC_ND_CTRL__ND1_EN__SHIFT 1 +#define ATLC_ND_CTRL__ND1_EN__WIDTH 1 +#define ATLC_ND_CTRL__ND1_EN__MASK 0x00000002U +#define ATLC_ND_CTRL__ND1_EN__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define ATLC_ND_CTRL__ND1_EN__WRITE(src) (((uint32_t)(src) << 1) & 0x00000002U) +#define ATLC_ND_CTRL__ND1_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define ATLC_ND_CTRL__ND1_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define ATLC_ND_CTRL__ND1_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATLC_ND_CTRL__ND1_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATLC_ND_CTRL__ND1_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nd2_en */ +/** + * @defgroup at_lc_regs_core_nd2_en_field nd2_en_field + * @brief macros for field nd2_en + * @details enable receive node 2 + * @{ + */ +#define ATLC_ND_CTRL__ND2_EN__SHIFT 2 +#define ATLC_ND_CTRL__ND2_EN__WIDTH 1 +#define ATLC_ND_CTRL__ND2_EN__MASK 0x00000004U +#define ATLC_ND_CTRL__ND2_EN__READ(src) (((uint32_t)(src) & 0x00000004U) >> 2) +#define ATLC_ND_CTRL__ND2_EN__WRITE(src) (((uint32_t)(src) << 2) & 0x00000004U) +#define ATLC_ND_CTRL__ND2_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define ATLC_ND_CTRL__ND2_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define ATLC_ND_CTRL__ND2_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define ATLC_ND_CTRL__ND2_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define ATLC_ND_CTRL__ND2_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nd3_en */ +/** + * @defgroup at_lc_regs_core_nd3_en_field nd3_en_field + * @brief macros for field nd3_en + * @details enable receive node 3 + * @{ + */ +#define ATLC_ND_CTRL__ND3_EN__SHIFT 3 +#define ATLC_ND_CTRL__ND3_EN__WIDTH 1 +#define ATLC_ND_CTRL__ND3_EN__MASK 0x00000008U +#define ATLC_ND_CTRL__ND3_EN__READ(src) (((uint32_t)(src) & 0x00000008U) >> 3) +#define ATLC_ND_CTRL__ND3_EN__WRITE(src) (((uint32_t)(src) << 3) & 0x00000008U) +#define ATLC_ND_CTRL__ND3_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define ATLC_ND_CTRL__ND3_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define ATLC_ND_CTRL__ND3_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define ATLC_ND_CTRL__ND3_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define ATLC_ND_CTRL__ND3_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nd4_en */ +/** + * @defgroup at_lc_regs_core_nd4_en_field nd4_en_field + * @brief macros for field nd4_en + * @details enable receive node 4 + * @{ + */ +#define ATLC_ND_CTRL__ND4_EN__SHIFT 4 +#define ATLC_ND_CTRL__ND4_EN__WIDTH 1 +#define ATLC_ND_CTRL__ND4_EN__MASK 0x00000010U +#define ATLC_ND_CTRL__ND4_EN__READ(src) (((uint32_t)(src) & 0x00000010U) >> 4) +#define ATLC_ND_CTRL__ND4_EN__WRITE(src) (((uint32_t)(src) << 4) & 0x00000010U) +#define ATLC_ND_CTRL__ND4_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define ATLC_ND_CTRL__ND4_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define ATLC_ND_CTRL__ND4_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define ATLC_ND_CTRL__ND4_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define ATLC_ND_CTRL__ND4_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nd5_en */ +/** + * @defgroup at_lc_regs_core_nd5_en_field nd5_en_field + * @brief macros for field nd5_en + * @details enable receive node 5 + * @{ + */ +#define ATLC_ND_CTRL__ND5_EN__SHIFT 5 +#define ATLC_ND_CTRL__ND5_EN__WIDTH 1 +#define ATLC_ND_CTRL__ND5_EN__MASK 0x00000020U +#define ATLC_ND_CTRL__ND5_EN__READ(src) (((uint32_t)(src) & 0x00000020U) >> 5) +#define ATLC_ND_CTRL__ND5_EN__WRITE(src) (((uint32_t)(src) << 5) & 0x00000020U) +#define ATLC_ND_CTRL__ND5_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define ATLC_ND_CTRL__ND5_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define ATLC_ND_CTRL__ND5_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define ATLC_ND_CTRL__ND5_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define ATLC_ND_CTRL__ND5_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nd6_en */ +/** + * @defgroup at_lc_regs_core_nd6_en_field nd6_en_field + * @brief macros for field nd6_en + * @details enable receive node 6 + * @{ + */ +#define ATLC_ND_CTRL__ND6_EN__SHIFT 6 +#define ATLC_ND_CTRL__ND6_EN__WIDTH 1 +#define ATLC_ND_CTRL__ND6_EN__MASK 0x00000040U +#define ATLC_ND_CTRL__ND6_EN__READ(src) (((uint32_t)(src) & 0x00000040U) >> 6) +#define ATLC_ND_CTRL__ND6_EN__WRITE(src) (((uint32_t)(src) << 6) & 0x00000040U) +#define ATLC_ND_CTRL__ND6_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define ATLC_ND_CTRL__ND6_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define ATLC_ND_CTRL__ND6_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define ATLC_ND_CTRL__ND6_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define ATLC_ND_CTRL__ND6_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field nd7_en */ +/** + * @defgroup at_lc_regs_core_nd7_en_field nd7_en_field + * @brief macros for field nd7_en + * @details enable receive node 7 + * @{ + */ +#define ATLC_ND_CTRL__ND7_EN__SHIFT 7 +#define ATLC_ND_CTRL__ND7_EN__WIDTH 1 +#define ATLC_ND_CTRL__ND7_EN__MASK 0x00000080U +#define ATLC_ND_CTRL__ND7_EN__READ(src) (((uint32_t)(src) & 0x00000080U) >> 7) +#define ATLC_ND_CTRL__ND7_EN__WRITE(src) (((uint32_t)(src) << 7) & 0x00000080U) +#define ATLC_ND_CTRL__ND7_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define ATLC_ND_CTRL__ND7_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define ATLC_ND_CTRL__ND7_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define ATLC_ND_CTRL__ND7_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define ATLC_ND_CTRL__ND7_EN__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_ND_CTRL__TYPE uint32_t +#define ATLC_ND_CTRL__READ 0x000000ffU +#define ATLC_ND_CTRL__WRITE 0x000000ffU +#define ATLC_ND_CTRL__PRESERVED 0x00000000U +#define ATLC_ND_CTRL__RESET_VALUE 0x00000000U + +#endif /* __ATLC_ND_CTRL_MACRO__ */ + +/** @} end of nd_ctrl */ + +/* macros for BlueprintGlobalNameSpace::ATLC_sync_wrd0 */ +/** + * @defgroup at_lc_regs_core_sync_wrd0 sync_wrd0 + * @brief Contains register fields associated with sync_wrd0. definitions. + * @{ + */ +#ifndef __ATLC_SYNC_WRD0_MACRO__ +#define __ATLC_SYNC_WRD0_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details synchronization word 0 + * @{ + */ +#define ATLC_SYNC_WRD0__VL__SHIFT 0 +#define ATLC_SYNC_WRD0__VL__WIDTH 32 +#define ATLC_SYNC_WRD0__VL__MASK 0xffffffffU +#define ATLC_SYNC_WRD0__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_SYNC_WRD0__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_SYNC_WRD0__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_SYNC_WRD0__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_SYNC_WRD0__VL__RESET_VALUE 0x8e89bed6U +/** @} */ +#define ATLC_SYNC_WRD0__TYPE uint32_t +#define ATLC_SYNC_WRD0__READ 0xffffffffU +#define ATLC_SYNC_WRD0__WRITE 0xffffffffU +#define ATLC_SYNC_WRD0__PRESERVED 0x00000000U +#define ATLC_SYNC_WRD0__RESET_VALUE 0x8e89bed6U + +#endif /* __ATLC_SYNC_WRD0_MACRO__ */ + +/** @} end of sync_wrd0 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_sync_wrd1 */ +/** + * @defgroup at_lc_regs_core_sync_wrd1 sync_wrd1 + * @brief Contains register fields associated with sync_wrd1. definitions. + * @{ + */ +#ifndef __ATLC_SYNC_WRD1_MACRO__ +#define __ATLC_SYNC_WRD1_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details synchronization word 1 + * @{ + */ +#define ATLC_SYNC_WRD1__VL__SHIFT 0 +#define ATLC_SYNC_WRD1__VL__WIDTH 32 +#define ATLC_SYNC_WRD1__VL__MASK 0xffffffffU +#define ATLC_SYNC_WRD1__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_SYNC_WRD1__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_SYNC_WRD1__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_SYNC_WRD1__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_SYNC_WRD1__VL__RESET_VALUE 0x5367a431U +/** @} */ +#define ATLC_SYNC_WRD1__TYPE uint32_t +#define ATLC_SYNC_WRD1__READ 0xffffffffU +#define ATLC_SYNC_WRD1__WRITE 0xffffffffU +#define ATLC_SYNC_WRD1__PRESERVED 0x00000000U +#define ATLC_SYNC_WRD1__RESET_VALUE 0x5367a431U + +#endif /* __ATLC_SYNC_WRD1_MACRO__ */ + +/** @} end of sync_wrd1 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rx_addr0 */ +/** + * @defgroup at_lc_regs_core_rx_addr0 rx_addr0 + * @brief Contains register fields associated with rx_addr0. definitions. + * @{ + */ +#ifndef __ATLC_RX_ADDR0_MACRO__ +#define __ATLC_RX_ADDR0_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx addr of rx node 0 and tx_addr for tx node 0 + * @{ + */ +#define ATLC_RX_ADDR0__VL__SHIFT 0 +#define ATLC_RX_ADDR0__VL__WIDTH 8 +#define ATLC_RX_ADDR0__VL__MASK 0x000000ffU +#define ATLC_RX_ADDR0__VL__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_RX_ADDR0__VL__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_RX_ADDR0__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define ATLC_RX_ADDR0__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x000000ffU))) +#define ATLC_RX_ADDR0__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RX_ADDR0__TYPE uint32_t +#define ATLC_RX_ADDR0__READ 0x000000ffU +#define ATLC_RX_ADDR0__WRITE 0x000000ffU +#define ATLC_RX_ADDR0__PRESERVED 0x00000000U +#define ATLC_RX_ADDR0__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RX_ADDR0_MACRO__ */ + +/** @} end of rx_addr0 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rx_addr1 */ +/** + * @defgroup at_lc_regs_core_rx_addr1 rx_addr1 + * @brief Contains register fields associated with rx_addr1. definitions. + * @{ + */ +#ifndef __ATLC_RX_ADDR1_MACRO__ +#define __ATLC_RX_ADDR1_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx addr of rx node 1 and tx_addr for tx node 1 + * @{ + */ +#define ATLC_RX_ADDR1__VL__SHIFT 0 +#define ATLC_RX_ADDR1__VL__WIDTH 8 +#define ATLC_RX_ADDR1__VL__MASK 0x000000ffU +#define ATLC_RX_ADDR1__VL__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_RX_ADDR1__VL__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_RX_ADDR1__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define ATLC_RX_ADDR1__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x000000ffU))) +#define ATLC_RX_ADDR1__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RX_ADDR1__TYPE uint32_t +#define ATLC_RX_ADDR1__READ 0x000000ffU +#define ATLC_RX_ADDR1__WRITE 0x000000ffU +#define ATLC_RX_ADDR1__PRESERVED 0x00000000U +#define ATLC_RX_ADDR1__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RX_ADDR1_MACRO__ */ + +/** @} end of rx_addr1 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rx_addr2 */ +/** + * @defgroup at_lc_regs_core_rx_addr2 rx_addr2 + * @brief Contains register fields associated with rx_addr2. definitions. + * @{ + */ +#ifndef __ATLC_RX_ADDR2_MACRO__ +#define __ATLC_RX_ADDR2_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx addr of rx node 2 and tx_addr for tx node 2 + * @{ + */ +#define ATLC_RX_ADDR2__VL__SHIFT 0 +#define ATLC_RX_ADDR2__VL__WIDTH 8 +#define ATLC_RX_ADDR2__VL__MASK 0x000000ffU +#define ATLC_RX_ADDR2__VL__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_RX_ADDR2__VL__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_RX_ADDR2__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define ATLC_RX_ADDR2__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x000000ffU))) +#define ATLC_RX_ADDR2__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RX_ADDR2__TYPE uint32_t +#define ATLC_RX_ADDR2__READ 0x000000ffU +#define ATLC_RX_ADDR2__WRITE 0x000000ffU +#define ATLC_RX_ADDR2__PRESERVED 0x00000000U +#define ATLC_RX_ADDR2__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RX_ADDR2_MACRO__ */ + +/** @} end of rx_addr2 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rx_addr3 */ +/** + * @defgroup at_lc_regs_core_rx_addr3 rx_addr3 + * @brief Contains register fields associated with rx_addr3. definitions. + * @{ + */ +#ifndef __ATLC_RX_ADDR3_MACRO__ +#define __ATLC_RX_ADDR3_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx addr of rx node 3 and tx_addr for tx node 3 + * @{ + */ +#define ATLC_RX_ADDR3__VL__SHIFT 0 +#define ATLC_RX_ADDR3__VL__WIDTH 8 +#define ATLC_RX_ADDR3__VL__MASK 0x000000ffU +#define ATLC_RX_ADDR3__VL__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_RX_ADDR3__VL__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_RX_ADDR3__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define ATLC_RX_ADDR3__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x000000ffU))) +#define ATLC_RX_ADDR3__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RX_ADDR3__TYPE uint32_t +#define ATLC_RX_ADDR3__READ 0x000000ffU +#define ATLC_RX_ADDR3__WRITE 0x000000ffU +#define ATLC_RX_ADDR3__PRESERVED 0x00000000U +#define ATLC_RX_ADDR3__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RX_ADDR3_MACRO__ */ + +/** @} end of rx_addr3 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rx_addr4 */ +/** + * @defgroup at_lc_regs_core_rx_addr4 rx_addr4 + * @brief Contains register fields associated with rx_addr4. definitions. + * @{ + */ +#ifndef __ATLC_RX_ADDR4_MACRO__ +#define __ATLC_RX_ADDR4_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx addr of rx node 4 and tx_addr for tx node 4 + * @{ + */ +#define ATLC_RX_ADDR4__VL__SHIFT 0 +#define ATLC_RX_ADDR4__VL__WIDTH 8 +#define ATLC_RX_ADDR4__VL__MASK 0x000000ffU +#define ATLC_RX_ADDR4__VL__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_RX_ADDR4__VL__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_RX_ADDR4__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define ATLC_RX_ADDR4__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x000000ffU))) +#define ATLC_RX_ADDR4__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RX_ADDR4__TYPE uint32_t +#define ATLC_RX_ADDR4__READ 0x000000ffU +#define ATLC_RX_ADDR4__WRITE 0x000000ffU +#define ATLC_RX_ADDR4__PRESERVED 0x00000000U +#define ATLC_RX_ADDR4__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RX_ADDR4_MACRO__ */ + +/** @} end of rx_addr4 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rx_addr5 */ +/** + * @defgroup at_lc_regs_core_rx_addr5 rx_addr5 + * @brief Contains register fields associated with rx_addr5. definitions. + * @{ + */ +#ifndef __ATLC_RX_ADDR5_MACRO__ +#define __ATLC_RX_ADDR5_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx addr of rx node 5 and tx_addr for tx node 5 + * @{ + */ +#define ATLC_RX_ADDR5__VL__SHIFT 0 +#define ATLC_RX_ADDR5__VL__WIDTH 8 +#define ATLC_RX_ADDR5__VL__MASK 0x000000ffU +#define ATLC_RX_ADDR5__VL__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_RX_ADDR5__VL__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_RX_ADDR5__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define ATLC_RX_ADDR5__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x000000ffU))) +#define ATLC_RX_ADDR5__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RX_ADDR5__TYPE uint32_t +#define ATLC_RX_ADDR5__READ 0x000000ffU +#define ATLC_RX_ADDR5__WRITE 0x000000ffU +#define ATLC_RX_ADDR5__PRESERVED 0x00000000U +#define ATLC_RX_ADDR5__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RX_ADDR5_MACRO__ */ + +/** @} end of rx_addr5 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rx_addr6 */ +/** + * @defgroup at_lc_regs_core_rx_addr6 rx_addr6 + * @brief Contains register fields associated with rx_addr6. definitions. + * @{ + */ +#ifndef __ATLC_RX_ADDR6_MACRO__ +#define __ATLC_RX_ADDR6_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx addr of rx node 6 and tx_addr for tx node 6 + * @{ + */ +#define ATLC_RX_ADDR6__VL__SHIFT 0 +#define ATLC_RX_ADDR6__VL__WIDTH 8 +#define ATLC_RX_ADDR6__VL__MASK 0x000000ffU +#define ATLC_RX_ADDR6__VL__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_RX_ADDR6__VL__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_RX_ADDR6__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define ATLC_RX_ADDR6__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x000000ffU))) +#define ATLC_RX_ADDR6__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RX_ADDR6__TYPE uint32_t +#define ATLC_RX_ADDR6__READ 0x000000ffU +#define ATLC_RX_ADDR6__WRITE 0x000000ffU +#define ATLC_RX_ADDR6__PRESERVED 0x00000000U +#define ATLC_RX_ADDR6__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RX_ADDR6_MACRO__ */ + +/** @} end of rx_addr6 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rx_addr7 */ +/** + * @defgroup at_lc_regs_core_rx_addr7 rx_addr7 + * @brief Contains register fields associated with rx_addr7. definitions. + * @{ + */ +#ifndef __ATLC_RX_ADDR7_MACRO__ +#define __ATLC_RX_ADDR7_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx addr of rx node 7 and tx_addr for tx node 7 + * @{ + */ +#define ATLC_RX_ADDR7__VL__SHIFT 0 +#define ATLC_RX_ADDR7__VL__WIDTH 8 +#define ATLC_RX_ADDR7__VL__MASK 0x000000ffU +#define ATLC_RX_ADDR7__VL__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_RX_ADDR7__VL__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_RX_ADDR7__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define ATLC_RX_ADDR7__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x000000ffU))) +#define ATLC_RX_ADDR7__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RX_ADDR7__TYPE uint32_t +#define ATLC_RX_ADDR7__READ 0x000000ffU +#define ATLC_RX_ADDR7__WRITE 0x000000ffU +#define ATLC_RX_ADDR7__PRESERVED 0x00000000U +#define ATLC_RX_ADDR7__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RX_ADDR7_MACRO__ */ + +/** @} end of rx_addr7 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff0_addr */ +/** + * @defgroup at_lc_regs_core_tff0_addr tff0_addr + * @brief Contains register fields associated with tff0_addr. definitions. + * @{ + */ +#ifndef __ATLC_TFF0_ADDR_MACRO__ +#define __ATLC_TFF0_ADDR_MACRO__ + +/* macros for field st */ +/** + * @defgroup at_lc_regs_core_st_field st_field + * @brief macros for field st + * @details tx fifo node 0 start addr + * @{ + */ +#define ATLC_TFF0_ADDR__ST__SHIFT 0 +#define ATLC_TFF0_ADDR__ST__WIDTH 16 +#define ATLC_TFF0_ADDR__ST__MASK 0x0000ffffU +#define ATLC_TFF0_ADDR__ST__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF0_ADDR__ST__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF0_ADDR__ST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_TFF0_ADDR__ST__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_TFF0_ADDR__ST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ed */ +/** + * @defgroup at_lc_regs_core_ed_field ed_field + * @brief macros for field ed + * @details tx fifo node 0 end addr + * @{ + */ +#define ATLC_TFF0_ADDR__ED__SHIFT 16 +#define ATLC_TFF0_ADDR__ED__WIDTH 16 +#define ATLC_TFF0_ADDR__ED__MASK 0xffff0000U +#define ATLC_TFF0_ADDR__ED__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define ATLC_TFF0_ADDR__ED__WRITE(src) (((uint32_t)(src) << 16) & 0xffff0000U) +#define ATLC_TFF0_ADDR__ED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define ATLC_TFF0_ADDR__ED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define ATLC_TFF0_ADDR__ED__RESET_VALUE 0x0000031eU +/** @} */ +#define ATLC_TFF0_ADDR__TYPE uint32_t +#define ATLC_TFF0_ADDR__READ 0xffffffffU +#define ATLC_TFF0_ADDR__WRITE 0xffffffffU +#define ATLC_TFF0_ADDR__PRESERVED 0x00000000U +#define ATLC_TFF0_ADDR__RESET_VALUE 0x031e0000U + +#endif /* __ATLC_TFF0_ADDR_MACRO__ */ + +/** @} end of tff0_addr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff0_addr */ +/** + * @defgroup at_lc_regs_core_rff0_addr rff0_addr + * @brief Contains register fields associated with rff0_addr. definitions. + * @{ + */ +#ifndef __ATLC_RFF0_ADDR_MACRO__ +#define __ATLC_RFF0_ADDR_MACRO__ + +/* macros for field st */ +/** + * @defgroup at_lc_regs_core_st_field st_field + * @brief macros for field st + * @details rx fifo node 0 start addr + * @{ + */ +#define ATLC_RFF0_ADDR__ST__SHIFT 0 +#define ATLC_RFF0_ADDR__ST__WIDTH 16 +#define ATLC_RFF0_ADDR__ST__MASK 0x0000ffffU +#define ATLC_RFF0_ADDR__ST__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF0_ADDR__ST__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF0_ADDR__ST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_RFF0_ADDR__ST__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_RFF0_ADDR__ST__RESET_VALUE 0x00000320U +/** @} */ + +/* macros for field ed */ +/** + * @defgroup at_lc_regs_core_ed_field ed_field + * @brief macros for field ed + * @details rx fifo node 0 end addr + * @{ + */ +#define ATLC_RFF0_ADDR__ED__SHIFT 16 +#define ATLC_RFF0_ADDR__ED__WIDTH 16 +#define ATLC_RFF0_ADDR__ED__MASK 0xffff0000U +#define ATLC_RFF0_ADDR__ED__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define ATLC_RFF0_ADDR__ED__WRITE(src) (((uint32_t)(src) << 16) & 0xffff0000U) +#define ATLC_RFF0_ADDR__ED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define ATLC_RFF0_ADDR__ED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define ATLC_RFF0_ADDR__ED__RESET_VALUE 0x0000063eU +/** @} */ +#define ATLC_RFF0_ADDR__TYPE uint32_t +#define ATLC_RFF0_ADDR__READ 0xffffffffU +#define ATLC_RFF0_ADDR__WRITE 0xffffffffU +#define ATLC_RFF0_ADDR__PRESERVED 0x00000000U +#define ATLC_RFF0_ADDR__RESET_VALUE 0x063e0320U + +#endif /* __ATLC_RFF0_ADDR_MACRO__ */ + +/** @} end of rff0_addr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff1_addr */ +/** + * @defgroup at_lc_regs_core_tff1_addr tff1_addr + * @brief Contains register fields associated with tff1_addr. definitions. + * @{ + */ +#ifndef __ATLC_TFF1_ADDR_MACRO__ +#define __ATLC_TFF1_ADDR_MACRO__ + +/* macros for field st */ +/** + * @defgroup at_lc_regs_core_st_field st_field + * @brief macros for field st + * @details tx fifo node 1 start addr + * @{ + */ +#define ATLC_TFF1_ADDR__ST__SHIFT 0 +#define ATLC_TFF1_ADDR__ST__WIDTH 16 +#define ATLC_TFF1_ADDR__ST__MASK 0x0000ffffU +#define ATLC_TFF1_ADDR__ST__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF1_ADDR__ST__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF1_ADDR__ST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_TFF1_ADDR__ST__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_TFF1_ADDR__ST__RESET_VALUE 0x00000640U +/** @} */ + +/* macros for field ed */ +/** + * @defgroup at_lc_regs_core_ed_field ed_field + * @brief macros for field ed + * @details tx fifo node 1 end addr + * @{ + */ +#define ATLC_TFF1_ADDR__ED__SHIFT 16 +#define ATLC_TFF1_ADDR__ED__WIDTH 16 +#define ATLC_TFF1_ADDR__ED__MASK 0xffff0000U +#define ATLC_TFF1_ADDR__ED__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define ATLC_TFF1_ADDR__ED__WRITE(src) (((uint32_t)(src) << 16) & 0xffff0000U) +#define ATLC_TFF1_ADDR__ED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define ATLC_TFF1_ADDR__ED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define ATLC_TFF1_ADDR__ED__RESET_VALUE 0x0000095eU +/** @} */ +#define ATLC_TFF1_ADDR__TYPE uint32_t +#define ATLC_TFF1_ADDR__READ 0xffffffffU +#define ATLC_TFF1_ADDR__WRITE 0xffffffffU +#define ATLC_TFF1_ADDR__PRESERVED 0x00000000U +#define ATLC_TFF1_ADDR__RESET_VALUE 0x095e0640U + +#endif /* __ATLC_TFF1_ADDR_MACRO__ */ + +/** @} end of tff1_addr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff1_addr */ +/** + * @defgroup at_lc_regs_core_rff1_addr rff1_addr + * @brief Contains register fields associated with rff1_addr. definitions. + * @{ + */ +#ifndef __ATLC_RFF1_ADDR_MACRO__ +#define __ATLC_RFF1_ADDR_MACRO__ + +/* macros for field st */ +/** + * @defgroup at_lc_regs_core_st_field st_field + * @brief macros for field st + * @details rx fifo node 1 start addr + * @{ + */ +#define ATLC_RFF1_ADDR__ST__SHIFT 0 +#define ATLC_RFF1_ADDR__ST__WIDTH 16 +#define ATLC_RFF1_ADDR__ST__MASK 0x0000ffffU +#define ATLC_RFF1_ADDR__ST__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF1_ADDR__ST__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF1_ADDR__ST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_RFF1_ADDR__ST__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_RFF1_ADDR__ST__RESET_VALUE 0x00000960U +/** @} */ + +/* macros for field ed */ +/** + * @defgroup at_lc_regs_core_ed_field ed_field + * @brief macros for field ed + * @details rx fifo node 1 end addr + * @{ + */ +#define ATLC_RFF1_ADDR__ED__SHIFT 16 +#define ATLC_RFF1_ADDR__ED__WIDTH 16 +#define ATLC_RFF1_ADDR__ED__MASK 0xffff0000U +#define ATLC_RFF1_ADDR__ED__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define ATLC_RFF1_ADDR__ED__WRITE(src) (((uint32_t)(src) << 16) & 0xffff0000U) +#define ATLC_RFF1_ADDR__ED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define ATLC_RFF1_ADDR__ED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define ATLC_RFF1_ADDR__ED__RESET_VALUE 0x00000c7eU +/** @} */ +#define ATLC_RFF1_ADDR__TYPE uint32_t +#define ATLC_RFF1_ADDR__READ 0xffffffffU +#define ATLC_RFF1_ADDR__WRITE 0xffffffffU +#define ATLC_RFF1_ADDR__PRESERVED 0x00000000U +#define ATLC_RFF1_ADDR__RESET_VALUE 0x0c7e0960U + +#endif /* __ATLC_RFF1_ADDR_MACRO__ */ + +/** @} end of rff1_addr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff2_addr */ +/** + * @defgroup at_lc_regs_core_tff2_addr tff2_addr + * @brief Contains register fields associated with tff2_addr. definitions. + * @{ + */ +#ifndef __ATLC_TFF2_ADDR_MACRO__ +#define __ATLC_TFF2_ADDR_MACRO__ + +/* macros for field st */ +/** + * @defgroup at_lc_regs_core_st_field st_field + * @brief macros for field st + * @details tx fifo node 2 start addr + * @{ + */ +#define ATLC_TFF2_ADDR__ST__SHIFT 0 +#define ATLC_TFF2_ADDR__ST__WIDTH 16 +#define ATLC_TFF2_ADDR__ST__MASK 0x0000ffffU +#define ATLC_TFF2_ADDR__ST__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF2_ADDR__ST__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF2_ADDR__ST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_TFF2_ADDR__ST__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_TFF2_ADDR__ST__RESET_VALUE 0x00000c80U +/** @} */ + +/* macros for field ed */ +/** + * @defgroup at_lc_regs_core_ed_field ed_field + * @brief macros for field ed + * @details tx fifo node 2 end addr + * @{ + */ +#define ATLC_TFF2_ADDR__ED__SHIFT 16 +#define ATLC_TFF2_ADDR__ED__WIDTH 16 +#define ATLC_TFF2_ADDR__ED__MASK 0xffff0000U +#define ATLC_TFF2_ADDR__ED__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define ATLC_TFF2_ADDR__ED__WRITE(src) (((uint32_t)(src) << 16) & 0xffff0000U) +#define ATLC_TFF2_ADDR__ED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define ATLC_TFF2_ADDR__ED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define ATLC_TFF2_ADDR__ED__RESET_VALUE 0x00000f9eU +/** @} */ +#define ATLC_TFF2_ADDR__TYPE uint32_t +#define ATLC_TFF2_ADDR__READ 0xffffffffU +#define ATLC_TFF2_ADDR__WRITE 0xffffffffU +#define ATLC_TFF2_ADDR__PRESERVED 0x00000000U +#define ATLC_TFF2_ADDR__RESET_VALUE 0x0f9e0c80U + +#endif /* __ATLC_TFF2_ADDR_MACRO__ */ + +/** @} end of tff2_addr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff2_addr */ +/** + * @defgroup at_lc_regs_core_rff2_addr rff2_addr + * @brief Contains register fields associated with rff2_addr. definitions. + * @{ + */ +#ifndef __ATLC_RFF2_ADDR_MACRO__ +#define __ATLC_RFF2_ADDR_MACRO__ + +/* macros for field st */ +/** + * @defgroup at_lc_regs_core_st_field st_field + * @brief macros for field st + * @details rx fifo node 2 start addr + * @{ + */ +#define ATLC_RFF2_ADDR__ST__SHIFT 0 +#define ATLC_RFF2_ADDR__ST__WIDTH 16 +#define ATLC_RFF2_ADDR__ST__MASK 0x0000ffffU +#define ATLC_RFF2_ADDR__ST__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF2_ADDR__ST__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF2_ADDR__ST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_RFF2_ADDR__ST__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_RFF2_ADDR__ST__RESET_VALUE 0x00000fa0U +/** @} */ + +/* macros for field ed */ +/** + * @defgroup at_lc_regs_core_ed_field ed_field + * @brief macros for field ed + * @details rx fifo node 2 end addr + * @{ + */ +#define ATLC_RFF2_ADDR__ED__SHIFT 16 +#define ATLC_RFF2_ADDR__ED__WIDTH 16 +#define ATLC_RFF2_ADDR__ED__MASK 0xffff0000U +#define ATLC_RFF2_ADDR__ED__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define ATLC_RFF2_ADDR__ED__WRITE(src) (((uint32_t)(src) << 16) & 0xffff0000U) +#define ATLC_RFF2_ADDR__ED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define ATLC_RFF2_ADDR__ED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define ATLC_RFF2_ADDR__ED__RESET_VALUE 0x000012beU +/** @} */ +#define ATLC_RFF2_ADDR__TYPE uint32_t +#define ATLC_RFF2_ADDR__READ 0xffffffffU +#define ATLC_RFF2_ADDR__WRITE 0xffffffffU +#define ATLC_RFF2_ADDR__PRESERVED 0x00000000U +#define ATLC_RFF2_ADDR__RESET_VALUE 0x12be0fa0U + +#endif /* __ATLC_RFF2_ADDR_MACRO__ */ + +/** @} end of rff2_addr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff3_addr */ +/** + * @defgroup at_lc_regs_core_tff3_addr tff3_addr + * @brief Contains register fields associated with tff3_addr. definitions. + * @{ + */ +#ifndef __ATLC_TFF3_ADDR_MACRO__ +#define __ATLC_TFF3_ADDR_MACRO__ + +/* macros for field st */ +/** + * @defgroup at_lc_regs_core_st_field st_field + * @brief macros for field st + * @details tx fifo node 3 start addr + * @{ + */ +#define ATLC_TFF3_ADDR__ST__SHIFT 0 +#define ATLC_TFF3_ADDR__ST__WIDTH 16 +#define ATLC_TFF3_ADDR__ST__MASK 0x0000ffffU +#define ATLC_TFF3_ADDR__ST__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF3_ADDR__ST__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF3_ADDR__ST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_TFF3_ADDR__ST__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_TFF3_ADDR__ST__RESET_VALUE 0x000012c0U +/** @} */ + +/* macros for field ed */ +/** + * @defgroup at_lc_regs_core_ed_field ed_field + * @brief macros for field ed + * @details tx fifo node 3 end addr + * @{ + */ +#define ATLC_TFF3_ADDR__ED__SHIFT 16 +#define ATLC_TFF3_ADDR__ED__WIDTH 16 +#define ATLC_TFF3_ADDR__ED__MASK 0xffff0000U +#define ATLC_TFF3_ADDR__ED__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define ATLC_TFF3_ADDR__ED__WRITE(src) (((uint32_t)(src) << 16) & 0xffff0000U) +#define ATLC_TFF3_ADDR__ED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define ATLC_TFF3_ADDR__ED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define ATLC_TFF3_ADDR__ED__RESET_VALUE 0x000015deU +/** @} */ +#define ATLC_TFF3_ADDR__TYPE uint32_t +#define ATLC_TFF3_ADDR__READ 0xffffffffU +#define ATLC_TFF3_ADDR__WRITE 0xffffffffU +#define ATLC_TFF3_ADDR__PRESERVED 0x00000000U +#define ATLC_TFF3_ADDR__RESET_VALUE 0x15de12c0U + +#endif /* __ATLC_TFF3_ADDR_MACRO__ */ + +/** @} end of tff3_addr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff3_addr */ +/** + * @defgroup at_lc_regs_core_rff3_addr rff3_addr + * @brief Contains register fields associated with rff3_addr. definitions. + * @{ + */ +#ifndef __ATLC_RFF3_ADDR_MACRO__ +#define __ATLC_RFF3_ADDR_MACRO__ + +/* macros for field st */ +/** + * @defgroup at_lc_regs_core_st_field st_field + * @brief macros for field st + * @details rx fifo node 3 start addr + * @{ + */ +#define ATLC_RFF3_ADDR__ST__SHIFT 0 +#define ATLC_RFF3_ADDR__ST__WIDTH 16 +#define ATLC_RFF3_ADDR__ST__MASK 0x0000ffffU +#define ATLC_RFF3_ADDR__ST__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF3_ADDR__ST__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF3_ADDR__ST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_RFF3_ADDR__ST__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_RFF3_ADDR__ST__RESET_VALUE 0x000015e0U +/** @} */ + +/* macros for field ed */ +/** + * @defgroup at_lc_regs_core_ed_field ed_field + * @brief macros for field ed + * @details rx fifo node 3 end addr + * @{ + */ +#define ATLC_RFF3_ADDR__ED__SHIFT 16 +#define ATLC_RFF3_ADDR__ED__WIDTH 16 +#define ATLC_RFF3_ADDR__ED__MASK 0xffff0000U +#define ATLC_RFF3_ADDR__ED__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define ATLC_RFF3_ADDR__ED__WRITE(src) (((uint32_t)(src) << 16) & 0xffff0000U) +#define ATLC_RFF3_ADDR__ED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define ATLC_RFF3_ADDR__ED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define ATLC_RFF3_ADDR__ED__RESET_VALUE 0x000018feU +/** @} */ +#define ATLC_RFF3_ADDR__TYPE uint32_t +#define ATLC_RFF3_ADDR__READ 0xffffffffU +#define ATLC_RFF3_ADDR__WRITE 0xffffffffU +#define ATLC_RFF3_ADDR__PRESERVED 0x00000000U +#define ATLC_RFF3_ADDR__RESET_VALUE 0x18fe15e0U + +#endif /* __ATLC_RFF3_ADDR_MACRO__ */ + +/** @} end of rff3_addr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff4_addr */ +/** + * @defgroup at_lc_regs_core_tff4_addr tff4_addr + * @brief Contains register fields associated with tff4_addr. definitions. + * @{ + */ +#ifndef __ATLC_TFF4_ADDR_MACRO__ +#define __ATLC_TFF4_ADDR_MACRO__ + +/* macros for field st */ +/** + * @defgroup at_lc_regs_core_st_field st_field + * @brief macros for field st + * @details tx fifo node 4 start addr + * @{ + */ +#define ATLC_TFF4_ADDR__ST__SHIFT 0 +#define ATLC_TFF4_ADDR__ST__WIDTH 16 +#define ATLC_TFF4_ADDR__ST__MASK 0x0000ffffU +#define ATLC_TFF4_ADDR__ST__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF4_ADDR__ST__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF4_ADDR__ST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_TFF4_ADDR__ST__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_TFF4_ADDR__ST__RESET_VALUE 0x00001900U +/** @} */ + +/* macros for field ed */ +/** + * @defgroup at_lc_regs_core_ed_field ed_field + * @brief macros for field ed + * @details tx fifo node 4 end addr + * @{ + */ +#define ATLC_TFF4_ADDR__ED__SHIFT 16 +#define ATLC_TFF4_ADDR__ED__WIDTH 16 +#define ATLC_TFF4_ADDR__ED__MASK 0xffff0000U +#define ATLC_TFF4_ADDR__ED__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define ATLC_TFF4_ADDR__ED__WRITE(src) (((uint32_t)(src) << 16) & 0xffff0000U) +#define ATLC_TFF4_ADDR__ED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define ATLC_TFF4_ADDR__ED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define ATLC_TFF4_ADDR__ED__RESET_VALUE 0x00001c1eU +/** @} */ +#define ATLC_TFF4_ADDR__TYPE uint32_t +#define ATLC_TFF4_ADDR__READ 0xffffffffU +#define ATLC_TFF4_ADDR__WRITE 0xffffffffU +#define ATLC_TFF4_ADDR__PRESERVED 0x00000000U +#define ATLC_TFF4_ADDR__RESET_VALUE 0x1c1e1900U + +#endif /* __ATLC_TFF4_ADDR_MACRO__ */ + +/** @} end of tff4_addr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff4_addr */ +/** + * @defgroup at_lc_regs_core_rff4_addr rff4_addr + * @brief Contains register fields associated with rff4_addr. definitions. + * @{ + */ +#ifndef __ATLC_RFF4_ADDR_MACRO__ +#define __ATLC_RFF4_ADDR_MACRO__ + +/* macros for field st */ +/** + * @defgroup at_lc_regs_core_st_field st_field + * @brief macros for field st + * @details rx fifo node 4 start addr + * @{ + */ +#define ATLC_RFF4_ADDR__ST__SHIFT 0 +#define ATLC_RFF4_ADDR__ST__WIDTH 16 +#define ATLC_RFF4_ADDR__ST__MASK 0x0000ffffU +#define ATLC_RFF4_ADDR__ST__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF4_ADDR__ST__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF4_ADDR__ST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_RFF4_ADDR__ST__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_RFF4_ADDR__ST__RESET_VALUE 0x00001c20U +/** @} */ + +/* macros for field ed */ +/** + * @defgroup at_lc_regs_core_ed_field ed_field + * @brief macros for field ed + * @details rx fifo node 4 end addr + * @{ + */ +#define ATLC_RFF4_ADDR__ED__SHIFT 16 +#define ATLC_RFF4_ADDR__ED__WIDTH 16 +#define ATLC_RFF4_ADDR__ED__MASK 0xffff0000U +#define ATLC_RFF4_ADDR__ED__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define ATLC_RFF4_ADDR__ED__WRITE(src) (((uint32_t)(src) << 16) & 0xffff0000U) +#define ATLC_RFF4_ADDR__ED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define ATLC_RFF4_ADDR__ED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define ATLC_RFF4_ADDR__ED__RESET_VALUE 0x00001f3eU +/** @} */ +#define ATLC_RFF4_ADDR__TYPE uint32_t +#define ATLC_RFF4_ADDR__READ 0xffffffffU +#define ATLC_RFF4_ADDR__WRITE 0xffffffffU +#define ATLC_RFF4_ADDR__PRESERVED 0x00000000U +#define ATLC_RFF4_ADDR__RESET_VALUE 0x1f3e1c20U + +#endif /* __ATLC_RFF4_ADDR_MACRO__ */ + +/** @} end of rff4_addr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff5_addr */ +/** + * @defgroup at_lc_regs_core_tff5_addr tff5_addr + * @brief Contains register fields associated with tff5_addr. definitions. + * @{ + */ +#ifndef __ATLC_TFF5_ADDR_MACRO__ +#define __ATLC_TFF5_ADDR_MACRO__ + +/* macros for field st */ +/** + * @defgroup at_lc_regs_core_st_field st_field + * @brief macros for field st + * @details tx fifo node 5 start addr + * @{ + */ +#define ATLC_TFF5_ADDR__ST__SHIFT 0 +#define ATLC_TFF5_ADDR__ST__WIDTH 16 +#define ATLC_TFF5_ADDR__ST__MASK 0x0000ffffU +#define ATLC_TFF5_ADDR__ST__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF5_ADDR__ST__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF5_ADDR__ST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_TFF5_ADDR__ST__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_TFF5_ADDR__ST__RESET_VALUE 0x00001f40U +/** @} */ + +/* macros for field ed */ +/** + * @defgroup at_lc_regs_core_ed_field ed_field + * @brief macros for field ed + * @details tx fifo node 5 end addr + * @{ + */ +#define ATLC_TFF5_ADDR__ED__SHIFT 16 +#define ATLC_TFF5_ADDR__ED__WIDTH 16 +#define ATLC_TFF5_ADDR__ED__MASK 0xffff0000U +#define ATLC_TFF5_ADDR__ED__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define ATLC_TFF5_ADDR__ED__WRITE(src) (((uint32_t)(src) << 16) & 0xffff0000U) +#define ATLC_TFF5_ADDR__ED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define ATLC_TFF5_ADDR__ED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define ATLC_TFF5_ADDR__ED__RESET_VALUE 0x0000225eU +/** @} */ +#define ATLC_TFF5_ADDR__TYPE uint32_t +#define ATLC_TFF5_ADDR__READ 0xffffffffU +#define ATLC_TFF5_ADDR__WRITE 0xffffffffU +#define ATLC_TFF5_ADDR__PRESERVED 0x00000000U +#define ATLC_TFF5_ADDR__RESET_VALUE 0x225e1f40U + +#endif /* __ATLC_TFF5_ADDR_MACRO__ */ + +/** @} end of tff5_addr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff5_addr */ +/** + * @defgroup at_lc_regs_core_rff5_addr rff5_addr + * @brief Contains register fields associated with rff5_addr. definitions. + * @{ + */ +#ifndef __ATLC_RFF5_ADDR_MACRO__ +#define __ATLC_RFF5_ADDR_MACRO__ + +/* macros for field st */ +/** + * @defgroup at_lc_regs_core_st_field st_field + * @brief macros for field st + * @details rx fifo node 5 start addr + * @{ + */ +#define ATLC_RFF5_ADDR__ST__SHIFT 0 +#define ATLC_RFF5_ADDR__ST__WIDTH 16 +#define ATLC_RFF5_ADDR__ST__MASK 0x0000ffffU +#define ATLC_RFF5_ADDR__ST__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF5_ADDR__ST__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF5_ADDR__ST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_RFF5_ADDR__ST__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_RFF5_ADDR__ST__RESET_VALUE 0x00002260U +/** @} */ + +/* macros for field ed */ +/** + * @defgroup at_lc_regs_core_ed_field ed_field + * @brief macros for field ed + * @details rx fifo node 5 end addr + * @{ + */ +#define ATLC_RFF5_ADDR__ED__SHIFT 16 +#define ATLC_RFF5_ADDR__ED__WIDTH 16 +#define ATLC_RFF5_ADDR__ED__MASK 0xffff0000U +#define ATLC_RFF5_ADDR__ED__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define ATLC_RFF5_ADDR__ED__WRITE(src) (((uint32_t)(src) << 16) & 0xffff0000U) +#define ATLC_RFF5_ADDR__ED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define ATLC_RFF5_ADDR__ED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define ATLC_RFF5_ADDR__ED__RESET_VALUE 0x0000257eU +/** @} */ +#define ATLC_RFF5_ADDR__TYPE uint32_t +#define ATLC_RFF5_ADDR__READ 0xffffffffU +#define ATLC_RFF5_ADDR__WRITE 0xffffffffU +#define ATLC_RFF5_ADDR__PRESERVED 0x00000000U +#define ATLC_RFF5_ADDR__RESET_VALUE 0x257e2260U + +#endif /* __ATLC_RFF5_ADDR_MACRO__ */ + +/** @} end of rff5_addr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff6_addr */ +/** + * @defgroup at_lc_regs_core_tff6_addr tff6_addr + * @brief Contains register fields associated with tff6_addr. definitions. + * @{ + */ +#ifndef __ATLC_TFF6_ADDR_MACRO__ +#define __ATLC_TFF6_ADDR_MACRO__ + +/* macros for field st */ +/** + * @defgroup at_lc_regs_core_st_field st_field + * @brief macros for field st + * @details tx fifo node 6 start addr + * @{ + */ +#define ATLC_TFF6_ADDR__ST__SHIFT 0 +#define ATLC_TFF6_ADDR__ST__WIDTH 16 +#define ATLC_TFF6_ADDR__ST__MASK 0x0000ffffU +#define ATLC_TFF6_ADDR__ST__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF6_ADDR__ST__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF6_ADDR__ST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_TFF6_ADDR__ST__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_TFF6_ADDR__ST__RESET_VALUE 0x00002580U +/** @} */ + +/* macros for field ed */ +/** + * @defgroup at_lc_regs_core_ed_field ed_field + * @brief macros for field ed + * @details tx fifo node 6 end addr + * @{ + */ +#define ATLC_TFF6_ADDR__ED__SHIFT 16 +#define ATLC_TFF6_ADDR__ED__WIDTH 16 +#define ATLC_TFF6_ADDR__ED__MASK 0xffff0000U +#define ATLC_TFF6_ADDR__ED__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define ATLC_TFF6_ADDR__ED__WRITE(src) (((uint32_t)(src) << 16) & 0xffff0000U) +#define ATLC_TFF6_ADDR__ED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define ATLC_TFF6_ADDR__ED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define ATLC_TFF6_ADDR__ED__RESET_VALUE 0x0000289eU +/** @} */ +#define ATLC_TFF6_ADDR__TYPE uint32_t +#define ATLC_TFF6_ADDR__READ 0xffffffffU +#define ATLC_TFF6_ADDR__WRITE 0xffffffffU +#define ATLC_TFF6_ADDR__PRESERVED 0x00000000U +#define ATLC_TFF6_ADDR__RESET_VALUE 0x289e2580U + +#endif /* __ATLC_TFF6_ADDR_MACRO__ */ + +/** @} end of tff6_addr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff6_addr */ +/** + * @defgroup at_lc_regs_core_rff6_addr rff6_addr + * @brief Contains register fields associated with rff6_addr. definitions. + * @{ + */ +#ifndef __ATLC_RFF6_ADDR_MACRO__ +#define __ATLC_RFF6_ADDR_MACRO__ + +/* macros for field st */ +/** + * @defgroup at_lc_regs_core_st_field st_field + * @brief macros for field st + * @details rx fifo node 6 start addr + * @{ + */ +#define ATLC_RFF6_ADDR__ST__SHIFT 0 +#define ATLC_RFF6_ADDR__ST__WIDTH 16 +#define ATLC_RFF6_ADDR__ST__MASK 0x0000ffffU +#define ATLC_RFF6_ADDR__ST__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF6_ADDR__ST__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF6_ADDR__ST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_RFF6_ADDR__ST__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_RFF6_ADDR__ST__RESET_VALUE 0x000028a0U +/** @} */ + +/* macros for field ed */ +/** + * @defgroup at_lc_regs_core_ed_field ed_field + * @brief macros for field ed + * @details rx fifo node 6 end addr + * @{ + */ +#define ATLC_RFF6_ADDR__ED__SHIFT 16 +#define ATLC_RFF6_ADDR__ED__WIDTH 16 +#define ATLC_RFF6_ADDR__ED__MASK 0xffff0000U +#define ATLC_RFF6_ADDR__ED__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define ATLC_RFF6_ADDR__ED__WRITE(src) (((uint32_t)(src) << 16) & 0xffff0000U) +#define ATLC_RFF6_ADDR__ED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define ATLC_RFF6_ADDR__ED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define ATLC_RFF6_ADDR__ED__RESET_VALUE 0x00002bbeU +/** @} */ +#define ATLC_RFF6_ADDR__TYPE uint32_t +#define ATLC_RFF6_ADDR__READ 0xffffffffU +#define ATLC_RFF6_ADDR__WRITE 0xffffffffU +#define ATLC_RFF6_ADDR__PRESERVED 0x00000000U +#define ATLC_RFF6_ADDR__RESET_VALUE 0x2bbe28a0U + +#endif /* __ATLC_RFF6_ADDR_MACRO__ */ + +/** @} end of rff6_addr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff7_addr */ +/** + * @defgroup at_lc_regs_core_tff7_addr tff7_addr + * @brief Contains register fields associated with tff7_addr. definitions. + * @{ + */ +#ifndef __ATLC_TFF7_ADDR_MACRO__ +#define __ATLC_TFF7_ADDR_MACRO__ + +/* macros for field st */ +/** + * @defgroup at_lc_regs_core_st_field st_field + * @brief macros for field st + * @details tx fifo node 7 start addr + * @{ + */ +#define ATLC_TFF7_ADDR__ST__SHIFT 0 +#define ATLC_TFF7_ADDR__ST__WIDTH 16 +#define ATLC_TFF7_ADDR__ST__MASK 0x0000ffffU +#define ATLC_TFF7_ADDR__ST__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF7_ADDR__ST__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF7_ADDR__ST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_TFF7_ADDR__ST__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_TFF7_ADDR__ST__RESET_VALUE 0x00002bc0U +/** @} */ + +/* macros for field ed */ +/** + * @defgroup at_lc_regs_core_ed_field ed_field + * @brief macros for field ed + * @details tx fifo node 7 end addr + * @{ + */ +#define ATLC_TFF7_ADDR__ED__SHIFT 16 +#define ATLC_TFF7_ADDR__ED__WIDTH 16 +#define ATLC_TFF7_ADDR__ED__MASK 0xffff0000U +#define ATLC_TFF7_ADDR__ED__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define ATLC_TFF7_ADDR__ED__WRITE(src) (((uint32_t)(src) << 16) & 0xffff0000U) +#define ATLC_TFF7_ADDR__ED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define ATLC_TFF7_ADDR__ED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define ATLC_TFF7_ADDR__ED__RESET_VALUE 0x00002edeU +/** @} */ +#define ATLC_TFF7_ADDR__TYPE uint32_t +#define ATLC_TFF7_ADDR__READ 0xffffffffU +#define ATLC_TFF7_ADDR__WRITE 0xffffffffU +#define ATLC_TFF7_ADDR__PRESERVED 0x00000000U +#define ATLC_TFF7_ADDR__RESET_VALUE 0x2ede2bc0U + +#endif /* __ATLC_TFF7_ADDR_MACRO__ */ + +/** @} end of tff7_addr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff7_addr */ +/** + * @defgroup at_lc_regs_core_rff7_addr rff7_addr + * @brief Contains register fields associated with rff7_addr. definitions. + * @{ + */ +#ifndef __ATLC_RFF7_ADDR_MACRO__ +#define __ATLC_RFF7_ADDR_MACRO__ + +/* macros for field st */ +/** + * @defgroup at_lc_regs_core_st_field st_field + * @brief macros for field st + * @details rx fifo node 7 start addr + * @{ + */ +#define ATLC_RFF7_ADDR__ST__SHIFT 0 +#define ATLC_RFF7_ADDR__ST__WIDTH 16 +#define ATLC_RFF7_ADDR__ST__MASK 0x0000ffffU +#define ATLC_RFF7_ADDR__ST__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF7_ADDR__ST__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF7_ADDR__ST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_RFF7_ADDR__ST__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_RFF7_ADDR__ST__RESET_VALUE 0x00002ee0U +/** @} */ + +/* macros for field ed */ +/** + * @defgroup at_lc_regs_core_ed_field ed_field + * @brief macros for field ed + * @details rx fifo node 7 end addr + * @{ + */ +#define ATLC_RFF7_ADDR__ED__SHIFT 16 +#define ATLC_RFF7_ADDR__ED__WIDTH 16 +#define ATLC_RFF7_ADDR__ED__MASK 0xffff0000U +#define ATLC_RFF7_ADDR__ED__READ(src) (((uint32_t)(src) & 0xffff0000U) >> 16) +#define ATLC_RFF7_ADDR__ED__WRITE(src) (((uint32_t)(src) << 16) & 0xffff0000U) +#define ATLC_RFF7_ADDR__ED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((uint32_t)(src) <<\ + 16) & 0xffff0000U) +#define ATLC_RFF7_ADDR__ED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0xffff0000U))) +#define ATLC_RFF7_ADDR__ED__RESET_VALUE 0x000031feU +/** @} */ +#define ATLC_RFF7_ADDR__TYPE uint32_t +#define ATLC_RFF7_ADDR__READ 0xffffffffU +#define ATLC_RFF7_ADDR__WRITE 0xffffffffU +#define ATLC_RFF7_ADDR__PRESERVED 0x00000000U +#define ATLC_RFF7_ADDR__RESET_VALUE 0x31fe2ee0U + +#endif /* __ATLC_RFF7_ADDR_MACRO__ */ + +/** @} end of rff7_addr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff0_rptr */ +/** + * @defgroup at_lc_regs_core_tff0_rptr tff0_rptr + * @brief Contains register fields associated with tff0_rptr. definitions. + * @{ + */ +#ifndef __ATLC_TFF0_RPTR_MACRO__ +#define __ATLC_TFF0_RPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details tx fifo node 0 read pointer + * @{ + */ +#define ATLC_TFF0_RPTR__VL__SHIFT 0 +#define ATLC_TFF0_RPTR__VL__WIDTH 16 +#define ATLC_TFF0_RPTR__VL__MASK 0x0000ffffU +#define ATLC_TFF0_RPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF0_RPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_TFF0_RPTR__TYPE uint32_t +#define ATLC_TFF0_RPTR__READ 0x0000ffffU +#define ATLC_TFF0_RPTR__PRESERVED 0x00000000U +#define ATLC_TFF0_RPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_TFF0_RPTR_MACRO__ */ + +/** @} end of tff0_rptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff0_wptr */ +/** + * @defgroup at_lc_regs_core_tff0_wptr tff0_wptr + * @brief Contains register fields associated with tff0_wptr. definitions. + * @{ + */ +#ifndef __ATLC_TFF0_WPTR_MACRO__ +#define __ATLC_TFF0_WPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details tx fifo node 0 write pointer + * @{ + */ +#define ATLC_TFF0_WPTR__VL__SHIFT 0 +#define ATLC_TFF0_WPTR__VL__WIDTH 16 +#define ATLC_TFF0_WPTR__VL__MASK 0x0000ffffU +#define ATLC_TFF0_WPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF0_WPTR__VL__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF0_WPTR__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_TFF0_WPTR__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_TFF0_WPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_TFF0_WPTR__TYPE uint32_t +#define ATLC_TFF0_WPTR__READ 0x0000ffffU +#define ATLC_TFF0_WPTR__WRITE 0x0000ffffU +#define ATLC_TFF0_WPTR__PRESERVED 0x00000000U +#define ATLC_TFF0_WPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_TFF0_WPTR_MACRO__ */ + +/** @} end of tff0_wptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff0_rptr */ +/** + * @defgroup at_lc_regs_core_rff0_rptr rff0_rptr + * @brief Contains register fields associated with rff0_rptr. definitions. + * @{ + */ +#ifndef __ATLC_RFF0_RPTR_MACRO__ +#define __ATLC_RFF0_RPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx fifo node 0 read pointer + * @{ + */ +#define ATLC_RFF0_RPTR__VL__SHIFT 0 +#define ATLC_RFF0_RPTR__VL__WIDTH 16 +#define ATLC_RFF0_RPTR__VL__MASK 0x0000ffffU +#define ATLC_RFF0_RPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF0_RPTR__VL__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF0_RPTR__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_RFF0_RPTR__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_RFF0_RPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RFF0_RPTR__TYPE uint32_t +#define ATLC_RFF0_RPTR__READ 0x0000ffffU +#define ATLC_RFF0_RPTR__WRITE 0x0000ffffU +#define ATLC_RFF0_RPTR__PRESERVED 0x00000000U +#define ATLC_RFF0_RPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RFF0_RPTR_MACRO__ */ + +/** @} end of rff0_rptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff0_wptr */ +/** + * @defgroup at_lc_regs_core_rff0_wptr rff0_wptr + * @brief Contains register fields associated with rff0_wptr. definitions. + * @{ + */ +#ifndef __ATLC_RFF0_WPTR_MACRO__ +#define __ATLC_RFF0_WPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx fifo node 0 write pointer + * @{ + */ +#define ATLC_RFF0_WPTR__VL__SHIFT 0 +#define ATLC_RFF0_WPTR__VL__WIDTH 16 +#define ATLC_RFF0_WPTR__VL__MASK 0x0000ffffU +#define ATLC_RFF0_WPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF0_WPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RFF0_WPTR__TYPE uint32_t +#define ATLC_RFF0_WPTR__READ 0x0000ffffU +#define ATLC_RFF0_WPTR__PRESERVED 0x00000000U +#define ATLC_RFF0_WPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RFF0_WPTR_MACRO__ */ + +/** @} end of rff0_wptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff1_rptr */ +/** + * @defgroup at_lc_regs_core_tff1_rptr tff1_rptr + * @brief Contains register fields associated with tff1_rptr. definitions. + * @{ + */ +#ifndef __ATLC_TFF1_RPTR_MACRO__ +#define __ATLC_TFF1_RPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details tx fifo node 1 read pointer + * @{ + */ +#define ATLC_TFF1_RPTR__VL__SHIFT 0 +#define ATLC_TFF1_RPTR__VL__WIDTH 16 +#define ATLC_TFF1_RPTR__VL__MASK 0x0000ffffU +#define ATLC_TFF1_RPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF1_RPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_TFF1_RPTR__TYPE uint32_t +#define ATLC_TFF1_RPTR__READ 0x0000ffffU +#define ATLC_TFF1_RPTR__PRESERVED 0x00000000U +#define ATLC_TFF1_RPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_TFF1_RPTR_MACRO__ */ + +/** @} end of tff1_rptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff1_wptr */ +/** + * @defgroup at_lc_regs_core_tff1_wptr tff1_wptr + * @brief Contains register fields associated with tff1_wptr. definitions. + * @{ + */ +#ifndef __ATLC_TFF1_WPTR_MACRO__ +#define __ATLC_TFF1_WPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details tx fifo node 1 write pointer + * @{ + */ +#define ATLC_TFF1_WPTR__VL__SHIFT 0 +#define ATLC_TFF1_WPTR__VL__WIDTH 16 +#define ATLC_TFF1_WPTR__VL__MASK 0x0000ffffU +#define ATLC_TFF1_WPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF1_WPTR__VL__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF1_WPTR__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_TFF1_WPTR__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_TFF1_WPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_TFF1_WPTR__TYPE uint32_t +#define ATLC_TFF1_WPTR__READ 0x0000ffffU +#define ATLC_TFF1_WPTR__WRITE 0x0000ffffU +#define ATLC_TFF1_WPTR__PRESERVED 0x00000000U +#define ATLC_TFF1_WPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_TFF1_WPTR_MACRO__ */ + +/** @} end of tff1_wptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff1_rptr */ +/** + * @defgroup at_lc_regs_core_rff1_rptr rff1_rptr + * @brief Contains register fields associated with rff1_rptr. definitions. + * @{ + */ +#ifndef __ATLC_RFF1_RPTR_MACRO__ +#define __ATLC_RFF1_RPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx fifo node 1 read pointer + * @{ + */ +#define ATLC_RFF1_RPTR__VL__SHIFT 0 +#define ATLC_RFF1_RPTR__VL__WIDTH 16 +#define ATLC_RFF1_RPTR__VL__MASK 0x0000ffffU +#define ATLC_RFF1_RPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF1_RPTR__VL__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF1_RPTR__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_RFF1_RPTR__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_RFF1_RPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RFF1_RPTR__TYPE uint32_t +#define ATLC_RFF1_RPTR__READ 0x0000ffffU +#define ATLC_RFF1_RPTR__WRITE 0x0000ffffU +#define ATLC_RFF1_RPTR__PRESERVED 0x00000000U +#define ATLC_RFF1_RPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RFF1_RPTR_MACRO__ */ + +/** @} end of rff1_rptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff1_wptr */ +/** + * @defgroup at_lc_regs_core_rff1_wptr rff1_wptr + * @brief Contains register fields associated with rff1_wptr. definitions. + * @{ + */ +#ifndef __ATLC_RFF1_WPTR_MACRO__ +#define __ATLC_RFF1_WPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx fifo node 1 write pointer + * @{ + */ +#define ATLC_RFF1_WPTR__VL__SHIFT 0 +#define ATLC_RFF1_WPTR__VL__WIDTH 16 +#define ATLC_RFF1_WPTR__VL__MASK 0x0000ffffU +#define ATLC_RFF1_WPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF1_WPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RFF1_WPTR__TYPE uint32_t +#define ATLC_RFF1_WPTR__READ 0x0000ffffU +#define ATLC_RFF1_WPTR__PRESERVED 0x00000000U +#define ATLC_RFF1_WPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RFF1_WPTR_MACRO__ */ + +/** @} end of rff1_wptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff2_rptr */ +/** + * @defgroup at_lc_regs_core_tff2_rptr tff2_rptr + * @brief Contains register fields associated with tff2_rptr. definitions. + * @{ + */ +#ifndef __ATLC_TFF2_RPTR_MACRO__ +#define __ATLC_TFF2_RPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details tx fifo node 2 read pointer + * @{ + */ +#define ATLC_TFF2_RPTR__VL__SHIFT 0 +#define ATLC_TFF2_RPTR__VL__WIDTH 16 +#define ATLC_TFF2_RPTR__VL__MASK 0x0000ffffU +#define ATLC_TFF2_RPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF2_RPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_TFF2_RPTR__TYPE uint32_t +#define ATLC_TFF2_RPTR__READ 0x0000ffffU +#define ATLC_TFF2_RPTR__PRESERVED 0x00000000U +#define ATLC_TFF2_RPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_TFF2_RPTR_MACRO__ */ + +/** @} end of tff2_rptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff2_wptr */ +/** + * @defgroup at_lc_regs_core_tff2_wptr tff2_wptr + * @brief Contains register fields associated with tff2_wptr. definitions. + * @{ + */ +#ifndef __ATLC_TFF2_WPTR_MACRO__ +#define __ATLC_TFF2_WPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details tx fifo node 2 write pointer + * @{ + */ +#define ATLC_TFF2_WPTR__VL__SHIFT 0 +#define ATLC_TFF2_WPTR__VL__WIDTH 16 +#define ATLC_TFF2_WPTR__VL__MASK 0x0000ffffU +#define ATLC_TFF2_WPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF2_WPTR__VL__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF2_WPTR__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_TFF2_WPTR__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_TFF2_WPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_TFF2_WPTR__TYPE uint32_t +#define ATLC_TFF2_WPTR__READ 0x0000ffffU +#define ATLC_TFF2_WPTR__WRITE 0x0000ffffU +#define ATLC_TFF2_WPTR__PRESERVED 0x00000000U +#define ATLC_TFF2_WPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_TFF2_WPTR_MACRO__ */ + +/** @} end of tff2_wptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff2_rptr */ +/** + * @defgroup at_lc_regs_core_rff2_rptr rff2_rptr + * @brief Contains register fields associated with rff2_rptr. definitions. + * @{ + */ +#ifndef __ATLC_RFF2_RPTR_MACRO__ +#define __ATLC_RFF2_RPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx fifo node 2 read pointer + * @{ + */ +#define ATLC_RFF2_RPTR__VL__SHIFT 0 +#define ATLC_RFF2_RPTR__VL__WIDTH 16 +#define ATLC_RFF2_RPTR__VL__MASK 0x0000ffffU +#define ATLC_RFF2_RPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF2_RPTR__VL__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF2_RPTR__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_RFF2_RPTR__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_RFF2_RPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RFF2_RPTR__TYPE uint32_t +#define ATLC_RFF2_RPTR__READ 0x0000ffffU +#define ATLC_RFF2_RPTR__WRITE 0x0000ffffU +#define ATLC_RFF2_RPTR__PRESERVED 0x00000000U +#define ATLC_RFF2_RPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RFF2_RPTR_MACRO__ */ + +/** @} end of rff2_rptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff2_wptr */ +/** + * @defgroup at_lc_regs_core_rff2_wptr rff2_wptr + * @brief Contains register fields associated with rff2_wptr. definitions. + * @{ + */ +#ifndef __ATLC_RFF2_WPTR_MACRO__ +#define __ATLC_RFF2_WPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx fifo node 2 write pointer + * @{ + */ +#define ATLC_RFF2_WPTR__VL__SHIFT 0 +#define ATLC_RFF2_WPTR__VL__WIDTH 16 +#define ATLC_RFF2_WPTR__VL__MASK 0x0000ffffU +#define ATLC_RFF2_WPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF2_WPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RFF2_WPTR__TYPE uint32_t +#define ATLC_RFF2_WPTR__READ 0x0000ffffU +#define ATLC_RFF2_WPTR__PRESERVED 0x00000000U +#define ATLC_RFF2_WPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RFF2_WPTR_MACRO__ */ + +/** @} end of rff2_wptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff3_rptr */ +/** + * @defgroup at_lc_regs_core_tff3_rptr tff3_rptr + * @brief Contains register fields associated with tff3_rptr. definitions. + * @{ + */ +#ifndef __ATLC_TFF3_RPTR_MACRO__ +#define __ATLC_TFF3_RPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details tx fifo node 3 read pointer + * @{ + */ +#define ATLC_TFF3_RPTR__VL__SHIFT 0 +#define ATLC_TFF3_RPTR__VL__WIDTH 16 +#define ATLC_TFF3_RPTR__VL__MASK 0x0000ffffU +#define ATLC_TFF3_RPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF3_RPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_TFF3_RPTR__TYPE uint32_t +#define ATLC_TFF3_RPTR__READ 0x0000ffffU +#define ATLC_TFF3_RPTR__PRESERVED 0x00000000U +#define ATLC_TFF3_RPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_TFF3_RPTR_MACRO__ */ + +/** @} end of tff3_rptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff3_wptr */ +/** + * @defgroup at_lc_regs_core_tff3_wptr tff3_wptr + * @brief Contains register fields associated with tff3_wptr. definitions. + * @{ + */ +#ifndef __ATLC_TFF3_WPTR_MACRO__ +#define __ATLC_TFF3_WPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details tx fifo node 3 write pointer + * @{ + */ +#define ATLC_TFF3_WPTR__VL__SHIFT 0 +#define ATLC_TFF3_WPTR__VL__WIDTH 16 +#define ATLC_TFF3_WPTR__VL__MASK 0x0000ffffU +#define ATLC_TFF3_WPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF3_WPTR__VL__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF3_WPTR__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_TFF3_WPTR__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_TFF3_WPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_TFF3_WPTR__TYPE uint32_t +#define ATLC_TFF3_WPTR__READ 0x0000ffffU +#define ATLC_TFF3_WPTR__WRITE 0x0000ffffU +#define ATLC_TFF3_WPTR__PRESERVED 0x00000000U +#define ATLC_TFF3_WPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_TFF3_WPTR_MACRO__ */ + +/** @} end of tff3_wptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff3_rptr */ +/** + * @defgroup at_lc_regs_core_rff3_rptr rff3_rptr + * @brief Contains register fields associated with rff3_rptr. definitions. + * @{ + */ +#ifndef __ATLC_RFF3_RPTR_MACRO__ +#define __ATLC_RFF3_RPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx fifo node 3 read pointer + * @{ + */ +#define ATLC_RFF3_RPTR__VL__SHIFT 0 +#define ATLC_RFF3_RPTR__VL__WIDTH 16 +#define ATLC_RFF3_RPTR__VL__MASK 0x0000ffffU +#define ATLC_RFF3_RPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF3_RPTR__VL__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF3_RPTR__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_RFF3_RPTR__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_RFF3_RPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RFF3_RPTR__TYPE uint32_t +#define ATLC_RFF3_RPTR__READ 0x0000ffffU +#define ATLC_RFF3_RPTR__WRITE 0x0000ffffU +#define ATLC_RFF3_RPTR__PRESERVED 0x00000000U +#define ATLC_RFF3_RPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RFF3_RPTR_MACRO__ */ + +/** @} end of rff3_rptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff3_wptr */ +/** + * @defgroup at_lc_regs_core_rff3_wptr rff3_wptr + * @brief Contains register fields associated with rff3_wptr. definitions. + * @{ + */ +#ifndef __ATLC_RFF3_WPTR_MACRO__ +#define __ATLC_RFF3_WPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx fifo node 3 write pointer + * @{ + */ +#define ATLC_RFF3_WPTR__VL__SHIFT 0 +#define ATLC_RFF3_WPTR__VL__WIDTH 16 +#define ATLC_RFF3_WPTR__VL__MASK 0x0000ffffU +#define ATLC_RFF3_WPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF3_WPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RFF3_WPTR__TYPE uint32_t +#define ATLC_RFF3_WPTR__READ 0x0000ffffU +#define ATLC_RFF3_WPTR__PRESERVED 0x00000000U +#define ATLC_RFF3_WPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RFF3_WPTR_MACRO__ */ + +/** @} end of rff3_wptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff4_rptr */ +/** + * @defgroup at_lc_regs_core_tff4_rptr tff4_rptr + * @brief Contains register fields associated with tff4_rptr. definitions. + * @{ + */ +#ifndef __ATLC_TFF4_RPTR_MACRO__ +#define __ATLC_TFF4_RPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details tx fifo node 4 read pointer + * @{ + */ +#define ATLC_TFF4_RPTR__VL__SHIFT 0 +#define ATLC_TFF4_RPTR__VL__WIDTH 16 +#define ATLC_TFF4_RPTR__VL__MASK 0x0000ffffU +#define ATLC_TFF4_RPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF4_RPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_TFF4_RPTR__TYPE uint32_t +#define ATLC_TFF4_RPTR__READ 0x0000ffffU +#define ATLC_TFF4_RPTR__PRESERVED 0x00000000U +#define ATLC_TFF4_RPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_TFF4_RPTR_MACRO__ */ + +/** @} end of tff4_rptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff4_wptr */ +/** + * @defgroup at_lc_regs_core_tff4_wptr tff4_wptr + * @brief Contains register fields associated with tff4_wptr. definitions. + * @{ + */ +#ifndef __ATLC_TFF4_WPTR_MACRO__ +#define __ATLC_TFF4_WPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details tx fifo node 4 write pointer + * @{ + */ +#define ATLC_TFF4_WPTR__VL__SHIFT 0 +#define ATLC_TFF4_WPTR__VL__WIDTH 16 +#define ATLC_TFF4_WPTR__VL__MASK 0x0000ffffU +#define ATLC_TFF4_WPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF4_WPTR__VL__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF4_WPTR__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_TFF4_WPTR__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_TFF4_WPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_TFF4_WPTR__TYPE uint32_t +#define ATLC_TFF4_WPTR__READ 0x0000ffffU +#define ATLC_TFF4_WPTR__WRITE 0x0000ffffU +#define ATLC_TFF4_WPTR__PRESERVED 0x00000000U +#define ATLC_TFF4_WPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_TFF4_WPTR_MACRO__ */ + +/** @} end of tff4_wptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff4_rptr */ +/** + * @defgroup at_lc_regs_core_rff4_rptr rff4_rptr + * @brief Contains register fields associated with rff4_rptr. definitions. + * @{ + */ +#ifndef __ATLC_RFF4_RPTR_MACRO__ +#define __ATLC_RFF4_RPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx fifo node 4 read pointer + * @{ + */ +#define ATLC_RFF4_RPTR__VL__SHIFT 0 +#define ATLC_RFF4_RPTR__VL__WIDTH 16 +#define ATLC_RFF4_RPTR__VL__MASK 0x0000ffffU +#define ATLC_RFF4_RPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF4_RPTR__VL__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF4_RPTR__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_RFF4_RPTR__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_RFF4_RPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RFF4_RPTR__TYPE uint32_t +#define ATLC_RFF4_RPTR__READ 0x0000ffffU +#define ATLC_RFF4_RPTR__WRITE 0x0000ffffU +#define ATLC_RFF4_RPTR__PRESERVED 0x00000000U +#define ATLC_RFF4_RPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RFF4_RPTR_MACRO__ */ + +/** @} end of rff4_rptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff4_wptr */ +/** + * @defgroup at_lc_regs_core_rff4_wptr rff4_wptr + * @brief Contains register fields associated with rff4_wptr. definitions. + * @{ + */ +#ifndef __ATLC_RFF4_WPTR_MACRO__ +#define __ATLC_RFF4_WPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx fifo node 4 write pointer + * @{ + */ +#define ATLC_RFF4_WPTR__VL__SHIFT 0 +#define ATLC_RFF4_WPTR__VL__WIDTH 16 +#define ATLC_RFF4_WPTR__VL__MASK 0x0000ffffU +#define ATLC_RFF4_WPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF4_WPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RFF4_WPTR__TYPE uint32_t +#define ATLC_RFF4_WPTR__READ 0x0000ffffU +#define ATLC_RFF4_WPTR__PRESERVED 0x00000000U +#define ATLC_RFF4_WPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RFF4_WPTR_MACRO__ */ + +/** @} end of rff4_wptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff5_rptr */ +/** + * @defgroup at_lc_regs_core_tff5_rptr tff5_rptr + * @brief Contains register fields associated with tff5_rptr. definitions. + * @{ + */ +#ifndef __ATLC_TFF5_RPTR_MACRO__ +#define __ATLC_TFF5_RPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details tx fifo node 5 read pointer + * @{ + */ +#define ATLC_TFF5_RPTR__VL__SHIFT 0 +#define ATLC_TFF5_RPTR__VL__WIDTH 16 +#define ATLC_TFF5_RPTR__VL__MASK 0x0000ffffU +#define ATLC_TFF5_RPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF5_RPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_TFF5_RPTR__TYPE uint32_t +#define ATLC_TFF5_RPTR__READ 0x0000ffffU +#define ATLC_TFF5_RPTR__PRESERVED 0x00000000U +#define ATLC_TFF5_RPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_TFF5_RPTR_MACRO__ */ + +/** @} end of tff5_rptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff5_wptr */ +/** + * @defgroup at_lc_regs_core_tff5_wptr tff5_wptr + * @brief Contains register fields associated with tff5_wptr. definitions. + * @{ + */ +#ifndef __ATLC_TFF5_WPTR_MACRO__ +#define __ATLC_TFF5_WPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details tx fifo node 5 write pointer + * @{ + */ +#define ATLC_TFF5_WPTR__VL__SHIFT 0 +#define ATLC_TFF5_WPTR__VL__WIDTH 16 +#define ATLC_TFF5_WPTR__VL__MASK 0x0000ffffU +#define ATLC_TFF5_WPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF5_WPTR__VL__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF5_WPTR__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_TFF5_WPTR__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_TFF5_WPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_TFF5_WPTR__TYPE uint32_t +#define ATLC_TFF5_WPTR__READ 0x0000ffffU +#define ATLC_TFF5_WPTR__WRITE 0x0000ffffU +#define ATLC_TFF5_WPTR__PRESERVED 0x00000000U +#define ATLC_TFF5_WPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_TFF5_WPTR_MACRO__ */ + +/** @} end of tff5_wptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff5_rptr */ +/** + * @defgroup at_lc_regs_core_rff5_rptr rff5_rptr + * @brief Contains register fields associated with rff5_rptr. definitions. + * @{ + */ +#ifndef __ATLC_RFF5_RPTR_MACRO__ +#define __ATLC_RFF5_RPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx fifo node 5 read pointer + * @{ + */ +#define ATLC_RFF5_RPTR__VL__SHIFT 0 +#define ATLC_RFF5_RPTR__VL__WIDTH 16 +#define ATLC_RFF5_RPTR__VL__MASK 0x0000ffffU +#define ATLC_RFF5_RPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF5_RPTR__VL__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF5_RPTR__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_RFF5_RPTR__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_RFF5_RPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RFF5_RPTR__TYPE uint32_t +#define ATLC_RFF5_RPTR__READ 0x0000ffffU +#define ATLC_RFF5_RPTR__WRITE 0x0000ffffU +#define ATLC_RFF5_RPTR__PRESERVED 0x00000000U +#define ATLC_RFF5_RPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RFF5_RPTR_MACRO__ */ + +/** @} end of rff5_rptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff5_wptr */ +/** + * @defgroup at_lc_regs_core_rff5_wptr rff5_wptr + * @brief Contains register fields associated with rff5_wptr. definitions. + * @{ + */ +#ifndef __ATLC_RFF5_WPTR_MACRO__ +#define __ATLC_RFF5_WPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx fifo node 5 write pointer + * @{ + */ +#define ATLC_RFF5_WPTR__VL__SHIFT 0 +#define ATLC_RFF5_WPTR__VL__WIDTH 16 +#define ATLC_RFF5_WPTR__VL__MASK 0x0000ffffU +#define ATLC_RFF5_WPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF5_WPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RFF5_WPTR__TYPE uint32_t +#define ATLC_RFF5_WPTR__READ 0x0000ffffU +#define ATLC_RFF5_WPTR__PRESERVED 0x00000000U +#define ATLC_RFF5_WPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RFF5_WPTR_MACRO__ */ + +/** @} end of rff5_wptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff6_rptr */ +/** + * @defgroup at_lc_regs_core_tff6_rptr tff6_rptr + * @brief Contains register fields associated with tff6_rptr. definitions. + * @{ + */ +#ifndef __ATLC_TFF6_RPTR_MACRO__ +#define __ATLC_TFF6_RPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details tx fifo node 6 read pointer + * @{ + */ +#define ATLC_TFF6_RPTR__VL__SHIFT 0 +#define ATLC_TFF6_RPTR__VL__WIDTH 16 +#define ATLC_TFF6_RPTR__VL__MASK 0x0000ffffU +#define ATLC_TFF6_RPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF6_RPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_TFF6_RPTR__TYPE uint32_t +#define ATLC_TFF6_RPTR__READ 0x0000ffffU +#define ATLC_TFF6_RPTR__PRESERVED 0x00000000U +#define ATLC_TFF6_RPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_TFF6_RPTR_MACRO__ */ + +/** @} end of tff6_rptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff6_wptr */ +/** + * @defgroup at_lc_regs_core_tff6_wptr tff6_wptr + * @brief Contains register fields associated with tff6_wptr. definitions. + * @{ + */ +#ifndef __ATLC_TFF6_WPTR_MACRO__ +#define __ATLC_TFF6_WPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details tx fifo node 6 write pointer + * @{ + */ +#define ATLC_TFF6_WPTR__VL__SHIFT 0 +#define ATLC_TFF6_WPTR__VL__WIDTH 16 +#define ATLC_TFF6_WPTR__VL__MASK 0x0000ffffU +#define ATLC_TFF6_WPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF6_WPTR__VL__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF6_WPTR__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_TFF6_WPTR__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_TFF6_WPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_TFF6_WPTR__TYPE uint32_t +#define ATLC_TFF6_WPTR__READ 0x0000ffffU +#define ATLC_TFF6_WPTR__WRITE 0x0000ffffU +#define ATLC_TFF6_WPTR__PRESERVED 0x00000000U +#define ATLC_TFF6_WPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_TFF6_WPTR_MACRO__ */ + +/** @} end of tff6_wptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff6_rptr */ +/** + * @defgroup at_lc_regs_core_rff6_rptr rff6_rptr + * @brief Contains register fields associated with rff6_rptr. definitions. + * @{ + */ +#ifndef __ATLC_RFF6_RPTR_MACRO__ +#define __ATLC_RFF6_RPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx fifo node 6 read pointer + * @{ + */ +#define ATLC_RFF6_RPTR__VL__SHIFT 0 +#define ATLC_RFF6_RPTR__VL__WIDTH 16 +#define ATLC_RFF6_RPTR__VL__MASK 0x0000ffffU +#define ATLC_RFF6_RPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF6_RPTR__VL__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF6_RPTR__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_RFF6_RPTR__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_RFF6_RPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RFF6_RPTR__TYPE uint32_t +#define ATLC_RFF6_RPTR__READ 0x0000ffffU +#define ATLC_RFF6_RPTR__WRITE 0x0000ffffU +#define ATLC_RFF6_RPTR__PRESERVED 0x00000000U +#define ATLC_RFF6_RPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RFF6_RPTR_MACRO__ */ + +/** @} end of rff6_rptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff6_wptr */ +/** + * @defgroup at_lc_regs_core_rff6_wptr rff6_wptr + * @brief Contains register fields associated with rff6_wptr. definitions. + * @{ + */ +#ifndef __ATLC_RFF6_WPTR_MACRO__ +#define __ATLC_RFF6_WPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx fifo node 6 write pointer + * @{ + */ +#define ATLC_RFF6_WPTR__VL__SHIFT 0 +#define ATLC_RFF6_WPTR__VL__WIDTH 16 +#define ATLC_RFF6_WPTR__VL__MASK 0x0000ffffU +#define ATLC_RFF6_WPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF6_WPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RFF6_WPTR__TYPE uint32_t +#define ATLC_RFF6_WPTR__READ 0x0000ffffU +#define ATLC_RFF6_WPTR__PRESERVED 0x00000000U +#define ATLC_RFF6_WPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RFF6_WPTR_MACRO__ */ + +/** @} end of rff6_wptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff7_rptr */ +/** + * @defgroup at_lc_regs_core_tff7_rptr tff7_rptr + * @brief Contains register fields associated with tff7_rptr. definitions. + * @{ + */ +#ifndef __ATLC_TFF7_RPTR_MACRO__ +#define __ATLC_TFF7_RPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details tx fifo node 7 read pointer + * @{ + */ +#define ATLC_TFF7_RPTR__VL__SHIFT 0 +#define ATLC_TFF7_RPTR__VL__WIDTH 16 +#define ATLC_TFF7_RPTR__VL__MASK 0x0000ffffU +#define ATLC_TFF7_RPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF7_RPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_TFF7_RPTR__TYPE uint32_t +#define ATLC_TFF7_RPTR__READ 0x0000ffffU +#define ATLC_TFF7_RPTR__PRESERVED 0x00000000U +#define ATLC_TFF7_RPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_TFF7_RPTR_MACRO__ */ + +/** @} end of tff7_rptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_tff7_wptr */ +/** + * @defgroup at_lc_regs_core_tff7_wptr tff7_wptr + * @brief Contains register fields associated with tff7_wptr. definitions. + * @{ + */ +#ifndef __ATLC_TFF7_WPTR_MACRO__ +#define __ATLC_TFF7_WPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details tx fifo node 7 write pointer + * @{ + */ +#define ATLC_TFF7_WPTR__VL__SHIFT 0 +#define ATLC_TFF7_WPTR__VL__WIDTH 16 +#define ATLC_TFF7_WPTR__VL__MASK 0x0000ffffU +#define ATLC_TFF7_WPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF7_WPTR__VL__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_TFF7_WPTR__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_TFF7_WPTR__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_TFF7_WPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_TFF7_WPTR__TYPE uint32_t +#define ATLC_TFF7_WPTR__READ 0x0000ffffU +#define ATLC_TFF7_WPTR__WRITE 0x0000ffffU +#define ATLC_TFF7_WPTR__PRESERVED 0x00000000U +#define ATLC_TFF7_WPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_TFF7_WPTR_MACRO__ */ + +/** @} end of tff7_wptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff7_rptr */ +/** + * @defgroup at_lc_regs_core_rff7_rptr rff7_rptr + * @brief Contains register fields associated with rff7_rptr. definitions. + * @{ + */ +#ifndef __ATLC_RFF7_RPTR_MACRO__ +#define __ATLC_RFF7_RPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx fifo node 7 read pointer + * @{ + */ +#define ATLC_RFF7_RPTR__VL__SHIFT 0 +#define ATLC_RFF7_RPTR__VL__WIDTH 16 +#define ATLC_RFF7_RPTR__VL__MASK 0x0000ffffU +#define ATLC_RFF7_RPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF7_RPTR__VL__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF7_RPTR__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_RFF7_RPTR__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x0000ffffU))) +#define ATLC_RFF7_RPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RFF7_RPTR__TYPE uint32_t +#define ATLC_RFF7_RPTR__READ 0x0000ffffU +#define ATLC_RFF7_RPTR__WRITE 0x0000ffffU +#define ATLC_RFF7_RPTR__PRESERVED 0x00000000U +#define ATLC_RFF7_RPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RFF7_RPTR_MACRO__ */ + +/** @} end of rff7_rptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_rff7_wptr */ +/** + * @defgroup at_lc_regs_core_rff7_wptr rff7_wptr + * @brief Contains register fields associated with rff7_wptr. definitions. + * @{ + */ +#ifndef __ATLC_RFF7_WPTR_MACRO__ +#define __ATLC_RFF7_WPTR_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details rx fifo node 7 write pointer + * @{ + */ +#define ATLC_RFF7_WPTR__VL__SHIFT 0 +#define ATLC_RFF7_WPTR__VL__WIDTH 16 +#define ATLC_RFF7_WPTR__VL__MASK 0x0000ffffU +#define ATLC_RFF7_WPTR__VL__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_RFF7_WPTR__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_RFF7_WPTR__TYPE uint32_t +#define ATLC_RFF7_WPTR__READ 0x0000ffffU +#define ATLC_RFF7_WPTR__PRESERVED 0x00000000U +#define ATLC_RFF7_WPTR__RESET_VALUE 0x00000000U + +#endif /* __ATLC_RFF7_WPTR_MACRO__ */ + +/** @} end of rff7_wptr */ + +/* macros for BlueprintGlobalNameSpace::ATLC_crc_plynml */ +/** + * @defgroup at_lc_regs_core_crc_plynml crc_plynml + * @brief Contains register fields associated with crc_plynml. definitions. + * @{ + */ +#ifndef __ATLC_CRC_PLYNML_MACRO__ +#define __ATLC_CRC_PLYNML_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details crc polynomial + * @{ + */ +#define ATLC_CRC_PLYNML__VL__SHIFT 0 +#define ATLC_CRC_PLYNML__VL__WIDTH 32 +#define ATLC_CRC_PLYNML__VL__MASK 0xffffffffU +#define ATLC_CRC_PLYNML__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_CRC_PLYNML__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_CRC_PLYNML__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_CRC_PLYNML__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_CRC_PLYNML__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_CRC_PLYNML__TYPE uint32_t +#define ATLC_CRC_PLYNML__READ 0xffffffffU +#define ATLC_CRC_PLYNML__WRITE 0xffffffffU +#define ATLC_CRC_PLYNML__PRESERVED 0x00000000U +#define ATLC_CRC_PLYNML__RESET_VALUE 0x00000000U + +#endif /* __ATLC_CRC_PLYNML_MACRO__ */ + +/** @} end of crc_plynml */ + +/* macros for BlueprintGlobalNameSpace::ATLC_crc */ +/** + * @defgroup at_lc_regs_core_crc crc + * @brief Contains register fields associated with crc. definitions. + * @{ + */ +#ifndef __ATLC_CRC_MACRO__ +#define __ATLC_CRC_MACRO__ + +/* macros for field sd */ +/** + * @defgroup at_lc_regs_core_sd_field sd_field + * @brief macros for field sd + * @details initial seed for crc + * @{ + */ +#define ATLC_CRC__SD__SHIFT 0 +#define ATLC_CRC__SD__WIDTH 32 +#define ATLC_CRC__SD__MASK 0xffffffffU +#define ATLC_CRC__SD__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_CRC__SD__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_CRC__SD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_CRC__SD__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_CRC__SD__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_CRC__TYPE uint32_t +#define ATLC_CRC__READ 0xffffffffU +#define ATLC_CRC__WRITE 0xffffffffU +#define ATLC_CRC__PRESERVED 0x00000000U +#define ATLC_CRC__RESET_VALUE 0x00000000U + +#endif /* __ATLC_CRC_MACRO__ */ + +/** @} end of crc */ + +/* macros for BlueprintGlobalNameSpace::ATLC_cmd */ +/** + * @defgroup at_lc_regs_core_cmd cmd + * @brief Contains register fields associated with cmd. definitions. + * @{ + */ +#ifndef __ATLC_CMD_MACRO__ +#define __ATLC_CMD_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details start command immediately sw needs to clear to idle after issuing command 0x00 idle 0x01 power down 0x02 start tx flow 0x03 start rx flow 0x04 flush tx fifo 0x05 flush rx fifo + * @{ + */ +#define ATLC_CMD__VL__SHIFT 0 +#define ATLC_CMD__VL__WIDTH 8 +#define ATLC_CMD__VL__MASK 0x000000ffU +#define ATLC_CMD__VL__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_CMD__VL__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define ATLC_CMD__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define ATLC_CMD__VL__VERIFY(src) (!(((uint32_t)(src) & ~0x000000ffU))) +#define ATLC_CMD__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_CMD__TYPE uint32_t +#define ATLC_CMD__READ 0x000000ffU +#define ATLC_CMD__WRITE 0x000000ffU +#define ATLC_CMD__PRESERVED 0x00000000U +#define ATLC_CMD__RESET_VALUE 0x00000000U + +#endif /* __ATLC_CMD_MACRO__ */ + +/** @} end of cmd */ + +/* macros for BlueprintGlobalNameSpace::ATLC_cmd_p5us */ +/** + * @defgroup at_lc_regs_core_cmd_p5us cmd_p5us + * @brief Contains register fields associated with cmd_p5us. definitions. + * @{ + */ +#ifndef __ATLC_CMD_P5US_MACRO__ +#define __ATLC_CMD_P5US_MACRO__ + +/* macros for field tm_stmp */ +/** + * @defgroup at_lc_regs_core_tm_stmp_field tm_stmp_field + * @brief macros for field tm_stmp + * @details define the time when the command will be executed, in unit of 0.5 micro second if tm_stmp is 0, command is executed immediately. + * @{ + */ +#define ATLC_CMD_P5US__TM_STMP__SHIFT 0 +#define ATLC_CMD_P5US__TM_STMP__WIDTH 16 +#define ATLC_CMD_P5US__TM_STMP__MASK 0x0000ffffU +#define ATLC_CMD_P5US__TM_STMP__READ(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_CMD_P5US__TM_STMP__WRITE(src) ((uint32_t)(src) & 0x0000ffffU) +#define ATLC_CMD_P5US__TM_STMP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((uint32_t)(src) &\ + 0x0000ffffU) +#define ATLC_CMD_P5US__TM_STMP__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000ffffU))) +#define ATLC_CMD_P5US__TM_STMP__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_CMD_P5US__TYPE uint32_t +#define ATLC_CMD_P5US__READ 0x0000ffffU +#define ATLC_CMD_P5US__WRITE 0x0000ffffU +#define ATLC_CMD_P5US__PRESERVED 0x00000000U +#define ATLC_CMD_P5US__RESET_VALUE 0x00000000U + +#endif /* __ATLC_CMD_P5US_MACRO__ */ + +/** @} end of cmd_p5us */ + +/* macros for BlueprintGlobalNameSpace::ATLC_cmd_312p5us */ +/** + * @defgroup at_lc_regs_core_cmd_312p5us cmd_312p5us + * @brief Contains register fields associated with cmd_312p5us. definitions. + * @{ + */ +#ifndef __ATLC_CMD_312P5US_MACRO__ +#define __ATLC_CMD_312P5US_MACRO__ + +/* macros for field tm_stmp */ +/** + * @defgroup at_lc_regs_core_tm_stmp_field tm_stmp_field + * @brief macros for field tm_stmp + * @details define the time when the command will be executed, in unit of 312.5 micro second if tm_stmp is 0, command is executed immediately. + * @{ + */ +#define ATLC_CMD_312P5US__TM_STMP__SHIFT 0 +#define ATLC_CMD_312P5US__TM_STMP__WIDTH 32 +#define ATLC_CMD_312P5US__TM_STMP__MASK 0xffffffffU +#define ATLC_CMD_312P5US__TM_STMP__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_CMD_312P5US__TM_STMP__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_CMD_312P5US__TM_STMP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_CMD_312P5US__TM_STMP__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define ATLC_CMD_312P5US__TM_STMP__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_CMD_312P5US__TYPE uint32_t +#define ATLC_CMD_312P5US__READ 0xffffffffU +#define ATLC_CMD_312P5US__WRITE 0xffffffffU +#define ATLC_CMD_312P5US__PRESERVED 0x00000000U +#define ATLC_CMD_312P5US__RESET_VALUE 0x00000000U + +#endif /* __ATLC_CMD_312P5US_MACRO__ */ + +/** @} end of cmd_312p5us */ + +/* macros for BlueprintGlobalNameSpace::ATLC_nd_st */ +/** + * @defgroup at_lc_regs_core_nd_st nd_st + * @brief Contains register fields associated with nd_st. definitions. + * @{ + */ +#ifndef __ATLC_ND_ST_MACRO__ +#define __ATLC_ND_ST_MACRO__ + +/* macros for field rx_drdy_nd */ +/** + * @defgroup at_lc_regs_core_rx_drdy_nd_field rx_drdy_nd_field + * @brief macros for field rx_drdy_nd + * @details node number for the receive data ready interrupt + * @{ + */ +#define ATLC_ND_ST__RX_DRDY_ND__SHIFT 0 +#define ATLC_ND_ST__RX_DRDY_ND__WIDTH 3 +#define ATLC_ND_ST__RX_DRDY_ND__MASK 0x00000007U +#define ATLC_ND_ST__RX_DRDY_ND__READ(src) ((uint32_t)(src) & 0x00000007U) +#define ATLC_ND_ST__RX_DRDY_ND__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rff_of_nd */ +/** + * @defgroup at_lc_regs_core_rff_of_nd_field rff_of_nd_field + * @brief macros for field rff_of_nd + * @details node number for the receive fifo overflow interrupt + * @{ + */ +#define ATLC_ND_ST__RFF_OF_ND__SHIFT 4 +#define ATLC_ND_ST__RFF_OF_ND__WIDTH 3 +#define ATLC_ND_ST__RFF_OF_ND__MASK 0x00000070U +#define ATLC_ND_ST__RFF_OF_ND__READ(src) (((uint32_t)(src) & 0x00000070U) >> 4) +#define ATLC_ND_ST__RFF_OF_ND__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tff_uf_nd */ +/** + * @defgroup at_lc_regs_core_tff_uf_nd_field tff_uf_nd_field + * @brief macros for field tff_uf_nd + * @details node number for the receive fifo underflow interrupt + * @{ + */ +#define ATLC_ND_ST__TFF_UF_ND__SHIFT 8 +#define ATLC_ND_ST__TFF_UF_ND__WIDTH 3 +#define ATLC_ND_ST__TFF_UF_ND__MASK 0x00000700U +#define ATLC_ND_ST__TFF_UF_ND__READ(src) (((uint32_t)(src) & 0x00000700U) >> 8) +#define ATLC_ND_ST__TFF_UF_ND__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rmff_of_nd */ +/** + * @defgroup at_lc_regs_core_rmff_of_nd_field rmff_of_nd_field + * @brief macros for field rmff_of_nd + * @details node number for the memory receive fifo overflow interrupt + * @{ + */ +#define ATLC_ND_ST__RMFF_OF_ND__SHIFT 12 +#define ATLC_ND_ST__RMFF_OF_ND__WIDTH 3 +#define ATLC_ND_ST__RMFF_OF_ND__MASK 0x00007000U +#define ATLC_ND_ST__RMFF_OF_ND__READ(src) \ + (((uint32_t)(src)\ + & 0x00007000U) >> 12) +#define ATLC_ND_ST__RMFF_OF_ND__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tmff_uf_nd */ +/** + * @defgroup at_lc_regs_core_tmff_uf_nd_field tmff_uf_nd_field + * @brief macros for field tmff_uf_nd + * @details node number for the memory transmit fifo underflow interrupt + * @{ + */ +#define ATLC_ND_ST__TMFF_UF_ND__SHIFT 16 +#define ATLC_ND_ST__TMFF_UF_ND__WIDTH 3 +#define ATLC_ND_ST__TMFF_UF_ND__MASK 0x00070000U +#define ATLC_ND_ST__TMFF_UF_ND__READ(src) \ + (((uint32_t)(src)\ + & 0x00070000U) >> 16) +#define ATLC_ND_ST__TMFF_UF_ND__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_ND_ST__TYPE uint32_t +#define ATLC_ND_ST__READ 0x00077777U +#define ATLC_ND_ST__PRESERVED 0x00000000U +#define ATLC_ND_ST__RESET_VALUE 0x00000000U + +#endif /* __ATLC_ND_ST_MACRO__ */ + +/** @} end of nd_st */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_irq */ +/** + * @defgroup at_lc_regs_core_lc_irq lc_irq + * @brief Contains register fields associated with lc_irq. definitions. + * @{ + */ +#ifndef __ATLC_LC_IRQ_MACRO__ +#define __ATLC_LC_IRQ_MACRO__ + +/* macros for field tx_dsnt */ +/** + * @defgroup at_lc_regs_core_tx_dsnt_field tx_dsnt_field + * @brief macros for field tx_dsnt + * @details interrupt for transmit data sent + * @{ + */ +#define ATLC_LC_IRQ__TX_DSNT__SHIFT 0 +#define ATLC_LC_IRQ__TX_DSNT__WIDTH 1 +#define ATLC_LC_IRQ__TX_DSNT__MASK 0x00000001U +#define ATLC_LC_IRQ__TX_DSNT__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATLC_LC_IRQ__TX_DSNT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATLC_LC_IRQ__TX_DSNT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATLC_LC_IRQ__TX_DSNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_drdy */ +/** + * @defgroup at_lc_regs_core_rx_drdy_field rx_drdy_field + * @brief macros for field rx_drdy + * @details interrupt for receive data ready + * @{ + */ +#define ATLC_LC_IRQ__RX_DRDY__SHIFT 1 +#define ATLC_LC_IRQ__RX_DRDY__WIDTH 1 +#define ATLC_LC_IRQ__RX_DRDY__MASK 0x00000002U +#define ATLC_LC_IRQ__RX_DRDY__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define ATLC_LC_IRQ__RX_DRDY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATLC_LC_IRQ__RX_DRDY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATLC_LC_IRQ__RX_DRDY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field max_rt */ +/** + * @defgroup at_lc_regs_core_max_rt_field max_rt_field + * @brief macros for field max_rt + * @details interrupt for maximum number of retransmission + * @{ + */ +#define ATLC_LC_IRQ__MAX_RT__SHIFT 2 +#define ATLC_LC_IRQ__MAX_RT__WIDTH 1 +#define ATLC_LC_IRQ__MAX_RT__MASK 0x00000004U +#define ATLC_LC_IRQ__MAX_RT__READ(src) (((uint32_t)(src) & 0x00000004U) >> 2) +#define ATLC_LC_IRQ__MAX_RT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define ATLC_LC_IRQ__MAX_RT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define ATLC_LC_IRQ__MAX_RT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_to */ +/** + * @defgroup at_lc_regs_core_rx_to_field rx_to_field + * @brief macros for field rx_to + * @details interrupt for receive time out + * @{ + */ +#define ATLC_LC_IRQ__RX_TO__SHIFT 3 +#define ATLC_LC_IRQ__RX_TO__WIDTH 1 +#define ATLC_LC_IRQ__RX_TO__MASK 0x00000008U +#define ATLC_LC_IRQ__RX_TO__READ(src) (((uint32_t)(src) & 0x00000008U) >> 3) +#define ATLC_LC_IRQ__RX_TO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define ATLC_LC_IRQ__RX_TO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define ATLC_LC_IRQ__RX_TO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rff_of */ +/** + * @defgroup at_lc_regs_core_rff_of_field rff_of_field + * @brief macros for field rff_of + * @details interrupt for receive fifo overflow + * @{ + */ +#define ATLC_LC_IRQ__RFF_OF__SHIFT 4 +#define ATLC_LC_IRQ__RFF_OF__WIDTH 1 +#define ATLC_LC_IRQ__RFF_OF__MASK 0x00000010U +#define ATLC_LC_IRQ__RFF_OF__READ(src) (((uint32_t)(src) & 0x00000010U) >> 4) +#define ATLC_LC_IRQ__RFF_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define ATLC_LC_IRQ__RFF_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define ATLC_LC_IRQ__RFF_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tff_uf */ +/** + * @defgroup at_lc_regs_core_tff_uf_field tff_uf_field + * @brief macros for field tff_uf + * @details interrupt for transmit fifo underflow + * @{ + */ +#define ATLC_LC_IRQ__TFF_UF__SHIFT 5 +#define ATLC_LC_IRQ__TFF_UF__WIDTH 1 +#define ATLC_LC_IRQ__TFF_UF__MASK 0x00000020U +#define ATLC_LC_IRQ__TFF_UF__READ(src) (((uint32_t)(src) & 0x00000020U) >> 5) +#define ATLC_LC_IRQ__TFF_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define ATLC_LC_IRQ__TFF_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define ATLC_LC_IRQ__TFF_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rmff_of */ +/** + * @defgroup at_lc_regs_core_rmff_of_field rmff_of_field + * @brief macros for field rmff_of + * @details interrupt for memory receive fifo overflow + * @{ + */ +#define ATLC_LC_IRQ__RMFF_OF__SHIFT 6 +#define ATLC_LC_IRQ__RMFF_OF__WIDTH 1 +#define ATLC_LC_IRQ__RMFF_OF__MASK 0x00000040U +#define ATLC_LC_IRQ__RMFF_OF__READ(src) (((uint32_t)(src) & 0x00000040U) >> 6) +#define ATLC_LC_IRQ__RMFF_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define ATLC_LC_IRQ__RMFF_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define ATLC_LC_IRQ__RMFF_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tmff_uf */ +/** + * @defgroup at_lc_regs_core_tmff_uf_field tmff_uf_field + * @brief macros for field tmff_uf + * @details interrupt for memory transmit fifo underflow + * @{ + */ +#define ATLC_LC_IRQ__TMFF_UF__SHIFT 7 +#define ATLC_LC_IRQ__TMFF_UF__WIDTH 1 +#define ATLC_LC_IRQ__TMFF_UF__MASK 0x00000080U +#define ATLC_LC_IRQ__TMFF_UF__READ(src) (((uint32_t)(src) & 0x00000080U) >> 7) +#define ATLC_LC_IRQ__TMFF_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define ATLC_LC_IRQ__TMFF_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define ATLC_LC_IRQ__TMFF_UF__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_LC_IRQ__TYPE uint32_t +#define ATLC_LC_IRQ__READ 0x000000ffU +#define ATLC_LC_IRQ__PRESERVED 0x00000000U +#define ATLC_LC_IRQ__RESET_VALUE 0x00000000U + +#endif /* __ATLC_LC_IRQ_MACRO__ */ + +/** @} end of lc_irq */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_irqm */ +/** + * @defgroup at_lc_regs_core_lc_irqm lc_irqm + * @brief Contains register fields associated with lc_irqm. definitions. + * @{ + */ +#ifndef __ATLC_LC_IRQM_MACRO__ +#define __ATLC_LC_IRQM_MACRO__ + +/* macros for field tx_dsnt */ +/** + * @defgroup at_lc_regs_core_tx_dsnt_field tx_dsnt_field + * @brief macros for field tx_dsnt + * @details interrupt mask for transmit data sent + * @{ + */ +#define ATLC_LC_IRQM__TX_DSNT__SHIFT 0 +#define ATLC_LC_IRQM__TX_DSNT__WIDTH 1 +#define ATLC_LC_IRQM__TX_DSNT__MASK 0x00000001U +#define ATLC_LC_IRQM__TX_DSNT__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATLC_LC_IRQM__TX_DSNT__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define ATLC_LC_IRQM__TX_DSNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATLC_LC_IRQM__TX_DSNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define ATLC_LC_IRQM__TX_DSNT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATLC_LC_IRQM__TX_DSNT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATLC_LC_IRQM__TX_DSNT__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field rx_drdy */ +/** + * @defgroup at_lc_regs_core_rx_drdy_field rx_drdy_field + * @brief macros for field rx_drdy + * @details interrupt mask for receive data ready + * @{ + */ +#define ATLC_LC_IRQM__RX_DRDY__SHIFT 1 +#define ATLC_LC_IRQM__RX_DRDY__WIDTH 1 +#define ATLC_LC_IRQM__RX_DRDY__MASK 0x00000002U +#define ATLC_LC_IRQM__RX_DRDY__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define ATLC_LC_IRQM__RX_DRDY__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define ATLC_LC_IRQM__RX_DRDY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define ATLC_LC_IRQM__RX_DRDY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define ATLC_LC_IRQM__RX_DRDY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATLC_LC_IRQM__RX_DRDY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATLC_LC_IRQM__RX_DRDY__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field max_rt */ +/** + * @defgroup at_lc_regs_core_max_rt_field max_rt_field + * @brief macros for field max_rt + * @details interrupt mask for maximum number of retransmission + * @{ + */ +#define ATLC_LC_IRQM__MAX_RT__SHIFT 2 +#define ATLC_LC_IRQM__MAX_RT__WIDTH 1 +#define ATLC_LC_IRQM__MAX_RT__MASK 0x00000004U +#define ATLC_LC_IRQM__MAX_RT__READ(src) (((uint32_t)(src) & 0x00000004U) >> 2) +#define ATLC_LC_IRQM__MAX_RT__WRITE(src) (((uint32_t)(src) << 2) & 0x00000004U) +#define ATLC_LC_IRQM__MAX_RT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define ATLC_LC_IRQM__MAX_RT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define ATLC_LC_IRQM__MAX_RT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define ATLC_LC_IRQM__MAX_RT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define ATLC_LC_IRQM__MAX_RT__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field rx_to */ +/** + * @defgroup at_lc_regs_core_rx_to_field rx_to_field + * @brief macros for field rx_to + * @details interrupt mask for receive time out + * @{ + */ +#define ATLC_LC_IRQM__RX_TO__SHIFT 3 +#define ATLC_LC_IRQM__RX_TO__WIDTH 1 +#define ATLC_LC_IRQM__RX_TO__MASK 0x00000008U +#define ATLC_LC_IRQM__RX_TO__READ(src) (((uint32_t)(src) & 0x00000008U) >> 3) +#define ATLC_LC_IRQM__RX_TO__WRITE(src) (((uint32_t)(src) << 3) & 0x00000008U) +#define ATLC_LC_IRQM__RX_TO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define ATLC_LC_IRQM__RX_TO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define ATLC_LC_IRQM__RX_TO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define ATLC_LC_IRQM__RX_TO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define ATLC_LC_IRQM__RX_TO__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field rff_of */ +/** + * @defgroup at_lc_regs_core_rff_of_field rff_of_field + * @brief macros for field rff_of + * @details interrupt mask for receive fifo overflow + * @{ + */ +#define ATLC_LC_IRQM__RFF_OF__SHIFT 4 +#define ATLC_LC_IRQM__RFF_OF__WIDTH 1 +#define ATLC_LC_IRQM__RFF_OF__MASK 0x00000010U +#define ATLC_LC_IRQM__RFF_OF__READ(src) (((uint32_t)(src) & 0x00000010U) >> 4) +#define ATLC_LC_IRQM__RFF_OF__WRITE(src) (((uint32_t)(src) << 4) & 0x00000010U) +#define ATLC_LC_IRQM__RFF_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define ATLC_LC_IRQM__RFF_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define ATLC_LC_IRQM__RFF_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define ATLC_LC_IRQM__RFF_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define ATLC_LC_IRQM__RFF_OF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field tff_uf */ +/** + * @defgroup at_lc_regs_core_tff_uf_field tff_uf_field + * @brief macros for field tff_uf + * @details interrupt mask for transmit fifo underflow + * @{ + */ +#define ATLC_LC_IRQM__TFF_UF__SHIFT 5 +#define ATLC_LC_IRQM__TFF_UF__WIDTH 1 +#define ATLC_LC_IRQM__TFF_UF__MASK 0x00000020U +#define ATLC_LC_IRQM__TFF_UF__READ(src) (((uint32_t)(src) & 0x00000020U) >> 5) +#define ATLC_LC_IRQM__TFF_UF__WRITE(src) (((uint32_t)(src) << 5) & 0x00000020U) +#define ATLC_LC_IRQM__TFF_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define ATLC_LC_IRQM__TFF_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define ATLC_LC_IRQM__TFF_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define ATLC_LC_IRQM__TFF_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define ATLC_LC_IRQM__TFF_UF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field rmff_of */ +/** + * @defgroup at_lc_regs_core_rmff_of_field rmff_of_field + * @brief macros for field rmff_of + * @details interrupt mask for memory receive fifo overflow + * @{ + */ +#define ATLC_LC_IRQM__RMFF_OF__SHIFT 6 +#define ATLC_LC_IRQM__RMFF_OF__WIDTH 1 +#define ATLC_LC_IRQM__RMFF_OF__MASK 0x00000040U +#define ATLC_LC_IRQM__RMFF_OF__READ(src) (((uint32_t)(src) & 0x00000040U) >> 6) +#define ATLC_LC_IRQM__RMFF_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define ATLC_LC_IRQM__RMFF_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define ATLC_LC_IRQM__RMFF_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define ATLC_LC_IRQM__RMFF_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define ATLC_LC_IRQM__RMFF_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define ATLC_LC_IRQM__RMFF_OF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field tmff_uf */ +/** + * @defgroup at_lc_regs_core_tmff_uf_field tmff_uf_field + * @brief macros for field tmff_uf + * @details interrupt mask for memory transmit fifo underflow + * @{ + */ +#define ATLC_LC_IRQM__TMFF_UF__SHIFT 7 +#define ATLC_LC_IRQM__TMFF_UF__WIDTH 1 +#define ATLC_LC_IRQM__TMFF_UF__MASK 0x00000080U +#define ATLC_LC_IRQM__TMFF_UF__READ(src) (((uint32_t)(src) & 0x00000080U) >> 7) +#define ATLC_LC_IRQM__TMFF_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define ATLC_LC_IRQM__TMFF_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define ATLC_LC_IRQM__TMFF_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define ATLC_LC_IRQM__TMFF_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define ATLC_LC_IRQM__TMFF_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define ATLC_LC_IRQM__TMFF_UF__RESET_VALUE 0x00000001U +/** @} */ +#define ATLC_LC_IRQM__TYPE uint32_t +#define ATLC_LC_IRQM__READ 0x000000ffU +#define ATLC_LC_IRQM__WRITE 0x000000ffU +#define ATLC_LC_IRQM__PRESERVED 0x00000000U +#define ATLC_LC_IRQM__RESET_VALUE 0x000000ffU + +#endif /* __ATLC_LC_IRQM_MACRO__ */ + +/** @} end of lc_irqm */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_irqs */ +/** + * @defgroup at_lc_regs_core_lc_irqs lc_irqs + * @brief Contains register fields associated with lc_irqs. definitions. + * @{ + */ +#ifndef __ATLC_LC_IRQS_MACRO__ +#define __ATLC_LC_IRQS_MACRO__ + +/* macros for field tx_dsnt */ +/** + * @defgroup at_lc_regs_core_tx_dsnt_field tx_dsnt_field + * @brief macros for field tx_dsnt + * @details interrupt for transmit data sent, write 1 to set + * @{ + */ +#define ATLC_LC_IRQS__TX_DSNT__SHIFT 0 +#define ATLC_LC_IRQS__TX_DSNT__WIDTH 1 +#define ATLC_LC_IRQS__TX_DSNT__MASK 0x00000001U +#define ATLC_LC_IRQS__TX_DSNT__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATLC_LC_IRQS__TX_DSNT__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define ATLC_LC_IRQS__TX_DSNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATLC_LC_IRQS__TX_DSNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define ATLC_LC_IRQS__TX_DSNT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATLC_LC_IRQS__TX_DSNT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATLC_LC_IRQS__TX_DSNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_drdy */ +/** + * @defgroup at_lc_regs_core_rx_drdy_field rx_drdy_field + * @brief macros for field rx_drdy + * @details interrupt for receive data ready, write 1 to set + * @{ + */ +#define ATLC_LC_IRQS__RX_DRDY__SHIFT 1 +#define ATLC_LC_IRQS__RX_DRDY__WIDTH 1 +#define ATLC_LC_IRQS__RX_DRDY__MASK 0x00000002U +#define ATLC_LC_IRQS__RX_DRDY__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define ATLC_LC_IRQS__RX_DRDY__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define ATLC_LC_IRQS__RX_DRDY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define ATLC_LC_IRQS__RX_DRDY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define ATLC_LC_IRQS__RX_DRDY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATLC_LC_IRQS__RX_DRDY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATLC_LC_IRQS__RX_DRDY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field max_rt */ +/** + * @defgroup at_lc_regs_core_max_rt_field max_rt_field + * @brief macros for field max_rt + * @details interrupt for maximum number of retransmission, write 1 to set + * @{ + */ +#define ATLC_LC_IRQS__MAX_RT__SHIFT 2 +#define ATLC_LC_IRQS__MAX_RT__WIDTH 1 +#define ATLC_LC_IRQS__MAX_RT__MASK 0x00000004U +#define ATLC_LC_IRQS__MAX_RT__READ(src) (((uint32_t)(src) & 0x00000004U) >> 2) +#define ATLC_LC_IRQS__MAX_RT__WRITE(src) (((uint32_t)(src) << 2) & 0x00000004U) +#define ATLC_LC_IRQS__MAX_RT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define ATLC_LC_IRQS__MAX_RT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define ATLC_LC_IRQS__MAX_RT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define ATLC_LC_IRQS__MAX_RT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define ATLC_LC_IRQS__MAX_RT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_to */ +/** + * @defgroup at_lc_regs_core_rx_to_field rx_to_field + * @brief macros for field rx_to + * @details interrupt for receive time out, write 1 to set + * @{ + */ +#define ATLC_LC_IRQS__RX_TO__SHIFT 3 +#define ATLC_LC_IRQS__RX_TO__WIDTH 1 +#define ATLC_LC_IRQS__RX_TO__MASK 0x00000008U +#define ATLC_LC_IRQS__RX_TO__READ(src) (((uint32_t)(src) & 0x00000008U) >> 3) +#define ATLC_LC_IRQS__RX_TO__WRITE(src) (((uint32_t)(src) << 3) & 0x00000008U) +#define ATLC_LC_IRQS__RX_TO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define ATLC_LC_IRQS__RX_TO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define ATLC_LC_IRQS__RX_TO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define ATLC_LC_IRQS__RX_TO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define ATLC_LC_IRQS__RX_TO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rff_of */ +/** + * @defgroup at_lc_regs_core_rff_of_field rff_of_field + * @brief macros for field rff_of + * @details interrupt for receive fifo overflow, write 1 to set + * @{ + */ +#define ATLC_LC_IRQS__RFF_OF__SHIFT 4 +#define ATLC_LC_IRQS__RFF_OF__WIDTH 1 +#define ATLC_LC_IRQS__RFF_OF__MASK 0x00000010U +#define ATLC_LC_IRQS__RFF_OF__READ(src) (((uint32_t)(src) & 0x00000010U) >> 4) +#define ATLC_LC_IRQS__RFF_OF__WRITE(src) (((uint32_t)(src) << 4) & 0x00000010U) +#define ATLC_LC_IRQS__RFF_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define ATLC_LC_IRQS__RFF_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define ATLC_LC_IRQS__RFF_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define ATLC_LC_IRQS__RFF_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define ATLC_LC_IRQS__RFF_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tff_uf */ +/** + * @defgroup at_lc_regs_core_tff_uf_field tff_uf_field + * @brief macros for field tff_uf + * @details interrupt for transmit fifo underflow, write 1 to set + * @{ + */ +#define ATLC_LC_IRQS__TFF_UF__SHIFT 5 +#define ATLC_LC_IRQS__TFF_UF__WIDTH 1 +#define ATLC_LC_IRQS__TFF_UF__MASK 0x00000020U +#define ATLC_LC_IRQS__TFF_UF__READ(src) (((uint32_t)(src) & 0x00000020U) >> 5) +#define ATLC_LC_IRQS__TFF_UF__WRITE(src) (((uint32_t)(src) << 5) & 0x00000020U) +#define ATLC_LC_IRQS__TFF_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define ATLC_LC_IRQS__TFF_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define ATLC_LC_IRQS__TFF_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define ATLC_LC_IRQS__TFF_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define ATLC_LC_IRQS__TFF_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rmff_of */ +/** + * @defgroup at_lc_regs_core_rmff_of_field rmff_of_field + * @brief macros for field rmff_of + * @details interrupt for memory receive fifo overflow, write 1 to set + * @{ + */ +#define ATLC_LC_IRQS__RMFF_OF__SHIFT 6 +#define ATLC_LC_IRQS__RMFF_OF__WIDTH 1 +#define ATLC_LC_IRQS__RMFF_OF__MASK 0x00000040U +#define ATLC_LC_IRQS__RMFF_OF__READ(src) (((uint32_t)(src) & 0x00000040U) >> 6) +#define ATLC_LC_IRQS__RMFF_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define ATLC_LC_IRQS__RMFF_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define ATLC_LC_IRQS__RMFF_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define ATLC_LC_IRQS__RMFF_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define ATLC_LC_IRQS__RMFF_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define ATLC_LC_IRQS__RMFF_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tmff_uf */ +/** + * @defgroup at_lc_regs_core_tmff_uf_field tmff_uf_field + * @brief macros for field tmff_uf + * @details interrupt for memory transmit fifo underflow, write 1 to set + * @{ + */ +#define ATLC_LC_IRQS__TMFF_UF__SHIFT 7 +#define ATLC_LC_IRQS__TMFF_UF__WIDTH 1 +#define ATLC_LC_IRQS__TMFF_UF__MASK 0x00000080U +#define ATLC_LC_IRQS__TMFF_UF__READ(src) (((uint32_t)(src) & 0x00000080U) >> 7) +#define ATLC_LC_IRQS__TMFF_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define ATLC_LC_IRQS__TMFF_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define ATLC_LC_IRQS__TMFF_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define ATLC_LC_IRQS__TMFF_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define ATLC_LC_IRQS__TMFF_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define ATLC_LC_IRQS__TMFF_UF__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_LC_IRQS__TYPE uint32_t +#define ATLC_LC_IRQS__READ 0x000000ffU +#define ATLC_LC_IRQS__WRITE 0x000000ffU +#define ATLC_LC_IRQS__PRESERVED 0x00000000U +#define ATLC_LC_IRQS__RESET_VALUE 0x00000000U + +#endif /* __ATLC_LC_IRQS_MACRO__ */ + +/** @} end of lc_irqs */ + +/* macros for BlueprintGlobalNameSpace::ATLC_lc_irqc */ +/** + * @defgroup at_lc_regs_core_lc_irqc lc_irqc + * @brief Contains register fields associated with lc_irqc. definitions. + * @{ + */ +#ifndef __ATLC_LC_IRQC_MACRO__ +#define __ATLC_LC_IRQC_MACRO__ + +/* macros for field tx_dsnt */ +/** + * @defgroup at_lc_regs_core_tx_dsnt_field tx_dsnt_field + * @brief macros for field tx_dsnt + * @details interrupt for transmit data sent, write 1 to clear + * @{ + */ +#define ATLC_LC_IRQC__TX_DSNT__SHIFT 0 +#define ATLC_LC_IRQC__TX_DSNT__WIDTH 1 +#define ATLC_LC_IRQC__TX_DSNT__MASK 0x00000001U +#define ATLC_LC_IRQC__TX_DSNT__READ(src) ((uint32_t)(src) & 0x00000001U) +#define ATLC_LC_IRQC__TX_DSNT__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define ATLC_LC_IRQC__TX_DSNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define ATLC_LC_IRQC__TX_DSNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define ATLC_LC_IRQC__TX_DSNT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define ATLC_LC_IRQC__TX_DSNT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define ATLC_LC_IRQC__TX_DSNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_drdy */ +/** + * @defgroup at_lc_regs_core_rx_drdy_field rx_drdy_field + * @brief macros for field rx_drdy + * @details interrupt for receive data ready, write 1 to clear + * @{ + */ +#define ATLC_LC_IRQC__RX_DRDY__SHIFT 1 +#define ATLC_LC_IRQC__RX_DRDY__WIDTH 1 +#define ATLC_LC_IRQC__RX_DRDY__MASK 0x00000002U +#define ATLC_LC_IRQC__RX_DRDY__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define ATLC_LC_IRQC__RX_DRDY__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define ATLC_LC_IRQC__RX_DRDY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define ATLC_LC_IRQC__RX_DRDY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define ATLC_LC_IRQC__RX_DRDY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define ATLC_LC_IRQC__RX_DRDY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define ATLC_LC_IRQC__RX_DRDY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field max_rt */ +/** + * @defgroup at_lc_regs_core_max_rt_field max_rt_field + * @brief macros for field max_rt + * @details interrupt for maximum number of retransmission, write 1 to clear + * @{ + */ +#define ATLC_LC_IRQC__MAX_RT__SHIFT 2 +#define ATLC_LC_IRQC__MAX_RT__WIDTH 1 +#define ATLC_LC_IRQC__MAX_RT__MASK 0x00000004U +#define ATLC_LC_IRQC__MAX_RT__READ(src) (((uint32_t)(src) & 0x00000004U) >> 2) +#define ATLC_LC_IRQC__MAX_RT__WRITE(src) (((uint32_t)(src) << 2) & 0x00000004U) +#define ATLC_LC_IRQC__MAX_RT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define ATLC_LC_IRQC__MAX_RT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define ATLC_LC_IRQC__MAX_RT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define ATLC_LC_IRQC__MAX_RT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define ATLC_LC_IRQC__MAX_RT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_to */ +/** + * @defgroup at_lc_regs_core_rx_to_field rx_to_field + * @brief macros for field rx_to + * @details interrupt for receive time out, write 1 to clear + * @{ + */ +#define ATLC_LC_IRQC__RX_TO__SHIFT 3 +#define ATLC_LC_IRQC__RX_TO__WIDTH 1 +#define ATLC_LC_IRQC__RX_TO__MASK 0x00000008U +#define ATLC_LC_IRQC__RX_TO__READ(src) (((uint32_t)(src) & 0x00000008U) >> 3) +#define ATLC_LC_IRQC__RX_TO__WRITE(src) (((uint32_t)(src) << 3) & 0x00000008U) +#define ATLC_LC_IRQC__RX_TO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define ATLC_LC_IRQC__RX_TO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define ATLC_LC_IRQC__RX_TO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define ATLC_LC_IRQC__RX_TO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define ATLC_LC_IRQC__RX_TO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rff_of */ +/** + * @defgroup at_lc_regs_core_rff_of_field rff_of_field + * @brief macros for field rff_of + * @details interrupt for receive fifo overflow, write 1 to clear + * @{ + */ +#define ATLC_LC_IRQC__RFF_OF__SHIFT 4 +#define ATLC_LC_IRQC__RFF_OF__WIDTH 1 +#define ATLC_LC_IRQC__RFF_OF__MASK 0x00000010U +#define ATLC_LC_IRQC__RFF_OF__READ(src) (((uint32_t)(src) & 0x00000010U) >> 4) +#define ATLC_LC_IRQC__RFF_OF__WRITE(src) (((uint32_t)(src) << 4) & 0x00000010U) +#define ATLC_LC_IRQC__RFF_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define ATLC_LC_IRQC__RFF_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define ATLC_LC_IRQC__RFF_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define ATLC_LC_IRQC__RFF_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define ATLC_LC_IRQC__RFF_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tff_uf */ +/** + * @defgroup at_lc_regs_core_tff_uf_field tff_uf_field + * @brief macros for field tff_uf + * @details interrupt for transmit fifo underflow, write 1 to clear + * @{ + */ +#define ATLC_LC_IRQC__TFF_UF__SHIFT 5 +#define ATLC_LC_IRQC__TFF_UF__WIDTH 1 +#define ATLC_LC_IRQC__TFF_UF__MASK 0x00000020U +#define ATLC_LC_IRQC__TFF_UF__READ(src) (((uint32_t)(src) & 0x00000020U) >> 5) +#define ATLC_LC_IRQC__TFF_UF__WRITE(src) (((uint32_t)(src) << 5) & 0x00000020U) +#define ATLC_LC_IRQC__TFF_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define ATLC_LC_IRQC__TFF_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define ATLC_LC_IRQC__TFF_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define ATLC_LC_IRQC__TFF_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define ATLC_LC_IRQC__TFF_UF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rmff_of */ +/** + * @defgroup at_lc_regs_core_rmff_of_field rmff_of_field + * @brief macros for field rmff_of + * @details interrupt for memory receive fifo overflow, write 1 to clear + * @{ + */ +#define ATLC_LC_IRQC__RMFF_OF__SHIFT 6 +#define ATLC_LC_IRQC__RMFF_OF__WIDTH 1 +#define ATLC_LC_IRQC__RMFF_OF__MASK 0x00000040U +#define ATLC_LC_IRQC__RMFF_OF__READ(src) (((uint32_t)(src) & 0x00000040U) >> 6) +#define ATLC_LC_IRQC__RMFF_OF__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define ATLC_LC_IRQC__RMFF_OF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define ATLC_LC_IRQC__RMFF_OF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define ATLC_LC_IRQC__RMFF_OF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define ATLC_LC_IRQC__RMFF_OF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define ATLC_LC_IRQC__RMFF_OF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tmff_uf */ +/** + * @defgroup at_lc_regs_core_tmff_uf_field tmff_uf_field + * @brief macros for field tmff_uf + * @details interrupt for memory transmit fifo underflow, write 1 to clear + * @{ + */ +#define ATLC_LC_IRQC__TMFF_UF__SHIFT 7 +#define ATLC_LC_IRQC__TMFF_UF__WIDTH 1 +#define ATLC_LC_IRQC__TMFF_UF__MASK 0x00000080U +#define ATLC_LC_IRQC__TMFF_UF__READ(src) (((uint32_t)(src) & 0x00000080U) >> 7) +#define ATLC_LC_IRQC__TMFF_UF__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define ATLC_LC_IRQC__TMFF_UF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define ATLC_LC_IRQC__TMFF_UF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define ATLC_LC_IRQC__TMFF_UF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define ATLC_LC_IRQC__TMFF_UF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define ATLC_LC_IRQC__TMFF_UF__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_LC_IRQC__TYPE uint32_t +#define ATLC_LC_IRQC__READ 0x000000ffU +#define ATLC_LC_IRQC__WRITE 0x000000ffU +#define ATLC_LC_IRQC__PRESERVED 0x00000000U +#define ATLC_LC_IRQC__RESET_VALUE 0x00000000U + +#endif /* __ATLC_LC_IRQC_MACRO__ */ + +/** @} end of lc_irqc */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aesctrl */ +/** + * @defgroup at_lc_regs_core_aesctrl aesctrl + * @brief Contains register fields associated with aesctrl. definitions. + * @{ + */ +#ifndef __ATLC_AESCTRL_MACRO__ +#define __ATLC_AESCTRL_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES control + * @{ + */ +#define ATLC_AESCTRL__VL__SHIFT 0 +#define ATLC_AESCTRL__VL__WIDTH 32 +#define ATLC_AESCTRL__VL__MASK 0xffffffffU +#define ATLC_AESCTRL__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESCTRL__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESCTRL__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESCTRL__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_AESCTRL__VL__RESET_VALUE 0x000000c0U +/** @} */ +#define ATLC_AESCTRL__TYPE uint32_t +#define ATLC_AESCTRL__READ 0xffffffffU +#define ATLC_AESCTRL__WRITE 0xffffffffU +#define ATLC_AESCTRL__PRESERVED 0x00000000U +#define ATLC_AESCTRL__RESET_VALUE 0x000000c0U + +#endif /* __ATLC_AESCTRL_MACRO__ */ + +/** @} end of aesctrl */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskey_s0_0 */ +/** + * @defgroup at_lc_regs_core_aeskey_s0_0 aeskey_s0_0 + * @brief Contains register fields associated with aeskey_s0_0. definitions. + * @{ + */ +#ifndef __ATLC_AESKEY_S0_0_MACRO__ +#define __ATLC_AESKEY_S0_0_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share0 key [31:0] + * @{ + */ +#define ATLC_AESKEY_S0_0__VL__SHIFT 0 +#define ATLC_AESKEY_S0_0__VL__WIDTH 32 +#define ATLC_AESKEY_S0_0__VL__MASK 0xffffffffU +#define ATLC_AESKEY_S0_0__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S0_0__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S0_0__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEY_S0_0__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_AESKEY_S0_0__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEY_S0_0__TYPE uint32_t +#define ATLC_AESKEY_S0_0__READ 0xffffffffU +#define ATLC_AESKEY_S0_0__WRITE 0xffffffffU +#define ATLC_AESKEY_S0_0__PRESERVED 0x00000000U +#define ATLC_AESKEY_S0_0__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEY_S0_0_MACRO__ */ + +/** @} end of aeskey_s0_0 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskey_s0_1 */ +/** + * @defgroup at_lc_regs_core_aeskey_s0_1 aeskey_s0_1 + * @brief Contains register fields associated with aeskey_s0_1. definitions. + * @{ + */ +#ifndef __ATLC_AESKEY_S0_1_MACRO__ +#define __ATLC_AESKEY_S0_1_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share0 key [63:32] + * @{ + */ +#define ATLC_AESKEY_S0_1__VL__SHIFT 0 +#define ATLC_AESKEY_S0_1__VL__WIDTH 32 +#define ATLC_AESKEY_S0_1__VL__MASK 0xffffffffU +#define ATLC_AESKEY_S0_1__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S0_1__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S0_1__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEY_S0_1__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_AESKEY_S0_1__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEY_S0_1__TYPE uint32_t +#define ATLC_AESKEY_S0_1__READ 0xffffffffU +#define ATLC_AESKEY_S0_1__WRITE 0xffffffffU +#define ATLC_AESKEY_S0_1__PRESERVED 0x00000000U +#define ATLC_AESKEY_S0_1__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEY_S0_1_MACRO__ */ + +/** @} end of aeskey_s0_1 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskey_s0_2 */ +/** + * @defgroup at_lc_regs_core_aeskey_s0_2 aeskey_s0_2 + * @brief Contains register fields associated with aeskey_s0_2. definitions. + * @{ + */ +#ifndef __ATLC_AESKEY_S0_2_MACRO__ +#define __ATLC_AESKEY_S0_2_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share0 key [95:64] + * @{ + */ +#define ATLC_AESKEY_S0_2__VL__SHIFT 0 +#define ATLC_AESKEY_S0_2__VL__WIDTH 32 +#define ATLC_AESKEY_S0_2__VL__MASK 0xffffffffU +#define ATLC_AESKEY_S0_2__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S0_2__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S0_2__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEY_S0_2__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_AESKEY_S0_2__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEY_S0_2__TYPE uint32_t +#define ATLC_AESKEY_S0_2__READ 0xffffffffU +#define ATLC_AESKEY_S0_2__WRITE 0xffffffffU +#define ATLC_AESKEY_S0_2__PRESERVED 0x00000000U +#define ATLC_AESKEY_S0_2__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEY_S0_2_MACRO__ */ + +/** @} end of aeskey_s0_2 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskey_s0_3 */ +/** + * @defgroup at_lc_regs_core_aeskey_s0_3 aeskey_s0_3 + * @brief Contains register fields associated with aeskey_s0_3. definitions. + * @{ + */ +#ifndef __ATLC_AESKEY_S0_3_MACRO__ +#define __ATLC_AESKEY_S0_3_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share0 key [127:96] + * @{ + */ +#define ATLC_AESKEY_S0_3__VL__SHIFT 0 +#define ATLC_AESKEY_S0_3__VL__WIDTH 32 +#define ATLC_AESKEY_S0_3__VL__MASK 0xffffffffU +#define ATLC_AESKEY_S0_3__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S0_3__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S0_3__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEY_S0_3__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_AESKEY_S0_3__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEY_S0_3__TYPE uint32_t +#define ATLC_AESKEY_S0_3__READ 0xffffffffU +#define ATLC_AESKEY_S0_3__WRITE 0xffffffffU +#define ATLC_AESKEY_S0_3__PRESERVED 0x00000000U +#define ATLC_AESKEY_S0_3__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEY_S0_3_MACRO__ */ + +/** @} end of aeskey_s0_3 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskey_s0_4 */ +/** + * @defgroup at_lc_regs_core_aeskey_s0_4 aeskey_s0_4 + * @brief Contains register fields associated with aeskey_s0_4. definitions. + * @{ + */ +#ifndef __ATLC_AESKEY_S0_4_MACRO__ +#define __ATLC_AESKEY_S0_4_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share0 key [159:128] + * @{ + */ +#define ATLC_AESKEY_S0_4__VL__SHIFT 0 +#define ATLC_AESKEY_S0_4__VL__WIDTH 32 +#define ATLC_AESKEY_S0_4__VL__MASK 0xffffffffU +#define ATLC_AESKEY_S0_4__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S0_4__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S0_4__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEY_S0_4__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_AESKEY_S0_4__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEY_S0_4__TYPE uint32_t +#define ATLC_AESKEY_S0_4__READ 0xffffffffU +#define ATLC_AESKEY_S0_4__WRITE 0xffffffffU +#define ATLC_AESKEY_S0_4__PRESERVED 0x00000000U +#define ATLC_AESKEY_S0_4__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEY_S0_4_MACRO__ */ + +/** @} end of aeskey_s0_4 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskey_s0_5 */ +/** + * @defgroup at_lc_regs_core_aeskey_s0_5 aeskey_s0_5 + * @brief Contains register fields associated with aeskey_s0_5. definitions. + * @{ + */ +#ifndef __ATLC_AESKEY_S0_5_MACRO__ +#define __ATLC_AESKEY_S0_5_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share0 key [191:160] + * @{ + */ +#define ATLC_AESKEY_S0_5__VL__SHIFT 0 +#define ATLC_AESKEY_S0_5__VL__WIDTH 32 +#define ATLC_AESKEY_S0_5__VL__MASK 0xffffffffU +#define ATLC_AESKEY_S0_5__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S0_5__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S0_5__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEY_S0_5__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_AESKEY_S0_5__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEY_S0_5__TYPE uint32_t +#define ATLC_AESKEY_S0_5__READ 0xffffffffU +#define ATLC_AESKEY_S0_5__WRITE 0xffffffffU +#define ATLC_AESKEY_S0_5__PRESERVED 0x00000000U +#define ATLC_AESKEY_S0_5__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEY_S0_5_MACRO__ */ + +/** @} end of aeskey_s0_5 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskey_s0_6 */ +/** + * @defgroup at_lc_regs_core_aeskey_s0_6 aeskey_s0_6 + * @brief Contains register fields associated with aeskey_s0_6. definitions. + * @{ + */ +#ifndef __ATLC_AESKEY_S0_6_MACRO__ +#define __ATLC_AESKEY_S0_6_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share0 key [223:192] + * @{ + */ +#define ATLC_AESKEY_S0_6__VL__SHIFT 0 +#define ATLC_AESKEY_S0_6__VL__WIDTH 32 +#define ATLC_AESKEY_S0_6__VL__MASK 0xffffffffU +#define ATLC_AESKEY_S0_6__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S0_6__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S0_6__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEY_S0_6__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_AESKEY_S0_6__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEY_S0_6__TYPE uint32_t +#define ATLC_AESKEY_S0_6__READ 0xffffffffU +#define ATLC_AESKEY_S0_6__WRITE 0xffffffffU +#define ATLC_AESKEY_S0_6__PRESERVED 0x00000000U +#define ATLC_AESKEY_S0_6__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEY_S0_6_MACRO__ */ + +/** @} end of aeskey_s0_6 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskey_s0_7 */ +/** + * @defgroup at_lc_regs_core_aeskey_s0_7 aeskey_s0_7 + * @brief Contains register fields associated with aeskey_s0_7. definitions. + * @{ + */ +#ifndef __ATLC_AESKEY_S0_7_MACRO__ +#define __ATLC_AESKEY_S0_7_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share0 key [255:224] + * @{ + */ +#define ATLC_AESKEY_S0_7__VL__SHIFT 0 +#define ATLC_AESKEY_S0_7__VL__WIDTH 32 +#define ATLC_AESKEY_S0_7__VL__MASK 0xffffffffU +#define ATLC_AESKEY_S0_7__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S0_7__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S0_7__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEY_S0_7__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_AESKEY_S0_7__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEY_S0_7__TYPE uint32_t +#define ATLC_AESKEY_S0_7__READ 0xffffffffU +#define ATLC_AESKEY_S0_7__WRITE 0xffffffffU +#define ATLC_AESKEY_S0_7__PRESERVED 0x00000000U +#define ATLC_AESKEY_S0_7__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEY_S0_7_MACRO__ */ + +/** @} end of aeskey_s0_7 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskey_s1_0 */ +/** + * @defgroup at_lc_regs_core_aeskey_s1_0 aeskey_s1_0 + * @brief Contains register fields associated with aeskey_s1_0. definitions. + * @{ + */ +#ifndef __ATLC_AESKEY_S1_0_MACRO__ +#define __ATLC_AESKEY_S1_0_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share1 key [31:0] + * @{ + */ +#define ATLC_AESKEY_S1_0__VL__SHIFT 0 +#define ATLC_AESKEY_S1_0__VL__WIDTH 32 +#define ATLC_AESKEY_S1_0__VL__MASK 0xffffffffU +#define ATLC_AESKEY_S1_0__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S1_0__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S1_0__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEY_S1_0__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_AESKEY_S1_0__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEY_S1_0__TYPE uint32_t +#define ATLC_AESKEY_S1_0__READ 0xffffffffU +#define ATLC_AESKEY_S1_0__WRITE 0xffffffffU +#define ATLC_AESKEY_S1_0__PRESERVED 0x00000000U +#define ATLC_AESKEY_S1_0__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEY_S1_0_MACRO__ */ + +/** @} end of aeskey_s1_0 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskey_s1_1 */ +/** + * @defgroup at_lc_regs_core_aeskey_s1_1 aeskey_s1_1 + * @brief Contains register fields associated with aeskey_s1_1. definitions. + * @{ + */ +#ifndef __ATLC_AESKEY_S1_1_MACRO__ +#define __ATLC_AESKEY_S1_1_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share1 key [63:32] + * @{ + */ +#define ATLC_AESKEY_S1_1__VL__SHIFT 0 +#define ATLC_AESKEY_S1_1__VL__WIDTH 32 +#define ATLC_AESKEY_S1_1__VL__MASK 0xffffffffU +#define ATLC_AESKEY_S1_1__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S1_1__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S1_1__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEY_S1_1__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_AESKEY_S1_1__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEY_S1_1__TYPE uint32_t +#define ATLC_AESKEY_S1_1__READ 0xffffffffU +#define ATLC_AESKEY_S1_1__WRITE 0xffffffffU +#define ATLC_AESKEY_S1_1__PRESERVED 0x00000000U +#define ATLC_AESKEY_S1_1__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEY_S1_1_MACRO__ */ + +/** @} end of aeskey_s1_1 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskey_s1_2 */ +/** + * @defgroup at_lc_regs_core_aeskey_s1_2 aeskey_s1_2 + * @brief Contains register fields associated with aeskey_s1_2. definitions. + * @{ + */ +#ifndef __ATLC_AESKEY_S1_2_MACRO__ +#define __ATLC_AESKEY_S1_2_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share1 key [95:64] + * @{ + */ +#define ATLC_AESKEY_S1_2__VL__SHIFT 0 +#define ATLC_AESKEY_S1_2__VL__WIDTH 32 +#define ATLC_AESKEY_S1_2__VL__MASK 0xffffffffU +#define ATLC_AESKEY_S1_2__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S1_2__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S1_2__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEY_S1_2__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_AESKEY_S1_2__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEY_S1_2__TYPE uint32_t +#define ATLC_AESKEY_S1_2__READ 0xffffffffU +#define ATLC_AESKEY_S1_2__WRITE 0xffffffffU +#define ATLC_AESKEY_S1_2__PRESERVED 0x00000000U +#define ATLC_AESKEY_S1_2__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEY_S1_2_MACRO__ */ + +/** @} end of aeskey_s1_2 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskey_s1_3 */ +/** + * @defgroup at_lc_regs_core_aeskey_s1_3 aeskey_s1_3 + * @brief Contains register fields associated with aeskey_s1_3. definitions. + * @{ + */ +#ifndef __ATLC_AESKEY_S1_3_MACRO__ +#define __ATLC_AESKEY_S1_3_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share1 key [127:96] + * @{ + */ +#define ATLC_AESKEY_S1_3__VL__SHIFT 0 +#define ATLC_AESKEY_S1_3__VL__WIDTH 32 +#define ATLC_AESKEY_S1_3__VL__MASK 0xffffffffU +#define ATLC_AESKEY_S1_3__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S1_3__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S1_3__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEY_S1_3__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_AESKEY_S1_3__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEY_S1_3__TYPE uint32_t +#define ATLC_AESKEY_S1_3__READ 0xffffffffU +#define ATLC_AESKEY_S1_3__WRITE 0xffffffffU +#define ATLC_AESKEY_S1_3__PRESERVED 0x00000000U +#define ATLC_AESKEY_S1_3__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEY_S1_3_MACRO__ */ + +/** @} end of aeskey_s1_3 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskey_s1_4 */ +/** + * @defgroup at_lc_regs_core_aeskey_s1_4 aeskey_s1_4 + * @brief Contains register fields associated with aeskey_s1_4. definitions. + * @{ + */ +#ifndef __ATLC_AESKEY_S1_4_MACRO__ +#define __ATLC_AESKEY_S1_4_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share1 key [159:128] + * @{ + */ +#define ATLC_AESKEY_S1_4__VL__SHIFT 0 +#define ATLC_AESKEY_S1_4__VL__WIDTH 32 +#define ATLC_AESKEY_S1_4__VL__MASK 0xffffffffU +#define ATLC_AESKEY_S1_4__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S1_4__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S1_4__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEY_S1_4__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_AESKEY_S1_4__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEY_S1_4__TYPE uint32_t +#define ATLC_AESKEY_S1_4__READ 0xffffffffU +#define ATLC_AESKEY_S1_4__WRITE 0xffffffffU +#define ATLC_AESKEY_S1_4__PRESERVED 0x00000000U +#define ATLC_AESKEY_S1_4__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEY_S1_4_MACRO__ */ + +/** @} end of aeskey_s1_4 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskey_s1_5 */ +/** + * @defgroup at_lc_regs_core_aeskey_s1_5 aeskey_s1_5 + * @brief Contains register fields associated with aeskey_s1_5. definitions. + * @{ + */ +#ifndef __ATLC_AESKEY_S1_5_MACRO__ +#define __ATLC_AESKEY_S1_5_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share1 key [191:160] + * @{ + */ +#define ATLC_AESKEY_S1_5__VL__SHIFT 0 +#define ATLC_AESKEY_S1_5__VL__WIDTH 32 +#define ATLC_AESKEY_S1_5__VL__MASK 0xffffffffU +#define ATLC_AESKEY_S1_5__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S1_5__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S1_5__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEY_S1_5__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_AESKEY_S1_5__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEY_S1_5__TYPE uint32_t +#define ATLC_AESKEY_S1_5__READ 0xffffffffU +#define ATLC_AESKEY_S1_5__WRITE 0xffffffffU +#define ATLC_AESKEY_S1_5__PRESERVED 0x00000000U +#define ATLC_AESKEY_S1_5__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEY_S1_5_MACRO__ */ + +/** @} end of aeskey_s1_5 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskey_s1_6 */ +/** + * @defgroup at_lc_regs_core_aeskey_s1_6 aeskey_s1_6 + * @brief Contains register fields associated with aeskey_s1_6. definitions. + * @{ + */ +#ifndef __ATLC_AESKEY_S1_6_MACRO__ +#define __ATLC_AESKEY_S1_6_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share1 key [223:192] + * @{ + */ +#define ATLC_AESKEY_S1_6__VL__SHIFT 0 +#define ATLC_AESKEY_S1_6__VL__WIDTH 32 +#define ATLC_AESKEY_S1_6__VL__MASK 0xffffffffU +#define ATLC_AESKEY_S1_6__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S1_6__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S1_6__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEY_S1_6__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_AESKEY_S1_6__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEY_S1_6__TYPE uint32_t +#define ATLC_AESKEY_S1_6__READ 0xffffffffU +#define ATLC_AESKEY_S1_6__WRITE 0xffffffffU +#define ATLC_AESKEY_S1_6__PRESERVED 0x00000000U +#define ATLC_AESKEY_S1_6__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEY_S1_6_MACRO__ */ + +/** @} end of aeskey_s1_6 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskey_s1_7 */ +/** + * @defgroup at_lc_regs_core_aeskey_s1_7 aeskey_s1_7 + * @brief Contains register fields associated with aeskey_s1_7. definitions. + * @{ + */ +#ifndef __ATLC_AESKEY_S1_7_MACRO__ +#define __ATLC_AESKEY_S1_7_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share1 key [255:224] + * @{ + */ +#define ATLC_AESKEY_S1_7__VL__SHIFT 0 +#define ATLC_AESKEY_S1_7__VL__WIDTH 32 +#define ATLC_AESKEY_S1_7__VL__MASK 0xffffffffU +#define ATLC_AESKEY_S1_7__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S1_7__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEY_S1_7__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEY_S1_7__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_AESKEY_S1_7__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEY_S1_7__TYPE uint32_t +#define ATLC_AESKEY_S1_7__READ 0xffffffffU +#define ATLC_AESKEY_S1_7__WRITE 0xffffffffU +#define ATLC_AESKEY_S1_7__PRESERVED 0x00000000U +#define ATLC_AESKEY_S1_7__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEY_S1_7_MACRO__ */ + +/** @} end of aeskey_s1_7 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_iv0 */ +/** + * @defgroup at_lc_regs_core_iv0 iv0 + * @brief Contains register fields associated with iv0. definitions. + * @{ + */ +#ifndef __ATLC_IV0_MACRO__ +#define __ATLC_IV0_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details initial vector [31:0] + * @{ + */ +#define ATLC_IV0__VL__SHIFT 0 +#define ATLC_IV0__VL__WIDTH 32 +#define ATLC_IV0__VL__MASK 0xffffffffU +#define ATLC_IV0__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_IV0__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_IV0__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_IV0__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_IV0__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_IV0__TYPE uint32_t +#define ATLC_IV0__READ 0xffffffffU +#define ATLC_IV0__WRITE 0xffffffffU +#define ATLC_IV0__PRESERVED 0x00000000U +#define ATLC_IV0__RESET_VALUE 0x00000000U + +#endif /* __ATLC_IV0_MACRO__ */ + +/** @} end of iv0 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_iv1 */ +/** + * @defgroup at_lc_regs_core_iv1 iv1 + * @brief Contains register fields associated with iv1. definitions. + * @{ + */ +#ifndef __ATLC_IV1_MACRO__ +#define __ATLC_IV1_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details initial vector [63:32] + * @{ + */ +#define ATLC_IV1__VL__SHIFT 0 +#define ATLC_IV1__VL__WIDTH 32 +#define ATLC_IV1__VL__MASK 0xffffffffU +#define ATLC_IV1__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_IV1__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_IV1__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_IV1__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_IV1__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_IV1__TYPE uint32_t +#define ATLC_IV1__READ 0xffffffffU +#define ATLC_IV1__WRITE 0xffffffffU +#define ATLC_IV1__PRESERVED 0x00000000U +#define ATLC_IV1__RESET_VALUE 0x00000000U + +#endif /* __ATLC_IV1_MACRO__ */ + +/** @} end of iv1 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_iv2 */ +/** + * @defgroup at_lc_regs_core_iv2 iv2 + * @brief Contains register fields associated with iv2. definitions. + * @{ + */ +#ifndef __ATLC_IV2_MACRO__ +#define __ATLC_IV2_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details initial vector [95:64] + * @{ + */ +#define ATLC_IV2__VL__SHIFT 0 +#define ATLC_IV2__VL__WIDTH 32 +#define ATLC_IV2__VL__MASK 0xffffffffU +#define ATLC_IV2__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_IV2__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_IV2__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_IV2__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_IV2__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_IV2__TYPE uint32_t +#define ATLC_IV2__READ 0xffffffffU +#define ATLC_IV2__WRITE 0xffffffffU +#define ATLC_IV2__PRESERVED 0x00000000U +#define ATLC_IV2__RESET_VALUE 0x00000000U + +#endif /* __ATLC_IV2_MACRO__ */ + +/** @} end of iv2 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_iv3 */ +/** + * @defgroup at_lc_regs_core_iv3 iv3 + * @brief Contains register fields associated with iv3. definitions. + * @{ + */ +#ifndef __ATLC_IV3_MACRO__ +#define __ATLC_IV3_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details initial vector [127:96] + * @{ + */ +#define ATLC_IV3__VL__SHIFT 0 +#define ATLC_IV3__VL__WIDTH 32 +#define ATLC_IV3__VL__MASK 0xffffffffU +#define ATLC_IV3__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_IV3__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_IV3__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_IV3__VL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define ATLC_IV3__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_IV3__TYPE uint32_t +#define ATLC_IV3__READ 0xffffffffU +#define ATLC_IV3__WRITE 0xffffffffU +#define ATLC_IV3__PRESERVED 0x00000000U +#define ATLC_IV3__RESET_VALUE 0x00000000U + +#endif /* __ATLC_IV3_MACRO__ */ + +/** @} end of iv3 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskeysl_s0_0 */ +/** + * @defgroup at_lc_regs_core_aeskeysl_s0_0 aeskeysl_s0_0 + * @brief Contains register fields associated with aeskeysl_s0_0. definitions. + * @{ + */ +#ifndef __ATLC_AESKEYSL_S0_0_MACRO__ +#define __ATLC_AESKEYSL_S0_0_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share0 key [31:0] + * @{ + */ +#define ATLC_AESKEYSL_S0_0__VL__SHIFT 0 +#define ATLC_AESKEYSL_S0_0__VL__WIDTH 32 +#define ATLC_AESKEYSL_S0_0__VL__MASK 0xffffffffU +#define ATLC_AESKEYSL_S0_0__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S0_0__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S0_0__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEYSL_S0_0__VL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define ATLC_AESKEYSL_S0_0__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEYSL_S0_0__TYPE uint32_t +#define ATLC_AESKEYSL_S0_0__READ 0xffffffffU +#define ATLC_AESKEYSL_S0_0__WRITE 0xffffffffU +#define ATLC_AESKEYSL_S0_0__PRESERVED 0x00000000U +#define ATLC_AESKEYSL_S0_0__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEYSL_S0_0_MACRO__ */ + +/** @} end of aeskeysl_s0_0 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskeysl_s0_1 */ +/** + * @defgroup at_lc_regs_core_aeskeysl_s0_1 aeskeysl_s0_1 + * @brief Contains register fields associated with aeskeysl_s0_1. definitions. + * @{ + */ +#ifndef __ATLC_AESKEYSL_S0_1_MACRO__ +#define __ATLC_AESKEYSL_S0_1_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share0 key [63:32] + * @{ + */ +#define ATLC_AESKEYSL_S0_1__VL__SHIFT 0 +#define ATLC_AESKEYSL_S0_1__VL__WIDTH 32 +#define ATLC_AESKEYSL_S0_1__VL__MASK 0xffffffffU +#define ATLC_AESKEYSL_S0_1__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S0_1__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S0_1__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEYSL_S0_1__VL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define ATLC_AESKEYSL_S0_1__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEYSL_S0_1__TYPE uint32_t +#define ATLC_AESKEYSL_S0_1__READ 0xffffffffU +#define ATLC_AESKEYSL_S0_1__WRITE 0xffffffffU +#define ATLC_AESKEYSL_S0_1__PRESERVED 0x00000000U +#define ATLC_AESKEYSL_S0_1__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEYSL_S0_1_MACRO__ */ + +/** @} end of aeskeysl_s0_1 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskeysl_s0_2 */ +/** + * @defgroup at_lc_regs_core_aeskeysl_s0_2 aeskeysl_s0_2 + * @brief Contains register fields associated with aeskeysl_s0_2. definitions. + * @{ + */ +#ifndef __ATLC_AESKEYSL_S0_2_MACRO__ +#define __ATLC_AESKEYSL_S0_2_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share0 key [95:64] + * @{ + */ +#define ATLC_AESKEYSL_S0_2__VL__SHIFT 0 +#define ATLC_AESKEYSL_S0_2__VL__WIDTH 32 +#define ATLC_AESKEYSL_S0_2__VL__MASK 0xffffffffU +#define ATLC_AESKEYSL_S0_2__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S0_2__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S0_2__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEYSL_S0_2__VL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define ATLC_AESKEYSL_S0_2__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEYSL_S0_2__TYPE uint32_t +#define ATLC_AESKEYSL_S0_2__READ 0xffffffffU +#define ATLC_AESKEYSL_S0_2__WRITE 0xffffffffU +#define ATLC_AESKEYSL_S0_2__PRESERVED 0x00000000U +#define ATLC_AESKEYSL_S0_2__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEYSL_S0_2_MACRO__ */ + +/** @} end of aeskeysl_s0_2 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskeysl_s0_3 */ +/** + * @defgroup at_lc_regs_core_aeskeysl_s0_3 aeskeysl_s0_3 + * @brief Contains register fields associated with aeskeysl_s0_3. definitions. + * @{ + */ +#ifndef __ATLC_AESKEYSL_S0_3_MACRO__ +#define __ATLC_AESKEYSL_S0_3_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share0 key [127:96] + * @{ + */ +#define ATLC_AESKEYSL_S0_3__VL__SHIFT 0 +#define ATLC_AESKEYSL_S0_3__VL__WIDTH 32 +#define ATLC_AESKEYSL_S0_3__VL__MASK 0xffffffffU +#define ATLC_AESKEYSL_S0_3__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S0_3__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S0_3__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEYSL_S0_3__VL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define ATLC_AESKEYSL_S0_3__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEYSL_S0_3__TYPE uint32_t +#define ATLC_AESKEYSL_S0_3__READ 0xffffffffU +#define ATLC_AESKEYSL_S0_3__WRITE 0xffffffffU +#define ATLC_AESKEYSL_S0_3__PRESERVED 0x00000000U +#define ATLC_AESKEYSL_S0_3__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEYSL_S0_3_MACRO__ */ + +/** @} end of aeskeysl_s0_3 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskeysl_s0_4 */ +/** + * @defgroup at_lc_regs_core_aeskeysl_s0_4 aeskeysl_s0_4 + * @brief Contains register fields associated with aeskeysl_s0_4. definitions. + * @{ + */ +#ifndef __ATLC_AESKEYSL_S0_4_MACRO__ +#define __ATLC_AESKEYSL_S0_4_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share0 key [159:128] + * @{ + */ +#define ATLC_AESKEYSL_S0_4__VL__SHIFT 0 +#define ATLC_AESKEYSL_S0_4__VL__WIDTH 32 +#define ATLC_AESKEYSL_S0_4__VL__MASK 0xffffffffU +#define ATLC_AESKEYSL_S0_4__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S0_4__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S0_4__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEYSL_S0_4__VL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define ATLC_AESKEYSL_S0_4__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEYSL_S0_4__TYPE uint32_t +#define ATLC_AESKEYSL_S0_4__READ 0xffffffffU +#define ATLC_AESKEYSL_S0_4__WRITE 0xffffffffU +#define ATLC_AESKEYSL_S0_4__PRESERVED 0x00000000U +#define ATLC_AESKEYSL_S0_4__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEYSL_S0_4_MACRO__ */ + +/** @} end of aeskeysl_s0_4 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskeysl_s0_5 */ +/** + * @defgroup at_lc_regs_core_aeskeysl_s0_5 aeskeysl_s0_5 + * @brief Contains register fields associated with aeskeysl_s0_5. definitions. + * @{ + */ +#ifndef __ATLC_AESKEYSL_S0_5_MACRO__ +#define __ATLC_AESKEYSL_S0_5_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share0 key [191:160] + * @{ + */ +#define ATLC_AESKEYSL_S0_5__VL__SHIFT 0 +#define ATLC_AESKEYSL_S0_5__VL__WIDTH 32 +#define ATLC_AESKEYSL_S0_5__VL__MASK 0xffffffffU +#define ATLC_AESKEYSL_S0_5__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S0_5__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S0_5__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEYSL_S0_5__VL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define ATLC_AESKEYSL_S0_5__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEYSL_S0_5__TYPE uint32_t +#define ATLC_AESKEYSL_S0_5__READ 0xffffffffU +#define ATLC_AESKEYSL_S0_5__WRITE 0xffffffffU +#define ATLC_AESKEYSL_S0_5__PRESERVED 0x00000000U +#define ATLC_AESKEYSL_S0_5__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEYSL_S0_5_MACRO__ */ + +/** @} end of aeskeysl_s0_5 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskeysl_s0_6 */ +/** + * @defgroup at_lc_regs_core_aeskeysl_s0_6 aeskeysl_s0_6 + * @brief Contains register fields associated with aeskeysl_s0_6. definitions. + * @{ + */ +#ifndef __ATLC_AESKEYSL_S0_6_MACRO__ +#define __ATLC_AESKEYSL_S0_6_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share0 key [223:192] + * @{ + */ +#define ATLC_AESKEYSL_S0_6__VL__SHIFT 0 +#define ATLC_AESKEYSL_S0_6__VL__WIDTH 32 +#define ATLC_AESKEYSL_S0_6__VL__MASK 0xffffffffU +#define ATLC_AESKEYSL_S0_6__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S0_6__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S0_6__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEYSL_S0_6__VL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define ATLC_AESKEYSL_S0_6__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEYSL_S0_6__TYPE uint32_t +#define ATLC_AESKEYSL_S0_6__READ 0xffffffffU +#define ATLC_AESKEYSL_S0_6__WRITE 0xffffffffU +#define ATLC_AESKEYSL_S0_6__PRESERVED 0x00000000U +#define ATLC_AESKEYSL_S0_6__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEYSL_S0_6_MACRO__ */ + +/** @} end of aeskeysl_s0_6 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskeysl_s0_7 */ +/** + * @defgroup at_lc_regs_core_aeskeysl_s0_7 aeskeysl_s0_7 + * @brief Contains register fields associated with aeskeysl_s0_7. definitions. + * @{ + */ +#ifndef __ATLC_AESKEYSL_S0_7_MACRO__ +#define __ATLC_AESKEYSL_S0_7_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share0 key [255:224] + * @{ + */ +#define ATLC_AESKEYSL_S0_7__VL__SHIFT 0 +#define ATLC_AESKEYSL_S0_7__VL__WIDTH 32 +#define ATLC_AESKEYSL_S0_7__VL__MASK 0xffffffffU +#define ATLC_AESKEYSL_S0_7__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S0_7__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S0_7__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEYSL_S0_7__VL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define ATLC_AESKEYSL_S0_7__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEYSL_S0_7__TYPE uint32_t +#define ATLC_AESKEYSL_S0_7__READ 0xffffffffU +#define ATLC_AESKEYSL_S0_7__WRITE 0xffffffffU +#define ATLC_AESKEYSL_S0_7__PRESERVED 0x00000000U +#define ATLC_AESKEYSL_S0_7__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEYSL_S0_7_MACRO__ */ + +/** @} end of aeskeysl_s0_7 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskeysl_s1_0 */ +/** + * @defgroup at_lc_regs_core_aeskeysl_s1_0 aeskeysl_s1_0 + * @brief Contains register fields associated with aeskeysl_s1_0. definitions. + * @{ + */ +#ifndef __ATLC_AESKEYSL_S1_0_MACRO__ +#define __ATLC_AESKEYSL_S1_0_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share1 key [31:0] + * @{ + */ +#define ATLC_AESKEYSL_S1_0__VL__SHIFT 0 +#define ATLC_AESKEYSL_S1_0__VL__WIDTH 32 +#define ATLC_AESKEYSL_S1_0__VL__MASK 0xffffffffU +#define ATLC_AESKEYSL_S1_0__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S1_0__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S1_0__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEYSL_S1_0__VL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define ATLC_AESKEYSL_S1_0__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEYSL_S1_0__TYPE uint32_t +#define ATLC_AESKEYSL_S1_0__READ 0xffffffffU +#define ATLC_AESKEYSL_S1_0__WRITE 0xffffffffU +#define ATLC_AESKEYSL_S1_0__PRESERVED 0x00000000U +#define ATLC_AESKEYSL_S1_0__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEYSL_S1_0_MACRO__ */ + +/** @} end of aeskeysl_s1_0 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskeysl_s1_1 */ +/** + * @defgroup at_lc_regs_core_aeskeysl_s1_1 aeskeysl_s1_1 + * @brief Contains register fields associated with aeskeysl_s1_1. definitions. + * @{ + */ +#ifndef __ATLC_AESKEYSL_S1_1_MACRO__ +#define __ATLC_AESKEYSL_S1_1_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share1 key [63:32] + * @{ + */ +#define ATLC_AESKEYSL_S1_1__VL__SHIFT 0 +#define ATLC_AESKEYSL_S1_1__VL__WIDTH 32 +#define ATLC_AESKEYSL_S1_1__VL__MASK 0xffffffffU +#define ATLC_AESKEYSL_S1_1__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S1_1__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S1_1__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEYSL_S1_1__VL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define ATLC_AESKEYSL_S1_1__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEYSL_S1_1__TYPE uint32_t +#define ATLC_AESKEYSL_S1_1__READ 0xffffffffU +#define ATLC_AESKEYSL_S1_1__WRITE 0xffffffffU +#define ATLC_AESKEYSL_S1_1__PRESERVED 0x00000000U +#define ATLC_AESKEYSL_S1_1__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEYSL_S1_1_MACRO__ */ + +/** @} end of aeskeysl_s1_1 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskeysl_s1_2 */ +/** + * @defgroup at_lc_regs_core_aeskeysl_s1_2 aeskeysl_s1_2 + * @brief Contains register fields associated with aeskeysl_s1_2. definitions. + * @{ + */ +#ifndef __ATLC_AESKEYSL_S1_2_MACRO__ +#define __ATLC_AESKEYSL_S1_2_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share1 key [95:64] + * @{ + */ +#define ATLC_AESKEYSL_S1_2__VL__SHIFT 0 +#define ATLC_AESKEYSL_S1_2__VL__WIDTH 32 +#define ATLC_AESKEYSL_S1_2__VL__MASK 0xffffffffU +#define ATLC_AESKEYSL_S1_2__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S1_2__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S1_2__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEYSL_S1_2__VL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define ATLC_AESKEYSL_S1_2__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEYSL_S1_2__TYPE uint32_t +#define ATLC_AESKEYSL_S1_2__READ 0xffffffffU +#define ATLC_AESKEYSL_S1_2__WRITE 0xffffffffU +#define ATLC_AESKEYSL_S1_2__PRESERVED 0x00000000U +#define ATLC_AESKEYSL_S1_2__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEYSL_S1_2_MACRO__ */ + +/** @} end of aeskeysl_s1_2 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskeysl_s1_3 */ +/** + * @defgroup at_lc_regs_core_aeskeysl_s1_3 aeskeysl_s1_3 + * @brief Contains register fields associated with aeskeysl_s1_3. definitions. + * @{ + */ +#ifndef __ATLC_AESKEYSL_S1_3_MACRO__ +#define __ATLC_AESKEYSL_S1_3_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share1 key [127:96] + * @{ + */ +#define ATLC_AESKEYSL_S1_3__VL__SHIFT 0 +#define ATLC_AESKEYSL_S1_3__VL__WIDTH 32 +#define ATLC_AESKEYSL_S1_3__VL__MASK 0xffffffffU +#define ATLC_AESKEYSL_S1_3__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S1_3__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S1_3__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEYSL_S1_3__VL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define ATLC_AESKEYSL_S1_3__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEYSL_S1_3__TYPE uint32_t +#define ATLC_AESKEYSL_S1_3__READ 0xffffffffU +#define ATLC_AESKEYSL_S1_3__WRITE 0xffffffffU +#define ATLC_AESKEYSL_S1_3__PRESERVED 0x00000000U +#define ATLC_AESKEYSL_S1_3__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEYSL_S1_3_MACRO__ */ + +/** @} end of aeskeysl_s1_3 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskeysl_s1_4 */ +/** + * @defgroup at_lc_regs_core_aeskeysl_s1_4 aeskeysl_s1_4 + * @brief Contains register fields associated with aeskeysl_s1_4. definitions. + * @{ + */ +#ifndef __ATLC_AESKEYSL_S1_4_MACRO__ +#define __ATLC_AESKEYSL_S1_4_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share1 key [159:128] + * @{ + */ +#define ATLC_AESKEYSL_S1_4__VL__SHIFT 0 +#define ATLC_AESKEYSL_S1_4__VL__WIDTH 32 +#define ATLC_AESKEYSL_S1_4__VL__MASK 0xffffffffU +#define ATLC_AESKEYSL_S1_4__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S1_4__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S1_4__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEYSL_S1_4__VL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define ATLC_AESKEYSL_S1_4__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEYSL_S1_4__TYPE uint32_t +#define ATLC_AESKEYSL_S1_4__READ 0xffffffffU +#define ATLC_AESKEYSL_S1_4__WRITE 0xffffffffU +#define ATLC_AESKEYSL_S1_4__PRESERVED 0x00000000U +#define ATLC_AESKEYSL_S1_4__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEYSL_S1_4_MACRO__ */ + +/** @} end of aeskeysl_s1_4 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskeysl_s1_5 */ +/** + * @defgroup at_lc_regs_core_aeskeysl_s1_5 aeskeysl_s1_5 + * @brief Contains register fields associated with aeskeysl_s1_5. definitions. + * @{ + */ +#ifndef __ATLC_AESKEYSL_S1_5_MACRO__ +#define __ATLC_AESKEYSL_S1_5_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share1 key [191:160] + * @{ + */ +#define ATLC_AESKEYSL_S1_5__VL__SHIFT 0 +#define ATLC_AESKEYSL_S1_5__VL__WIDTH 32 +#define ATLC_AESKEYSL_S1_5__VL__MASK 0xffffffffU +#define ATLC_AESKEYSL_S1_5__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S1_5__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S1_5__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEYSL_S1_5__VL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define ATLC_AESKEYSL_S1_5__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEYSL_S1_5__TYPE uint32_t +#define ATLC_AESKEYSL_S1_5__READ 0xffffffffU +#define ATLC_AESKEYSL_S1_5__WRITE 0xffffffffU +#define ATLC_AESKEYSL_S1_5__PRESERVED 0x00000000U +#define ATLC_AESKEYSL_S1_5__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEYSL_S1_5_MACRO__ */ + +/** @} end of aeskeysl_s1_5 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskeysl_s1_6 */ +/** + * @defgroup at_lc_regs_core_aeskeysl_s1_6 aeskeysl_s1_6 + * @brief Contains register fields associated with aeskeysl_s1_6. definitions. + * @{ + */ +#ifndef __ATLC_AESKEYSL_S1_6_MACRO__ +#define __ATLC_AESKEYSL_S1_6_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share1 key [223:192] + * @{ + */ +#define ATLC_AESKEYSL_S1_6__VL__SHIFT 0 +#define ATLC_AESKEYSL_S1_6__VL__WIDTH 32 +#define ATLC_AESKEYSL_S1_6__VL__MASK 0xffffffffU +#define ATLC_AESKEYSL_S1_6__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S1_6__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S1_6__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEYSL_S1_6__VL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define ATLC_AESKEYSL_S1_6__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEYSL_S1_6__TYPE uint32_t +#define ATLC_AESKEYSL_S1_6__READ 0xffffffffU +#define ATLC_AESKEYSL_S1_6__WRITE 0xffffffffU +#define ATLC_AESKEYSL_S1_6__PRESERVED 0x00000000U +#define ATLC_AESKEYSL_S1_6__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEYSL_S1_6_MACRO__ */ + +/** @} end of aeskeysl_s1_6 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_aeskeysl_s1_7 */ +/** + * @defgroup at_lc_regs_core_aeskeysl_s1_7 aeskeysl_s1_7 + * @brief Contains register fields associated with aeskeysl_s1_7. definitions. + * @{ + */ +#ifndef __ATLC_AESKEYSL_S1_7_MACRO__ +#define __ATLC_AESKEYSL_S1_7_MACRO__ + +/* macros for field vl */ +/** + * @defgroup at_lc_regs_core_vl_field vl_field + * @brief macros for field vl + * @details AES share1 key [255:224] + * @{ + */ +#define ATLC_AESKEYSL_S1_7__VL__SHIFT 0 +#define ATLC_AESKEYSL_S1_7__VL__WIDTH 32 +#define ATLC_AESKEYSL_S1_7__VL__MASK 0xffffffffU +#define ATLC_AESKEYSL_S1_7__VL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S1_7__VL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_AESKEYSL_S1_7__VL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define ATLC_AESKEYSL_S1_7__VL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define ATLC_AESKEYSL_S1_7__VL__RESET_VALUE 0x00000000U +/** @} */ +#define ATLC_AESKEYSL_S1_7__TYPE uint32_t +#define ATLC_AESKEYSL_S1_7__READ 0xffffffffU +#define ATLC_AESKEYSL_S1_7__WRITE 0xffffffffU +#define ATLC_AESKEYSL_S1_7__PRESERVED 0x00000000U +#define ATLC_AESKEYSL_S1_7__RESET_VALUE 0x00000000U + +#endif /* __ATLC_AESKEYSL_S1_7_MACRO__ */ + +/** @} end of aeskeysl_s1_7 */ + +/* macros for BlueprintGlobalNameSpace::ATLC_id */ +/** + * @defgroup at_lc_regs_core_id id + * @brief Contains register fields associated with id. definitions. + * @{ + */ +#ifndef __ATLC_ID_MACRO__ +#define __ATLC_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup at_lc_regs_core_id_field id_field + * @brief macros for field id + * @details 'ATLC' in ASCII + * @{ + */ +#define ATLC_ID__ID__SHIFT 0 +#define ATLC_ID__ID__WIDTH 32 +#define ATLC_ID__ID__MASK 0xffffffffU +#define ATLC_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define ATLC_ID__ID__RESET_VALUE 0x41544c43U +/** @} */ +#define ATLC_ID__TYPE uint32_t +#define ATLC_ID__READ 0xffffffffU +#define ATLC_ID__PRESERVED 0x00000000U +#define ATLC_ID__RESET_VALUE 0x41544c43U + +#endif /* __ATLC_ID_MACRO__ */ + +/** @} end of id */ + +/** @} end of AT_LC_REGS_CORE */ +#endif /* __REG_AT_LC_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/at_pinmux.h b/ATM33xx-5/include/reg/at_pinmux.h new file mode 100644 index 0000000..1fd5472 --- /dev/null +++ b/ATM33xx-5/include/reg/at_pinmux.h @@ -0,0 +1,1676 @@ +/** + ***************************************************************************** + * + * @file at_pinmux.h + * + * @brief Pinmux definitions + * + * Copyright (C) Atmosic 2022-2024 + * + ***************************************************************************** + */ + +#pragma once + +#define PINMUX_SWDCLK 1 +#define PINMUX_SWDIO 2 +#define PINMUX_QSPI_CLK 3 +#define PINMUX_QSPI_CSN 4 +#define PINMUX_QSPI_D0 5 +#define PINMUX_QSPI_D1 6 +#define PINMUX_QSPI_D2 7 +#define PINMUX_QSPI_D3 8 +#define PINMUX_SPI0_CSN 9 +#define PINMUX_SPI0_CS 9 +#define PINMUX_SPI0_SCLK 10 +#define PINMUX_SPI0_CLK 10 +#define PINMUX_SPI0_MOSI 11 +#define PINMUX_SPI0_MISO 12 +#define PINMUX_SPI1_CSN 13 +#define PINMUX_SPI1_CS 13 +#define PINMUX_SPI1_SCLK 14 +#define PINMUX_SPI1_CLK 14 +#define PINMUX_SPI1_MOSI 15 +#define PINMUX_SPI1_MISO 16 +#define PINMUX_I2C0_SCK 17 +#define PINMUX_I2C0_SCL 17 +#define PINMUX_I2C0_SDA 18 +#define PINMUX_I2C1_SCK 19 +#define PINMUX_I2C1_SCL 19 +#define PINMUX_I2C1_SDA 20 +#define PINMUX_PDM0_CLK 21 +#define PINMUX_PDM0_IN 22 +#define PINMUX_PDM1_CLK 23 +#define PINMUX_PDM1_IN 24 +#define PINMUX_I2S0_SCK_OUT 25 +#define PINMUX_I2S0_WS_OUT 26 +#define PINMUX_I2S0_SD_OUT 27 +#define PINMUX_I2S0_SCK_IN 28 +#define PINMUX_I2S0_WS_IN 29 +#define PINMUX_I2S0_SD_IN 30 +#define PINMUX_UART0_RX 31 +#define PINMUX_UART0_TX 32 +#define PINMUX_UART0_CTS 33 +#define PINMUX_UART0_RTS 34 +#define PINMUX_UART1_RX 35 +#define PINMUX_UART1_TX 36 +#define PINMUX_UART1_CTS 37 +#define PINMUX_UART1_RTS 38 +#define PINMUX_PWM0 39 +#define PINMUX_PWM1 40 +#define PINMUX_PWM2 41 +#define PINMUX_PWM3 42 +#define PINMUX_PWM4 43 +#define PINMUX_PWM5 44 +#define PINMUX_PWM6 45 +#define PINMUX_PWM7 46 +#define PINMUX_KSI19 47 +#define PINMUX_KSI18 48 +#define PINMUX_KSI17 49 +#define PINMUX_KSI16 50 +#define PINMUX_KSI15 51 +#define PINMUX_KSI14 52 +#define PINMUX_KSI13 53 +#define PINMUX_KSI12 54 +#define PINMUX_KSI11 55 +#define PINMUX_KSI10 56 +#define PINMUX_KSI9 57 +#define PINMUX_KSI8 58 +#define PINMUX_KSI7 59 +#define PINMUX_KSI6 60 +#define PINMUX_KSI5 61 +#define PINMUX_KSI4 62 +#define PINMUX_KSI3 63 +#define PINMUX_KSI2 64 +#define PINMUX_KSI1 65 +#define PINMUX_KSI0 66 +#define PINMUX_KSO19 67 +#define PINMUX_KSO18 68 +#define PINMUX_KSO17 69 +#define PINMUX_KSO16 70 +#define PINMUX_KSO15 71 +#define PINMUX_KSO14 72 +#define PINMUX_KSO13 73 +#define PINMUX_KSO12 74 +#define PINMUX_KSO11 75 +#define PINMUX_KSO10 76 +#define PINMUX_KSO9 77 +#define PINMUX_KSO8 78 +#define PINMUX_KSO7 79 +#define PINMUX_KSO6 80 +#define PINMUX_KSO5 81 +#define PINMUX_KSO4 82 +#define PINMUX_KSO3 83 +#define PINMUX_KSO2 84 +#define PINMUX_KSO1 85 +#define PINMUX_KSO0 86 +#define PINMUX_SHUB_SPI0_CSN 87 +#define PINMUX_SHUB_SPI0_CS 87 +#define PINMUX_SHUB_SPI0_SCLK 88 +#define PINMUX_SHUB_SPI0_CLK 88 +#define PINMUX_SHUB_SPI0_MOSI 89 +#define PINMUX_SHUB_SPI0_MISO 90 +#define PINMUX_SHUB_SPI1_CSN 91 +#define PINMUX_SHUB_SPI1_CS 91 +#define PINMUX_SHUB_SPI1_SCLK 92 +#define PINMUX_SHUB_SPI1_CLK 92 +#define PINMUX_SHUB_SPI1_MOSI 93 +#define PINMUX_SHUB_SPI1_MISO 94 +#define PINMUX_SHUB_I2C0_SCK 95 +#define PINMUX_SHUB_I2C0_SCL 95 +#define PINMUX_SHUB_I2C0_SDA 96 +#define PINMUX_SHUB_I2C1_SCK 97 +#define PINMUX_SHUB_I2C1_SCL 97 +#define PINMUX_SHUB_I2C1_SDA 98 +#define PINMUX_QDEC0_A 99 +#define PINMUX_QDEC0_B 100 +#define PINMUX_QDEC1_A 101 +#define PINMUX_QDEC1_B 102 +#define PINMUX_QDEC2_A 103 +#define PINMUX_QDEC2_B 104 +#define PINMUX_XLNA_XPA0 105 +#define PINMUX_XLNA_XPA1 106 +#define PINMUX_XLNA_XPA2 107 +#define PINMUX_XLNA_XPA3 108 +#define PINMUX_XLNA_XPA4 109 +#define PINMUX_MDM_IN4 110 +#define PINMUX_MDM_IN3 111 +#define PINMUX_MDM_IN2 112 +#define PINMUX_MDM_IN1 113 +#define PINMUX_MDM_IN0 114 +#define PINMUX_MDM_OUT7 115 +#define PINMUX_MDM_OUT6 116 +#define PINMUX_MDM_OUT5 117 +#define PINMUX_MDM_OUT4 118 +#define PINMUX_MDM_OUT3 119 +#define PINMUX_MDM_OUT2 120 +#define PINMUX_MDM_OUT1 121 +#define PINMUX_MDM_OUT0 122 +#define PINMUX_LC_RX_EN 123 +#define PINMUX_LC_TX_EN 124 +#define PINMUX_ANT_OUT7 125 +#define PINMUX_ANT_OUT6 126 +#define PINMUX_ANT_OUT5 127 +#define PINMUX_ANT_OUT4 128 +#define PINMUX_ANT_OUT3 129 +#define PINMUX_ANT_OUT2 130 +#define PINMUX_ANT_OUT1 131 +#define PINMUX_ANT_OUT0 132 +#define PINMUX_BLE_SYNC 133 +#define PINMUX_BLE_IN_PROCESS 134 +#define PINMUX_BLE_TX 135 +#define PINMUX_BLE_RX 136 +#define PINMUX_BLE_PTI0 137 +#define PINMUX_BLE_PTI1 138 +#define PINMUX_BLE_PTI2 139 +#define PINMUX_BLE_PTI3 140 +#define PINMUX_WLAN_TX 141 +#define PINMUX_WLAN_RX 142 +#define PINMUX_TRACECLKOUT 143 +#define PINMUX_TRACEDATA_IQ0 144 +#define PINMUX_TRACEDATA_IQ1 145 +#define PINMUX_TRACEDATA_IQ2 146 +#define PINMUX_TRACEDATA_IQ3 147 +#define PINMUX_TRACEDATA_IQ4 148 +#define PINMUX_TRACEDATA_IQ5 149 +#define PINMUX_TRACEDATA_IQ6 150 +#define PINMUX_TRACEDATA_IQ7 151 +#define PINMUX_TRACEDATA_IQ8 152 +#define PINMUX_TRACEDATA_IQ9 153 +#define PINMUX_TRACEDATA_IQ10 154 +#define PINMUX_TRACEDATA_IQ11 155 +#define PINMUX_TRACEDATA_IQ12 156 +#define PINMUX_TRACEDATA_IQ13 157 +#define PINMUX_TRACEDATA_IQ14 158 +#define PINMUX_TRACEDATA_IQ15 159 +#define PINMUX_DBG 160 +#define PINMUX_DTOPBYP 161 +#define PINMUX_GPIO 0 +/* +pin count = 31 +package = 7x7 +bond outs = 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + P0 + P1 + P2 + P3 + P4 + P5 + P6 + P7 + P8 + P9 + P10 + P11 + P12 + P13 + P14 + P15 + P16 + P17 + P18 + P19 + P20 + P21 + P22 + P23 + P24 + P25 + P26 + P27 + P28 + P29 + P30 +swdclk : x.............................. +swdio : .x............................. +qspi_clk : x.....x.....x.....x...........x +qspi_csn : .x.....x.....x.....x.....x..... +qspi_d0 : ..x.....x.....x.....x.....x.... +qspi_d1 : ...x...........x.....x.....x... +qspi_d2 : ....x...........x.....x.....x.. +qspi_d3 : .....x...........x.....x.....x. +spi0_csn : x.......x.......x...x.........x +spi0_sclk : .x...............x.......x.x... +spi0_mosi : ..x...............x.......x.x.. +spi0_miso : ...x...............x.........x. +spi1_csn : ....x.......x.......x.......... +spi1_sclk : .....x.......x.......x......... +spi1_mosi : ......x.......x.......x........ +spi1_miso : .......x.......x.......x....... +i2c0_sck : x...x...x...x...x...x.....x...x +i2c0_sda : .x...x.......x...x...x...x.x.x. +i2c1_sck : ..x...x.......x...x...x...x.x.. +i2c1_sda : ...x...x.......x...x...x.....x. +pdm0_clk : x...x...x...x...x...x.........x +pdm0_in : .x...x.......x...x...x...x.x... +pdm1_clk : ..x...x.......x...x...x...x.x.. +pdm1_in : ...x...x.......x...x...x.....x. +i2s0_sck_out : x..x..x.....x..x..x..x.....x..x +i2s0_ws_out : .x..x..x.....x..x..x..x..x..x.. +i2s0_sd_out : ..x..x..x.....x..x..x..x..x..x. +i2s0_sck_in : x..x..x.....x..x..x..x.....x..x +i2s0_ws_in : .x..x..x.....x..x..x..x..x..x.. +i2s0_sd_in : ..x..x..x.....x..x..x..x..x..x. +uart0_rx : x.x.x.x.x...x.x.x.x.x.x...x.x.x +uart0_tx : .x.x.x.x.....x.x.x.x.x.x.x.x.x. +uart0_cts : x...x...x...x...x...x........xx +uart0_rts : .x...x.......x...x...x...x.x... +uart1_rx : .x...x.......x...x...x...x.x... +uart1_tx : ..x...x.......x...x...x...xxx.. +uart1_cts : ...x...x.......x...x...x.....x. +uart1_rts : x...x...x...x...x...x.........x +pwm0 : x....x..x...x...x.............x +pwm1 : .x...............x.......x.x... +pwm2 : ..x...............x.......x.x.. +pwm3 : ...x...............x.........x. +pwm4 : ....x.......x.......x.......... +pwm5 : .....x.......x.......x......... +pwm6 : ......x.......x.......x........ +pwm7 : .......x.......x.......x....... +ksi19 : ..........................x.... +ksi18 : ...........................x... +ksi17 : ...................x........... +ksi16 : ..................x............ +ksi15 : .................x............. +ksi14 : ................x.............. +ksi13 : ...............x............... +ksi12 : ............x............x..... +ksi11 : ...........x.................xx +ksi10 : ..........x............x....x.. +ksi9 : .........x............x....x... +ksi8 : ........x............x......... +ksi7 : .......x............x.......... +ksi6 : ......x............x........... +ksi5 : .....x............x............ +ksi4 : ....x............x............. +ksi3 : ...x............x.............. +ksi2 : ..x............x............... +ksi1 : .x............x................ +ksi0 : x............x............x.... +kso19 : ..........................x.... +kso18 : ...........................x... +kso17 : ..............................x +kso16 : .............................x. +kso15 : ............................x.. +kso14 : ........................x...... +kso13 : .......................x....... +kso12 : ............x............x..... +kso11 : ...........x.................xx +kso10 : ..........x............x....x.. +kso9 : .........x............x....x... +kso8 : ........x............x......... +kso7 : .......x............x.......... +kso6 : ......x............x........... +kso5 : .....x............x............ +kso4 : ....x............x............. +kso3 : ...x............x.............. +kso2 : ..x............x............... +kso1 : .x............x................ +kso0 : x............x............x.... +shub_spi0_csn : x.......x.......x...x.........x +shub_spi0_sclk : .x...............x.......x.x... +shub_spi0_mosi : ..x...............x.......x.x.. +shub_spi0_miso : ...x...............x.........x. +shub_spi1_csn : ....x.......x.......x.......... +shub_spi1_sclk : .....x.......x.......x......... +shub_spi1_mosi : ......x.......x.......x........ +shub_spi1_miso : .......x.......x.......x....... +shub_i2c0_sck : x...x...x...x...x...x.........x +shub_i2c0_sda : .x...x.......x...x...x...x.x.x. +shub_i2c1_sck : ..x...............x............ +shub_i2c1_sda : ...x...............x........... +qdec0_a : x.....x.....x.....x...........x +qdec0_b : .x.....x.....x.....x.....x..... +qdec1_a : ..x.....x.....x.....x.....x.... +qdec1_b : ...x...........x.....x.....x... +qdec2_a : ....x...........x.....x.....x.. +qdec2_b : .....x...........x.....x.....x. +xlna_xpa0 : x....x.........x....x....x..x.. +xlna_xpa1 : .x....x.........x....x....x..x. +xlna_xpa2 : ..x....x....x....x....x........ +xlna_xpa3 : ...x....x....x....x....x....... +xlna_xpa4 : ....x.........x....x.......x..x +mdm_in4 : ...........................x... +mdm_in3 : ........x...................... +mdm_in2 : .......x....................... +mdm_in1 : ......x........................ +mdm_in0 : .....x......................... +mdm_out7 : ..........................x.... +mdm_out6 : .........................x..... +mdm_out5 : ..............................x +mdm_out4 : .......................x....... +mdm_out3 : ......................x........ +mdm_out2 : .....................x......... +mdm_out1 : ....................x.......... +mdm_out0 : ...................x........... +lc_rx_en : x.x.x.x.x...x.x.x.x.x.x...x.x.x +lc_tx_en : .x.x.x.x.....x.x.x.x.x.x.x.x.x. +ant_out7 : .......x.......x.......x....... +ant_out6 : ......x.......x.......x........ +ant_out5 : .....x.......x.......x......... +ant_out4 : ....x.......x.......x.......... +ant_out3 : ...x...............x.........x. +ant_out2 : ..x...............x.......x.x.. +ant_out1 : .x...............x.......x.x... +ant_out0 : x.......x.......x.............x +ble_sync : x...................x.......x.. +ble_in_process : .x...................x.......x. +ble_tx : ..x.........x.........x........ +ble_rx : ...x.........x.........x....... +ble_pti0 : ....x.........x...............x +ble_pti1 : .....x.........x.........x..... +ble_pti2 : ......x.........x.........x.... +ble_pti3 : .......x.........x............. +wlan_tx : ........x.........x............ +wlan_rx : ...................x.......x... +traceclkout : x.......x.......x.............x +tracedata_iq0 : .x...............x.......x.x... +tracedata_iq1 : ..x...............x.......x.x.. +tracedata_iq2 : ...x...............x.........x. +tracedata_iq3 : ....x.......x.......x.......... +tracedata_iq4 : .....x.......x.......x......... +tracedata_iq5 : ......x.......x.......x........ +tracedata_iq6 : .......x.......x.......x....... +tracedata_iq7 : x.......x.......x.............x +tracedata_iq8 : .x...............x.......x.x... +tracedata_iq9 : ..x...............x.......x.x.. +tracedata_iq10 : ...x...............x.........x. +tracedata_iq11 : ....x.......x.......x.......... +tracedata_iq12 : .....x.......x.......x......... +tracedata_iq13 : ......x.......x.......x........ +tracedata_iq14 : .......x.......x.......x....... +tracedata_iq15 : x.......x.......x.............x +dbg : xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +dtopbyp : xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +gpio : xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +*/ +#define ANT_OUT0__MASK 0x40010101 +#define ANT_OUT1__MASK 0x0a020002 +#define ANT_OUT2__MASK 0x14040004 +#define ANT_OUT3__MASK 0x20080008 +#define ANT_OUT4__MASK 0x00101010 +#define ANT_OUT5__MASK 0x00202020 +#define ANT_OUT6__MASK 0x00404040 +#define ANT_OUT7__MASK 0x00808080 +#define BLE_IN_PROCESS__MASK 0x20200002 +#define BLE_PTI0__MASK 0x40004010 +#define BLE_PTI1__MASK 0x02008020 +#define BLE_PTI2__MASK 0x04010040 +#define BLE_PTI3__MASK 0x00020080 +#define BLE_RX__MASK 0x00802008 +#define BLE_SYNC__MASK 0x10100001 +#define BLE_TX__MASK 0x00401004 +#define DBG__MASK 0x7fffffff +#define DTOPBYP__MASK 0x7fffffff +#define GPIO__MASK 0x7fffffff +#define I2C0_SCK__MASK 0x44111111 +#define I2C0_SCL__MASK 0x44111111 +#define I2C0_SDA__MASK 0x2a222022 +#define I2C1_SCK__MASK 0x14444044 +#define I2C1_SCL__MASK 0x14444044 +#define I2C1_SDA__MASK 0x20888088 +#define I2S0_SCK_IN__MASK 0x48249049 +#define I2S0_SCK_OUT__MASK 0x48249049 +#define I2S0_SD_IN__MASK 0x24924124 +#define I2S0_SD_OUT__MASK 0x24924124 +#define I2S0_WS_IN__MASK 0x12492092 +#define I2S0_WS_OUT__MASK 0x12492092 +#define KSI0__MASK 0x04002001 +#define KSI1__MASK 0x00004002 +#define KSI10__MASK 0x10800400 +#define KSI11__MASK 0x60000800 +#define KSI12__MASK 0x02001000 +#define KSI13__MASK 0x00008000 +#define KSI14__MASK 0x00010000 +#define KSI15__MASK 0x00020000 +#define KSI16__MASK 0x00040000 +#define KSI17__MASK 0x00080000 +#define KSI18__MASK 0x08000000 +#define KSI19__MASK 0x04000000 +#define KSI2__MASK 0x00008004 +#define KSI3__MASK 0x00010008 +#define KSI4__MASK 0x00020010 +#define KSI5__MASK 0x00040020 +#define KSI6__MASK 0x00080040 +#define KSI7__MASK 0x00100080 +#define KSI8__MASK 0x00200100 +#define KSI9__MASK 0x08400200 +#define KSO0__MASK 0x04002001 +#define KSO1__MASK 0x00004002 +#define KSO10__MASK 0x10800400 +#define KSO11__MASK 0x60000800 +#define KSO12__MASK 0x02001000 +#define KSO13__MASK 0x00800000 +#define KSO14__MASK 0x01000000 +#define KSO15__MASK 0x10000000 +#define KSO16__MASK 0x20000000 +#define KSO17__MASK 0x40000000 +#define KSO18__MASK 0x08000000 +#define KSO19__MASK 0x04000000 +#define KSO2__MASK 0x00008004 +#define KSO3__MASK 0x00010008 +#define KSO4__MASK 0x00020010 +#define KSO5__MASK 0x00040020 +#define KSO6__MASK 0x00080040 +#define KSO7__MASK 0x00100080 +#define KSO8__MASK 0x00200100 +#define KSO9__MASK 0x08400200 +#define LC_RX_EN__MASK 0x54555155 +#define LC_TX_EN__MASK 0x2aaaa0aa +#define MDM_IN0__MASK 0x00000020 +#define MDM_IN1__MASK 0x00000040 +#define MDM_IN2__MASK 0x00000080 +#define MDM_IN3__MASK 0x00000100 +#define MDM_IN4__MASK 0x08000000 +#define MDM_OUT0__MASK 0x00080000 +#define MDM_OUT1__MASK 0x00100000 +#define MDM_OUT2__MASK 0x00200000 +#define MDM_OUT3__MASK 0x00400000 +#define MDM_OUT4__MASK 0x00800000 +#define MDM_OUT5__MASK 0x40000000 +#define MDM_OUT6__MASK 0x02000000 +#define MDM_OUT7__MASK 0x04000000 +#define PDM0_CLK__MASK 0x40111111 +#define PDM0_IN__MASK 0x0a222022 +#define PDM1_CLK__MASK 0x14444044 +#define PDM1_IN__MASK 0x20888088 +#define PWM0__MASK 0x40011121 +#define PWM1__MASK 0x0a020002 +#define PWM2__MASK 0x14040004 +#define PWM3__MASK 0x20080008 +#define PWM4__MASK 0x00101010 +#define PWM5__MASK 0x00202020 +#define PWM6__MASK 0x00404040 +#define PWM7__MASK 0x00808080 +#define QDEC0_A__MASK 0x40041041 +#define QDEC0_B__MASK 0x02082082 +#define QDEC1_A__MASK 0x04104104 +#define QDEC1_B__MASK 0x08208008 +#define QDEC2_A__MASK 0x10410010 +#define QDEC2_B__MASK 0x20820020 +#define QSPI_CLK__MASK 0x40041041 +#define QSPI_CSN__MASK 0x02082082 +#define QSPI_D0__MASK 0x04104104 +#define QSPI_D1__MASK 0x08208008 +#define QSPI_D2__MASK 0x10410010 +#define QSPI_D3__MASK 0x20820020 +#define SHUB_I2C0_SCK__MASK 0x40111111 +#define SHUB_I2C0_SCL__MASK 0x40111111 +#define SHUB_I2C0_SDA__MASK 0x2a222022 +#define SHUB_I2C1_SCK__MASK 0x00040004 +#define SHUB_I2C1_SCL__MASK 0x00040004 +#define SHUB_I2C1_SDA__MASK 0x00080008 +#define SHUB_SPI0_CSN__MASK 0x40110101 +#define SHUB_SPI0_CS__MASK 0x40110101 +#define SHUB_SPI0_MISO__MASK 0x20080008 +#define SHUB_SPI0_MOSI__MASK 0x14040004 +#define SHUB_SPI0_SCLK__MASK 0x0a020002 +#define SHUB_SPI0_CLK__MASK 0x0a020002 +#define SHUB_SPI1_CSN__MASK 0x00101010 +#define SHUB_SPI1_CS__MASK 0x00101010 +#define SHUB_SPI1_MISO__MASK 0x00808080 +#define SHUB_SPI1_MOSI__MASK 0x00404040 +#define SHUB_SPI1_SCLK__MASK 0x00202020 +#define SHUB_SPI1_CLK__MASK 0x00202020 +#define SPI0_CSN__MASK 0x40110101 +#define SPI0_CS__MASK 0x40110101 +#define SPI0_MISO__MASK 0x20080008 +#define SPI0_MOSI__MASK 0x14040004 +#define SPI0_SCLK__MASK 0x0a020002 +#define SPI0_CLK__MASK 0x0a020002 +#define SPI1_CSN__MASK 0x00101010 +#define SPI1_CS__MASK 0x00101010 +#define SPI1_MISO__MASK 0x00808080 +#define SPI1_MOSI__MASK 0x00404040 +#define SPI1_SCLK__MASK 0x00202020 +#define SPI1_CLK__MASK 0x00202020 +#define SWDCLK__MASK 0x00000001 +#define SWDIO__MASK 0x00000002 +#define TRACECLKOUT__MASK 0x40010101 +#define TRACEDATA_IQ0__MASK 0x0a020002 +#define TRACEDATA_IQ1__MASK 0x14040004 +#define TRACEDATA_IQ10__MASK 0x20080008 +#define TRACEDATA_IQ11__MASK 0x00101010 +#define TRACEDATA_IQ12__MASK 0x00202020 +#define TRACEDATA_IQ13__MASK 0x00404040 +#define TRACEDATA_IQ14__MASK 0x00808080 +#define TRACEDATA_IQ15__MASK 0x40010101 +#define TRACEDATA_IQ2__MASK 0x20080008 +#define TRACEDATA_IQ3__MASK 0x00101010 +#define TRACEDATA_IQ4__MASK 0x00202020 +#define TRACEDATA_IQ5__MASK 0x00404040 +#define TRACEDATA_IQ6__MASK 0x00808080 +#define TRACEDATA_IQ7__MASK 0x40010101 +#define TRACEDATA_IQ8__MASK 0x0a020002 +#define TRACEDATA_IQ9__MASK 0x14040004 +#define UART0_CTS__MASK 0x60111111 +#define UART0_RTS__MASK 0x0a222022 +#define UART0_RX__MASK 0x54555155 +#define UART0_TX__MASK 0x2aaaa0aa +#define UART1_CTS__MASK 0x20888088 +#define UART1_RTS__MASK 0x40111111 +#define UART1_RX__MASK 0x0a222022 +#define UART1_TX__MASK 0x1c444044 +#define WLAN_RX__MASK 0x08080000 +#define WLAN_TX__MASK 0x00040100 +#define XLNA_XPA0__MASK 0x12108021 +#define XLNA_XPA1__MASK 0x24210042 +#define XLNA_XPA2__MASK 0x00421084 +#define XLNA_XPA3__MASK 0x00842108 +#define XLNA_XPA4__MASK 0x48084010 +/* +pin count = 31 +package = 6x6 +bond outs = 0 1 2 3 4 5 6 7 8 12 13 14 15 16 17 18 19 20 21 22 23 25 26 27 28 29 30 + P0 + P1 + P2 + P3 + P4 + P5 + P6 + P7 + P8 + P9 + P10 + P11 + P12 + P13 + P14 + P15 + P16 + P17 + P18 + P19 + P20 + P21 + P22 + P23 + P24 + P25 + P26 + P27 + P28 + P29 + P30 +swdclk : x.............................. +swdio : .x............................. +qspi_clk : x.....x.....x.....x...........x +qspi_csn : .x.....x.....x.....x.....x..... +qspi_d0 : ..x.....x.....x.....x.....x.... +qspi_d1 : ...x...........x.....x.....x... +qspi_d2 : ....x...........x.....x.....x.. +qspi_d3 : .....x...........x.....x.....x. +spi0_csn : x.......x.......x...x.........x +spi0_sclk : .x...............x.......x.x... +spi0_mosi : ..x...............x.......x.x.. +spi0_miso : ...x...............x.........x. +spi1_csn : ....x.......x.......x.......... +spi1_sclk : .....x.......x.......x......... +spi1_mosi : ......x.......x.......x........ +spi1_miso : .......x.......x.......x....... +i2c0_sck : x...x...x...x...x...x.....x...x +i2c0_sda : .x...x.......x...x...x...x.x.x. +i2c1_sck : ..x...x.......x...x...x...x.x.. +i2c1_sda : ...x...x.......x...x...x.....x. +pdm0_clk : x...x...x...x...x...x.........x +pdm0_in : .x...x.......x...x...x...x.x... +pdm1_clk : ..x...x.......x...x...x...x.x.. +pdm1_in : ...x...x.......x...x...x.....x. +i2s0_sck_out : x..x..x.....x..x..x..x.....x..x +i2s0_ws_out : .x..x..x.....x..x..x..x..x..x.. +i2s0_sd_out : ..x..x..x.....x..x..x..x..x..x. +i2s0_sck_in : x..x..x.....x..x..x..x.....x..x +i2s0_ws_in : .x..x..x.....x..x..x..x..x..x.. +i2s0_sd_in : ..x..x..x.....x..x..x..x..x..x. +uart0_rx : x.x.x.x.x...x.x.x.x.x.x...x.x.x +uart0_tx : .x.x.x.x.....x.x.x.x.x.x.x.x.x. +uart0_cts : x...x...x...x...x...x........xx +uart0_rts : .x...x.......x...x...x...x.x... +uart1_rx : .x...x.......x...x...x...x.x... +uart1_tx : ..x...x.......x...x...x...xxx.. +uart1_cts : ...x...x.......x...x...x.....x. +uart1_rts : x...x...x...x...x...x.........x +pwm0 : x....x..x...x...x.............x +pwm1 : .x...............x.......x.x... +pwm2 : ..x...............x.......x.x.. +pwm3 : ...x...............x.........x. +pwm4 : ....x.......x.......x.......... +pwm5 : .....x.......x.......x......... +pwm6 : ......x.......x.......x........ +pwm7 : .......x.......x.......x....... +ksi19 : ..........................x.... +ksi18 : ...........................x... +ksi17 : ...................x........... +ksi16 : ..................x............ +ksi15 : .................x............. +ksi14 : ................x.............. +ksi13 : ...............x............... +ksi12 : ............x............x..... +ksi11 : ...........!.................xx +ksi10 : ..........!............x....x.. +ksi9 : .........!............x....x... +ksi8 : ........x............x......... +ksi7 : .......x............x.......... +ksi6 : ......x............x........... +ksi5 : .....x............x............ +ksi4 : ....x............x............. +ksi3 : ...x............x.............. +ksi2 : ..x............x............... +ksi1 : .x............x................ +ksi0 : x............x............x.... +kso19 : ..........................x.... +kso18 : ...........................x... +kso17 : ..............................x +kso16 : .............................x. +kso15 : ............................x.. +kso14 : ........................!...... +kso13 : .......................x....... +kso12 : ............x............x..... +kso11 : ...........!.................xx +kso10 : ..........!............x....x.. +kso9 : .........!............x....x... +kso8 : ........x............x......... +kso7 : .......x............x.......... +kso6 : ......x............x........... +kso5 : .....x............x............ +kso4 : ....x............x............. +kso3 : ...x............x.............. +kso2 : ..x............x............... +kso1 : .x............x................ +kso0 : x............x............x.... +shub_spi0_csn : x.......x.......x...x.........x +shub_spi0_sclk : .x...............x.......x.x... +shub_spi0_mosi : ..x...............x.......x.x.. +shub_spi0_miso : ...x...............x.........x. +shub_spi1_csn : ....x.......x.......x.......... +shub_spi1_sclk : .....x.......x.......x......... +shub_spi1_mosi : ......x.......x.......x........ +shub_spi1_miso : .......x.......x.......x....... +shub_i2c0_sck : x...x...x...x...x...x.........x +shub_i2c0_sda : .x...x.......x...x...x...x.x.x. +shub_i2c1_sck : ..x...............x............ +shub_i2c1_sda : ...x...............x........... +qdec0_a : x.....x.....x.....x...........x +qdec0_b : .x.....x.....x.....x.....x..... +qdec1_a : ..x.....x.....x.....x.....x.... +qdec1_b : ...x...........x.....x.....x... +qdec2_a : ....x...........x.....x.....x.. +qdec2_b : .....x...........x.....x.....x. +xlna_xpa0 : x....x.........x....x....x..x.. +xlna_xpa1 : .x....x.........x....x....x..x. +xlna_xpa2 : ..x....x....x....x....x........ +xlna_xpa3 : ...x....x....x....x....x....... +xlna_xpa4 : ....x.........x....x.......x..x +mdm_in4 : ...........................x... +mdm_in3 : ........x...................... +mdm_in2 : .......x....................... +mdm_in1 : ......x........................ +mdm_in0 : .....x......................... +mdm_out7 : ..........................x.... +mdm_out6 : .........................x..... +mdm_out5 : ..............................x +mdm_out4 : .......................x....... +mdm_out3 : ......................x........ +mdm_out2 : .....................x......... +mdm_out1 : ....................x.......... +mdm_out0 : ...................x........... +lc_rx_en : x.x.x.x.x...x.x.x.x.x.x...x.x.x +lc_tx_en : .x.x.x.x.....x.x.x.x.x.x.x.x.x. +ant_out7 : .......x.......x.......x....... +ant_out6 : ......x.......x.......x........ +ant_out5 : .....x.......x.......x......... +ant_out4 : ....x.......x.......x.......... +ant_out3 : ...x...............x.........x. +ant_out2 : ..x...............x.......x.x.. +ant_out1 : .x...............x.......x.x... +ant_out0 : x.......x.......x.............x +ble_sync : x...................x.......x.. +ble_in_process : .x...................x.......x. +ble_tx : ..x.........x.........x........ +ble_rx : ...x.........x.........x....... +ble_pti0 : ....x.........x...............x +ble_pti1 : .....x.........x.........x..... +ble_pti2 : ......x.........x.........x.... +ble_pti3 : .......x.........x............. +wlan_tx : ........x.........x............ +wlan_rx : ...................x.......x... +traceclkout : x.......x.......x.............x +tracedata_iq0 : .x...............x.......x.x... +tracedata_iq1 : ..x...............x.......x.x.. +tracedata_iq2 : ...x...............x.........x. +tracedata_iq3 : ....x.......x.......x.......... +tracedata_iq4 : .....x.......x.......x......... +tracedata_iq5 : ......x.......x.......x........ +tracedata_iq6 : .......x.......x.......x....... +tracedata_iq7 : x.......x.......x.............x +tracedata_iq8 : .x...............x.......x.x... +tracedata_iq9 : ..x...............x.......x.x.. +tracedata_iq10 : ...x...............x.........x. +tracedata_iq11 : ....x.......x.......x.......... +tracedata_iq12 : .....x.......x.......x......... +tracedata_iq13 : ......x.......x.......x........ +tracedata_iq14 : .......x.......x.......x....... +tracedata_iq15 : x.......x.......x.............x +dbg : xxxxxxxxx!!!xxxxxxxxxxxx!xxxxxx +dtopbyp : xxxxxxxxx!!!xxxxxxxxxxxx!xxxxxx +gpio : xxxxxxxxx!!!xxxxxxxxxxxx!xxxxxx +*/ +#define ANT_OUT0__MASK_6X6 0x40010101 +#define ANT_OUT1__MASK_6X6 0x0a020002 +#define ANT_OUT2__MASK_6X6 0x14040004 +#define ANT_OUT3__MASK_6X6 0x20080008 +#define ANT_OUT4__MASK_6X6 0x00101010 +#define ANT_OUT5__MASK_6X6 0x00202020 +#define ANT_OUT6__MASK_6X6 0x00404040 +#define ANT_OUT7__MASK_6X6 0x00808080 +#define BLE_IN_PROCESS__MASK_6X6 0x20200002 +#define BLE_PTI0__MASK_6X6 0x40004010 +#define BLE_PTI1__MASK_6X6 0x02008020 +#define BLE_PTI2__MASK_6X6 0x04010040 +#define BLE_PTI3__MASK_6X6 0x00020080 +#define BLE_RX__MASK_6X6 0x00802008 +#define BLE_SYNC__MASK_6X6 0x10100001 +#define BLE_TX__MASK_6X6 0x00401004 +#define DBG__MASK_6X6 0x7fffffff +#define DTOPBYP__MASK_6X6 0x7fffffff +#define GPIO__MASK_6X6 0x7fffffff +#define I2C0_SCK__MASK_6X6 0x44111111 +#define I2C0_SCL__MASK_6X6 0x44111111 +#define I2C0_SDA__MASK_6X6 0x2a222022 +#define I2C1_SCK__MASK_6X6 0x14444044 +#define I2C1_SCL__MASK_6X6 0x14444044 +#define I2C1_SDA__MASK_6X6 0x20888088 +#define I2S0_SCK_IN__MASK_6X6 0x48249049 +#define I2S0_SCK_OUT__MASK_6X6 0x48249049 +#define I2S0_SD_IN__MASK_6X6 0x24924124 +#define I2S0_SD_OUT__MASK_6X6 0x24924124 +#define I2S0_WS_IN__MASK_6X6 0x12492092 +#define I2S0_WS_OUT__MASK_6X6 0x12492092 +#define KSI0__MASK_6X6 0x04002001 +#define KSI1__MASK_6X6 0x00004002 +#define KSI10__MASK_6X6 0x10800400 +#define KSI11__MASK_6X6 0x60000800 +#define KSI12__MASK_6X6 0x02001000 +#define KSI13__MASK_6X6 0x00008000 +#define KSI14__MASK_6X6 0x00010000 +#define KSI15__MASK_6X6 0x00020000 +#define KSI16__MASK_6X6 0x00040000 +#define KSI17__MASK_6X6 0x00080000 +#define KSI18__MASK_6X6 0x08000000 +#define KSI19__MASK_6X6 0x04000000 +#define KSI2__MASK_6X6 0x00008004 +#define KSI3__MASK_6X6 0x00010008 +#define KSI4__MASK_6X6 0x00020010 +#define KSI5__MASK_6X6 0x00040020 +#define KSI6__MASK_6X6 0x00080040 +#define KSI7__MASK_6X6 0x00100080 +#define KSI8__MASK_6X6 0x00200100 +#define KSI9__MASK_6X6 0x08400200 +#define KSO0__MASK_6X6 0x04002001 +#define KSO1__MASK_6X6 0x00004002 +#define KSO10__MASK_6X6 0x10800400 +#define KSO11__MASK_6X6 0x60000800 +#define KSO12__MASK_6X6 0x02001000 +#define KSO13__MASK_6X6 0x00800000 +#define KSO14__MASK_6X6 0x01000000 +#define KSO15__MASK_6X6 0x10000000 +#define KSO16__MASK_6X6 0x20000000 +#define KSO17__MASK_6X6 0x40000000 +#define KSO18__MASK_6X6 0x08000000 +#define KSO19__MASK_6X6 0x04000000 +#define KSO2__MASK_6X6 0x00008004 +#define KSO3__MASK_6X6 0x00010008 +#define KSO4__MASK_6X6 0x00020010 +#define KSO5__MASK_6X6 0x00040020 +#define KSO6__MASK_6X6 0x00080040 +#define KSO7__MASK_6X6 0x00100080 +#define KSO8__MASK_6X6 0x00200100 +#define KSO9__MASK_6X6 0x08400200 +#define LC_RX_EN__MASK_6X6 0x54555155 +#define LC_TX_EN__MASK_6X6 0x2aaaa0aa +#define MDM_IN0__MASK_6X6 0x00000020 +#define MDM_IN1__MASK_6X6 0x00000040 +#define MDM_IN2__MASK_6X6 0x00000080 +#define MDM_IN3__MASK_6X6 0x00000100 +#define MDM_IN4__MASK_6X6 0x08000000 +#define MDM_OUT0__MASK_6X6 0x00080000 +#define MDM_OUT1__MASK_6X6 0x00100000 +#define MDM_OUT2__MASK_6X6 0x00200000 +#define MDM_OUT3__MASK_6X6 0x00400000 +#define MDM_OUT4__MASK_6X6 0x00800000 +#define MDM_OUT5__MASK_6X6 0x40000000 +#define MDM_OUT6__MASK_6X6 0x02000000 +#define MDM_OUT7__MASK_6X6 0x04000000 +#define PDM0_CLK__MASK_6X6 0x40111111 +#define PDM0_IN__MASK_6X6 0x0a222022 +#define PDM1_CLK__MASK_6X6 0x14444044 +#define PDM1_IN__MASK_6X6 0x20888088 +#define PWM0__MASK_6X6 0x40011121 +#define PWM1__MASK_6X6 0x0a020002 +#define PWM2__MASK_6X6 0x14040004 +#define PWM3__MASK_6X6 0x20080008 +#define PWM4__MASK_6X6 0x00101010 +#define PWM5__MASK_6X6 0x00202020 +#define PWM6__MASK_6X6 0x00404040 +#define PWM7__MASK_6X6 0x00808080 +#define QDEC0_A__MASK_6X6 0x40041041 +#define QDEC0_B__MASK_6X6 0x02082082 +#define QDEC1_A__MASK_6X6 0x04104104 +#define QDEC1_B__MASK_6X6 0x08208008 +#define QDEC2_A__MASK_6X6 0x10410010 +#define QDEC2_B__MASK_6X6 0x20820020 +#define QSPI_CLK__MASK_6X6 0x40041041 +#define QSPI_CSN__MASK_6X6 0x02082082 +#define QSPI_D0__MASK_6X6 0x04104104 +#define QSPI_D1__MASK_6X6 0x08208008 +#define QSPI_D2__MASK_6X6 0x10410010 +#define QSPI_D3__MASK_6X6 0x20820020 +#define SHUB_I2C0_SCK__MASK_6X6 0x40111111 +#define SHUB_I2C0_SCL__MASK_6X6 0x40111111 +#define SHUB_I2C0_SDA__MASK_6X6 0x2a222022 +#define SHUB_I2C1_SCK__MASK_6X6 0x00040004 +#define SHUB_I2C1_SCL__MASK_6X6 0x00040004 +#define SHUB_I2C1_SDA__MASK_6X6 0x00080008 +#define SHUB_SPI0_CSN__MASK_6X6 0x40110101 +#define SHUB_SPI0_CS__MASK_6X6 0x40110101 +#define SHUB_SPI0_MISO__MASK_6X6 0x20080008 +#define SHUB_SPI0_MOSI__MASK_6X6 0x14040004 +#define SHUB_SPI0_SCLK__MASK_6X6 0x0a020002 +#define SHUB_SPI0_CLK__MASK_6X6 0x0a020002 +#define SHUB_SPI1_CSN__MASK_6X6 0x00101010 +#define SHUB_SPI1_CS__MASK_6X6 0x00101010 +#define SHUB_SPI1_MISO__MASK_6X6 0x00808080 +#define SHUB_SPI1_MOSI__MASK_6X6 0x00404040 +#define SHUB_SPI1_SCLK__MASK_6X6 0x00202020 +#define SHUB_SPI1_CLK__MASK_6X6 0x00202020 +#define SPI0_CSN__MASK_6X6 0x40110101 +#define SPI0_CS__MASK_6X6 0x40110101 +#define SPI0_MISO__MASK_6X6 0x20080008 +#define SPI0_MOSI__MASK_6X6 0x14040004 +#define SPI0_SCLK__MASK_6X6 0x0a020002 +#define SPI0_CLK__MASK_6X6 0x0a020002 +#define SPI1_CSN__MASK_6X6 0x00101010 +#define SPI1_CS__MASK_6X6 0x00101010 +#define SPI1_MISO__MASK_6X6 0x00808080 +#define SPI1_MOSI__MASK_6X6 0x00404040 +#define SPI1_SCLK__MASK_6X6 0x00202020 +#define SPI1_CLK__MASK_6X6 0x00202020 +#define SWDCLK__MASK_6X6 0x00000001 +#define SWDIO__MASK_6X6 0x00000002 +#define TRACECLKOUT__MASK_6X6 0x40010101 +#define TRACEDATA_IQ0__MASK_6X6 0x0a020002 +#define TRACEDATA_IQ1__MASK_6X6 0x14040004 +#define TRACEDATA_IQ10__MASK_6X6 0x20080008 +#define TRACEDATA_IQ11__MASK_6X6 0x00101010 +#define TRACEDATA_IQ12__MASK_6X6 0x00202020 +#define TRACEDATA_IQ13__MASK_6X6 0x00404040 +#define TRACEDATA_IQ14__MASK_6X6 0x00808080 +#define TRACEDATA_IQ15__MASK_6X6 0x40010101 +#define TRACEDATA_IQ2__MASK_6X6 0x20080008 +#define TRACEDATA_IQ3__MASK_6X6 0x00101010 +#define TRACEDATA_IQ4__MASK_6X6 0x00202020 +#define TRACEDATA_IQ5__MASK_6X6 0x00404040 +#define TRACEDATA_IQ6__MASK_6X6 0x00808080 +#define TRACEDATA_IQ7__MASK_6X6 0x40010101 +#define TRACEDATA_IQ8__MASK_6X6 0x0a020002 +#define TRACEDATA_IQ9__MASK_6X6 0x14040004 +#define UART0_CTS__MASK_6X6 0x60111111 +#define UART0_RTS__MASK_6X6 0x0a222022 +#define UART0_RX__MASK_6X6 0x54555155 +#define UART0_TX__MASK_6X6 0x2aaaa0aa +#define UART1_CTS__MASK_6X6 0x20888088 +#define UART1_RTS__MASK_6X6 0x40111111 +#define UART1_RX__MASK_6X6 0x0a222022 +#define UART1_TX__MASK_6X6 0x1c444044 +#define WLAN_RX__MASK_6X6 0x08080000 +#define WLAN_TX__MASK_6X6 0x00040100 +#define XLNA_XPA0__MASK_6X6 0x12108021 +#define XLNA_XPA1__MASK_6X6 0x24210042 +#define XLNA_XPA2__MASK_6X6 0x00421084 +#define XLNA_XPA3__MASK_6X6 0x00842108 +#define XLNA_XPA4__MASK_6X6 0x48084010 +/* +pin count = 31 +package = 5x5 +bond outs = 0 1 4 5 15 17 18 19 20 21 22 25 27 29 30 + P0 + P1 + P2 + P3 + P4 + P5 + P6 + P7 + P8 + P9 + P10 + P11 + P12 + P13 + P14 + P15 + P16 + P17 + P18 + P19 + P20 + P21 + P22 + P23 + P24 + P25 + P26 + P27 + P28 + P29 + P30 +swdclk : x.............................. +swdio : .x............................. +qspi_clk : x.....!.....!.....x...........x +qspi_csn : .x.....!.....!.....x.....x..... +qspi_d0 : ..!.....!.....!.....x.....!.... +qspi_d1 : ...!...........x.....x.....x... +qspi_d2 : ....x...........!.....x.....!.. +qspi_d3 : .....x...........x.....!.....x. +spi0_csn : x.......!.......!...x.........x +spi0_sclk : .x...............x.......x.x... +spi0_mosi : ..!...............x.......!.!.. +spi0_miso : ...!...............x.........x. +spi1_csn : ....x.......!.......x.......... +spi1_sclk : .....x.......!.......x......... +spi1_mosi : ......!.......!.......x........ +spi1_miso : .......!.......x.......!....... +i2c0_sck : x...x...!...!...!...x.....!...x +i2c0_sda : .x...x.......!...x...x...x.x.x. +i2c1_sck : ..!...!.......!...x...x...!.!.. +i2c1_sda : ...!...!.......x...x...!.....x. +pdm0_clk : x...x...!...!...!...x.........x +pdm0_in : .x...x.......!...x...x...x.x... +pdm1_clk : ..!...!.......!...x...x...!.!.. +pdm1_in : ...!...!.......x...x...!.....x. +i2s0_sck_out : x..!..!.....!..x..x..x.....x..x +i2s0_ws_out : .x..x..!.....!..!..x..x..x..!.. +i2s0_sd_out : ..!..x..!.....!..x..x..!..!..x. +i2s0_sck_in : x..!..!.....!..x..x..x.....x..x +i2s0_ws_in : .x..x..!.....!..!..x..x..x..!.. +i2s0_sd_in : ..!..x..!.....!..x..x..!..!..x. +uart0_rx : x.!.x.!.!...!.!.!.x.x.x...!.!.x +uart0_tx : .x.!.x.!.....!.x.x.x.x.!.x.x.x. +uart0_cts : x...x...!...!...!...x........xx +uart0_rts : .x...x.......!...x...x...x.x... +uart1_rx : .x...x.......!...x...x...x.x... +uart1_tx : ..!...!.......!...x...x...!x!.. +uart1_cts : ...!...!.......x...x...!.....x. +uart1_rts : x...x...!...!...!...x.........x +pwm0 : x....x..!...!...!.............x +pwm1 : .x...............x.......x.x... +pwm2 : ..!...............x.......!.!.. +pwm3 : ...!...............x.........x. +pwm4 : ....x.......!.......x.......... +pwm5 : .....x.......!.......x......... +pwm6 : ......!.......!.......x........ +pwm7 : .......!.......x.......!....... +ksi19 : ..........................!.... +ksi18 : ...........................x... +ksi17 : ...................x........... +ksi16 : ..................x............ +ksi15 : .................x............. +ksi14 : ................!.............. +ksi13 : ...............x............... +ksi12 : ............!............x..... +ksi11 : ...........!.................xx +ksi10 : ..........!............!....!.. +ksi9 : .........!............x....x... +ksi8 : ........!............x......... +ksi7 : .......!............x.......... +ksi6 : ......!............x........... +ksi5 : .....x............x............ +ksi4 : ....x............x............. +ksi3 : ...!............!.............. +ksi2 : ..!............x............... +ksi1 : .x............!................ +ksi0 : x............!............!.... +kso19 : ..........................!.... +kso18 : ...........................x... +kso17 : ..............................x +kso16 : .............................x. +kso15 : ............................!.. +kso14 : ........................!...... +kso13 : .......................!....... +kso12 : ............!............x..... +kso11 : ...........!.................xx +kso10 : ..........!............!....!.. +kso9 : .........!............x....x... +kso8 : ........!............x......... +kso7 : .......!............x.......... +kso6 : ......!............x........... +kso5 : .....x............x............ +kso4 : ....x............x............. +kso3 : ...!............!.............. +kso2 : ..!............x............... +kso1 : .x............!................ +kso0 : x............!............!.... +shub_spi0_csn : x.......!.......!...x.........x +shub_spi0_sclk : .x...............x.......x.x... +shub_spi0_mosi : ..!...............x.......!.!.. +shub_spi0_miso : ...!...............x.........x. +shub_spi1_csn : ....x.......!.......x.......... +shub_spi1_sclk : .....x.......!.......x......... +shub_spi1_mosi : ......!.......!.......x........ +shub_spi1_miso : .......!.......x.......!....... +shub_i2c0_sck : x...x...!...!...!...x.........x +shub_i2c0_sda : .x...x.......!...x...x...x.x.x. +shub_i2c1_sck : ..!...............x............ +shub_i2c1_sda : ...!...............x........... +qdec0_a : x.....!.....!.....x...........x +qdec0_b : .x.....!.....!.....x.....x..... +qdec1_a : ..!.....!.....!.....x.....!.... +qdec1_b : ...!...........x.....x.....x... +qdec2_a : ....x...........!.....x.....!.. +qdec2_b : .....x...........x.....!.....x. +xlna_xpa0 : x....x.........x....x....x..!.. +xlna_xpa1 : .x....!.........!....x....!..x. +xlna_xpa2 : ..!....!....!....x....x........ +xlna_xpa3 : ...!....!....!....x....!....... +xlna_xpa4 : ....x.........!....x.......x..x +mdm_in4 : ...........................x... +mdm_in3 : ........!...................... +mdm_in2 : .......!....................... +mdm_in1 : ......!........................ +mdm_in0 : .....x......................... +mdm_out7 : ..........................!.... +mdm_out6 : .........................x..... +mdm_out5 : ..............................x +mdm_out4 : .......................!....... +mdm_out3 : ......................x........ +mdm_out2 : .....................x......... +mdm_out1 : ....................x.......... +mdm_out0 : ...................x........... +lc_rx_en : x.!.x.!.!...!.!.!.x.x.x...!.!.x +lc_tx_en : .x.!.x.!.....!.x.x.x.x.!.x.x.x. +ant_out7 : .......!.......x.......!....... +ant_out6 : ......!.......!.......x........ +ant_out5 : .....x.......!.......x......... +ant_out4 : ....x.......!.......x.......... +ant_out3 : ...!...............x.........x. +ant_out2 : ..!...............x.......!.!.. +ant_out1 : .x...............x.......x.x... +ant_out0 : x.......!.......!.............x +ble_sync : x...................x.......!.. +ble_in_process : .x...................x.......x. +ble_tx : ..!.........!.........x........ +ble_rx : ...!.........!.........!....... +ble_pti0 : ....x.........!...............x +ble_pti1 : .....x.........x.........x..... +ble_pti2 : ......!.........!.........!.... +ble_pti3 : .......!.........x............. +wlan_tx : ........!.........x............ +wlan_rx : ...................x.......x... +traceclkout : x.......!.......!.............x +tracedata_iq0 : .x...............x.......x.x... +tracedata_iq1 : ..!...............x.......!.!.. +tracedata_iq2 : ...!...............x.........x. +tracedata_iq3 : ....x.......!.......x.......... +tracedata_iq4 : .....x.......!.......x......... +tracedata_iq5 : ......!.......!.......x........ +tracedata_iq6 : .......!.......x.......!....... +tracedata_iq7 : x.......!.......!.............x +tracedata_iq8 : .x...............x.......x.x... +tracedata_iq9 : ..!...............x.......!.!.. +tracedata_iq10 : ...!...............x.........x. +tracedata_iq11 : ....x.......!.......x.......... +tracedata_iq12 : .....x.......!.......x......... +tracedata_iq13 : ......!.......!.......x........ +tracedata_iq14 : .......!.......x.......!....... +tracedata_iq15 : x.......!.......!.............x +dbg : xx!!xx!!!!!!!!!x!xxxxxx!!x!x!xx +dtopbyp : xx!!xx!!!!!!!!!x!xxxxxx!!x!x!xx +gpio : xx!!xx!!!!!!!!!x!xxxxxx!!x!x!xx +*/ +#define ANT_OUT0__MASK_5X5 0x40010101 +#define ANT_OUT1__MASK_5X5 0x0a020002 +#define ANT_OUT2__MASK_5X5 0x14040004 +#define ANT_OUT3__MASK_5X5 0x20080008 +#define ANT_OUT4__MASK_5X5 0x00101010 +#define ANT_OUT5__MASK_5X5 0x00202020 +#define ANT_OUT6__MASK_5X5 0x00404040 +#define ANT_OUT7__MASK_5X5 0x00808080 +#define BLE_IN_PROCESS__MASK_5X5 0x20200002 +#define BLE_PTI0__MASK_5X5 0x40004010 +#define BLE_PTI1__MASK_5X5 0x02008020 +#define BLE_PTI2__MASK_5X5 0x04010040 +#define BLE_PTI3__MASK_5X5 0x00020080 +#define BLE_RX__MASK_5X5 0x00802008 +#define BLE_SYNC__MASK_5X5 0x10100001 +#define BLE_TX__MASK_5X5 0x00401004 +#define DBG__MASK_5X5 0x7fffffff +#define DTOPBYP__MASK_5X5 0x7fffffff +#define GPIO__MASK_5X5 0x7fffffff +#define I2C0_SCK__MASK_5X5 0x44111111 +#define I2C0_SCL__MASK_5X5 0x44111111 +#define I2C0_SDA__MASK_5X5 0x2a222022 +#define I2C1_SCK__MASK_5X5 0x14444044 +#define I2C1_SCL__MASK_5X5 0x14444044 +#define I2C1_SDA__MASK_5X5 0x20888088 +#define I2S0_SCK_IN__MASK_5X5 0x48249049 +#define I2S0_SCK_OUT__MASK_5X5 0x48249049 +#define I2S0_SD_IN__MASK_5X5 0x24924124 +#define I2S0_SD_OUT__MASK_5X5 0x24924124 +#define I2S0_WS_IN__MASK_5X5 0x12492092 +#define I2S0_WS_OUT__MASK_5X5 0x12492092 +#define KSI0__MASK_5X5 0x04002001 +#define KSI1__MASK_5X5 0x00004002 +#define KSI10__MASK_5X5 0x10800400 +#define KSI11__MASK_5X5 0x60000800 +#define KSI12__MASK_5X5 0x02001000 +#define KSI13__MASK_5X5 0x00008000 +#define KSI14__MASK_5X5 0x00010000 +#define KSI15__MASK_5X5 0x00020000 +#define KSI16__MASK_5X5 0x00040000 +#define KSI17__MASK_5X5 0x00080000 +#define KSI18__MASK_5X5 0x08000000 +#define KSI19__MASK_5X5 0x04000000 +#define KSI2__MASK_5X5 0x00008004 +#define KSI3__MASK_5X5 0x00010008 +#define KSI4__MASK_5X5 0x00020010 +#define KSI5__MASK_5X5 0x00040020 +#define KSI6__MASK_5X5 0x00080040 +#define KSI7__MASK_5X5 0x00100080 +#define KSI8__MASK_5X5 0x00200100 +#define KSI9__MASK_5X5 0x08400200 +#define KSO0__MASK_5X5 0x04002001 +#define KSO1__MASK_5X5 0x00004002 +#define KSO10__MASK_5X5 0x10800400 +#define KSO11__MASK_5X5 0x60000800 +#define KSO12__MASK_5X5 0x02001000 +#define KSO13__MASK_5X5 0x00800000 +#define KSO14__MASK_5X5 0x01000000 +#define KSO15__MASK_5X5 0x10000000 +#define KSO16__MASK_5X5 0x20000000 +#define KSO17__MASK_5X5 0x40000000 +#define KSO18__MASK_5X5 0x08000000 +#define KSO19__MASK_5X5 0x04000000 +#define KSO2__MASK_5X5 0x00008004 +#define KSO3__MASK_5X5 0x00010008 +#define KSO4__MASK_5X5 0x00020010 +#define KSO5__MASK_5X5 0x00040020 +#define KSO6__MASK_5X5 0x00080040 +#define KSO7__MASK_5X5 0x00100080 +#define KSO8__MASK_5X5 0x00200100 +#define KSO9__MASK_5X5 0x08400200 +#define LC_RX_EN__MASK_5X5 0x54555155 +#define LC_TX_EN__MASK_5X5 0x2aaaa0aa +#define MDM_IN0__MASK_5X5 0x00000020 +#define MDM_IN1__MASK_5X5 0x00000040 +#define MDM_IN2__MASK_5X5 0x00000080 +#define MDM_IN3__MASK_5X5 0x00000100 +#define MDM_IN4__MASK_5X5 0x08000000 +#define MDM_OUT0__MASK_5X5 0x00080000 +#define MDM_OUT1__MASK_5X5 0x00100000 +#define MDM_OUT2__MASK_5X5 0x00200000 +#define MDM_OUT3__MASK_5X5 0x00400000 +#define MDM_OUT4__MASK_5X5 0x00800000 +#define MDM_OUT5__MASK_5X5 0x40000000 +#define MDM_OUT6__MASK_5X5 0x02000000 +#define MDM_OUT7__MASK_5X5 0x04000000 +#define PDM0_CLK__MASK_5X5 0x40111111 +#define PDM0_IN__MASK_5X5 0x0a222022 +#define PDM1_CLK__MASK_5X5 0x14444044 +#define PDM1_IN__MASK_5X5 0x20888088 +#define PWM0__MASK_5X5 0x40011121 +#define PWM1__MASK_5X5 0x0a020002 +#define PWM2__MASK_5X5 0x14040004 +#define PWM3__MASK_5X5 0x20080008 +#define PWM4__MASK_5X5 0x00101010 +#define PWM5__MASK_5X5 0x00202020 +#define PWM6__MASK_5X5 0x00404040 +#define PWM7__MASK_5X5 0x00808080 +#define QDEC0_A__MASK_5X5 0x40041041 +#define QDEC0_B__MASK_5X5 0x02082082 +#define QDEC1_A__MASK_5X5 0x04104104 +#define QDEC1_B__MASK_5X5 0x08208008 +#define QDEC2_A__MASK_5X5 0x10410010 +#define QDEC2_B__MASK_5X5 0x20820020 +#define QSPI_CLK__MASK_5X5 0x40041041 +#define QSPI_CSN__MASK_5X5 0x02082082 +#define QSPI_D0__MASK_5X5 0x04104104 +#define QSPI_D1__MASK_5X5 0x08208008 +#define QSPI_D2__MASK_5X5 0x10410010 +#define QSPI_D3__MASK_5X5 0x20820020 +#define SHUB_I2C0_SCK__MASK_5X5 0x40111111 +#define SHUB_I2C0_SCL__MASK_5X5 0x40111111 +#define SHUB_I2C0_SDA__MASK_5X5 0x2a222022 +#define SHUB_I2C1_SCK__MASK_5X5 0x00040004 +#define SHUB_I2C1_SCL__MASK_5X5 0x00040004 +#define SHUB_I2C1_SDA__MASK_5X5 0x00080008 +#define SHUB_SPI0_CSN__MASK_5X5 0x40110101 +#define SHUB_SPI0_CS__MASK_5X5 0x40110101 +#define SHUB_SPI0_MISO__MASK_5X5 0x20080008 +#define SHUB_SPI0_MOSI__MASK_5X5 0x14040004 +#define SHUB_SPI0_SCLK__MASK_5X5 0x0a020002 +#define SHUB_SPI0_CLK__MASK_5X5 0x0a020002 +#define SHUB_SPI1_CSN__MASK_5X5 0x00101010 +#define SHUB_SPI1_CS__MASK_5X5 0x00101010 +#define SHUB_SPI1_MISO__MASK_5X5 0x00808080 +#define SHUB_SPI1_MOSI__MASK_5X5 0x00404040 +#define SHUB_SPI1_SCLK__MASK_5X5 0x00202020 +#define SHUB_SPI1_CLK__MASK_5X5 0x00202020 +#define SPI0_CSN__MASK_5X5 0x40110101 +#define SPI0_CS__MASK_5X5 0x40110101 +#define SPI0_MISO__MASK_5X5 0x20080008 +#define SPI0_MOSI__MASK_5X5 0x14040004 +#define SPI0_SCLK__MASK_5X5 0x0a020002 +#define SPI0_CLK__MASK_5X5 0x0a020002 +#define SPI1_CSN__MASK_5X5 0x00101010 +#define SPI1_CS__MASK_5X5 0x00101010 +#define SPI1_MISO__MASK_5X5 0x00808080 +#define SPI1_MOSI__MASK_5X5 0x00404040 +#define SPI1_SCLK__MASK_5X5 0x00202020 +#define SPI1_CLK__MASK_5X5 0x00202020 +#define SWDCLK__MASK_5X5 0x00000001 +#define SWDIO__MASK_5X5 0x00000002 +#define TRACECLKOUT__MASK_5X5 0x40010101 +#define TRACEDATA_IQ0__MASK_5X5 0x0a020002 +#define TRACEDATA_IQ1__MASK_5X5 0x14040004 +#define TRACEDATA_IQ10__MASK_5X5 0x20080008 +#define TRACEDATA_IQ11__MASK_5X5 0x00101010 +#define TRACEDATA_IQ12__MASK_5X5 0x00202020 +#define TRACEDATA_IQ13__MASK_5X5 0x00404040 +#define TRACEDATA_IQ14__MASK_5X5 0x00808080 +#define TRACEDATA_IQ15__MASK_5X5 0x40010101 +#define TRACEDATA_IQ2__MASK_5X5 0x20080008 +#define TRACEDATA_IQ3__MASK_5X5 0x00101010 +#define TRACEDATA_IQ4__MASK_5X5 0x00202020 +#define TRACEDATA_IQ5__MASK_5X5 0x00404040 +#define TRACEDATA_IQ6__MASK_5X5 0x00808080 +#define TRACEDATA_IQ7__MASK_5X5 0x40010101 +#define TRACEDATA_IQ8__MASK_5X5 0x0a020002 +#define TRACEDATA_IQ9__MASK_5X5 0x14040004 +#define UART0_CTS__MASK_5X5 0x60111111 +#define UART0_RTS__MASK_5X5 0x0a222022 +#define UART0_RX__MASK_5X5 0x54555155 +#define UART0_TX__MASK_5X5 0x2aaaa0aa +#define UART1_CTS__MASK_5X5 0x20888088 +#define UART1_RTS__MASK_5X5 0x40111111 +#define UART1_RX__MASK_5X5 0x0a222022 +#define UART1_TX__MASK_5X5 0x1c444044 +#define WLAN_RX__MASK_5X5 0x08080000 +#define WLAN_TX__MASK_5X5 0x00040100 +#define XLNA_XPA0__MASK_5X5 0x12108021 +#define XLNA_XPA1__MASK_5X5 0x24210042 +#define XLNA_XPA2__MASK_5X5 0x00421084 +#define XLNA_XPA3__MASK_5X5 0x00842108 +#define XLNA_XPA4__MASK_5X5 0x48084010 +/* +pin count = 31 +package = csp +bond outs = 0 1 4 5 6 7 12 13 15 17 18 19 20 21 22 25 27 29 30 + P0 + P1 + P2 + P3 + P4 + P5 + P6 + P7 + P8 + P9 + P10 + P11 + P12 + P13 + P14 + P15 + P16 + P17 + P18 + P19 + P20 + P21 + P22 + P23 + P24 + P25 + P26 + P27 + P28 + P29 + P30 +swdclk : x.............................. +swdio : .x............................. +qspi_clk : x.....x.....x.....x...........x +qspi_csn : .x.....x.....x.....x.....x..... +qspi_d0 : ..!.....!.....!.....x.....!.... +qspi_d1 : ...!...........x.....x.....x... +qspi_d2 : ....x...........!.....x.....!.. +qspi_d3 : .....x...........x.....!.....x. +spi0_csn : x.......!.......!...x.........x +spi0_sclk : .x...............x.......x.x... +spi0_mosi : ..!...............x.......!.!.. +spi0_miso : ...!...............x.........x. +spi1_csn : ....x.......x.......x.......... +spi1_sclk : .....x.......x.......x......... +spi1_mosi : ......x.......!.......x........ +spi1_miso : .......x.......x.......!....... +i2c0_sck : x...x...!...x...!...x.....!...x +i2c0_sda : .x...x.......x...x...x...x.x.x. +i2c1_sck : ..!...x.......!...x...x...!.!.. +i2c1_sda : ...!...x.......x...x...!.....x. +pdm0_clk : x...x...!...x...!...x.........x +pdm0_in : .x...x.......x...x...x...x.x... +pdm1_clk : ..!...x.......!...x...x...!.!.. +pdm1_in : ...!...x.......x...x...!.....x. +i2s0_sck_out : x..!..x.....x..x..x..x.....x..x +i2s0_ws_out : .x..x..x.....x..!..x..x..x..!.. +i2s0_sd_out : ..!..x..!.....!..x..x..!..!..x. +i2s0_sck_in : x..!..x.....x..x..x..x.....x..x +i2s0_ws_in : .x..x..x.....x..!..x..x..x..!.. +i2s0_sd_in : ..!..x..!.....!..x..x..!..!..x. +uart0_rx : x.!.x.x.!...x.!.!.x.x.x...!.!.x +uart0_tx : .x.!.x.x.....x.x.x.x.x.!.x.x.x. +uart0_cts : x...x...!...x...!...x........xx +uart0_rts : .x...x.......x...x...x...x.x... +uart1_rx : .x...x.......x...x...x...x.x... +uart1_tx : ..!...x.......!...x...x...!x!.. +uart1_cts : ...!...x.......x...x...!.....x. +uart1_rts : x...x...!...x...!...x.........x +pwm0 : x....x..!...x...!.............x +pwm1 : .x...............x.......x.x... +pwm2 : ..!...............x.......!.!.. +pwm3 : ...!...............x.........x. +pwm4 : ....x.......x.......x.......... +pwm5 : .....x.......x.......x......... +pwm6 : ......x.......!.......x........ +pwm7 : .......x.......x.......!....... +ksi19 : ..........................!.... +ksi18 : ...........................x... +ksi17 : ...................x........... +ksi16 : ..................x............ +ksi15 : .................x............. +ksi14 : ................!.............. +ksi13 : ...............x............... +ksi12 : ............x............x..... +ksi11 : ...........!.................xx +ksi10 : ..........!............!....!.. +ksi9 : .........!............x....x... +ksi8 : ........!............x......... +ksi7 : .......x............x.......... +ksi6 : ......x............x........... +ksi5 : .....x............x............ +ksi4 : ....x............x............. +ksi3 : ...!............!.............. +ksi2 : ..!............x............... +ksi1 : .x............!................ +ksi0 : x............x............!.... +kso19 : ..........................!.... +kso18 : ...........................x... +kso17 : ..............................x +kso16 : .............................x. +kso15 : ............................!.. +kso14 : ........................!...... +kso13 : .......................!....... +kso12 : ............x............x..... +kso11 : ...........!.................xx +kso10 : ..........!............!....!.. +kso9 : .........!............x....x... +kso8 : ........!............x......... +kso7 : .......x............x.......... +kso6 : ......x............x........... +kso5 : .....x............x............ +kso4 : ....x............x............. +kso3 : ...!............!.............. +kso2 : ..!............x............... +kso1 : .x............!................ +kso0 : x............x............!.... +shub_spi0_csn : x.......!.......!...x.........x +shub_spi0_sclk : .x...............x.......x.x... +shub_spi0_mosi : ..!...............x.......!.!.. +shub_spi0_miso : ...!...............x.........x. +shub_spi1_csn : ....x.......x.......x.......... +shub_spi1_sclk : .....x.......x.......x......... +shub_spi1_mosi : ......x.......!.......x........ +shub_spi1_miso : .......x.......x.......!....... +shub_i2c0_sck : x...x...!...x...!...x.........x +shub_i2c0_sda : .x...x.......x...x...x...x.x.x. +shub_i2c1_sck : ..!...............x............ +shub_i2c1_sda : ...!...............x........... +qdec0_a : x.....x.....x.....x...........x +qdec0_b : .x.....x.....x.....x.....x..... +qdec1_a : ..!.....!.....!.....x.....!.... +qdec1_b : ...!...........x.....x.....x... +qdec2_a : ....x...........!.....x.....!.. +qdec2_b : .....x...........x.....!.....x. +xlna_xpa0 : x....x.........x....x....x..!.. +xlna_xpa1 : .x....x.........!....x....!..x. +xlna_xpa2 : ..!....x....x....x....x........ +xlna_xpa3 : ...!....!....x....x....!....... +xlna_xpa4 : ....x.........!....x.......x..x +mdm_in4 : ...........................x... +mdm_in3 : ........!...................... +mdm_in2 : .......x....................... +mdm_in1 : ......x........................ +mdm_in0 : .....x......................... +mdm_out7 : ..........................!.... +mdm_out6 : .........................x..... +mdm_out5 : ..............................x +mdm_out4 : .......................!....... +mdm_out3 : ......................x........ +mdm_out2 : .....................x......... +mdm_out1 : ....................x.......... +mdm_out0 : ...................x........... +lc_rx_en : x.!.x.x.!...x.!.!.x.x.x...!.!.x +lc_tx_en : .x.!.x.x.....x.x.x.x.x.!.x.x.x. +ant_out7 : .......x.......x.......!....... +ant_out6 : ......x.......!.......x........ +ant_out5 : .....x.......x.......x......... +ant_out4 : ....x.......x.......x.......... +ant_out3 : ...!...............x.........x. +ant_out2 : ..!...............x.......!.!.. +ant_out1 : .x...............x.......x.x... +ant_out0 : x.......!.......!.............x +ble_sync : x...................x.......!.. +ble_in_process : .x...................x.......x. +ble_tx : ..!.........x.........x........ +ble_rx : ...!.........x.........!....... +ble_pti0 : ....x.........!...............x +ble_pti1 : .....x.........x.........x..... +ble_pti2 : ......x.........!.........!.... +ble_pti3 : .......x.........x............. +wlan_tx : ........!.........x............ +wlan_rx : ...................x.......x... +traceclkout : x.......!.......!.............x +tracedata_iq0 : .x...............x.......x.x... +tracedata_iq1 : ..!...............x.......!.!.. +tracedata_iq2 : ...!...............x.........x. +tracedata_iq3 : ....x.......x.......x.......... +tracedata_iq4 : .....x.......x.......x......... +tracedata_iq5 : ......x.......!.......x........ +tracedata_iq6 : .......x.......x.......!....... +tracedata_iq7 : x.......!.......!.............x +tracedata_iq8 : .x...............x.......x.x... +tracedata_iq9 : ..!...............x.......!.!.. +tracedata_iq10 : ...!...............x.........x. +tracedata_iq11 : ....x.......x.......x.......... +tracedata_iq12 : .....x.......x.......x......... +tracedata_iq13 : ......x.......!.......x........ +tracedata_iq14 : .......x.......x.......!....... +tracedata_iq15 : x.......!.......!.............x +dbg : xx!!xxxx!!!!xx!x!xxxxxx!!x!x!xx +dtopbyp : xx!!xxxx!!!!xx!x!xxxxxx!!x!x!xx +gpio : xx!!xxxx!!!!xx!x!xxxxxx!!x!x!xx +*/ +#define ANT_OUT0__MASK_CSP 0x40010101 +#define ANT_OUT1__MASK_CSP 0x0a020002 +#define ANT_OUT2__MASK_CSP 0x14040004 +#define ANT_OUT3__MASK_CSP 0x20080008 +#define ANT_OUT4__MASK_CSP 0x00101010 +#define ANT_OUT5__MASK_CSP 0x00202020 +#define ANT_OUT6__MASK_CSP 0x00404040 +#define ANT_OUT7__MASK_CSP 0x00808080 +#define BLE_IN_PROCESS__MASK_CSP 0x20200002 +#define BLE_PTI0__MASK_CSP 0x40004010 +#define BLE_PTI1__MASK_CSP 0x02008020 +#define BLE_PTI2__MASK_CSP 0x04010040 +#define BLE_PTI3__MASK_CSP 0x00020080 +#define BLE_RX__MASK_CSP 0x00802008 +#define BLE_SYNC__MASK_CSP 0x10100001 +#define BLE_TX__MASK_CSP 0x00401004 +#define DBG__MASK_CSP 0x7fffffff +#define DTOPBYP__MASK_CSP 0x7fffffff +#define GPIO__MASK_CSP 0x7fffffff +#define I2C0_SCK__MASK_CSP 0x44111111 +#define I2C0_SCL__MASK_CSP 0x44111111 +#define I2C0_SDA__MASK_CSP 0x2a222022 +#define I2C1_SCK__MASK_CSP 0x14444044 +#define I2C1_SCL__MASK_CSP 0x14444044 +#define I2C1_SDA__MASK_CSP 0x20888088 +#define I2S0_SCK_IN__MASK_CSP 0x48249049 +#define I2S0_SCK_OUT__MASK_CSP 0x48249049 +#define I2S0_SD_IN__MASK_CSP 0x24924124 +#define I2S0_SD_OUT__MASK_CSP 0x24924124 +#define I2S0_WS_IN__MASK_CSP 0x12492092 +#define I2S0_WS_OUT__MASK_CSP 0x12492092 +#define KSI0__MASK_CSP 0x04002001 +#define KSI1__MASK_CSP 0x00004002 +#define KSI10__MASK_CSP 0x10800400 +#define KSI11__MASK_CSP 0x60000800 +#define KSI12__MASK_CSP 0x02001000 +#define KSI13__MASK_CSP 0x00008000 +#define KSI14__MASK_CSP 0x00010000 +#define KSI15__MASK_CSP 0x00020000 +#define KSI16__MASK_CSP 0x00040000 +#define KSI17__MASK_CSP 0x00080000 +#define KSI18__MASK_CSP 0x08000000 +#define KSI19__MASK_CSP 0x04000000 +#define KSI2__MASK_CSP 0x00008004 +#define KSI3__MASK_CSP 0x00010008 +#define KSI4__MASK_CSP 0x00020010 +#define KSI5__MASK_CSP 0x00040020 +#define KSI6__MASK_CSP 0x00080040 +#define KSI7__MASK_CSP 0x00100080 +#define KSI8__MASK_CSP 0x00200100 +#define KSI9__MASK_CSP 0x08400200 +#define KSO0__MASK_CSP 0x04002001 +#define KSO1__MASK_CSP 0x00004002 +#define KSO10__MASK_CSP 0x10800400 +#define KSO11__MASK_CSP 0x60000800 +#define KSO12__MASK_CSP 0x02001000 +#define KSO13__MASK_CSP 0x00800000 +#define KSO14__MASK_CSP 0x01000000 +#define KSO15__MASK_CSP 0x10000000 +#define KSO16__MASK_CSP 0x20000000 +#define KSO17__MASK_CSP 0x40000000 +#define KSO18__MASK_CSP 0x08000000 +#define KSO19__MASK_CSP 0x04000000 +#define KSO2__MASK_CSP 0x00008004 +#define KSO3__MASK_CSP 0x00010008 +#define KSO4__MASK_CSP 0x00020010 +#define KSO5__MASK_CSP 0x00040020 +#define KSO6__MASK_CSP 0x00080040 +#define KSO7__MASK_CSP 0x00100080 +#define KSO8__MASK_CSP 0x00200100 +#define KSO9__MASK_CSP 0x08400200 +#define LC_RX_EN__MASK_CSP 0x54555155 +#define LC_TX_EN__MASK_CSP 0x2aaaa0aa +#define MDM_IN0__MASK_CSP 0x00000020 +#define MDM_IN1__MASK_CSP 0x00000040 +#define MDM_IN2__MASK_CSP 0x00000080 +#define MDM_IN3__MASK_CSP 0x00000100 +#define MDM_IN4__MASK_CSP 0x08000000 +#define MDM_OUT0__MASK_CSP 0x00080000 +#define MDM_OUT1__MASK_CSP 0x00100000 +#define MDM_OUT2__MASK_CSP 0x00200000 +#define MDM_OUT3__MASK_CSP 0x00400000 +#define MDM_OUT4__MASK_CSP 0x00800000 +#define MDM_OUT5__MASK_CSP 0x40000000 +#define MDM_OUT6__MASK_CSP 0x02000000 +#define MDM_OUT7__MASK_CSP 0x04000000 +#define PDM0_CLK__MASK_CSP 0x40111111 +#define PDM0_IN__MASK_CSP 0x0a222022 +#define PDM1_CLK__MASK_CSP 0x14444044 +#define PDM1_IN__MASK_CSP 0x20888088 +#define PWM0__MASK_CSP 0x40011121 +#define PWM1__MASK_CSP 0x0a020002 +#define PWM2__MASK_CSP 0x14040004 +#define PWM3__MASK_CSP 0x20080008 +#define PWM4__MASK_CSP 0x00101010 +#define PWM5__MASK_CSP 0x00202020 +#define PWM6__MASK_CSP 0x00404040 +#define PWM7__MASK_CSP 0x00808080 +#define QDEC0_A__MASK_CSP 0x40041041 +#define QDEC0_B__MASK_CSP 0x02082082 +#define QDEC1_A__MASK_CSP 0x04104104 +#define QDEC1_B__MASK_CSP 0x08208008 +#define QDEC2_A__MASK_CSP 0x10410010 +#define QDEC2_B__MASK_CSP 0x20820020 +#define QSPI_CLK__MASK_CSP 0x40041041 +#define QSPI_CSN__MASK_CSP 0x02082082 +#define QSPI_D0__MASK_CSP 0x04104104 +#define QSPI_D1__MASK_CSP 0x08208008 +#define QSPI_D2__MASK_CSP 0x10410010 +#define QSPI_D3__MASK_CSP 0x20820020 +#define SHUB_I2C0_SCK__MASK_CSP 0x40111111 +#define SHUB_I2C0_SCL__MASK_CSP 0x40111111 +#define SHUB_I2C0_SDA__MASK_CSP 0x2a222022 +#define SHUB_I2C1_SCK__MASK_CSP 0x00040004 +#define SHUB_I2C1_SCL__MASK_CSP 0x00040004 +#define SHUB_I2C1_SDA__MASK_CSP 0x00080008 +#define SHUB_SPI0_CSN__MASK_CSP 0x40110101 +#define SHUB_SPI0_CS__MASK_CSP 0x40110101 +#define SHUB_SPI0_MISO__MASK_CSP 0x20080008 +#define SHUB_SPI0_MOSI__MASK_CSP 0x14040004 +#define SHUB_SPI0_SCLK__MASK_CSP 0x0a020002 +#define SHUB_SPI0_CLK__MASK_CSP 0x0a020002 +#define SHUB_SPI1_CSN__MASK_CSP 0x00101010 +#define SHUB_SPI1_CS__MASK_CSP 0x00101010 +#define SHUB_SPI1_MISO__MASK_CSP 0x00808080 +#define SHUB_SPI1_MOSI__MASK_CSP 0x00404040 +#define SHUB_SPI1_SCLK__MASK_CSP 0x00202020 +#define SHUB_SPI1_CLK__MASK_CSP 0x00202020 +#define SPI0_CSN__MASK_CSP 0x40110101 +#define SPI0_CS__MASK_CSP 0x40110101 +#define SPI0_MISO__MASK_CSP 0x20080008 +#define SPI0_MOSI__MASK_CSP 0x14040004 +#define SPI0_SCLK__MASK_CSP 0x0a020002 +#define SPI0_CLK__MASK_CSP 0x0a020002 +#define SPI1_CSN__MASK_CSP 0x00101010 +#define SPI1_CS__MASK_CSP 0x00101010 +#define SPI1_MISO__MASK_CSP 0x00808080 +#define SPI1_MOSI__MASK_CSP 0x00404040 +#define SPI1_SCLK__MASK_CSP 0x00202020 +#define SPI1_CLK__MASK_CSP 0x00202020 +#define SWDCLK__MASK_CSP 0x00000001 +#define SWDIO__MASK_CSP 0x00000002 +#define TRACECLKOUT__MASK_CSP 0x40010101 +#define TRACEDATA_IQ0__MASK_CSP 0x0a020002 +#define TRACEDATA_IQ1__MASK_CSP 0x14040004 +#define TRACEDATA_IQ10__MASK_CSP 0x20080008 +#define TRACEDATA_IQ11__MASK_CSP 0x00101010 +#define TRACEDATA_IQ12__MASK_CSP 0x00202020 +#define TRACEDATA_IQ13__MASK_CSP 0x00404040 +#define TRACEDATA_IQ14__MASK_CSP 0x00808080 +#define TRACEDATA_IQ15__MASK_CSP 0x40010101 +#define TRACEDATA_IQ2__MASK_CSP 0x20080008 +#define TRACEDATA_IQ3__MASK_CSP 0x00101010 +#define TRACEDATA_IQ4__MASK_CSP 0x00202020 +#define TRACEDATA_IQ5__MASK_CSP 0x00404040 +#define TRACEDATA_IQ6__MASK_CSP 0x00808080 +#define TRACEDATA_IQ7__MASK_CSP 0x40010101 +#define TRACEDATA_IQ8__MASK_CSP 0x0a020002 +#define TRACEDATA_IQ9__MASK_CSP 0x14040004 +#define UART0_CTS__MASK_CSP 0x60111111 +#define UART0_RTS__MASK_CSP 0x0a222022 +#define UART0_RX__MASK_CSP 0x54555155 +#define UART0_TX__MASK_CSP 0x2aaaa0aa +#define UART1_CTS__MASK_CSP 0x20888088 +#define UART1_RTS__MASK_CSP 0x40111111 +#define UART1_RX__MASK_CSP 0x0a222022 +#define UART1_TX__MASK_CSP 0x1c444044 +#define WLAN_RX__MASK_CSP 0x08080000 +#define WLAN_TX__MASK_CSP 0x00040100 +#define XLNA_XPA0__MASK_CSP 0x12108021 +#define XLNA_XPA1__MASK_CSP 0x24210042 +#define XLNA_XPA2__MASK_CSP 0x00421084 +#define XLNA_XPA3__MASK_CSP 0x00842108 +#define XLNA_XPA4__MASK_CSP 0x48084010 diff --git a/ATM33xx-5/include/reg/at_wrpr.h b/ATM33xx-5/include/reg/at_wrpr.h new file mode 100644 index 0000000..905fb89 --- /dev/null +++ b/ATM33xx-5/include/reg/at_wrpr.h @@ -0,0 +1,222 @@ +/** + ****************************************************************************** + * + * @file at_wrpr.h + * + * @brief Peripheral module clock and reset control + * + * Copyright (C) Atmosic 2020-2023 + * + ****************************************************************************** + */ + +#pragma once + +#include "at_apb_wrpr_pins_regs_core_macro.h" + +#define WRPR_CTRL__CLK_DISABLE 0x00000000U +#define WRPR_CTRL__CLK_ENABLE 0x00000001U +#define WRPR_CTRL__SRESET 0x00000002U +#define WRPR_CTRL__CLK_SEL 0x00000004U + +#define PCLK_ALT_FREQ 16000000U + +#define APB_MOD_SIZE 0x1000 +#define APB0_NONSECURE_BASE 0x40140000 +#define APB1_NONSECURE_BASE 0x40150000 +#define APB2_NONSECURE_BASE 0x40160000 +#define APB0_SECURE_BASE 0x50140000 +#define APB1_SECURE_BASE 0x50150000 +#define APB2_SECURE_BASE 0x50160000 +#define APB0_NUM_MODULES 16 +#define APB1_NUM_MODULES 14 +#define APB2_NUM_MODULES 8 + +__STATIC_FORCEINLINE volatile uint32_t * +module_to_ctrl(volatile const void *addr) +{ + uintptr_t address = (uintptr_t)addr; + + if ((address >= APB0_NONSECURE_BASE) && + (address < APB0_NONSECURE_BASE + (APB_MOD_SIZE * APB0_NUM_MODULES))) { + int i = (address - APB0_NONSECURE_BASE) / APB_MOD_SIZE; + return ((&CMSDK_WRPR0_NONSECURE->APB0_CTRL) + i); + } + if ((address >= APB1_NONSECURE_BASE) && + (address < APB1_NONSECURE_BASE + (APB_MOD_SIZE * APB1_NUM_MODULES))) { + int i = (address - APB1_NONSECURE_BASE) / APB_MOD_SIZE; + return ((&CMSDK_WRPR1_NONSECURE->APB0_CTRL) + i); + } + if ((address >= APB2_NONSECURE_BASE) && + (address < APB2_NONSECURE_BASE + (APB_MOD_SIZE * APB2_NUM_MODULES))) { + int i = (address - APB2_NONSECURE_BASE) / APB_MOD_SIZE; + return ((&CMSDK_WRPR2_NONSECURE->APB0_CTRL) + i); + } + if ((address >= APB0_SECURE_BASE) && + (address < APB0_SECURE_BASE + (APB_MOD_SIZE * APB0_NUM_MODULES))) { + int i = (address - APB0_SECURE_BASE) / APB_MOD_SIZE; + return ((&CMSDK_WRPR0_SECURE->APB0_CTRL) + i); + } + if ((address >= APB1_SECURE_BASE) && + (address < APB1_SECURE_BASE + (APB_MOD_SIZE * APB1_NUM_MODULES))) { + int i = (address - APB1_SECURE_BASE) / APB_MOD_SIZE; + return ((&CMSDK_WRPR1_SECURE->APB0_CTRL) + i); + } + if ((address >= APB2_SECURE_BASE) && + (address < APB2_SECURE_BASE + (APB_MOD_SIZE * APB2_NUM_MODULES))) { + int i = (address - APB2_SECURE_BASE) / APB_MOD_SIZE; + return ((&CMSDK_WRPR2_SECURE->APB0_CTRL) + i); + } + return (NULL); +} + +#define WRPR_CTRL_GET(__m) ({ \ + *module_to_ctrl(__m); \ +}) + +#define WRPR_CTRL_SET(__m, __s) do { \ + *module_to_ctrl(__m) = (__s); \ +} while (0) + +#define WRPR_CTRL_GETSET(__m, __s) ({ \ + volatile uint32_t *_ctrl = module_to_ctrl(__m); \ + uint32_t _ret = *_ctrl; \ + *_ctrl = (__s); \ + _ret; \ +}) + +/* + * PUSH/POP macros mimic do/while syntax: + * + * WRPR_CTRL_PUSH(CMSDK_PSEQ, WRPR_CTRL__CLK_ENABLE) { + * ...; + * } WRPR_CTRL_POP(); + */ +#define WRPR_CTRL_PUSH(__m, __s) do { \ + volatile uint32_t *wrpr_ctrl_addr = module_to_ctrl(__m); \ + uint32_t wrpr_ctrl_save = *wrpr_ctrl_addr; \ + *wrpr_ctrl_addr = (__s); \ + do + +#define WRPR_CTRL_POP() \ + while (0); \ + *wrpr_ctrl_addr = wrpr_ctrl_save; \ +} while (0) + +/* + * Pin to selection register mapping + */ +#define PSEL_REG_P0 PSEL_A +#define PSEL_REG_P1 PSEL_A +#define PSEL_REG_P2 PSEL_A +#define PSEL_REG_P3 PSEL_A +#define PSEL_REG_P4 PSEL_B +#define PSEL_REG_P5 PSEL_B +#define PSEL_REG_P6 PSEL_B +#define PSEL_REG_P7 PSEL_B +#define PSEL_REG_P8 PSEL_C +#define PSEL_REG_P9 PSEL_C +#define PSEL_REG_P10 PSEL_C +#define PSEL_REG_P11 PSEL_C +#define PSEL_REG_P12 PSEL_D +#define PSEL_REG_P13 PSEL_D +#define PSEL_REG_P14 PSEL_D +#define PSEL_REG_P15 PSEL_D +#define PSEL_REG_P16 PSEL_E +#define PSEL_REG_P17 PSEL_E +#define PSEL_REG_P18 PSEL_E +#define PSEL_REG_P19 PSEL_E +#define PSEL_REG_P20 PSEL_F +#define PSEL_REG_P21 PSEL_F +#define PSEL_REG_P22 PSEL_F +#define PSEL_REG_P23 PSEL_F +#define PSEL_REG_P24 PSEL_G +#define PSEL_REG_P25 PSEL_G +#define PSEL_REG_P26 PSEL_G +#define PSEL_REG_P27 PSEL_G +#define PSEL_REG_P28 PSEL_H +#define PSEL_REG_P29 PSEL_H +#define PSEL_REG_P30 PSEL_H + +#define PIN2REG(pin) _PIN2REG(pin) +#define _PIN2REG(pin) PSEL_REG_P ## pin + +/* + * Compute pin selection register core macro + */ +#define PIN_SEL(pin, sfx) _PIN_SEL(PIN2REG(pin), pin, sfx) +#define _PIN_SEL(sel, pin, sfx) __PIN_SEL(sel, pin, sfx) +#define __PIN_SEL(sel, pin, sfx) \ + WRPRPINS_ ## sel ## __P ## pin ## _SEL__ ## sfx + +/* + * Compute signal macro (see at_pinmux.h) + */ +#define PIN_SIG(pin, sig) ({ \ + STATIC_ASSERT((1 << pin) & sig ## __MASK, "Pin does not support signal"); \ + PINMUX_ ## sig; \ +}) + +/* + * Assign signal to pin + */ +#define PIN_SELECT(pin, sig) \ + PIN_SEL(pin, MODIFY)(CMSDK_WRPR0_NONSECURE->PIN2REG(pin), PIN_SIG(pin, sig)) + +/* + * Set pin pullup + */ +#define PIN_PULLUP(pin) do { \ + STATIC_ASSERT((1 << pin) & WRPRPINS_PUPD_OVRD__WRITE, \ + "Pin does not support pull"); \ + uint32_t mask = (1 << pin); \ + CMSDK_WRPR0_NONSECURE->PUPD_OVRD_VAL |= mask; \ + CMSDK_WRPR0_NONSECURE->PUPD_OVRD |= mask; \ +} while(0) + +/* + * Set pin pulldown + */ +#define PIN_PULLDOWN(pin) do { \ + STATIC_ASSERT((1 << pin) & WRPRPINS_PUPD_OVRD__WRITE, \ + "Pin does not support pull"); \ + uint32_t mask = (1 << pin); \ + CMSDK_WRPR0_NONSECURE->PUPD_OVRD_VAL &= ~mask; \ + CMSDK_WRPR0_NONSECURE->PUPD_OVRD |= mask; \ +} while(0) + +/* + * Clear pin pull + */ +#define PIN_PULL_CLR(pin) do { \ + STATIC_ASSERT((1 << pin) & WRPRPINS_PUPD_OVRD__WRITE, \ + "Pin does not support pull"); \ + uint32_t mask = (1 << pin); \ + CMSDK_WRPR0_NONSECURE->PUPD_OVRD &= ~mask; \ +} while(0) + +/* + * Set pin drive strength high + */ +#define PIN_PDSN_HIGH(pin) do { \ + STATIC_ASSERT((1 << pin) & WRPRPINS_PDSN__WRITE, \ + "Pin does not support drive strength"); \ + uint32_t mask = (1 << pin); \ + CMSDK_WRPR0_NONSECURE->PDSN &= ~mask; \ +} while (0) + +/* + * Set pin drive strength low + */ +#define PIN_PDSN_LOW(pin) do { \ + STATIC_ASSERT((1 << pin) & WRPRPINS_PDSN__WRITE, \ + "Pin does not support drive strength"); \ + uint32_t mask = (1 << pin); \ + CMSDK_WRPR0_NONSECURE->PDSN |= mask; \ +} while (0) + +/* + * Lookup GPIO bit from pin + */ +#define PIN2GPIO(pin) _PIN2GPIO(pin, GPIO) +#define _PIN2GPIO(pin, sig) P ## pin ## _ ## sig diff --git a/ATM33xx-5/include/reg/base_addr.h b/ATM33xx-5/include/reg/base_addr.h new file mode 100644 index 0000000..fdd01d7 --- /dev/null +++ b/ATM33xx-5/include/reg/base_addr.h @@ -0,0 +1,1280 @@ +/** + ***************************************************************************** + * + * @file base_addr.h + * + * @brief Base Address definitions + * + * Copyright (C) Atmosic 2022-2024 + * + ***************************************************************************** + */ + +#pragma once +#include "base_addr_place_holders.h" + +/** + * @defgroup at_base_addr base_addr + * @ingroup AT_REG + * @brief base address definitions. + * @{ + */ +/*---------- AT_AHB_PRRF ----------*/ +typedef struct { + __IO uint32_t PATCH_TAG0; + __IO uint32_t PATCH_TAG1; + __IO uint32_t PATCH_TAG2; + __IO uint32_t PATCH_TAG3; + __IO uint32_t PATCH_TAG4; + __IO uint32_t PATCH_TAG5; + __IO uint32_t PATCH_TAG6; + __IO uint32_t PATCH_TAG7; + __IO uint32_t PATCH_TAG8; + __IO uint32_t PATCH_TAG9; + __IO uint32_t PATCH_TAG10; + __IO uint32_t PATCH_TAG11; + __IO uint32_t PATCH_TAG12; + __IO uint32_t PATCH_TAG13; + __IO uint32_t PATCH_TAG14; + __IO uint32_t PATCH_TAG15; + __IO uint32_t PATCH0; + __IO uint32_t PATCH1; + __IO uint32_t PATCH2; + __IO uint32_t PATCH3; + __IO uint32_t PATCH4; + __IO uint32_t PATCH5; + __IO uint32_t PATCH6; + __IO uint32_t PATCH7; + __IO uint32_t PATCH8; + __IO uint32_t PATCH9; + __IO uint32_t PATCH10; + __IO uint32_t PATCH11; + __IO uint32_t PATCH12; + __IO uint32_t PATCH13; + __IO uint32_t PATCH14; + __IO uint32_t PATCH15; + __IO uint32_t PATCH16; + __IO uint32_t PATCH17; + __IO uint32_t PATCH18; + __IO uint32_t PATCH19; + __IO uint32_t PATCH20; + __IO uint32_t PATCH21; + __IO uint32_t PATCH22; + __IO uint32_t PATCH23; + __IO uint32_t PATCH24; + __IO uint32_t PATCH25; + __IO uint32_t PATCH26; + __IO uint32_t PATCH27; + __IO uint32_t PATCH28; + __IO uint32_t PATCH29; + __IO uint32_t PATCH30; + __IO uint32_t PATCH31; + __IO uint32_t PATCH32; + __IO uint32_t PATCH33; + __IO uint32_t PATCH34; + __IO uint32_t PATCH35; + __IO uint32_t PATCH36; + __IO uint32_t PATCH37; + __IO uint32_t PATCH38; + __IO uint32_t PATCH39; + __IO uint32_t PATCH40; + __IO uint32_t PATCH41; + __IO uint32_t PATCH42; + __IO uint32_t PATCH43; + __IO uint32_t PATCH44; + __IO uint32_t PATCH45; + __IO uint32_t PATCH46; + __IO uint32_t PATCH47; + __IO uint32_t RRAM_WRT_CONFIG_LO; + __IO uint32_t RRAM_WRT_CONFIG_HI; + __I uint32_t RRAM_READ_CONFIG_LO; + __I uint32_t RRAM_READ_CONFIG_HI; + __IO uint32_t RRAM_CACHE_CONFIG; + __IO uint32_t RRAM_MEM_CONFIG; + __I uint32_t RRAM_STATUS; +} CMSDK_AT_AHB_PRRF_TypeDef; + +/*---------- AT_AHB_SHA2 ----------*/ +typedef struct { + __IO uint32_t CONTROL; + __IO uint32_t SIDELOAD_CTRL; + __IO uint32_t CMD; + __I uint32_t MESSAGE_LENGTH_LO; + __I uint32_t MESSAGE_LENGTH_HI; + __IO uint32_t WIPE_V; + __IO uint32_t FIFO_PUSH; + __I uint32_t DIGEST0; + __I uint32_t DIGEST1; + __I uint32_t DIGEST2; + __I uint32_t DIGEST3; + __I uint32_t DIGEST4; + __I uint32_t DIGEST5; + __I uint32_t DIGEST6; + __I uint32_t DIGEST7; + __IO uint32_t KEY_0; + __IO uint32_t KEY_1; + __IO uint32_t KEY_2; + __IO uint32_t KEY_3; + __IO uint32_t KEY_4; + __IO uint32_t KEY_5; + __IO uint32_t KEY_6; + __IO uint32_t KEY_7; + __I uint32_t STATUS; + __I uint32_t INTERRUPT_STATUS; + __IO uint32_t INTERRUPT_MASK; + __IO uint32_t SET_INTERRUPT; + __IO uint32_t RESET_INTERRUPT; + __I uint32_t ERR_CODE; + uint32_t RESERVED0[994]; + __I uint32_t ID; +} CMSDK_AT_AHB_SHA2_TypeDef; + +/*---------- AT_APB_WRPR_PINS ----------*/ +typedef struct { + __IO uint32_t APB0_CTRL; + __IO uint32_t APB1_CTRL; + __IO uint32_t APB2_CTRL; + __IO uint32_t APB3_CTRL; + __IO uint32_t APB4_CTRL; + __IO uint32_t APB5_CTRL; + __IO uint32_t APB6_CTRL; + __IO uint32_t APB7_CTRL; + __IO uint32_t APB8_CTRL; + __IO uint32_t APB9_CTRL; + __IO uint32_t APB10_CTRL; + __IO uint32_t APB11_CTRL; + __IO uint32_t APB12_CTRL; + __IO uint32_t APB13_CTRL; + __IO uint32_t APB14_CTRL; + __IO uint32_t APB15_CTRL; + __IO uint32_t CLK_HPC_PIN_OUT_CTRL; + __IO uint32_t CLK_MPC_PIN_OUT_CTRL; + __IO uint32_t CLK_LPC_PIN_OUT_CTRL; + __IO uint32_t DBG_CTRL; + __IO uint32_t PSEL_A; + __IO uint32_t PSEL_B; + __IO uint32_t PSEL_C; + __IO uint32_t PSEL_D; + __IO uint32_t PSEL_E; + __IO uint32_t PSEL_F; + __IO uint32_t PSEL_G; + __IO uint32_t PSEL_H; + __IO uint32_t PSEL_I; + __IO uint32_t PUPD_OVRD; + __IO uint32_t PUPD_OVRD_VAL; + __IO uint32_t REMAP; + __IO uint32_t AHB_INTERPOSERS; + __IO uint32_t SCRATCHPAD_A; + __IO uint32_t SCRATCHPAD_B; + __IO uint32_t SCRATCHPAD_C; + __IO uint32_t SCRATCHPAD_D; + __IO uint32_t RRAM_WRITE_PROTECTION0; + __IO uint32_t RRAM_WRITE_PROTECTION1; + __IO uint32_t RRAM_WRITE_PROTECTION2; + __IO uint32_t RRAM_WRITE_PROTECTION3; + __IO uint32_t RRAM_WRITE_PROTECTION4; + __IO uint32_t RRAM_WRITE_PROTECTION5; + __IO uint32_t RRAM_WRITE_PROTECTION6; + __IO uint32_t RRAM_WRITE_PROTECTION7; + __IO uint32_t RRAM_STICKY_WRITE_PROTECTION0; + __IO uint32_t RRAM_STICKY_WRITE_PROTECTION1; + __IO uint32_t RRAM_STICKY_WRITE_PROTECTION2; + __IO uint32_t RRAM_STICKY_WRITE_PROTECTION3; + __IO uint32_t RRAM_STICKY_WRITE_PROTECTION4; + __IO uint32_t RRAM_STICKY_WRITE_PROTECTION5; + __IO uint32_t RRAM_STICKY_WRITE_PROTECTION6; + __IO uint32_t RRAM_STICKY_WRITE_PROTECTION7; + __I uint32_t RRAM_STICKY_WRITE_PROTECTION_STATUS0; + __I uint32_t RRAM_STICKY_WRITE_PROTECTION_STATUS1; + __I uint32_t RRAM_STICKY_WRITE_PROTECTION_STATUS2; + __I uint32_t RRAM_STICKY_WRITE_PROTECTION_STATUS3; + __I uint32_t RRAM_STICKY_WRITE_PROTECTION_STATUS4; + __I uint32_t RRAM_STICKY_WRITE_PROTECTION_STATUS5; + __I uint32_t RRAM_STICKY_WRITE_PROTECTION_STATUS6; + __I uint32_t RRAM_STICKY_WRITE_PROTECTION_STATUS7; + __IO uint32_t RRAM_STICKY_READ_PROTECTION0; + __I uint32_t RRAM_STICKY_READ_PROTECTION_STATUS0; + __IO uint32_t PROT_BITS_SET0; + __IO uint32_t PROT_BITS_SET1; + __I uint32_t PROT_BITS_STAT0; + __I uint32_t PROT_BITS_STAT1; + __IO uint32_t QSPI_STICKY_WRITE_PROTECTION0; + __IO uint32_t QSPI_STICKY_WRITE_PROTECTION1; + __I uint32_t QSPI_STICKY_WRITE_PROTECTION_STATUS0; + __I uint32_t QSPI_STICKY_WRITE_PROTECTION_STATUS1; + __IO uint32_t PDSN; + __I uint32_t CALCOUNTRC; + __IO uint32_t SECURE_DEBUG_CTRL; + __I uint32_t SECURE_DEBUG_STAT; + uint32_t RESERVED0[945]; + __I uint32_t CHIPID1; + __I uint32_t CHIPID2; + __I uint32_t CHIPREV; + __I uint32_t CORE_ID; +} CMSDK_AT_APB_WRPR_PINS_TypeDef; + +/*---------- AT_APB_UART ----------*/ +typedef struct { + __IO uint32_t DATA; + __IO uint32_t STATE; + __IO uint32_t CTRL; + union { + __IO uint32_t INTSTATUS_CLEAR; + __I uint32_t INTSTATUS; + __O uint32_t INTCLEAR; + }; + __IO uint32_t BAUDDIV; + __IO uint32_t RX_LWM; + __IO uint32_t TX_LWM; + __I uint32_t RX_FIFO_SPACES; + __I uint32_t TX_FIFO_SPACES; + __IO uint32_t HW_FLOW_OVRD; + __IO uint32_t BAUD_RATE_DETECT; + __IO uint32_t BAUD_DIV_CEIL; + __I uint32_t BRD_STAT; + __IO uint32_t INTMASK; + __I uint32_t RX_FIFO_ENTRIES; + union { + __IO uint32_t INTSTATUS_SET; + __IO uint32_t INTSET; + }; + uint32_t RESERVED0[996]; + __I uint32_t PID4; + __I uint32_t PID5; + __I uint32_t PID6; + __I uint32_t PID7; + __I uint32_t PID0; + __I uint32_t PID1; + __I uint32_t PID2; + __I uint32_t PID3; + __I uint32_t CID0; + __I uint32_t CID1; + __I uint32_t CID2; + __I uint32_t CID3; +} CMSDK_AT_APB_UART_TypeDef; + +/*---------- AT_APB_PWM ----------*/ +typedef struct { + __IO uint32_t PWM_CTRL; + __IO uint32_t PWM0_CTRL; + __IO uint32_t PWM0_DUR; + __IO uint32_t PWM0_CFG; + __IO uint32_t PWM1_CTRL; + __IO uint32_t PWM1_DUR; + __IO uint32_t PWM1_CFG; + __IO uint32_t PWM2_CTRL; + __IO uint32_t PWM2_DUR; + __IO uint32_t PWM2_CFG; + __IO uint32_t PWM3_CTRL; + __IO uint32_t PWM3_DUR; + __IO uint32_t PWM3_CFG; + __IO uint32_t PWM4_CTRL; + __IO uint32_t PWM4_DUR; + __IO uint32_t PWM4_CFG; + __IO uint32_t PWM5_CTRL; + __IO uint32_t PWM5_DUR; + __IO uint32_t PWM5_CFG; + __IO uint32_t PWM6_CTRL; + __IO uint32_t PWM6_DUR; + __IO uint32_t PWM6_CFG; + __IO uint32_t PWM7_CTRL; + __IO uint32_t PWM7_DUR; + __IO uint32_t PWM7_CFG; + __I uint32_t FSM_STATE; + __IO uint32_t FIFO_CFG; + __IO uint32_t FIFO_CARRIER1_DUR; + __IO uint32_t FIFO_CARRIER2_DUR; + __I uint32_t FIFO_STAT; + __I uint32_t FIFO_STAT1; + __IO uint32_t FIFO_SEL_ERR_SOURCE; + __I uint32_t INTERRUPTS; + __IO uint32_t INTERRUPTS_MASK; + __IO uint32_t INTERRUPTS_CLEAR; + __IO uint32_t INTERRUPTS_SET; + uint32_t RESERVED0[984]; + __IO uint32_t FIFO_DATA; + __I uint32_t CORE_ID; + __I uint32_t REV_HASH; + __I uint32_t REV_KEY; +} CMSDK_AT_APB_PWM_TypeDef; + +/*---------- AT_APB_SPI ----------*/ +typedef struct { + __IO uint32_t CTRL; + __IO uint32_t TRANSACTION_SETUP; + __IO uint32_t TRANSACTION_SETUP_DMA; + __I uint32_t TRANSACTION_STATUS; + __IO uint32_t DATA_BYTES_LOWER; + __IO uint32_t DATA_BYTES_UPPER; + __IO uint32_t INTERRUPT_MASK; + __I uint32_t INTERRUPT_STATUS; + __IO uint32_t SET_INTERRUPT; + __IO uint32_t RESET_INTERRUPT; + uint32_t RESERVED0[1013]; + __I uint32_t CORE_ID; +} CMSDK_AT_APB_SPI_TypeDef; + +/*---------- AT_APB_KSM ----------*/ +typedef struct { + __IO uint32_t CTRL0; + __IO uint32_t TIME_PARAM0; + __IO uint32_t TIME_PARAM1; + __IO uint32_t MATRIX_SIZE; + uint32_t RESERVED0[12]; + __I uint32_t KEYBOARD_PACKET; + __I uint32_t LOW_POWER; + uint32_t RESERVED1[4]; + __IO uint32_t LPBACK_KSI; + uint32_t RESERVED2[9]; + __I uint32_t STATUS; + uint32_t RESERVED3[15]; + __I uint32_t INTERRUPTS; + __IO uint32_t INTERRUPT_MASK; + __IO uint32_t INTERRUPT_CLEAR; + uint32_t RESERVED4[970]; + __I uint32_t DEBUG; + __I uint32_t DEBUG2; + __I uint32_t CORE_ID; +} CMSDK_AT_APB_KSM_TypeDef; + +/*---------- AT_APB_QDEC ----------*/ +typedef struct { + __IO uint32_t SETUP_FOR_AXIS_0; + __I uint32_t ACCUM_PURGE_STATUS_FOR_AXIS_0; + __I uint32_t ACCUMULATOR_VALUE_FOR_AXIS_0; + __I uint32_t ERR_PURGE_STATUS_FOR_AXIS_0; + __I uint32_t ERROR_COUNT_FOR_AXIS_0; + __IO uint32_t SETUP_FOR_AXIS_1; + __I uint32_t ACCUM_PURGE_STATUS_FOR_AXIS_1; + __I uint32_t ACCUMULATOR_VALUE_FOR_AXIS_1; + __I uint32_t ERR_PURGE_STATUS_FOR_AXIS_1; + __I uint32_t ERROR_COUNT_FOR_AXIS_1; + __IO uint32_t SETUP_FOR_AXIS_2; + __I uint32_t ACCUM_PURGE_STATUS_FOR_AXIS_2; + __I uint32_t ACCUMULATOR_VALUE_FOR_AXIS_2; + __I uint32_t ERR_PURGE_STATUS_FOR_AXIS_2; + __I uint32_t ERROR_COUNT_FOR_AXIS_2; + uint32_t RESERVED0[1008]; + __I uint32_t CORE_ID; +} CMSDK_AT_APB_QDEC_TypeDef; + +/*---------- AT_APB_SLWTIMER ----------*/ +typedef struct { + __IO uint32_t CONTROL; + __IO uint32_t INIT_LOW; + __IO uint32_t INIT_HIGH; + __I uint32_t CNT_LOW; + __I uint32_t CNT_HIGH; + __IO uint32_t THRES0_LOW; + __IO uint32_t THRES0_HIGH; + __IO uint32_t THRES1_LOW; + __IO uint32_t THRES1_HIGH; + __IO uint32_t THRES2_LOW; + __IO uint32_t THRES2_HIGH; + __I uint32_t STATUS; + __I uint32_t INTERRUPT_STATUS; + __IO uint32_t INTERRUPT_MASK; + uint32_t RESERVED0[1009]; + __I uint32_t CORE_ID; +} CMSDK_AT_APB_SLWTIMER_TypeDef; + +/*---------- AT_APB_QSPI ----------*/ +typedef struct { + __IO uint32_t TRANSACTION_SETUP; + __I uint32_t READ_DATA; + __IO uint32_t OVERRIDE_DIN; + __IO uint32_t MODE; + __IO uint32_t REMOTE_AHB_SETUP; + __IO uint32_t REMOTE_AHB_SETUP_2; + __IO uint32_t REMOTE_AHB_SETUP_3; + __IO uint32_t REMOTE_AHB_SETUP_4; + __IO uint32_t REMOTE_AHB_SETUP_5; + __IO uint32_t REMOTE_AHB_SETUP_6; + __IO uint32_t REMOTE_AHB_SETUP_7; + __I uint32_t REMOTE_AHB_WLE_CNT; + __I uint32_t REMOTE_AHB_WIP_CNT; + __I uint32_t REMOTE_AHB_DBG0; + __I uint32_t REMOTE_AHB_DBG1; + __I uint32_t REMOTE_AHB_DBG2; + uint32_t RESERVED0[1007]; + __I uint32_t CORE_ID; +} CMSDK_AT_APB_QSPI_TypeDef; + +/*---------- AT_APB_I2C ----------*/ +typedef struct { + __IO uint32_t TRANSACTION_SETUP; + __IO uint32_t CLOCK_CONTROL; + __IO uint32_t OUTGOING_DATA; + __IO uint32_t OUTGOING_DATA1; + __IO uint32_t IO_CTRL; + __I uint32_t INCOMING_DATA; + __I uint32_t INCOMING_DATA1; + __I uint32_t TRANSACTION_STATUS; + __IO uint32_t INTERRUPT_MASK; + __I uint32_t INTERRUPT_STATUS; + __IO uint32_t SET_INTERRUPT; + __IO uint32_t RESET_INTERRUPT; + uint32_t RESERVED0[1011]; + __I uint32_t ID; +} CMSDK_AT_APB_I2C_TypeDef; + +/*---------- AT_APB_TSMC_NVM ----------*/ +typedef struct { + __IO uint32_t OPMODE; + __IO uint32_t CTRL; + __IO uint32_t DATA0; + __IO uint32_t DATA1; + __I uint32_t STATUS; + __IO uint32_t T_SP_VQ; + __IO uint32_t T_HP_VQ; + __IO uint32_t T_SP_PG; + __IO uint32_t T_HP_PG; + __IO uint32_t T_HP_CK; + __IO uint32_t T_S_PGM; + __IO uint32_t T_H_PGM; + __IO uint32_t T_CKHP; + __IO uint32_t T_CKLP; + __IO uint32_t T_SPS_CK; + __IO uint32_t T_SR_CK; + __IO uint32_t T_HR_CK; + __IO uint32_t T_CKLR; + __IO uint32_t T_CKHR; + __IO uint32_t T_SRS_CK; + __I uint32_t INTERRUPT_STATUS; + __IO uint32_t INTERRUPT_MASK; + __IO uint32_t INTERRUPT_SET; + __IO uint32_t INTERRUPT_RESET; + uint32_t RESERVED0[999]; + __I uint32_t CORE_ID; +} CMSDK_AT_APB_TSMC_NVM_TypeDef; + +/*---------- AT_APB_WRPR_SHORT ----------*/ +typedef struct { + __IO uint32_t APB0_CTRL; + __IO uint32_t APB1_CTRL; + __IO uint32_t APB2_CTRL; + __IO uint32_t APB3_CTRL; + __IO uint32_t APB4_CTRL; + __IO uint32_t APB5_CTRL; + __IO uint32_t APB6_CTRL; + __IO uint32_t APB7_CTRL; + __IO uint32_t APB8_CTRL; + __IO uint32_t APB9_CTRL; + __IO uint32_t APB10_CTRL; + __IO uint32_t APB11_CTRL; + __IO uint32_t APB12_CTRL; + __IO uint32_t APB13_CTRL; + __IO uint32_t APB14_CTRL; + __IO uint32_t APB15_CTRL; + uint32_t RESERVED0[1007]; + __I uint32_t CORE_ID; +} CMSDK_AT_APB_WRPR_SHORT_TypeDef; + +/*---------- RIF ----------*/ +typedef struct { + __IO uint32_t BIAS; + __IO uint32_t RXBBF; + __IO uint32_t RXBBF_1M; + __IO uint32_t RXBBF_2M; + __IO uint32_t SYNTX_MODGAIN; + __IO uint32_t SYNTX_VCOCAP; + __IO uint32_t LNA; + __IO uint32_t RGT; + __IO uint32_t RGTHW; + __IO uint32_t TXGAIN0; + __IO uint32_t TXGAIN1; + __IO uint32_t TXGAIN2; + __IO uint32_t TXGAIN3; + __IO uint32_t RXGAIN0; + __IO uint32_t RXGAIN1; + __IO uint32_t RXGAIN2; + __IO uint32_t RXGAIN3; + __IO uint32_t RXGAIN4; + __IO uint32_t RXGAIN5; + __IO uint32_t RXGAIN6; + __IO uint32_t RXGAIN7; + __IO uint32_t RXGAIN8; + __IO uint32_t RXGAIN9; + __IO uint32_t RXGAIN10; + __IO uint32_t RXGAIN11; + __IO uint32_t RXGAIN12; + __IO uint32_t RXGAIN13; + __IO uint32_t RXGAIN14; + __IO uint32_t RXGAIN15; + __IO uint32_t SYNTX_CAL; + __IO uint32_t SYNTX0; + __IO uint32_t SYNTX1; + __IO uint32_t SYNTX2; + __IO uint32_t SYNTX3; + __IO uint32_t SYNTX4; + __IO uint32_t SYNTX5; + __IO uint32_t DUTY_CYCLE; + __IO uint32_t TXGAIN0_PMU; + __IO uint32_t TXGAIN1_PMU; + __IO uint32_t TXGAIN2_PMU; + __IO uint32_t RX0; + __IO uint32_t TIMER0; + __IO uint32_t TIMER1; + __IO uint32_t TIMER2; + __IO uint32_t TIMER3; + __IO uint32_t HADM_TIMER0; + __IO uint32_t HADM_TIMER1; + __IO uint32_t HADM_TIMER2; + __IO uint32_t HADM_TIMER3; + __IO uint32_t RXDC7; + __IO uint32_t SYNTH_CHAN0; + __IO uint32_t SYNTH_CHAN1; + __IO uint32_t SYNTH_CHAN2; + __IO uint32_t SYNTH_CHAN3; + __IO uint32_t SYNTH_CHAN4; + __IO uint32_t SYNTH_CHAN5; + __IO uint32_t ADC_CNTL; + __IO uint32_t MODE_CNTL; + __IO uint32_t MODE_CNTL2; + __IO uint32_t XLNA_XPA_CNTL; + __IO uint32_t CAL_CNTL; + __I uint32_t CAL_DONE; + uint32_t RESERVED0[961]; + __I uint32_t ID; +} CMSDK_RIF_TypeDef; + +/*---------- MDM ----------*/ +typedef struct { + __IO uint32_t AGCMEAS; + __IO uint32_t AGCGAIN; + __IO uint32_t DCOFF; + __IO uint32_t TIA_FORCE_DCCALRESULTS; + __IO uint32_t TIA_FORCE_DCCALRESULTS2; + __IO uint32_t TIA_LP_FORCE_DCCALRESULTS; + __IO uint32_t TIA_LP_FORCE_DCCALRESULTS2; + __IO uint32_t PGA_FORCE_DCCALRESULTS; + __IO uint32_t PGA_FORCE_DCCALRESULTS2; + __IO uint32_t PGA_LP_FORCE_DCCALRESULTS; + __IO uint32_t PGA_LP_FORCE_DCCALRESULTS2; + __IO uint32_t NOTCH_FORCE_DCCALRESULTS; + __IO uint32_t PGA_CAL_GAIN_FORCE_DCCALRESULTS; + __IO uint32_t PGA_CAL_GAIN_FORCE_DCCALRESULTS2; + __IO uint32_t IQCORR; + __IO uint32_t AGCMEAS_ALT; + __IO uint32_t AGCGAIN_ALT; + __IO uint32_t XLNA; + __IO uint32_t XLNA_ALT; + __IO uint32_t AGCSAT; + __IO uint32_t AGCSAT_ALT; + __IO uint32_t BASELINE; + __IO uint32_t BASELINE_ALT; + __IO uint32_t MARGIN; + __IO uint32_t MARGIN_ALT; + __IO uint32_t PWRSTEP; + __IO uint32_t PWRSTEP_ALT; + __IO uint32_t AGCPWR; + __IO uint32_t AGCPWR_ALT; + __IO uint32_t AGCPWR2; + __IO uint32_t AGCPWR2_ALT; + __IO uint32_t AGCTIME; + __IO uint32_t AGCTIME_ALT; + __IO uint32_t TWOMEG_AGCTIME; + __IO uint32_t TWOMEG_AGCTIME_ALT; + __IO uint32_t AGCTIME2; + __IO uint32_t AGCTIME2_ALT; + __IO uint32_t AGCCNTL; + __IO uint32_t AGCCNTL_ALT; + __IO uint32_t AGCPD; + __IO uint32_t AGCPD_ALT; + __IO uint32_t AGCDET; + __IO uint32_t AGCDET_ALT; + __IO uint32_t AGCOFFSET; + __IO uint32_t AGCOFFSET_ALT; + __IO uint32_t SYNCH; + __IO uint32_t SYNCH_ALT; + __IO uint32_t TIMETRACK; + __IO uint32_t TIMESYNC; + __IO uint32_t TIMESYNC_ALT; + __IO uint32_t SYNCDEMOD; + __IO uint32_t SYNCDEMOD_ALT; + __IO uint32_t RESETINITCFO; + __IO uint32_t RESETINITCFO_ALT; + __IO uint32_t INTMFREQ; + __IO uint32_t INTMFREQ_ALT; + __IO uint32_t TSTIMEOUT; + __IO uint32_t DEMOD; + __IO uint32_t DFEWITHFFE; + __IO uint32_t DFEWITHOUTFFE; + __IO uint32_t TWOMEG_DFEWITHFFE; + __IO uint32_t TWOMEG_DFEWITHOUTFFE; + __IO uint32_t FREQ; + __IO uint32_t FREQLIM; + __IO uint32_t LR; + __IO uint32_t LR_ALT; + __IO uint32_t MIXER; + __IO uint32_t ACCESS_ADDRESS; + __IO uint32_t MODE; + __IO uint32_t DCCAL; + __IO uint32_t DCCAL2; + __IO uint32_t DCCAL_CTRL; + __IO uint32_t TIA_DCCAL; + __IO uint32_t TIA_DCCAL2; + __IO uint32_t TIA_DCCAL3; + __IO uint32_t TIA_DCCAL4; + __IO uint32_t PGA_DCCAL; + __IO uint32_t PGA_DCCAL2; + __IO uint32_t PGA_DCCAL3; + __IO uint32_t PGA_DCCAL4; + __IO uint32_t PGA_DCCAL5; + __IO uint32_t NOTCH_DCCAL; + __IO uint32_t NOTCH_DCCAL2; + __IO uint32_t NOTCH_DCCAL3; + __IO uint32_t DCOFFTRK; + __IO uint32_t DCOFFTRK_ALT; + __IO uint32_t DCOFFTRK2; + __IO uint32_t DCOFFTRK2_ALT; + __IO uint32_t DFCNTL; + __IO uint32_t DFCNTL_ALT; + __IO uint32_t SWANTCTETIME; + __IO uint32_t DFTABLE; + __I uint32_t DFSTATUS; + __IO uint32_t ANTRX3TO0; + __IO uint32_t ANTTX3TO0; + __IO uint32_t ANTRX7TO4; + __IO uint32_t ANTTX7TO4; + __IO uint32_t ANTIDLE; + __IO uint32_t ANTID3TO0; + __IO uint32_t ANTID7TO4; + __IO uint32_t WHT_CTRL; + __I uint32_t DCCALRESULTS; + __I uint32_t DCCALRESULTS2; + __I uint32_t TIA_RETENT_DCCALRESULTS; + __I uint32_t TIA_DCCALRESULTS2; + __I uint32_t TIA_DCCALRESULTS3; + __I uint32_t TIA_LP_RETENT_DCCALRESULTS; + __I uint32_t TIA_LP_DCCALRESULTS2; + __I uint32_t PGA_RETENT_DCCALRESULTS; + __I uint32_t PGA_DCCALRESULTS2; + __I uint32_t PGA_DCCALRESULTS3; + __I uint32_t PGA_LP_RETENT_DCCALRESULTS; + __I uint32_t PGA_LP_DCCALRESULTS2; + __I uint32_t NOTCH_RETENT_DCCALRESULTS; + __I uint32_t NOTCH_DCCALRESULTS2; + __I uint32_t AGCSTATUS; + __I uint32_t MEASFREQ; + __IO uint32_t EXPER; + __IO uint32_t SPARE0; + __IO uint32_t DEBUG; + __IO uint32_t LC2LC; + __I uint32_t IRQ; + __IO uint32_t IRQM; + __IO uint32_t IRQC; + __IO uint32_t ERR_INJ; + __IO uint32_t DEBUG32; + __IO uint32_t DUO; + uint32_t RESERVED0[896]; + __I uint32_t CORE_ID; +} CMSDK_MDM_TypeDef; + +/*---------- AT_APB_PSEQ_PARIS ----------*/ +typedef struct { + __IO uint32_t CTRL0; + __IO uint32_t CTRL1; + __IO uint32_t RETAIN_ALL_WAKE_MASK; + __IO uint32_t HIB_WAKE_MASK; + __IO uint32_t BLE_RET_TO_BLE_ACT_WAKE_MASK; + __IO uint32_t BLE_RET_TO_CPU_ACT_WAKE_MASK; + __IO uint32_t GPIO_WAKE_MASK; + __IO uint32_t GPIO_WAKE_TYPE; + __IO uint32_t GPIO_WAKE_POL; + __IO uint32_t GPIO_WAKE_BOTH_EDGES; + __I uint32_t GPIO_WAKE_STATUS; + __IO uint32_t WURX_CONFIG; + __IO uint32_t WURX_CONFIG1; + __IO uint32_t WURX_CONFIG2; + __IO uint32_t GADC_CONFIG; + __IO uint32_t XTAL_BITS0; + __IO uint32_t XTAL_BITS1; + __IO uint32_t OVERRIDES; + __IO uint32_t OVERRIDES2; + __IO uint32_t OVERRIDES3; + __IO uint32_t OVERRIDES4; + __IO uint32_t OVERRIDES5; + __IO uint32_t SYSRAM_OVERRIDES; + __IO uint32_t SYSRAM_OVERRIDES2; + __IO uint32_t SYSRAM_OVERRIDES3; + __IO uint32_t SYSRAM_OVERRIDES4; + __IO uint32_t SYSRAM_OVERRIDES5; + __IO uint32_t SYSRAM_OVERRIDES6; + __IO uint32_t SYSRAM_OVERRIDES7; + __IO uint32_t SYSRAM_OVERRIDES8; + __IO uint32_t EMRAM_OVERRIDES; + __IO uint32_t EMRAM_OVERRIDES2; + __IO uint32_t EMRAM_OVERRIDES3; + __IO uint32_t EMRAM_OVERRIDES4; + __IO uint32_t EMRAM_OVERRIDES5; + __IO uint32_t EMRAM_OVERRIDES6; + __IO uint32_t EMRAM_OVERRIDES7; + __IO uint32_t EMRAM_OVERRIDES8; + __IO uint32_t ICACHE_OVERRIDES; + __IO uint32_t ICACHE_OVERRIDES2; + __IO uint32_t ICACHE_OVERRIDES3; + __IO uint32_t ICACHE_OVERRIDES4; + __IO uint32_t ICACHE_OVERRIDES5; + __IO uint32_t ICACHE_OVERRIDES6; + __IO uint32_t ICACHE_OVERRIDES7; + __IO uint32_t ICACHE_OVERRIDES8; + __IO uint32_t RRAMCACHE_OVERRIDES; + __IO uint32_t RRAMCACHE_OVERRIDES2; + __IO uint32_t RRAMCACHE_OVERRIDES3; + __IO uint32_t RRAMCACHE_OVERRIDES4; + __IO uint32_t RRAMCACHE_OVERRIDES5; + __IO uint32_t RRAMCACHE_OVERRIDES6; + __IO uint32_t RRAMCACHE_OVERRIDES7; + __IO uint32_t RRAMCACHE_OVERRIDES8; + __IO uint32_t QSPICACHE_OVERRIDES; + __IO uint32_t COUNTER_CONTROL; + __I uint32_t CURRENT_REAL_TIME; + __I uint32_t CURRENT_COUNT_DOWN_TIME; + __IO uint32_t INIT_COUNT_DOWN; + __I uint32_t INST_PENDING; + __I uint32_t STATUS; + __IO uint32_t PERSISTENT0; + __IO uint32_t PERSISTENT1; + __IO uint32_t PERSISTENT2; + __IO uint32_t PERSISTENT3; + __IO uint32_t PERSISTENT4; + __IO uint32_t PERSISTENT5; + __IO uint32_t PERSISTENT6; + __IO uint32_t PERSISTENT7; + __IO uint32_t SENSOR_HUB_CONTROL; + __IO uint32_t KSMQDEC_CONTROL; + __IO uint32_t SPII2C_CONTROL; + __IO uint32_t FLASH_CONTROL; + __IO uint32_t FLASH_CONTROL2; + __I uint32_t PMU_STATUS; + __IO uint32_t PMU_INTERRUPT; + __IO uint32_t SYSRAM_WRITE_BLOCK_CFG; + __IO uint32_t SYSRAM_SSRS_CFG; + __I uint32_t INTERRUPT_STATUS; + __IO uint32_t INTERRUPT_MASK; + __IO uint32_t RESET_INTERRUPT; + __IO uint32_t FPGA_CFG; + __IO uint32_t PLL; + __I uint32_t RADIO_STATUS; + __I uint32_t RRAM_READ_CONFIG_LO; + __I uint32_t RRAM_READ_CONFIG_HI; + __IO uint32_t SENSOR_HUB_IMM_BREAKOUT_MASK; + __IO uint32_t FSM_TUNINGA; + __IO uint32_t FSM_TUNINGB; + __IO uint32_t WDOG_CONTROL; + __I uint32_t WDOG_TIMER; + uint32_t RESERVED0[932]; + __I uint32_t CORE_ID; +} CMSDK_AT_APB_PSEQ_PARIS_TypeDef; + +/*---------- AT_APB_SWD ----------*/ +typedef struct { + __IO uint32_t DAP_ADDR_CTRL; + __IO uint32_t DAP_WDATA_CTRL; + __IO uint32_t SWD_CLK_DIV_CTRL; + __IO uint32_t PATTERN_UPPER_CTRL; + __IO uint32_t PATTERN_LOWER_CTRL; + __IO uint32_t TAIL_DUR; + __IO uint32_t PATTERN_DUR; + __I uint32_t DAP_BRIDGE_STATUS; + __I uint32_t DAP_RESP_STATUS; + __IO uint32_t RW_CTRL; + __IO uint32_t APNDP_CTRL; + __IO uint32_t TRIGGER_CTRL; + __I uint32_t DAP_RDATA; + __IO uint32_t INTERRUPT_MASK; + __I uint32_t INTERRUPT_STATUS; + __IO uint32_t SET_INTERRUPT; + __IO uint32_t RESET_INTERRUPT; + __IO uint32_t DTOP_BYPASS_CTRL; + __I uint32_t DTOP_BYPASS_STAT; + __IO uint32_t DTOP_BYPASS_GPO; + __IO uint32_t DTOP_BYPASS_RIF_MODE_CNTL; + __IO uint32_t DTOP_BYPASS_RIF_CAL_CNTL; + __IO uint32_t DTOP_BYPASS_RIF_RXDC7; + uint32_t RESERVED0[1000]; + __I uint32_t CORE_ID; +} CMSDK_AT_APB_SWD_TypeDef; + +/*---------- AT_APB_GADC ----------*/ +typedef struct { + __IO uint32_t CTRL; + __IO uint32_t CTRL1; + __IO uint32_t CH1_DATAPATH_CONFIG; + __IO uint32_t CH2_DATAPATH_CONFIG; + __IO uint32_t CH3_DATAPATH_CONFIG; + __IO uint32_t CH4_DATAPATH_CONFIG; + __IO uint32_t CH5_DATAPATH_CONFIG; + __IO uint32_t CH6_DATAPATH_CONFIG; + __IO uint32_t CH7_DATAPATH_CONFIG; + __IO uint32_t CH8_DATAPATH_CONFIG; + __IO uint32_t CH9_DATAPATH_CONFIG; + __IO uint32_t CH10_DATAPATH_CONFIG; + __IO uint32_t CH11_DATAPATH_CONFIG; + __IO uint32_t CH12_DATAPATH_CONFIG; + __IO uint32_t GAIN_CONFIG0; + __IO uint32_t GAIN_CONFIG1; + __I uint32_t DATAPATH_OUTPUT; + __I uint32_t INTERRUPTS; + __IO uint32_t INTERRUPT_MASK; + __IO uint32_t INTERRUPT_CLEAR; + __I uint32_t FIFO_DBG; + uint32_t RESERVED0[1002]; + __I uint32_t CORE_ID; +} CMSDK_AT_APB_GADC_TypeDef; + +/*---------- AT_APB_TRNG ----------*/ +typedef struct { + __IO uint32_t CONTROL; + __I uint32_t STATUS; + __I uint32_t INTERRUPT_STATUS; + __IO uint32_t INTERRUPT_MASK; + __IO uint32_t SET_INTERRUPT; + __IO uint32_t RESET_INTERRUPT; + __I uint32_t TRNG; + uint32_t RESERVED0[1016]; + __I uint32_t CORE_ID; +} CMSDK_AT_APB_TRNG_TypeDef; + +/*---------- AT_APB_RCOS_CAL ----------*/ +typedef struct { + __IO uint32_t CAL_CTRL; + __IO uint32_t SLOW_CLK_SET; + __I uint32_t SLOW_CLK_CNT; + __I uint32_t FAST_CLK_CNT; + __IO uint32_t SOURCE_CLK_SEL; + __IO uint32_t FORCE_RESET; + __I uint32_t STAT; + __I uint32_t INTERRUPT_STATUS; + __IO uint32_t INTERRUPT_MASK; + __IO uint32_t SET_INTERRUPT; + __IO uint32_t RESET_INTERRUPT; + uint32_t RESERVED0[1012]; + __I uint32_t CORE_ID; +} CMSDK_AT_APB_RCOS_CAL_TypeDef; + +/*---------- AT_APB_SHUB ----------*/ +typedef struct { + __IO uint32_t SETUP0; + __IO uint32_t SETUP1; + __IO uint32_t PORT0_SETUP; + __IO uint32_t PORT0_SENSOR0_SETUP; + __IO uint32_t PORT0_SENSOR1_SETUP; + __IO uint32_t PORT0_SENSOR2_SETUP; + __IO uint32_t PORT0_SENSOR3_SETUP; + __IO uint32_t PORT0_SENSOR4_SETUP; + __IO uint32_t PORT0_SENSOR5_SETUP; + __IO uint32_t PORT0_SENSOR6_SETUP; + __IO uint32_t PORT0_SENSOR7_SETUP; + __IO uint32_t PORT0_SPI_ENG0_CTRL; + __IO uint32_t PORT0_I2C_IDW_0; + __IO uint32_t PORT0_I2C_IDW_1; + __IO uint32_t PORT0_I2C_IDW_2; + __IO uint32_t PORT0_I2C_IDW_3; + __IO uint32_t PORT0_I2C_IDW_4; + __IO uint32_t PORT0_I2C_IDW_5; + __IO uint32_t PORT0_I2C_IDW_6; + __IO uint32_t PORT0_I2C_IDW_7; + __IO uint32_t PORT0_I2C_ADDR_0; + __IO uint32_t PORT0_I2C_ADDR_1; + __IO uint32_t PORT0_I2C_ADDR_2; + __IO uint32_t PORT0_I2C_ADDR_3; + __IO uint32_t PORT0_I2C_ADDR_4; + __IO uint32_t PORT0_I2C_ADDR_5; + __IO uint32_t PORT0_I2C_ADDR_6; + __IO uint32_t PORT0_I2C_ADDR_7; + __IO uint32_t PORT0_I2C_IDR_0; + __IO uint32_t PORT0_I2C_IDR_1; + __IO uint32_t PORT0_I2C_IDR_2; + __IO uint32_t PORT0_I2C_IDR_3; + __IO uint32_t PORT0_I2C_IDR_4; + __IO uint32_t PORT0_I2C_IDR_5; + __IO uint32_t PORT0_I2C_IDR_6; + __IO uint32_t PORT0_I2C_IDR_7; + __IO uint32_t PORT0_I2C_DAT_CTRL; + __IO uint32_t PORT0_I2C_DAT_LAST_CTRL; + __IO uint32_t PORT0_ALM0_QUAN_CTRL; + __IO uint32_t PORT0_ALM1_QUAN_CTRL; + __IO uint32_t PORT0_ALM0_TRIG_CTRL; + __IO uint32_t PORT0_ALM1_TRIG_CTRL; + __IO uint32_t PORT0_ALM0_THRHLD_MAX_0; + __IO uint32_t PORT0_ALM0_THRHLD_MAX_1; + __IO uint32_t PORT0_ALM0_THRHLD_MAX_2; + __IO uint32_t PORT0_ALM0_THRHLD_MIN_0; + __IO uint32_t PORT0_ALM0_THRHLD_MIN_1; + __IO uint32_t PORT0_ALM0_THRHLD_MIN_2; + __IO uint32_t PORT0_ALM1_THRHLD_MAX_0; + __IO uint32_t PORT0_ALM1_THRHLD_MAX_1; + __IO uint32_t PORT0_ALM1_THRHLD_MAX_2; + __IO uint32_t PORT0_ALM1_THRHLD_MIN_0; + __IO uint32_t PORT0_ALM1_THRHLD_MIN_1; + __IO uint32_t PORT0_ALM1_THRHLD_MIN_2; + __I uint32_t PORT0_STATUS; + __IO uint32_t PORT1_SETUP; + __IO uint32_t PORT1_SENSOR0_SETUP; + __IO uint32_t PORT1_SPI_ENG0_CTRL; + __IO uint32_t PORT1_I2C_IDW_0; + __IO uint32_t PORT1_I2C_ADDR_0; + __IO uint32_t PORT1_I2C_IDR_0; + __IO uint32_t PORT1_I2C_DAT_CTRL; + __IO uint32_t PORT1_I2C_DAT_LAST_CTRL; + __IO uint32_t PORT1_ALM0_QUAN_CTRL; + __IO uint32_t PORT1_ALM0_TRIG_CTRL; + __IO uint32_t PORT1_ALM0_THRHLD_MAX_0; + __IO uint32_t PORT1_ALM0_THRHLD_MAX_1; + __IO uint32_t PORT1_ALM0_THRHLD_MAX_2; + __IO uint32_t PORT1_ALM0_THRHLD_MIN_0; + __IO uint32_t PORT1_ALM0_THRHLD_MIN_1; + __IO uint32_t PORT1_ALM0_THRHLD_MIN_2; + __I uint32_t PORT1_STATUS; + __IO uint32_t FLASH_CTRL0; + __IO uint32_t FLASH_CTRL1; + __IO uint32_t FLASH_CTRL2; + __IO uint32_t FLASH_CTRL3; + __IO uint32_t FLASH_CTRL4; + __I uint32_t FLASH_STATUS0; + __I uint32_t FLASH_STATUS1; + __I uint32_t SHUB_STATUS0; + __IO uint32_t PC_CTRL; + __IO uint32_t PC_CTRL2; + __I uint32_t REG7; + __IO uint32_t SHUB_SRAM_CLK_SEL; + __IO uint32_t REGFILE_SEL; + __IO uint32_t REGFILE_REGW; + uint32_t RESERVED0[937]; + __I uint32_t ID; +} CMSDK_AT_APB_SHUB_TypeDef; + +/*---------- AT_APB_PDM ----------*/ +typedef struct { + __IO uint32_t CONTROL; + __IO uint32_t FILTER_CONFIG; + __IO uint32_t FILTER_CONFIG1; + __IO uint32_t GAIN_CONTROL_CONFIG; + __I uint32_t PCM_SAMPLE; + __I uint32_t FIFO_DEBUG; + __I uint32_t INTERRUPTS; + __IO uint32_t INTERRUPT_MASK; + __IO uint32_t INTERRUPT_CLEAR; + __IO uint32_t BUFFER_ACCESS_MODE; + __I uint32_t AUTO_COUNTER; + __I uint32_t BUFFER_DEPTH; + uint32_t RESERVED0[1009]; + __I uint32_t CORE_ID; + __I uint32_t REV_HASH; + __I uint32_t REV_KEY; +} CMSDK_AT_APB_PDM_TypeDef; + +/*---------- AT_I2S ----------*/ +typedef struct { + __IO uint32_t I2S_CTRL0; + __IO uint32_t I2S_CTRL1_TX; + __IO uint32_t I2S_CTRL1_RX; + __IO uint32_t I2S_CTRL2_TX; + __IO uint32_t I2S_CTRL2_RX; + __IO uint32_t I2S_CTRL3; + __IO uint32_t I2S_CTRL4; + __IO uint32_t I2S_CTRL5_TX; + __IO uint32_t I2S_CTRL5_RX; + __IO uint32_t I2S_INTRP_CTRL; + __I uint32_t I2S_PP1_RDATA; + __O uint32_t I2S_PP0_WDATA; + __IO uint32_t I2S_PP1_CTRL; + __IO uint32_t I2S_PP0_CTRL; + __I uint32_t I2S_IRQ0; + __IO uint32_t I2S_IRQM0; + __IO uint32_t I2S_IRQS0; + __IO uint32_t I2S_IRQC0; + __I uint32_t I2S_IRQ1; + __IO uint32_t I2S_IRQM1; + __IO uint32_t I2S_IRQS1; + __IO uint32_t I2S_IRQC1; + __I uint32_t BUFFER_DEPTH; + __I uint32_t PP_ST; + __IO uint32_t I2S_SPARE; + __IO uint32_t I2S_DBG; + uint32_t RESERVED0[997]; + __I uint32_t ID; +} CMSDK_AT_I2S_TypeDef; + +/*---------- AT_APB_CLKRSTGEN ----------*/ +typedef struct { + __IO uint32_t CLK_BP_CTRL; + __I uint32_t CLK_BP_CTRL_STAT; + __IO uint32_t CLK_AUD_CTRL; + __IO uint32_t PLL_CTRL; + __IO uint32_t USER_RESETS; + __IO uint32_t USER_CLK_DISABLES; + __IO uint32_t USER_CLK_GATE_FORCE_ON; + __IO uint32_t USER_CLK_GATE_CTRL; + __I uint32_t CONFIGURATION; + __IO uint32_t CLKSYNC; + uint32_t RESERVED0[1013]; + __I uint32_t CORE_ID; +} CMSDK_AT_APB_CLKRSTGEN_TypeDef; + +/*---------- AT_APB_AES ----------*/ +typedef struct { + __IO uint32_t ALERT_TEST; + __IO uint32_t KEY_SHARE0_0; + __IO uint32_t KEY_SHARE0_1; + __IO uint32_t KEY_SHARE0_2; + __IO uint32_t KEY_SHARE0_3; + __IO uint32_t KEY_SHARE0_4; + __IO uint32_t KEY_SHARE0_5; + __IO uint32_t KEY_SHARE0_6; + __IO uint32_t KEY_SHARE0_7; + __IO uint32_t KEY_SHARE1_0; + __IO uint32_t KEY_SHARE1_1; + __IO uint32_t KEY_SHARE1_2; + __IO uint32_t KEY_SHARE1_3; + __IO uint32_t KEY_SHARE1_4; + __IO uint32_t KEY_SHARE1_5; + __IO uint32_t KEY_SHARE1_6; + __IO uint32_t KEY_SHARE1_7; + __IO uint32_t IV_0; + __IO uint32_t IV_1; + __IO uint32_t IV_2; + __IO uint32_t IV_3; + __IO uint32_t DATA_IN_0; + __IO uint32_t DATA_IN_1; + __IO uint32_t DATA_IN_2; + __IO uint32_t DATA_IN_3; + __I uint32_t DATA_OUT_0; + __I uint32_t DATA_OUT_1; + __I uint32_t DATA_OUT_2; + __I uint32_t DATA_OUT_3; + __IO uint32_t CTRL_SHADOWED; + __IO uint32_t TRIGGER; + __I uint32_t STATUS; + uint32_t RESERVED0[989]; + __I uint32_t STATUS1; + __IO uint32_t SIDELOAD_CTRL; + __I uint32_t ID; +} CMSDK_AT_APB_AES_TypeDef; + +/*---------- AT_AHB_DMA ----------*/ +typedef struct { + __IO uint32_t OPMODE; + __IO uint32_t CONST_WDATA; + __IO uint32_t SRC_ADDR; + __IO uint32_t TAR_ADDR; + __IO uint32_t SIZE; + __IO uint32_t SRC_CTRL; + __IO uint32_t TAR_CTRL; + __IO uint32_t FIFO_DPTH_ADDR; + __IO uint32_t FIFO_PORT_SEL; + __IO uint32_t SPI_PORT_SEL; + __I uint32_t ERR_STAT; + __I uint32_t STATUS; + __I uint32_t TOTAL_WRITE_REMAINDER; + __I uint32_t INTERRUPT_STATUS; + __IO uint32_t INTERRUPT_MASK; + __IO uint32_t SET_INTERRUPT; + __IO uint32_t RESET_INTERRUPT; + __IO uint32_t CFG_HNONSEC; + __IO uint32_t CHAN1_OPMODE; + __IO uint32_t CHAN1_CONST_WDATA; + __IO uint32_t CHAN1_SRC_ADDR; + __IO uint32_t CHAN1_TAR_ADDR; + __IO uint32_t CHAN1_SIZE; + __IO uint32_t CHAN1_SRC_CTRL; + __IO uint32_t CHAN1_TAR_CTRL; + __IO uint32_t CHAN1_FIFO_DPTH_ADDR; + __IO uint32_t CHAN1_FIFO_PORT_SEL; + __IO uint32_t CHAN1_SPI_PORT_SEL; + __I uint32_t CHAN1_ERR_STAT; + __I uint32_t CHAN1_STATUS; + __I uint32_t CHAN1_TOTAL_WRITE_REMAINDER; + __I uint32_t CHAN1_INTERRUPT_STATUS; + __IO uint32_t CHAN1_INTERRUPT_MASK; + __IO uint32_t CHAN1_SET_INTERRUPT; + __IO uint32_t CHAN1_RESET_INTERRUPT; + __IO uint32_t CHAN1_CFG_HNONSEC; + __IO uint32_t CHAN2_OPMODE; + __IO uint32_t CHAN2_CONST_WDATA; + __IO uint32_t CHAN2_SRC_ADDR; + __IO uint32_t CHAN2_TAR_ADDR; + __IO uint32_t CHAN2_SIZE; + __IO uint32_t CHAN2_SRC_CTRL; + __IO uint32_t CHAN2_TAR_CTRL; + __IO uint32_t CHAN2_FIFO_DPTH_ADDR; + __IO uint32_t CHAN2_FIFO_PORT_SEL; + __IO uint32_t CHAN2_SPI_PORT_SEL; + __I uint32_t CHAN2_ERR_STAT; + __I uint32_t CHAN2_STATUS; + __I uint32_t CHAN2_TOTAL_WRITE_REMAINDER; + __I uint32_t CHAN2_INTERRUPT_STATUS; + __IO uint32_t CHAN2_INTERRUPT_MASK; + __IO uint32_t CHAN2_SET_INTERRUPT; + __IO uint32_t CHAN2_RESET_INTERRUPT; + __IO uint32_t CHAN2_CFG_HNONSEC; + __IO uint32_t CHAN3_OPMODE; + __IO uint32_t CHAN3_CONST_WDATA; + __IO uint32_t CHAN3_SRC_ADDR; + __IO uint32_t CHAN3_TAR_ADDR; + __IO uint32_t CHAN3_SIZE; + __IO uint32_t CHAN3_SRC_CTRL; + __IO uint32_t CHAN3_TAR_CTRL; + __IO uint32_t CHAN3_FIFO_DPTH_ADDR; + __IO uint32_t CHAN3_FIFO_PORT_SEL; + __IO uint32_t CHAN3_SPI_PORT_SEL; + __I uint32_t CHAN3_ERR_STAT; + __I uint32_t CHAN3_STATUS; + __I uint32_t CHAN3_TOTAL_WRITE_REMAINDER; + __I uint32_t CHAN3_INTERRUPT_STATUS; + __IO uint32_t CHAN3_INTERRUPT_MASK; + __IO uint32_t CHAN3_SET_INTERRUPT; + __IO uint32_t CHAN3_RESET_INTERRUPT; + __IO uint32_t CHAN3_CFG_HNONSEC; + __IO uint32_t ERR_INTERRUPT_DLY; + __IO uint32_t ARBITER_CTRL; + __I uint32_t ARBITER_GRANT_STAT; + __IO uint32_t DIAGCNTL; + uint32_t RESERVED0[947]; + __I uint32_t ID; +} CMSDK_AT_AHB_DMA_TypeDef; + +#define CMSDK_AT_PRRF_NONSECURE_BASE 0x1ffe00 +#define CMSDK_AT_PRRF_SECURE_BASE 0x101ffe00 +#define CMSDK_SHA2_NONSECURE_BASE 0x40103000 +#define CMSDK_WRPR0_NONSECURE_BASE 0x40143000 +#define CMSDK_AT_UART0_NONSECURE_BASE 0x40144000 +#define CMSDK_AT_UART1_NONSECURE_BASE 0x40145000 +#define CMSDK_PWM_NONSECURE_BASE 0x40146000 +#define CMSDK_SPI0_NONSECURE_BASE 0x40147000 +#define CMSDK_KSM_NONSECURE_BASE 0x4014a000 +#define CMSDK_SPI2_NONSECURE_BASE 0x4014b000 +#define CMSDK_QDEC_NONSECURE_BASE 0x4014c000 +#define CMSDK_SPI1_NONSECURE_BASE 0x4014d000 +#define CMSDK_SLWTIMER_NONSECURE_BASE 0x4014e000 +#define CMSDK_QSPI_NONSECURE_BASE 0x4014f000 +#define CMSDK_I2C0_NONSECURE_BASE 0x40150000 +#define CMSDK_I2C1_NONSECURE_BASE 0x40151000 +#define CMSDK_NVM_NONSECURE_BASE 0x40152000 +#define CMSDK_WRPR1_NONSECURE_BASE 0x40153000 +#define CMSDK_RIF_NONSECURE_BASE 0x40154000 +#define CMSDK_RADIO_NONSECURE_BASE 0x40155000 +#define CMSDK_MDM_NONSECURE_BASE 0x40156000 +#define CMSDK_PMU_NONSECURE_BASE 0x40157000 +#define CMSDK_PSEQ_NONSECURE_BASE 0x40158000 +#define CMSDK_SWD_NONSECURE_BASE 0x40159000 +#define CMSDK_GADC_NONSECURE_BASE 0x4015a000 +#define CMSDK_TRNG_NONSECURE_BASE 0x4015b000 +#define CMSDK_RCOS_CAL_NONSECURE_BASE 0x4015c000 +#define CMSDK_SHUB_NONSECURE_BASE 0x4015d000 +#define CMSDK_PDM0_NONSECURE_BASE 0x40160000 +#define CMSDK_PDM1_NONSECURE_BASE 0x40161000 +#define CMSDK_WRPR2_NONSECURE_BASE 0x40163000 +#define CMSDK_I2S_NONSECURE_BASE 0x40165000 +#define CMSDK_CLKRSTGEN_NONSECURE_BASE 0x40166000 +#define CMSDK_AES_NONSECURE_BASE 0x40167000 +#define CMSDK_AT_DMA_NONSECURE_BASE 0x40170000 +#define CMSDK_SHA2_SECURE_BASE 0x50103000 +#define CMSDK_WRPR0_SECURE_BASE 0x50143000 +#define CMSDK_AT_UART0_SECURE_BASE 0x50144000 +#define CMSDK_AT_UART0_BASE CMSDK_AT_UART0_SECURE_BASE +#define CMSDK_AT_UART1_SECURE_BASE 0x50145000 +#define CMSDK_AT_UART1_BASE CMSDK_AT_UART1_SECURE_BASE +#define CMSDK_PWM_SECURE_BASE 0x50146000 +#define CMSDK_SPI0_SECURE_BASE 0x50147000 +#define CMSDK_KSM_SECURE_BASE 0x5014a000 +#define CMSDK_SPI2_SECURE_BASE 0x5014b000 +#define CMSDK_QDEC_SECURE_BASE 0x5014c000 +#define CMSDK_SPI1_SECURE_BASE 0x5014d000 +#define CMSDK_SLWTIMER_SECURE_BASE 0x5014e000 +#define CMSDK_QSPI_SECURE_BASE 0x5014f000 +#define CMSDK_I2C0_SECURE_BASE 0x50150000 +#define CMSDK_I2C1_SECURE_BASE 0x50151000 +#define CMSDK_NVM_SECURE_BASE 0x50152000 +#define CMSDK_WRPR1_SECURE_BASE 0x50153000 +#define CMSDK_RIF_SECURE_BASE 0x50154000 +#define CMSDK_RADIO_SECURE_BASE 0x50155000 +#define CMSDK_MDM_SECURE_BASE 0x50156000 +#define CMSDK_PMU_SECURE_BASE 0x50157000 +#define CMSDK_PSEQ_SECURE_BASE 0x50158000 +#define CMSDK_SWD_SECURE_BASE 0x50159000 +#define CMSDK_GADC_SECURE_BASE 0x5015a000 +#define CMSDK_TRNG_SECURE_BASE 0x5015b000 +#define CMSDK_RCOS_CAL_SECURE_BASE 0x5015c000 +#define CMSDK_SHUB_SECURE_BASE 0x5015d000 +#define CMSDK_PDM0_SECURE_BASE 0x50160000 +#define CMSDK_PDM1_SECURE_BASE 0x50161000 +#define CMSDK_WRPR2_SECURE_BASE 0x50163000 +#define CMSDK_I2S_SECURE_BASE 0x50165000 +#define CMSDK_CLKRSTGEN_SECURE_BASE 0x50166000 +#define CMSDK_AES_SECURE_BASE 0x50167000 +#define CMSDK_AT_DMA_SECURE_BASE 0x50170000 + +#define CMSDK_AT_PRRF_NONSECURE ((CMSDK_AT_AHB_PRRF_TypeDef *) CMSDK_AT_PRRF_NONSECURE_BASE) +#define CMSDK_AT_PRRF_SECURE ((CMSDK_AT_AHB_PRRF_TypeDef *) CMSDK_AT_PRRF_SECURE_BASE) +#define CMSDK_SHA2_NONSECURE ((CMSDK_AT_AHB_SHA2_TypeDef *) CMSDK_SHA2_NONSECURE_BASE) +#define CMSDK_WRPR0_NONSECURE ((CMSDK_AT_APB_WRPR_PINS_TypeDef *) CMSDK_WRPR0_NONSECURE_BASE) +#define CMSDK_AT_UART0_NONSECURE ((CMSDK_AT_APB_UART_TypeDef *) CMSDK_AT_UART0_NONSECURE_BASE) +#define CMSDK_AT_UART1_NONSECURE ((CMSDK_AT_APB_UART_TypeDef *) CMSDK_AT_UART1_NONSECURE_BASE) +#define CMSDK_PWM_NONSECURE ((CMSDK_AT_APB_PWM_TypeDef *) CMSDK_PWM_NONSECURE_BASE) +#define CMSDK_SPI0_NONSECURE ((CMSDK_AT_APB_SPI_TypeDef *) CMSDK_SPI0_NONSECURE_BASE) +#define CMSDK_KSM_NONSECURE ((CMSDK_AT_APB_KSM_TypeDef *) CMSDK_KSM_NONSECURE_BASE) +#define CMSDK_SPI2_NONSECURE ((CMSDK_AT_APB_SPI_TypeDef *) CMSDK_SPI2_NONSECURE_BASE) +#define CMSDK_QDEC_NONSECURE ((CMSDK_AT_APB_QDEC_TypeDef *) CMSDK_QDEC_NONSECURE_BASE) +#define CMSDK_SPI1_NONSECURE ((CMSDK_AT_APB_SPI_TypeDef *) CMSDK_SPI1_NONSECURE_BASE) +#define CMSDK_SLWTIMER_NONSECURE ((CMSDK_AT_APB_SLWTIMER_TypeDef *) CMSDK_SLWTIMER_NONSECURE_BASE) +#define CMSDK_QSPI_NONSECURE ((CMSDK_AT_APB_QSPI_TypeDef *) CMSDK_QSPI_NONSECURE_BASE) +#define CMSDK_I2C0_NONSECURE ((CMSDK_AT_APB_I2C_TypeDef *) CMSDK_I2C0_NONSECURE_BASE) +#define CMSDK_I2C1_NONSECURE ((CMSDK_AT_APB_I2C_TypeDef *) CMSDK_I2C1_NONSECURE_BASE) +#define CMSDK_NVM_NONSECURE ((CMSDK_AT_APB_TSMC_NVM_TypeDef *) CMSDK_NVM_NONSECURE_BASE) +#define CMSDK_WRPR1_NONSECURE ((CMSDK_AT_APB_WRPR_SHORT_TypeDef *) CMSDK_WRPR1_NONSECURE_BASE) +#define CMSDK_RIF_NONSECURE ((CMSDK_RIF_TypeDef *) CMSDK_RIF_NONSECURE_BASE) +#define CMSDK_RADIO_NONSECURE ((CMSDK_AT_APB_SPI_TypeDef *) CMSDK_RADIO_NONSECURE_BASE) +#define CMSDK_MDM_NONSECURE ((CMSDK_MDM_TypeDef *) CMSDK_MDM_NONSECURE_BASE) +#define CMSDK_PMU_NONSECURE ((CMSDK_AT_APB_SPI_TypeDef *) CMSDK_PMU_NONSECURE_BASE) +#define CMSDK_PSEQ_NONSECURE ((CMSDK_AT_APB_PSEQ_PARIS_TypeDef *) CMSDK_PSEQ_NONSECURE_BASE) +#define CMSDK_SWD_NONSECURE ((CMSDK_AT_APB_SWD_TypeDef *) CMSDK_SWD_NONSECURE_BASE) +#define CMSDK_GADC_NONSECURE ((CMSDK_AT_APB_GADC_TypeDef *) CMSDK_GADC_NONSECURE_BASE) +#define CMSDK_TRNG_NONSECURE ((CMSDK_AT_APB_TRNG_TypeDef *) CMSDK_TRNG_NONSECURE_BASE) +#define CMSDK_RCOS_CAL_NONSECURE ((CMSDK_AT_APB_RCOS_CAL_TypeDef *) CMSDK_RCOS_CAL_NONSECURE_BASE) +#define CMSDK_SHUB_NONSECURE ((CMSDK_AT_APB_SHUB_TypeDef *) CMSDK_SHUB_NONSECURE_BASE) +#define CMSDK_PDM0_NONSECURE ((CMSDK_AT_APB_PDM_TypeDef *) CMSDK_PDM0_NONSECURE_BASE) +#define CMSDK_PDM1_NONSECURE ((CMSDK_AT_APB_PDM_TypeDef *) CMSDK_PDM1_NONSECURE_BASE) +#define CMSDK_WRPR2_NONSECURE ((CMSDK_AT_APB_WRPR_SHORT_TypeDef *) CMSDK_WRPR2_NONSECURE_BASE) +#define CMSDK_I2S_NONSECURE ((CMSDK_AT_I2S_TypeDef *) CMSDK_I2S_NONSECURE_BASE) +#define CMSDK_CLKRSTGEN_NONSECURE ((CMSDK_AT_APB_CLKRSTGEN_TypeDef *) CMSDK_CLKRSTGEN_NONSECURE_BASE) +#define CMSDK_AES_NONSECURE ((CMSDK_AT_APB_AES_TypeDef *) CMSDK_AES_NONSECURE_BASE) +#define CMSDK_AT_DMA_NONSECURE ((CMSDK_AT_AHB_DMA_TypeDef *) CMSDK_AT_DMA_NONSECURE_BASE) +#define CMSDK_SHA2_SECURE ((CMSDK_AT_AHB_SHA2_TypeDef *) CMSDK_SHA2_SECURE_BASE) +#define CMSDK_WRPR0_SECURE ((CMSDK_AT_APB_WRPR_PINS_TypeDef *) CMSDK_WRPR0_SECURE_BASE) +#define CMSDK_AT_UART0_SECURE ((CMSDK_AT_APB_UART_TypeDef *) CMSDK_AT_UART0_SECURE_BASE) +#define CMSDK_AT_UART0 CMSDK_AT_UART0_SECURE +#define CMSDK_AT_UART1_SECURE ((CMSDK_AT_APB_UART_TypeDef *) CMSDK_AT_UART1_SECURE_BASE) +#define CMSDK_AT_UART1 CMSDK_AT_UART1_SECURE +#define CMSDK_PWM_SECURE ((CMSDK_AT_APB_PWM_TypeDef *) CMSDK_PWM_SECURE_BASE) +#define CMSDK_SPI0_SECURE ((CMSDK_AT_APB_SPI_TypeDef *) CMSDK_SPI0_SECURE_BASE) +#define CMSDK_KSM_SECURE ((CMSDK_AT_APB_KSM_TypeDef *) CMSDK_KSM_SECURE_BASE) +#define CMSDK_SPI2_SECURE ((CMSDK_AT_APB_SPI_TypeDef *) CMSDK_SPI2_SECURE_BASE) +#define CMSDK_QDEC_SECURE ((CMSDK_AT_APB_QDEC_TypeDef *) CMSDK_QDEC_SECURE_BASE) +#define CMSDK_SPI1_SECURE ((CMSDK_AT_APB_SPI_TypeDef *) CMSDK_SPI1_SECURE_BASE) +#define CMSDK_SLWTIMER_SECURE ((CMSDK_AT_APB_SLWTIMER_TypeDef *) CMSDK_SLWTIMER_SECURE_BASE) +#define CMSDK_QSPI_SECURE ((CMSDK_AT_APB_QSPI_TypeDef *) CMSDK_QSPI_SECURE_BASE) +#define CMSDK_I2C0_SECURE ((CMSDK_AT_APB_I2C_TypeDef *) CMSDK_I2C0_SECURE_BASE) +#define CMSDK_I2C1_SECURE ((CMSDK_AT_APB_I2C_TypeDef *) CMSDK_I2C1_SECURE_BASE) +#define CMSDK_NVM_SECURE ((CMSDK_AT_APB_TSMC_NVM_TypeDef *) CMSDK_NVM_SECURE_BASE) +#define CMSDK_WRPR1_SECURE ((CMSDK_AT_APB_WRPR_SHORT_TypeDef *) CMSDK_WRPR1_SECURE_BASE) +#define CMSDK_RIF_SECURE ((CMSDK_RIF_TypeDef *) CMSDK_RIF_SECURE_BASE) +#define CMSDK_RADIO_SECURE ((CMSDK_AT_APB_SPI_TypeDef *) CMSDK_RADIO_SECURE_BASE) +#define CMSDK_MDM_SECURE ((CMSDK_MDM_TypeDef *) CMSDK_MDM_SECURE_BASE) +#define CMSDK_PMU_SECURE ((CMSDK_AT_APB_SPI_TypeDef *) CMSDK_PMU_SECURE_BASE) +#define CMSDK_PSEQ_SECURE ((CMSDK_AT_APB_PSEQ_PARIS_TypeDef *) CMSDK_PSEQ_SECURE_BASE) +#define CMSDK_SWD_SECURE ((CMSDK_AT_APB_SWD_TypeDef *) CMSDK_SWD_SECURE_BASE) +#define CMSDK_GADC_SECURE ((CMSDK_AT_APB_GADC_TypeDef *) CMSDK_GADC_SECURE_BASE) +#define CMSDK_TRNG_SECURE ((CMSDK_AT_APB_TRNG_TypeDef *) CMSDK_TRNG_SECURE_BASE) +#define CMSDK_RCOS_CAL_SECURE ((CMSDK_AT_APB_RCOS_CAL_TypeDef *) CMSDK_RCOS_CAL_SECURE_BASE) +#define CMSDK_SHUB_SECURE ((CMSDK_AT_APB_SHUB_TypeDef *) CMSDK_SHUB_SECURE_BASE) +#define CMSDK_PDM0_SECURE ((CMSDK_AT_APB_PDM_TypeDef *) CMSDK_PDM0_SECURE_BASE) +#define CMSDK_PDM1_SECURE ((CMSDK_AT_APB_PDM_TypeDef *) CMSDK_PDM1_SECURE_BASE) +#define CMSDK_WRPR2_SECURE ((CMSDK_AT_APB_WRPR_SHORT_TypeDef *) CMSDK_WRPR2_SECURE_BASE) +#define CMSDK_I2S_SECURE ((CMSDK_AT_I2S_TypeDef *) CMSDK_I2S_SECURE_BASE) +#define CMSDK_CLKRSTGEN_SECURE ((CMSDK_AT_APB_CLKRSTGEN_TypeDef *) CMSDK_CLKRSTGEN_SECURE_BASE) +#define CMSDK_AES_SECURE ((CMSDK_AT_APB_AES_TypeDef *) CMSDK_AES_SECURE_BASE) +#define CMSDK_AT_DMA_SECURE ((CMSDK_AT_AHB_DMA_TypeDef *) CMSDK_AT_DMA_SECURE_BASE) +/** @} end of at_base_addr */ diff --git a/ATM33xx-5/include/reg/base_addr_place_holders.h b/ATM33xx-5/include/reg/base_addr_place_holders.h new file mode 100644 index 0000000..032070a --- /dev/null +++ b/ATM33xx-5/include/reg/base_addr_place_holders.h @@ -0,0 +1,69 @@ +/** + ******************************************************************************* + * + * @file base_addr_place_holders.h + * + * @brief Base Address manual definitions + * + * Copyright (C) Atmosic 2020-2024 + * + ******************************************************************************* + */ + +// This is a temporary, manually written companion to base_addr.h for +// paris. It is a place holder for definitions that aren't yet +// generated by Blueprint but are necessary to build software. The +// idea is to shrink this -- rather quickly -- until it is empty, at +// which point CHIP_HDR_PLACEHOLDERS in this directory's makefile can +// be unset. + +#pragma once + +#define CMSDK_EXT_FLASH_NONSECURE_BASE 0x00200000 + +#define CMSDK_PDM0_PP_NONSECURE_BASE 0x40300000 +#define CMSDK_PDM1_PP_NONSECURE_BASE 0x40301000 +#define CMSDK_I2S_PP_NONSECURE_BASE 0x40304000 +#define BLE_NONSECURE_BASE 0x40120000 + +#define CMSDK_PDM0_PP_SECURE_BASE 0x50300000 +#define CMSDK_PDM1_PP_SECURE_BASE 0x50301000 +#define CMSDK_I2S_PP_SECURE_BASE 0x50304000 +#define BLE_SECURE_BASE 0x50120000 + + +//////////////////////////////////////////////////////////////////////////////// +// Selectively move above this line definitions from the section below if they +// are needed but not generated by blueprint +//////////////////////////////////////////////////////////////////////////////// + +#if 0 +/*---------- AT_APB_OLED ----------*/ +typedef struct { + __IO uint32_t CONTROL; + __IO uint32_t CHARS_0A; + __IO uint32_t CHARS_0B; + __IO uint32_t CHARS_0C; + __IO uint32_t CHARS_0D; + __IO uint32_t CHARS_1A; + __IO uint32_t CHARS_1B; + __IO uint32_t CHARS_1C; + __IO uint32_t CHARS_1D; + __IO uint32_t CHARS_2A; + __IO uint32_t CHARS_2B; + __IO uint32_t CHARS_2C; + __IO uint32_t CHARS_2D; + __IO uint32_t CHARS_3A; + __IO uint32_t CHARS_3B; + __IO uint32_t CHARS_3C; + __IO uint32_t CHARS_3D; + __I uint32_t STATUS; + uint32_t RESERVED0[1005]; + __I uint32_t CORE_ID; +} CMSDK_AT_APB_OLED_TypeDef; + +#define CMSDK_DPR_NONSECURE_BASE 0x4016F000 + +#define CMSDK_DPR_NONSECURE ((CMSDK_AT_APB_DPR_TypeDef *) CMSDK_DPR_NONSECURE_BASE) + +#endif // 0 diff --git a/ATM33xx-5/include/reg/base_addr_utils.h b/ATM33xx-5/include/reg/base_addr_utils.h new file mode 100644 index 0000000..6456a31 --- /dev/null +++ b/ATM33xx-5/include/reg/base_addr_utils.h @@ -0,0 +1,1499 @@ +/** + ***************************************************************************** + * + * @file base_addr_utils.h + * + * @brief Base Address Utility definitions + * + * Copyright (C) Atmosic 2022-2024 + * + ***************************************************************************** + */ + +#pragma once + + +#include "base_addr.h" + +/** + * @defgroup at_base_addr_utils base_addr_utils + * @ingroup AT_REG + * @brief base address utils definitions. + * @{ + */ +/*---------- AT_AHB_PRRF ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_AHB_PRRF_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "PATCH_TAG0"; + case 4: return "PATCH_TAG1"; + case 8: return "PATCH_TAG2"; + case 12: return "PATCH_TAG3"; + case 16: return "PATCH_TAG4"; + case 20: return "PATCH_TAG5"; + case 24: return "PATCH_TAG6"; + case 28: return "PATCH_TAG7"; + case 32: return "PATCH_TAG8"; + case 36: return "PATCH_TAG9"; + case 40: return "PATCH_TAG10"; + case 44: return "PATCH_TAG11"; + case 48: return "PATCH_TAG12"; + case 52: return "PATCH_TAG13"; + case 56: return "PATCH_TAG14"; + case 60: return "PATCH_TAG15"; + case 64: return "PATCH0"; + case 68: return "PATCH1"; + case 72: return "PATCH2"; + case 76: return "PATCH3"; + case 80: return "PATCH4"; + case 84: return "PATCH5"; + case 88: return "PATCH6"; + case 92: return "PATCH7"; + case 96: return "PATCH8"; + case 100: return "PATCH9"; + case 104: return "PATCH10"; + case 108: return "PATCH11"; + case 112: return "PATCH12"; + case 116: return "PATCH13"; + case 120: return "PATCH14"; + case 124: return "PATCH15"; + case 128: return "PATCH16"; + case 132: return "PATCH17"; + case 136: return "PATCH18"; + case 140: return "PATCH19"; + case 144: return "PATCH20"; + case 148: return "PATCH21"; + case 152: return "PATCH22"; + case 156: return "PATCH23"; + case 160: return "PATCH24"; + case 164: return "PATCH25"; + case 168: return "PATCH26"; + case 172: return "PATCH27"; + case 176: return "PATCH28"; + case 180: return "PATCH29"; + case 184: return "PATCH30"; + case 188: return "PATCH31"; + case 192: return "PATCH32"; + case 196: return "PATCH33"; + case 200: return "PATCH34"; + case 204: return "PATCH35"; + case 208: return "PATCH36"; + case 212: return "PATCH37"; + case 216: return "PATCH38"; + case 220: return "PATCH39"; + case 224: return "PATCH40"; + case 228: return "PATCH41"; + case 232: return "PATCH42"; + case 236: return "PATCH43"; + case 240: return "PATCH44"; + case 244: return "PATCH45"; + case 248: return "PATCH46"; + case 252: return "PATCH47"; + case 256: return "RRAM_WRT_CONFIG_LO"; + case 260: return "RRAM_WRT_CONFIG_HI"; + case 264: return "RRAM_READ_CONFIG_LO"; + case 268: return "RRAM_READ_CONFIG_HI"; + case 272: return "RRAM_CACHE_CONFIG"; + case 276: return "RRAM_MEM_CONFIG"; + case 280: return "RRAM_STATUS"; + default: return "unknown CMSDK_AT_AHB_PRRF offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_AHB_PRRF_begin_offset() { return 0; } +static inline int CMSDK_AT_AHB_PRRF_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_AHB_PRRF_TypeDef); } +static inline uint32_t CMSDK_AT_AHB_PRRF_next_offset(uint32_t offset) { + switch (offset) { + default: return offset + 4; + } +} +/*---------- AT_AHB_SHA2 ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_AHB_SHA2_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "CONTROL"; + case 4: return "SIDELOAD_CTRL"; + case 8: return "CMD"; + case 12: return "MESSAGE_LENGTH_LO"; + case 16: return "MESSAGE_LENGTH_HI"; + case 20: return "WIPE_V"; + case 24: return "FIFO_PUSH"; + case 28: return "DIGEST0"; + case 32: return "DIGEST1"; + case 36: return "DIGEST2"; + case 40: return "DIGEST3"; + case 44: return "DIGEST4"; + case 48: return "DIGEST5"; + case 52: return "DIGEST6"; + case 56: return "DIGEST7"; + case 60: return "KEY_0"; + case 64: return "KEY_1"; + case 68: return "KEY_2"; + case 72: return "KEY_3"; + case 76: return "KEY_4"; + case 80: return "KEY_5"; + case 84: return "KEY_6"; + case 88: return "KEY_7"; + case 92: return "STATUS"; + case 96: return "INTERRUPT_STATUS"; + case 100: return "INTERRUPT_MASK"; + case 104: return "SET_INTERRUPT"; + case 108: return "RESET_INTERRUPT"; + case 112: return "ERR_CODE"; + case 4092: return "ID"; + default: return "unknown CMSDK_AT_AHB_SHA2 offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_AHB_SHA2_begin_offset() { return 0; } +static inline int CMSDK_AT_AHB_SHA2_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_AHB_SHA2_TypeDef); } +static inline uint32_t CMSDK_AT_AHB_SHA2_next_offset(uint32_t offset) { + switch (offset) { + case 112: return 4092; + default: return offset + 4; + } +} +/*---------- AT_APB_WRPR_PINS ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_APB_WRPR_PINS_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "APB0_CTRL"; + case 4: return "APB1_CTRL"; + case 8: return "APB2_CTRL"; + case 12: return "APB3_CTRL"; + case 16: return "APB4_CTRL"; + case 20: return "APB5_CTRL"; + case 24: return "APB6_CTRL"; + case 28: return "APB7_CTRL"; + case 32: return "APB8_CTRL"; + case 36: return "APB9_CTRL"; + case 40: return "APB10_CTRL"; + case 44: return "APB11_CTRL"; + case 48: return "APB12_CTRL"; + case 52: return "APB13_CTRL"; + case 56: return "APB14_CTRL"; + case 60: return "APB15_CTRL"; + case 64: return "CLK_HPC_PIN_OUT_CTRL"; + case 68: return "CLK_MPC_PIN_OUT_CTRL"; + case 72: return "CLK_LPC_PIN_OUT_CTRL"; + case 76: return "DBG_CTRL"; + case 80: return "PSEL_A"; + case 84: return "PSEL_B"; + case 88: return "PSEL_C"; + case 92: return "PSEL_D"; + case 96: return "PSEL_E"; + case 100: return "PSEL_F"; + case 104: return "PSEL_G"; + case 108: return "PSEL_H"; + case 112: return "PSEL_I"; + case 116: return "PUPD_OVRD"; + case 120: return "PUPD_OVRD_VAL"; + case 124: return "REMAP"; + case 128: return "AHB_INTERPOSERS"; + case 132: return "SCRATCHPAD_A"; + case 136: return "SCRATCHPAD_B"; + case 140: return "SCRATCHPAD_C"; + case 144: return "SCRATCHPAD_D"; + case 148: return "RRAM_WRITE_PROTECTION0"; + case 152: return "RRAM_WRITE_PROTECTION1"; + case 156: return "RRAM_WRITE_PROTECTION2"; + case 160: return "RRAM_WRITE_PROTECTION3"; + case 164: return "RRAM_WRITE_PROTECTION4"; + case 168: return "RRAM_WRITE_PROTECTION5"; + case 172: return "RRAM_WRITE_PROTECTION6"; + case 176: return "RRAM_WRITE_PROTECTION7"; + case 180: return "RRAM_STICKY_WRITE_PROTECTION0"; + case 184: return "RRAM_STICKY_WRITE_PROTECTION1"; + case 188: return "RRAM_STICKY_WRITE_PROTECTION2"; + case 192: return "RRAM_STICKY_WRITE_PROTECTION3"; + case 196: return "RRAM_STICKY_WRITE_PROTECTION4"; + case 200: return "RRAM_STICKY_WRITE_PROTECTION5"; + case 204: return "RRAM_STICKY_WRITE_PROTECTION6"; + case 208: return "RRAM_STICKY_WRITE_PROTECTION7"; + case 212: return "RRAM_STICKY_WRITE_PROTECTION_STATUS0"; + case 216: return "RRAM_STICKY_WRITE_PROTECTION_STATUS1"; + case 220: return "RRAM_STICKY_WRITE_PROTECTION_STATUS2"; + case 224: return "RRAM_STICKY_WRITE_PROTECTION_STATUS3"; + case 228: return "RRAM_STICKY_WRITE_PROTECTION_STATUS4"; + case 232: return "RRAM_STICKY_WRITE_PROTECTION_STATUS5"; + case 236: return "RRAM_STICKY_WRITE_PROTECTION_STATUS6"; + case 240: return "RRAM_STICKY_WRITE_PROTECTION_STATUS7"; + case 244: return "RRAM_STICKY_READ_PROTECTION0"; + case 248: return "RRAM_STICKY_READ_PROTECTION_STATUS0"; + case 252: return "PROT_BITS_SET0"; + case 256: return "PROT_BITS_SET1"; + case 260: return "PROT_BITS_STAT0"; + case 264: return "PROT_BITS_STAT1"; + case 268: return "QSPI_STICKY_WRITE_PROTECTION0"; + case 272: return "QSPI_STICKY_WRITE_PROTECTION1"; + case 276: return "QSPI_STICKY_WRITE_PROTECTION_STATUS0"; + case 280: return "QSPI_STICKY_WRITE_PROTECTION_STATUS1"; + case 284: return "PDSN"; + case 288: return "CALCOUNTRC"; + case 292: return "SECURE_DEBUG_CTRL"; + case 296: return "SECURE_DEBUG_STAT"; + case 4080: return "CHIPID1"; + case 4084: return "CHIPID2"; + case 4088: return "CHIPREV"; + case 4092: return "CORE_ID"; + default: return "unknown CMSDK_AT_APB_WRPR_PINS offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_APB_WRPR_PINS_begin_offset() { return 0; } +static inline int CMSDK_AT_APB_WRPR_PINS_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_APB_WRPR_PINS_TypeDef); } +static inline uint32_t CMSDK_AT_APB_WRPR_PINS_next_offset(uint32_t offset) { + switch (offset) { + case 296: return 4080; + default: return offset + 4; + } +} +/*---------- AT_APB_UART ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_APB_UART_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "DATA"; + case 4: return "STATE"; + case 8: return "CTRL"; + case 12: return "INTSTATUS_CLEAR"; + case 16: return "BAUDDIV"; + case 20: return "RX_LWM"; + case 24: return "TX_LWM"; + case 28: return "RX_FIFO_SPACES"; + case 32: return "TX_FIFO_SPACES"; + case 36: return "HW_FLOW_OVRD"; + case 40: return "BAUD_RATE_DETECT"; + case 44: return "BAUD_DIV_CEIL"; + case 48: return "BRD_STAT"; + case 52: return "INTMASK"; + case 56: return "RX_FIFO_ENTRIES"; + case 60: return "INTSTATUS_SET"; + case 4048: return "PID4"; + case 4052: return "PID5"; + case 4056: return "PID6"; + case 4060: return "PID7"; + case 4064: return "PID0"; + case 4068: return "PID1"; + case 4072: return "PID2"; + case 4076: return "PID3"; + case 4080: return "CID0"; + case 4084: return "CID1"; + case 4088: return "CID2"; + case 4092: return "CID3"; + default: return "unknown CMSDK_AT_APB_UART offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_APB_UART_begin_offset() { return 0; } +static inline int CMSDK_AT_APB_UART_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_APB_UART_TypeDef); } +static inline uint32_t CMSDK_AT_APB_UART_next_offset(uint32_t offset) { + switch (offset) { + case 60: return 4048; + default: return offset + 4; + } +} +/*---------- AT_APB_PWM ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_APB_PWM_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "PWM_CTRL"; + case 4: return "PWM0_CTRL"; + case 8: return "PWM0_DUR"; + case 12: return "PWM0_CFG"; + case 16: return "PWM1_CTRL"; + case 20: return "PWM1_DUR"; + case 24: return "PWM1_CFG"; + case 28: return "PWM2_CTRL"; + case 32: return "PWM2_DUR"; + case 36: return "PWM2_CFG"; + case 40: return "PWM3_CTRL"; + case 44: return "PWM3_DUR"; + case 48: return "PWM3_CFG"; + case 52: return "PWM4_CTRL"; + case 56: return "PWM4_DUR"; + case 60: return "PWM4_CFG"; + case 64: return "PWM5_CTRL"; + case 68: return "PWM5_DUR"; + case 72: return "PWM5_CFG"; + case 76: return "PWM6_CTRL"; + case 80: return "PWM6_DUR"; + case 84: return "PWM6_CFG"; + case 88: return "PWM7_CTRL"; + case 92: return "PWM7_DUR"; + case 96: return "PWM7_CFG"; + case 100: return "FSM_STATE"; + case 104: return "FIFO_CFG"; + case 108: return "FIFO_CARRIER1_DUR"; + case 112: return "FIFO_CARRIER2_DUR"; + case 116: return "FIFO_STAT"; + case 120: return "FIFO_STAT1"; + case 124: return "FIFO_SEL_ERR_SOURCE"; + case 128: return "INTERRUPTS"; + case 132: return "INTERRUPTS_MASK"; + case 136: return "INTERRUPTS_CLEAR"; + case 140: return "INTERRUPTS_SET"; + case 4080: return "FIFO_DATA"; + case 4084: return "CORE_ID"; + case 4088: return "REV_HASH"; + case 4092: return "REV_KEY"; + default: return "unknown CMSDK_AT_APB_PWM offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_APB_PWM_begin_offset() { return 0; } +static inline int CMSDK_AT_APB_PWM_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_APB_PWM_TypeDef); } +static inline uint32_t CMSDK_AT_APB_PWM_next_offset(uint32_t offset) { + switch (offset) { + case 140: return 4080; + default: return offset + 4; + } +} +/*---------- AT_APB_SPI ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_APB_SPI_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "CTRL"; + case 4: return "TRANSACTION_SETUP"; + case 8: return "TRANSACTION_SETUP_DMA"; + case 12: return "TRANSACTION_STATUS"; + case 16: return "DATA_BYTES_LOWER"; + case 20: return "DATA_BYTES_UPPER"; + case 24: return "INTERRUPT_MASK"; + case 28: return "INTERRUPT_STATUS"; + case 32: return "SET_INTERRUPT"; + case 36: return "RESET_INTERRUPT"; + case 4092: return "CORE_ID"; + default: return "unknown CMSDK_AT_APB_SPI offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_APB_SPI_begin_offset() { return 0; } +static inline int CMSDK_AT_APB_SPI_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_APB_SPI_TypeDef); } +static inline uint32_t CMSDK_AT_APB_SPI_next_offset(uint32_t offset) { + switch (offset) { + case 36: return 4092; + default: return offset + 4; + } +} +/*---------- AT_APB_KSM ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_APB_KSM_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "CTRL0"; + case 4: return "TIME_PARAM0"; + case 8: return "TIME_PARAM1"; + case 12: return "MATRIX_SIZE"; + case 64: return "KEYBOARD_PACKET"; + case 68: return "LOW_POWER"; + case 88: return "LPBACK_KSI"; + case 128: return "STATUS"; + case 192: return "INTERRUPTS"; + case 196: return "INTERRUPT_MASK"; + case 200: return "INTERRUPT_CLEAR"; + case 4084: return "DEBUG"; + case 4088: return "DEBUG2"; + case 4092: return "CORE_ID"; + default: return "unknown CMSDK_AT_APB_KSM offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_APB_KSM_begin_offset() { return 0; } +static inline int CMSDK_AT_APB_KSM_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_APB_KSM_TypeDef); } +static inline uint32_t CMSDK_AT_APB_KSM_next_offset(uint32_t offset) { + switch (offset) { + case 12: return 64; + case 68: return 88; + case 88: return 128; + case 128: return 192; + case 200: return 4084; + default: return offset + 4; + } +} +/*---------- AT_APB_QDEC ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_APB_QDEC_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "SETUP_FOR_AXIS_0"; + case 4: return "ACCUM_PURGE_STATUS_FOR_AXIS_0"; + case 8: return "ACCUMULATOR_VALUE_FOR_AXIS_0"; + case 12: return "ERR_PURGE_STATUS_FOR_AXIS_0"; + case 16: return "ERROR_COUNT_FOR_AXIS_0"; + case 20: return "SETUP_FOR_AXIS_1"; + case 24: return "ACCUM_PURGE_STATUS_FOR_AXIS_1"; + case 28: return "ACCUMULATOR_VALUE_FOR_AXIS_1"; + case 32: return "ERR_PURGE_STATUS_FOR_AXIS_1"; + case 36: return "ERROR_COUNT_FOR_AXIS_1"; + case 40: return "SETUP_FOR_AXIS_2"; + case 44: return "ACCUM_PURGE_STATUS_FOR_AXIS_2"; + case 48: return "ACCUMULATOR_VALUE_FOR_AXIS_2"; + case 52: return "ERR_PURGE_STATUS_FOR_AXIS_2"; + case 56: return "ERROR_COUNT_FOR_AXIS_2"; + case 4092: return "CORE_ID"; + default: return "unknown CMSDK_AT_APB_QDEC offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_APB_QDEC_begin_offset() { return 0; } +static inline int CMSDK_AT_APB_QDEC_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_APB_QDEC_TypeDef); } +static inline uint32_t CMSDK_AT_APB_QDEC_next_offset(uint32_t offset) { + switch (offset) { + case 56: return 4092; + default: return offset + 4; + } +} +/*---------- AT_APB_SLWTIMER ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_APB_SLWTIMER_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "CONTROL"; + case 4: return "INIT_LOW"; + case 8: return "INIT_HIGH"; + case 12: return "CNT_LOW"; + case 16: return "CNT_HIGH"; + case 20: return "THRES0_LOW"; + case 24: return "THRES0_HIGH"; + case 28: return "THRES1_LOW"; + case 32: return "THRES1_HIGH"; + case 36: return "THRES2_LOW"; + case 40: return "THRES2_HIGH"; + case 44: return "STATUS"; + case 48: return "INTERRUPT_STATUS"; + case 52: return "INTERRUPT_MASK"; + case 4092: return "CORE_ID"; + default: return "unknown CMSDK_AT_APB_SLWTIMER offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_APB_SLWTIMER_begin_offset() { return 0; } +static inline int CMSDK_AT_APB_SLWTIMER_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_APB_SLWTIMER_TypeDef); } +static inline uint32_t CMSDK_AT_APB_SLWTIMER_next_offset(uint32_t offset) { + switch (offset) { + case 52: return 4092; + default: return offset + 4; + } +} +/*---------- AT_APB_QSPI ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_APB_QSPI_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "TRANSACTION_SETUP"; + case 4: return "READ_DATA"; + case 8: return "OVERRIDE_DIN"; + case 12: return "MODE"; + case 16: return "REMOTE_AHB_SETUP"; + case 20: return "REMOTE_AHB_SETUP_2"; + case 24: return "REMOTE_AHB_SETUP_3"; + case 28: return "REMOTE_AHB_SETUP_4"; + case 32: return "REMOTE_AHB_SETUP_5"; + case 36: return "REMOTE_AHB_SETUP_6"; + case 40: return "REMOTE_AHB_SETUP_7"; + case 44: return "REMOTE_AHB_WLE_CNT"; + case 48: return "REMOTE_AHB_WIP_CNT"; + case 52: return "REMOTE_AHB_DBG0"; + case 56: return "REMOTE_AHB_DBG1"; + case 60: return "REMOTE_AHB_DBG2"; + case 4092: return "CORE_ID"; + default: return "unknown CMSDK_AT_APB_QSPI offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_APB_QSPI_begin_offset() { return 0; } +static inline int CMSDK_AT_APB_QSPI_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_APB_QSPI_TypeDef); } +static inline uint32_t CMSDK_AT_APB_QSPI_next_offset(uint32_t offset) { + switch (offset) { + case 60: return 4092; + default: return offset + 4; + } +} +/*---------- AT_APB_I2C ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_APB_I2C_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "TRANSACTION_SETUP"; + case 4: return "CLOCK_CONTROL"; + case 8: return "OUTGOING_DATA"; + case 12: return "OUTGOING_DATA1"; + case 16: return "IO_CTRL"; + case 20: return "INCOMING_DATA"; + case 24: return "INCOMING_DATA1"; + case 28: return "TRANSACTION_STATUS"; + case 32: return "INTERRUPT_MASK"; + case 36: return "INTERRUPT_STATUS"; + case 40: return "SET_INTERRUPT"; + case 44: return "RESET_INTERRUPT"; + case 4092: return "ID"; + default: return "unknown CMSDK_AT_APB_I2C offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_APB_I2C_begin_offset() { return 0; } +static inline int CMSDK_AT_APB_I2C_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_APB_I2C_TypeDef); } +static inline uint32_t CMSDK_AT_APB_I2C_next_offset(uint32_t offset) { + switch (offset) { + case 44: return 4092; + default: return offset + 4; + } +} +/*---------- AT_APB_TSMC_NVM ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_APB_TSMC_NVM_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "OPMODE"; + case 4: return "CTRL"; + case 8: return "DATA0"; + case 12: return "DATA1"; + case 16: return "STATUS"; + case 20: return "T_SP_VQ"; + case 24: return "T_HP_VQ"; + case 28: return "T_SP_PG"; + case 32: return "T_HP_PG"; + case 36: return "T_HP_CK"; + case 40: return "T_S_PGM"; + case 44: return "T_H_PGM"; + case 48: return "T_CKHP"; + case 52: return "T_CKLP"; + case 56: return "T_SPS_CK"; + case 60: return "T_SR_CK"; + case 64: return "T_HR_CK"; + case 68: return "T_CKLR"; + case 72: return "T_CKHR"; + case 76: return "T_SRS_CK"; + case 80: return "INTERRUPT_STATUS"; + case 84: return "INTERRUPT_MASK"; + case 88: return "INTERRUPT_SET"; + case 92: return "INTERRUPT_RESET"; + case 4092: return "CORE_ID"; + default: return "unknown CMSDK_AT_APB_TSMC_NVM offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_APB_TSMC_NVM_begin_offset() { return 0; } +static inline int CMSDK_AT_APB_TSMC_NVM_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_APB_TSMC_NVM_TypeDef); } +static inline uint32_t CMSDK_AT_APB_TSMC_NVM_next_offset(uint32_t offset) { + switch (offset) { + case 92: return 4092; + default: return offset + 4; + } +} +/*---------- AT_APB_WRPR_SHORT ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_APB_WRPR_SHORT_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "APB0_CTRL"; + case 4: return "APB1_CTRL"; + case 8: return "APB2_CTRL"; + case 12: return "APB3_CTRL"; + case 16: return "APB4_CTRL"; + case 20: return "APB5_CTRL"; + case 24: return "APB6_CTRL"; + case 28: return "APB7_CTRL"; + case 32: return "APB8_CTRL"; + case 36: return "APB9_CTRL"; + case 40: return "APB10_CTRL"; + case 44: return "APB11_CTRL"; + case 48: return "APB12_CTRL"; + case 52: return "APB13_CTRL"; + case 56: return "APB14_CTRL"; + case 60: return "APB15_CTRL"; + case 4092: return "CORE_ID"; + default: return "unknown CMSDK_AT_APB_WRPR_SHORT offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_APB_WRPR_SHORT_begin_offset() { return 0; } +static inline int CMSDK_AT_APB_WRPR_SHORT_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_APB_WRPR_SHORT_TypeDef); } +static inline uint32_t CMSDK_AT_APB_WRPR_SHORT_next_offset(uint32_t offset) { + switch (offset) { + case 60: return 4092; + default: return offset + 4; + } +} +/*---------- RIF ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_RIF_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "BIAS"; + case 4: return "RXBBF"; + case 8: return "RXBBF_1M"; + case 12: return "RXBBF_2M"; + case 16: return "SYNTX_MODGAIN"; + case 20: return "SYNTX_VCOCAP"; + case 24: return "LNA"; + case 28: return "RGT"; + case 32: return "RGTHW"; + case 36: return "TXGAIN0"; + case 40: return "TXGAIN1"; + case 44: return "TXGAIN2"; + case 48: return "TXGAIN3"; + case 52: return "RXGAIN0"; + case 56: return "RXGAIN1"; + case 60: return "RXGAIN2"; + case 64: return "RXGAIN3"; + case 68: return "RXGAIN4"; + case 72: return "RXGAIN5"; + case 76: return "RXGAIN6"; + case 80: return "RXGAIN7"; + case 84: return "RXGAIN8"; + case 88: return "RXGAIN9"; + case 92: return "RXGAIN10"; + case 96: return "RXGAIN11"; + case 100: return "RXGAIN12"; + case 104: return "RXGAIN13"; + case 108: return "RXGAIN14"; + case 112: return "RXGAIN15"; + case 116: return "SYNTX_CAL"; + case 120: return "SYNTX0"; + case 124: return "SYNTX1"; + case 128: return "SYNTX2"; + case 132: return "SYNTX3"; + case 136: return "SYNTX4"; + case 140: return "SYNTX5"; + case 144: return "DUTY_CYCLE"; + case 148: return "TXGAIN0_PMU"; + case 152: return "TXGAIN1_PMU"; + case 156: return "TXGAIN2_PMU"; + case 160: return "RX0"; + case 164: return "TIMER0"; + case 168: return "TIMER1"; + case 172: return "TIMER2"; + case 176: return "TIMER3"; + case 180: return "HADM_TIMER0"; + case 184: return "HADM_TIMER1"; + case 188: return "HADM_TIMER2"; + case 192: return "HADM_TIMER3"; + case 196: return "RXDC7"; + case 200: return "SYNTH_CHAN0"; + case 204: return "SYNTH_CHAN1"; + case 208: return "SYNTH_CHAN2"; + case 212: return "SYNTH_CHAN3"; + case 216: return "SYNTH_CHAN4"; + case 220: return "SYNTH_CHAN5"; + case 224: return "ADC_CNTL"; + case 228: return "MODE_CNTL"; + case 232: return "MODE_CNTL2"; + case 236: return "XLNA_XPA_CNTL"; + case 240: return "CAL_CNTL"; + case 244: return "CAL_DONE"; + case 4092: return "ID"; + default: return "unknown CMSDK_RIF offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_RIF_begin_offset() { return 0; } +static inline int CMSDK_RIF_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_RIF_TypeDef); } +static inline uint32_t CMSDK_RIF_next_offset(uint32_t offset) { + switch (offset) { + case 244: return 4092; + default: return offset + 4; + } +} +/*---------- MDM ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_MDM_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "AGCMEAS"; + case 4: return "AGCGAIN"; + case 8: return "DCOFF"; + case 12: return "TIA_FORCE_DCCALRESULTS"; + case 16: return "TIA_FORCE_DCCALRESULTS2"; + case 20: return "TIA_LP_FORCE_DCCALRESULTS"; + case 24: return "TIA_LP_FORCE_DCCALRESULTS2"; + case 28: return "PGA_FORCE_DCCALRESULTS"; + case 32: return "PGA_FORCE_DCCALRESULTS2"; + case 36: return "PGA_LP_FORCE_DCCALRESULTS"; + case 40: return "PGA_LP_FORCE_DCCALRESULTS2"; + case 44: return "NOTCH_FORCE_DCCALRESULTS"; + case 48: return "PGA_CAL_GAIN_FORCE_DCCALRESULTS"; + case 52: return "PGA_CAL_GAIN_FORCE_DCCALRESULTS2"; + case 56: return "IQCORR"; + case 60: return "AGCMEAS_ALT"; + case 64: return "AGCGAIN_ALT"; + case 68: return "XLNA"; + case 72: return "XLNA_ALT"; + case 76: return "AGCSAT"; + case 80: return "AGCSAT_ALT"; + case 84: return "BASELINE"; + case 88: return "BASELINE_ALT"; + case 92: return "MARGIN"; + case 96: return "MARGIN_ALT"; + case 100: return "PWRSTEP"; + case 104: return "PWRSTEP_ALT"; + case 108: return "AGCPWR"; + case 112: return "AGCPWR_ALT"; + case 116: return "AGCPWR2"; + case 120: return "AGCPWR2_ALT"; + case 124: return "AGCTIME"; + case 128: return "AGCTIME_ALT"; + case 132: return "TWOMEG_AGCTIME"; + case 136: return "TWOMEG_AGCTIME_ALT"; + case 140: return "AGCTIME2"; + case 144: return "AGCTIME2_ALT"; + case 148: return "AGCCNTL"; + case 152: return "AGCCNTL_ALT"; + case 156: return "AGCPD"; + case 160: return "AGCPD_ALT"; + case 164: return "AGCDET"; + case 168: return "AGCDET_ALT"; + case 172: return "AGCOFFSET"; + case 176: return "AGCOFFSET_ALT"; + case 180: return "SYNCH"; + case 184: return "SYNCH_ALT"; + case 188: return "TIMETRACK"; + case 192: return "TIMESYNC"; + case 196: return "TIMESYNC_ALT"; + case 200: return "SYNCDEMOD"; + case 204: return "SYNCDEMOD_ALT"; + case 208: return "RESETINITCFO"; + case 212: return "RESETINITCFO_ALT"; + case 216: return "INTMFREQ"; + case 220: return "INTMFREQ_ALT"; + case 224: return "TSTIMEOUT"; + case 228: return "DEMOD"; + case 232: return "DFEWITHFFE"; + case 236: return "DFEWITHOUTFFE"; + case 240: return "TWOMEG_DFEWITHFFE"; + case 244: return "TWOMEG_DFEWITHOUTFFE"; + case 248: return "FREQ"; + case 252: return "FREQLIM"; + case 256: return "LR"; + case 260: return "LR_ALT"; + case 264: return "MIXER"; + case 268: return "ACCESS_ADDRESS"; + case 272: return "MODE"; + case 276: return "DCCAL"; + case 280: return "DCCAL2"; + case 284: return "DCCAL_CTRL"; + case 288: return "TIA_DCCAL"; + case 292: return "TIA_DCCAL2"; + case 296: return "TIA_DCCAL3"; + case 300: return "TIA_DCCAL4"; + case 304: return "PGA_DCCAL"; + case 308: return "PGA_DCCAL2"; + case 312: return "PGA_DCCAL3"; + case 316: return "PGA_DCCAL4"; + case 320: return "PGA_DCCAL5"; + case 324: return "NOTCH_DCCAL"; + case 328: return "NOTCH_DCCAL2"; + case 332: return "NOTCH_DCCAL3"; + case 336: return "DCOFFTRK"; + case 340: return "DCOFFTRK_ALT"; + case 344: return "DCOFFTRK2"; + case 348: return "DCOFFTRK2_ALT"; + case 352: return "DFCNTL"; + case 356: return "DFCNTL_ALT"; + case 360: return "SWANTCTETIME"; + case 364: return "DFTABLE"; + case 368: return "DFSTATUS"; + case 372: return "ANTRX3TO0"; + case 376: return "ANTTX3TO0"; + case 380: return "ANTRX7TO4"; + case 384: return "ANTTX7TO4"; + case 388: return "ANTIDLE"; + case 392: return "ANTID3TO0"; + case 396: return "ANTID7TO4"; + case 400: return "WHT_CTRL"; + case 404: return "DCCALRESULTS"; + case 408: return "DCCALRESULTS2"; + case 412: return "TIA_RETENT_DCCALRESULTS"; + case 416: return "TIA_DCCALRESULTS2"; + case 420: return "TIA_DCCALRESULTS3"; + case 424: return "TIA_LP_RETENT_DCCALRESULTS"; + case 428: return "TIA_LP_DCCALRESULTS2"; + case 432: return "PGA_RETENT_DCCALRESULTS"; + case 436: return "PGA_DCCALRESULTS2"; + case 440: return "PGA_DCCALRESULTS3"; + case 444: return "PGA_LP_RETENT_DCCALRESULTS"; + case 448: return "PGA_LP_DCCALRESULTS2"; + case 452: return "NOTCH_RETENT_DCCALRESULTS"; + case 456: return "NOTCH_DCCALRESULTS2"; + case 460: return "AGCSTATUS"; + case 464: return "MEASFREQ"; + case 468: return "EXPER"; + case 472: return "SPARE0"; + case 476: return "DEBUG"; + case 480: return "LC2LC"; + case 484: return "IRQ"; + case 488: return "IRQM"; + case 492: return "IRQC"; + case 496: return "ERR_INJ"; + case 500: return "DEBUG32"; + case 504: return "DUO"; + case 4092: return "CORE_ID"; + default: return "unknown CMSDK_MDM offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_MDM_begin_offset() { return 0; } +static inline int CMSDK_MDM_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_MDM_TypeDef); } +static inline uint32_t CMSDK_MDM_next_offset(uint32_t offset) { + switch (offset) { + case 504: return 4092; + default: return offset + 4; + } +} +/*---------- AT_APB_PSEQ_PARIS ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_APB_PSEQ_PARIS_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "CTRL0"; + case 4: return "CTRL1"; + case 8: return "RETAIN_ALL_WAKE_MASK"; + case 12: return "HIB_WAKE_MASK"; + case 16: return "BLE_RET_TO_BLE_ACT_WAKE_MASK"; + case 20: return "BLE_RET_TO_CPU_ACT_WAKE_MASK"; + case 24: return "GPIO_WAKE_MASK"; + case 28: return "GPIO_WAKE_TYPE"; + case 32: return "GPIO_WAKE_POL"; + case 36: return "GPIO_WAKE_BOTH_EDGES"; + case 40: return "GPIO_WAKE_STATUS"; + case 44: return "WURX_CONFIG"; + case 48: return "WURX_CONFIG1"; + case 52: return "WURX_CONFIG2"; + case 56: return "GADC_CONFIG"; + case 60: return "XTAL_BITS0"; + case 64: return "XTAL_BITS1"; + case 68: return "OVERRIDES"; + case 72: return "OVERRIDES2"; + case 76: return "OVERRIDES3"; + case 80: return "OVERRIDES4"; + case 84: return "OVERRIDES5"; + case 88: return "SYSRAM_OVERRIDES"; + case 92: return "SYSRAM_OVERRIDES2"; + case 96: return "SYSRAM_OVERRIDES3"; + case 100: return "SYSRAM_OVERRIDES4"; + case 104: return "SYSRAM_OVERRIDES5"; + case 108: return "SYSRAM_OVERRIDES6"; + case 112: return "SYSRAM_OVERRIDES7"; + case 116: return "SYSRAM_OVERRIDES8"; + case 120: return "EMRAM_OVERRIDES"; + case 124: return "EMRAM_OVERRIDES2"; + case 128: return "EMRAM_OVERRIDES3"; + case 132: return "EMRAM_OVERRIDES4"; + case 136: return "EMRAM_OVERRIDES5"; + case 140: return "EMRAM_OVERRIDES6"; + case 144: return "EMRAM_OVERRIDES7"; + case 148: return "EMRAM_OVERRIDES8"; + case 152: return "ICACHE_OVERRIDES"; + case 156: return "ICACHE_OVERRIDES2"; + case 160: return "ICACHE_OVERRIDES3"; + case 164: return "ICACHE_OVERRIDES4"; + case 168: return "ICACHE_OVERRIDES5"; + case 172: return "ICACHE_OVERRIDES6"; + case 176: return "ICACHE_OVERRIDES7"; + case 180: return "ICACHE_OVERRIDES8"; + case 184: return "RRAMCACHE_OVERRIDES"; + case 188: return "RRAMCACHE_OVERRIDES2"; + case 192: return "RRAMCACHE_OVERRIDES3"; + case 196: return "RRAMCACHE_OVERRIDES4"; + case 200: return "RRAMCACHE_OVERRIDES5"; + case 204: return "RRAMCACHE_OVERRIDES6"; + case 208: return "RRAMCACHE_OVERRIDES7"; + case 212: return "RRAMCACHE_OVERRIDES8"; + case 216: return "QSPICACHE_OVERRIDES"; + case 220: return "COUNTER_CONTROL"; + case 224: return "CURRENT_REAL_TIME"; + case 228: return "CURRENT_COUNT_DOWN_TIME"; + case 232: return "INIT_COUNT_DOWN"; + case 236: return "INST_PENDING"; + case 240: return "STATUS"; + case 244: return "PERSISTENT0"; + case 248: return "PERSISTENT1"; + case 252: return "PERSISTENT2"; + case 256: return "PERSISTENT3"; + case 260: return "PERSISTENT4"; + case 264: return "PERSISTENT5"; + case 268: return "PERSISTENT6"; + case 272: return "PERSISTENT7"; + case 276: return "SENSOR_HUB_CONTROL"; + case 280: return "KSMQDEC_CONTROL"; + case 284: return "SPII2C_CONTROL"; + case 288: return "FLASH_CONTROL"; + case 292: return "FLASH_CONTROL2"; + case 296: return "PMU_STATUS"; + case 300: return "PMU_INTERRUPT"; + case 304: return "SYSRAM_WRITE_BLOCK_CFG"; + case 308: return "SYSRAM_SSRS_CFG"; + case 312: return "INTERRUPT_STATUS"; + case 316: return "INTERRUPT_MASK"; + case 320: return "RESET_INTERRUPT"; + case 324: return "FPGA_CFG"; + case 328: return "PLL"; + case 332: return "RADIO_STATUS"; + case 336: return "RRAM_READ_CONFIG_LO"; + case 340: return "RRAM_READ_CONFIG_HI"; + case 344: return "SENSOR_HUB_IMM_BREAKOUT_MASK"; + case 348: return "FSM_TUNINGA"; + case 352: return "FSM_TUNINGB"; + case 356: return "WDOG_CONTROL"; + case 360: return "WDOG_TIMER"; + case 4092: return "CORE_ID"; + default: return "unknown CMSDK_AT_APB_PSEQ_PARIS offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_APB_PSEQ_PARIS_begin_offset() { return 0; } +static inline int CMSDK_AT_APB_PSEQ_PARIS_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_APB_PSEQ_PARIS_TypeDef); } +static inline uint32_t CMSDK_AT_APB_PSEQ_PARIS_next_offset(uint32_t offset) { + switch (offset) { + case 360: return 4092; + default: return offset + 4; + } +} +/*---------- AT_APB_SWD ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_APB_SWD_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "DAP_ADDR_CTRL"; + case 4: return "DAP_WDATA_CTRL"; + case 8: return "SWD_CLK_DIV_CTRL"; + case 12: return "PATTERN_UPPER_CTRL"; + case 16: return "PATTERN_LOWER_CTRL"; + case 20: return "TAIL_DUR"; + case 24: return "PATTERN_DUR"; + case 28: return "DAP_BRIDGE_STATUS"; + case 32: return "DAP_RESP_STATUS"; + case 36: return "RW_CTRL"; + case 40: return "APNDP_CTRL"; + case 44: return "TRIGGER_CTRL"; + case 48: return "DAP_RDATA"; + case 52: return "INTERRUPT_MASK"; + case 56: return "INTERRUPT_STATUS"; + case 60: return "SET_INTERRUPT"; + case 64: return "RESET_INTERRUPT"; + case 68: return "DTOP_BYPASS_CTRL"; + case 72: return "DTOP_BYPASS_STAT"; + case 76: return "DTOP_BYPASS_GPO"; + case 80: return "DTOP_BYPASS_RIF_MODE_CNTL"; + case 84: return "DTOP_BYPASS_RIF_CAL_CNTL"; + case 88: return "DTOP_BYPASS_RIF_RXDC7"; + case 4092: return "CORE_ID"; + default: return "unknown CMSDK_AT_APB_SWD offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_APB_SWD_begin_offset() { return 0; } +static inline int CMSDK_AT_APB_SWD_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_APB_SWD_TypeDef); } +static inline uint32_t CMSDK_AT_APB_SWD_next_offset(uint32_t offset) { + switch (offset) { + case 88: return 4092; + default: return offset + 4; + } +} +/*---------- AT_APB_GADC ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_APB_GADC_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "CTRL"; + case 4: return "CTRL1"; + case 8: return "CH1_DATAPATH_CONFIG"; + case 12: return "CH2_DATAPATH_CONFIG"; + case 16: return "CH3_DATAPATH_CONFIG"; + case 20: return "CH4_DATAPATH_CONFIG"; + case 24: return "CH5_DATAPATH_CONFIG"; + case 28: return "CH6_DATAPATH_CONFIG"; + case 32: return "CH7_DATAPATH_CONFIG"; + case 36: return "CH8_DATAPATH_CONFIG"; + case 40: return "CH9_DATAPATH_CONFIG"; + case 44: return "CH10_DATAPATH_CONFIG"; + case 48: return "CH11_DATAPATH_CONFIG"; + case 52: return "CH12_DATAPATH_CONFIG"; + case 56: return "GAIN_CONFIG0"; + case 60: return "GAIN_CONFIG1"; + case 64: return "DATAPATH_OUTPUT"; + case 68: return "INTERRUPTS"; + case 72: return "INTERRUPT_MASK"; + case 76: return "INTERRUPT_CLEAR"; + case 80: return "FIFO_DBG"; + case 4092: return "CORE_ID"; + default: return "unknown CMSDK_AT_APB_GADC offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_APB_GADC_begin_offset() { return 0; } +static inline int CMSDK_AT_APB_GADC_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_APB_GADC_TypeDef); } +static inline uint32_t CMSDK_AT_APB_GADC_next_offset(uint32_t offset) { + switch (offset) { + case 80: return 4092; + default: return offset + 4; + } +} +/*---------- AT_APB_TRNG ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_APB_TRNG_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "CONTROL"; + case 4: return "STATUS"; + case 8: return "INTERRUPT_STATUS"; + case 12: return "INTERRUPT_MASK"; + case 16: return "SET_INTERRUPT"; + case 20: return "RESET_INTERRUPT"; + case 24: return "TRNG"; + case 4092: return "CORE_ID"; + default: return "unknown CMSDK_AT_APB_TRNG offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_APB_TRNG_begin_offset() { return 0; } +static inline int CMSDK_AT_APB_TRNG_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_APB_TRNG_TypeDef); } +static inline uint32_t CMSDK_AT_APB_TRNG_next_offset(uint32_t offset) { + switch (offset) { + case 24: return 4092; + default: return offset + 4; + } +} +/*---------- AT_APB_RCOS_CAL ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_APB_RCOS_CAL_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "CAL_CTRL"; + case 4: return "SLOW_CLK_SET"; + case 8: return "SLOW_CLK_CNT"; + case 12: return "FAST_CLK_CNT"; + case 16: return "SOURCE_CLK_SEL"; + case 20: return "FORCE_RESET"; + case 24: return "STAT"; + case 28: return "INTERRUPT_STATUS"; + case 32: return "INTERRUPT_MASK"; + case 36: return "SET_INTERRUPT"; + case 40: return "RESET_INTERRUPT"; + case 4092: return "CORE_ID"; + default: return "unknown CMSDK_AT_APB_RCOS_CAL offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_APB_RCOS_CAL_begin_offset() { return 0; } +static inline int CMSDK_AT_APB_RCOS_CAL_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_APB_RCOS_CAL_TypeDef); } +static inline uint32_t CMSDK_AT_APB_RCOS_CAL_next_offset(uint32_t offset) { + switch (offset) { + case 40: return 4092; + default: return offset + 4; + } +} +/*---------- AT_APB_SHUB ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_APB_SHUB_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "SETUP0"; + case 4: return "SETUP1"; + case 8: return "PORT0_SETUP"; + case 12: return "PORT0_SENSOR0_SETUP"; + case 16: return "PORT0_SENSOR1_SETUP"; + case 20: return "PORT0_SENSOR2_SETUP"; + case 24: return "PORT0_SENSOR3_SETUP"; + case 28: return "PORT0_SENSOR4_SETUP"; + case 32: return "PORT0_SENSOR5_SETUP"; + case 36: return "PORT0_SENSOR6_SETUP"; + case 40: return "PORT0_SENSOR7_SETUP"; + case 44: return "PORT0_SPI_ENG0_CTRL"; + case 48: return "PORT0_I2C_IDW_0"; + case 52: return "PORT0_I2C_IDW_1"; + case 56: return "PORT0_I2C_IDW_2"; + case 60: return "PORT0_I2C_IDW_3"; + case 64: return "PORT0_I2C_IDW_4"; + case 68: return "PORT0_I2C_IDW_5"; + case 72: return "PORT0_I2C_IDW_6"; + case 76: return "PORT0_I2C_IDW_7"; + case 80: return "PORT0_I2C_ADDR_0"; + case 84: return "PORT0_I2C_ADDR_1"; + case 88: return "PORT0_I2C_ADDR_2"; + case 92: return "PORT0_I2C_ADDR_3"; + case 96: return "PORT0_I2C_ADDR_4"; + case 100: return "PORT0_I2C_ADDR_5"; + case 104: return "PORT0_I2C_ADDR_6"; + case 108: return "PORT0_I2C_ADDR_7"; + case 112: return "PORT0_I2C_IDR_0"; + case 116: return "PORT0_I2C_IDR_1"; + case 120: return "PORT0_I2C_IDR_2"; + case 124: return "PORT0_I2C_IDR_3"; + case 128: return "PORT0_I2C_IDR_4"; + case 132: return "PORT0_I2C_IDR_5"; + case 136: return "PORT0_I2C_IDR_6"; + case 140: return "PORT0_I2C_IDR_7"; + case 144: return "PORT0_I2C_DAT_CTRL"; + case 148: return "PORT0_I2C_DAT_LAST_CTRL"; + case 152: return "PORT0_ALM0_QUAN_CTRL"; + case 156: return "PORT0_ALM1_QUAN_CTRL"; + case 160: return "PORT0_ALM0_TRIG_CTRL"; + case 164: return "PORT0_ALM1_TRIG_CTRL"; + case 168: return "PORT0_ALM0_THRHLD_MAX_0"; + case 172: return "PORT0_ALM0_THRHLD_MAX_1"; + case 176: return "PORT0_ALM0_THRHLD_MAX_2"; + case 180: return "PORT0_ALM0_THRHLD_MIN_0"; + case 184: return "PORT0_ALM0_THRHLD_MIN_1"; + case 188: return "PORT0_ALM0_THRHLD_MIN_2"; + case 192: return "PORT0_ALM1_THRHLD_MAX_0"; + case 196: return "PORT0_ALM1_THRHLD_MAX_1"; + case 200: return "PORT0_ALM1_THRHLD_MAX_2"; + case 204: return "PORT0_ALM1_THRHLD_MIN_0"; + case 208: return "PORT0_ALM1_THRHLD_MIN_1"; + case 212: return "PORT0_ALM1_THRHLD_MIN_2"; + case 216: return "PORT0_STATUS"; + case 220: return "PORT1_SETUP"; + case 224: return "PORT1_SENSOR0_SETUP"; + case 228: return "PORT1_SPI_ENG0_CTRL"; + case 232: return "PORT1_I2C_IDW_0"; + case 236: return "PORT1_I2C_ADDR_0"; + case 240: return "PORT1_I2C_IDR_0"; + case 244: return "PORT1_I2C_DAT_CTRL"; + case 248: return "PORT1_I2C_DAT_LAST_CTRL"; + case 252: return "PORT1_ALM0_QUAN_CTRL"; + case 256: return "PORT1_ALM0_TRIG_CTRL"; + case 260: return "PORT1_ALM0_THRHLD_MAX_0"; + case 264: return "PORT1_ALM0_THRHLD_MAX_1"; + case 268: return "PORT1_ALM0_THRHLD_MAX_2"; + case 272: return "PORT1_ALM0_THRHLD_MIN_0"; + case 276: return "PORT1_ALM0_THRHLD_MIN_1"; + case 280: return "PORT1_ALM0_THRHLD_MIN_2"; + case 284: return "PORT1_STATUS"; + case 288: return "FLASH_CTRL0"; + case 292: return "FLASH_CTRL1"; + case 296: return "FLASH_CTRL2"; + case 300: return "FLASH_CTRL3"; + case 304: return "FLASH_CTRL4"; + case 308: return "FLASH_STATUS0"; + case 312: return "FLASH_STATUS1"; + case 316: return "SHUB_STATUS0"; + case 320: return "PC_CTRL"; + case 324: return "PC_CTRL2"; + case 328: return "REG7"; + case 332: return "SHUB_SRAM_CLK_SEL"; + case 336: return "REGFILE_SEL"; + case 340: return "REGFILE_REGW"; + case 4092: return "ID"; + default: return "unknown CMSDK_AT_APB_SHUB offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_APB_SHUB_begin_offset() { return 0; } +static inline int CMSDK_AT_APB_SHUB_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_APB_SHUB_TypeDef); } +static inline uint32_t CMSDK_AT_APB_SHUB_next_offset(uint32_t offset) { + switch (offset) { + case 340: return 4092; + default: return offset + 4; + } +} +/*---------- AT_APB_PDM ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_APB_PDM_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "CONTROL"; + case 4: return "FILTER_CONFIG"; + case 8: return "FILTER_CONFIG1"; + case 12: return "GAIN_CONTROL_CONFIG"; + case 16: return "PCM_SAMPLE"; + case 20: return "FIFO_DEBUG"; + case 24: return "INTERRUPTS"; + case 28: return "INTERRUPT_MASK"; + case 32: return "INTERRUPT_CLEAR"; + case 36: return "BUFFER_ACCESS_MODE"; + case 40: return "AUTO_COUNTER"; + case 44: return "BUFFER_DEPTH"; + case 4084: return "CORE_ID"; + case 4088: return "REV_HASH"; + case 4092: return "REV_KEY"; + default: return "unknown CMSDK_AT_APB_PDM offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_APB_PDM_begin_offset() { return 0; } +static inline int CMSDK_AT_APB_PDM_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_APB_PDM_TypeDef); } +static inline uint32_t CMSDK_AT_APB_PDM_next_offset(uint32_t offset) { + switch (offset) { + case 44: return 4084; + default: return offset + 4; + } +} +/*---------- AT_I2S ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_I2S_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "I2S_CTRL0"; + case 4: return "I2S_CTRL1_TX"; + case 8: return "I2S_CTRL1_RX"; + case 12: return "I2S_CTRL2_TX"; + case 16: return "I2S_CTRL2_RX"; + case 20: return "I2S_CTRL3"; + case 24: return "I2S_CTRL4"; + case 28: return "I2S_CTRL5_TX"; + case 32: return "I2S_CTRL5_RX"; + case 36: return "I2S_INTRP_CTRL"; + case 40: return "I2S_PP1_RDATA"; + case 44: return "I2S_PP0_WDATA"; + case 48: return "I2S_PP1_CTRL"; + case 52: return "I2S_PP0_CTRL"; + case 56: return "I2S_IRQ0"; + case 60: return "I2S_IRQM0"; + case 64: return "I2S_IRQS0"; + case 68: return "I2S_IRQC0"; + case 72: return "I2S_IRQ1"; + case 76: return "I2S_IRQM1"; + case 80: return "I2S_IRQS1"; + case 84: return "I2S_IRQC1"; + case 88: return "BUFFER_DEPTH"; + case 92: return "PP_ST"; + case 96: return "I2S_SPARE"; + case 100: return "I2S_DBG"; + case 4092: return "ID"; + default: return "unknown CMSDK_AT_I2S offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_I2S_begin_offset() { return 0; } +static inline int CMSDK_AT_I2S_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_I2S_TypeDef); } +static inline uint32_t CMSDK_AT_I2S_next_offset(uint32_t offset) { + switch (offset) { + case 100: return 4092; + default: return offset + 4; + } +} +/*---------- AT_APB_CLKRSTGEN ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_APB_CLKRSTGEN_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "CLK_BP_CTRL"; + case 4: return "CLK_BP_CTRL_STAT"; + case 8: return "CLK_AUD_CTRL"; + case 12: return "PLL_CTRL"; + case 16: return "USER_RESETS"; + case 20: return "USER_CLK_DISABLES"; + case 24: return "USER_CLK_GATE_FORCE_ON"; + case 28: return "USER_CLK_GATE_CTRL"; + case 32: return "CONFIGURATION"; + case 36: return "CLKSYNC"; + case 4092: return "CORE_ID"; + default: return "unknown CMSDK_AT_APB_CLKRSTGEN offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_APB_CLKRSTGEN_begin_offset() { return 0; } +static inline int CMSDK_AT_APB_CLKRSTGEN_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_APB_CLKRSTGEN_TypeDef); } +static inline uint32_t CMSDK_AT_APB_CLKRSTGEN_next_offset(uint32_t offset) { + switch (offset) { + case 36: return 4092; + default: return offset + 4; + } +} +/*---------- AT_APB_AES ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_APB_AES_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "ALERT_TEST"; + case 4: return "KEY_SHARE0_0"; + case 8: return "KEY_SHARE0_1"; + case 12: return "KEY_SHARE0_2"; + case 16: return "KEY_SHARE0_3"; + case 20: return "KEY_SHARE0_4"; + case 24: return "KEY_SHARE0_5"; + case 28: return "KEY_SHARE0_6"; + case 32: return "KEY_SHARE0_7"; + case 36: return "KEY_SHARE1_0"; + case 40: return "KEY_SHARE1_1"; + case 44: return "KEY_SHARE1_2"; + case 48: return "KEY_SHARE1_3"; + case 52: return "KEY_SHARE1_4"; + case 56: return "KEY_SHARE1_5"; + case 60: return "KEY_SHARE1_6"; + case 64: return "KEY_SHARE1_7"; + case 68: return "IV_0"; + case 72: return "IV_1"; + case 76: return "IV_2"; + case 80: return "IV_3"; + case 84: return "DATA_IN_0"; + case 88: return "DATA_IN_1"; + case 92: return "DATA_IN_2"; + case 96: return "DATA_IN_3"; + case 100: return "DATA_OUT_0"; + case 104: return "DATA_OUT_1"; + case 108: return "DATA_OUT_2"; + case 112: return "DATA_OUT_3"; + case 116: return "CTRL_SHADOWED"; + case 120: return "TRIGGER"; + case 124: return "STATUS"; + case 4084: return "STATUS1"; + case 4088: return "SIDELOAD_CTRL"; + case 4092: return "ID"; + default: return "unknown CMSDK_AT_APB_AES offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_APB_AES_begin_offset() { return 0; } +static inline int CMSDK_AT_APB_AES_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_APB_AES_TypeDef); } +static inline uint32_t CMSDK_AT_APB_AES_next_offset(uint32_t offset) { + switch (offset) { + case 124: return 4084; + default: return offset + 4; + } +} +/*---------- AT_AHB_DMA ----------*/ +/*---------- Field name map ----------*/ +static inline char const *CMSDK_AT_AHB_DMA_offset_to_str(uint32_t offset) { + switch (offset) { + case 0: return "OPMODE"; + case 4: return "CONST_WDATA"; + case 8: return "SRC_ADDR"; + case 12: return "TAR_ADDR"; + case 16: return "SIZE"; + case 20: return "SRC_CTRL"; + case 24: return "TAR_CTRL"; + case 28: return "FIFO_DPTH_ADDR"; + case 32: return "FIFO_PORT_SEL"; + case 36: return "SPI_PORT_SEL"; + case 40: return "ERR_STAT"; + case 44: return "STATUS"; + case 48: return "TOTAL_WRITE_REMAINDER"; + case 52: return "INTERRUPT_STATUS"; + case 56: return "INTERRUPT_MASK"; + case 60: return "SET_INTERRUPT"; + case 64: return "RESET_INTERRUPT"; + case 68: return "CFG_HNONSEC"; + case 72: return "CHAN1_OPMODE"; + case 76: return "CHAN1_CONST_WDATA"; + case 80: return "CHAN1_SRC_ADDR"; + case 84: return "CHAN1_TAR_ADDR"; + case 88: return "CHAN1_SIZE"; + case 92: return "CHAN1_SRC_CTRL"; + case 96: return "CHAN1_TAR_CTRL"; + case 100: return "CHAN1_FIFO_DPTH_ADDR"; + case 104: return "CHAN1_FIFO_PORT_SEL"; + case 108: return "CHAN1_SPI_PORT_SEL"; + case 112: return "CHAN1_ERR_STAT"; + case 116: return "CHAN1_STATUS"; + case 120: return "CHAN1_TOTAL_WRITE_REMAINDER"; + case 124: return "CHAN1_INTERRUPT_STATUS"; + case 128: return "CHAN1_INTERRUPT_MASK"; + case 132: return "CHAN1_SET_INTERRUPT"; + case 136: return "CHAN1_RESET_INTERRUPT"; + case 140: return "CHAN1_CFG_HNONSEC"; + case 144: return "CHAN2_OPMODE"; + case 148: return "CHAN2_CONST_WDATA"; + case 152: return "CHAN2_SRC_ADDR"; + case 156: return "CHAN2_TAR_ADDR"; + case 160: return "CHAN2_SIZE"; + case 164: return "CHAN2_SRC_CTRL"; + case 168: return "CHAN2_TAR_CTRL"; + case 172: return "CHAN2_FIFO_DPTH_ADDR"; + case 176: return "CHAN2_FIFO_PORT_SEL"; + case 180: return "CHAN2_SPI_PORT_SEL"; + case 184: return "CHAN2_ERR_STAT"; + case 188: return "CHAN2_STATUS"; + case 192: return "CHAN2_TOTAL_WRITE_REMAINDER"; + case 196: return "CHAN2_INTERRUPT_STATUS"; + case 200: return "CHAN2_INTERRUPT_MASK"; + case 204: return "CHAN2_SET_INTERRUPT"; + case 208: return "CHAN2_RESET_INTERRUPT"; + case 212: return "CHAN2_CFG_HNONSEC"; + case 216: return "CHAN3_OPMODE"; + case 220: return "CHAN3_CONST_WDATA"; + case 224: return "CHAN3_SRC_ADDR"; + case 228: return "CHAN3_TAR_ADDR"; + case 232: return "CHAN3_SIZE"; + case 236: return "CHAN3_SRC_CTRL"; + case 240: return "CHAN3_TAR_CTRL"; + case 244: return "CHAN3_FIFO_DPTH_ADDR"; + case 248: return "CHAN3_FIFO_PORT_SEL"; + case 252: return "CHAN3_SPI_PORT_SEL"; + case 256: return "CHAN3_ERR_STAT"; + case 260: return "CHAN3_STATUS"; + case 264: return "CHAN3_TOTAL_WRITE_REMAINDER"; + case 268: return "CHAN3_INTERRUPT_STATUS"; + case 272: return "CHAN3_INTERRUPT_MASK"; + case 276: return "CHAN3_SET_INTERRUPT"; + case 280: return "CHAN3_RESET_INTERRUPT"; + case 284: return "CHAN3_CFG_HNONSEC"; + case 288: return "ERR_INTERRUPT_DLY"; + case 292: return "ARBITER_CTRL"; + case 296: return "ARBITER_GRANT_STAT"; + case 300: return "DIAGCNTL"; + case 4092: return "ID"; + default: return "unknown CMSDK_AT_AHB_DMA offset"; + } +} + +/*---------- Iterator ----------*/ +static inline uint32_t CMSDK_AT_AHB_DMA_begin_offset() { return 0; } +static inline int CMSDK_AT_AHB_DMA_end_offset(uint32_t offset) { return offset >= sizeof(CMSDK_AT_AHB_DMA_TypeDef); } +static inline uint32_t CMSDK_AT_AHB_DMA_next_offset(uint32_t offset) { + switch (offset) { + case 300: return 4092; + default: return offset + 4; + } +} + + + + /*------------ ALL BLOCKS ------------*/ +typedef struct block_utils_s { + struct { + char const *name; + uint32_t addr; + } meta; + struct { + uint32_t (*begin)(void); + int (*end)(uint32_t offset); + uint32_t (*next)(uint32_t offset); + } offset_iter; + char const *(*offset_to_str)(uint32_t offset); +} block_utils_t; + + +static inline block_utils_t const *all_blocks(size_t *num_blocks) { + static const block_utils_t blocks[] = { + {{ .name = "AT_UART0_NONSECURE", .addr = 0x40144000 }, { .begin = CMSDK_AT_APB_UART_begin_offset, .end = CMSDK_AT_APB_UART_end_offset, .next = CMSDK_AT_APB_UART_next_offset}, .offset_to_str = CMSDK_AT_APB_UART_offset_to_str }, + {{ .name = "KSM_NONSECURE", .addr = 0x4014a000 }, { .begin = CMSDK_AT_APB_KSM_begin_offset, .end = CMSDK_AT_APB_KSM_end_offset, .next = CMSDK_AT_APB_KSM_next_offset}, .offset_to_str = CMSDK_AT_APB_KSM_offset_to_str }, + {{ .name = "WRPR0_NONSECURE", .addr = 0x40143000 }, { .begin = CMSDK_AT_APB_WRPR_PINS_begin_offset, .end = CMSDK_AT_APB_WRPR_PINS_end_offset, .next = CMSDK_AT_APB_WRPR_PINS_next_offset}, .offset_to_str = CMSDK_AT_APB_WRPR_PINS_offset_to_str }, + {{ .name = "CLKRSTGEN_NONSECURE", .addr = 0x40166000 }, { .begin = CMSDK_AT_APB_CLKRSTGEN_begin_offset, .end = CMSDK_AT_APB_CLKRSTGEN_end_offset, .next = CMSDK_AT_APB_CLKRSTGEN_next_offset}, .offset_to_str = CMSDK_AT_APB_CLKRSTGEN_offset_to_str }, + {{ .name = "RCOS_CAL_NONSECURE", .addr = 0x4015c000 }, { .begin = CMSDK_AT_APB_RCOS_CAL_begin_offset, .end = CMSDK_AT_APB_RCOS_CAL_end_offset, .next = CMSDK_AT_APB_RCOS_CAL_next_offset}, .offset_to_str = CMSDK_AT_APB_RCOS_CAL_offset_to_str }, + {{ .name = "TRNG_NONSECURE", .addr = 0x4015b000 }, { .begin = CMSDK_AT_APB_TRNG_begin_offset, .end = CMSDK_AT_APB_TRNG_end_offset, .next = CMSDK_AT_APB_TRNG_next_offset}, .offset_to_str = CMSDK_AT_APB_TRNG_offset_to_str }, + {{ .name = "RIF_NONSECURE", .addr = 0x40154000 }, { .begin = CMSDK_RIF_begin_offset, .end = CMSDK_RIF_end_offset, .next = CMSDK_RIF_next_offset}, .offset_to_str = CMSDK_RIF_offset_to_str }, + {{ .name = "AT_DMA_NONSECURE", .addr = 0x40170000 }, { .begin = CMSDK_AT_AHB_DMA_begin_offset, .end = CMSDK_AT_AHB_DMA_end_offset, .next = CMSDK_AT_AHB_DMA_next_offset}, .offset_to_str = CMSDK_AT_AHB_DMA_offset_to_str }, + {{ .name = "AES_NONSECURE", .addr = 0x40167000 }, { .begin = CMSDK_AT_APB_AES_begin_offset, .end = CMSDK_AT_APB_AES_end_offset, .next = CMSDK_AT_APB_AES_next_offset}, .offset_to_str = CMSDK_AT_APB_AES_offset_to_str }, + {{ .name = "WRPR1_NONSECURE", .addr = 0x40153000 }, { .begin = CMSDK_AT_APB_WRPR_SHORT_begin_offset, .end = CMSDK_AT_APB_WRPR_SHORT_end_offset, .next = CMSDK_AT_APB_WRPR_SHORT_next_offset}, .offset_to_str = CMSDK_AT_APB_WRPR_SHORT_offset_to_str }, + {{ .name = "SHUB_NONSECURE", .addr = 0x4015d000 }, { .begin = CMSDK_AT_APB_SHUB_begin_offset, .end = CMSDK_AT_APB_SHUB_end_offset, .next = CMSDK_AT_APB_SHUB_next_offset}, .offset_to_str = CMSDK_AT_APB_SHUB_offset_to_str }, + {{ .name = "QDEC_NONSECURE", .addr = 0x4014c000 }, { .begin = CMSDK_AT_APB_QDEC_begin_offset, .end = CMSDK_AT_APB_QDEC_end_offset, .next = CMSDK_AT_APB_QDEC_next_offset}, .offset_to_str = CMSDK_AT_APB_QDEC_offset_to_str }, + {{ .name = "I2C0_NONSECURE", .addr = 0x40150000 }, { .begin = CMSDK_AT_APB_I2C_begin_offset, .end = CMSDK_AT_APB_I2C_end_offset, .next = CMSDK_AT_APB_I2C_next_offset}, .offset_to_str = CMSDK_AT_APB_I2C_offset_to_str }, + {{ .name = "PDM0_NONSECURE", .addr = 0x40160000 }, { .begin = CMSDK_AT_APB_PDM_begin_offset, .end = CMSDK_AT_APB_PDM_end_offset, .next = CMSDK_AT_APB_PDM_next_offset}, .offset_to_str = CMSDK_AT_APB_PDM_offset_to_str }, + {{ .name = "AT_PRRF_NONSECURE", .addr = 0x1ffe00 }, { .begin = CMSDK_AT_AHB_PRRF_begin_offset, .end = CMSDK_AT_AHB_PRRF_end_offset, .next = CMSDK_AT_AHB_PRRF_next_offset}, .offset_to_str = CMSDK_AT_AHB_PRRF_offset_to_str }, + {{ .name = "GADC_NONSECURE", .addr = 0x4015a000 }, { .begin = CMSDK_AT_APB_GADC_begin_offset, .end = CMSDK_AT_APB_GADC_end_offset, .next = CMSDK_AT_APB_GADC_next_offset}, .offset_to_str = CMSDK_AT_APB_GADC_offset_to_str }, + {{ .name = "SWD_NONSECURE", .addr = 0x40159000 }, { .begin = CMSDK_AT_APB_SWD_begin_offset, .end = CMSDK_AT_APB_SWD_end_offset, .next = CMSDK_AT_APB_SWD_next_offset}, .offset_to_str = CMSDK_AT_APB_SWD_offset_to_str }, + {{ .name = "SLWTIMER_NONSECURE", .addr = 0x4014e000 }, { .begin = CMSDK_AT_APB_SLWTIMER_begin_offset, .end = CMSDK_AT_APB_SLWTIMER_end_offset, .next = CMSDK_AT_APB_SLWTIMER_next_offset}, .offset_to_str = CMSDK_AT_APB_SLWTIMER_offset_to_str }, + {{ .name = "I2S_NONSECURE", .addr = 0x40165000 }, { .begin = CMSDK_AT_I2S_begin_offset, .end = CMSDK_AT_I2S_end_offset, .next = CMSDK_AT_I2S_next_offset}, .offset_to_str = CMSDK_AT_I2S_offset_to_str }, + {{ .name = "QSPI_NONSECURE", .addr = 0x4014f000 }, { .begin = CMSDK_AT_APB_QSPI_begin_offset, .end = CMSDK_AT_APB_QSPI_end_offset, .next = CMSDK_AT_APB_QSPI_next_offset}, .offset_to_str = CMSDK_AT_APB_QSPI_offset_to_str }, + {{ .name = "NVM_NONSECURE", .addr = 0x40152000 }, { .begin = CMSDK_AT_APB_TSMC_NVM_begin_offset, .end = CMSDK_AT_APB_TSMC_NVM_end_offset, .next = CMSDK_AT_APB_TSMC_NVM_next_offset}, .offset_to_str = CMSDK_AT_APB_TSMC_NVM_offset_to_str }, + {{ .name = "SPI0_NONSECURE", .addr = 0x40147000 }, { .begin = CMSDK_AT_APB_SPI_begin_offset, .end = CMSDK_AT_APB_SPI_end_offset, .next = CMSDK_AT_APB_SPI_next_offset}, .offset_to_str = CMSDK_AT_APB_SPI_offset_to_str }, + {{ .name = "SHA2_NONSECURE", .addr = 0x40103000 }, { .begin = CMSDK_AT_AHB_SHA2_begin_offset, .end = CMSDK_AT_AHB_SHA2_end_offset, .next = CMSDK_AT_AHB_SHA2_next_offset}, .offset_to_str = CMSDK_AT_AHB_SHA2_offset_to_str }, + {{ .name = "MDM_NONSECURE", .addr = 0x40156000 }, { .begin = CMSDK_MDM_begin_offset, .end = CMSDK_MDM_end_offset, .next = CMSDK_MDM_next_offset}, .offset_to_str = CMSDK_MDM_offset_to_str }, + {{ .name = "PWM_NONSECURE", .addr = 0x40146000 }, { .begin = CMSDK_AT_APB_PWM_begin_offset, .end = CMSDK_AT_APB_PWM_end_offset, .next = CMSDK_AT_APB_PWM_next_offset}, .offset_to_str = CMSDK_AT_APB_PWM_offset_to_str }, + {{ .name = "PSEQ_NONSECURE", .addr = 0x40158000 }, { .begin = CMSDK_AT_APB_PSEQ_PARIS_begin_offset, .end = CMSDK_AT_APB_PSEQ_PARIS_end_offset, .next = CMSDK_AT_APB_PSEQ_PARIS_next_offset}, .offset_to_str = CMSDK_AT_APB_PSEQ_PARIS_offset_to_str } + }; + *num_blocks = sizeof(blocks)/sizeof(blocks[0]); + return blocks; +} + +#define CMSDK_BLOCK_ADDR_MASK 0xFFF + +/** @} end of at_base_addr_utils */ diff --git a/ATM33xx-5/include/reg/mdm_macro.h b/ATM33xx-5/include/reg/mdm_macro.h new file mode 100644 index 0000000..4a8825b --- /dev/null +++ b/ATM33xx-5/include/reg/mdm_macro.h @@ -0,0 +1,15938 @@ +/* */ +/* File: mdm_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic mdm_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_MDM_REGS_CORE_H__ +#define __REG_MDM_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup MDM_REGS_CORE mdm_regs_core + * @ingroup AT_REG + * @brief mdm_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::MDM_agcmeas */ +/** + * @defgroup mdm_regs_core_agcmeas agcmeas + * @brief Power measurements definitions. + * @{ + */ +#ifndef __MDM_AGCMEAS_MACRO__ +#define __MDM_AGCMEAS_MACRO__ + +/* macros for field rssi_offset */ +/** + * @defgroup mdm_regs_core_rssi_offset_field rssi_offset_field + * @brief macros for field rssi_offset + * @details RSSI = rxgain - (measured_power after RXFIR) plus rssi_offset. Signed. Register replicated for 2 Mb/s + * @{ + */ +#define MDM_AGCMEAS__RSSI_OFFSET__SHIFT 0 +#define MDM_AGCMEAS__RSSI_OFFSET__WIDTH 8 +#define MDM_AGCMEAS__RSSI_OFFSET__MASK 0x000000ffU +#define MDM_AGCMEAS__RSSI_OFFSET__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_AGCMEAS__RSSI_OFFSET__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_AGCMEAS__RSSI_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_AGCMEAS__RSSI_OFFSET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define MDM_AGCMEAS__RSSI_OFFSET__RESET_VALUE 0x00000011U +/** @} */ + +/* macros for field det_min */ +/** + * @defgroup mdm_regs_core_det_min_field det_min_field + * @brief macros for field det_min + * @details Signed, relative to full scale agc filter output. Lowest allowed inband power measurement 7'h4d = -51. Register replicated for 2 Mb/s + * @{ + */ +#define MDM_AGCMEAS__DET_MIN__SHIFT 8 +#define MDM_AGCMEAS__DET_MIN__WIDTH 7 +#define MDM_AGCMEAS__DET_MIN__MASK 0x00007f00U +#define MDM_AGCMEAS__DET_MIN__READ(src) (((uint32_t)(src) & 0x00007f00U) >> 8) +#define MDM_AGCMEAS__DET_MIN__WRITE(src) (((uint32_t)(src) << 8) & 0x00007f00U) +#define MDM_AGCMEAS__DET_MIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007f00U) | (((uint32_t)(src) <<\ + 8) & 0x00007f00U) +#define MDM_AGCMEAS__DET_MIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00007f00U))) +#define MDM_AGCMEAS__DET_MIN__RESET_VALUE 0x0000004dU +/** @} */ + +/* macros for field twomeg_rssi_offset */ +/** + * @defgroup mdm_regs_core_twomeg_rssi_offset_field twomeg_rssi_offset_field + * @brief macros for field twomeg_rssi_offset + * @details RSSI = rxgain - (measured_power after RXFIR) plus rssi_offset. 2 Mb/s version of register. + * @{ + */ +#define MDM_AGCMEAS__TWOMEG_RSSI_OFFSET__SHIFT 15 +#define MDM_AGCMEAS__TWOMEG_RSSI_OFFSET__WIDTH 8 +#define MDM_AGCMEAS__TWOMEG_RSSI_OFFSET__MASK 0x007f8000U +#define MDM_AGCMEAS__TWOMEG_RSSI_OFFSET__READ(src) \ + (((uint32_t)(src)\ + & 0x007f8000U) >> 15) +#define MDM_AGCMEAS__TWOMEG_RSSI_OFFSET__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x007f8000U) +#define MDM_AGCMEAS__TWOMEG_RSSI_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007f8000U) | (((uint32_t)(src) <<\ + 15) & 0x007f8000U) +#define MDM_AGCMEAS__TWOMEG_RSSI_OFFSET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x007f8000U))) +#define MDM_AGCMEAS__TWOMEG_RSSI_OFFSET__RESET_VALUE 0x00000011U +/** @} */ + +/* macros for field twomeg_det_min */ +/** + * @defgroup mdm_regs_core_twomeg_det_min_field twomeg_det_min_field + * @brief macros for field twomeg_det_min + * @details Signed, relative to full scale agc filter output. Lowest allowed inband power measurement 7'h50 = -48. 2 Mb/s version of this register + * @{ + */ +#define MDM_AGCMEAS__TWOMEG_DET_MIN__SHIFT 23 +#define MDM_AGCMEAS__TWOMEG_DET_MIN__WIDTH 7 +#define MDM_AGCMEAS__TWOMEG_DET_MIN__MASK 0x3f800000U +#define MDM_AGCMEAS__TWOMEG_DET_MIN__READ(src) \ + (((uint32_t)(src)\ + & 0x3f800000U) >> 23) +#define MDM_AGCMEAS__TWOMEG_DET_MIN__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x3f800000U) +#define MDM_AGCMEAS__TWOMEG_DET_MIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f800000U) | (((uint32_t)(src) <<\ + 23) & 0x3f800000U) +#define MDM_AGCMEAS__TWOMEG_DET_MIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x3f800000U))) +#define MDM_AGCMEAS__TWOMEG_DET_MIN__RESET_VALUE 0x00000050U +/** @} */ +#define MDM_AGCMEAS__TYPE uint32_t +#define MDM_AGCMEAS__READ 0x3fffffffU +#define MDM_AGCMEAS__WRITE 0x3fffffffU +#define MDM_AGCMEAS__PRESERVED 0x00000000U +#define MDM_AGCMEAS__RESET_VALUE 0x2808cd11U + +#endif /* __MDM_AGCMEAS_MACRO__ */ + +/** @} end of agcmeas */ + +/* macros for BlueprintGlobalNameSpace::MDM_agcgain */ +/** + * @defgroup mdm_regs_core_agcgain agcgain + * @brief Gain settings definitions. + * @{ + */ +#ifndef __MDM_AGCGAIN_MACRO__ +#define __MDM_AGCGAIN_MACRO__ + +/* macros for field start */ +/** + * @defgroup mdm_regs_core_start_field start_field + * @brief macros for field start + * @details RX gain to use at start of packet search + * @{ + */ +#define MDM_AGCGAIN__START__SHIFT 0 +#define MDM_AGCGAIN__START__WIDTH 7 +#define MDM_AGCGAIN__START__MASK 0x0000007fU +#define MDM_AGCGAIN__START__READ(src) ((uint32_t)(src) & 0x0000007fU) +#define MDM_AGCGAIN__START__WRITE(src) ((uint32_t)(src) & 0x0000007fU) +#define MDM_AGCGAIN__START__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define MDM_AGCGAIN__START__VERIFY(src) (!(((uint32_t)(src) & ~0x0000007fU))) +#define MDM_AGCGAIN__START__RESET_VALUE 0x0000004cU +/** @} */ + +/* macros for field rfin_pd_quick_drop */ +/** + * @defgroup mdm_regs_core_rfin_pd_quick_drop_field rfin_pd_quick_drop_field + * @brief macros for field rfin_pd_quick_drop + * @details Gain drop in dB when rfin peak detect indicated + * @{ + */ +#define MDM_AGCGAIN__RFIN_PD_QUICK_DROP__SHIFT 14 +#define MDM_AGCGAIN__RFIN_PD_QUICK_DROP__WIDTH 7 +#define MDM_AGCGAIN__RFIN_PD_QUICK_DROP__MASK 0x001fc000U +#define MDM_AGCGAIN__RFIN_PD_QUICK_DROP__READ(src) \ + (((uint32_t)(src)\ + & 0x001fc000U) >> 14) +#define MDM_AGCGAIN__RFIN_PD_QUICK_DROP__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x001fc000U) +#define MDM_AGCGAIN__RFIN_PD_QUICK_DROP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001fc000U) | (((uint32_t)(src) <<\ + 14) & 0x001fc000U) +#define MDM_AGCGAIN__RFIN_PD_QUICK_DROP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x001fc000U))) +#define MDM_AGCGAIN__RFIN_PD_QUICK_DROP__RESET_VALUE 0x00000045U +/** @} */ + +/* macros for field tia_quick_drop */ +/** + * @defgroup mdm_regs_core_tia_quick_drop_field tia_quick_drop_field + * @brief macros for field tia_quick_drop + * @details Gain drop in dB when peak detect indicated + * @{ + */ +#define MDM_AGCGAIN__TIA_QUICK_DROP__SHIFT 21 +#define MDM_AGCGAIN__TIA_QUICK_DROP__WIDTH 7 +#define MDM_AGCGAIN__TIA_QUICK_DROP__MASK 0x0fe00000U +#define MDM_AGCGAIN__TIA_QUICK_DROP__READ(src) \ + (((uint32_t)(src)\ + & 0x0fe00000U) >> 21) +#define MDM_AGCGAIN__TIA_QUICK_DROP__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x0fe00000U) +#define MDM_AGCGAIN__TIA_QUICK_DROP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fe00000U) | (((uint32_t)(src) <<\ + 21) & 0x0fe00000U) +#define MDM_AGCGAIN__TIA_QUICK_DROP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x0fe00000U))) +#define MDM_AGCGAIN__TIA_QUICK_DROP__RESET_VALUE 0x00000036U +/** @} */ +#define MDM_AGCGAIN__TYPE uint32_t +#define MDM_AGCGAIN__READ 0x0fffc07fU +#define MDM_AGCGAIN__WRITE 0x0fffc07fU +#define MDM_AGCGAIN__PRESERVED 0x00000000U +#define MDM_AGCGAIN__RESET_VALUE 0x06d1404cU + +#endif /* __MDM_AGCGAIN_MACRO__ */ + +/** @} end of agcgain */ + +/* macros for BlueprintGlobalNameSpace::MDM_dcoff */ +/** + * @defgroup mdm_regs_core_dcoff dcoff + * @brief DC Offset forcing definitions. + * @{ + */ +#ifndef __MDM_DCOFF_MACRO__ +#define __MDM_DCOFF_MACRO__ + +/* macros for field force */ +/** + * @defgroup mdm_regs_core_force_field force_field + * @brief macros for field force + * @details If set, modem will subtract the forced_i and forced_q values after the ADC. + * @{ + */ +#define MDM_DCOFF__FORCE__SHIFT 0 +#define MDM_DCOFF__FORCE__WIDTH 1 +#define MDM_DCOFF__FORCE__MASK 0x00000001U +#define MDM_DCOFF__FORCE__READ(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_DCOFF__FORCE__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_DCOFF__FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define MDM_DCOFF__FORCE__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define MDM_DCOFF__FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_DCOFF__FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_DCOFF__FORCE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field forced_i */ +/** + * @defgroup mdm_regs_core_forced_i_field forced_i_field + * @brief macros for field forced_i + * @details Signed, in units of ADC LSBs + * @{ + */ +#define MDM_DCOFF__FORCED_I__SHIFT 1 +#define MDM_DCOFF__FORCED_I__WIDTH 8 +#define MDM_DCOFF__FORCED_I__MASK 0x000001feU +#define MDM_DCOFF__FORCED_I__READ(src) (((uint32_t)(src) & 0x000001feU) >> 1) +#define MDM_DCOFF__FORCED_I__WRITE(src) (((uint32_t)(src) << 1) & 0x000001feU) +#define MDM_DCOFF__FORCED_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((uint32_t)(src) <<\ + 1) & 0x000001feU) +#define MDM_DCOFF__FORCED_I__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000001feU))) +#define MDM_DCOFF__FORCED_I__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field forced_q */ +/** + * @defgroup mdm_regs_core_forced_q_field forced_q_field + * @brief macros for field forced_q + * @details Signed, in units of ADC LSBs + * @{ + */ +#define MDM_DCOFF__FORCED_Q__SHIFT 9 +#define MDM_DCOFF__FORCED_Q__WIDTH 8 +#define MDM_DCOFF__FORCED_Q__MASK 0x0001fe00U +#define MDM_DCOFF__FORCED_Q__READ(src) (((uint32_t)(src) & 0x0001fe00U) >> 9) +#define MDM_DCOFF__FORCED_Q__WRITE(src) (((uint32_t)(src) << 9) & 0x0001fe00U) +#define MDM_DCOFF__FORCED_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0001fe00U) +#define MDM_DCOFF__FORCED_Q__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0001fe00U))) +#define MDM_DCOFF__FORCED_Q__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_DCOFF__TYPE uint32_t +#define MDM_DCOFF__READ 0x0001ffffU +#define MDM_DCOFF__WRITE 0x0001ffffU +#define MDM_DCOFF__PRESERVED 0x00000000U +#define MDM_DCOFF__RESET_VALUE 0x00000001U + +#endif /* __MDM_DCOFF_MACRO__ */ + +/** @} end of dcoff */ + +/* macros for BlueprintGlobalNameSpace::MDM_tia_force_dccalresults */ +/** + * @defgroup mdm_regs_core_tia_force_dccalresults tia_force_dccalresults + * @brief Force DC offset calibration results for TIA for paris definitions. + * @{ + */ +#ifndef __MDM_TIA_FORCE_DCCALRESULTS_MACRO__ +#define __MDM_TIA_FORCE_DCCALRESULTS_MACRO__ + +/* macros for field q_off */ +/** + * @defgroup mdm_regs_core_q_off_field q_off_field + * @brief macros for field q_off + * @details forced TIA Q offset + * @{ + */ +#define MDM_TIA_FORCE_DCCALRESULTS__Q_OFF__SHIFT 0 +#define MDM_TIA_FORCE_DCCALRESULTS__Q_OFF__WIDTH 8 +#define MDM_TIA_FORCE_DCCALRESULTS__Q_OFF__MASK 0x000000ffU +#define MDM_TIA_FORCE_DCCALRESULTS__Q_OFF__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_TIA_FORCE_DCCALRESULTS__Q_OFF__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_TIA_FORCE_DCCALRESULTS__Q_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_TIA_FORCE_DCCALRESULTS__Q_OFF__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define MDM_TIA_FORCE_DCCALRESULTS__Q_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field i_off */ +/** + * @defgroup mdm_regs_core_i_off_field i_off_field + * @brief macros for field i_off + * @details forced TIA I offset + * @{ + */ +#define MDM_TIA_FORCE_DCCALRESULTS__I_OFF__SHIFT 8 +#define MDM_TIA_FORCE_DCCALRESULTS__I_OFF__WIDTH 8 +#define MDM_TIA_FORCE_DCCALRESULTS__I_OFF__MASK 0x0000ff00U +#define MDM_TIA_FORCE_DCCALRESULTS__I_OFF__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_TIA_FORCE_DCCALRESULTS__I_OFF__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define MDM_TIA_FORCE_DCCALRESULTS__I_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MDM_TIA_FORCE_DCCALRESULTS__I_OFF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define MDM_TIA_FORCE_DCCALRESULTS__I_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bb2gain */ +/** + * @defgroup mdm_regs_core_bb2gain_field bb2gain_field + * @brief macros for field bb2gain + * @details bb2gain value used in TIA cal + * @{ + */ +#define MDM_TIA_FORCE_DCCALRESULTS__BB2GAIN__SHIFT 16 +#define MDM_TIA_FORCE_DCCALRESULTS__BB2GAIN__WIDTH 5 +#define MDM_TIA_FORCE_DCCALRESULTS__BB2GAIN__MASK 0x001f0000U +#define MDM_TIA_FORCE_DCCALRESULTS__BB2GAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x001f0000U) >> 16) +#define MDM_TIA_FORCE_DCCALRESULTS__BB2GAIN__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x001f0000U) +#define MDM_TIA_FORCE_DCCALRESULTS__BB2GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((uint32_t)(src) <<\ + 16) & 0x001f0000U) +#define MDM_TIA_FORCE_DCCALRESULTS__BB2GAIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x001f0000U))) +#define MDM_TIA_FORCE_DCCALRESULTS__BB2GAIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field force */ +/** + * @defgroup mdm_regs_core_force_field force_field + * @brief macros for field force + * @details force to use offset in this register + * @{ + */ +#define MDM_TIA_FORCE_DCCALRESULTS__FORCE__SHIFT 31 +#define MDM_TIA_FORCE_DCCALRESULTS__FORCE__WIDTH 1 +#define MDM_TIA_FORCE_DCCALRESULTS__FORCE__MASK 0x80000000U +#define MDM_TIA_FORCE_DCCALRESULTS__FORCE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_TIA_FORCE_DCCALRESULTS__FORCE__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define MDM_TIA_FORCE_DCCALRESULTS__FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define MDM_TIA_FORCE_DCCALRESULTS__FORCE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define MDM_TIA_FORCE_DCCALRESULTS__FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_TIA_FORCE_DCCALRESULTS__FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_TIA_FORCE_DCCALRESULTS__FORCE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_TIA_FORCE_DCCALRESULTS__TYPE uint32_t +#define MDM_TIA_FORCE_DCCALRESULTS__READ 0x801fffffU +#define MDM_TIA_FORCE_DCCALRESULTS__WRITE 0x801fffffU +#define MDM_TIA_FORCE_DCCALRESULTS__PRESERVED 0x00000000U +#define MDM_TIA_FORCE_DCCALRESULTS__RESET_VALUE 0x00000000U + +#endif /* __MDM_TIA_FORCE_DCCALRESULTS_MACRO__ */ + +/** @} end of tia_force_dccalresults */ + +/* macros for BlueprintGlobalNameSpace::MDM_tia_force_dccalresults2 */ +/** + * @defgroup mdm_regs_core_tia_force_dccalresults2 tia_force_dccalresults2 + * @brief Force DC offset calibration results for TIA for paris definitions. + * @{ + */ +#ifndef __MDM_TIA_FORCE_DCCALRESULTS2_MACRO__ +#define __MDM_TIA_FORCE_DCCALRESULTS2_MACRO__ + +/* macros for field avg_q */ +/** + * @defgroup mdm_regs_core_avg_q_field avg_q_field + * @brief macros for field avg_q + * @details calculated average of ADC Q samples + * @{ + */ +#define MDM_TIA_FORCE_DCCALRESULTS2__AVG_Q__SHIFT 0 +#define MDM_TIA_FORCE_DCCALRESULTS2__AVG_Q__WIDTH 8 +#define MDM_TIA_FORCE_DCCALRESULTS2__AVG_Q__MASK 0x000000ffU +#define MDM_TIA_FORCE_DCCALRESULTS2__AVG_Q__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_TIA_FORCE_DCCALRESULTS2__AVG_Q__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_TIA_FORCE_DCCALRESULTS2__AVG_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_TIA_FORCE_DCCALRESULTS2__AVG_Q__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define MDM_TIA_FORCE_DCCALRESULTS2__AVG_Q__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field avg_i */ +/** + * @defgroup mdm_regs_core_avg_i_field avg_i_field + * @brief macros for field avg_i + * @details calculated average of ADC I samples + * @{ + */ +#define MDM_TIA_FORCE_DCCALRESULTS2__AVG_I__SHIFT 8 +#define MDM_TIA_FORCE_DCCALRESULTS2__AVG_I__WIDTH 8 +#define MDM_TIA_FORCE_DCCALRESULTS2__AVG_I__MASK 0x0000ff00U +#define MDM_TIA_FORCE_DCCALRESULTS2__AVG_I__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_TIA_FORCE_DCCALRESULTS2__AVG_I__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define MDM_TIA_FORCE_DCCALRESULTS2__AVG_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MDM_TIA_FORCE_DCCALRESULTS2__AVG_I__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define MDM_TIA_FORCE_DCCALRESULTS2__AVG_I__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field force */ +/** + * @defgroup mdm_regs_core_force_field force_field + * @brief macros for field force + * @details force to use average in this register + * @{ + */ +#define MDM_TIA_FORCE_DCCALRESULTS2__FORCE__SHIFT 31 +#define MDM_TIA_FORCE_DCCALRESULTS2__FORCE__WIDTH 1 +#define MDM_TIA_FORCE_DCCALRESULTS2__FORCE__MASK 0x80000000U +#define MDM_TIA_FORCE_DCCALRESULTS2__FORCE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_TIA_FORCE_DCCALRESULTS2__FORCE__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define MDM_TIA_FORCE_DCCALRESULTS2__FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define MDM_TIA_FORCE_DCCALRESULTS2__FORCE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define MDM_TIA_FORCE_DCCALRESULTS2__FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_TIA_FORCE_DCCALRESULTS2__FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_TIA_FORCE_DCCALRESULTS2__FORCE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_TIA_FORCE_DCCALRESULTS2__TYPE uint32_t +#define MDM_TIA_FORCE_DCCALRESULTS2__READ 0x8000ffffU +#define MDM_TIA_FORCE_DCCALRESULTS2__WRITE 0x8000ffffU +#define MDM_TIA_FORCE_DCCALRESULTS2__PRESERVED 0x00000000U +#define MDM_TIA_FORCE_DCCALRESULTS2__RESET_VALUE 0x00000000U + +#endif /* __MDM_TIA_FORCE_DCCALRESULTS2_MACRO__ */ + +/** @} end of tia_force_dccalresults2 */ + +/* macros for BlueprintGlobalNameSpace::MDM_tia_lp_force_dccalresults */ +/** + * @defgroup mdm_regs_core_tia_lp_force_dccalresults tia_lp_force_dccalresults + * @brief Force DC offset calibration results for TIA for low power mode for paris definitions. + * @{ + */ +#ifndef __MDM_TIA_LP_FORCE_DCCALRESULTS_MACRO__ +#define __MDM_TIA_LP_FORCE_DCCALRESULTS_MACRO__ + +/* macros for field q_off */ +/** + * @defgroup mdm_regs_core_q_off_field q_off_field + * @brief macros for field q_off + * @details forced TIA Q offset + * @{ + */ +#define MDM_TIA_LP_FORCE_DCCALRESULTS__Q_OFF__SHIFT 0 +#define MDM_TIA_LP_FORCE_DCCALRESULTS__Q_OFF__WIDTH 8 +#define MDM_TIA_LP_FORCE_DCCALRESULTS__Q_OFF__MASK 0x000000ffU +#define MDM_TIA_LP_FORCE_DCCALRESULTS__Q_OFF__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_TIA_LP_FORCE_DCCALRESULTS__Q_OFF__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_TIA_LP_FORCE_DCCALRESULTS__Q_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_TIA_LP_FORCE_DCCALRESULTS__Q_OFF__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define MDM_TIA_LP_FORCE_DCCALRESULTS__Q_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field i_off */ +/** + * @defgroup mdm_regs_core_i_off_field i_off_field + * @brief macros for field i_off + * @details forced TIA I offset + * @{ + */ +#define MDM_TIA_LP_FORCE_DCCALRESULTS__I_OFF__SHIFT 8 +#define MDM_TIA_LP_FORCE_DCCALRESULTS__I_OFF__WIDTH 8 +#define MDM_TIA_LP_FORCE_DCCALRESULTS__I_OFF__MASK 0x0000ff00U +#define MDM_TIA_LP_FORCE_DCCALRESULTS__I_OFF__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_TIA_LP_FORCE_DCCALRESULTS__I_OFF__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define MDM_TIA_LP_FORCE_DCCALRESULTS__I_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MDM_TIA_LP_FORCE_DCCALRESULTS__I_OFF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define MDM_TIA_LP_FORCE_DCCALRESULTS__I_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bb2gain */ +/** + * @defgroup mdm_regs_core_bb2gain_field bb2gain_field + * @brief macros for field bb2gain + * @details bb2gain value used in TIA cal + * @{ + */ +#define MDM_TIA_LP_FORCE_DCCALRESULTS__BB2GAIN__SHIFT 16 +#define MDM_TIA_LP_FORCE_DCCALRESULTS__BB2GAIN__WIDTH 5 +#define MDM_TIA_LP_FORCE_DCCALRESULTS__BB2GAIN__MASK 0x001f0000U +#define MDM_TIA_LP_FORCE_DCCALRESULTS__BB2GAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x001f0000U) >> 16) +#define MDM_TIA_LP_FORCE_DCCALRESULTS__BB2GAIN__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x001f0000U) +#define MDM_TIA_LP_FORCE_DCCALRESULTS__BB2GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((uint32_t)(src) <<\ + 16) & 0x001f0000U) +#define MDM_TIA_LP_FORCE_DCCALRESULTS__BB2GAIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x001f0000U))) +#define MDM_TIA_LP_FORCE_DCCALRESULTS__BB2GAIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field force */ +/** + * @defgroup mdm_regs_core_force_field force_field + * @brief macros for field force + * @details force to use offset in this register + * @{ + */ +#define MDM_TIA_LP_FORCE_DCCALRESULTS__FORCE__SHIFT 31 +#define MDM_TIA_LP_FORCE_DCCALRESULTS__FORCE__WIDTH 1 +#define MDM_TIA_LP_FORCE_DCCALRESULTS__FORCE__MASK 0x80000000U +#define MDM_TIA_LP_FORCE_DCCALRESULTS__FORCE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_TIA_LP_FORCE_DCCALRESULTS__FORCE__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define MDM_TIA_LP_FORCE_DCCALRESULTS__FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define MDM_TIA_LP_FORCE_DCCALRESULTS__FORCE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define MDM_TIA_LP_FORCE_DCCALRESULTS__FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_TIA_LP_FORCE_DCCALRESULTS__FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_TIA_LP_FORCE_DCCALRESULTS__FORCE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_TIA_LP_FORCE_DCCALRESULTS__TYPE uint32_t +#define MDM_TIA_LP_FORCE_DCCALRESULTS__READ 0x801fffffU +#define MDM_TIA_LP_FORCE_DCCALRESULTS__WRITE 0x801fffffU +#define MDM_TIA_LP_FORCE_DCCALRESULTS__PRESERVED 0x00000000U +#define MDM_TIA_LP_FORCE_DCCALRESULTS__RESET_VALUE 0x00000000U + +#endif /* __MDM_TIA_LP_FORCE_DCCALRESULTS_MACRO__ */ + +/** @} end of tia_lp_force_dccalresults */ + +/* macros for BlueprintGlobalNameSpace::MDM_tia_lp_force_dccalresults2 */ +/** + * @defgroup mdm_regs_core_tia_lp_force_dccalresults2 tia_lp_force_dccalresults2 + * @brief Force DC offset calibration results for TIA for low power mode for paris definitions. + * @{ + */ +#ifndef __MDM_TIA_LP_FORCE_DCCALRESULTS2_MACRO__ +#define __MDM_TIA_LP_FORCE_DCCALRESULTS2_MACRO__ + +/* macros for field avg_q */ +/** + * @defgroup mdm_regs_core_avg_q_field avg_q_field + * @brief macros for field avg_q + * @details calculated average of ADC Q samples + * @{ + */ +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__AVG_Q__SHIFT 0 +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__AVG_Q__WIDTH 8 +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__AVG_Q__MASK 0x000000ffU +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__AVG_Q__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__AVG_Q__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__AVG_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__AVG_Q__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__AVG_Q__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field avg_i */ +/** + * @defgroup mdm_regs_core_avg_i_field avg_i_field + * @brief macros for field avg_i + * @details calculated average of ADC I samples + * @{ + */ +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__AVG_I__SHIFT 8 +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__AVG_I__WIDTH 8 +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__AVG_I__MASK 0x0000ff00U +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__AVG_I__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__AVG_I__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__AVG_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__AVG_I__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__AVG_I__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field force */ +/** + * @defgroup mdm_regs_core_force_field force_field + * @brief macros for field force + * @details force to use average in this register + * @{ + */ +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__FORCE__SHIFT 31 +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__FORCE__WIDTH 1 +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__FORCE__MASK 0x80000000U +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__FORCE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__FORCE__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__FORCE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__FORCE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__TYPE uint32_t +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__READ 0x8000ffffU +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__WRITE 0x8000ffffU +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__PRESERVED 0x00000000U +#define MDM_TIA_LP_FORCE_DCCALRESULTS2__RESET_VALUE 0x00000000U + +#endif /* __MDM_TIA_LP_FORCE_DCCALRESULTS2_MACRO__ */ + +/** @} end of tia_lp_force_dccalresults2 */ + +/* macros for BlueprintGlobalNameSpace::MDM_pga_force_dccalresults */ +/** + * @defgroup mdm_regs_core_pga_force_dccalresults pga_force_dccalresults + * @brief Force DC offset calibration results for PGA for paris definitions. + * @{ + */ +#ifndef __MDM_PGA_FORCE_DCCALRESULTS_MACRO__ +#define __MDM_PGA_FORCE_DCCALRESULTS_MACRO__ + +/* macros for field q_off */ +/** + * @defgroup mdm_regs_core_q_off_field q_off_field + * @brief macros for field q_off + * @details forced PGA Q offset + * @{ + */ +#define MDM_PGA_FORCE_DCCALRESULTS__Q_OFF__SHIFT 0 +#define MDM_PGA_FORCE_DCCALRESULTS__Q_OFF__WIDTH 5 +#define MDM_PGA_FORCE_DCCALRESULTS__Q_OFF__MASK 0x0000001fU +#define MDM_PGA_FORCE_DCCALRESULTS__Q_OFF__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define MDM_PGA_FORCE_DCCALRESULTS__Q_OFF__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define MDM_PGA_FORCE_DCCALRESULTS__Q_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define MDM_PGA_FORCE_DCCALRESULTS__Q_OFF__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define MDM_PGA_FORCE_DCCALRESULTS__Q_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field i_off */ +/** + * @defgroup mdm_regs_core_i_off_field i_off_field + * @brief macros for field i_off + * @details forced PGA I offset + * @{ + */ +#define MDM_PGA_FORCE_DCCALRESULTS__I_OFF__SHIFT 8 +#define MDM_PGA_FORCE_DCCALRESULTS__I_OFF__WIDTH 5 +#define MDM_PGA_FORCE_DCCALRESULTS__I_OFF__MASK 0x00001f00U +#define MDM_PGA_FORCE_DCCALRESULTS__I_OFF__READ(src) \ + (((uint32_t)(src)\ + & 0x00001f00U) >> 8) +#define MDM_PGA_FORCE_DCCALRESULTS__I_OFF__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00001f00U) +#define MDM_PGA_FORCE_DCCALRESULTS__I_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((uint32_t)(src) <<\ + 8) & 0x00001f00U) +#define MDM_PGA_FORCE_DCCALRESULTS__I_OFF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00001f00U))) +#define MDM_PGA_FORCE_DCCALRESULTS__I_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bb2gain */ +/** + * @defgroup mdm_regs_core_bb2gain_field bb2gain_field + * @brief macros for field bb2gain + * @details bb2gain value used in PGA cal + * @{ + */ +#define MDM_PGA_FORCE_DCCALRESULTS__BB2GAIN__SHIFT 16 +#define MDM_PGA_FORCE_DCCALRESULTS__BB2GAIN__WIDTH 5 +#define MDM_PGA_FORCE_DCCALRESULTS__BB2GAIN__MASK 0x001f0000U +#define MDM_PGA_FORCE_DCCALRESULTS__BB2GAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x001f0000U) >> 16) +#define MDM_PGA_FORCE_DCCALRESULTS__BB2GAIN__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x001f0000U) +#define MDM_PGA_FORCE_DCCALRESULTS__BB2GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((uint32_t)(src) <<\ + 16) & 0x001f0000U) +#define MDM_PGA_FORCE_DCCALRESULTS__BB2GAIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x001f0000U))) +#define MDM_PGA_FORCE_DCCALRESULTS__BB2GAIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field force */ +/** + * @defgroup mdm_regs_core_force_field force_field + * @brief macros for field force + * @details force to use offset in this register + * @{ + */ +#define MDM_PGA_FORCE_DCCALRESULTS__FORCE__SHIFT 31 +#define MDM_PGA_FORCE_DCCALRESULTS__FORCE__WIDTH 1 +#define MDM_PGA_FORCE_DCCALRESULTS__FORCE__MASK 0x80000000U +#define MDM_PGA_FORCE_DCCALRESULTS__FORCE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_PGA_FORCE_DCCALRESULTS__FORCE__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define MDM_PGA_FORCE_DCCALRESULTS__FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define MDM_PGA_FORCE_DCCALRESULTS__FORCE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define MDM_PGA_FORCE_DCCALRESULTS__FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_PGA_FORCE_DCCALRESULTS__FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_PGA_FORCE_DCCALRESULTS__FORCE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_PGA_FORCE_DCCALRESULTS__TYPE uint32_t +#define MDM_PGA_FORCE_DCCALRESULTS__READ 0x801f1f1fU +#define MDM_PGA_FORCE_DCCALRESULTS__WRITE 0x801f1f1fU +#define MDM_PGA_FORCE_DCCALRESULTS__PRESERVED 0x00000000U +#define MDM_PGA_FORCE_DCCALRESULTS__RESET_VALUE 0x00000000U + +#endif /* __MDM_PGA_FORCE_DCCALRESULTS_MACRO__ */ + +/** @} end of pga_force_dccalresults */ + +/* macros for BlueprintGlobalNameSpace::MDM_pga_force_dccalresults2 */ +/** + * @defgroup mdm_regs_core_pga_force_dccalresults2 pga_force_dccalresults2 + * @brief Force DC offset calibration results for PGA for paris definitions. + * @{ + */ +#ifndef __MDM_PGA_FORCE_DCCALRESULTS2_MACRO__ +#define __MDM_PGA_FORCE_DCCALRESULTS2_MACRO__ + +/* macros for field avg_q */ +/** + * @defgroup mdm_regs_core_avg_q_field avg_q_field + * @brief macros for field avg_q + * @details calculated average of ADC Q samples + * @{ + */ +#define MDM_PGA_FORCE_DCCALRESULTS2__AVG_Q__SHIFT 0 +#define MDM_PGA_FORCE_DCCALRESULTS2__AVG_Q__WIDTH 8 +#define MDM_PGA_FORCE_DCCALRESULTS2__AVG_Q__MASK 0x000000ffU +#define MDM_PGA_FORCE_DCCALRESULTS2__AVG_Q__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_PGA_FORCE_DCCALRESULTS2__AVG_Q__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_PGA_FORCE_DCCALRESULTS2__AVG_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_PGA_FORCE_DCCALRESULTS2__AVG_Q__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define MDM_PGA_FORCE_DCCALRESULTS2__AVG_Q__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field avg_i */ +/** + * @defgroup mdm_regs_core_avg_i_field avg_i_field + * @brief macros for field avg_i + * @details calculated average of ADC I samples + * @{ + */ +#define MDM_PGA_FORCE_DCCALRESULTS2__AVG_I__SHIFT 8 +#define MDM_PGA_FORCE_DCCALRESULTS2__AVG_I__WIDTH 8 +#define MDM_PGA_FORCE_DCCALRESULTS2__AVG_I__MASK 0x0000ff00U +#define MDM_PGA_FORCE_DCCALRESULTS2__AVG_I__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_PGA_FORCE_DCCALRESULTS2__AVG_I__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define MDM_PGA_FORCE_DCCALRESULTS2__AVG_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MDM_PGA_FORCE_DCCALRESULTS2__AVG_I__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define MDM_PGA_FORCE_DCCALRESULTS2__AVG_I__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field force */ +/** + * @defgroup mdm_regs_core_force_field force_field + * @brief macros for field force + * @details force to use average in this register + * @{ + */ +#define MDM_PGA_FORCE_DCCALRESULTS2__FORCE__SHIFT 31 +#define MDM_PGA_FORCE_DCCALRESULTS2__FORCE__WIDTH 1 +#define MDM_PGA_FORCE_DCCALRESULTS2__FORCE__MASK 0x80000000U +#define MDM_PGA_FORCE_DCCALRESULTS2__FORCE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_PGA_FORCE_DCCALRESULTS2__FORCE__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define MDM_PGA_FORCE_DCCALRESULTS2__FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define MDM_PGA_FORCE_DCCALRESULTS2__FORCE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define MDM_PGA_FORCE_DCCALRESULTS2__FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_PGA_FORCE_DCCALRESULTS2__FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_PGA_FORCE_DCCALRESULTS2__FORCE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_PGA_FORCE_DCCALRESULTS2__TYPE uint32_t +#define MDM_PGA_FORCE_DCCALRESULTS2__READ 0x8000ffffU +#define MDM_PGA_FORCE_DCCALRESULTS2__WRITE 0x8000ffffU +#define MDM_PGA_FORCE_DCCALRESULTS2__PRESERVED 0x00000000U +#define MDM_PGA_FORCE_DCCALRESULTS2__RESET_VALUE 0x00000000U + +#endif /* __MDM_PGA_FORCE_DCCALRESULTS2_MACRO__ */ + +/** @} end of pga_force_dccalresults2 */ + +/* macros for BlueprintGlobalNameSpace::MDM_pga_lp_force_dccalresults */ +/** + * @defgroup mdm_regs_core_pga_lp_force_dccalresults pga_lp_force_dccalresults + * @brief Force DC offset calibration results for PGA for low power mode for paris definitions. + * @{ + */ +#ifndef __MDM_PGA_LP_FORCE_DCCALRESULTS_MACRO__ +#define __MDM_PGA_LP_FORCE_DCCALRESULTS_MACRO__ + +/* macros for field q_off */ +/** + * @defgroup mdm_regs_core_q_off_field q_off_field + * @brief macros for field q_off + * @details forced PGA Q offset + * @{ + */ +#define MDM_PGA_LP_FORCE_DCCALRESULTS__Q_OFF__SHIFT 0 +#define MDM_PGA_LP_FORCE_DCCALRESULTS__Q_OFF__WIDTH 5 +#define MDM_PGA_LP_FORCE_DCCALRESULTS__Q_OFF__MASK 0x0000001fU +#define MDM_PGA_LP_FORCE_DCCALRESULTS__Q_OFF__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define MDM_PGA_LP_FORCE_DCCALRESULTS__Q_OFF__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define MDM_PGA_LP_FORCE_DCCALRESULTS__Q_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define MDM_PGA_LP_FORCE_DCCALRESULTS__Q_OFF__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define MDM_PGA_LP_FORCE_DCCALRESULTS__Q_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field i_off */ +/** + * @defgroup mdm_regs_core_i_off_field i_off_field + * @brief macros for field i_off + * @details forced PGA I offset + * @{ + */ +#define MDM_PGA_LP_FORCE_DCCALRESULTS__I_OFF__SHIFT 8 +#define MDM_PGA_LP_FORCE_DCCALRESULTS__I_OFF__WIDTH 5 +#define MDM_PGA_LP_FORCE_DCCALRESULTS__I_OFF__MASK 0x00001f00U +#define MDM_PGA_LP_FORCE_DCCALRESULTS__I_OFF__READ(src) \ + (((uint32_t)(src)\ + & 0x00001f00U) >> 8) +#define MDM_PGA_LP_FORCE_DCCALRESULTS__I_OFF__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00001f00U) +#define MDM_PGA_LP_FORCE_DCCALRESULTS__I_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((uint32_t)(src) <<\ + 8) & 0x00001f00U) +#define MDM_PGA_LP_FORCE_DCCALRESULTS__I_OFF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00001f00U))) +#define MDM_PGA_LP_FORCE_DCCALRESULTS__I_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bb2gain */ +/** + * @defgroup mdm_regs_core_bb2gain_field bb2gain_field + * @brief macros for field bb2gain + * @details bb2gain value used in PGA cal + * @{ + */ +#define MDM_PGA_LP_FORCE_DCCALRESULTS__BB2GAIN__SHIFT 16 +#define MDM_PGA_LP_FORCE_DCCALRESULTS__BB2GAIN__WIDTH 5 +#define MDM_PGA_LP_FORCE_DCCALRESULTS__BB2GAIN__MASK 0x001f0000U +#define MDM_PGA_LP_FORCE_DCCALRESULTS__BB2GAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x001f0000U) >> 16) +#define MDM_PGA_LP_FORCE_DCCALRESULTS__BB2GAIN__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x001f0000U) +#define MDM_PGA_LP_FORCE_DCCALRESULTS__BB2GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((uint32_t)(src) <<\ + 16) & 0x001f0000U) +#define MDM_PGA_LP_FORCE_DCCALRESULTS__BB2GAIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x001f0000U))) +#define MDM_PGA_LP_FORCE_DCCALRESULTS__BB2GAIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field force */ +/** + * @defgroup mdm_regs_core_force_field force_field + * @brief macros for field force + * @details force to use offset in this register + * @{ + */ +#define MDM_PGA_LP_FORCE_DCCALRESULTS__FORCE__SHIFT 31 +#define MDM_PGA_LP_FORCE_DCCALRESULTS__FORCE__WIDTH 1 +#define MDM_PGA_LP_FORCE_DCCALRESULTS__FORCE__MASK 0x80000000U +#define MDM_PGA_LP_FORCE_DCCALRESULTS__FORCE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_PGA_LP_FORCE_DCCALRESULTS__FORCE__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define MDM_PGA_LP_FORCE_DCCALRESULTS__FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define MDM_PGA_LP_FORCE_DCCALRESULTS__FORCE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define MDM_PGA_LP_FORCE_DCCALRESULTS__FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_PGA_LP_FORCE_DCCALRESULTS__FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_PGA_LP_FORCE_DCCALRESULTS__FORCE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_PGA_LP_FORCE_DCCALRESULTS__TYPE uint32_t +#define MDM_PGA_LP_FORCE_DCCALRESULTS__READ 0x801f1f1fU +#define MDM_PGA_LP_FORCE_DCCALRESULTS__WRITE 0x801f1f1fU +#define MDM_PGA_LP_FORCE_DCCALRESULTS__PRESERVED 0x00000000U +#define MDM_PGA_LP_FORCE_DCCALRESULTS__RESET_VALUE 0x00000000U + +#endif /* __MDM_PGA_LP_FORCE_DCCALRESULTS_MACRO__ */ + +/** @} end of pga_lp_force_dccalresults */ + +/* macros for BlueprintGlobalNameSpace::MDM_pga_lp_force_dccalresults2 */ +/** + * @defgroup mdm_regs_core_pga_lp_force_dccalresults2 pga_lp_force_dccalresults2 + * @brief Force DC offset calibration results for PGA for low power mode for paris definitions. + * @{ + */ +#ifndef __MDM_PGA_LP_FORCE_DCCALRESULTS2_MACRO__ +#define __MDM_PGA_LP_FORCE_DCCALRESULTS2_MACRO__ + +/* macros for field avg_q */ +/** + * @defgroup mdm_regs_core_avg_q_field avg_q_field + * @brief macros for field avg_q + * @details calculated average of ADC Q samples + * @{ + */ +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__AVG_Q__SHIFT 0 +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__AVG_Q__WIDTH 8 +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__AVG_Q__MASK 0x000000ffU +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__AVG_Q__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__AVG_Q__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__AVG_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__AVG_Q__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__AVG_Q__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field avg_i */ +/** + * @defgroup mdm_regs_core_avg_i_field avg_i_field + * @brief macros for field avg_i + * @details calculated average of ADC I samples + * @{ + */ +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__AVG_I__SHIFT 8 +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__AVG_I__WIDTH 8 +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__AVG_I__MASK 0x0000ff00U +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__AVG_I__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__AVG_I__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__AVG_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__AVG_I__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__AVG_I__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field force */ +/** + * @defgroup mdm_regs_core_force_field force_field + * @brief macros for field force + * @details force to use average in this register + * @{ + */ +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__FORCE__SHIFT 31 +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__FORCE__WIDTH 1 +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__FORCE__MASK 0x80000000U +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__FORCE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__FORCE__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__FORCE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__FORCE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__TYPE uint32_t +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__READ 0x8000ffffU +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__WRITE 0x8000ffffU +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__PRESERVED 0x00000000U +#define MDM_PGA_LP_FORCE_DCCALRESULTS2__RESET_VALUE 0x00000000U + +#endif /* __MDM_PGA_LP_FORCE_DCCALRESULTS2_MACRO__ */ + +/** @} end of pga_lp_force_dccalresults2 */ + +/* macros for BlueprintGlobalNameSpace::MDM_notch_force_dccalresults */ +/** + * @defgroup mdm_regs_core_notch_force_dccalresults notch_force_dccalresults + * @brief DC offset calibration results for notch filter definitions. + * @{ + */ +#ifndef __MDM_NOTCH_FORCE_DCCALRESULTS_MACRO__ +#define __MDM_NOTCH_FORCE_DCCALRESULTS_MACRO__ + +/* macros for field ctn */ +/** + * @defgroup mdm_regs_core_ctn_field ctn_field + * @brief macros for field ctn + * @details forced notch ctune + * @{ + */ +#define MDM_NOTCH_FORCE_DCCALRESULTS__CTN__SHIFT 0 +#define MDM_NOTCH_FORCE_DCCALRESULTS__CTN__WIDTH 6 +#define MDM_NOTCH_FORCE_DCCALRESULTS__CTN__MASK 0x0000003fU +#define MDM_NOTCH_FORCE_DCCALRESULTS__CTN__READ(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_NOTCH_FORCE_DCCALRESULTS__CTN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_NOTCH_FORCE_DCCALRESULTS__CTN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define MDM_NOTCH_FORCE_DCCALRESULTS__CTN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define MDM_NOTCH_FORCE_DCCALRESULTS__CTN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field force */ +/** + * @defgroup mdm_regs_core_force_field force_field + * @brief macros for field force + * @details force to use tune in this register + * @{ + */ +#define MDM_NOTCH_FORCE_DCCALRESULTS__FORCE__SHIFT 31 +#define MDM_NOTCH_FORCE_DCCALRESULTS__FORCE__WIDTH 1 +#define MDM_NOTCH_FORCE_DCCALRESULTS__FORCE__MASK 0x80000000U +#define MDM_NOTCH_FORCE_DCCALRESULTS__FORCE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_NOTCH_FORCE_DCCALRESULTS__FORCE__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define MDM_NOTCH_FORCE_DCCALRESULTS__FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define MDM_NOTCH_FORCE_DCCALRESULTS__FORCE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define MDM_NOTCH_FORCE_DCCALRESULTS__FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_NOTCH_FORCE_DCCALRESULTS__FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_NOTCH_FORCE_DCCALRESULTS__FORCE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_NOTCH_FORCE_DCCALRESULTS__TYPE uint32_t +#define MDM_NOTCH_FORCE_DCCALRESULTS__READ 0x8000003fU +#define MDM_NOTCH_FORCE_DCCALRESULTS__WRITE 0x8000003fU +#define MDM_NOTCH_FORCE_DCCALRESULTS__PRESERVED 0x00000000U +#define MDM_NOTCH_FORCE_DCCALRESULTS__RESET_VALUE 0x00000000U + +#endif /* __MDM_NOTCH_FORCE_DCCALRESULTS_MACRO__ */ + +/** @} end of notch_force_dccalresults */ + +/* macros for BlueprintGlobalNameSpace::MDM_pga_cal_gain_force_dccalresults */ +/** + * @defgroup mdm_regs_core_pga_cal_gain_force_dccalresults pga_cal_gain_force_dccalresults + * @brief force DC offset calibration results for PGA at cal gain definitions. + * @{ + */ +#ifndef __MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS_MACRO__ +#define __MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS_MACRO__ + +/* macros for field q_off */ +/** + * @defgroup mdm_regs_core_q_off_field q_off_field + * @brief macros for field q_off + * @details forced PGA Q offset + * @{ + */ +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__Q_OFF__SHIFT 0 +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__Q_OFF__WIDTH 5 +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__Q_OFF__MASK 0x0000001fU +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__Q_OFF__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__Q_OFF__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__Q_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__Q_OFF__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__Q_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field i_off */ +/** + * @defgroup mdm_regs_core_i_off_field i_off_field + * @brief macros for field i_off + * @details forced PGA I offset + * @{ + */ +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__I_OFF__SHIFT 5 +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__I_OFF__WIDTH 5 +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__I_OFF__MASK 0x000003e0U +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__I_OFF__READ(src) \ + (((uint32_t)(src)\ + & 0x000003e0U) >> 5) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__I_OFF__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x000003e0U) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__I_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((uint32_t)(src) <<\ + 5) & 0x000003e0U) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__I_OFF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000003e0U))) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__I_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field force */ +/** + * @defgroup mdm_regs_core_force_field force_field + * @brief macros for field force + * @details force to use offset in this register + * @{ + */ +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__FORCE__SHIFT 31 +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__FORCE__WIDTH 1 +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__FORCE__MASK 0x80000000U +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__FORCE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__FORCE__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__FORCE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__FORCE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__TYPE uint32_t +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__READ 0x800003ffU +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__WRITE 0x800003ffU +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__PRESERVED 0x00000000U +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS__RESET_VALUE 0x00000000U + +#endif /* __MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS_MACRO__ */ + +/** @} end of pga_cal_gain_force_dccalresults */ + +/* macros for BlueprintGlobalNameSpace::MDM_pga_cal_gain_force_dccalresults2 */ +/** + * @defgroup mdm_regs_core_pga_cal_gain_force_dccalresults2 pga_cal_gain_force_dccalresults2 + * @brief force DC offset calibration results for PGA at cal gain definitions. + * @{ + */ +#ifndef __MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2_MACRO__ +#define __MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2_MACRO__ + +/* macros for field avg_q */ +/** + * @defgroup mdm_regs_core_avg_q_field avg_q_field + * @brief macros for field avg_q + * @details forced residue DC Q from DC cal + * @{ + */ +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__AVG_Q__SHIFT 0 +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__AVG_Q__WIDTH 8 +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__AVG_Q__MASK 0x000000ffU +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__AVG_Q__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__AVG_Q__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__AVG_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__AVG_Q__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__AVG_Q__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field avg_i */ +/** + * @defgroup mdm_regs_core_avg_i_field avg_i_field + * @brief macros for field avg_i + * @details forced residue DC I from DC cal + * @{ + */ +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__AVG_I__SHIFT 8 +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__AVG_I__WIDTH 8 +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__AVG_I__MASK 0x0000ff00U +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__AVG_I__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__AVG_I__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__AVG_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__AVG_I__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__AVG_I__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bb2gain */ +/** + * @defgroup mdm_regs_core_bb2gain_field bb2gain_field + * @brief macros for field bb2gain + * @details forced bb2gain value used in PGA cal + * @{ + */ +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__BB2GAIN__SHIFT 16 +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__BB2GAIN__WIDTH 5 +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__BB2GAIN__MASK 0x001f0000U +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__BB2GAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x001f0000U) >> 16) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__BB2GAIN__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x001f0000U) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__BB2GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((uint32_t)(src) <<\ + 16) & 0x001f0000U) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__BB2GAIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x001f0000U))) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__BB2GAIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field force_avg */ +/** + * @defgroup mdm_regs_core_force_avg_field force_avg_field + * @brief macros for field force_avg + * @details force to use residue DC this register + * @{ + */ +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__FORCE_AVG__SHIFT 30 +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__FORCE_AVG__WIDTH 1 +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__FORCE_AVG__MASK 0x40000000U +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__FORCE_AVG__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__FORCE_AVG__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__FORCE_AVG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__FORCE_AVG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__FORCE_AVG__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__FORCE_AVG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__FORCE_AVG__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field force_bb2gain */ +/** + * @defgroup mdm_regs_core_force_bb2gain_field force_bb2gain_field + * @brief macros for field force_bb2gain + * @details force to use bb2gain this register + * @{ + */ +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__FORCE_BB2GAIN__SHIFT 31 +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__FORCE_BB2GAIN__WIDTH 1 +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__FORCE_BB2GAIN__MASK 0x80000000U +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__FORCE_BB2GAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__FORCE_BB2GAIN__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__FORCE_BB2GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__FORCE_BB2GAIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__FORCE_BB2GAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__FORCE_BB2GAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__FORCE_BB2GAIN__RESET_VALUE \ + 0x00000000U +/** @} */ +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__TYPE uint32_t +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__READ 0xc01fffffU +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__WRITE 0xc01fffffU +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__PRESERVED 0x00000000U +#define MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2__RESET_VALUE 0x00000000U + +#endif /* __MDM_PGA_CAL_GAIN_FORCE_DCCALRESULTS2_MACRO__ */ + +/** @} end of pga_cal_gain_force_dccalresults2 */ + +/* macros for BlueprintGlobalNameSpace::MDM_iqcorr */ +/** + * @defgroup mdm_regs_core_iqcorr iqcorr + * @brief I/Q correction: Default definitions. + * @{ + */ +#ifndef __MDM_IQCORR_MACRO__ +#define __MDM_IQCORR_MACRO__ + +/* macros for field ampl_corr_default */ +/** + * @defgroup mdm_regs_core_ampl_corr_default_field ampl_corr_default_field + * @brief macros for field ampl_corr_default + * @details Signed + * @{ + */ +#define MDM_IQCORR__AMPL_CORR_DEFAULT__SHIFT 0 +#define MDM_IQCORR__AMPL_CORR_DEFAULT__WIDTH 8 +#define MDM_IQCORR__AMPL_CORR_DEFAULT__MASK 0x000000ffU +#define MDM_IQCORR__AMPL_CORR_DEFAULT__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_IQCORR__AMPL_CORR_DEFAULT__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_IQCORR__AMPL_CORR_DEFAULT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_IQCORR__AMPL_CORR_DEFAULT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define MDM_IQCORR__AMPL_CORR_DEFAULT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field phase_corr_default */ +/** + * @defgroup mdm_regs_core_phase_corr_default_field phase_corr_default_field + * @brief macros for field phase_corr_default + * @details Signed + * @{ + */ +#define MDM_IQCORR__PHASE_CORR_DEFAULT__SHIFT 8 +#define MDM_IQCORR__PHASE_CORR_DEFAULT__WIDTH 8 +#define MDM_IQCORR__PHASE_CORR_DEFAULT__MASK 0x0000ff00U +#define MDM_IQCORR__PHASE_CORR_DEFAULT__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_IQCORR__PHASE_CORR_DEFAULT__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define MDM_IQCORR__PHASE_CORR_DEFAULT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MDM_IQCORR__PHASE_CORR_DEFAULT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define MDM_IQCORR__PHASE_CORR_DEFAULT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field twomeg_ampl_corr_default */ +/** + * @defgroup mdm_regs_core_twomeg_ampl_corr_default_field twomeg_ampl_corr_default_field + * @brief macros for field twomeg_ampl_corr_default + * @details Signed + * @{ + */ +#define MDM_IQCORR__TWOMEG_AMPL_CORR_DEFAULT__SHIFT 16 +#define MDM_IQCORR__TWOMEG_AMPL_CORR_DEFAULT__WIDTH 8 +#define MDM_IQCORR__TWOMEG_AMPL_CORR_DEFAULT__MASK 0x00ff0000U +#define MDM_IQCORR__TWOMEG_AMPL_CORR_DEFAULT__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MDM_IQCORR__TWOMEG_AMPL_CORR_DEFAULT__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define MDM_IQCORR__TWOMEG_AMPL_CORR_DEFAULT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MDM_IQCORR__TWOMEG_AMPL_CORR_DEFAULT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define MDM_IQCORR__TWOMEG_AMPL_CORR_DEFAULT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field twomeg_phase_corr_default */ +/** + * @defgroup mdm_regs_core_twomeg_phase_corr_default_field twomeg_phase_corr_default_field + * @brief macros for field twomeg_phase_corr_default + * @details Signed + * @{ + */ +#define MDM_IQCORR__TWOMEG_PHASE_CORR_DEFAULT__SHIFT 24 +#define MDM_IQCORR__TWOMEG_PHASE_CORR_DEFAULT__WIDTH 8 +#define MDM_IQCORR__TWOMEG_PHASE_CORR_DEFAULT__MASK 0xff000000U +#define MDM_IQCORR__TWOMEG_PHASE_CORR_DEFAULT__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define MDM_IQCORR__TWOMEG_PHASE_CORR_DEFAULT__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define MDM_IQCORR__TWOMEG_PHASE_CORR_DEFAULT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define MDM_IQCORR__TWOMEG_PHASE_CORR_DEFAULT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define MDM_IQCORR__TWOMEG_PHASE_CORR_DEFAULT__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_IQCORR__TYPE uint32_t +#define MDM_IQCORR__READ 0xffffffffU +#define MDM_IQCORR__WRITE 0xffffffffU +#define MDM_IQCORR__PRESERVED 0x00000000U +#define MDM_IQCORR__RESET_VALUE 0x00000000U + +#endif /* __MDM_IQCORR_MACRO__ */ + +/** @} end of iqcorr */ + +/* macros for BlueprintGlobalNameSpace::MDM_agcmeas_alt */ +/** + * @defgroup mdm_regs_core_agcmeas_alt agcmeas_alt + * @brief Power measurements, alternate set definitions. + * @{ + */ +#ifndef __MDM_AGCMEAS_ALT_MACRO__ +#define __MDM_AGCMEAS_ALT_MACRO__ + +/* macros for field rssi_offset */ +/** + * @defgroup mdm_regs_core_rssi_offset_field rssi_offset_field + * @brief macros for field rssi_offset + * @details RSSI = rxgain - (measured_power after RXFIR) plus rssi_offset. Signed. Register replicated for 2 Mb/s + * @{ + */ +#define MDM_AGCMEAS_ALT__RSSI_OFFSET__SHIFT 0 +#define MDM_AGCMEAS_ALT__RSSI_OFFSET__WIDTH 8 +#define MDM_AGCMEAS_ALT__RSSI_OFFSET__MASK 0x000000ffU +#define MDM_AGCMEAS_ALT__RSSI_OFFSET__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_AGCMEAS_ALT__RSSI_OFFSET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_AGCMEAS_ALT__RSSI_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_AGCMEAS_ALT__RSSI_OFFSET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define MDM_AGCMEAS_ALT__RSSI_OFFSET__RESET_VALUE 0x00000011U +/** @} */ + +/* macros for field det_min */ +/** + * @defgroup mdm_regs_core_det_min_field det_min_field + * @brief macros for field det_min + * @details Signed, relative to full scale agc filter output. Lowest allowed inband power measurement 7'h4d = -51. Register replicated for 2 Mb/s + * @{ + */ +#define MDM_AGCMEAS_ALT__DET_MIN__SHIFT 8 +#define MDM_AGCMEAS_ALT__DET_MIN__WIDTH 7 +#define MDM_AGCMEAS_ALT__DET_MIN__MASK 0x00007f00U +#define MDM_AGCMEAS_ALT__DET_MIN__READ(src) \ + (((uint32_t)(src)\ + & 0x00007f00U) >> 8) +#define MDM_AGCMEAS_ALT__DET_MIN__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00007f00U) +#define MDM_AGCMEAS_ALT__DET_MIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007f00U) | (((uint32_t)(src) <<\ + 8) & 0x00007f00U) +#define MDM_AGCMEAS_ALT__DET_MIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00007f00U))) +#define MDM_AGCMEAS_ALT__DET_MIN__RESET_VALUE 0x0000004dU +/** @} */ + +/* macros for field twomeg_rssi_offset */ +/** + * @defgroup mdm_regs_core_twomeg_rssi_offset_field twomeg_rssi_offset_field + * @brief macros for field twomeg_rssi_offset + * @details RSSI = rxgain - (measured_power after RXFIR) plus rssi_offset. 2 Mb/s version of register. + * @{ + */ +#define MDM_AGCMEAS_ALT__TWOMEG_RSSI_OFFSET__SHIFT 15 +#define MDM_AGCMEAS_ALT__TWOMEG_RSSI_OFFSET__WIDTH 8 +#define MDM_AGCMEAS_ALT__TWOMEG_RSSI_OFFSET__MASK 0x007f8000U +#define MDM_AGCMEAS_ALT__TWOMEG_RSSI_OFFSET__READ(src) \ + (((uint32_t)(src)\ + & 0x007f8000U) >> 15) +#define MDM_AGCMEAS_ALT__TWOMEG_RSSI_OFFSET__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x007f8000U) +#define MDM_AGCMEAS_ALT__TWOMEG_RSSI_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007f8000U) | (((uint32_t)(src) <<\ + 15) & 0x007f8000U) +#define MDM_AGCMEAS_ALT__TWOMEG_RSSI_OFFSET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x007f8000U))) +#define MDM_AGCMEAS_ALT__TWOMEG_RSSI_OFFSET__RESET_VALUE 0x00000011U +/** @} */ + +/* macros for field twomeg_det_min */ +/** + * @defgroup mdm_regs_core_twomeg_det_min_field twomeg_det_min_field + * @brief macros for field twomeg_det_min + * @details Signed, relative to full scale agc filter output. Lowest allowed inband power measurement 7'h50 = -48. 2 Mb/s version of this register + * @{ + */ +#define MDM_AGCMEAS_ALT__TWOMEG_DET_MIN__SHIFT 23 +#define MDM_AGCMEAS_ALT__TWOMEG_DET_MIN__WIDTH 7 +#define MDM_AGCMEAS_ALT__TWOMEG_DET_MIN__MASK 0x3f800000U +#define MDM_AGCMEAS_ALT__TWOMEG_DET_MIN__READ(src) \ + (((uint32_t)(src)\ + & 0x3f800000U) >> 23) +#define MDM_AGCMEAS_ALT__TWOMEG_DET_MIN__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x3f800000U) +#define MDM_AGCMEAS_ALT__TWOMEG_DET_MIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f800000U) | (((uint32_t)(src) <<\ + 23) & 0x3f800000U) +#define MDM_AGCMEAS_ALT__TWOMEG_DET_MIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x3f800000U))) +#define MDM_AGCMEAS_ALT__TWOMEG_DET_MIN__RESET_VALUE 0x00000050U +/** @} */ +#define MDM_AGCMEAS_ALT__TYPE uint32_t +#define MDM_AGCMEAS_ALT__READ 0x3fffffffU +#define MDM_AGCMEAS_ALT__WRITE 0x3fffffffU +#define MDM_AGCMEAS_ALT__PRESERVED 0x00000000U +#define MDM_AGCMEAS_ALT__RESET_VALUE 0x2808cd11U + +#endif /* __MDM_AGCMEAS_ALT_MACRO__ */ + +/** @} end of agcmeas_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_agcgain_alt */ +/** + * @defgroup mdm_regs_core_agcgain_alt agcgain_alt + * @brief Gain settings, alternate set definitions. + * @{ + */ +#ifndef __MDM_AGCGAIN_ALT_MACRO__ +#define __MDM_AGCGAIN_ALT_MACRO__ + +/* macros for field start */ +/** + * @defgroup mdm_regs_core_start_field start_field + * @brief macros for field start + * @details RX gain to use at start of packet search + * @{ + */ +#define MDM_AGCGAIN_ALT__START__SHIFT 0 +#define MDM_AGCGAIN_ALT__START__WIDTH 7 +#define MDM_AGCGAIN_ALT__START__MASK 0x0000007fU +#define MDM_AGCGAIN_ALT__START__READ(src) ((uint32_t)(src) & 0x0000007fU) +#define MDM_AGCGAIN_ALT__START__WRITE(src) ((uint32_t)(src) & 0x0000007fU) +#define MDM_AGCGAIN_ALT__START__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define MDM_AGCGAIN_ALT__START__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000007fU))) +#define MDM_AGCGAIN_ALT__START__RESET_VALUE 0x0000004cU +/** @} */ + +/* macros for field rfin_pd_quick_drop */ +/** + * @defgroup mdm_regs_core_rfin_pd_quick_drop_field rfin_pd_quick_drop_field + * @brief macros for field rfin_pd_quick_drop + * @details Gain drop in dB when rfin peak detect indicated + * @{ + */ +#define MDM_AGCGAIN_ALT__RFIN_PD_QUICK_DROP__SHIFT 14 +#define MDM_AGCGAIN_ALT__RFIN_PD_QUICK_DROP__WIDTH 7 +#define MDM_AGCGAIN_ALT__RFIN_PD_QUICK_DROP__MASK 0x001fc000U +#define MDM_AGCGAIN_ALT__RFIN_PD_QUICK_DROP__READ(src) \ + (((uint32_t)(src)\ + & 0x001fc000U) >> 14) +#define MDM_AGCGAIN_ALT__RFIN_PD_QUICK_DROP__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x001fc000U) +#define MDM_AGCGAIN_ALT__RFIN_PD_QUICK_DROP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001fc000U) | (((uint32_t)(src) <<\ + 14) & 0x001fc000U) +#define MDM_AGCGAIN_ALT__RFIN_PD_QUICK_DROP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x001fc000U))) +#define MDM_AGCGAIN_ALT__RFIN_PD_QUICK_DROP__RESET_VALUE 0x00000045U +/** @} */ + +/* macros for field tia_quick_drop */ +/** + * @defgroup mdm_regs_core_tia_quick_drop_field tia_quick_drop_field + * @brief macros for field tia_quick_drop + * @details Gain drop in dB when peak detect indicated + * @{ + */ +#define MDM_AGCGAIN_ALT__TIA_QUICK_DROP__SHIFT 21 +#define MDM_AGCGAIN_ALT__TIA_QUICK_DROP__WIDTH 7 +#define MDM_AGCGAIN_ALT__TIA_QUICK_DROP__MASK 0x0fe00000U +#define MDM_AGCGAIN_ALT__TIA_QUICK_DROP__READ(src) \ + (((uint32_t)(src)\ + & 0x0fe00000U) >> 21) +#define MDM_AGCGAIN_ALT__TIA_QUICK_DROP__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x0fe00000U) +#define MDM_AGCGAIN_ALT__TIA_QUICK_DROP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fe00000U) | (((uint32_t)(src) <<\ + 21) & 0x0fe00000U) +#define MDM_AGCGAIN_ALT__TIA_QUICK_DROP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x0fe00000U))) +#define MDM_AGCGAIN_ALT__TIA_QUICK_DROP__RESET_VALUE 0x00000036U +/** @} */ +#define MDM_AGCGAIN_ALT__TYPE uint32_t +#define MDM_AGCGAIN_ALT__READ 0x0fffc07fU +#define MDM_AGCGAIN_ALT__WRITE 0x0fffc07fU +#define MDM_AGCGAIN_ALT__PRESERVED 0x00000000U +#define MDM_AGCGAIN_ALT__RESET_VALUE 0x06d1404cU + +#endif /* __MDM_AGCGAIN_ALT_MACRO__ */ + +/** @} end of agcgain_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_xlna */ +/** + * @defgroup mdm_regs_core_xlna xlna + * @brief XLNA control definitions. + * @{ + */ +#ifndef __MDM_XLNA_MACRO__ +#define __MDM_XLNA_MACRO__ + +/* macros for field gain_settle */ +/** + * @defgroup mdm_regs_core_gain_settle_field gain_settle_field + * @brief macros for field gain_settle + * @details When XLNA switches, use this instead of agctime_gain_settle + * @{ + */ +#define MDM_XLNA__GAIN_SETTLE__SHIFT 0 +#define MDM_XLNA__GAIN_SETTLE__WIDTH 6 +#define MDM_XLNA__GAIN_SETTLE__MASK 0x0000003fU +#define MDM_XLNA__GAIN_SETTLE__READ(src) ((uint32_t)(src) & 0x0000003fU) +#define MDM_XLNA__GAIN_SETTLE__WRITE(src) ((uint32_t)(src) & 0x0000003fU) +#define MDM_XLNA__GAIN_SETTLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define MDM_XLNA__GAIN_SETTLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define MDM_XLNA__GAIN_SETTLE__RESET_VALUE 0x0000001cU +/** @} */ + +/* macros for field twomeg_gain_settle */ +/** + * @defgroup mdm_regs_core_twomeg_gain_settle_field twomeg_gain_settle_field + * @brief macros for field twomeg_gain_settle + * @details When XLNA switches, use this instead of twomeg_agctime_gain_settle + * @{ + */ +#define MDM_XLNA__TWOMEG_GAIN_SETTLE__SHIFT 6 +#define MDM_XLNA__TWOMEG_GAIN_SETTLE__WIDTH 6 +#define MDM_XLNA__TWOMEG_GAIN_SETTLE__MASK 0x00000fc0U +#define MDM_XLNA__TWOMEG_GAIN_SETTLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000fc0U) >> 6) +#define MDM_XLNA__TWOMEG_GAIN_SETTLE__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000fc0U) +#define MDM_XLNA__TWOMEG_GAIN_SETTLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((uint32_t)(src) <<\ + 6) & 0x00000fc0U) +#define MDM_XLNA__TWOMEG_GAIN_SETTLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000fc0U))) +#define MDM_XLNA__TWOMEG_GAIN_SETTLE__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field reset_filt_delay */ +/** + * @defgroup mdm_regs_core_reset_filt_delay_field reset_filt_delay_field + * @brief macros for field reset_filt_delay + * @details When XLNA switches, use this instead of agctime2_reset_filt_delay + * @{ + */ +#define MDM_XLNA__RESET_FILT_DELAY__SHIFT 12 +#define MDM_XLNA__RESET_FILT_DELAY__WIDTH 6 +#define MDM_XLNA__RESET_FILT_DELAY__MASK 0x0003f000U +#define MDM_XLNA__RESET_FILT_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x0003f000U) >> 12) +#define MDM_XLNA__RESET_FILT_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0003f000U) +#define MDM_XLNA__RESET_FILT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((uint32_t)(src) <<\ + 12) & 0x0003f000U) +#define MDM_XLNA__RESET_FILT_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0003f000U))) +#define MDM_XLNA__RESET_FILT_DELAY__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field twomeg_reset_filt_delay */ +/** + * @defgroup mdm_regs_core_twomeg_reset_filt_delay_field twomeg_reset_filt_delay_field + * @brief macros for field twomeg_reset_filt_delay + * @details When XLNA switches, use this instead of agctime2_twomeg_reset_filt_delay + * @{ + */ +#define MDM_XLNA__TWOMEG_RESET_FILT_DELAY__SHIFT 18 +#define MDM_XLNA__TWOMEG_RESET_FILT_DELAY__WIDTH 6 +#define MDM_XLNA__TWOMEG_RESET_FILT_DELAY__MASK 0x00fc0000U +#define MDM_XLNA__TWOMEG_RESET_FILT_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x00fc0000U) >> 18) +#define MDM_XLNA__TWOMEG_RESET_FILT_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00fc0000U) +#define MDM_XLNA__TWOMEG_RESET_FILT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((uint32_t)(src) <<\ + 18) & 0x00fc0000U) +#define MDM_XLNA__TWOMEG_RESET_FILT_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00fc0000U))) +#define MDM_XLNA__TWOMEG_RESET_FILT_DELAY__RESET_VALUE 0x0000000aU +/** @} */ + +/* macros for field thresh */ +/** + * @defgroup mdm_regs_core_thresh_field thresh_field + * @brief macros for field thresh + * @details During active RX, turn on XLNA when rxgain index is greater than this threshold. Turn off XLNA when rxgain index is less than this threshold. At 127, XLNA will never turn on + * @{ + */ +#define MDM_XLNA__THRESH__SHIFT 24 +#define MDM_XLNA__THRESH__WIDTH 7 +#define MDM_XLNA__THRESH__MASK 0x7f000000U +#define MDM_XLNA__THRESH__READ(src) (((uint32_t)(src) & 0x7f000000U) >> 24) +#define MDM_XLNA__THRESH__WRITE(src) (((uint32_t)(src) << 24) & 0x7f000000U) +#define MDM_XLNA__THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((uint32_t)(src) <<\ + 24) & 0x7f000000U) +#define MDM_XLNA__THRESH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x7f000000U))) +#define MDM_XLNA__THRESH__RESET_VALUE 0x0000007fU +/** @} */ +#define MDM_XLNA__TYPE uint32_t +#define MDM_XLNA__READ 0x7fffffffU +#define MDM_XLNA__WRITE 0x7fffffffU +#define MDM_XLNA__PRESERVED 0x00000000U +#define MDM_XLNA__RESET_VALUE 0x7f29041cU + +#endif /* __MDM_XLNA_MACRO__ */ + +/** @} end of xlna */ + +/* macros for BlueprintGlobalNameSpace::MDM_xlna_alt */ +/** + * @defgroup mdm_regs_core_xlna_alt xlna_alt + * @brief XLNA control, alternate set definitions. + * @{ + */ +#ifndef __MDM_XLNA_ALT_MACRO__ +#define __MDM_XLNA_ALT_MACRO__ + +/* macros for field gain_settle */ +/** + * @defgroup mdm_regs_core_gain_settle_field gain_settle_field + * @brief macros for field gain_settle + * @details When XLNA switches, use this instead of agctime_gain_settle + * @{ + */ +#define MDM_XLNA_ALT__GAIN_SETTLE__SHIFT 0 +#define MDM_XLNA_ALT__GAIN_SETTLE__WIDTH 6 +#define MDM_XLNA_ALT__GAIN_SETTLE__MASK 0x0000003fU +#define MDM_XLNA_ALT__GAIN_SETTLE__READ(src) ((uint32_t)(src) & 0x0000003fU) +#define MDM_XLNA_ALT__GAIN_SETTLE__WRITE(src) ((uint32_t)(src) & 0x0000003fU) +#define MDM_XLNA_ALT__GAIN_SETTLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define MDM_XLNA_ALT__GAIN_SETTLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define MDM_XLNA_ALT__GAIN_SETTLE__RESET_VALUE 0x0000001cU +/** @} */ + +/* macros for field twomeg_gain_settle */ +/** + * @defgroup mdm_regs_core_twomeg_gain_settle_field twomeg_gain_settle_field + * @brief macros for field twomeg_gain_settle + * @details When XLNA switches, use this instead of twomeg_agctime_gain_settle + * @{ + */ +#define MDM_XLNA_ALT__TWOMEG_GAIN_SETTLE__SHIFT 6 +#define MDM_XLNA_ALT__TWOMEG_GAIN_SETTLE__WIDTH 6 +#define MDM_XLNA_ALT__TWOMEG_GAIN_SETTLE__MASK 0x00000fc0U +#define MDM_XLNA_ALT__TWOMEG_GAIN_SETTLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000fc0U) >> 6) +#define MDM_XLNA_ALT__TWOMEG_GAIN_SETTLE__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000fc0U) +#define MDM_XLNA_ALT__TWOMEG_GAIN_SETTLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((uint32_t)(src) <<\ + 6) & 0x00000fc0U) +#define MDM_XLNA_ALT__TWOMEG_GAIN_SETTLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000fc0U))) +#define MDM_XLNA_ALT__TWOMEG_GAIN_SETTLE__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field reset_filt_delay */ +/** + * @defgroup mdm_regs_core_reset_filt_delay_field reset_filt_delay_field + * @brief macros for field reset_filt_delay + * @details When XLNA switches, use this instead of agctime2_reset_filt_delay + * @{ + */ +#define MDM_XLNA_ALT__RESET_FILT_DELAY__SHIFT 12 +#define MDM_XLNA_ALT__RESET_FILT_DELAY__WIDTH 6 +#define MDM_XLNA_ALT__RESET_FILT_DELAY__MASK 0x0003f000U +#define MDM_XLNA_ALT__RESET_FILT_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x0003f000U) >> 12) +#define MDM_XLNA_ALT__RESET_FILT_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0003f000U) +#define MDM_XLNA_ALT__RESET_FILT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((uint32_t)(src) <<\ + 12) & 0x0003f000U) +#define MDM_XLNA_ALT__RESET_FILT_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0003f000U))) +#define MDM_XLNA_ALT__RESET_FILT_DELAY__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field twomeg_reset_filt_delay */ +/** + * @defgroup mdm_regs_core_twomeg_reset_filt_delay_field twomeg_reset_filt_delay_field + * @brief macros for field twomeg_reset_filt_delay + * @details When XLNA switches, use this instead of agctime2_twomeg_reset_filt_delay + * @{ + */ +#define MDM_XLNA_ALT__TWOMEG_RESET_FILT_DELAY__SHIFT 18 +#define MDM_XLNA_ALT__TWOMEG_RESET_FILT_DELAY__WIDTH 6 +#define MDM_XLNA_ALT__TWOMEG_RESET_FILT_DELAY__MASK 0x00fc0000U +#define MDM_XLNA_ALT__TWOMEG_RESET_FILT_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x00fc0000U) >> 18) +#define MDM_XLNA_ALT__TWOMEG_RESET_FILT_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00fc0000U) +#define MDM_XLNA_ALT__TWOMEG_RESET_FILT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((uint32_t)(src) <<\ + 18) & 0x00fc0000U) +#define MDM_XLNA_ALT__TWOMEG_RESET_FILT_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00fc0000U))) +#define MDM_XLNA_ALT__TWOMEG_RESET_FILT_DELAY__RESET_VALUE 0x0000000aU +/** @} */ + +/* macros for field thresh */ +/** + * @defgroup mdm_regs_core_thresh_field thresh_field + * @brief macros for field thresh + * @details During active RX, turn on XLNA when rxgain index is greater than this threshold. Turn off XLNA when rxgain index is less than this threshold. At 127, XLNA will never turn on + * @{ + */ +#define MDM_XLNA_ALT__THRESH__SHIFT 24 +#define MDM_XLNA_ALT__THRESH__WIDTH 7 +#define MDM_XLNA_ALT__THRESH__MASK 0x7f000000U +#define MDM_XLNA_ALT__THRESH__READ(src) (((uint32_t)(src) & 0x7f000000U) >> 24) +#define MDM_XLNA_ALT__THRESH__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x7f000000U) +#define MDM_XLNA_ALT__THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((uint32_t)(src) <<\ + 24) & 0x7f000000U) +#define MDM_XLNA_ALT__THRESH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x7f000000U))) +#define MDM_XLNA_ALT__THRESH__RESET_VALUE 0x0000007fU +/** @} */ +#define MDM_XLNA_ALT__TYPE uint32_t +#define MDM_XLNA_ALT__READ 0x7fffffffU +#define MDM_XLNA_ALT__WRITE 0x7fffffffU +#define MDM_XLNA_ALT__PRESERVED 0x00000000U +#define MDM_XLNA_ALT__RESET_VALUE 0x7f29041cU + +#endif /* __MDM_XLNA_ALT_MACRO__ */ + +/** @} end of xlna_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_agcsat */ +/** + * @defgroup mdm_regs_core_agcsat agcsat + * @brief Saturation control definitions. + * @{ + */ +#ifndef __MDM_AGCSAT_MACRO__ +#define __MDM_AGCSAT_MACRO__ + +/* macros for field check_win */ +/** + * @defgroup mdm_regs_core_check_win_field check_win_field + * @brief macros for field check_win + * @details Number of samples to measure for EACH of I and Q. Maximum allowed is 8. If set to 0, then saturation detection is disabled. + * @{ + */ +#define MDM_AGCSAT__CHECK_WIN__SHIFT 0 +#define MDM_AGCSAT__CHECK_WIN__WIDTH 4 +#define MDM_AGCSAT__CHECK_WIN__MASK 0x0000000fU +#define MDM_AGCSAT__CHECK_WIN__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define MDM_AGCSAT__CHECK_WIN__WRITE(src) ((uint32_t)(src) & 0x0000000fU) +#define MDM_AGCSAT__CHECK_WIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define MDM_AGCSAT__CHECK_WIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define MDM_AGCSAT__CHECK_WIN__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field thr_cnt */ +/** + * @defgroup mdm_regs_core_thr_cnt_field thr_cnt_field + * @brief macros for field thr_cnt + * @details Number of saturated I and Q samples (add up I and Q) needed to declare a saturated signal. Saturation will be declared if number of measurements is greater than or equal to thr_cnt + * @{ + */ +#define MDM_AGCSAT__THR_CNT__SHIFT 4 +#define MDM_AGCSAT__THR_CNT__WIDTH 4 +#define MDM_AGCSAT__THR_CNT__MASK 0x000000f0U +#define MDM_AGCSAT__THR_CNT__READ(src) (((uint32_t)(src) & 0x000000f0U) >> 4) +#define MDM_AGCSAT__THR_CNT__WRITE(src) (((uint32_t)(src) << 4) & 0x000000f0U) +#define MDM_AGCSAT__THR_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define MDM_AGCSAT__THR_CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define MDM_AGCSAT__THR_CNT__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field check_thr_high */ +/** + * @defgroup mdm_regs_core_check_thr_high_field check_thr_high_field + * @brief macros for field check_thr_high + * @details High threshold. Signed, in units of ADC LSBs. An I or Q sample greater than or equal to check_thr_high is considered saturated. + * @{ + */ +#define MDM_AGCSAT__CHECK_THR_HIGH__SHIFT 8 +#define MDM_AGCSAT__CHECK_THR_HIGH__WIDTH 8 +#define MDM_AGCSAT__CHECK_THR_HIGH__MASK 0x0000ff00U +#define MDM_AGCSAT__CHECK_THR_HIGH__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_AGCSAT__CHECK_THR_HIGH__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define MDM_AGCSAT__CHECK_THR_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MDM_AGCSAT__CHECK_THR_HIGH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define MDM_AGCSAT__CHECK_THR_HIGH__RESET_VALUE 0x00000066U +/** @} */ + +/* macros for field check_thr_low */ +/** + * @defgroup mdm_regs_core_check_thr_low_field check_thr_low_field + * @brief macros for field check_thr_low + * @details Low threshold. Signed, in units of ADC LSBs. An I or Q sample less than or equal to check_thr_low is considered saturated. (Default 8'h9a = -102). + * @{ + */ +#define MDM_AGCSAT__CHECK_THR_LOW__SHIFT 16 +#define MDM_AGCSAT__CHECK_THR_LOW__WIDTH 8 +#define MDM_AGCSAT__CHECK_THR_LOW__MASK 0x00ff0000U +#define MDM_AGCSAT__CHECK_THR_LOW__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MDM_AGCSAT__CHECK_THR_LOW__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define MDM_AGCSAT__CHECK_THR_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MDM_AGCSAT__CHECK_THR_LOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define MDM_AGCSAT__CHECK_THR_LOW__RESET_VALUE 0x0000009aU +/** @} */ +#define MDM_AGCSAT__TYPE uint32_t +#define MDM_AGCSAT__READ 0x00ffffffU +#define MDM_AGCSAT__WRITE 0x00ffffffU +#define MDM_AGCSAT__PRESERVED 0x00000000U +#define MDM_AGCSAT__RESET_VALUE 0x009a6614U + +#endif /* __MDM_AGCSAT_MACRO__ */ + +/** @} end of agcsat */ + +/* macros for BlueprintGlobalNameSpace::MDM_agcsat_alt */ +/** + * @defgroup mdm_regs_core_agcsat_alt agcsat_alt + * @brief Saturation control, alternate set definitions. + * @{ + */ +#ifndef __MDM_AGCSAT_ALT_MACRO__ +#define __MDM_AGCSAT_ALT_MACRO__ + +/* macros for field check_win */ +/** + * @defgroup mdm_regs_core_check_win_field check_win_field + * @brief macros for field check_win + * @details Number of samples to measure for EACH of I and Q. Maximum allowed is 8. If set to 0, then saturation detection is disabled. + * @{ + */ +#define MDM_AGCSAT_ALT__CHECK_WIN__SHIFT 0 +#define MDM_AGCSAT_ALT__CHECK_WIN__WIDTH 4 +#define MDM_AGCSAT_ALT__CHECK_WIN__MASK 0x0000000fU +#define MDM_AGCSAT_ALT__CHECK_WIN__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define MDM_AGCSAT_ALT__CHECK_WIN__WRITE(src) ((uint32_t)(src) & 0x0000000fU) +#define MDM_AGCSAT_ALT__CHECK_WIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define MDM_AGCSAT_ALT__CHECK_WIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define MDM_AGCSAT_ALT__CHECK_WIN__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field thr_cnt */ +/** + * @defgroup mdm_regs_core_thr_cnt_field thr_cnt_field + * @brief macros for field thr_cnt + * @details Number of saturated I and Q samples (add up I and Q) needed to declare a saturated signal. Saturation will be declared if number of measurements is greater than or equal to thr_cnt + * @{ + */ +#define MDM_AGCSAT_ALT__THR_CNT__SHIFT 4 +#define MDM_AGCSAT_ALT__THR_CNT__WIDTH 4 +#define MDM_AGCSAT_ALT__THR_CNT__MASK 0x000000f0U +#define MDM_AGCSAT_ALT__THR_CNT__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define MDM_AGCSAT_ALT__THR_CNT__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x000000f0U) +#define MDM_AGCSAT_ALT__THR_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define MDM_AGCSAT_ALT__THR_CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define MDM_AGCSAT_ALT__THR_CNT__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field check_thr_high */ +/** + * @defgroup mdm_regs_core_check_thr_high_field check_thr_high_field + * @brief macros for field check_thr_high + * @details High threshold. Signed, in units of ADC LSBs. An I or Q sample greater than or equal to check_thr_high is considered saturated. + * @{ + */ +#define MDM_AGCSAT_ALT__CHECK_THR_HIGH__SHIFT 8 +#define MDM_AGCSAT_ALT__CHECK_THR_HIGH__WIDTH 8 +#define MDM_AGCSAT_ALT__CHECK_THR_HIGH__MASK 0x0000ff00U +#define MDM_AGCSAT_ALT__CHECK_THR_HIGH__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_AGCSAT_ALT__CHECK_THR_HIGH__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define MDM_AGCSAT_ALT__CHECK_THR_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MDM_AGCSAT_ALT__CHECK_THR_HIGH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define MDM_AGCSAT_ALT__CHECK_THR_HIGH__RESET_VALUE 0x00000066U +/** @} */ + +/* macros for field check_thr_low */ +/** + * @defgroup mdm_regs_core_check_thr_low_field check_thr_low_field + * @brief macros for field check_thr_low + * @details Low threshold. Signed, in units of ADC LSBs. An I or Q sample less than or equal to check_thr_low is considered saturated. (Default 8'h9a = -102). + * @{ + */ +#define MDM_AGCSAT_ALT__CHECK_THR_LOW__SHIFT 16 +#define MDM_AGCSAT_ALT__CHECK_THR_LOW__WIDTH 8 +#define MDM_AGCSAT_ALT__CHECK_THR_LOW__MASK 0x00ff0000U +#define MDM_AGCSAT_ALT__CHECK_THR_LOW__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MDM_AGCSAT_ALT__CHECK_THR_LOW__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define MDM_AGCSAT_ALT__CHECK_THR_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MDM_AGCSAT_ALT__CHECK_THR_LOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define MDM_AGCSAT_ALT__CHECK_THR_LOW__RESET_VALUE 0x0000009aU +/** @} */ +#define MDM_AGCSAT_ALT__TYPE uint32_t +#define MDM_AGCSAT_ALT__READ 0x00ffffffU +#define MDM_AGCSAT_ALT__WRITE 0x00ffffffU +#define MDM_AGCSAT_ALT__PRESERVED 0x00000000U +#define MDM_AGCSAT_ALT__RESET_VALUE 0x009a6614U + +#endif /* __MDM_AGCSAT_ALT_MACRO__ */ + +/** @} end of agcsat_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_baseline */ +/** + * @defgroup mdm_regs_core_baseline baseline + * @brief Thresholds for declaring a low baseline power, used in gain_delta calculation definitions. + * @{ + */ +#ifndef __MDM_BASELINE_MACRO__ +#define __MDM_BASELINE_MACRO__ + +/* macros for field low_pwr_thr */ +/** + * @defgroup mdm_regs_core_low_pwr_thr_field low_pwr_thr_field + * @brief macros for field low_pwr_thr + * @details Signed. 1 Mb/s, 125 Kb/s and 500 Kb/s version. 8'hd6 = -42 + * @{ + */ +#define MDM_BASELINE__LOW_PWR_THR__SHIFT 0 +#define MDM_BASELINE__LOW_PWR_THR__WIDTH 8 +#define MDM_BASELINE__LOW_PWR_THR__MASK 0x000000ffU +#define MDM_BASELINE__LOW_PWR_THR__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_BASELINE__LOW_PWR_THR__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_BASELINE__LOW_PWR_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_BASELINE__LOW_PWR_THR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define MDM_BASELINE__LOW_PWR_THR__RESET_VALUE 0x000000d6U +/** @} */ + +/* macros for field twomeg_low_pwr_thr */ +/** + * @defgroup mdm_regs_core_twomeg_low_pwr_thr_field twomeg_low_pwr_thr_field + * @brief macros for field twomeg_low_pwr_thr + * @details Signed. 2 Mb/s version. 8'hd9 = -39 + * @{ + */ +#define MDM_BASELINE__TWOMEG_LOW_PWR_THR__SHIFT 8 +#define MDM_BASELINE__TWOMEG_LOW_PWR_THR__WIDTH 8 +#define MDM_BASELINE__TWOMEG_LOW_PWR_THR__MASK 0x0000ff00U +#define MDM_BASELINE__TWOMEG_LOW_PWR_THR__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_BASELINE__TWOMEG_LOW_PWR_THR__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define MDM_BASELINE__TWOMEG_LOW_PWR_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MDM_BASELINE__TWOMEG_LOW_PWR_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define MDM_BASELINE__TWOMEG_LOW_PWR_THR__RESET_VALUE 0x000000d9U +/** @} */ +#define MDM_BASELINE__TYPE uint32_t +#define MDM_BASELINE__READ 0x0000ffffU +#define MDM_BASELINE__WRITE 0x0000ffffU +#define MDM_BASELINE__PRESERVED 0x00000000U +#define MDM_BASELINE__RESET_VALUE 0x0000d9d6U + +#endif /* __MDM_BASELINE_MACRO__ */ + +/** @} end of baseline */ + +/* macros for BlueprintGlobalNameSpace::MDM_baseline_alt */ +/** + * @defgroup mdm_regs_core_baseline_alt baseline_alt + * @brief Thresholds for declaring a low baseline power, used in gain_delta calculation, alternate set definitions. + * @{ + */ +#ifndef __MDM_BASELINE_ALT_MACRO__ +#define __MDM_BASELINE_ALT_MACRO__ + +/* macros for field low_pwr_thr */ +/** + * @defgroup mdm_regs_core_low_pwr_thr_field low_pwr_thr_field + * @brief macros for field low_pwr_thr + * @details Signed. 1 Mb/s, 125 Kb/s and 500 Kb/s version. 8'hd6 = -42 + * @{ + */ +#define MDM_BASELINE_ALT__LOW_PWR_THR__SHIFT 0 +#define MDM_BASELINE_ALT__LOW_PWR_THR__WIDTH 8 +#define MDM_BASELINE_ALT__LOW_PWR_THR__MASK 0x000000ffU +#define MDM_BASELINE_ALT__LOW_PWR_THR__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_BASELINE_ALT__LOW_PWR_THR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_BASELINE_ALT__LOW_PWR_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_BASELINE_ALT__LOW_PWR_THR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define MDM_BASELINE_ALT__LOW_PWR_THR__RESET_VALUE 0x000000d6U +/** @} */ + +/* macros for field twomeg_low_pwr_thr */ +/** + * @defgroup mdm_regs_core_twomeg_low_pwr_thr_field twomeg_low_pwr_thr_field + * @brief macros for field twomeg_low_pwr_thr + * @details Signed. 2 Mb/s version. 8'hd9 = -39 + * @{ + */ +#define MDM_BASELINE_ALT__TWOMEG_LOW_PWR_THR__SHIFT 8 +#define MDM_BASELINE_ALT__TWOMEG_LOW_PWR_THR__WIDTH 8 +#define MDM_BASELINE_ALT__TWOMEG_LOW_PWR_THR__MASK 0x0000ff00U +#define MDM_BASELINE_ALT__TWOMEG_LOW_PWR_THR__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_BASELINE_ALT__TWOMEG_LOW_PWR_THR__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define MDM_BASELINE_ALT__TWOMEG_LOW_PWR_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MDM_BASELINE_ALT__TWOMEG_LOW_PWR_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define MDM_BASELINE_ALT__TWOMEG_LOW_PWR_THR__RESET_VALUE 0x000000d9U +/** @} */ +#define MDM_BASELINE_ALT__TYPE uint32_t +#define MDM_BASELINE_ALT__READ 0x0000ffffU +#define MDM_BASELINE_ALT__WRITE 0x0000ffffU +#define MDM_BASELINE_ALT__PRESERVED 0x00000000U +#define MDM_BASELINE_ALT__RESET_VALUE 0x0000d9d6U + +#endif /* __MDM_BASELINE_ALT_MACRO__ */ + +/** @} end of baseline_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_margin */ +/** + * @defgroup mdm_regs_core_margin margin + * @brief Adjustment to gain_delta when blocker is present and inband power is low definitions. + * @{ + */ +#ifndef __MDM_MARGIN_MACRO__ +#define __MDM_MARGIN_MACRO__ + +/* macros for field adc_max_low_inband_pwr */ +/** + * @defgroup mdm_regs_core_adc_max_low_inband_pwr_field adc_max_low_inband_pwr_field + * @brief macros for field adc_max_low_inband_pwr + * @details Signed. 1 Mb/s, 125 Kb/s and 500 Kb/s version + * @{ + */ +#define MDM_MARGIN__ADC_MAX_LOW_INBAND_PWR__SHIFT 0 +#define MDM_MARGIN__ADC_MAX_LOW_INBAND_PWR__WIDTH 6 +#define MDM_MARGIN__ADC_MAX_LOW_INBAND_PWR__MASK 0x0000003fU +#define MDM_MARGIN__ADC_MAX_LOW_INBAND_PWR__READ(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_MARGIN__ADC_MAX_LOW_INBAND_PWR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_MARGIN__ADC_MAX_LOW_INBAND_PWR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define MDM_MARGIN__ADC_MAX_LOW_INBAND_PWR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define MDM_MARGIN__ADC_MAX_LOW_INBAND_PWR__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field twomeg_adc_max_low_inband_pwr */ +/** + * @defgroup mdm_regs_core_twomeg_adc_max_low_inband_pwr_field twomeg_adc_max_low_inband_pwr_field + * @brief macros for field twomeg_adc_max_low_inband_pwr + * @details Signed. 1 Mb/s, 125 Kb/s and 500 Kb/s version + * @{ + */ +#define MDM_MARGIN__TWOMEG_ADC_MAX_LOW_INBAND_PWR__SHIFT 6 +#define MDM_MARGIN__TWOMEG_ADC_MAX_LOW_INBAND_PWR__WIDTH 6 +#define MDM_MARGIN__TWOMEG_ADC_MAX_LOW_INBAND_PWR__MASK 0x00000fc0U +#define MDM_MARGIN__TWOMEG_ADC_MAX_LOW_INBAND_PWR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000fc0U) >> 6) +#define MDM_MARGIN__TWOMEG_ADC_MAX_LOW_INBAND_PWR__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000fc0U) +#define MDM_MARGIN__TWOMEG_ADC_MAX_LOW_INBAND_PWR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((uint32_t)(src) <<\ + 6) & 0x00000fc0U) +#define MDM_MARGIN__TWOMEG_ADC_MAX_LOW_INBAND_PWR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000fc0U))) +#define MDM_MARGIN__TWOMEG_ADC_MAX_LOW_INBAND_PWR__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field strong_blocker_thr */ +/** + * @defgroup mdm_regs_core_strong_blocker_thr_field strong_blocker_thr_field + * @brief macros for field strong_blocker_thr + * @details Signed. For bit in agcstatus register, strong_blocker = (total_pwr - baseline_pwr) > cf_margin_strong_blocker_thr + * @{ + */ +#define MDM_MARGIN__STRONG_BLOCKER_THR__SHIFT 12 +#define MDM_MARGIN__STRONG_BLOCKER_THR__WIDTH 8 +#define MDM_MARGIN__STRONG_BLOCKER_THR__MASK 0x000ff000U +#define MDM_MARGIN__STRONG_BLOCKER_THR__READ(src) \ + (((uint32_t)(src)\ + & 0x000ff000U) >> 12) +#define MDM_MARGIN__STRONG_BLOCKER_THR__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x000ff000U) +#define MDM_MARGIN__STRONG_BLOCKER_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ff000U) | (((uint32_t)(src) <<\ + 12) & 0x000ff000U) +#define MDM_MARGIN__STRONG_BLOCKER_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x000ff000U))) +#define MDM_MARGIN__STRONG_BLOCKER_THR__RESET_VALUE 0x00000009U +/** @} */ +#define MDM_MARGIN__TYPE uint32_t +#define MDM_MARGIN__READ 0x000fffffU +#define MDM_MARGIN__WRITE 0x000fffffU +#define MDM_MARGIN__PRESERVED 0x00000000U +#define MDM_MARGIN__RESET_VALUE 0x00009184U + +#endif /* __MDM_MARGIN_MACRO__ */ + +/** @} end of margin */ + +/* macros for BlueprintGlobalNameSpace::MDM_margin_alt */ +/** + * @defgroup mdm_regs_core_margin_alt margin_alt + * @brief Adjustment to gain_delta when blocker is present and inband power is low, alternate set definitions. + * @{ + */ +#ifndef __MDM_MARGIN_ALT_MACRO__ +#define __MDM_MARGIN_ALT_MACRO__ + +/* macros for field adc_max_low_inband_pwr */ +/** + * @defgroup mdm_regs_core_adc_max_low_inband_pwr_field adc_max_low_inband_pwr_field + * @brief macros for field adc_max_low_inband_pwr + * @details Signed. 1 Mb/s, 125 Kb/s and 500 Kb/s version + * @{ + */ +#define MDM_MARGIN_ALT__ADC_MAX_LOW_INBAND_PWR__SHIFT 0 +#define MDM_MARGIN_ALT__ADC_MAX_LOW_INBAND_PWR__WIDTH 6 +#define MDM_MARGIN_ALT__ADC_MAX_LOW_INBAND_PWR__MASK 0x0000003fU +#define MDM_MARGIN_ALT__ADC_MAX_LOW_INBAND_PWR__READ(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_MARGIN_ALT__ADC_MAX_LOW_INBAND_PWR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_MARGIN_ALT__ADC_MAX_LOW_INBAND_PWR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define MDM_MARGIN_ALT__ADC_MAX_LOW_INBAND_PWR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define MDM_MARGIN_ALT__ADC_MAX_LOW_INBAND_PWR__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field twomeg_adc_max_low_inband_pwr */ +/** + * @defgroup mdm_regs_core_twomeg_adc_max_low_inband_pwr_field twomeg_adc_max_low_inband_pwr_field + * @brief macros for field twomeg_adc_max_low_inband_pwr + * @details Signed. 1 Mb/s, 125 Kb/s and 500 Kb/s version + * @{ + */ +#define MDM_MARGIN_ALT__TWOMEG_ADC_MAX_LOW_INBAND_PWR__SHIFT 6 +#define MDM_MARGIN_ALT__TWOMEG_ADC_MAX_LOW_INBAND_PWR__WIDTH 6 +#define MDM_MARGIN_ALT__TWOMEG_ADC_MAX_LOW_INBAND_PWR__MASK 0x00000fc0U +#define MDM_MARGIN_ALT__TWOMEG_ADC_MAX_LOW_INBAND_PWR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000fc0U) >> 6) +#define MDM_MARGIN_ALT__TWOMEG_ADC_MAX_LOW_INBAND_PWR__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000fc0U) +#define MDM_MARGIN_ALT__TWOMEG_ADC_MAX_LOW_INBAND_PWR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((uint32_t)(src) <<\ + 6) & 0x00000fc0U) +#define MDM_MARGIN_ALT__TWOMEG_ADC_MAX_LOW_INBAND_PWR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000fc0U))) +#define MDM_MARGIN_ALT__TWOMEG_ADC_MAX_LOW_INBAND_PWR__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field strong_blocker_thr */ +/** + * @defgroup mdm_regs_core_strong_blocker_thr_field strong_blocker_thr_field + * @brief macros for field strong_blocker_thr + * @details Signed. For bit in agcstatus register, strong_blocker = (total_pwr - baseline_pwr) > cf_margin_strong_blocker_thr + * @{ + */ +#define MDM_MARGIN_ALT__STRONG_BLOCKER_THR__SHIFT 12 +#define MDM_MARGIN_ALT__STRONG_BLOCKER_THR__WIDTH 8 +#define MDM_MARGIN_ALT__STRONG_BLOCKER_THR__MASK 0x000ff000U +#define MDM_MARGIN_ALT__STRONG_BLOCKER_THR__READ(src) \ + (((uint32_t)(src)\ + & 0x000ff000U) >> 12) +#define MDM_MARGIN_ALT__STRONG_BLOCKER_THR__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x000ff000U) +#define MDM_MARGIN_ALT__STRONG_BLOCKER_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ff000U) | (((uint32_t)(src) <<\ + 12) & 0x000ff000U) +#define MDM_MARGIN_ALT__STRONG_BLOCKER_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x000ff000U))) +#define MDM_MARGIN_ALT__STRONG_BLOCKER_THR__RESET_VALUE 0x00000009U +/** @} */ +#define MDM_MARGIN_ALT__TYPE uint32_t +#define MDM_MARGIN_ALT__READ 0x000fffffU +#define MDM_MARGIN_ALT__WRITE 0x000fffffU +#define MDM_MARGIN_ALT__PRESERVED 0x00000000U +#define MDM_MARGIN_ALT__RESET_VALUE 0x00009184U + +#endif /* __MDM_MARGIN_ALT_MACRO__ */ + +/** @} end of margin_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_pwrstep */ +/** + * @defgroup mdm_regs_core_pwrstep pwrstep + * @brief Control for power step detection definitions. + * @{ + */ +#ifndef __MDM_PWRSTEP_MACRO__ +#define __MDM_PWRSTEP_MACRO__ + +/* macros for field baseline_meas_dur */ +/** + * @defgroup mdm_regs_core_baseline_meas_dur_field baseline_meas_dur_field + * @brief macros for field baseline_meas_dur + * @details 2'b00 -> 16; 2'b01 -> 24; 2'b10 -> 32; 2'b11 -> 40 + * @{ + */ +#define MDM_PWRSTEP__BASELINE_MEAS_DUR__SHIFT 0 +#define MDM_PWRSTEP__BASELINE_MEAS_DUR__WIDTH 2 +#define MDM_PWRSTEP__BASELINE_MEAS_DUR__MASK 0x00000003U +#define MDM_PWRSTEP__BASELINE_MEAS_DUR__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define MDM_PWRSTEP__BASELINE_MEAS_DUR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define MDM_PWRSTEP__BASELINE_MEAS_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define MDM_PWRSTEP__BASELINE_MEAS_DUR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define MDM_PWRSTEP__BASELINE_MEAS_DUR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field baseline_meas_delay */ +/** + * @defgroup mdm_regs_core_baseline_meas_delay_field baseline_meas_delay_field + * @brief macros for field baseline_meas_delay + * @details Number of clocks between baseline and inband_pwr to compare 2'b00 -> 4; 2'b01 -> 8; 2'b10 -> 12; 2'b11 -> 16 + * @{ + */ +#define MDM_PWRSTEP__BASELINE_MEAS_DELAY__SHIFT 2 +#define MDM_PWRSTEP__BASELINE_MEAS_DELAY__WIDTH 2 +#define MDM_PWRSTEP__BASELINE_MEAS_DELAY__MASK 0x0000000cU +#define MDM_PWRSTEP__BASELINE_MEAS_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x0000000cU) >> 2) +#define MDM_PWRSTEP__BASELINE_MEAS_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000000cU) +#define MDM_PWRSTEP__BASELINE_MEAS_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((uint32_t)(src) <<\ + 2) & 0x0000000cU) +#define MDM_PWRSTEP__BASELINE_MEAS_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000000cU))) +#define MDM_PWRSTEP__BASELINE_MEAS_DELAY__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field cnt */ +/** + * @defgroup mdm_regs_core_cnt_field cnt_field + * @brief macros for field cnt + * @details Number of most recent power delta values to use + * @{ + */ +#define MDM_PWRSTEP__CNT__SHIFT 4 +#define MDM_PWRSTEP__CNT__WIDTH 4 +#define MDM_PWRSTEP__CNT__MASK 0x000000f0U +#define MDM_PWRSTEP__CNT__READ(src) (((uint32_t)(src) & 0x000000f0U) >> 4) +#define MDM_PWRSTEP__CNT__WRITE(src) (((uint32_t)(src) << 4) & 0x000000f0U) +#define MDM_PWRSTEP__CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define MDM_PWRSTEP__CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define MDM_PWRSTEP__CNT__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field cnt_thr */ +/** + * @defgroup mdm_regs_core_cnt_thr_field cnt_thr_field + * @brief macros for field cnt_thr + * @details Out of the cnt values, how many needed to declare power step + * @{ + */ +#define MDM_PWRSTEP__CNT_THR__SHIFT 8 +#define MDM_PWRSTEP__CNT_THR__WIDTH 4 +#define MDM_PWRSTEP__CNT_THR__MASK 0x00000f00U +#define MDM_PWRSTEP__CNT_THR__READ(src) (((uint32_t)(src) & 0x00000f00U) >> 8) +#define MDM_PWRSTEP__CNT_THR__WRITE(src) (((uint32_t)(src) << 8) & 0x00000f00U) +#define MDM_PWRSTEP__CNT_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((uint32_t)(src) <<\ + 8) & 0x00000f00U) +#define MDM_PWRSTEP__CNT_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000f00U))) +#define MDM_PWRSTEP__CNT_THR__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field hyst_thr */ +/** + * @defgroup mdm_regs_core_hyst_thr_field hyst_thr_field + * @brief macros for field hyst_thr + * @details Power step hysteresis threshold + * @{ + */ +#define MDM_PWRSTEP__HYST_THR__SHIFT 12 +#define MDM_PWRSTEP__HYST_THR__WIDTH 4 +#define MDM_PWRSTEP__HYST_THR__MASK 0x0000f000U +#define MDM_PWRSTEP__HYST_THR__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f000U) >> 12) +#define MDM_PWRSTEP__HYST_THR__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0000f000U) +#define MDM_PWRSTEP__HYST_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((uint32_t)(src) <<\ + 12) & 0x0000f000U) +#define MDM_PWRSTEP__HYST_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0000f000U))) +#define MDM_PWRSTEP__HYST_THR__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field disable_hyst_for_blocker */ +/** + * @defgroup mdm_regs_core_disable_hyst_for_blocker_field disable_hyst_for_blocker_field + * @brief macros for field disable_hyst_for_blocker + * @details If bit is set and there is a strong blocker, do not require hst_thr criteria to be met to declare a power step + * @{ + */ +#define MDM_PWRSTEP__DISABLE_HYST_FOR_BLOCKER__SHIFT 16 +#define MDM_PWRSTEP__DISABLE_HYST_FOR_BLOCKER__WIDTH 1 +#define MDM_PWRSTEP__DISABLE_HYST_FOR_BLOCKER__MASK 0x00010000U +#define MDM_PWRSTEP__DISABLE_HYST_FOR_BLOCKER__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define MDM_PWRSTEP__DISABLE_HYST_FOR_BLOCKER__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define MDM_PWRSTEP__DISABLE_HYST_FOR_BLOCKER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define MDM_PWRSTEP__DISABLE_HYST_FOR_BLOCKER__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define MDM_PWRSTEP__DISABLE_HYST_FOR_BLOCKER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define MDM_PWRSTEP__DISABLE_HYST_FOR_BLOCKER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define MDM_PWRSTEP__DISABLE_HYST_FOR_BLOCKER__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field twomeg_baseline_meas_dur */ +/** + * @defgroup mdm_regs_core_twomeg_baseline_meas_dur_field twomeg_baseline_meas_dur_field + * @brief macros for field twomeg_baseline_meas_dur + * @details 2'b00 -> 16; 2'b01 -> 24; 2'b10 -> 32; 2'b11 -> 40. 2M rate + * @{ + */ +#define MDM_PWRSTEP__TWOMEG_BASELINE_MEAS_DUR__SHIFT 17 +#define MDM_PWRSTEP__TWOMEG_BASELINE_MEAS_DUR__WIDTH 2 +#define MDM_PWRSTEP__TWOMEG_BASELINE_MEAS_DUR__MASK 0x00060000U +#define MDM_PWRSTEP__TWOMEG_BASELINE_MEAS_DUR__READ(src) \ + (((uint32_t)(src)\ + & 0x00060000U) >> 17) +#define MDM_PWRSTEP__TWOMEG_BASELINE_MEAS_DUR__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00060000U) +#define MDM_PWRSTEP__TWOMEG_BASELINE_MEAS_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00060000U) | (((uint32_t)(src) <<\ + 17) & 0x00060000U) +#define MDM_PWRSTEP__TWOMEG_BASELINE_MEAS_DUR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00060000U))) +#define MDM_PWRSTEP__TWOMEG_BASELINE_MEAS_DUR__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field twomeg_baseline_meas_delay */ +/** + * @defgroup mdm_regs_core_twomeg_baseline_meas_delay_field twomeg_baseline_meas_delay_field + * @brief macros for field twomeg_baseline_meas_delay + * @details Number of clocks between baseline and inband_pwr to compare 2'b00 -> 4; 2'b01 -> 8; 2'b10 -> 12; 2'b11 -> 16. 2M rate + * @{ + */ +#define MDM_PWRSTEP__TWOMEG_BASELINE_MEAS_DELAY__SHIFT 19 +#define MDM_PWRSTEP__TWOMEG_BASELINE_MEAS_DELAY__WIDTH 2 +#define MDM_PWRSTEP__TWOMEG_BASELINE_MEAS_DELAY__MASK 0x00180000U +#define MDM_PWRSTEP__TWOMEG_BASELINE_MEAS_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define MDM_PWRSTEP__TWOMEG_BASELINE_MEAS_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define MDM_PWRSTEP__TWOMEG_BASELINE_MEAS_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define MDM_PWRSTEP__TWOMEG_BASELINE_MEAS_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define MDM_PWRSTEP__TWOMEG_BASELINE_MEAS_DELAY__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field separate_pos_and_neg */ +/** + * @defgroup mdm_regs_core_separate_pos_and_neg_field separate_pos_and_neg_field + * @brief macros for field separate_pos_and_neg + * @details If bit is set, threshold positive and negative power steps separately + * @{ + */ +#define MDM_PWRSTEP__SEPARATE_POS_AND_NEG__SHIFT 21 +#define MDM_PWRSTEP__SEPARATE_POS_AND_NEG__WIDTH 1 +#define MDM_PWRSTEP__SEPARATE_POS_AND_NEG__MASK 0x00200000U +#define MDM_PWRSTEP__SEPARATE_POS_AND_NEG__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define MDM_PWRSTEP__SEPARATE_POS_AND_NEG__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define MDM_PWRSTEP__SEPARATE_POS_AND_NEG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define MDM_PWRSTEP__SEPARATE_POS_AND_NEG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define MDM_PWRSTEP__SEPARATE_POS_AND_NEG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define MDM_PWRSTEP__SEPARATE_POS_AND_NEG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define MDM_PWRSTEP__SEPARATE_POS_AND_NEG__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_PWRSTEP__TYPE uint32_t +#define MDM_PWRSTEP__READ 0x003fffffU +#define MDM_PWRSTEP__WRITE 0x003fffffU +#define MDM_PWRSTEP__PRESERVED 0x00000000U +#define MDM_PWRSTEP__RESET_VALUE 0x000d4684U + +#endif /* __MDM_PWRSTEP_MACRO__ */ + +/** @} end of pwrstep */ + +/* macros for BlueprintGlobalNameSpace::MDM_pwrstep_alt */ +/** + * @defgroup mdm_regs_core_pwrstep_alt pwrstep_alt + * @brief Control for power step detection, alternate set definitions. + * @{ + */ +#ifndef __MDM_PWRSTEP_ALT_MACRO__ +#define __MDM_PWRSTEP_ALT_MACRO__ + +/* macros for field baseline_meas_dur */ +/** + * @defgroup mdm_regs_core_baseline_meas_dur_field baseline_meas_dur_field + * @brief macros for field baseline_meas_dur + * @details 2'b00 -> 16; 2'b01 -> 24; 2'b10 -> 32; 2'b11 -> 40 + * @{ + */ +#define MDM_PWRSTEP_ALT__BASELINE_MEAS_DUR__SHIFT 0 +#define MDM_PWRSTEP_ALT__BASELINE_MEAS_DUR__WIDTH 2 +#define MDM_PWRSTEP_ALT__BASELINE_MEAS_DUR__MASK 0x00000003U +#define MDM_PWRSTEP_ALT__BASELINE_MEAS_DUR__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define MDM_PWRSTEP_ALT__BASELINE_MEAS_DUR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define MDM_PWRSTEP_ALT__BASELINE_MEAS_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define MDM_PWRSTEP_ALT__BASELINE_MEAS_DUR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define MDM_PWRSTEP_ALT__BASELINE_MEAS_DUR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field baseline_meas_delay */ +/** + * @defgroup mdm_regs_core_baseline_meas_delay_field baseline_meas_delay_field + * @brief macros for field baseline_meas_delay + * @details Number of clocks between baseline and inband_pwr to compare 2'b00 -> 4; 2'b01 -> 8; 2'b10 -> 12; 2'b11 -> 16 + * @{ + */ +#define MDM_PWRSTEP_ALT__BASELINE_MEAS_DELAY__SHIFT 2 +#define MDM_PWRSTEP_ALT__BASELINE_MEAS_DELAY__WIDTH 2 +#define MDM_PWRSTEP_ALT__BASELINE_MEAS_DELAY__MASK 0x0000000cU +#define MDM_PWRSTEP_ALT__BASELINE_MEAS_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x0000000cU) >> 2) +#define MDM_PWRSTEP_ALT__BASELINE_MEAS_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000000cU) +#define MDM_PWRSTEP_ALT__BASELINE_MEAS_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((uint32_t)(src) <<\ + 2) & 0x0000000cU) +#define MDM_PWRSTEP_ALT__BASELINE_MEAS_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000000cU))) +#define MDM_PWRSTEP_ALT__BASELINE_MEAS_DELAY__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field cnt */ +/** + * @defgroup mdm_regs_core_cnt_field cnt_field + * @brief macros for field cnt + * @details Number of most recent power delta values to use + * @{ + */ +#define MDM_PWRSTEP_ALT__CNT__SHIFT 4 +#define MDM_PWRSTEP_ALT__CNT__WIDTH 4 +#define MDM_PWRSTEP_ALT__CNT__MASK 0x000000f0U +#define MDM_PWRSTEP_ALT__CNT__READ(src) (((uint32_t)(src) & 0x000000f0U) >> 4) +#define MDM_PWRSTEP_ALT__CNT__WRITE(src) (((uint32_t)(src) << 4) & 0x000000f0U) +#define MDM_PWRSTEP_ALT__CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define MDM_PWRSTEP_ALT__CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define MDM_PWRSTEP_ALT__CNT__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field cnt_thr */ +/** + * @defgroup mdm_regs_core_cnt_thr_field cnt_thr_field + * @brief macros for field cnt_thr + * @details Out of the cnt values, how many needed to declare power step + * @{ + */ +#define MDM_PWRSTEP_ALT__CNT_THR__SHIFT 8 +#define MDM_PWRSTEP_ALT__CNT_THR__WIDTH 4 +#define MDM_PWRSTEP_ALT__CNT_THR__MASK 0x00000f00U +#define MDM_PWRSTEP_ALT__CNT_THR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000f00U) >> 8) +#define MDM_PWRSTEP_ALT__CNT_THR__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000f00U) +#define MDM_PWRSTEP_ALT__CNT_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((uint32_t)(src) <<\ + 8) & 0x00000f00U) +#define MDM_PWRSTEP_ALT__CNT_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000f00U))) +#define MDM_PWRSTEP_ALT__CNT_THR__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field hyst_thr */ +/** + * @defgroup mdm_regs_core_hyst_thr_field hyst_thr_field + * @brief macros for field hyst_thr + * @details Power step hysteresis threshold + * @{ + */ +#define MDM_PWRSTEP_ALT__HYST_THR__SHIFT 12 +#define MDM_PWRSTEP_ALT__HYST_THR__WIDTH 4 +#define MDM_PWRSTEP_ALT__HYST_THR__MASK 0x0000f000U +#define MDM_PWRSTEP_ALT__HYST_THR__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f000U) >> 12) +#define MDM_PWRSTEP_ALT__HYST_THR__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0000f000U) +#define MDM_PWRSTEP_ALT__HYST_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((uint32_t)(src) <<\ + 12) & 0x0000f000U) +#define MDM_PWRSTEP_ALT__HYST_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0000f000U))) +#define MDM_PWRSTEP_ALT__HYST_THR__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field disable_hyst_for_blocker */ +/** + * @defgroup mdm_regs_core_disable_hyst_for_blocker_field disable_hyst_for_blocker_field + * @brief macros for field disable_hyst_for_blocker + * @details If bit is set and there is a strong blocker, do not require hst_thr criteria to be met to declare a power step + * @{ + */ +#define MDM_PWRSTEP_ALT__DISABLE_HYST_FOR_BLOCKER__SHIFT 16 +#define MDM_PWRSTEP_ALT__DISABLE_HYST_FOR_BLOCKER__WIDTH 1 +#define MDM_PWRSTEP_ALT__DISABLE_HYST_FOR_BLOCKER__MASK 0x00010000U +#define MDM_PWRSTEP_ALT__DISABLE_HYST_FOR_BLOCKER__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define MDM_PWRSTEP_ALT__DISABLE_HYST_FOR_BLOCKER__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define MDM_PWRSTEP_ALT__DISABLE_HYST_FOR_BLOCKER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define MDM_PWRSTEP_ALT__DISABLE_HYST_FOR_BLOCKER__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define MDM_PWRSTEP_ALT__DISABLE_HYST_FOR_BLOCKER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define MDM_PWRSTEP_ALT__DISABLE_HYST_FOR_BLOCKER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define MDM_PWRSTEP_ALT__DISABLE_HYST_FOR_BLOCKER__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field twomeg_baseline_meas_dur */ +/** + * @defgroup mdm_regs_core_twomeg_baseline_meas_dur_field twomeg_baseline_meas_dur_field + * @brief macros for field twomeg_baseline_meas_dur + * @details 2'b00 -> 16; 2'b01 -> 24; 2'b10 -> 32; 2'b11 -> 40. 2M rate + * @{ + */ +#define MDM_PWRSTEP_ALT__TWOMEG_BASELINE_MEAS_DUR__SHIFT 17 +#define MDM_PWRSTEP_ALT__TWOMEG_BASELINE_MEAS_DUR__WIDTH 2 +#define MDM_PWRSTEP_ALT__TWOMEG_BASELINE_MEAS_DUR__MASK 0x00060000U +#define MDM_PWRSTEP_ALT__TWOMEG_BASELINE_MEAS_DUR__READ(src) \ + (((uint32_t)(src)\ + & 0x00060000U) >> 17) +#define MDM_PWRSTEP_ALT__TWOMEG_BASELINE_MEAS_DUR__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00060000U) +#define MDM_PWRSTEP_ALT__TWOMEG_BASELINE_MEAS_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00060000U) | (((uint32_t)(src) <<\ + 17) & 0x00060000U) +#define MDM_PWRSTEP_ALT__TWOMEG_BASELINE_MEAS_DUR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00060000U))) +#define MDM_PWRSTEP_ALT__TWOMEG_BASELINE_MEAS_DUR__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field twomeg_baseline_meas_delay */ +/** + * @defgroup mdm_regs_core_twomeg_baseline_meas_delay_field twomeg_baseline_meas_delay_field + * @brief macros for field twomeg_baseline_meas_delay + * @details Number of clocks between baseline and inband_pwr to compare 2'b00 -> 4; 2'b01 -> 8; 2'b10 -> 12; 2'b11 -> 16. 2M rate + * @{ + */ +#define MDM_PWRSTEP_ALT__TWOMEG_BASELINE_MEAS_DELAY__SHIFT 19 +#define MDM_PWRSTEP_ALT__TWOMEG_BASELINE_MEAS_DELAY__WIDTH 2 +#define MDM_PWRSTEP_ALT__TWOMEG_BASELINE_MEAS_DELAY__MASK 0x00180000U +#define MDM_PWRSTEP_ALT__TWOMEG_BASELINE_MEAS_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define MDM_PWRSTEP_ALT__TWOMEG_BASELINE_MEAS_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define MDM_PWRSTEP_ALT__TWOMEG_BASELINE_MEAS_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define MDM_PWRSTEP_ALT__TWOMEG_BASELINE_MEAS_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define MDM_PWRSTEP_ALT__TWOMEG_BASELINE_MEAS_DELAY__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field separate_pos_and_neg */ +/** + * @defgroup mdm_regs_core_separate_pos_and_neg_field separate_pos_and_neg_field + * @brief macros for field separate_pos_and_neg + * @details If bit is set, threshold positive and negative power steps separately + * @{ + */ +#define MDM_PWRSTEP_ALT__SEPARATE_POS_AND_NEG__SHIFT 21 +#define MDM_PWRSTEP_ALT__SEPARATE_POS_AND_NEG__WIDTH 1 +#define MDM_PWRSTEP_ALT__SEPARATE_POS_AND_NEG__MASK 0x00200000U +#define MDM_PWRSTEP_ALT__SEPARATE_POS_AND_NEG__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define MDM_PWRSTEP_ALT__SEPARATE_POS_AND_NEG__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define MDM_PWRSTEP_ALT__SEPARATE_POS_AND_NEG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define MDM_PWRSTEP_ALT__SEPARATE_POS_AND_NEG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define MDM_PWRSTEP_ALT__SEPARATE_POS_AND_NEG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define MDM_PWRSTEP_ALT__SEPARATE_POS_AND_NEG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define MDM_PWRSTEP_ALT__SEPARATE_POS_AND_NEG__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_PWRSTEP_ALT__TYPE uint32_t +#define MDM_PWRSTEP_ALT__READ 0x003fffffU +#define MDM_PWRSTEP_ALT__WRITE 0x003fffffU +#define MDM_PWRSTEP_ALT__PRESERVED 0x00000000U +#define MDM_PWRSTEP_ALT__RESET_VALUE 0x000d4684U + +#endif /* __MDM_PWRSTEP_ALT_MACRO__ */ + +/** @} end of pwrstep_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_agcpwr */ +/** + * @defgroup mdm_regs_core_agcpwr agcpwr + * @brief Power measurement targets definitions. + * @{ + */ +#ifndef __MDM_AGCPWR_MACRO__ +#define __MDM_AGCPWR_MACRO__ + +/* macros for field inband_target */ +/** + * @defgroup mdm_regs_core_inband_target_field inband_target_field + * @brief macros for field inband_target + * @details Signed, relative to full scale agc filter output 7'h65 = -27 + * @{ + */ +#define MDM_AGCPWR__INBAND_TARGET__SHIFT 0 +#define MDM_AGCPWR__INBAND_TARGET__WIDTH 7 +#define MDM_AGCPWR__INBAND_TARGET__MASK 0x0000007fU +#define MDM_AGCPWR__INBAND_TARGET__READ(src) ((uint32_t)(src) & 0x0000007fU) +#define MDM_AGCPWR__INBAND_TARGET__WRITE(src) ((uint32_t)(src) & 0x0000007fU) +#define MDM_AGCPWR__INBAND_TARGET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define MDM_AGCPWR__INBAND_TARGET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000007fU))) +#define MDM_AGCPWR__INBAND_TARGET__RESET_VALUE 0x00000065U +/** @} */ + +/* macros for field adc_max_target */ +/** + * @defgroup mdm_regs_core_adc_max_target_field adc_max_target_field + * @brief macros for field adc_max_target + * @details Signed, relative to full scale ADC. 7'h77 = -9. + * @{ + */ +#define MDM_AGCPWR__ADC_MAX_TARGET__SHIFT 7 +#define MDM_AGCPWR__ADC_MAX_TARGET__WIDTH 7 +#define MDM_AGCPWR__ADC_MAX_TARGET__MASK 0x00003f80U +#define MDM_AGCPWR__ADC_MAX_TARGET__READ(src) \ + (((uint32_t)(src)\ + & 0x00003f80U) >> 7) +#define MDM_AGCPWR__ADC_MAX_TARGET__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00003f80U) +#define MDM_AGCPWR__ADC_MAX_TARGET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((uint32_t)(src) <<\ + 7) & 0x00003f80U) +#define MDM_AGCPWR__ADC_MAX_TARGET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00003f80U))) +#define MDM_AGCPWR__ADC_MAX_TARGET__RESET_VALUE 0x00000077U +/** @} */ + +/* macros for field twomeg_inband_target */ +/** + * @defgroup mdm_regs_core_twomeg_inband_target_field twomeg_inband_target_field + * @brief macros for field twomeg_inband_target + * @details Signed, relative to full scale agc filter output 7'h68 = -24 + * @{ + */ +#define MDM_AGCPWR__TWOMEG_INBAND_TARGET__SHIFT 14 +#define MDM_AGCPWR__TWOMEG_INBAND_TARGET__WIDTH 7 +#define MDM_AGCPWR__TWOMEG_INBAND_TARGET__MASK 0x001fc000U +#define MDM_AGCPWR__TWOMEG_INBAND_TARGET__READ(src) \ + (((uint32_t)(src)\ + & 0x001fc000U) >> 14) +#define MDM_AGCPWR__TWOMEG_INBAND_TARGET__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x001fc000U) +#define MDM_AGCPWR__TWOMEG_INBAND_TARGET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001fc000U) | (((uint32_t)(src) <<\ + 14) & 0x001fc000U) +#define MDM_AGCPWR__TWOMEG_INBAND_TARGET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x001fc000U))) +#define MDM_AGCPWR__TWOMEG_INBAND_TARGET__RESET_VALUE 0x00000068U +/** @} */ + +/* macros for field inband_pwr_err_thr_hi */ +/** + * @defgroup mdm_regs_core_inband_pwr_err_thr_hi_field inband_pwr_err_thr_hi_field + * @brief macros for field inband_pwr_err_thr_hi + * @details Threshold to check if inband power is within this range of inband target after fine gain change, for positive gain_delta1 + * @{ + */ +#define MDM_AGCPWR__INBAND_PWR_ERR_THR_HI__SHIFT 21 +#define MDM_AGCPWR__INBAND_PWR_ERR_THR_HI__WIDTH 4 +#define MDM_AGCPWR__INBAND_PWR_ERR_THR_HI__MASK 0x01e00000U +#define MDM_AGCPWR__INBAND_PWR_ERR_THR_HI__READ(src) \ + (((uint32_t)(src)\ + & 0x01e00000U) >> 21) +#define MDM_AGCPWR__INBAND_PWR_ERR_THR_HI__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x01e00000U) +#define MDM_AGCPWR__INBAND_PWR_ERR_THR_HI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01e00000U) | (((uint32_t)(src) <<\ + 21) & 0x01e00000U) +#define MDM_AGCPWR__INBAND_PWR_ERR_THR_HI__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x01e00000U))) +#define MDM_AGCPWR__INBAND_PWR_ERR_THR_HI__RESET_VALUE 0x0000000cU +/** @} */ + +/* macros for field inband_pwr_err_thr_lo */ +/** + * @defgroup mdm_regs_core_inband_pwr_err_thr_lo_field inband_pwr_err_thr_lo_field + * @brief macros for field inband_pwr_err_thr_lo + * @details Threshold to check if inband power is within this range of inband target after fine gain change, for negative gain_delta1 + * @{ + */ +#define MDM_AGCPWR__INBAND_PWR_ERR_THR_LO__SHIFT 25 +#define MDM_AGCPWR__INBAND_PWR_ERR_THR_LO__WIDTH 4 +#define MDM_AGCPWR__INBAND_PWR_ERR_THR_LO__MASK 0x1e000000U +#define MDM_AGCPWR__INBAND_PWR_ERR_THR_LO__READ(src) \ + (((uint32_t)(src)\ + & 0x1e000000U) >> 25) +#define MDM_AGCPWR__INBAND_PWR_ERR_THR_LO__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x1e000000U) +#define MDM_AGCPWR__INBAND_PWR_ERR_THR_LO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1e000000U) | (((uint32_t)(src) <<\ + 25) & 0x1e000000U) +#define MDM_AGCPWR__INBAND_PWR_ERR_THR_LO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x1e000000U))) +#define MDM_AGCPWR__INBAND_PWR_ERR_THR_LO__RESET_VALUE 0x0000000cU +/** @} */ +#define MDM_AGCPWR__TYPE uint32_t +#define MDM_AGCPWR__READ 0x1fffffffU +#define MDM_AGCPWR__WRITE 0x1fffffffU +#define MDM_AGCPWR__PRESERVED 0x00000000U +#define MDM_AGCPWR__RESET_VALUE 0x199a3be5U + +#endif /* __MDM_AGCPWR_MACRO__ */ + +/** @} end of agcpwr */ + +/* macros for BlueprintGlobalNameSpace::MDM_agcpwr_alt */ +/** + * @defgroup mdm_regs_core_agcpwr_alt agcpwr_alt + * @brief Power measurement targets, alternate set definitions. + * @{ + */ +#ifndef __MDM_AGCPWR_ALT_MACRO__ +#define __MDM_AGCPWR_ALT_MACRO__ + +/* macros for field inband_target */ +/** + * @defgroup mdm_regs_core_inband_target_field inband_target_field + * @brief macros for field inband_target + * @details Signed, relative to full scale agc filter output 7'h65 = -27 + * @{ + */ +#define MDM_AGCPWR_ALT__INBAND_TARGET__SHIFT 0 +#define MDM_AGCPWR_ALT__INBAND_TARGET__WIDTH 7 +#define MDM_AGCPWR_ALT__INBAND_TARGET__MASK 0x0000007fU +#define MDM_AGCPWR_ALT__INBAND_TARGET__READ(src) \ + ((uint32_t)(src)\ + & 0x0000007fU) +#define MDM_AGCPWR_ALT__INBAND_TARGET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000007fU) +#define MDM_AGCPWR_ALT__INBAND_TARGET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define MDM_AGCPWR_ALT__INBAND_TARGET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000007fU))) +#define MDM_AGCPWR_ALT__INBAND_TARGET__RESET_VALUE 0x00000065U +/** @} */ + +/* macros for field adc_max_target */ +/** + * @defgroup mdm_regs_core_adc_max_target_field adc_max_target_field + * @brief macros for field adc_max_target + * @details Signed, relative to full scale ADC. 7'h77 = -9. + * @{ + */ +#define MDM_AGCPWR_ALT__ADC_MAX_TARGET__SHIFT 7 +#define MDM_AGCPWR_ALT__ADC_MAX_TARGET__WIDTH 7 +#define MDM_AGCPWR_ALT__ADC_MAX_TARGET__MASK 0x00003f80U +#define MDM_AGCPWR_ALT__ADC_MAX_TARGET__READ(src) \ + (((uint32_t)(src)\ + & 0x00003f80U) >> 7) +#define MDM_AGCPWR_ALT__ADC_MAX_TARGET__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00003f80U) +#define MDM_AGCPWR_ALT__ADC_MAX_TARGET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((uint32_t)(src) <<\ + 7) & 0x00003f80U) +#define MDM_AGCPWR_ALT__ADC_MAX_TARGET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00003f80U))) +#define MDM_AGCPWR_ALT__ADC_MAX_TARGET__RESET_VALUE 0x00000077U +/** @} */ + +/* macros for field twomeg_inband_target */ +/** + * @defgroup mdm_regs_core_twomeg_inband_target_field twomeg_inband_target_field + * @brief macros for field twomeg_inband_target + * @details Signed, relative to full scale agc filter output 7'h68 = -24 + * @{ + */ +#define MDM_AGCPWR_ALT__TWOMEG_INBAND_TARGET__SHIFT 14 +#define MDM_AGCPWR_ALT__TWOMEG_INBAND_TARGET__WIDTH 7 +#define MDM_AGCPWR_ALT__TWOMEG_INBAND_TARGET__MASK 0x001fc000U +#define MDM_AGCPWR_ALT__TWOMEG_INBAND_TARGET__READ(src) \ + (((uint32_t)(src)\ + & 0x001fc000U) >> 14) +#define MDM_AGCPWR_ALT__TWOMEG_INBAND_TARGET__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x001fc000U) +#define MDM_AGCPWR_ALT__TWOMEG_INBAND_TARGET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001fc000U) | (((uint32_t)(src) <<\ + 14) & 0x001fc000U) +#define MDM_AGCPWR_ALT__TWOMEG_INBAND_TARGET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x001fc000U))) +#define MDM_AGCPWR_ALT__TWOMEG_INBAND_TARGET__RESET_VALUE 0x00000068U +/** @} */ + +/* macros for field inband_pwr_err_thr_hi */ +/** + * @defgroup mdm_regs_core_inband_pwr_err_thr_hi_field inband_pwr_err_thr_hi_field + * @brief macros for field inband_pwr_err_thr_hi + * @details Threshold to check if inband power is within this range of inband target after fine gain change, for positive gain_delta1 + * @{ + */ +#define MDM_AGCPWR_ALT__INBAND_PWR_ERR_THR_HI__SHIFT 21 +#define MDM_AGCPWR_ALT__INBAND_PWR_ERR_THR_HI__WIDTH 4 +#define MDM_AGCPWR_ALT__INBAND_PWR_ERR_THR_HI__MASK 0x01e00000U +#define MDM_AGCPWR_ALT__INBAND_PWR_ERR_THR_HI__READ(src) \ + (((uint32_t)(src)\ + & 0x01e00000U) >> 21) +#define MDM_AGCPWR_ALT__INBAND_PWR_ERR_THR_HI__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x01e00000U) +#define MDM_AGCPWR_ALT__INBAND_PWR_ERR_THR_HI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01e00000U) | (((uint32_t)(src) <<\ + 21) & 0x01e00000U) +#define MDM_AGCPWR_ALT__INBAND_PWR_ERR_THR_HI__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x01e00000U))) +#define MDM_AGCPWR_ALT__INBAND_PWR_ERR_THR_HI__RESET_VALUE 0x0000000cU +/** @} */ + +/* macros for field inband_pwr_err_thr_lo */ +/** + * @defgroup mdm_regs_core_inband_pwr_err_thr_lo_field inband_pwr_err_thr_lo_field + * @brief macros for field inband_pwr_err_thr_lo + * @details Threshold to check if inband power is within this range of inband target after fine gain change, for negative gain_delta1 + * @{ + */ +#define MDM_AGCPWR_ALT__INBAND_PWR_ERR_THR_LO__SHIFT 25 +#define MDM_AGCPWR_ALT__INBAND_PWR_ERR_THR_LO__WIDTH 4 +#define MDM_AGCPWR_ALT__INBAND_PWR_ERR_THR_LO__MASK 0x1e000000U +#define MDM_AGCPWR_ALT__INBAND_PWR_ERR_THR_LO__READ(src) \ + (((uint32_t)(src)\ + & 0x1e000000U) >> 25) +#define MDM_AGCPWR_ALT__INBAND_PWR_ERR_THR_LO__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x1e000000U) +#define MDM_AGCPWR_ALT__INBAND_PWR_ERR_THR_LO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1e000000U) | (((uint32_t)(src) <<\ + 25) & 0x1e000000U) +#define MDM_AGCPWR_ALT__INBAND_PWR_ERR_THR_LO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x1e000000U))) +#define MDM_AGCPWR_ALT__INBAND_PWR_ERR_THR_LO__RESET_VALUE 0x0000000cU +/** @} */ +#define MDM_AGCPWR_ALT__TYPE uint32_t +#define MDM_AGCPWR_ALT__READ 0x1fffffffU +#define MDM_AGCPWR_ALT__WRITE 0x1fffffffU +#define MDM_AGCPWR_ALT__PRESERVED 0x00000000U +#define MDM_AGCPWR_ALT__RESET_VALUE 0x199a3be5U + +#endif /* __MDM_AGCPWR_ALT_MACRO__ */ + +/** @} end of agcpwr_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_agcpwr2 */ +/** + * @defgroup mdm_regs_core_agcpwr2 agcpwr2 + * @brief Power control definitions. + * @{ + */ +#ifndef __MDM_AGCPWR2_MACRO__ +#define __MDM_AGCPWR2_MACRO__ + +/* macros for field meas_win */ +/** + * @defgroup mdm_regs_core_meas_win_field meas_win_field + * @brief macros for field meas_win + * @details Number of 16 MHz samples for power measurement. Encoding: 0 -> 4; 1 -> 8; 2 -> 12; 3 -> 16 When running front end at 8 MHz (1 Mb/s, 500 Kb/s, or 125 Kb/s), then this number is cut in half + * @{ + */ +#define MDM_AGCPWR2__MEAS_WIN__SHIFT 0 +#define MDM_AGCPWR2__MEAS_WIN__WIDTH 2 +#define MDM_AGCPWR2__MEAS_WIN__MASK 0x00000003U +#define MDM_AGCPWR2__MEAS_WIN__READ(src) ((uint32_t)(src) & 0x00000003U) +#define MDM_AGCPWR2__MEAS_WIN__WRITE(src) ((uint32_t)(src) & 0x00000003U) +#define MDM_AGCPWR2__MEAS_WIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define MDM_AGCPWR2__MEAS_WIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define MDM_AGCPWR2__MEAS_WIN__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field det_step */ +/** + * @defgroup mdm_regs_core_det_step_field det_step_field + * @brief macros for field det_step + * @details dB increase required for detection based on power step + * @{ + */ +#define MDM_AGCPWR2__DET_STEP__SHIFT 2 +#define MDM_AGCPWR2__DET_STEP__WIDTH 5 +#define MDM_AGCPWR2__DET_STEP__MASK 0x0000007cU +#define MDM_AGCPWR2__DET_STEP__READ(src) (((uint32_t)(src) & 0x0000007cU) >> 2) +#define MDM_AGCPWR2__DET_STEP__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000007cU) +#define MDM_AGCPWR2__DET_STEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007cU) | (((uint32_t)(src) <<\ + 2) & 0x0000007cU) +#define MDM_AGCPWR2__DET_STEP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000007cU))) +#define MDM_AGCPWR2__DET_STEP__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field det_step_delta */ +/** + * @defgroup mdm_regs_core_det_step_delta_field det_step_delta_field + * @brief macros for field det_step_delta + * @details Addition in dB to det_step if baseline power < det_min + baseline_blk_pwr_offset + * @{ + */ +#define MDM_AGCPWR2__DET_STEP_DELTA__SHIFT 7 +#define MDM_AGCPWR2__DET_STEP_DELTA__WIDTH 4 +#define MDM_AGCPWR2__DET_STEP_DELTA__MASK 0x00000780U +#define MDM_AGCPWR2__DET_STEP_DELTA__READ(src) \ + (((uint32_t)(src)\ + & 0x00000780U) >> 7) +#define MDM_AGCPWR2__DET_STEP_DELTA__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000780U) +#define MDM_AGCPWR2__DET_STEP_DELTA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000780U) | (((uint32_t)(src) <<\ + 7) & 0x00000780U) +#define MDM_AGCPWR2__DET_STEP_DELTA__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000780U))) +#define MDM_AGCPWR2__DET_STEP_DELTA__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field baseline_blk_pwr_offset */ +/** + * @defgroup mdm_regs_core_baseline_blk_pwr_offset_field baseline_blk_pwr_offset_field + * @brief macros for field baseline_blk_pwr_offset + * @details Used in comparison to adjust det_step + * @{ + */ +#define MDM_AGCPWR2__BASELINE_BLK_PWR_OFFSET__SHIFT 11 +#define MDM_AGCPWR2__BASELINE_BLK_PWR_OFFSET__WIDTH 6 +#define MDM_AGCPWR2__BASELINE_BLK_PWR_OFFSET__MASK 0x0001f800U +#define MDM_AGCPWR2__BASELINE_BLK_PWR_OFFSET__READ(src) \ + (((uint32_t)(src)\ + & 0x0001f800U) >> 11) +#define MDM_AGCPWR2__BASELINE_BLK_PWR_OFFSET__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x0001f800U) +#define MDM_AGCPWR2__BASELINE_BLK_PWR_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f800U) | (((uint32_t)(src) <<\ + 11) & 0x0001f800U) +#define MDM_AGCPWR2__BASELINE_BLK_PWR_OFFSET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x0001f800U))) +#define MDM_AGCPWR2__BASELINE_BLK_PWR_OFFSET__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field rssi_thr_to_force_ffe */ +/** + * @defgroup mdm_regs_core_rssi_thr_to_force_ffe_field rssi_thr_to_force_ffe_field + * @brief macros for field rssi_thr_to_force_ffe + * @details If RSSI is below this value, then use ffe (for uncoded only) 8'd127 implies always use ffe. 8'hab = -85 + * @{ + */ +#define MDM_AGCPWR2__RSSI_THR_TO_FORCE_FFE__SHIFT 17 +#define MDM_AGCPWR2__RSSI_THR_TO_FORCE_FFE__WIDTH 8 +#define MDM_AGCPWR2__RSSI_THR_TO_FORCE_FFE__MASK 0x01fe0000U +#define MDM_AGCPWR2__RSSI_THR_TO_FORCE_FFE__READ(src) \ + (((uint32_t)(src)\ + & 0x01fe0000U) >> 17) +#define MDM_AGCPWR2__RSSI_THR_TO_FORCE_FFE__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x01fe0000U) +#define MDM_AGCPWR2__RSSI_THR_TO_FORCE_FFE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01fe0000U) | (((uint32_t)(src) <<\ + 17) & 0x01fe0000U) +#define MDM_AGCPWR2__RSSI_THR_TO_FORCE_FFE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x01fe0000U))) +#define MDM_AGCPWR2__RSSI_THR_TO_FORCE_FFE__RESET_VALUE 0x000000abU +/** @} */ + +/* macros for field delay_total_pwr_for_blocker_det */ +/** + * @defgroup mdm_regs_core_delay_total_pwr_for_blocker_det_field delay_total_pwr_for_blocker_det_field + * @brief macros for field delay_total_pwr_for_blocker_det + * @details Delay on total_pwr for add_det_step delta Encoding: 2'b00 -> 0; 2'b01 -> 4; 2'b10 -> 8; 3'b11 -> 12 + * @{ + */ +#define MDM_AGCPWR2__DELAY_TOTAL_PWR_FOR_BLOCKER_DET__SHIFT 25 +#define MDM_AGCPWR2__DELAY_TOTAL_PWR_FOR_BLOCKER_DET__WIDTH 2 +#define MDM_AGCPWR2__DELAY_TOTAL_PWR_FOR_BLOCKER_DET__MASK 0x06000000U +#define MDM_AGCPWR2__DELAY_TOTAL_PWR_FOR_BLOCKER_DET__READ(src) \ + (((uint32_t)(src)\ + & 0x06000000U) >> 25) +#define MDM_AGCPWR2__DELAY_TOTAL_PWR_FOR_BLOCKER_DET__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x06000000U) +#define MDM_AGCPWR2__DELAY_TOTAL_PWR_FOR_BLOCKER_DET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x06000000U) | (((uint32_t)(src) <<\ + 25) & 0x06000000U) +#define MDM_AGCPWR2__DELAY_TOTAL_PWR_FOR_BLOCKER_DET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x06000000U))) +#define MDM_AGCPWR2__DELAY_TOTAL_PWR_FOR_BLOCKER_DET__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field twomeg_delay_total_pwr_for_blocker_det */ +/** + * @defgroup mdm_regs_core_twomeg_delay_total_pwr_for_blocker_det_field twomeg_delay_total_pwr_for_blocker_det_field + * @brief macros for field twomeg_delay_total_pwr_for_blocker_det + * @details 2M rate. Delay on total_pwr for add_det_step delta Encoding: 2'b00 -> 0; 2'b01 -> 4; 2'b10 -> 8; 3'b11 -> 12 + * @{ + */ +#define MDM_AGCPWR2__TWOMEG_DELAY_TOTAL_PWR_FOR_BLOCKER_DET__SHIFT 27 +#define MDM_AGCPWR2__TWOMEG_DELAY_TOTAL_PWR_FOR_BLOCKER_DET__WIDTH 2 +#define MDM_AGCPWR2__TWOMEG_DELAY_TOTAL_PWR_FOR_BLOCKER_DET__MASK 0x18000000U +#define MDM_AGCPWR2__TWOMEG_DELAY_TOTAL_PWR_FOR_BLOCKER_DET__READ(src) \ + (((uint32_t)(src)\ + & 0x18000000U) >> 27) +#define MDM_AGCPWR2__TWOMEG_DELAY_TOTAL_PWR_FOR_BLOCKER_DET__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x18000000U) +#define MDM_AGCPWR2__TWOMEG_DELAY_TOTAL_PWR_FOR_BLOCKER_DET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x18000000U) | (((uint32_t)(src) <<\ + 27) & 0x18000000U) +#define MDM_AGCPWR2__TWOMEG_DELAY_TOTAL_PWR_FOR_BLOCKER_DET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x18000000U))) +#define MDM_AGCPWR2__TWOMEG_DELAY_TOTAL_PWR_FOR_BLOCKER_DET__RESET_VALUE \ + 0x00000002U +/** @} */ +#define MDM_AGCPWR2__TYPE uint32_t +#define MDM_AGCPWR2__READ 0x1fffffffU +#define MDM_AGCPWR2__WRITE 0x1fffffffU +#define MDM_AGCPWR2__PRESERVED 0x00000000U +#define MDM_AGCPWR2__RESET_VALUE 0x1556411bU + +#endif /* __MDM_AGCPWR2_MACRO__ */ + +/** @} end of agcpwr2 */ + +/* macros for BlueprintGlobalNameSpace::MDM_agcpwr2_alt */ +/** + * @defgroup mdm_regs_core_agcpwr2_alt agcpwr2_alt + * @brief Power control, alternate set definitions. + * @{ + */ +#ifndef __MDM_AGCPWR2_ALT_MACRO__ +#define __MDM_AGCPWR2_ALT_MACRO__ + +/* macros for field meas_win */ +/** + * @defgroup mdm_regs_core_meas_win_field meas_win_field + * @brief macros for field meas_win + * @details Number of 16 MHz samples for power measurement. Encoding: 0 -> 4; 1 -> 8; 2 -> 12; 3 -> 16 When running front end at 8 MHz (1 Mb/s, 500 Kb/s, or 125 Kb/s), then this number is cut in half + * @{ + */ +#define MDM_AGCPWR2_ALT__MEAS_WIN__SHIFT 0 +#define MDM_AGCPWR2_ALT__MEAS_WIN__WIDTH 2 +#define MDM_AGCPWR2_ALT__MEAS_WIN__MASK 0x00000003U +#define MDM_AGCPWR2_ALT__MEAS_WIN__READ(src) ((uint32_t)(src) & 0x00000003U) +#define MDM_AGCPWR2_ALT__MEAS_WIN__WRITE(src) ((uint32_t)(src) & 0x00000003U) +#define MDM_AGCPWR2_ALT__MEAS_WIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define MDM_AGCPWR2_ALT__MEAS_WIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define MDM_AGCPWR2_ALT__MEAS_WIN__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field det_step */ +/** + * @defgroup mdm_regs_core_det_step_field det_step_field + * @brief macros for field det_step + * @details dB increase required for detection based on power step + * @{ + */ +#define MDM_AGCPWR2_ALT__DET_STEP__SHIFT 2 +#define MDM_AGCPWR2_ALT__DET_STEP__WIDTH 5 +#define MDM_AGCPWR2_ALT__DET_STEP__MASK 0x0000007cU +#define MDM_AGCPWR2_ALT__DET_STEP__READ(src) \ + (((uint32_t)(src)\ + & 0x0000007cU) >> 2) +#define MDM_AGCPWR2_ALT__DET_STEP__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000007cU) +#define MDM_AGCPWR2_ALT__DET_STEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007cU) | (((uint32_t)(src) <<\ + 2) & 0x0000007cU) +#define MDM_AGCPWR2_ALT__DET_STEP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000007cU))) +#define MDM_AGCPWR2_ALT__DET_STEP__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field det_step_delta */ +/** + * @defgroup mdm_regs_core_det_step_delta_field det_step_delta_field + * @brief macros for field det_step_delta + * @details Addition in dB to det_step if baseline power < det_min + baseline_blk_pwr_offset + * @{ + */ +#define MDM_AGCPWR2_ALT__DET_STEP_DELTA__SHIFT 7 +#define MDM_AGCPWR2_ALT__DET_STEP_DELTA__WIDTH 4 +#define MDM_AGCPWR2_ALT__DET_STEP_DELTA__MASK 0x00000780U +#define MDM_AGCPWR2_ALT__DET_STEP_DELTA__READ(src) \ + (((uint32_t)(src)\ + & 0x00000780U) >> 7) +#define MDM_AGCPWR2_ALT__DET_STEP_DELTA__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000780U) +#define MDM_AGCPWR2_ALT__DET_STEP_DELTA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000780U) | (((uint32_t)(src) <<\ + 7) & 0x00000780U) +#define MDM_AGCPWR2_ALT__DET_STEP_DELTA__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000780U))) +#define MDM_AGCPWR2_ALT__DET_STEP_DELTA__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field baseline_blk_pwr_offset */ +/** + * @defgroup mdm_regs_core_baseline_blk_pwr_offset_field baseline_blk_pwr_offset_field + * @brief macros for field baseline_blk_pwr_offset + * @details Used in comparison to adjust det_step + * @{ + */ +#define MDM_AGCPWR2_ALT__BASELINE_BLK_PWR_OFFSET__SHIFT 11 +#define MDM_AGCPWR2_ALT__BASELINE_BLK_PWR_OFFSET__WIDTH 6 +#define MDM_AGCPWR2_ALT__BASELINE_BLK_PWR_OFFSET__MASK 0x0001f800U +#define MDM_AGCPWR2_ALT__BASELINE_BLK_PWR_OFFSET__READ(src) \ + (((uint32_t)(src)\ + & 0x0001f800U) >> 11) +#define MDM_AGCPWR2_ALT__BASELINE_BLK_PWR_OFFSET__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x0001f800U) +#define MDM_AGCPWR2_ALT__BASELINE_BLK_PWR_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f800U) | (((uint32_t)(src) <<\ + 11) & 0x0001f800U) +#define MDM_AGCPWR2_ALT__BASELINE_BLK_PWR_OFFSET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x0001f800U))) +#define MDM_AGCPWR2_ALT__BASELINE_BLK_PWR_OFFSET__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field rssi_thr_to_force_ffe */ +/** + * @defgroup mdm_regs_core_rssi_thr_to_force_ffe_field rssi_thr_to_force_ffe_field + * @brief macros for field rssi_thr_to_force_ffe + * @details If RSSI is below this value, then use ffe (for uncoded only) 8'd127 implies always use ffe. 8'hab = -85 + * @{ + */ +#define MDM_AGCPWR2_ALT__RSSI_THR_TO_FORCE_FFE__SHIFT 17 +#define MDM_AGCPWR2_ALT__RSSI_THR_TO_FORCE_FFE__WIDTH 8 +#define MDM_AGCPWR2_ALT__RSSI_THR_TO_FORCE_FFE__MASK 0x01fe0000U +#define MDM_AGCPWR2_ALT__RSSI_THR_TO_FORCE_FFE__READ(src) \ + (((uint32_t)(src)\ + & 0x01fe0000U) >> 17) +#define MDM_AGCPWR2_ALT__RSSI_THR_TO_FORCE_FFE__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x01fe0000U) +#define MDM_AGCPWR2_ALT__RSSI_THR_TO_FORCE_FFE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01fe0000U) | (((uint32_t)(src) <<\ + 17) & 0x01fe0000U) +#define MDM_AGCPWR2_ALT__RSSI_THR_TO_FORCE_FFE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x01fe0000U))) +#define MDM_AGCPWR2_ALT__RSSI_THR_TO_FORCE_FFE__RESET_VALUE 0x000000abU +/** @} */ + +/* macros for field delay_total_pwr_for_blocker_det */ +/** + * @defgroup mdm_regs_core_delay_total_pwr_for_blocker_det_field delay_total_pwr_for_blocker_det_field + * @brief macros for field delay_total_pwr_for_blocker_det + * @details Delay on total_pwr for add_det_step delta Encoding: 2'b00 -> 0; 2'b01 -> 4; 2'b10 -> 8; 3'b11 -> 12 + * @{ + */ +#define MDM_AGCPWR2_ALT__DELAY_TOTAL_PWR_FOR_BLOCKER_DET__SHIFT 25 +#define MDM_AGCPWR2_ALT__DELAY_TOTAL_PWR_FOR_BLOCKER_DET__WIDTH 2 +#define MDM_AGCPWR2_ALT__DELAY_TOTAL_PWR_FOR_BLOCKER_DET__MASK 0x06000000U +#define MDM_AGCPWR2_ALT__DELAY_TOTAL_PWR_FOR_BLOCKER_DET__READ(src) \ + (((uint32_t)(src)\ + & 0x06000000U) >> 25) +#define MDM_AGCPWR2_ALT__DELAY_TOTAL_PWR_FOR_BLOCKER_DET__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x06000000U) +#define MDM_AGCPWR2_ALT__DELAY_TOTAL_PWR_FOR_BLOCKER_DET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x06000000U) | (((uint32_t)(src) <<\ + 25) & 0x06000000U) +#define MDM_AGCPWR2_ALT__DELAY_TOTAL_PWR_FOR_BLOCKER_DET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x06000000U))) +#define MDM_AGCPWR2_ALT__DELAY_TOTAL_PWR_FOR_BLOCKER_DET__RESET_VALUE \ + 0x00000002U +/** @} */ + +/* macros for field twomeg_delay_total_pwr_for_blocker_det */ +/** + * @defgroup mdm_regs_core_twomeg_delay_total_pwr_for_blocker_det_field twomeg_delay_total_pwr_for_blocker_det_field + * @brief macros for field twomeg_delay_total_pwr_for_blocker_det + * @details 2M rate. Delay on total_pwr for add_det_step delta Encoding: 2'b00 -> 0; 2'b01 -> 4; 2'b10 -> 8; 3'b11 -> 12 + * @{ + */ +#define MDM_AGCPWR2_ALT__TWOMEG_DELAY_TOTAL_PWR_FOR_BLOCKER_DET__SHIFT 27 +#define MDM_AGCPWR2_ALT__TWOMEG_DELAY_TOTAL_PWR_FOR_BLOCKER_DET__WIDTH 2 +#define MDM_AGCPWR2_ALT__TWOMEG_DELAY_TOTAL_PWR_FOR_BLOCKER_DET__MASK \ + 0x18000000U +#define MDM_AGCPWR2_ALT__TWOMEG_DELAY_TOTAL_PWR_FOR_BLOCKER_DET__READ(src) \ + (((uint32_t)(src)\ + & 0x18000000U) >> 27) +#define MDM_AGCPWR2_ALT__TWOMEG_DELAY_TOTAL_PWR_FOR_BLOCKER_DET__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x18000000U) +#define MDM_AGCPWR2_ALT__TWOMEG_DELAY_TOTAL_PWR_FOR_BLOCKER_DET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x18000000U) | (((uint32_t)(src) <<\ + 27) & 0x18000000U) +#define MDM_AGCPWR2_ALT__TWOMEG_DELAY_TOTAL_PWR_FOR_BLOCKER_DET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x18000000U))) +#define MDM_AGCPWR2_ALT__TWOMEG_DELAY_TOTAL_PWR_FOR_BLOCKER_DET__RESET_VALUE \ + 0x00000002U +/** @} */ +#define MDM_AGCPWR2_ALT__TYPE uint32_t +#define MDM_AGCPWR2_ALT__READ 0x1fffffffU +#define MDM_AGCPWR2_ALT__WRITE 0x1fffffffU +#define MDM_AGCPWR2_ALT__PRESERVED 0x00000000U +#define MDM_AGCPWR2_ALT__RESET_VALUE 0x1556411bU + +#endif /* __MDM_AGCPWR2_ALT_MACRO__ */ + +/** @} end of agcpwr2_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_agctime */ +/** + * @defgroup mdm_regs_core_agctime agctime + * @brief agc delays definitions. + * @{ + */ +#ifndef __MDM_AGCTIME_MACRO__ +#define __MDM_AGCTIME_MACRO__ + +/* macros for field gain_settle */ +/** + * @defgroup mdm_regs_core_gain_settle_field gain_settle_field + * @brief macros for field gain_settle + * @details number of 16 MHz clocks from gain change to when coarse/saturation measurements can begin. MUST BE EVEN. Register replicated for 2 Mb/s + * @{ + */ +#define MDM_AGCTIME__GAIN_SETTLE__SHIFT 0 +#define MDM_AGCTIME__GAIN_SETTLE__WIDTH 6 +#define MDM_AGCTIME__GAIN_SETTLE__MASK 0x0000003fU +#define MDM_AGCTIME__GAIN_SETTLE__READ(src) ((uint32_t)(src) & 0x0000003fU) +#define MDM_AGCTIME__GAIN_SETTLE__WRITE(src) ((uint32_t)(src) & 0x0000003fU) +#define MDM_AGCTIME__GAIN_SETTLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define MDM_AGCTIME__GAIN_SETTLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define MDM_AGCTIME__GAIN_SETTLE__RESET_VALUE 0x0000001cU +/** @} */ + +/* macros for field filt_settle */ +/** + * @defgroup mdm_regs_core_filt_settle_field filt_settle_field + * @brief macros for field filt_settle + * @details Number of 16 MHz cycles for agc filter to settle. MUST BE EVEN. Register replicated for 2 Mb/s + * @{ + */ +#define MDM_AGCTIME__FILT_SETTLE__SHIFT 25 +#define MDM_AGCTIME__FILT_SETTLE__WIDTH 7 +#define MDM_AGCTIME__FILT_SETTLE__MASK 0xfe000000U +#define MDM_AGCTIME__FILT_SETTLE__READ(src) \ + (((uint32_t)(src)\ + & 0xfe000000U) >> 25) +#define MDM_AGCTIME__FILT_SETTLE__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0xfe000000U) +#define MDM_AGCTIME__FILT_SETTLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfe000000U) | (((uint32_t)(src) <<\ + 25) & 0xfe000000U) +#define MDM_AGCTIME__FILT_SETTLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0xfe000000U))) +#define MDM_AGCTIME__FILT_SETTLE__RESET_VALUE 0x0000001cU +/** @} */ +#define MDM_AGCTIME__TYPE uint32_t +#define MDM_AGCTIME__READ 0xfe00003fU +#define MDM_AGCTIME__WRITE 0xfe00003fU +#define MDM_AGCTIME__PRESERVED 0x00000000U +#define MDM_AGCTIME__RESET_VALUE 0x3800001cU + +#endif /* __MDM_AGCTIME_MACRO__ */ + +/** @} end of agctime */ + +/* macros for BlueprintGlobalNameSpace::MDM_agctime_alt */ +/** + * @defgroup mdm_regs_core_agctime_alt agctime_alt + * @brief agc delays, alternate set definitions. + * @{ + */ +#ifndef __MDM_AGCTIME_ALT_MACRO__ +#define __MDM_AGCTIME_ALT_MACRO__ + +/* macros for field gain_settle */ +/** + * @defgroup mdm_regs_core_gain_settle_field gain_settle_field + * @brief macros for field gain_settle + * @details number of 16 MHz clocks from gain change to when coarse/saturation measurements can begin. MUST BE EVEN. Register replicated for 2 Mb/s + * @{ + */ +#define MDM_AGCTIME_ALT__GAIN_SETTLE__SHIFT 0 +#define MDM_AGCTIME_ALT__GAIN_SETTLE__WIDTH 6 +#define MDM_AGCTIME_ALT__GAIN_SETTLE__MASK 0x0000003fU +#define MDM_AGCTIME_ALT__GAIN_SETTLE__READ(src) ((uint32_t)(src) & 0x0000003fU) +#define MDM_AGCTIME_ALT__GAIN_SETTLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_AGCTIME_ALT__GAIN_SETTLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define MDM_AGCTIME_ALT__GAIN_SETTLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define MDM_AGCTIME_ALT__GAIN_SETTLE__RESET_VALUE 0x0000001cU +/** @} */ + +/* macros for field filt_settle */ +/** + * @defgroup mdm_regs_core_filt_settle_field filt_settle_field + * @brief macros for field filt_settle + * @details Number of 16 MHz cycles for agc filter to settle. MUST BE EVEN. Register replicated for 2 Mb/s + * @{ + */ +#define MDM_AGCTIME_ALT__FILT_SETTLE__SHIFT 25 +#define MDM_AGCTIME_ALT__FILT_SETTLE__WIDTH 7 +#define MDM_AGCTIME_ALT__FILT_SETTLE__MASK 0xfe000000U +#define MDM_AGCTIME_ALT__FILT_SETTLE__READ(src) \ + (((uint32_t)(src)\ + & 0xfe000000U) >> 25) +#define MDM_AGCTIME_ALT__FILT_SETTLE__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0xfe000000U) +#define MDM_AGCTIME_ALT__FILT_SETTLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfe000000U) | (((uint32_t)(src) <<\ + 25) & 0xfe000000U) +#define MDM_AGCTIME_ALT__FILT_SETTLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0xfe000000U))) +#define MDM_AGCTIME_ALT__FILT_SETTLE__RESET_VALUE 0x0000001cU +/** @} */ +#define MDM_AGCTIME_ALT__TYPE uint32_t +#define MDM_AGCTIME_ALT__READ 0xfe00003fU +#define MDM_AGCTIME_ALT__WRITE 0xfe00003fU +#define MDM_AGCTIME_ALT__PRESERVED 0x00000000U +#define MDM_AGCTIME_ALT__RESET_VALUE 0x3800001cU + +#endif /* __MDM_AGCTIME_ALT_MACRO__ */ + +/** @} end of agctime_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_twomeg_agctime */ +/** + * @defgroup mdm_regs_core_twomeg_agctime twomeg_agctime + * @brief agc delays for 2 Mb/s definitions. + * @{ + */ +#ifndef __MDM_TWOMEG_AGCTIME_MACRO__ +#define __MDM_TWOMEG_AGCTIME_MACRO__ + +/* macros for field gain_settle */ +/** + * @defgroup mdm_regs_core_gain_settle_field gain_settle_field + * @brief macros for field gain_settle + * @details number of 16 MHz clocks from gain change to when coarse/saturation measurements can begin. 2 Mb/s version of register + * @{ + */ +#define MDM_TWOMEG_AGCTIME__GAIN_SETTLE__SHIFT 0 +#define MDM_TWOMEG_AGCTIME__GAIN_SETTLE__WIDTH 6 +#define MDM_TWOMEG_AGCTIME__GAIN_SETTLE__MASK 0x0000003fU +#define MDM_TWOMEG_AGCTIME__GAIN_SETTLE__READ(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_TWOMEG_AGCTIME__GAIN_SETTLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_TWOMEG_AGCTIME__GAIN_SETTLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define MDM_TWOMEG_AGCTIME__GAIN_SETTLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define MDM_TWOMEG_AGCTIME__GAIN_SETTLE__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field filt_settle */ +/** + * @defgroup mdm_regs_core_filt_settle_field filt_settle_field + * @brief macros for field filt_settle + * @details Number of 16 MHz cycles for agc filter to settle. 2 Mb/s version of register + * @{ + */ +#define MDM_TWOMEG_AGCTIME__FILT_SETTLE__SHIFT 25 +#define MDM_TWOMEG_AGCTIME__FILT_SETTLE__WIDTH 7 +#define MDM_TWOMEG_AGCTIME__FILT_SETTLE__MASK 0xfe000000U +#define MDM_TWOMEG_AGCTIME__FILT_SETTLE__READ(src) \ + (((uint32_t)(src)\ + & 0xfe000000U) >> 25) +#define MDM_TWOMEG_AGCTIME__FILT_SETTLE__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0xfe000000U) +#define MDM_TWOMEG_AGCTIME__FILT_SETTLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfe000000U) | (((uint32_t)(src) <<\ + 25) & 0xfe000000U) +#define MDM_TWOMEG_AGCTIME__FILT_SETTLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0xfe000000U))) +#define MDM_TWOMEG_AGCTIME__FILT_SETTLE__RESET_VALUE 0x00000010U +/** @} */ +#define MDM_TWOMEG_AGCTIME__TYPE uint32_t +#define MDM_TWOMEG_AGCTIME__READ 0xfe00003fU +#define MDM_TWOMEG_AGCTIME__WRITE 0xfe00003fU +#define MDM_TWOMEG_AGCTIME__PRESERVED 0x00000000U +#define MDM_TWOMEG_AGCTIME__RESET_VALUE 0x20000010U + +#endif /* __MDM_TWOMEG_AGCTIME_MACRO__ */ + +/** @} end of twomeg_agctime */ + +/* macros for BlueprintGlobalNameSpace::MDM_twomeg_agctime_alt */ +/** + * @defgroup mdm_regs_core_twomeg_agctime_alt twomeg_agctime_alt + * @brief agc delays for 2 Mb/s definitions. + * @{ + */ +#ifndef __MDM_TWOMEG_AGCTIME_ALT_MACRO__ +#define __MDM_TWOMEG_AGCTIME_ALT_MACRO__ + +/* macros for field gain_settle */ +/** + * @defgroup mdm_regs_core_gain_settle_field gain_settle_field + * @brief macros for field gain_settle + * @details number of 16 MHz clocks from gain change to when coarse/saturation measurements can begin. 2 Mb/s version of register + * @{ + */ +#define MDM_TWOMEG_AGCTIME_ALT__GAIN_SETTLE__SHIFT 0 +#define MDM_TWOMEG_AGCTIME_ALT__GAIN_SETTLE__WIDTH 6 +#define MDM_TWOMEG_AGCTIME_ALT__GAIN_SETTLE__MASK 0x0000003fU +#define MDM_TWOMEG_AGCTIME_ALT__GAIN_SETTLE__READ(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_TWOMEG_AGCTIME_ALT__GAIN_SETTLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_TWOMEG_AGCTIME_ALT__GAIN_SETTLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define MDM_TWOMEG_AGCTIME_ALT__GAIN_SETTLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define MDM_TWOMEG_AGCTIME_ALT__GAIN_SETTLE__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field filt_settle */ +/** + * @defgroup mdm_regs_core_filt_settle_field filt_settle_field + * @brief macros for field filt_settle + * @details Number of 16 MHz cycles for agc filter to settle. 2 Mb/s version of register + * @{ + */ +#define MDM_TWOMEG_AGCTIME_ALT__FILT_SETTLE__SHIFT 25 +#define MDM_TWOMEG_AGCTIME_ALT__FILT_SETTLE__WIDTH 7 +#define MDM_TWOMEG_AGCTIME_ALT__FILT_SETTLE__MASK 0xfe000000U +#define MDM_TWOMEG_AGCTIME_ALT__FILT_SETTLE__READ(src) \ + (((uint32_t)(src)\ + & 0xfe000000U) >> 25) +#define MDM_TWOMEG_AGCTIME_ALT__FILT_SETTLE__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0xfe000000U) +#define MDM_TWOMEG_AGCTIME_ALT__FILT_SETTLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfe000000U) | (((uint32_t)(src) <<\ + 25) & 0xfe000000U) +#define MDM_TWOMEG_AGCTIME_ALT__FILT_SETTLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0xfe000000U))) +#define MDM_TWOMEG_AGCTIME_ALT__FILT_SETTLE__RESET_VALUE 0x00000010U +/** @} */ +#define MDM_TWOMEG_AGCTIME_ALT__TYPE uint32_t +#define MDM_TWOMEG_AGCTIME_ALT__READ 0xfe00003fU +#define MDM_TWOMEG_AGCTIME_ALT__WRITE 0xfe00003fU +#define MDM_TWOMEG_AGCTIME_ALT__PRESERVED 0x00000000U +#define MDM_TWOMEG_AGCTIME_ALT__RESET_VALUE 0x20000010U + +#endif /* __MDM_TWOMEG_AGCTIME_ALT_MACRO__ */ + +/** @} end of twomeg_agctime_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_agctime2 */ +/** + * @defgroup mdm_regs_core_agctime2 agctime2 + * @brief agc delays definitions. + * @{ + */ +#ifndef __MDM_AGCTIME2_MACRO__ +#define __MDM_AGCTIME2_MACRO__ + +/* macros for field rx_en_to_search */ +/** + * @defgroup mdm_regs_core_rx_en_to_search_field rx_en_to_search_field + * @brief macros for field rx_en_to_search + * @details number of 16 MHz clocks from rx_en assertion to agc start search. Need to keep in sync with rif registers for rxon and adcon. + * @{ + */ +#define MDM_AGCTIME2__RX_EN_TO_SEARCH__SHIFT 0 +#define MDM_AGCTIME2__RX_EN_TO_SEARCH__WIDTH 11 +#define MDM_AGCTIME2__RX_EN_TO_SEARCH__MASK 0x000007ffU +#define MDM_AGCTIME2__RX_EN_TO_SEARCH__READ(src) \ + ((uint32_t)(src)\ + & 0x000007ffU) +#define MDM_AGCTIME2__RX_EN_TO_SEARCH__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000007ffU) +#define MDM_AGCTIME2__RX_EN_TO_SEARCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007ffU) | ((uint32_t)(src) &\ + 0x000007ffU) +#define MDM_AGCTIME2__RX_EN_TO_SEARCH__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000007ffU))) +#define MDM_AGCTIME2__RX_EN_TO_SEARCH__RESET_VALUE 0x00000326U +/** @} */ + +/* macros for field lna_protect_settle */ +/** + * @defgroup mdm_regs_core_lna_protect_settle_field lna_protect_settle_field + * @brief macros for field lna_protect_settle + * @details When DC cal is bypassed, the number of 16 MHz clocks prior to transitioning to MEASURE to drop lna_protect + * @{ + */ +#define MDM_AGCTIME2__LNA_PROTECT_SETTLE__SHIFT 11 +#define MDM_AGCTIME2__LNA_PROTECT_SETTLE__WIDTH 8 +#define MDM_AGCTIME2__LNA_PROTECT_SETTLE__MASK 0x0007f800U +#define MDM_AGCTIME2__LNA_PROTECT_SETTLE__READ(src) \ + (((uint32_t)(src)\ + & 0x0007f800U) >> 11) +#define MDM_AGCTIME2__LNA_PROTECT_SETTLE__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x0007f800U) +#define MDM_AGCTIME2__LNA_PROTECT_SETTLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007f800U) | (((uint32_t)(src) <<\ + 11) & 0x0007f800U) +#define MDM_AGCTIME2__LNA_PROTECT_SETTLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x0007f800U))) +#define MDM_AGCTIME2__LNA_PROTECT_SETTLE__RESET_VALUE 0x00000020U +/** @} */ + +/* macros for field reset_filt_delay */ +/** + * @defgroup mdm_regs_core_reset_filt_delay_field reset_filt_delay_field + * @brief macros for field reset_filt_delay + * @details Number of 16 MHz clocks to hold agc filter in reset before releasing in the WAIT_GAIN_SETTLE state. MUST BE EVEN AND AT LEAST 4 AND LESS THAN OR EQUAL TO AGCTIME_GAIN_SETTLE. Register replicated for 2 Mb/s. + * @{ + */ +#define MDM_AGCTIME2__RESET_FILT_DELAY__SHIFT 19 +#define MDM_AGCTIME2__RESET_FILT_DELAY__WIDTH 6 +#define MDM_AGCTIME2__RESET_FILT_DELAY__MASK 0x01f80000U +#define MDM_AGCTIME2__RESET_FILT_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x01f80000U) >> 19) +#define MDM_AGCTIME2__RESET_FILT_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x01f80000U) +#define MDM_AGCTIME2__RESET_FILT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f80000U) | (((uint32_t)(src) <<\ + 19) & 0x01f80000U) +#define MDM_AGCTIME2__RESET_FILT_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x01f80000U))) +#define MDM_AGCTIME2__RESET_FILT_DELAY__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field twomeg_reset_filt_delay */ +/** + * @defgroup mdm_regs_core_twomeg_reset_filt_delay_field twomeg_reset_filt_delay_field + * @brief macros for field twomeg_reset_filt_delay + * @details Number of 16 MHz clocks to hold agc filter in reset before releasing in the WAIT_GAIN_SETTLE state. MUST BE AT LEAST 4 AND LESS THAN OR EQUAL TO TWOMEG_AGCTIME_GAIN_SETTLE. 2 Mb/s version of this register + * @{ + */ +#define MDM_AGCTIME2__TWOMEG_RESET_FILT_DELAY__SHIFT 25 +#define MDM_AGCTIME2__TWOMEG_RESET_FILT_DELAY__WIDTH 6 +#define MDM_AGCTIME2__TWOMEG_RESET_FILT_DELAY__MASK 0x7e000000U +#define MDM_AGCTIME2__TWOMEG_RESET_FILT_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x7e000000U) >> 25) +#define MDM_AGCTIME2__TWOMEG_RESET_FILT_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x7e000000U) +#define MDM_AGCTIME2__TWOMEG_RESET_FILT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7e000000U) | (((uint32_t)(src) <<\ + 25) & 0x7e000000U) +#define MDM_AGCTIME2__TWOMEG_RESET_FILT_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x7e000000U))) +#define MDM_AGCTIME2__TWOMEG_RESET_FILT_DELAY__RESET_VALUE 0x0000000aU +/** @} */ +#define MDM_AGCTIME2__TYPE uint32_t +#define MDM_AGCTIME2__READ 0x7fffffffU +#define MDM_AGCTIME2__WRITE 0x7fffffffU +#define MDM_AGCTIME2__PRESERVED 0x00000000U +#define MDM_AGCTIME2__RESET_VALUE 0x14810326U + +#endif /* __MDM_AGCTIME2_MACRO__ */ + +/** @} end of agctime2 */ + +/* macros for BlueprintGlobalNameSpace::MDM_agctime2_alt */ +/** + * @defgroup mdm_regs_core_agctime2_alt agctime2_alt + * @brief agc delays, alternate set definitions. + * @{ + */ +#ifndef __MDM_AGCTIME2_ALT_MACRO__ +#define __MDM_AGCTIME2_ALT_MACRO__ + +/* macros for field rx_en_to_search */ +/** + * @defgroup mdm_regs_core_rx_en_to_search_field rx_en_to_search_field + * @brief macros for field rx_en_to_search + * @details number of 16 MHz clocks from rx_en assertion to agc start search. Need to keep in sync with rif registers for rxon and adcon. + * @{ + */ +#define MDM_AGCTIME2_ALT__RX_EN_TO_SEARCH__SHIFT 0 +#define MDM_AGCTIME2_ALT__RX_EN_TO_SEARCH__WIDTH 11 +#define MDM_AGCTIME2_ALT__RX_EN_TO_SEARCH__MASK 0x000007ffU +#define MDM_AGCTIME2_ALT__RX_EN_TO_SEARCH__READ(src) \ + ((uint32_t)(src)\ + & 0x000007ffU) +#define MDM_AGCTIME2_ALT__RX_EN_TO_SEARCH__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000007ffU) +#define MDM_AGCTIME2_ALT__RX_EN_TO_SEARCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007ffU) | ((uint32_t)(src) &\ + 0x000007ffU) +#define MDM_AGCTIME2_ALT__RX_EN_TO_SEARCH__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000007ffU))) +#define MDM_AGCTIME2_ALT__RX_EN_TO_SEARCH__RESET_VALUE 0x00000326U +/** @} */ + +/* macros for field lna_protect_settle */ +/** + * @defgroup mdm_regs_core_lna_protect_settle_field lna_protect_settle_field + * @brief macros for field lna_protect_settle + * @details When DC cal is bypassed, the number of 16 MHz clocks prior to transitioning to MEASURE to drop lna_protect + * @{ + */ +#define MDM_AGCTIME2_ALT__LNA_PROTECT_SETTLE__SHIFT 11 +#define MDM_AGCTIME2_ALT__LNA_PROTECT_SETTLE__WIDTH 8 +#define MDM_AGCTIME2_ALT__LNA_PROTECT_SETTLE__MASK 0x0007f800U +#define MDM_AGCTIME2_ALT__LNA_PROTECT_SETTLE__READ(src) \ + (((uint32_t)(src)\ + & 0x0007f800U) >> 11) +#define MDM_AGCTIME2_ALT__LNA_PROTECT_SETTLE__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x0007f800U) +#define MDM_AGCTIME2_ALT__LNA_PROTECT_SETTLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007f800U) | (((uint32_t)(src) <<\ + 11) & 0x0007f800U) +#define MDM_AGCTIME2_ALT__LNA_PROTECT_SETTLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x0007f800U))) +#define MDM_AGCTIME2_ALT__LNA_PROTECT_SETTLE__RESET_VALUE 0x00000020U +/** @} */ + +/* macros for field reset_filt_delay */ +/** + * @defgroup mdm_regs_core_reset_filt_delay_field reset_filt_delay_field + * @brief macros for field reset_filt_delay + * @details Number of 16 MHz clocks to hold agc filter in reset before releasing in the WAIT_GAIN_SETTLE state. MUST BE EVEN AND AT LEAST 4 AND LESS THAN OR EQUAL TO AGCTIME_GAIN_SETTLE. Register replicated for 2 Mb/s. + * @{ + */ +#define MDM_AGCTIME2_ALT__RESET_FILT_DELAY__SHIFT 19 +#define MDM_AGCTIME2_ALT__RESET_FILT_DELAY__WIDTH 6 +#define MDM_AGCTIME2_ALT__RESET_FILT_DELAY__MASK 0x01f80000U +#define MDM_AGCTIME2_ALT__RESET_FILT_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x01f80000U) >> 19) +#define MDM_AGCTIME2_ALT__RESET_FILT_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x01f80000U) +#define MDM_AGCTIME2_ALT__RESET_FILT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f80000U) | (((uint32_t)(src) <<\ + 19) & 0x01f80000U) +#define MDM_AGCTIME2_ALT__RESET_FILT_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x01f80000U))) +#define MDM_AGCTIME2_ALT__RESET_FILT_DELAY__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field twomeg_reset_filt_delay */ +/** + * @defgroup mdm_regs_core_twomeg_reset_filt_delay_field twomeg_reset_filt_delay_field + * @brief macros for field twomeg_reset_filt_delay + * @details Number of 16 MHz clocks to hold agc filter in reset before releasing in the WAIT_GAIN_SETTLE state. MUST BE AT LEAST 4 AND LESS THAN OR EQUAL TO TWOMEG_AGCTIME_GAIN_SETTLE. 2 Mb/s version of this register + * @{ + */ +#define MDM_AGCTIME2_ALT__TWOMEG_RESET_FILT_DELAY__SHIFT 25 +#define MDM_AGCTIME2_ALT__TWOMEG_RESET_FILT_DELAY__WIDTH 6 +#define MDM_AGCTIME2_ALT__TWOMEG_RESET_FILT_DELAY__MASK 0x7e000000U +#define MDM_AGCTIME2_ALT__TWOMEG_RESET_FILT_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x7e000000U) >> 25) +#define MDM_AGCTIME2_ALT__TWOMEG_RESET_FILT_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x7e000000U) +#define MDM_AGCTIME2_ALT__TWOMEG_RESET_FILT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7e000000U) | (((uint32_t)(src) <<\ + 25) & 0x7e000000U) +#define MDM_AGCTIME2_ALT__TWOMEG_RESET_FILT_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x7e000000U))) +#define MDM_AGCTIME2_ALT__TWOMEG_RESET_FILT_DELAY__RESET_VALUE 0x0000000aU +/** @} */ +#define MDM_AGCTIME2_ALT__TYPE uint32_t +#define MDM_AGCTIME2_ALT__READ 0x7fffffffU +#define MDM_AGCTIME2_ALT__WRITE 0x7fffffffU +#define MDM_AGCTIME2_ALT__PRESERVED 0x00000000U +#define MDM_AGCTIME2_ALT__RESET_VALUE 0x14810326U + +#endif /* __MDM_AGCTIME2_ALT_MACRO__ */ + +/** @} end of agctime2_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_agccntl */ +/** + * @defgroup mdm_regs_core_agccntl agccntl + * @brief agc control definitions. + * @{ + */ +#ifndef __MDM_AGCCNTL_MACRO__ +#define __MDM_AGCCNTL_MACRO__ + +/* macros for field enable_rfin_peakdet */ +/** + * @defgroup mdm_regs_core_enable_rfin_peakdet_field enable_rfin_peakdet_field + * @brief macros for field enable_rfin_peakdet + * @details RX state machine will observe lna_peakdet + * @{ + */ +#define MDM_AGCCNTL__ENABLE_RFIN_PEAKDET__SHIFT 0 +#define MDM_AGCCNTL__ENABLE_RFIN_PEAKDET__WIDTH 1 +#define MDM_AGCCNTL__ENABLE_RFIN_PEAKDET__MASK 0x00000001U +#define MDM_AGCCNTL__ENABLE_RFIN_PEAKDET__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define MDM_AGCCNTL__ENABLE_RFIN_PEAKDET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define MDM_AGCCNTL__ENABLE_RFIN_PEAKDET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define MDM_AGCCNTL__ENABLE_RFIN_PEAKDET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define MDM_AGCCNTL__ENABLE_RFIN_PEAKDET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_AGCCNTL__ENABLE_RFIN_PEAKDET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_AGCCNTL__ENABLE_RFIN_PEAKDET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field enable_tia_peakdet */ +/** + * @defgroup mdm_regs_core_enable_tia_peakdet_field enable_tia_peakdet_field + * @brief macros for field enable_tia_peakdet + * @details RX state machine will observe tia_peakdet + * @{ + */ +#define MDM_AGCCNTL__ENABLE_TIA_PEAKDET__SHIFT 1 +#define MDM_AGCCNTL__ENABLE_TIA_PEAKDET__WIDTH 1 +#define MDM_AGCCNTL__ENABLE_TIA_PEAKDET__MASK 0x00000002U +#define MDM_AGCCNTL__ENABLE_TIA_PEAKDET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define MDM_AGCCNTL__ENABLE_TIA_PEAKDET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define MDM_AGCCNTL__ENABLE_TIA_PEAKDET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define MDM_AGCCNTL__ENABLE_TIA_PEAKDET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define MDM_AGCCNTL__ENABLE_TIA_PEAKDET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define MDM_AGCCNTL__ENABLE_TIA_PEAKDET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define MDM_AGCCNTL__ENABLE_TIA_PEAKDET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field max */ +/** + * @defgroup mdm_regs_core_max_field max_field + * @brief macros for field max + * @details Max RX gain + * @{ + */ +#define MDM_AGCCNTL__MAX__SHIFT 2 +#define MDM_AGCCNTL__MAX__WIDTH 7 +#define MDM_AGCCNTL__MAX__MASK 0x000001fcU +#define MDM_AGCCNTL__MAX__READ(src) (((uint32_t)(src) & 0x000001fcU) >> 2) +#define MDM_AGCCNTL__MAX__WRITE(src) (((uint32_t)(src) << 2) & 0x000001fcU) +#define MDM_AGCCNTL__MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001fcU) | (((uint32_t)(src) <<\ + 2) & 0x000001fcU) +#define MDM_AGCCNTL__MAX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x000001fcU))) +#define MDM_AGCCNTL__MAX__RESET_VALUE 0x0000004cU +/** @} */ + +/* macros for field force_rxgain */ +/** + * @defgroup mdm_regs_core_force_rxgain_field force_rxgain_field + * @brief macros for field force_rxgain + * @details If set, force rxgain + * @{ + */ +#define MDM_AGCCNTL__FORCE_RXGAIN__SHIFT 9 +#define MDM_AGCCNTL__FORCE_RXGAIN__WIDTH 1 +#define MDM_AGCCNTL__FORCE_RXGAIN__MASK 0x00000200U +#define MDM_AGCCNTL__FORCE_RXGAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define MDM_AGCCNTL__FORCE_RXGAIN__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define MDM_AGCCNTL__FORCE_RXGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define MDM_AGCCNTL__FORCE_RXGAIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define MDM_AGCCNTL__FORCE_RXGAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define MDM_AGCCNTL__FORCE_RXGAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define MDM_AGCCNTL__FORCE_RXGAIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field forced_rxgain_value */ +/** + * @defgroup mdm_regs_core_forced_rxgain_value_field forced_rxgain_value_field + * @brief macros for field forced_rxgain_value + * @details When rxgain forced, use this value + * @{ + */ +#define MDM_AGCCNTL__FORCED_RXGAIN_VALUE__SHIFT 10 +#define MDM_AGCCNTL__FORCED_RXGAIN_VALUE__WIDTH 7 +#define MDM_AGCCNTL__FORCED_RXGAIN_VALUE__MASK 0x0001fc00U +#define MDM_AGCCNTL__FORCED_RXGAIN_VALUE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fc00U) >> 10) +#define MDM_AGCCNTL__FORCED_RXGAIN_VALUE__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x0001fc00U) +#define MDM_AGCCNTL__FORCED_RXGAIN_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fc00U) | (((uint32_t)(src) <<\ + 10) & 0x0001fc00U) +#define MDM_AGCCNTL__FORCED_RXGAIN_VALUE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x0001fc00U))) +#define MDM_AGCCNTL__FORCED_RXGAIN_VALUE__RESET_VALUE 0x00000005U +/** @} */ + +/* macros for field allow_sat_after_peak */ +/** + * @defgroup mdm_regs_core_allow_sat_after_peak_field allow_sat_after_peak_field + * @brief macros for field allow_sat_after_peak + * @details After a peak detect, allow a saturation detect prior to the automatic fine gain change + * @{ + */ +#define MDM_AGCCNTL__ALLOW_SAT_AFTER_PEAK__SHIFT 17 +#define MDM_AGCCNTL__ALLOW_SAT_AFTER_PEAK__WIDTH 1 +#define MDM_AGCCNTL__ALLOW_SAT_AFTER_PEAK__MASK 0x00020000U +#define MDM_AGCCNTL__ALLOW_SAT_AFTER_PEAK__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define MDM_AGCCNTL__ALLOW_SAT_AFTER_PEAK__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define MDM_AGCCNTL__ALLOW_SAT_AFTER_PEAK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define MDM_AGCCNTL__ALLOW_SAT_AFTER_PEAK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define MDM_AGCCNTL__ALLOW_SAT_AFTER_PEAK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define MDM_AGCCNTL__ALLOW_SAT_AFTER_PEAK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define MDM_AGCCNTL__ALLOW_SAT_AFTER_PEAK__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field allow_sat_after_sat */ +/** + * @defgroup mdm_regs_core_allow_sat_after_sat_field allow_sat_after_sat_field + * @brief macros for field allow_sat_after_sat + * @details After a saturation detect, allow another saturation detect prior to the automatic fine gain change + * @{ + */ +#define MDM_AGCCNTL__ALLOW_SAT_AFTER_SAT__SHIFT 18 +#define MDM_AGCCNTL__ALLOW_SAT_AFTER_SAT__WIDTH 1 +#define MDM_AGCCNTL__ALLOW_SAT_AFTER_SAT__MASK 0x00040000U +#define MDM_AGCCNTL__ALLOW_SAT_AFTER_SAT__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define MDM_AGCCNTL__ALLOW_SAT_AFTER_SAT__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define MDM_AGCCNTL__ALLOW_SAT_AFTER_SAT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define MDM_AGCCNTL__ALLOW_SAT_AFTER_SAT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define MDM_AGCCNTL__ALLOW_SAT_AFTER_SAT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define MDM_AGCCNTL__ALLOW_SAT_AFTER_SAT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define MDM_AGCCNTL__ALLOW_SAT_AFTER_SAT__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field bypass_rxfir */ +/** + * @defgroup mdm_regs_core_bypass_rxfir_field bypass_rxfir_field + * @brief macros for field bypass_rxfir + * @details When set, RXFIR output = RXFIR input. Register replicated for 2 Mb/s + * @{ + */ +#define MDM_AGCCNTL__BYPASS_RXFIR__SHIFT 19 +#define MDM_AGCCNTL__BYPASS_RXFIR__WIDTH 1 +#define MDM_AGCCNTL__BYPASS_RXFIR__MASK 0x00080000U +#define MDM_AGCCNTL__BYPASS_RXFIR__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define MDM_AGCCNTL__BYPASS_RXFIR__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define MDM_AGCCNTL__BYPASS_RXFIR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define MDM_AGCCNTL__BYPASS_RXFIR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define MDM_AGCCNTL__BYPASS_RXFIR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define MDM_AGCCNTL__BYPASS_RXFIR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define MDM_AGCCNTL__BYPASS_RXFIR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field twomeg_bypass_rxfir */ +/** + * @defgroup mdm_regs_core_twomeg_bypass_rxfir_field twomeg_bypass_rxfir_field + * @brief macros for field twomeg_bypass_rxfir + * @details When set, RXFIR output = RXFIR input 2 Mb/s version of register + * @{ + */ +#define MDM_AGCCNTL__TWOMEG_BYPASS_RXFIR__SHIFT 20 +#define MDM_AGCCNTL__TWOMEG_BYPASS_RXFIR__WIDTH 1 +#define MDM_AGCCNTL__TWOMEG_BYPASS_RXFIR__MASK 0x00100000U +#define MDM_AGCCNTL__TWOMEG_BYPASS_RXFIR__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define MDM_AGCCNTL__TWOMEG_BYPASS_RXFIR__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define MDM_AGCCNTL__TWOMEG_BYPASS_RXFIR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define MDM_AGCCNTL__TWOMEG_BYPASS_RXFIR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define MDM_AGCCNTL__TWOMEG_BYPASS_RXFIR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define MDM_AGCCNTL__TWOMEG_BYPASS_RXFIR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define MDM_AGCCNTL__TWOMEG_BYPASS_RXFIR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field min_rxgain_increase */ +/** + * @defgroup mdm_regs_core_min_rxgain_increase_field min_rxgain_increase_field + * @brief macros for field min_rxgain_increase + * @details Minimum amount of rxgain increase + * @{ + */ +#define MDM_AGCCNTL__MIN_RXGAIN_INCREASE__SHIFT 21 +#define MDM_AGCCNTL__MIN_RXGAIN_INCREASE__WIDTH 4 +#define MDM_AGCCNTL__MIN_RXGAIN_INCREASE__MASK 0x01e00000U +#define MDM_AGCCNTL__MIN_RXGAIN_INCREASE__READ(src) \ + (((uint32_t)(src)\ + & 0x01e00000U) >> 21) +#define MDM_AGCCNTL__MIN_RXGAIN_INCREASE__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x01e00000U) +#define MDM_AGCCNTL__MIN_RXGAIN_INCREASE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01e00000U) | (((uint32_t)(src) <<\ + 21) & 0x01e00000U) +#define MDM_AGCCNTL__MIN_RXGAIN_INCREASE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x01e00000U))) +#define MDM_AGCCNTL__MIN_RXGAIN_INCREASE__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field min_rxgain_decrease */ +/** + * @defgroup mdm_regs_core_min_rxgain_decrease_field min_rxgain_decrease_field + * @brief macros for field min_rxgain_decrease + * @details Minimum amount of rxgain decrease + * @{ + */ +#define MDM_AGCCNTL__MIN_RXGAIN_DECREASE__SHIFT 25 +#define MDM_AGCCNTL__MIN_RXGAIN_DECREASE__WIDTH 4 +#define MDM_AGCCNTL__MIN_RXGAIN_DECREASE__MASK 0x1e000000U +#define MDM_AGCCNTL__MIN_RXGAIN_DECREASE__READ(src) \ + (((uint32_t)(src)\ + & 0x1e000000U) >> 25) +#define MDM_AGCCNTL__MIN_RXGAIN_DECREASE__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x1e000000U) +#define MDM_AGCCNTL__MIN_RXGAIN_DECREASE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1e000000U) | (((uint32_t)(src) <<\ + 25) & 0x1e000000U) +#define MDM_AGCCNTL__MIN_RXGAIN_DECREASE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x1e000000U))) +#define MDM_AGCCNTL__MIN_RXGAIN_DECREASE__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field enable_iqcorr */ +/** + * @defgroup mdm_regs_core_enable_iqcorr_field enable_iqcorr_field + * @brief macros for field enable_iqcorr + * @details Enable for 1 Mb/s or coded + * @{ + */ +#define MDM_AGCCNTL__ENABLE_IQCORR__SHIFT 29 +#define MDM_AGCCNTL__ENABLE_IQCORR__WIDTH 1 +#define MDM_AGCCNTL__ENABLE_IQCORR__MASK 0x20000000U +#define MDM_AGCCNTL__ENABLE_IQCORR__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define MDM_AGCCNTL__ENABLE_IQCORR__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define MDM_AGCCNTL__ENABLE_IQCORR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define MDM_AGCCNTL__ENABLE_IQCORR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define MDM_AGCCNTL__ENABLE_IQCORR__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define MDM_AGCCNTL__ENABLE_IQCORR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define MDM_AGCCNTL__ENABLE_IQCORR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field twomeg_enable_iqcorr */ +/** + * @defgroup mdm_regs_core_twomeg_enable_iqcorr_field twomeg_enable_iqcorr_field + * @brief macros for field twomeg_enable_iqcorr + * @details Enable for 2 Mb/s + * @{ + */ +#define MDM_AGCCNTL__TWOMEG_ENABLE_IQCORR__SHIFT 30 +#define MDM_AGCCNTL__TWOMEG_ENABLE_IQCORR__WIDTH 1 +#define MDM_AGCCNTL__TWOMEG_ENABLE_IQCORR__MASK 0x40000000U +#define MDM_AGCCNTL__TWOMEG_ENABLE_IQCORR__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define MDM_AGCCNTL__TWOMEG_ENABLE_IQCORR__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define MDM_AGCCNTL__TWOMEG_ENABLE_IQCORR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define MDM_AGCCNTL__TWOMEG_ENABLE_IQCORR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define MDM_AGCCNTL__TWOMEG_ENABLE_IQCORR__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define MDM_AGCCNTL__TWOMEG_ENABLE_IQCORR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define MDM_AGCCNTL__TWOMEG_ENABLE_IQCORR__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_AGCCNTL__TYPE uint32_t +#define MDM_AGCCNTL__READ 0x7fffffffU +#define MDM_AGCCNTL__WRITE 0x7fffffffU +#define MDM_AGCCNTL__PRESERVED 0x00000000U +#define MDM_AGCCNTL__RESET_VALUE 0x0c661533U + +#endif /* __MDM_AGCCNTL_MACRO__ */ + +/** @} end of agccntl */ + +/* macros for BlueprintGlobalNameSpace::MDM_agccntl_alt */ +/** + * @defgroup mdm_regs_core_agccntl_alt agccntl_alt + * @brief agc control, alternate set definitions. + * @{ + */ +#ifndef __MDM_AGCCNTL_ALT_MACRO__ +#define __MDM_AGCCNTL_ALT_MACRO__ + +/* macros for field enable_rfin_peakdet */ +/** + * @defgroup mdm_regs_core_enable_rfin_peakdet_field enable_rfin_peakdet_field + * @brief macros for field enable_rfin_peakdet + * @details RX state machine will observe lna_peakdet + * @{ + */ +#define MDM_AGCCNTL_ALT__ENABLE_RFIN_PEAKDET__SHIFT 0 +#define MDM_AGCCNTL_ALT__ENABLE_RFIN_PEAKDET__WIDTH 1 +#define MDM_AGCCNTL_ALT__ENABLE_RFIN_PEAKDET__MASK 0x00000001U +#define MDM_AGCCNTL_ALT__ENABLE_RFIN_PEAKDET__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define MDM_AGCCNTL_ALT__ENABLE_RFIN_PEAKDET__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define MDM_AGCCNTL_ALT__ENABLE_RFIN_PEAKDET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define MDM_AGCCNTL_ALT__ENABLE_RFIN_PEAKDET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define MDM_AGCCNTL_ALT__ENABLE_RFIN_PEAKDET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_AGCCNTL_ALT__ENABLE_RFIN_PEAKDET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_AGCCNTL_ALT__ENABLE_RFIN_PEAKDET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field enable_tia_peakdet */ +/** + * @defgroup mdm_regs_core_enable_tia_peakdet_field enable_tia_peakdet_field + * @brief macros for field enable_tia_peakdet + * @details RX state machine will observe tia_peakdet + * @{ + */ +#define MDM_AGCCNTL_ALT__ENABLE_TIA_PEAKDET__SHIFT 1 +#define MDM_AGCCNTL_ALT__ENABLE_TIA_PEAKDET__WIDTH 1 +#define MDM_AGCCNTL_ALT__ENABLE_TIA_PEAKDET__MASK 0x00000002U +#define MDM_AGCCNTL_ALT__ENABLE_TIA_PEAKDET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define MDM_AGCCNTL_ALT__ENABLE_TIA_PEAKDET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define MDM_AGCCNTL_ALT__ENABLE_TIA_PEAKDET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define MDM_AGCCNTL_ALT__ENABLE_TIA_PEAKDET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define MDM_AGCCNTL_ALT__ENABLE_TIA_PEAKDET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define MDM_AGCCNTL_ALT__ENABLE_TIA_PEAKDET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define MDM_AGCCNTL_ALT__ENABLE_TIA_PEAKDET__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field max */ +/** + * @defgroup mdm_regs_core_max_field max_field + * @brief macros for field max + * @details Max RX gain + * @{ + */ +#define MDM_AGCCNTL_ALT__MAX__SHIFT 2 +#define MDM_AGCCNTL_ALT__MAX__WIDTH 7 +#define MDM_AGCCNTL_ALT__MAX__MASK 0x000001fcU +#define MDM_AGCCNTL_ALT__MAX__READ(src) (((uint32_t)(src) & 0x000001fcU) >> 2) +#define MDM_AGCCNTL_ALT__MAX__WRITE(src) (((uint32_t)(src) << 2) & 0x000001fcU) +#define MDM_AGCCNTL_ALT__MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001fcU) | (((uint32_t)(src) <<\ + 2) & 0x000001fcU) +#define MDM_AGCCNTL_ALT__MAX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x000001fcU))) +#define MDM_AGCCNTL_ALT__MAX__RESET_VALUE 0x0000004cU +/** @} */ + +/* macros for field force_rxgain */ +/** + * @defgroup mdm_regs_core_force_rxgain_field force_rxgain_field + * @brief macros for field force_rxgain + * @details If set, force rxgain + * @{ + */ +#define MDM_AGCCNTL_ALT__FORCE_RXGAIN__SHIFT 9 +#define MDM_AGCCNTL_ALT__FORCE_RXGAIN__WIDTH 1 +#define MDM_AGCCNTL_ALT__FORCE_RXGAIN__MASK 0x00000200U +#define MDM_AGCCNTL_ALT__FORCE_RXGAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define MDM_AGCCNTL_ALT__FORCE_RXGAIN__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define MDM_AGCCNTL_ALT__FORCE_RXGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define MDM_AGCCNTL_ALT__FORCE_RXGAIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define MDM_AGCCNTL_ALT__FORCE_RXGAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define MDM_AGCCNTL_ALT__FORCE_RXGAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define MDM_AGCCNTL_ALT__FORCE_RXGAIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field forced_rxgain_value */ +/** + * @defgroup mdm_regs_core_forced_rxgain_value_field forced_rxgain_value_field + * @brief macros for field forced_rxgain_value + * @details When rxgain forced, use this value + * @{ + */ +#define MDM_AGCCNTL_ALT__FORCED_RXGAIN_VALUE__SHIFT 10 +#define MDM_AGCCNTL_ALT__FORCED_RXGAIN_VALUE__WIDTH 7 +#define MDM_AGCCNTL_ALT__FORCED_RXGAIN_VALUE__MASK 0x0001fc00U +#define MDM_AGCCNTL_ALT__FORCED_RXGAIN_VALUE__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fc00U) >> 10) +#define MDM_AGCCNTL_ALT__FORCED_RXGAIN_VALUE__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x0001fc00U) +#define MDM_AGCCNTL_ALT__FORCED_RXGAIN_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fc00U) | (((uint32_t)(src) <<\ + 10) & 0x0001fc00U) +#define MDM_AGCCNTL_ALT__FORCED_RXGAIN_VALUE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x0001fc00U))) +#define MDM_AGCCNTL_ALT__FORCED_RXGAIN_VALUE__RESET_VALUE 0x00000005U +/** @} */ + +/* macros for field allow_sat_after_peak */ +/** + * @defgroup mdm_regs_core_allow_sat_after_peak_field allow_sat_after_peak_field + * @brief macros for field allow_sat_after_peak + * @details After a peak detect, allow a saturation detect prior to the automatic fine gain change + * @{ + */ +#define MDM_AGCCNTL_ALT__ALLOW_SAT_AFTER_PEAK__SHIFT 17 +#define MDM_AGCCNTL_ALT__ALLOW_SAT_AFTER_PEAK__WIDTH 1 +#define MDM_AGCCNTL_ALT__ALLOW_SAT_AFTER_PEAK__MASK 0x00020000U +#define MDM_AGCCNTL_ALT__ALLOW_SAT_AFTER_PEAK__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define MDM_AGCCNTL_ALT__ALLOW_SAT_AFTER_PEAK__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define MDM_AGCCNTL_ALT__ALLOW_SAT_AFTER_PEAK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define MDM_AGCCNTL_ALT__ALLOW_SAT_AFTER_PEAK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define MDM_AGCCNTL_ALT__ALLOW_SAT_AFTER_PEAK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define MDM_AGCCNTL_ALT__ALLOW_SAT_AFTER_PEAK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define MDM_AGCCNTL_ALT__ALLOW_SAT_AFTER_PEAK__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field allow_sat_after_sat */ +/** + * @defgroup mdm_regs_core_allow_sat_after_sat_field allow_sat_after_sat_field + * @brief macros for field allow_sat_after_sat + * @details After a saturation detect, allow another saturation detect prior to the automatic fine gain change + * @{ + */ +#define MDM_AGCCNTL_ALT__ALLOW_SAT_AFTER_SAT__SHIFT 18 +#define MDM_AGCCNTL_ALT__ALLOW_SAT_AFTER_SAT__WIDTH 1 +#define MDM_AGCCNTL_ALT__ALLOW_SAT_AFTER_SAT__MASK 0x00040000U +#define MDM_AGCCNTL_ALT__ALLOW_SAT_AFTER_SAT__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define MDM_AGCCNTL_ALT__ALLOW_SAT_AFTER_SAT__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define MDM_AGCCNTL_ALT__ALLOW_SAT_AFTER_SAT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define MDM_AGCCNTL_ALT__ALLOW_SAT_AFTER_SAT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define MDM_AGCCNTL_ALT__ALLOW_SAT_AFTER_SAT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define MDM_AGCCNTL_ALT__ALLOW_SAT_AFTER_SAT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define MDM_AGCCNTL_ALT__ALLOW_SAT_AFTER_SAT__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field bypass_rxfir */ +/** + * @defgroup mdm_regs_core_bypass_rxfir_field bypass_rxfir_field + * @brief macros for field bypass_rxfir + * @details When set, RXFIR output = RXFIR input. Register replicated for 2 Mb/s + * @{ + */ +#define MDM_AGCCNTL_ALT__BYPASS_RXFIR__SHIFT 19 +#define MDM_AGCCNTL_ALT__BYPASS_RXFIR__WIDTH 1 +#define MDM_AGCCNTL_ALT__BYPASS_RXFIR__MASK 0x00080000U +#define MDM_AGCCNTL_ALT__BYPASS_RXFIR__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define MDM_AGCCNTL_ALT__BYPASS_RXFIR__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define MDM_AGCCNTL_ALT__BYPASS_RXFIR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define MDM_AGCCNTL_ALT__BYPASS_RXFIR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define MDM_AGCCNTL_ALT__BYPASS_RXFIR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define MDM_AGCCNTL_ALT__BYPASS_RXFIR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define MDM_AGCCNTL_ALT__BYPASS_RXFIR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field twomeg_bypass_rxfir */ +/** + * @defgroup mdm_regs_core_twomeg_bypass_rxfir_field twomeg_bypass_rxfir_field + * @brief macros for field twomeg_bypass_rxfir + * @details When set, RXFIR output = RXFIR input 2 Mb/s version of register + * @{ + */ +#define MDM_AGCCNTL_ALT__TWOMEG_BYPASS_RXFIR__SHIFT 20 +#define MDM_AGCCNTL_ALT__TWOMEG_BYPASS_RXFIR__WIDTH 1 +#define MDM_AGCCNTL_ALT__TWOMEG_BYPASS_RXFIR__MASK 0x00100000U +#define MDM_AGCCNTL_ALT__TWOMEG_BYPASS_RXFIR__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define MDM_AGCCNTL_ALT__TWOMEG_BYPASS_RXFIR__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define MDM_AGCCNTL_ALT__TWOMEG_BYPASS_RXFIR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define MDM_AGCCNTL_ALT__TWOMEG_BYPASS_RXFIR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define MDM_AGCCNTL_ALT__TWOMEG_BYPASS_RXFIR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define MDM_AGCCNTL_ALT__TWOMEG_BYPASS_RXFIR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define MDM_AGCCNTL_ALT__TWOMEG_BYPASS_RXFIR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field min_rxgain_increase */ +/** + * @defgroup mdm_regs_core_min_rxgain_increase_field min_rxgain_increase_field + * @brief macros for field min_rxgain_increase + * @details Minimum amount of rxgain increase + * @{ + */ +#define MDM_AGCCNTL_ALT__MIN_RXGAIN_INCREASE__SHIFT 21 +#define MDM_AGCCNTL_ALT__MIN_RXGAIN_INCREASE__WIDTH 4 +#define MDM_AGCCNTL_ALT__MIN_RXGAIN_INCREASE__MASK 0x01e00000U +#define MDM_AGCCNTL_ALT__MIN_RXGAIN_INCREASE__READ(src) \ + (((uint32_t)(src)\ + & 0x01e00000U) >> 21) +#define MDM_AGCCNTL_ALT__MIN_RXGAIN_INCREASE__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x01e00000U) +#define MDM_AGCCNTL_ALT__MIN_RXGAIN_INCREASE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01e00000U) | (((uint32_t)(src) <<\ + 21) & 0x01e00000U) +#define MDM_AGCCNTL_ALT__MIN_RXGAIN_INCREASE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x01e00000U))) +#define MDM_AGCCNTL_ALT__MIN_RXGAIN_INCREASE__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field min_rxgain_decrease */ +/** + * @defgroup mdm_regs_core_min_rxgain_decrease_field min_rxgain_decrease_field + * @brief macros for field min_rxgain_decrease + * @details Minimum amount of rxgain decrease + * @{ + */ +#define MDM_AGCCNTL_ALT__MIN_RXGAIN_DECREASE__SHIFT 25 +#define MDM_AGCCNTL_ALT__MIN_RXGAIN_DECREASE__WIDTH 4 +#define MDM_AGCCNTL_ALT__MIN_RXGAIN_DECREASE__MASK 0x1e000000U +#define MDM_AGCCNTL_ALT__MIN_RXGAIN_DECREASE__READ(src) \ + (((uint32_t)(src)\ + & 0x1e000000U) >> 25) +#define MDM_AGCCNTL_ALT__MIN_RXGAIN_DECREASE__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x1e000000U) +#define MDM_AGCCNTL_ALT__MIN_RXGAIN_DECREASE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1e000000U) | (((uint32_t)(src) <<\ + 25) & 0x1e000000U) +#define MDM_AGCCNTL_ALT__MIN_RXGAIN_DECREASE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x1e000000U))) +#define MDM_AGCCNTL_ALT__MIN_RXGAIN_DECREASE__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field enable_iqcorr */ +/** + * @defgroup mdm_regs_core_enable_iqcorr_field enable_iqcorr_field + * @brief macros for field enable_iqcorr + * @details Enable for 1 Mb/s or coded + * @{ + */ +#define MDM_AGCCNTL_ALT__ENABLE_IQCORR__SHIFT 29 +#define MDM_AGCCNTL_ALT__ENABLE_IQCORR__WIDTH 1 +#define MDM_AGCCNTL_ALT__ENABLE_IQCORR__MASK 0x20000000U +#define MDM_AGCCNTL_ALT__ENABLE_IQCORR__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define MDM_AGCCNTL_ALT__ENABLE_IQCORR__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define MDM_AGCCNTL_ALT__ENABLE_IQCORR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define MDM_AGCCNTL_ALT__ENABLE_IQCORR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define MDM_AGCCNTL_ALT__ENABLE_IQCORR__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define MDM_AGCCNTL_ALT__ENABLE_IQCORR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define MDM_AGCCNTL_ALT__ENABLE_IQCORR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field twomeg_enable_iqcorr */ +/** + * @defgroup mdm_regs_core_twomeg_enable_iqcorr_field twomeg_enable_iqcorr_field + * @brief macros for field twomeg_enable_iqcorr + * @details Enable for 2 Mb/s + * @{ + */ +#define MDM_AGCCNTL_ALT__TWOMEG_ENABLE_IQCORR__SHIFT 30 +#define MDM_AGCCNTL_ALT__TWOMEG_ENABLE_IQCORR__WIDTH 1 +#define MDM_AGCCNTL_ALT__TWOMEG_ENABLE_IQCORR__MASK 0x40000000U +#define MDM_AGCCNTL_ALT__TWOMEG_ENABLE_IQCORR__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define MDM_AGCCNTL_ALT__TWOMEG_ENABLE_IQCORR__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define MDM_AGCCNTL_ALT__TWOMEG_ENABLE_IQCORR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define MDM_AGCCNTL_ALT__TWOMEG_ENABLE_IQCORR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define MDM_AGCCNTL_ALT__TWOMEG_ENABLE_IQCORR__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define MDM_AGCCNTL_ALT__TWOMEG_ENABLE_IQCORR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define MDM_AGCCNTL_ALT__TWOMEG_ENABLE_IQCORR__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_AGCCNTL_ALT__TYPE uint32_t +#define MDM_AGCCNTL_ALT__READ 0x7fffffffU +#define MDM_AGCCNTL_ALT__WRITE 0x7fffffffU +#define MDM_AGCCNTL_ALT__PRESERVED 0x00000000U +#define MDM_AGCCNTL_ALT__RESET_VALUE 0x0c661533U + +#endif /* __MDM_AGCCNTL_ALT_MACRO__ */ + +/** @} end of agccntl_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_agcpd */ +/** + * @defgroup mdm_regs_core_agcpd agcpd + * @brief agc peak detect control definitions. + * @{ + */ +#ifndef __MDM_AGCPD_MACRO__ +#define __MDM_AGCPD_MACRO__ + +/* macros for field check_win */ +/** + * @defgroup mdm_regs_core_check_win_field check_win_field + * @brief macros for field check_win + * @details Number of samples to measure for peak detection + * @{ + */ +#define MDM_AGCPD__CHECK_WIN__SHIFT 0 +#define MDM_AGCPD__CHECK_WIN__WIDTH 4 +#define MDM_AGCPD__CHECK_WIN__MASK 0x0000000fU +#define MDM_AGCPD__CHECK_WIN__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define MDM_AGCPD__CHECK_WIN__WRITE(src) ((uint32_t)(src) & 0x0000000fU) +#define MDM_AGCPD__CHECK_WIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define MDM_AGCPD__CHECK_WIN__VERIFY(src) (!(((uint32_t)(src) & ~0x0000000fU))) +#define MDM_AGCPD__CHECK_WIN__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field rfin_peak_thr_high */ +/** + * @defgroup mdm_regs_core_rfin_peak_thr_high_field rfin_peak_thr_high_field + * @brief macros for field rfin_peak_thr_high + * @details Threshold for LNA peak detector when peak not currently detected + * @{ + */ +#define MDM_AGCPD__RFIN_PEAK_THR_HIGH__SHIFT 4 +#define MDM_AGCPD__RFIN_PEAK_THR_HIGH__WIDTH 4 +#define MDM_AGCPD__RFIN_PEAK_THR_HIGH__MASK 0x000000f0U +#define MDM_AGCPD__RFIN_PEAK_THR_HIGH__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define MDM_AGCPD__RFIN_PEAK_THR_HIGH__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x000000f0U) +#define MDM_AGCPD__RFIN_PEAK_THR_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define MDM_AGCPD__RFIN_PEAK_THR_HIGH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define MDM_AGCPD__RFIN_PEAK_THR_HIGH__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field rfin_peak_thr_low */ +/** + * @defgroup mdm_regs_core_rfin_peak_thr_low_field rfin_peak_thr_low_field + * @brief macros for field rfin_peak_thr_low + * @details Threshold for LNA peak detector when peak currently detected + * @{ + */ +#define MDM_AGCPD__RFIN_PEAK_THR_LOW__SHIFT 8 +#define MDM_AGCPD__RFIN_PEAK_THR_LOW__WIDTH 4 +#define MDM_AGCPD__RFIN_PEAK_THR_LOW__MASK 0x00000f00U +#define MDM_AGCPD__RFIN_PEAK_THR_LOW__READ(src) \ + (((uint32_t)(src)\ + & 0x00000f00U) >> 8) +#define MDM_AGCPD__RFIN_PEAK_THR_LOW__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000f00U) +#define MDM_AGCPD__RFIN_PEAK_THR_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((uint32_t)(src) <<\ + 8) & 0x00000f00U) +#define MDM_AGCPD__RFIN_PEAK_THR_LOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000f00U))) +#define MDM_AGCPD__RFIN_PEAK_THR_LOW__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field tia_peak_thr_high */ +/** + * @defgroup mdm_regs_core_tia_peak_thr_high_field tia_peak_thr_high_field + * @brief macros for field tia_peak_thr_high + * @details Threshold for TIA peak detector when peak not currently detected + * @{ + */ +#define MDM_AGCPD__TIA_PEAK_THR_HIGH__SHIFT 12 +#define MDM_AGCPD__TIA_PEAK_THR_HIGH__WIDTH 4 +#define MDM_AGCPD__TIA_PEAK_THR_HIGH__MASK 0x0000f000U +#define MDM_AGCPD__TIA_PEAK_THR_HIGH__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f000U) >> 12) +#define MDM_AGCPD__TIA_PEAK_THR_HIGH__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0000f000U) +#define MDM_AGCPD__TIA_PEAK_THR_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((uint32_t)(src) <<\ + 12) & 0x0000f000U) +#define MDM_AGCPD__TIA_PEAK_THR_HIGH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0000f000U))) +#define MDM_AGCPD__TIA_PEAK_THR_HIGH__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field tia_peak_thr_low */ +/** + * @defgroup mdm_regs_core_tia_peak_thr_low_field tia_peak_thr_low_field + * @brief macros for field tia_peak_thr_low + * @details Threshold for TIA peak detector when peak currently detected + * @{ + */ +#define MDM_AGCPD__TIA_PEAK_THR_LOW__SHIFT 16 +#define MDM_AGCPD__TIA_PEAK_THR_LOW__WIDTH 4 +#define MDM_AGCPD__TIA_PEAK_THR_LOW__MASK 0x000f0000U +#define MDM_AGCPD__TIA_PEAK_THR_LOW__READ(src) \ + (((uint32_t)(src)\ + & 0x000f0000U) >> 16) +#define MDM_AGCPD__TIA_PEAK_THR_LOW__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x000f0000U) +#define MDM_AGCPD__TIA_PEAK_THR_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((uint32_t)(src) <<\ + 16) & 0x000f0000U) +#define MDM_AGCPD__TIA_PEAK_THR_LOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x000f0000U))) +#define MDM_AGCPD__TIA_PEAK_THR_LOW__RESET_VALUE 0x00000002U +/** @} */ +#define MDM_AGCPD__TYPE uint32_t +#define MDM_AGCPD__READ 0x000fffffU +#define MDM_AGCPD__WRITE 0x000fffffU +#define MDM_AGCPD__PRESERVED 0x00000000U +#define MDM_AGCPD__RESET_VALUE 0x00022268U + +#endif /* __MDM_AGCPD_MACRO__ */ + +/** @} end of agcpd */ + +/* macros for BlueprintGlobalNameSpace::MDM_agcpd_alt */ +/** + * @defgroup mdm_regs_core_agcpd_alt agcpd_alt + * @brief agc peak detect control, alternate set definitions. + * @{ + */ +#ifndef __MDM_AGCPD_ALT_MACRO__ +#define __MDM_AGCPD_ALT_MACRO__ + +/* macros for field check_win */ +/** + * @defgroup mdm_regs_core_check_win_field check_win_field + * @brief macros for field check_win + * @details Number of samples to measure for peak detection + * @{ + */ +#define MDM_AGCPD_ALT__CHECK_WIN__SHIFT 0 +#define MDM_AGCPD_ALT__CHECK_WIN__WIDTH 4 +#define MDM_AGCPD_ALT__CHECK_WIN__MASK 0x0000000fU +#define MDM_AGCPD_ALT__CHECK_WIN__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define MDM_AGCPD_ALT__CHECK_WIN__WRITE(src) ((uint32_t)(src) & 0x0000000fU) +#define MDM_AGCPD_ALT__CHECK_WIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define MDM_AGCPD_ALT__CHECK_WIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define MDM_AGCPD_ALT__CHECK_WIN__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field rfin_peak_thr_high */ +/** + * @defgroup mdm_regs_core_rfin_peak_thr_high_field rfin_peak_thr_high_field + * @brief macros for field rfin_peak_thr_high + * @details Threshold for LNA peak detector when peak not currently detected + * @{ + */ +#define MDM_AGCPD_ALT__RFIN_PEAK_THR_HIGH__SHIFT 4 +#define MDM_AGCPD_ALT__RFIN_PEAK_THR_HIGH__WIDTH 4 +#define MDM_AGCPD_ALT__RFIN_PEAK_THR_HIGH__MASK 0x000000f0U +#define MDM_AGCPD_ALT__RFIN_PEAK_THR_HIGH__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define MDM_AGCPD_ALT__RFIN_PEAK_THR_HIGH__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x000000f0U) +#define MDM_AGCPD_ALT__RFIN_PEAK_THR_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define MDM_AGCPD_ALT__RFIN_PEAK_THR_HIGH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define MDM_AGCPD_ALT__RFIN_PEAK_THR_HIGH__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field rfin_peak_thr_low */ +/** + * @defgroup mdm_regs_core_rfin_peak_thr_low_field rfin_peak_thr_low_field + * @brief macros for field rfin_peak_thr_low + * @details Threshold for LNA peak detector when peak currently detected + * @{ + */ +#define MDM_AGCPD_ALT__RFIN_PEAK_THR_LOW__SHIFT 8 +#define MDM_AGCPD_ALT__RFIN_PEAK_THR_LOW__WIDTH 4 +#define MDM_AGCPD_ALT__RFIN_PEAK_THR_LOW__MASK 0x00000f00U +#define MDM_AGCPD_ALT__RFIN_PEAK_THR_LOW__READ(src) \ + (((uint32_t)(src)\ + & 0x00000f00U) >> 8) +#define MDM_AGCPD_ALT__RFIN_PEAK_THR_LOW__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000f00U) +#define MDM_AGCPD_ALT__RFIN_PEAK_THR_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((uint32_t)(src) <<\ + 8) & 0x00000f00U) +#define MDM_AGCPD_ALT__RFIN_PEAK_THR_LOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000f00U))) +#define MDM_AGCPD_ALT__RFIN_PEAK_THR_LOW__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field tia_peak_thr_high */ +/** + * @defgroup mdm_regs_core_tia_peak_thr_high_field tia_peak_thr_high_field + * @brief macros for field tia_peak_thr_high + * @details Threshold for TIA peak detector when peak not currently detected + * @{ + */ +#define MDM_AGCPD_ALT__TIA_PEAK_THR_HIGH__SHIFT 12 +#define MDM_AGCPD_ALT__TIA_PEAK_THR_HIGH__WIDTH 4 +#define MDM_AGCPD_ALT__TIA_PEAK_THR_HIGH__MASK 0x0000f000U +#define MDM_AGCPD_ALT__TIA_PEAK_THR_HIGH__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f000U) >> 12) +#define MDM_AGCPD_ALT__TIA_PEAK_THR_HIGH__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0000f000U) +#define MDM_AGCPD_ALT__TIA_PEAK_THR_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((uint32_t)(src) <<\ + 12) & 0x0000f000U) +#define MDM_AGCPD_ALT__TIA_PEAK_THR_HIGH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0000f000U))) +#define MDM_AGCPD_ALT__TIA_PEAK_THR_HIGH__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field tia_peak_thr_low */ +/** + * @defgroup mdm_regs_core_tia_peak_thr_low_field tia_peak_thr_low_field + * @brief macros for field tia_peak_thr_low + * @details Threshold for TIA peak detector when peak currently detected + * @{ + */ +#define MDM_AGCPD_ALT__TIA_PEAK_THR_LOW__SHIFT 16 +#define MDM_AGCPD_ALT__TIA_PEAK_THR_LOW__WIDTH 4 +#define MDM_AGCPD_ALT__TIA_PEAK_THR_LOW__MASK 0x000f0000U +#define MDM_AGCPD_ALT__TIA_PEAK_THR_LOW__READ(src) \ + (((uint32_t)(src)\ + & 0x000f0000U) >> 16) +#define MDM_AGCPD_ALT__TIA_PEAK_THR_LOW__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x000f0000U) +#define MDM_AGCPD_ALT__TIA_PEAK_THR_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((uint32_t)(src) <<\ + 16) & 0x000f0000U) +#define MDM_AGCPD_ALT__TIA_PEAK_THR_LOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x000f0000U))) +#define MDM_AGCPD_ALT__TIA_PEAK_THR_LOW__RESET_VALUE 0x00000002U +/** @} */ +#define MDM_AGCPD_ALT__TYPE uint32_t +#define MDM_AGCPD_ALT__READ 0x000fffffU +#define MDM_AGCPD_ALT__WRITE 0x000fffffU +#define MDM_AGCPD_ALT__PRESERVED 0x00000000U +#define MDM_AGCPD_ALT__RESET_VALUE 0x00022268U + +#endif /* __MDM_AGCPD_ALT_MACRO__ */ + +/** @} end of agcpd_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_agcdet */ +/** + * @defgroup mdm_regs_core_agcdet agcdet + * @brief 16 MHz clock delays added to saturation and TIA peak detect relative to RFIN peak detect definitions. + * @{ + */ +#ifndef __MDM_AGCDET_MACRO__ +#define __MDM_AGCDET_MACRO__ + +/* macros for field sat_delay */ +/** + * @defgroup mdm_regs_core_sat_delay_field sat_delay_field + * @brief macros for field sat_delay + * @details Delay for saturation, 1M + * @{ + */ +#define MDM_AGCDET__SAT_DELAY__SHIFT 0 +#define MDM_AGCDET__SAT_DELAY__WIDTH 5 +#define MDM_AGCDET__SAT_DELAY__MASK 0x0000001fU +#define MDM_AGCDET__SAT_DELAY__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define MDM_AGCDET__SAT_DELAY__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define MDM_AGCDET__SAT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define MDM_AGCDET__SAT_DELAY__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define MDM_AGCDET__SAT_DELAY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field twomeg_sat_delay */ +/** + * @defgroup mdm_regs_core_twomeg_sat_delay_field twomeg_sat_delay_field + * @brief macros for field twomeg_sat_delay + * @details Delay for saturation, 2M + * @{ + */ +#define MDM_AGCDET__TWOMEG_SAT_DELAY__SHIFT 5 +#define MDM_AGCDET__TWOMEG_SAT_DELAY__WIDTH 5 +#define MDM_AGCDET__TWOMEG_SAT_DELAY__MASK 0x000003e0U +#define MDM_AGCDET__TWOMEG_SAT_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x000003e0U) >> 5) +#define MDM_AGCDET__TWOMEG_SAT_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x000003e0U) +#define MDM_AGCDET__TWOMEG_SAT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((uint32_t)(src) <<\ + 5) & 0x000003e0U) +#define MDM_AGCDET__TWOMEG_SAT_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000003e0U))) +#define MDM_AGCDET__TWOMEG_SAT_DELAY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tiapd_delay */ +/** + * @defgroup mdm_regs_core_tiapd_delay_field tiapd_delay_field + * @brief macros for field tiapd_delay + * @details Delay for saturation, 1M + * @{ + */ +#define MDM_AGCDET__TIAPD_DELAY__SHIFT 10 +#define MDM_AGCDET__TIAPD_DELAY__WIDTH 5 +#define MDM_AGCDET__TIAPD_DELAY__MASK 0x00007c00U +#define MDM_AGCDET__TIAPD_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x00007c00U) >> 10) +#define MDM_AGCDET__TIAPD_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00007c00U) +#define MDM_AGCDET__TIAPD_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((uint32_t)(src) <<\ + 10) & 0x00007c00U) +#define MDM_AGCDET__TIAPD_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00007c00U))) +#define MDM_AGCDET__TIAPD_DELAY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field twomeg_tiapd_delay */ +/** + * @defgroup mdm_regs_core_twomeg_tiapd_delay_field twomeg_tiapd_delay_field + * @brief macros for field twomeg_tiapd_delay + * @details Delay for saturation, 2M + * @{ + */ +#define MDM_AGCDET__TWOMEG_TIAPD_DELAY__SHIFT 15 +#define MDM_AGCDET__TWOMEG_TIAPD_DELAY__WIDTH 5 +#define MDM_AGCDET__TWOMEG_TIAPD_DELAY__MASK 0x000f8000U +#define MDM_AGCDET__TWOMEG_TIAPD_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x000f8000U) >> 15) +#define MDM_AGCDET__TWOMEG_TIAPD_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x000f8000U) +#define MDM_AGCDET__TWOMEG_TIAPD_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((uint32_t)(src) <<\ + 15) & 0x000f8000U) +#define MDM_AGCDET__TWOMEG_TIAPD_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x000f8000U))) +#define MDM_AGCDET__TWOMEG_TIAPD_DELAY__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_AGCDET__TYPE uint32_t +#define MDM_AGCDET__READ 0x000fffffU +#define MDM_AGCDET__WRITE 0x000fffffU +#define MDM_AGCDET__PRESERVED 0x00000000U +#define MDM_AGCDET__RESET_VALUE 0x00000000U + +#endif /* __MDM_AGCDET_MACRO__ */ + +/** @} end of agcdet */ + +/* macros for BlueprintGlobalNameSpace::MDM_agcdet_alt */ +/** + * @defgroup mdm_regs_core_agcdet_alt agcdet_alt + * @brief 16 MHz clock delays added to saturation and TIA peak detect relative to RFIN peak detect, alternate set definitions. + * @{ + */ +#ifndef __MDM_AGCDET_ALT_MACRO__ +#define __MDM_AGCDET_ALT_MACRO__ + +/* macros for field sat_delay */ +/** + * @defgroup mdm_regs_core_sat_delay_field sat_delay_field + * @brief macros for field sat_delay + * @details Delay for saturation, 1M + * @{ + */ +#define MDM_AGCDET_ALT__SAT_DELAY__SHIFT 0 +#define MDM_AGCDET_ALT__SAT_DELAY__WIDTH 5 +#define MDM_AGCDET_ALT__SAT_DELAY__MASK 0x0000001fU +#define MDM_AGCDET_ALT__SAT_DELAY__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define MDM_AGCDET_ALT__SAT_DELAY__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define MDM_AGCDET_ALT__SAT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define MDM_AGCDET_ALT__SAT_DELAY__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define MDM_AGCDET_ALT__SAT_DELAY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field twomeg_sat_delay */ +/** + * @defgroup mdm_regs_core_twomeg_sat_delay_field twomeg_sat_delay_field + * @brief macros for field twomeg_sat_delay + * @details Delay for saturation, 2M + * @{ + */ +#define MDM_AGCDET_ALT__TWOMEG_SAT_DELAY__SHIFT 5 +#define MDM_AGCDET_ALT__TWOMEG_SAT_DELAY__WIDTH 5 +#define MDM_AGCDET_ALT__TWOMEG_SAT_DELAY__MASK 0x000003e0U +#define MDM_AGCDET_ALT__TWOMEG_SAT_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x000003e0U) >> 5) +#define MDM_AGCDET_ALT__TWOMEG_SAT_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x000003e0U) +#define MDM_AGCDET_ALT__TWOMEG_SAT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((uint32_t)(src) <<\ + 5) & 0x000003e0U) +#define MDM_AGCDET_ALT__TWOMEG_SAT_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000003e0U))) +#define MDM_AGCDET_ALT__TWOMEG_SAT_DELAY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tiapd_delay */ +/** + * @defgroup mdm_regs_core_tiapd_delay_field tiapd_delay_field + * @brief macros for field tiapd_delay + * @details Delay for saturation, 1M + * @{ + */ +#define MDM_AGCDET_ALT__TIAPD_DELAY__SHIFT 10 +#define MDM_AGCDET_ALT__TIAPD_DELAY__WIDTH 5 +#define MDM_AGCDET_ALT__TIAPD_DELAY__MASK 0x00007c00U +#define MDM_AGCDET_ALT__TIAPD_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x00007c00U) >> 10) +#define MDM_AGCDET_ALT__TIAPD_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00007c00U) +#define MDM_AGCDET_ALT__TIAPD_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((uint32_t)(src) <<\ + 10) & 0x00007c00U) +#define MDM_AGCDET_ALT__TIAPD_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00007c00U))) +#define MDM_AGCDET_ALT__TIAPD_DELAY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field twomeg_tiapd_delay */ +/** + * @defgroup mdm_regs_core_twomeg_tiapd_delay_field twomeg_tiapd_delay_field + * @brief macros for field twomeg_tiapd_delay + * @details Delay for saturation, 2M + * @{ + */ +#define MDM_AGCDET_ALT__TWOMEG_TIAPD_DELAY__SHIFT 15 +#define MDM_AGCDET_ALT__TWOMEG_TIAPD_DELAY__WIDTH 5 +#define MDM_AGCDET_ALT__TWOMEG_TIAPD_DELAY__MASK 0x000f8000U +#define MDM_AGCDET_ALT__TWOMEG_TIAPD_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x000f8000U) >> 15) +#define MDM_AGCDET_ALT__TWOMEG_TIAPD_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x000f8000U) +#define MDM_AGCDET_ALT__TWOMEG_TIAPD_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((uint32_t)(src) <<\ + 15) & 0x000f8000U) +#define MDM_AGCDET_ALT__TWOMEG_TIAPD_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x000f8000U))) +#define MDM_AGCDET_ALT__TWOMEG_TIAPD_DELAY__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_AGCDET_ALT__TYPE uint32_t +#define MDM_AGCDET_ALT__READ 0x000fffffU +#define MDM_AGCDET_ALT__WRITE 0x000fffffU +#define MDM_AGCDET_ALT__PRESERVED 0x00000000U +#define MDM_AGCDET_ALT__RESET_VALUE 0x00000000U + +#endif /* __MDM_AGCDET_ALT_MACRO__ */ + +/** @} end of agcdet_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_agcoffset */ +/** + * @defgroup mdm_regs_core_agcoffset agcoffset + * @brief Paris: agcoffset_adc_quick_drop = Saturation offset of TIA with respect to ADC, in dB: New rxgain = Old rxgain - pgagain - agcoffset_adc_quick_drop Sydney ASIC with Paris FPGA (dtop_bypass): agcoffset_sydney__adc_quick_drop = Saturation offset of LNA with respect to ADC: New rxgain = Old LNA gain + 18 - agcoffset_sydney_adc_quick_drop The intent is to reduce rxgain to barely get us out of ADC saturation after the drop. Add a couple dB of margin to the values programmed below. definitions. + * @{ + */ +#ifndef __MDM_AGCOFFSET_MACRO__ +#define __MDM_AGCOFFSET_MACRO__ + +/* macros for field adc_quick_drop */ +/** + * @defgroup mdm_regs_core_adc_quick_drop_field adc_quick_drop_field + * @brief macros for field adc_quick_drop + * @details Signed. 1M + * @{ + */ +#define MDM_AGCOFFSET__ADC_QUICK_DROP__SHIFT 0 +#define MDM_AGCOFFSET__ADC_QUICK_DROP__WIDTH 6 +#define MDM_AGCOFFSET__ADC_QUICK_DROP__MASK 0x0000003fU +#define MDM_AGCOFFSET__ADC_QUICK_DROP__READ(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_AGCOFFSET__ADC_QUICK_DROP__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_AGCOFFSET__ADC_QUICK_DROP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define MDM_AGCOFFSET__ADC_QUICK_DROP__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define MDM_AGCOFFSET__ADC_QUICK_DROP__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field twomeg_adc_quick_drop */ +/** + * @defgroup mdm_regs_core_twomeg_adc_quick_drop_field twomeg_adc_quick_drop_field + * @brief macros for field twomeg_adc_quick_drop + * @details Signed. 2M + * @{ + */ +#define MDM_AGCOFFSET__TWOMEG_ADC_QUICK_DROP__SHIFT 6 +#define MDM_AGCOFFSET__TWOMEG_ADC_QUICK_DROP__WIDTH 6 +#define MDM_AGCOFFSET__TWOMEG_ADC_QUICK_DROP__MASK 0x00000fc0U +#define MDM_AGCOFFSET__TWOMEG_ADC_QUICK_DROP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000fc0U) >> 6) +#define MDM_AGCOFFSET__TWOMEG_ADC_QUICK_DROP__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000fc0U) +#define MDM_AGCOFFSET__TWOMEG_ADC_QUICK_DROP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((uint32_t)(src) <<\ + 6) & 0x00000fc0U) +#define MDM_AGCOFFSET__TWOMEG_ADC_QUICK_DROP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000fc0U))) +#define MDM_AGCOFFSET__TWOMEG_ADC_QUICK_DROP__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field sydney_adc_quick_drop */ +/** + * @defgroup mdm_regs_core_sydney_adc_quick_drop_field sydney_adc_quick_drop_field + * @brief macros for field sydney_adc_quick_drop + * @details Signed. 1M. 0x3f = -1 + * @{ + */ +#define MDM_AGCOFFSET__SYDNEY_ADC_QUICK_DROP__SHIFT 12 +#define MDM_AGCOFFSET__SYDNEY_ADC_QUICK_DROP__WIDTH 6 +#define MDM_AGCOFFSET__SYDNEY_ADC_QUICK_DROP__MASK 0x0003f000U +#define MDM_AGCOFFSET__SYDNEY_ADC_QUICK_DROP__READ(src) \ + (((uint32_t)(src)\ + & 0x0003f000U) >> 12) +#define MDM_AGCOFFSET__SYDNEY_ADC_QUICK_DROP__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0003f000U) +#define MDM_AGCOFFSET__SYDNEY_ADC_QUICK_DROP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((uint32_t)(src) <<\ + 12) & 0x0003f000U) +#define MDM_AGCOFFSET__SYDNEY_ADC_QUICK_DROP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0003f000U))) +#define MDM_AGCOFFSET__SYDNEY_ADC_QUICK_DROP__RESET_VALUE 0x0000003fU +/** @} */ + +/* macros for field sydney_twomeg_adc_quick_drop */ +/** + * @defgroup mdm_regs_core_sydney_twomeg_adc_quick_drop_field sydney_twomeg_adc_quick_drop_field + * @brief macros for field sydney_twomeg_adc_quick_drop + * @details Signed. 2M. 0x3f = -1 + * @{ + */ +#define MDM_AGCOFFSET__SYDNEY_TWOMEG_ADC_QUICK_DROP__SHIFT 18 +#define MDM_AGCOFFSET__SYDNEY_TWOMEG_ADC_QUICK_DROP__WIDTH 6 +#define MDM_AGCOFFSET__SYDNEY_TWOMEG_ADC_QUICK_DROP__MASK 0x00fc0000U +#define MDM_AGCOFFSET__SYDNEY_TWOMEG_ADC_QUICK_DROP__READ(src) \ + (((uint32_t)(src)\ + & 0x00fc0000U) >> 18) +#define MDM_AGCOFFSET__SYDNEY_TWOMEG_ADC_QUICK_DROP__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00fc0000U) +#define MDM_AGCOFFSET__SYDNEY_TWOMEG_ADC_QUICK_DROP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((uint32_t)(src) <<\ + 18) & 0x00fc0000U) +#define MDM_AGCOFFSET__SYDNEY_TWOMEG_ADC_QUICK_DROP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00fc0000U))) +#define MDM_AGCOFFSET__SYDNEY_TWOMEG_ADC_QUICK_DROP__RESET_VALUE 0x0000003fU +/** @} */ +#define MDM_AGCOFFSET__TYPE uint32_t +#define MDM_AGCOFFSET__READ 0x00ffffffU +#define MDM_AGCOFFSET__WRITE 0x00ffffffU +#define MDM_AGCOFFSET__PRESERVED 0x00000000U +#define MDM_AGCOFFSET__RESET_VALUE 0x00fff082U + +#endif /* __MDM_AGCOFFSET_MACRO__ */ + +/** @} end of agcoffset */ + +/* macros for BlueprintGlobalNameSpace::MDM_agcoffset_alt */ +/** + * @defgroup mdm_regs_core_agcoffset_alt agcoffset_alt + * @brief Paris: agcoffset_adc_quick_drop = Saturation offset of TIA with respect to ADC, in dB: New rxgain = Old rxgain - pgagain - agcoffset_adc_quick_drop Sydney ASIC with Paris FPGA (dtop_bypass): agcoffset_sydney__adc_quick_drop = Saturation offset of LNA with respect to ADC: New rxgain = Old LNA gain + 18 - agcoffset_sydney_adc_quick_drop The intent is to reduce rxgain to barely get us out of ADC saturation after the drop. Add a couple dB of margin to the values programmed below. definitions. + * @{ + */ +#ifndef __MDM_AGCOFFSET_ALT_MACRO__ +#define __MDM_AGCOFFSET_ALT_MACRO__ + +/* macros for field adc_quick_drop */ +/** + * @defgroup mdm_regs_core_adc_quick_drop_field adc_quick_drop_field + * @brief macros for field adc_quick_drop + * @details Signed. 1M + * @{ + */ +#define MDM_AGCOFFSET_ALT__ADC_QUICK_DROP__SHIFT 0 +#define MDM_AGCOFFSET_ALT__ADC_QUICK_DROP__WIDTH 6 +#define MDM_AGCOFFSET_ALT__ADC_QUICK_DROP__MASK 0x0000003fU +#define MDM_AGCOFFSET_ALT__ADC_QUICK_DROP__READ(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_AGCOFFSET_ALT__ADC_QUICK_DROP__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_AGCOFFSET_ALT__ADC_QUICK_DROP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define MDM_AGCOFFSET_ALT__ADC_QUICK_DROP__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define MDM_AGCOFFSET_ALT__ADC_QUICK_DROP__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field twomeg_adc_quick_drop */ +/** + * @defgroup mdm_regs_core_twomeg_adc_quick_drop_field twomeg_adc_quick_drop_field + * @brief macros for field twomeg_adc_quick_drop + * @details Signed. 2M + * @{ + */ +#define MDM_AGCOFFSET_ALT__TWOMEG_ADC_QUICK_DROP__SHIFT 6 +#define MDM_AGCOFFSET_ALT__TWOMEG_ADC_QUICK_DROP__WIDTH 6 +#define MDM_AGCOFFSET_ALT__TWOMEG_ADC_QUICK_DROP__MASK 0x00000fc0U +#define MDM_AGCOFFSET_ALT__TWOMEG_ADC_QUICK_DROP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000fc0U) >> 6) +#define MDM_AGCOFFSET_ALT__TWOMEG_ADC_QUICK_DROP__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000fc0U) +#define MDM_AGCOFFSET_ALT__TWOMEG_ADC_QUICK_DROP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((uint32_t)(src) <<\ + 6) & 0x00000fc0U) +#define MDM_AGCOFFSET_ALT__TWOMEG_ADC_QUICK_DROP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000fc0U))) +#define MDM_AGCOFFSET_ALT__TWOMEG_ADC_QUICK_DROP__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field sydney_adc_quick_drop */ +/** + * @defgroup mdm_regs_core_sydney_adc_quick_drop_field sydney_adc_quick_drop_field + * @brief macros for field sydney_adc_quick_drop + * @details Signed. 1M. 0x3f = -1 + * @{ + */ +#define MDM_AGCOFFSET_ALT__SYDNEY_ADC_QUICK_DROP__SHIFT 12 +#define MDM_AGCOFFSET_ALT__SYDNEY_ADC_QUICK_DROP__WIDTH 6 +#define MDM_AGCOFFSET_ALT__SYDNEY_ADC_QUICK_DROP__MASK 0x0003f000U +#define MDM_AGCOFFSET_ALT__SYDNEY_ADC_QUICK_DROP__READ(src) \ + (((uint32_t)(src)\ + & 0x0003f000U) >> 12) +#define MDM_AGCOFFSET_ALT__SYDNEY_ADC_QUICK_DROP__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0003f000U) +#define MDM_AGCOFFSET_ALT__SYDNEY_ADC_QUICK_DROP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((uint32_t)(src) <<\ + 12) & 0x0003f000U) +#define MDM_AGCOFFSET_ALT__SYDNEY_ADC_QUICK_DROP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0003f000U))) +#define MDM_AGCOFFSET_ALT__SYDNEY_ADC_QUICK_DROP__RESET_VALUE 0x0000003fU +/** @} */ + +/* macros for field sydney_twomeg_adc_quick_drop */ +/** + * @defgroup mdm_regs_core_sydney_twomeg_adc_quick_drop_field sydney_twomeg_adc_quick_drop_field + * @brief macros for field sydney_twomeg_adc_quick_drop + * @details Signed. 2M. 0x3f = -1 + * @{ + */ +#define MDM_AGCOFFSET_ALT__SYDNEY_TWOMEG_ADC_QUICK_DROP__SHIFT 18 +#define MDM_AGCOFFSET_ALT__SYDNEY_TWOMEG_ADC_QUICK_DROP__WIDTH 6 +#define MDM_AGCOFFSET_ALT__SYDNEY_TWOMEG_ADC_QUICK_DROP__MASK 0x00fc0000U +#define MDM_AGCOFFSET_ALT__SYDNEY_TWOMEG_ADC_QUICK_DROP__READ(src) \ + (((uint32_t)(src)\ + & 0x00fc0000U) >> 18) +#define MDM_AGCOFFSET_ALT__SYDNEY_TWOMEG_ADC_QUICK_DROP__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00fc0000U) +#define MDM_AGCOFFSET_ALT__SYDNEY_TWOMEG_ADC_QUICK_DROP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((uint32_t)(src) <<\ + 18) & 0x00fc0000U) +#define MDM_AGCOFFSET_ALT__SYDNEY_TWOMEG_ADC_QUICK_DROP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00fc0000U))) +#define MDM_AGCOFFSET_ALT__SYDNEY_TWOMEG_ADC_QUICK_DROP__RESET_VALUE \ + 0x0000003fU +/** @} */ +#define MDM_AGCOFFSET_ALT__TYPE uint32_t +#define MDM_AGCOFFSET_ALT__READ 0x00ffffffU +#define MDM_AGCOFFSET_ALT__WRITE 0x00ffffffU +#define MDM_AGCOFFSET_ALT__PRESERVED 0x00000000U +#define MDM_AGCOFFSET_ALT__RESET_VALUE 0x00fff082U + +#endif /* __MDM_AGCOFFSET_ALT_MACRO__ */ + +/** @} end of agcoffset_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_synch */ +/** + * @defgroup mdm_regs_core_synch synch + * @brief Frequency and timing synchronization control definitions. + * @{ + */ +#ifndef __MDM_SYNCH_MACRO__ +#define __MDM_SYNCH_MACRO__ + +/* macros for field pg */ +/** + * @defgroup mdm_regs_core_pg_field pg_field + * @brief macros for field pg + * @details Proportional gain for timing tracking Encoding: 0 -> 0. Else 2^(-pg) + * @{ + */ +#define MDM_SYNCH__PG__SHIFT 2 +#define MDM_SYNCH__PG__WIDTH 2 +#define MDM_SYNCH__PG__MASK 0x0000000cU +#define MDM_SYNCH__PG__READ(src) (((uint32_t)(src) & 0x0000000cU) >> 2) +#define MDM_SYNCH__PG__WRITE(src) (((uint32_t)(src) << 2) & 0x0000000cU) +#define MDM_SYNCH__PG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((uint32_t)(src) <<\ + 2) & 0x0000000cU) +#define MDM_SYNCH__PG__VERIFY(src) (!((((uint32_t)(src) << 2) & ~0x0000000cU))) +#define MDM_SYNCH__PG__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ph_reg_thr */ +/** + * @defgroup mdm_regs_core_ph_reg_thr_field ph_reg_thr_field + * @brief macros for field ph_reg_thr + * @details Phase accumulator threshold for timing tracking Encoding: 2^(ph_reg_thr). Gear 1. Supported range: 0-5 + * @{ + */ +#define MDM_SYNCH__PH_REG_THR__SHIFT 4 +#define MDM_SYNCH__PH_REG_THR__WIDTH 3 +#define MDM_SYNCH__PH_REG_THR__MASK 0x00000070U +#define MDM_SYNCH__PH_REG_THR__READ(src) (((uint32_t)(src) & 0x00000070U) >> 4) +#define MDM_SYNCH__PH_REG_THR__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000070U) +#define MDM_SYNCH__PH_REG_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((uint32_t)(src) <<\ + 4) & 0x00000070U) +#define MDM_SYNCH__PH_REG_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000070U))) +#define MDM_SYNCH__PH_REG_THR__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ph_reg_thr2 */ +/** + * @defgroup mdm_regs_core_ph_reg_thr2_field ph_reg_thr2_field + * @brief macros for field ph_reg_thr2 + * @details Phase accumulator threshold for timing tracking Encoding: 2^(ph_reg_thr). Gear 2. Supported range: 0-5 + * @{ + */ +#define MDM_SYNCH__PH_REG_THR2__SHIFT 7 +#define MDM_SYNCH__PH_REG_THR2__WIDTH 3 +#define MDM_SYNCH__PH_REG_THR2__MASK 0x00000380U +#define MDM_SYNCH__PH_REG_THR2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000380U) >> 7) +#define MDM_SYNCH__PH_REG_THR2__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000380U) +#define MDM_SYNCH__PH_REG_THR2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000380U) | (((uint32_t)(src) <<\ + 7) & 0x00000380U) +#define MDM_SYNCH__PH_REG_THR2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000380U))) +#define MDM_SYNCH__PH_REG_THR2__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field ph_reg_thr3 */ +/** + * @defgroup mdm_regs_core_ph_reg_thr3_field ph_reg_thr3_field + * @brief macros for field ph_reg_thr3 + * @details Phase accumulator threshold for timing tracking Encoding: 2^(ph_reg_thr). Gear 3. Supported range: 0-5 + * @{ + */ +#define MDM_SYNCH__PH_REG_THR3__SHIFT 10 +#define MDM_SYNCH__PH_REG_THR3__WIDTH 3 +#define MDM_SYNCH__PH_REG_THR3__MASK 0x00001c00U +#define MDM_SYNCH__PH_REG_THR3__READ(src) \ + (((uint32_t)(src)\ + & 0x00001c00U) >> 10) +#define MDM_SYNCH__PH_REG_THR3__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00001c00U) +#define MDM_SYNCH__PH_REG_THR3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001c00U) | (((uint32_t)(src) <<\ + 10) & 0x00001c00U) +#define MDM_SYNCH__PH_REG_THR3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00001c00U))) +#define MDM_SYNCH__PH_REG_THR3__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field enable_time_track */ +/** + * @defgroup mdm_regs_core_enable_time_track_field enable_time_track_field + * @brief macros for field enable_time_track + * @details Enable time tracking, although can also be disabled with setting pg to 2'd0 + * @{ + */ +#define MDM_SYNCH__ENABLE_TIME_TRACK__SHIFT 13 +#define MDM_SYNCH__ENABLE_TIME_TRACK__WIDTH 1 +#define MDM_SYNCH__ENABLE_TIME_TRACK__MASK 0x00002000U +#define MDM_SYNCH__ENABLE_TIME_TRACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define MDM_SYNCH__ENABLE_TIME_TRACK__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define MDM_SYNCH__ENABLE_TIME_TRACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define MDM_SYNCH__ENABLE_TIME_TRACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define MDM_SYNCH__ENABLE_TIME_TRACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define MDM_SYNCH__ENABLE_TIME_TRACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define MDM_SYNCH__ENABLE_TIME_TRACK__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field freq_force_initial */ +/** + * @defgroup mdm_regs_core_freq_force_initial_field freq_force_initial_field + * @brief macros for field freq_force_initial + * @details Force initial frequency estimate + * @{ + */ +#define MDM_SYNCH__FREQ_FORCE_INITIAL__SHIFT 14 +#define MDM_SYNCH__FREQ_FORCE_INITIAL__WIDTH 1 +#define MDM_SYNCH__FREQ_FORCE_INITIAL__MASK 0x00004000U +#define MDM_SYNCH__FREQ_FORCE_INITIAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define MDM_SYNCH__FREQ_FORCE_INITIAL__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define MDM_SYNCH__FREQ_FORCE_INITIAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define MDM_SYNCH__FREQ_FORCE_INITIAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define MDM_SYNCH__FREQ_FORCE_INITIAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define MDM_SYNCH__FREQ_FORCE_INITIAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define MDM_SYNCH__FREQ_FORCE_INITIAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field freq_forced_value */ +/** + * @defgroup mdm_regs_core_freq_forced_value_field freq_forced_value_field + * @brief macros for field freq_forced_value + * @details Forced initial frequency estimate value. Signed quantity. MSB has weight of -1 MHz. Subsequent bits have weight of 1/2 MHz, 1/4 MHz ... LSB has weight of 1/4096 MHz + * @{ + */ +#define MDM_SYNCH__FREQ_FORCED_VALUE__SHIFT 15 +#define MDM_SYNCH__FREQ_FORCED_VALUE__WIDTH 13 +#define MDM_SYNCH__FREQ_FORCED_VALUE__MASK 0x0fff8000U +#define MDM_SYNCH__FREQ_FORCED_VALUE__READ(src) \ + (((uint32_t)(src)\ + & 0x0fff8000U) >> 15) +#define MDM_SYNCH__FREQ_FORCED_VALUE__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x0fff8000U) +#define MDM_SYNCH__FREQ_FORCED_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fff8000U) | (((uint32_t)(src) <<\ + 15) & 0x0fff8000U) +#define MDM_SYNCH__FREQ_FORCED_VALUE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x0fff8000U))) +#define MDM_SYNCH__FREQ_FORCED_VALUE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rst_freq_no_gain_change_pwrstep */ +/** + * @defgroup mdm_regs_core_rst_freq_no_gain_change_pwrstep_field rst_freq_no_gain_change_pwrstep_field + * @brief macros for field rst_freq_no_gain_change_pwrstep + * @details Allow (unlimited) assert_reset_freq_sync due to power step within a MEASURE state, with no gain change + * @{ + */ +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_PWRSTEP__SHIFT 28 +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_PWRSTEP__WIDTH 1 +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_PWRSTEP__MASK 0x10000000U +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_PWRSTEP__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_PWRSTEP__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_PWRSTEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_PWRSTEP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_PWRSTEP__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_PWRSTEP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_PWRSTEP__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field rst_freq_no_gain_change_rfin */ +/** + * @defgroup mdm_regs_core_rst_freq_no_gain_change_rfin_field rst_freq_no_gain_change_rfin_field + * @brief macros for field rst_freq_no_gain_change_rfin + * @details Allow one assert_reset_freq_sync due to rfin peak within a MEASURE state, with no gain change + * @{ + */ +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_RFIN__SHIFT 29 +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_RFIN__WIDTH 1 +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_RFIN__MASK 0x20000000U +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_RFIN__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_RFIN__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_RFIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_RFIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_RFIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_RFIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_RFIN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field rst_freq_no_gain_change_tia */ +/** + * @defgroup mdm_regs_core_rst_freq_no_gain_change_tia_field rst_freq_no_gain_change_tia_field + * @brief macros for field rst_freq_no_gain_change_tia + * @details Allow one assert_reset_freq_sync due to tia peak within a MEASURE state, with no gain change + * @{ + */ +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_TIA__SHIFT 30 +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_TIA__WIDTH 1 +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_TIA__MASK 0x40000000U +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_TIA__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_TIA__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_TIA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_TIA__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_TIA__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_TIA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_TIA__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field rst_freq_no_gain_change_sat */ +/** + * @defgroup mdm_regs_core_rst_freq_no_gain_change_sat_field rst_freq_no_gain_change_sat_field + * @brief macros for field rst_freq_no_gain_change_sat + * @details Allow one assert_reset_freq_sync due to adc sat within a MEASURE state, with no gain change + * @{ + */ +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_SAT__SHIFT 31 +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_SAT__WIDTH 1 +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_SAT__MASK 0x80000000U +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_SAT__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_SAT__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_SAT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_SAT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_SAT__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_SAT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_SYNCH__RST_FREQ_NO_GAIN_CHANGE_SAT__RESET_VALUE 0x00000001U +/** @} */ +#define MDM_SYNCH__TYPE uint32_t +#define MDM_SYNCH__READ 0xfffffffcU +#define MDM_SYNCH__WRITE 0xfffffffcU +#define MDM_SYNCH__PRESERVED 0x00000000U +#define MDM_SYNCH__RESET_VALUE 0xf0003194U + +#endif /* __MDM_SYNCH_MACRO__ */ + +/** @} end of synch */ + +/* macros for BlueprintGlobalNameSpace::MDM_synch_alt */ +/** + * @defgroup mdm_regs_core_synch_alt synch_alt + * @brief Frequency and timing synchronization control, alternate set definitions. + * @{ + */ +#ifndef __MDM_SYNCH_ALT_MACRO__ +#define __MDM_SYNCH_ALT_MACRO__ + +/* macros for field pg */ +/** + * @defgroup mdm_regs_core_pg_field pg_field + * @brief macros for field pg + * @details Proportional gain for timing tracking Encoding: 0 -> 0. Else 2^(-pg) + * @{ + */ +#define MDM_SYNCH_ALT__PG__SHIFT 2 +#define MDM_SYNCH_ALT__PG__WIDTH 2 +#define MDM_SYNCH_ALT__PG__MASK 0x0000000cU +#define MDM_SYNCH_ALT__PG__READ(src) (((uint32_t)(src) & 0x0000000cU) >> 2) +#define MDM_SYNCH_ALT__PG__WRITE(src) (((uint32_t)(src) << 2) & 0x0000000cU) +#define MDM_SYNCH_ALT__PG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((uint32_t)(src) <<\ + 2) & 0x0000000cU) +#define MDM_SYNCH_ALT__PG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000000cU))) +#define MDM_SYNCH_ALT__PG__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ph_reg_thr */ +/** + * @defgroup mdm_regs_core_ph_reg_thr_field ph_reg_thr_field + * @brief macros for field ph_reg_thr + * @details Phase accumulator threshold for timing tracking Encoding: 2^(ph_reg_thr). Gear 1. Supported range: 0-5 + * @{ + */ +#define MDM_SYNCH_ALT__PH_REG_THR__SHIFT 4 +#define MDM_SYNCH_ALT__PH_REG_THR__WIDTH 3 +#define MDM_SYNCH_ALT__PH_REG_THR__MASK 0x00000070U +#define MDM_SYNCH_ALT__PH_REG_THR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000070U) >> 4) +#define MDM_SYNCH_ALT__PH_REG_THR__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000070U) +#define MDM_SYNCH_ALT__PH_REG_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((uint32_t)(src) <<\ + 4) & 0x00000070U) +#define MDM_SYNCH_ALT__PH_REG_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000070U))) +#define MDM_SYNCH_ALT__PH_REG_THR__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ph_reg_thr2 */ +/** + * @defgroup mdm_regs_core_ph_reg_thr2_field ph_reg_thr2_field + * @brief macros for field ph_reg_thr2 + * @details Phase accumulator threshold for timing tracking Encoding: 2^(ph_reg_thr). Gear 2. Supported range: 0-5 + * @{ + */ +#define MDM_SYNCH_ALT__PH_REG_THR2__SHIFT 7 +#define MDM_SYNCH_ALT__PH_REG_THR2__WIDTH 3 +#define MDM_SYNCH_ALT__PH_REG_THR2__MASK 0x00000380U +#define MDM_SYNCH_ALT__PH_REG_THR2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000380U) >> 7) +#define MDM_SYNCH_ALT__PH_REG_THR2__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000380U) +#define MDM_SYNCH_ALT__PH_REG_THR2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000380U) | (((uint32_t)(src) <<\ + 7) & 0x00000380U) +#define MDM_SYNCH_ALT__PH_REG_THR2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000380U))) +#define MDM_SYNCH_ALT__PH_REG_THR2__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field ph_reg_thr3 */ +/** + * @defgroup mdm_regs_core_ph_reg_thr3_field ph_reg_thr3_field + * @brief macros for field ph_reg_thr3 + * @details Phase accumulator threshold for timing tracking Encoding: 2^(ph_reg_thr). Gear 3. Supported range: 0-5 + * @{ + */ +#define MDM_SYNCH_ALT__PH_REG_THR3__SHIFT 10 +#define MDM_SYNCH_ALT__PH_REG_THR3__WIDTH 3 +#define MDM_SYNCH_ALT__PH_REG_THR3__MASK 0x00001c00U +#define MDM_SYNCH_ALT__PH_REG_THR3__READ(src) \ + (((uint32_t)(src)\ + & 0x00001c00U) >> 10) +#define MDM_SYNCH_ALT__PH_REG_THR3__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00001c00U) +#define MDM_SYNCH_ALT__PH_REG_THR3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001c00U) | (((uint32_t)(src) <<\ + 10) & 0x00001c00U) +#define MDM_SYNCH_ALT__PH_REG_THR3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00001c00U))) +#define MDM_SYNCH_ALT__PH_REG_THR3__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field enable_time_track */ +/** + * @defgroup mdm_regs_core_enable_time_track_field enable_time_track_field + * @brief macros for field enable_time_track + * @details Enable time tracking, although can also be disabled with setting pg to 2'd0 + * @{ + */ +#define MDM_SYNCH_ALT__ENABLE_TIME_TRACK__SHIFT 13 +#define MDM_SYNCH_ALT__ENABLE_TIME_TRACK__WIDTH 1 +#define MDM_SYNCH_ALT__ENABLE_TIME_TRACK__MASK 0x00002000U +#define MDM_SYNCH_ALT__ENABLE_TIME_TRACK__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define MDM_SYNCH_ALT__ENABLE_TIME_TRACK__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define MDM_SYNCH_ALT__ENABLE_TIME_TRACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define MDM_SYNCH_ALT__ENABLE_TIME_TRACK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define MDM_SYNCH_ALT__ENABLE_TIME_TRACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define MDM_SYNCH_ALT__ENABLE_TIME_TRACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define MDM_SYNCH_ALT__ENABLE_TIME_TRACK__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field freq_force_initial */ +/** + * @defgroup mdm_regs_core_freq_force_initial_field freq_force_initial_field + * @brief macros for field freq_force_initial + * @details Force initial frequency estimate + * @{ + */ +#define MDM_SYNCH_ALT__FREQ_FORCE_INITIAL__SHIFT 14 +#define MDM_SYNCH_ALT__FREQ_FORCE_INITIAL__WIDTH 1 +#define MDM_SYNCH_ALT__FREQ_FORCE_INITIAL__MASK 0x00004000U +#define MDM_SYNCH_ALT__FREQ_FORCE_INITIAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define MDM_SYNCH_ALT__FREQ_FORCE_INITIAL__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define MDM_SYNCH_ALT__FREQ_FORCE_INITIAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define MDM_SYNCH_ALT__FREQ_FORCE_INITIAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define MDM_SYNCH_ALT__FREQ_FORCE_INITIAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define MDM_SYNCH_ALT__FREQ_FORCE_INITIAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define MDM_SYNCH_ALT__FREQ_FORCE_INITIAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field freq_forced_value */ +/** + * @defgroup mdm_regs_core_freq_forced_value_field freq_forced_value_field + * @brief macros for field freq_forced_value + * @details Forced initial frequency estimate value. Signed quantity. MSB has weight of -1 MHz. Subsequent bits have weight of 1/2 MHz, 1/4 MHz ... LSB has weight of 1/4096 MHz + * @{ + */ +#define MDM_SYNCH_ALT__FREQ_FORCED_VALUE__SHIFT 15 +#define MDM_SYNCH_ALT__FREQ_FORCED_VALUE__WIDTH 13 +#define MDM_SYNCH_ALT__FREQ_FORCED_VALUE__MASK 0x0fff8000U +#define MDM_SYNCH_ALT__FREQ_FORCED_VALUE__READ(src) \ + (((uint32_t)(src)\ + & 0x0fff8000U) >> 15) +#define MDM_SYNCH_ALT__FREQ_FORCED_VALUE__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x0fff8000U) +#define MDM_SYNCH_ALT__FREQ_FORCED_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fff8000U) | (((uint32_t)(src) <<\ + 15) & 0x0fff8000U) +#define MDM_SYNCH_ALT__FREQ_FORCED_VALUE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x0fff8000U))) +#define MDM_SYNCH_ALT__FREQ_FORCED_VALUE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rst_freq_no_gain_change_pwrstep */ +/** + * @defgroup mdm_regs_core_rst_freq_no_gain_change_pwrstep_field rst_freq_no_gain_change_pwrstep_field + * @brief macros for field rst_freq_no_gain_change_pwrstep + * @details Allow (unlimited) assert_reset_freq_sync due to power step within a MEASURE state, with no gain change + * @{ + */ +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_PWRSTEP__SHIFT 28 +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_PWRSTEP__WIDTH 1 +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_PWRSTEP__MASK 0x10000000U +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_PWRSTEP__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_PWRSTEP__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_PWRSTEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_PWRSTEP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_PWRSTEP__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_PWRSTEP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_PWRSTEP__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field rst_freq_no_gain_change_rfin */ +/** + * @defgroup mdm_regs_core_rst_freq_no_gain_change_rfin_field rst_freq_no_gain_change_rfin_field + * @brief macros for field rst_freq_no_gain_change_rfin + * @details Allow one assert_reset_freq_sync due to rfin peak within a MEASURE state, with no gain change + * @{ + */ +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_RFIN__SHIFT 29 +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_RFIN__WIDTH 1 +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_RFIN__MASK 0x20000000U +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_RFIN__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_RFIN__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_RFIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_RFIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_RFIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_RFIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_RFIN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field rst_freq_no_gain_change_tia */ +/** + * @defgroup mdm_regs_core_rst_freq_no_gain_change_tia_field rst_freq_no_gain_change_tia_field + * @brief macros for field rst_freq_no_gain_change_tia + * @details Allow one assert_reset_freq_sync due to tia peak within a MEASURE state, with no gain change + * @{ + */ +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_TIA__SHIFT 30 +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_TIA__WIDTH 1 +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_TIA__MASK 0x40000000U +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_TIA__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_TIA__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_TIA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_TIA__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_TIA__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_TIA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_TIA__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field rst_freq_no_gain_change_sat */ +/** + * @defgroup mdm_regs_core_rst_freq_no_gain_change_sat_field rst_freq_no_gain_change_sat_field + * @brief macros for field rst_freq_no_gain_change_sat + * @details Allow one assert_reset_freq_sync due to adc sat within a MEASURE state, with no gain change + * @{ + */ +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_SAT__SHIFT 31 +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_SAT__WIDTH 1 +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_SAT__MASK 0x80000000U +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_SAT__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_SAT__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_SAT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_SAT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_SAT__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_SAT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_SYNCH_ALT__RST_FREQ_NO_GAIN_CHANGE_SAT__RESET_VALUE 0x00000001U +/** @} */ +#define MDM_SYNCH_ALT__TYPE uint32_t +#define MDM_SYNCH_ALT__READ 0xfffffffcU +#define MDM_SYNCH_ALT__WRITE 0xfffffffcU +#define MDM_SYNCH_ALT__PRESERVED 0x00000000U +#define MDM_SYNCH_ALT__RESET_VALUE 0xf0003194U + +#endif /* __MDM_SYNCH_ALT_MACRO__ */ + +/** @} end of synch_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_timetrack */ +/** + * @defgroup mdm_regs_core_timetrack timetrack + * @brief Specifies gears for time tracking definitions. + * @{ + */ +#ifndef __MDM_TIMETRACK_MACRO__ +#define __MDM_TIMETRACK_MACRO__ + +/* macros for field byte_count */ +/** + * @defgroup mdm_regs_core_byte_count_field byte_count_field + * @brief macros for field byte_count + * @details Number of bytes to process before switching from gear 1 to gear 2 + * @{ + */ +#define MDM_TIMETRACK__BYTE_COUNT__SHIFT 0 +#define MDM_TIMETRACK__BYTE_COUNT__WIDTH 8 +#define MDM_TIMETRACK__BYTE_COUNT__MASK 0x000000ffU +#define MDM_TIMETRACK__BYTE_COUNT__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_TIMETRACK__BYTE_COUNT__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_TIMETRACK__BYTE_COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_TIMETRACK__BYTE_COUNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define MDM_TIMETRACK__BYTE_COUNT__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field byte_count2 */ +/** + * @defgroup mdm_regs_core_byte_count2_field byte_count2_field + * @brief macros for field byte_count2 + * @details Number of bytes to process before switching to gear 3. (Includes bytes from gear 1 PLUS gear 2) + * @{ + */ +#define MDM_TIMETRACK__BYTE_COUNT2__SHIFT 8 +#define MDM_TIMETRACK__BYTE_COUNT2__WIDTH 8 +#define MDM_TIMETRACK__BYTE_COUNT2__MASK 0x0000ff00U +#define MDM_TIMETRACK__BYTE_COUNT2__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_TIMETRACK__BYTE_COUNT2__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define MDM_TIMETRACK__BYTE_COUNT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MDM_TIMETRACK__BYTE_COUNT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define MDM_TIMETRACK__BYTE_COUNT2__RESET_VALUE 0x00000002U +/** @} */ +#define MDM_TIMETRACK__TYPE uint32_t +#define MDM_TIMETRACK__READ 0x0000ffffU +#define MDM_TIMETRACK__WRITE 0x0000ffffU +#define MDM_TIMETRACK__PRESERVED 0x00000000U +#define MDM_TIMETRACK__RESET_VALUE 0x00000201U + +#endif /* __MDM_TIMETRACK_MACRO__ */ + +/** @} end of timetrack */ + +/* macros for BlueprintGlobalNameSpace::MDM_timesync */ +/** + * @defgroup mdm_regs_core_timesync timesync + * @brief Time sync RSSI and absolute difference thresholds definitions. + * @{ + */ +#ifndef __MDM_TIMESYNC_MACRO__ +#define __MDM_TIMESYNC_MACRO__ + +/* macros for field rssi_thr */ +/** + * @defgroup mdm_regs_core_rssi_thr_field rssi_thr_field + * @brief macros for field rssi_thr + * @details Ignore min_thr checks if rssi <= rssi_thr. 8'd168 = -88 + * @{ + */ +#define MDM_TIMESYNC__RSSI_THR__SHIFT 0 +#define MDM_TIMESYNC__RSSI_THR__WIDTH 8 +#define MDM_TIMESYNC__RSSI_THR__MASK 0x000000ffU +#define MDM_TIMESYNC__RSSI_THR__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_TIMESYNC__RSSI_THR__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_TIMESYNC__RSSI_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_TIMESYNC__RSSI_THR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define MDM_TIMESYNC__RSSI_THR__RESET_VALUE 0x000000a8U +/** @} */ + +/* macros for field corr_tmg_adj */ +/** + * @defgroup mdm_regs_core_corr_tmg_adj_field corr_tmg_adj_field + * @brief macros for field corr_tmg_adj + * @details When FFE is enabled post AA detection, amount of timing adjustment (range is [-8, 7]) + * @{ + */ +#define MDM_TIMESYNC__CORR_TMG_ADJ__SHIFT 8 +#define MDM_TIMESYNC__CORR_TMG_ADJ__WIDTH 4 +#define MDM_TIMESYNC__CORR_TMG_ADJ__MASK 0x00000f00U +#define MDM_TIMESYNC__CORR_TMG_ADJ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000f00U) >> 8) +#define MDM_TIMESYNC__CORR_TMG_ADJ__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000f00U) +#define MDM_TIMESYNC__CORR_TMG_ADJ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((uint32_t)(src) <<\ + 8) & 0x00000f00U) +#define MDM_TIMESYNC__CORR_TMG_ADJ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000f00U))) +#define MDM_TIMESYNC__CORR_TMG_ADJ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field twomeg_corr_tmg_adj */ +/** + * @defgroup mdm_regs_core_twomeg_corr_tmg_adj_field twomeg_corr_tmg_adj_field + * @brief macros for field twomeg_corr_tmg_adj + * @details When FFE is enabled post AA detection, amount of timing adjustment (range is [-8, 7]) + * @{ + */ +#define MDM_TIMESYNC__TWOMEG_CORR_TMG_ADJ__SHIFT 12 +#define MDM_TIMESYNC__TWOMEG_CORR_TMG_ADJ__WIDTH 4 +#define MDM_TIMESYNC__TWOMEG_CORR_TMG_ADJ__MASK 0x0000f000U +#define MDM_TIMESYNC__TWOMEG_CORR_TMG_ADJ__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f000U) >> 12) +#define MDM_TIMESYNC__TWOMEG_CORR_TMG_ADJ__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0000f000U) +#define MDM_TIMESYNC__TWOMEG_CORR_TMG_ADJ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((uint32_t)(src) <<\ + 12) & 0x0000f000U) +#define MDM_TIMESYNC__TWOMEG_CORR_TMG_ADJ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0000f000U))) +#define MDM_TIMESYNC__TWOMEG_CORR_TMG_ADJ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field coded_min_thr */ +/** + * @defgroup mdm_regs_core_coded_min_thr_field coded_min_thr_field + * @brief macros for field coded_min_thr + * @details Minimum absolute difference for coded rates + * @{ + */ +#define MDM_TIMESYNC__CODED_MIN_THR__SHIFT 24 +#define MDM_TIMESYNC__CODED_MIN_THR__WIDTH 8 +#define MDM_TIMESYNC__CODED_MIN_THR__MASK 0xff000000U +#define MDM_TIMESYNC__CODED_MIN_THR__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define MDM_TIMESYNC__CODED_MIN_THR__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define MDM_TIMESYNC__CODED_MIN_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define MDM_TIMESYNC__CODED_MIN_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define MDM_TIMESYNC__CODED_MIN_THR__RESET_VALUE 0x00000096U +/** @} */ +#define MDM_TIMESYNC__TYPE uint32_t +#define MDM_TIMESYNC__READ 0xff00ffffU +#define MDM_TIMESYNC__WRITE 0xff00ffffU +#define MDM_TIMESYNC__PRESERVED 0x00000000U +#define MDM_TIMESYNC__RESET_VALUE 0x960000a8U + +#endif /* __MDM_TIMESYNC_MACRO__ */ + +/** @} end of timesync */ + +/* macros for BlueprintGlobalNameSpace::MDM_timesync_alt */ +/** + * @defgroup mdm_regs_core_timesync_alt timesync_alt + * @brief Time sync RSSI and absolute difference thresholds, alternate set definitions. + * @{ + */ +#ifndef __MDM_TIMESYNC_ALT_MACRO__ +#define __MDM_TIMESYNC_ALT_MACRO__ + +/* macros for field rssi_thr */ +/** + * @defgroup mdm_regs_core_rssi_thr_field rssi_thr_field + * @brief macros for field rssi_thr + * @details Ignore min_thr checks if rssi <= rssi_thr. 8'd168 = -88 + * @{ + */ +#define MDM_TIMESYNC_ALT__RSSI_THR__SHIFT 0 +#define MDM_TIMESYNC_ALT__RSSI_THR__WIDTH 8 +#define MDM_TIMESYNC_ALT__RSSI_THR__MASK 0x000000ffU +#define MDM_TIMESYNC_ALT__RSSI_THR__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_TIMESYNC_ALT__RSSI_THR__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_TIMESYNC_ALT__RSSI_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_TIMESYNC_ALT__RSSI_THR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define MDM_TIMESYNC_ALT__RSSI_THR__RESET_VALUE 0x000000a8U +/** @} */ + +/* macros for field corr_tmg_adj */ +/** + * @defgroup mdm_regs_core_corr_tmg_adj_field corr_tmg_adj_field + * @brief macros for field corr_tmg_adj + * @details When FFE is enabled post AA detection, amount of timing adjustment (range is [-8, 7]) + * @{ + */ +#define MDM_TIMESYNC_ALT__CORR_TMG_ADJ__SHIFT 8 +#define MDM_TIMESYNC_ALT__CORR_TMG_ADJ__WIDTH 4 +#define MDM_TIMESYNC_ALT__CORR_TMG_ADJ__MASK 0x00000f00U +#define MDM_TIMESYNC_ALT__CORR_TMG_ADJ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000f00U) >> 8) +#define MDM_TIMESYNC_ALT__CORR_TMG_ADJ__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000f00U) +#define MDM_TIMESYNC_ALT__CORR_TMG_ADJ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((uint32_t)(src) <<\ + 8) & 0x00000f00U) +#define MDM_TIMESYNC_ALT__CORR_TMG_ADJ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000f00U))) +#define MDM_TIMESYNC_ALT__CORR_TMG_ADJ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field twomeg_corr_tmg_adj */ +/** + * @defgroup mdm_regs_core_twomeg_corr_tmg_adj_field twomeg_corr_tmg_adj_field + * @brief macros for field twomeg_corr_tmg_adj + * @details When FFE is enabled post AA detection, amount of timing adjustment (range is [-8, 7]) + * @{ + */ +#define MDM_TIMESYNC_ALT__TWOMEG_CORR_TMG_ADJ__SHIFT 12 +#define MDM_TIMESYNC_ALT__TWOMEG_CORR_TMG_ADJ__WIDTH 4 +#define MDM_TIMESYNC_ALT__TWOMEG_CORR_TMG_ADJ__MASK 0x0000f000U +#define MDM_TIMESYNC_ALT__TWOMEG_CORR_TMG_ADJ__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f000U) >> 12) +#define MDM_TIMESYNC_ALT__TWOMEG_CORR_TMG_ADJ__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0000f000U) +#define MDM_TIMESYNC_ALT__TWOMEG_CORR_TMG_ADJ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((uint32_t)(src) <<\ + 12) & 0x0000f000U) +#define MDM_TIMESYNC_ALT__TWOMEG_CORR_TMG_ADJ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0000f000U))) +#define MDM_TIMESYNC_ALT__TWOMEG_CORR_TMG_ADJ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field coded_min_thr */ +/** + * @defgroup mdm_regs_core_coded_min_thr_field coded_min_thr_field + * @brief macros for field coded_min_thr + * @details Minimum absolute difference for coded rates + * @{ + */ +#define MDM_TIMESYNC_ALT__CODED_MIN_THR__SHIFT 24 +#define MDM_TIMESYNC_ALT__CODED_MIN_THR__WIDTH 8 +#define MDM_TIMESYNC_ALT__CODED_MIN_THR__MASK 0xff000000U +#define MDM_TIMESYNC_ALT__CODED_MIN_THR__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define MDM_TIMESYNC_ALT__CODED_MIN_THR__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define MDM_TIMESYNC_ALT__CODED_MIN_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define MDM_TIMESYNC_ALT__CODED_MIN_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define MDM_TIMESYNC_ALT__CODED_MIN_THR__RESET_VALUE 0x00000096U +/** @} */ +#define MDM_TIMESYNC_ALT__TYPE uint32_t +#define MDM_TIMESYNC_ALT__READ 0xff00ffffU +#define MDM_TIMESYNC_ALT__WRITE 0xff00ffffU +#define MDM_TIMESYNC_ALT__PRESERVED 0x00000000U +#define MDM_TIMESYNC_ALT__RESET_VALUE 0x960000a8U + +#endif /* __MDM_TIMESYNC_ALT_MACRO__ */ + +/** @} end of timesync_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_syncdemod */ +/** + * @defgroup mdm_regs_core_syncdemod syncdemod + * @brief Additional sync/demod controls definitions. + * @{ + */ +#ifndef __MDM_SYNCDEMOD_MACRO__ +#define __MDM_SYNCDEMOD_MACRO__ + +/* macros for field coded_find_two_peaks */ +/** + * @defgroup mdm_regs_core_coded_find_two_peaks_field coded_find_two_peaks_field + * @brief macros for field coded_find_two_peaks + * @details For timing sync, coded with 2x or 4x averaging, require best absolute difference from last 4 us window and absolute difference from first 4 us window (using best timing index from last window) to exceed threshold. Coded version. + * @{ + */ +#define MDM_SYNCDEMOD__CODED_FIND_TWO_PEAKS__SHIFT 0 +#define MDM_SYNCDEMOD__CODED_FIND_TWO_PEAKS__WIDTH 1 +#define MDM_SYNCDEMOD__CODED_FIND_TWO_PEAKS__MASK 0x00000001U +#define MDM_SYNCDEMOD__CODED_FIND_TWO_PEAKS__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define MDM_SYNCDEMOD__CODED_FIND_TWO_PEAKS__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define MDM_SYNCDEMOD__CODED_FIND_TWO_PEAKS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define MDM_SYNCDEMOD__CODED_FIND_TWO_PEAKS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define MDM_SYNCDEMOD__CODED_FIND_TWO_PEAKS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_SYNCDEMOD__CODED_FIND_TWO_PEAKS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_SYNCDEMOD__CODED_FIND_TWO_PEAKS__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field freqwin1 */ +/** + * @defgroup mdm_regs_core_freqwin1_field freqwin1_field + * @brief macros for field freqwin1 + * @details Uncoded freqsync window length, default case Encoding in number of symbols 3'd0->2, 3'd1->2.5, 3'd2->3, 3'd3->3.5, 3'd4->4.0 + * @{ + */ +#define MDM_SYNCDEMOD__FREQWIN1__SHIFT 1 +#define MDM_SYNCDEMOD__FREQWIN1__WIDTH 3 +#define MDM_SYNCDEMOD__FREQWIN1__MASK 0x0000000eU +#define MDM_SYNCDEMOD__FREQWIN1__READ(src) \ + (((uint32_t)(src)\ + & 0x0000000eU) >> 1) +#define MDM_SYNCDEMOD__FREQWIN1__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x0000000eU) +#define MDM_SYNCDEMOD__FREQWIN1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((uint32_t)(src) <<\ + 1) & 0x0000000eU) +#define MDM_SYNCDEMOD__FREQWIN1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x0000000eU))) +#define MDM_SYNCDEMOD__FREQWIN1__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field freqwin2 */ +/** + * @defgroup mdm_regs_core_freqwin2_field freqwin2_field + * @brief macros for field freqwin2 + * @details After back-to-back peak/sat and sat + * @{ + */ +#define MDM_SYNCDEMOD__FREQWIN2__SHIFT 4 +#define MDM_SYNCDEMOD__FREQWIN2__WIDTH 3 +#define MDM_SYNCDEMOD__FREQWIN2__MASK 0x00000070U +#define MDM_SYNCDEMOD__FREQWIN2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000070U) >> 4) +#define MDM_SYNCDEMOD__FREQWIN2__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000070U) +#define MDM_SYNCDEMOD__FREQWIN2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((uint32_t)(src) <<\ + 4) & 0x00000070U) +#define MDM_SYNCDEMOD__FREQWIN2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000070U))) +#define MDM_SYNCDEMOD__FREQWIN2__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field freqwin3 */ +/** + * @defgroup mdm_regs_core_freqwin3_field freqwin3_field + * @brief macros for field freqwin3 + * @details Power step, no gain change + * @{ + */ +#define MDM_SYNCDEMOD__FREQWIN3__SHIFT 7 +#define MDM_SYNCDEMOD__FREQWIN3__WIDTH 3 +#define MDM_SYNCDEMOD__FREQWIN3__MASK 0x00000380U +#define MDM_SYNCDEMOD__FREQWIN3__READ(src) \ + (((uint32_t)(src)\ + & 0x00000380U) >> 7) +#define MDM_SYNCDEMOD__FREQWIN3__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000380U) +#define MDM_SYNCDEMOD__FREQWIN3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000380U) | (((uint32_t)(src) <<\ + 7) & 0x00000380U) +#define MDM_SYNCDEMOD__FREQWIN3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000380U))) +#define MDM_SYNCDEMOD__FREQWIN3__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field twomeg_freqwin1 */ +/** + * @defgroup mdm_regs_core_twomeg_freqwin1_field twomeg_freqwin1_field + * @brief macros for field twomeg_freqwin1 + * @details Uncoded freqsync window length, default case Encoding in number of symbols 3'd0->2, 3'd1->2.5, 3'd2->3, 3'd3->3.5, 3'd4->4.0. 2M rate + * @{ + */ +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN1__SHIFT 10 +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN1__WIDTH 3 +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN1__MASK 0x00001c00U +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN1__READ(src) \ + (((uint32_t)(src)\ + & 0x00001c00U) >> 10) +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN1__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00001c00U) +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001c00U) | (((uint32_t)(src) <<\ + 10) & 0x00001c00U) +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00001c00U))) +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN1__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field twomeg_freqwin2 */ +/** + * @defgroup mdm_regs_core_twomeg_freqwin2_field twomeg_freqwin2_field + * @brief macros for field twomeg_freqwin2 + * @details After back-to-back peak/sat and sat. 2M rate + * @{ + */ +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN2__SHIFT 13 +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN2__WIDTH 3 +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN2__MASK 0x0000e000U +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN2__READ(src) \ + (((uint32_t)(src)\ + & 0x0000e000U) >> 13) +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN2__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0000e000U) +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((uint32_t)(src) <<\ + 13) & 0x0000e000U) +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0000e000U))) +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN2__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field twomeg_freqwin3 */ +/** + * @defgroup mdm_regs_core_twomeg_freqwin3_field twomeg_freqwin3_field + * @brief macros for field twomeg_freqwin3 + * @details Power step, no gain change. 2M rate + * @{ + */ +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN3__SHIFT 16 +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN3__WIDTH 3 +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN3__MASK 0x00070000U +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN3__READ(src) \ + (((uint32_t)(src)\ + & 0x00070000U) >> 16) +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN3__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00070000U) +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((uint32_t)(src) <<\ + 16) & 0x00070000U) +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00070000U))) +#define MDM_SYNCDEMOD__TWOMEG_FREQWIN3__RESET_VALUE 0x00000004U +/** @} */ +#define MDM_SYNCDEMOD__TYPE uint32_t +#define MDM_SYNCDEMOD__READ 0x0007ffffU +#define MDM_SYNCDEMOD__WRITE 0x0007ffffU +#define MDM_SYNCDEMOD__PRESERVED 0x00000000U +#define MDM_SYNCDEMOD__RESET_VALUE 0x00042a15U + +#endif /* __MDM_SYNCDEMOD_MACRO__ */ + +/** @} end of syncdemod */ + +/* macros for BlueprintGlobalNameSpace::MDM_syncdemod_alt */ +/** + * @defgroup mdm_regs_core_syncdemod_alt syncdemod_alt + * @brief Additional sync/demod controls, alternate set definitions. + * @{ + */ +#ifndef __MDM_SYNCDEMOD_ALT_MACRO__ +#define __MDM_SYNCDEMOD_ALT_MACRO__ + +/* macros for field coded_find_two_peaks */ +/** + * @defgroup mdm_regs_core_coded_find_two_peaks_field coded_find_two_peaks_field + * @brief macros for field coded_find_two_peaks + * @details For timing sync, coded with 2x or 4x averaging, require best absolute difference from last 4 us window and absolute difference from first 4 us window (using best timing index from last window) to exceed threshold. Coded version. + * @{ + */ +#define MDM_SYNCDEMOD_ALT__CODED_FIND_TWO_PEAKS__SHIFT 0 +#define MDM_SYNCDEMOD_ALT__CODED_FIND_TWO_PEAKS__WIDTH 1 +#define MDM_SYNCDEMOD_ALT__CODED_FIND_TWO_PEAKS__MASK 0x00000001U +#define MDM_SYNCDEMOD_ALT__CODED_FIND_TWO_PEAKS__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define MDM_SYNCDEMOD_ALT__CODED_FIND_TWO_PEAKS__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define MDM_SYNCDEMOD_ALT__CODED_FIND_TWO_PEAKS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define MDM_SYNCDEMOD_ALT__CODED_FIND_TWO_PEAKS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define MDM_SYNCDEMOD_ALT__CODED_FIND_TWO_PEAKS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_SYNCDEMOD_ALT__CODED_FIND_TWO_PEAKS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_SYNCDEMOD_ALT__CODED_FIND_TWO_PEAKS__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field freqwin1 */ +/** + * @defgroup mdm_regs_core_freqwin1_field freqwin1_field + * @brief macros for field freqwin1 + * @details Uncoded freqsync window length, default case Encoding in number of symbols 3'd0->2, 3'd1->2.5, 3'd2->3, 3'd3->3.5, 3'd4->4.0 + * @{ + */ +#define MDM_SYNCDEMOD_ALT__FREQWIN1__SHIFT 1 +#define MDM_SYNCDEMOD_ALT__FREQWIN1__WIDTH 3 +#define MDM_SYNCDEMOD_ALT__FREQWIN1__MASK 0x0000000eU +#define MDM_SYNCDEMOD_ALT__FREQWIN1__READ(src) \ + (((uint32_t)(src)\ + & 0x0000000eU) >> 1) +#define MDM_SYNCDEMOD_ALT__FREQWIN1__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x0000000eU) +#define MDM_SYNCDEMOD_ALT__FREQWIN1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((uint32_t)(src) <<\ + 1) & 0x0000000eU) +#define MDM_SYNCDEMOD_ALT__FREQWIN1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x0000000eU))) +#define MDM_SYNCDEMOD_ALT__FREQWIN1__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field freqwin2 */ +/** + * @defgroup mdm_regs_core_freqwin2_field freqwin2_field + * @brief macros for field freqwin2 + * @details After back-to-back peak/sat and sat + * @{ + */ +#define MDM_SYNCDEMOD_ALT__FREQWIN2__SHIFT 4 +#define MDM_SYNCDEMOD_ALT__FREQWIN2__WIDTH 3 +#define MDM_SYNCDEMOD_ALT__FREQWIN2__MASK 0x00000070U +#define MDM_SYNCDEMOD_ALT__FREQWIN2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000070U) >> 4) +#define MDM_SYNCDEMOD_ALT__FREQWIN2__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000070U) +#define MDM_SYNCDEMOD_ALT__FREQWIN2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((uint32_t)(src) <<\ + 4) & 0x00000070U) +#define MDM_SYNCDEMOD_ALT__FREQWIN2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000070U))) +#define MDM_SYNCDEMOD_ALT__FREQWIN2__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field freqwin3 */ +/** + * @defgroup mdm_regs_core_freqwin3_field freqwin3_field + * @brief macros for field freqwin3 + * @details Power step, no gain change + * @{ + */ +#define MDM_SYNCDEMOD_ALT__FREQWIN3__SHIFT 7 +#define MDM_SYNCDEMOD_ALT__FREQWIN3__WIDTH 3 +#define MDM_SYNCDEMOD_ALT__FREQWIN3__MASK 0x00000380U +#define MDM_SYNCDEMOD_ALT__FREQWIN3__READ(src) \ + (((uint32_t)(src)\ + & 0x00000380U) >> 7) +#define MDM_SYNCDEMOD_ALT__FREQWIN3__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000380U) +#define MDM_SYNCDEMOD_ALT__FREQWIN3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000380U) | (((uint32_t)(src) <<\ + 7) & 0x00000380U) +#define MDM_SYNCDEMOD_ALT__FREQWIN3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000380U))) +#define MDM_SYNCDEMOD_ALT__FREQWIN3__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field twomeg_freqwin1 */ +/** + * @defgroup mdm_regs_core_twomeg_freqwin1_field twomeg_freqwin1_field + * @brief macros for field twomeg_freqwin1 + * @details Uncoded freqsync window length, default case Encoding in number of symbols 3'd0->2, 3'd1->2.5, 3'd2->3, 3'd3->3.5, 3'd4->4.0. 2M rate + * @{ + */ +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN1__SHIFT 10 +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN1__WIDTH 3 +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN1__MASK 0x00001c00U +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN1__READ(src) \ + (((uint32_t)(src)\ + & 0x00001c00U) >> 10) +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN1__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00001c00U) +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001c00U) | (((uint32_t)(src) <<\ + 10) & 0x00001c00U) +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00001c00U))) +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN1__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field twomeg_freqwin2 */ +/** + * @defgroup mdm_regs_core_twomeg_freqwin2_field twomeg_freqwin2_field + * @brief macros for field twomeg_freqwin2 + * @details After back-to-back peak/sat and sat. 2M rate + * @{ + */ +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN2__SHIFT 13 +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN2__WIDTH 3 +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN2__MASK 0x0000e000U +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN2__READ(src) \ + (((uint32_t)(src)\ + & 0x0000e000U) >> 13) +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN2__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0000e000U) +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((uint32_t)(src) <<\ + 13) & 0x0000e000U) +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0000e000U))) +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN2__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field twomeg_freqwin3 */ +/** + * @defgroup mdm_regs_core_twomeg_freqwin3_field twomeg_freqwin3_field + * @brief macros for field twomeg_freqwin3 + * @details Power step, no gain change. 2M rate + * @{ + */ +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN3__SHIFT 16 +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN3__WIDTH 3 +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN3__MASK 0x00070000U +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN3__READ(src) \ + (((uint32_t)(src)\ + & 0x00070000U) >> 16) +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN3__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00070000U) +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((uint32_t)(src) <<\ + 16) & 0x00070000U) +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00070000U))) +#define MDM_SYNCDEMOD_ALT__TWOMEG_FREQWIN3__RESET_VALUE 0x00000004U +/** @} */ +#define MDM_SYNCDEMOD_ALT__TYPE uint32_t +#define MDM_SYNCDEMOD_ALT__READ 0x0007ffffU +#define MDM_SYNCDEMOD_ALT__WRITE 0x0007ffffU +#define MDM_SYNCDEMOD_ALT__PRESERVED 0x00000000U +#define MDM_SYNCDEMOD_ALT__RESET_VALUE 0x00042a15U + +#endif /* __MDM_SYNCDEMOD_ALT_MACRO__ */ + +/** @} end of syncdemod_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_resetinitcfo */ +/** + * @defgroup mdm_regs_core_resetinitcfo resetinitcfo + * @brief Control for resetting initial CFO estimate, uncoded only definitions. + * @{ + */ +#ifndef __MDM_RESETINITCFO_MACRO__ +#define __MDM_RESETINITCFO_MACRO__ + +/* macros for field en */ +/** + * @defgroup mdm_regs_core_en_field en_field + * @brief macros for field en + * @details Enable for run-length based reset of one-shot CFO estimation + * @{ + */ +#define MDM_RESETINITCFO__EN__SHIFT 0 +#define MDM_RESETINITCFO__EN__WIDTH 1 +#define MDM_RESETINITCFO__EN__MASK 0x00000001U +#define MDM_RESETINITCFO__EN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_RESETINITCFO__EN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_RESETINITCFO__EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define MDM_RESETINITCFO__EN__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define MDM_RESETINITCFO__EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_RESETINITCFO__EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_RESETINITCFO__EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field runlen_updt_thr */ +/** + * @defgroup mdm_regs_core_runlen_updt_thr_field runlen_updt_thr_field + * @brief macros for field runlen_updt_thr + * @details Threshold for abs(diff(MF out)) below which the run-length is incremented + * @{ + */ +#define MDM_RESETINITCFO__RUNLEN_UPDT_THR__SHIFT 1 +#define MDM_RESETINITCFO__RUNLEN_UPDT_THR__WIDTH 6 +#define MDM_RESETINITCFO__RUNLEN_UPDT_THR__MASK 0x0000007eU +#define MDM_RESETINITCFO__RUNLEN_UPDT_THR__READ(src) \ + (((uint32_t)(src)\ + & 0x0000007eU) >> 1) +#define MDM_RESETINITCFO__RUNLEN_UPDT_THR__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x0000007eU) +#define MDM_RESETINITCFO__RUNLEN_UPDT_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007eU) | (((uint32_t)(src) <<\ + 1) & 0x0000007eU) +#define MDM_RESETINITCFO__RUNLEN_UPDT_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x0000007eU))) +#define MDM_RESETINITCFO__RUNLEN_UPDT_THR__RESET_VALUE 0x00000016U +/** @} */ + +/* macros for field runlen_thr_to_reset_cfo */ +/** + * @defgroup mdm_regs_core_runlen_thr_to_reset_cfo_field runlen_thr_to_reset_cfo_field + * @brief macros for field runlen_thr_to_reset_cfo + * @details Threshold for run-length above which assert_reset_freq_sync is asserted + * @{ + */ +#define MDM_RESETINITCFO__RUNLEN_THR_TO_RESET_CFO__SHIFT 7 +#define MDM_RESETINITCFO__RUNLEN_THR_TO_RESET_CFO__WIDTH 6 +#define MDM_RESETINITCFO__RUNLEN_THR_TO_RESET_CFO__MASK 0x00001f80U +#define MDM_RESETINITCFO__RUNLEN_THR_TO_RESET_CFO__READ(src) \ + (((uint32_t)(src)\ + & 0x00001f80U) >> 7) +#define MDM_RESETINITCFO__RUNLEN_THR_TO_RESET_CFO__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00001f80U) +#define MDM_RESETINITCFO__RUNLEN_THR_TO_RESET_CFO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f80U) | (((uint32_t)(src) <<\ + 7) & 0x00001f80U) +#define MDM_RESETINITCFO__RUNLEN_THR_TO_RESET_CFO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00001f80U))) +#define MDM_RESETINITCFO__RUNLEN_THR_TO_RESET_CFO__RESET_VALUE 0x0000000fU +/** @} */ + +/* macros for field use_twosamples_to_updt_runlen */ +/** + * @defgroup mdm_regs_core_use_twosamples_to_updt_runlen_field use_twosamples_to_updt_runlen_field + * @brief macros for field use_twosamples_to_updt_runlen + * @details When 1, use OR of two most recent abs(diff(MF out)). When 0, use just most recent + * @{ + */ +#define MDM_RESETINITCFO__USE_TWOSAMPLES_TO_UPDT_RUNLEN__SHIFT 13 +#define MDM_RESETINITCFO__USE_TWOSAMPLES_TO_UPDT_RUNLEN__WIDTH 1 +#define MDM_RESETINITCFO__USE_TWOSAMPLES_TO_UPDT_RUNLEN__MASK 0x00002000U +#define MDM_RESETINITCFO__USE_TWOSAMPLES_TO_UPDT_RUNLEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define MDM_RESETINITCFO__USE_TWOSAMPLES_TO_UPDT_RUNLEN__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define MDM_RESETINITCFO__USE_TWOSAMPLES_TO_UPDT_RUNLEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define MDM_RESETINITCFO__USE_TWOSAMPLES_TO_UPDT_RUNLEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define MDM_RESETINITCFO__USE_TWOSAMPLES_TO_UPDT_RUNLEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define MDM_RESETINITCFO__USE_TWOSAMPLES_TO_UPDT_RUNLEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define MDM_RESETINITCFO__USE_TWOSAMPLES_TO_UPDT_RUNLEN__RESET_VALUE \ + 0x00000001U +/** @} */ + +/* macros for field reset_runlen_on_gainchg_pwrstep_only */ +/** + * @defgroup mdm_regs_core_reset_runlen_on_gainchg_pwrstep_only_field reset_runlen_on_gainchg_pwrstep_only_field + * @brief macros for field reset_runlen_on_gainchg_pwrstep_only + * @details When 1, don't reset run length counter if only run length triggered assert_reset_freq_sync + * @{ + */ +#define MDM_RESETINITCFO__RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__SHIFT 14 +#define MDM_RESETINITCFO__RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__WIDTH 1 +#define MDM_RESETINITCFO__RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__MASK \ + 0x00004000U +#define MDM_RESETINITCFO__RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define MDM_RESETINITCFO__RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define MDM_RESETINITCFO__RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define MDM_RESETINITCFO__RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define MDM_RESETINITCFO__RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define MDM_RESETINITCFO__RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define MDM_RESETINITCFO__RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__RESET_VALUE \ + 0x00000001U +/** @} */ + +/* macros for field twomeg_en */ +/** + * @defgroup mdm_regs_core_twomeg_en_field twomeg_en_field + * @brief macros for field twomeg_en + * @details Enable for run-length based reset of one-shot CFO estimation, 2M version + * @{ + */ +#define MDM_RESETINITCFO__TWOMEG_EN__SHIFT 16 +#define MDM_RESETINITCFO__TWOMEG_EN__WIDTH 1 +#define MDM_RESETINITCFO__TWOMEG_EN__MASK 0x00010000U +#define MDM_RESETINITCFO__TWOMEG_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define MDM_RESETINITCFO__TWOMEG_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define MDM_RESETINITCFO__TWOMEG_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define MDM_RESETINITCFO__TWOMEG_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define MDM_RESETINITCFO__TWOMEG_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define MDM_RESETINITCFO__TWOMEG_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define MDM_RESETINITCFO__TWOMEG_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field twomeg_runlen_updt_thr */ +/** + * @defgroup mdm_regs_core_twomeg_runlen_updt_thr_field twomeg_runlen_updt_thr_field + * @brief macros for field twomeg_runlen_updt_thr + * @details Threshold for abs(diff(MF out)) below which the run-length is incremented, 2M version + * @{ + */ +#define MDM_RESETINITCFO__TWOMEG_RUNLEN_UPDT_THR__SHIFT 17 +#define MDM_RESETINITCFO__TWOMEG_RUNLEN_UPDT_THR__WIDTH 6 +#define MDM_RESETINITCFO__TWOMEG_RUNLEN_UPDT_THR__MASK 0x007e0000U +#define MDM_RESETINITCFO__TWOMEG_RUNLEN_UPDT_THR__READ(src) \ + (((uint32_t)(src)\ + & 0x007e0000U) >> 17) +#define MDM_RESETINITCFO__TWOMEG_RUNLEN_UPDT_THR__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x007e0000U) +#define MDM_RESETINITCFO__TWOMEG_RUNLEN_UPDT_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007e0000U) | (((uint32_t)(src) <<\ + 17) & 0x007e0000U) +#define MDM_RESETINITCFO__TWOMEG_RUNLEN_UPDT_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x007e0000U))) +#define MDM_RESETINITCFO__TWOMEG_RUNLEN_UPDT_THR__RESET_VALUE 0x00000016U +/** @} */ + +/* macros for field twomeg_runlen_thr_to_reset_cfo */ +/** + * @defgroup mdm_regs_core_twomeg_runlen_thr_to_reset_cfo_field twomeg_runlen_thr_to_reset_cfo_field + * @brief macros for field twomeg_runlen_thr_to_reset_cfo + * @details Threshold for run-length above which assert_reset_freq_sync is asserted, 2M version + * @{ + */ +#define MDM_RESETINITCFO__TWOMEG_RUNLEN_THR_TO_RESET_CFO__SHIFT 23 +#define MDM_RESETINITCFO__TWOMEG_RUNLEN_THR_TO_RESET_CFO__WIDTH 6 +#define MDM_RESETINITCFO__TWOMEG_RUNLEN_THR_TO_RESET_CFO__MASK 0x1f800000U +#define MDM_RESETINITCFO__TWOMEG_RUNLEN_THR_TO_RESET_CFO__READ(src) \ + (((uint32_t)(src)\ + & 0x1f800000U) >> 23) +#define MDM_RESETINITCFO__TWOMEG_RUNLEN_THR_TO_RESET_CFO__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x1f800000U) +#define MDM_RESETINITCFO__TWOMEG_RUNLEN_THR_TO_RESET_CFO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1f800000U) | (((uint32_t)(src) <<\ + 23) & 0x1f800000U) +#define MDM_RESETINITCFO__TWOMEG_RUNLEN_THR_TO_RESET_CFO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x1f800000U))) +#define MDM_RESETINITCFO__TWOMEG_RUNLEN_THR_TO_RESET_CFO__RESET_VALUE \ + 0x0000000fU +/** @} */ + +/* macros for field twomeg_use_twosamples_to_updt_runlen */ +/** + * @defgroup mdm_regs_core_twomeg_use_twosamples_to_updt_runlen_field twomeg_use_twosamples_to_updt_runlen_field + * @brief macros for field twomeg_use_twosamples_to_updt_runlen + * @details When 1, use OR of two most recent abs(diff(MF out)). When 0, use just most recent, 2M version + * @{ + */ +#define MDM_RESETINITCFO__TWOMEG_USE_TWOSAMPLES_TO_UPDT_RUNLEN__SHIFT 29 +#define MDM_RESETINITCFO__TWOMEG_USE_TWOSAMPLES_TO_UPDT_RUNLEN__WIDTH 1 +#define MDM_RESETINITCFO__TWOMEG_USE_TWOSAMPLES_TO_UPDT_RUNLEN__MASK \ + 0x20000000U +#define MDM_RESETINITCFO__TWOMEG_USE_TWOSAMPLES_TO_UPDT_RUNLEN__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define MDM_RESETINITCFO__TWOMEG_USE_TWOSAMPLES_TO_UPDT_RUNLEN__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define MDM_RESETINITCFO__TWOMEG_USE_TWOSAMPLES_TO_UPDT_RUNLEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define MDM_RESETINITCFO__TWOMEG_USE_TWOSAMPLES_TO_UPDT_RUNLEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define MDM_RESETINITCFO__TWOMEG_USE_TWOSAMPLES_TO_UPDT_RUNLEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define MDM_RESETINITCFO__TWOMEG_USE_TWOSAMPLES_TO_UPDT_RUNLEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define MDM_RESETINITCFO__TWOMEG_USE_TWOSAMPLES_TO_UPDT_RUNLEN__RESET_VALUE \ + 0x00000001U +/** @} */ + +/* macros for field twomeg_reset_runlen_on_gainchg_pwrstep_only */ +/** + * @defgroup mdm_regs_core_twomeg_reset_runlen_on_gainchg_pwrstep_only_field twomeg_reset_runlen_on_gainchg_pwrstep_only_field + * @brief macros for field twomeg_reset_runlen_on_gainchg_pwrstep_only + * @details When 1, don't reset run length counter if only run length triggered assert_reset_freq_sync, 2M version + * @{ + */ +#define MDM_RESETINITCFO__TWOMEG_RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__SHIFT 30 +#define MDM_RESETINITCFO__TWOMEG_RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__WIDTH 1 +#define MDM_RESETINITCFO__TWOMEG_RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__MASK \ + 0x40000000U +#define MDM_RESETINITCFO__TWOMEG_RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define MDM_RESETINITCFO__TWOMEG_RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define MDM_RESETINITCFO__TWOMEG_RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define MDM_RESETINITCFO__TWOMEG_RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define MDM_RESETINITCFO__TWOMEG_RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define MDM_RESETINITCFO__TWOMEG_RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define MDM_RESETINITCFO__TWOMEG_RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__RESET_VALUE \ + 0x00000001U +/** @} */ +#define MDM_RESETINITCFO__TYPE uint32_t +#define MDM_RESETINITCFO__READ 0x7fff7fffU +#define MDM_RESETINITCFO__WRITE 0x7fff7fffU +#define MDM_RESETINITCFO__PRESERVED 0x00000000U +#define MDM_RESETINITCFO__RESET_VALUE 0x67ac67acU + +#endif /* __MDM_RESETINITCFO_MACRO__ */ + +/** @} end of resetinitcfo */ + +/* macros for BlueprintGlobalNameSpace::MDM_resetinitcfo_alt */ +/** + * @defgroup mdm_regs_core_resetinitcfo_alt resetinitcfo_alt + * @brief Control for resetting initial CFO estimate, uncoded only, alternate set definitions. + * @{ + */ +#ifndef __MDM_RESETINITCFO_ALT_MACRO__ +#define __MDM_RESETINITCFO_ALT_MACRO__ + +/* macros for field en */ +/** + * @defgroup mdm_regs_core_en_field en_field + * @brief macros for field en + * @details Enable for run-length based reset of one-shot CFO estimation + * @{ + */ +#define MDM_RESETINITCFO_ALT__EN__SHIFT 0 +#define MDM_RESETINITCFO_ALT__EN__WIDTH 1 +#define MDM_RESETINITCFO_ALT__EN__MASK 0x00000001U +#define MDM_RESETINITCFO_ALT__EN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_RESETINITCFO_ALT__EN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_RESETINITCFO_ALT__EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define MDM_RESETINITCFO_ALT__EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define MDM_RESETINITCFO_ALT__EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_RESETINITCFO_ALT__EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_RESETINITCFO_ALT__EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field runlen_updt_thr */ +/** + * @defgroup mdm_regs_core_runlen_updt_thr_field runlen_updt_thr_field + * @brief macros for field runlen_updt_thr + * @details Threshold for abs(diff(MF out)) below which the run-length is incremented + * @{ + */ +#define MDM_RESETINITCFO_ALT__RUNLEN_UPDT_THR__SHIFT 1 +#define MDM_RESETINITCFO_ALT__RUNLEN_UPDT_THR__WIDTH 6 +#define MDM_RESETINITCFO_ALT__RUNLEN_UPDT_THR__MASK 0x0000007eU +#define MDM_RESETINITCFO_ALT__RUNLEN_UPDT_THR__READ(src) \ + (((uint32_t)(src)\ + & 0x0000007eU) >> 1) +#define MDM_RESETINITCFO_ALT__RUNLEN_UPDT_THR__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x0000007eU) +#define MDM_RESETINITCFO_ALT__RUNLEN_UPDT_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007eU) | (((uint32_t)(src) <<\ + 1) & 0x0000007eU) +#define MDM_RESETINITCFO_ALT__RUNLEN_UPDT_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x0000007eU))) +#define MDM_RESETINITCFO_ALT__RUNLEN_UPDT_THR__RESET_VALUE 0x00000016U +/** @} */ + +/* macros for field runlen_thr_to_reset_cfo */ +/** + * @defgroup mdm_regs_core_runlen_thr_to_reset_cfo_field runlen_thr_to_reset_cfo_field + * @brief macros for field runlen_thr_to_reset_cfo + * @details Threshold for run-length above which assert_reset_freq_sync is asserted + * @{ + */ +#define MDM_RESETINITCFO_ALT__RUNLEN_THR_TO_RESET_CFO__SHIFT 7 +#define MDM_RESETINITCFO_ALT__RUNLEN_THR_TO_RESET_CFO__WIDTH 6 +#define MDM_RESETINITCFO_ALT__RUNLEN_THR_TO_RESET_CFO__MASK 0x00001f80U +#define MDM_RESETINITCFO_ALT__RUNLEN_THR_TO_RESET_CFO__READ(src) \ + (((uint32_t)(src)\ + & 0x00001f80U) >> 7) +#define MDM_RESETINITCFO_ALT__RUNLEN_THR_TO_RESET_CFO__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00001f80U) +#define MDM_RESETINITCFO_ALT__RUNLEN_THR_TO_RESET_CFO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f80U) | (((uint32_t)(src) <<\ + 7) & 0x00001f80U) +#define MDM_RESETINITCFO_ALT__RUNLEN_THR_TO_RESET_CFO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00001f80U))) +#define MDM_RESETINITCFO_ALT__RUNLEN_THR_TO_RESET_CFO__RESET_VALUE 0x0000000fU +/** @} */ + +/* macros for field use_twosamples_to_updt_runlen */ +/** + * @defgroup mdm_regs_core_use_twosamples_to_updt_runlen_field use_twosamples_to_updt_runlen_field + * @brief macros for field use_twosamples_to_updt_runlen + * @details When 1, use OR of two most recent abs(diff(MF out)). When 0, use just most recent + * @{ + */ +#define MDM_RESETINITCFO_ALT__USE_TWOSAMPLES_TO_UPDT_RUNLEN__SHIFT 13 +#define MDM_RESETINITCFO_ALT__USE_TWOSAMPLES_TO_UPDT_RUNLEN__WIDTH 1 +#define MDM_RESETINITCFO_ALT__USE_TWOSAMPLES_TO_UPDT_RUNLEN__MASK 0x00002000U +#define MDM_RESETINITCFO_ALT__USE_TWOSAMPLES_TO_UPDT_RUNLEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define MDM_RESETINITCFO_ALT__USE_TWOSAMPLES_TO_UPDT_RUNLEN__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define MDM_RESETINITCFO_ALT__USE_TWOSAMPLES_TO_UPDT_RUNLEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define MDM_RESETINITCFO_ALT__USE_TWOSAMPLES_TO_UPDT_RUNLEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define MDM_RESETINITCFO_ALT__USE_TWOSAMPLES_TO_UPDT_RUNLEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define MDM_RESETINITCFO_ALT__USE_TWOSAMPLES_TO_UPDT_RUNLEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define MDM_RESETINITCFO_ALT__USE_TWOSAMPLES_TO_UPDT_RUNLEN__RESET_VALUE \ + 0x00000001U +/** @} */ + +/* macros for field reset_runlen_on_gainchg_pwrstep_only */ +/** + * @defgroup mdm_regs_core_reset_runlen_on_gainchg_pwrstep_only_field reset_runlen_on_gainchg_pwrstep_only_field + * @brief macros for field reset_runlen_on_gainchg_pwrstep_only + * @details When 1, don't reset run length counter if only run length triggered assert_reset_freq_sync + * @{ + */ +#define MDM_RESETINITCFO_ALT__RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__SHIFT 14 +#define MDM_RESETINITCFO_ALT__RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__WIDTH 1 +#define MDM_RESETINITCFO_ALT__RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__MASK \ + 0x00004000U +#define MDM_RESETINITCFO_ALT__RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define MDM_RESETINITCFO_ALT__RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define MDM_RESETINITCFO_ALT__RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define MDM_RESETINITCFO_ALT__RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define MDM_RESETINITCFO_ALT__RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define MDM_RESETINITCFO_ALT__RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define MDM_RESETINITCFO_ALT__RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__RESET_VALUE \ + 0x00000001U +/** @} */ + +/* macros for field twomeg_en */ +/** + * @defgroup mdm_regs_core_twomeg_en_field twomeg_en_field + * @brief macros for field twomeg_en + * @details Enable for run-length based reset of one-shot CFO estimation, 2M version + * @{ + */ +#define MDM_RESETINITCFO_ALT__TWOMEG_EN__SHIFT 16 +#define MDM_RESETINITCFO_ALT__TWOMEG_EN__WIDTH 1 +#define MDM_RESETINITCFO_ALT__TWOMEG_EN__MASK 0x00010000U +#define MDM_RESETINITCFO_ALT__TWOMEG_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define MDM_RESETINITCFO_ALT__TWOMEG_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define MDM_RESETINITCFO_ALT__TWOMEG_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define MDM_RESETINITCFO_ALT__TWOMEG_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define MDM_RESETINITCFO_ALT__TWOMEG_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define MDM_RESETINITCFO_ALT__TWOMEG_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define MDM_RESETINITCFO_ALT__TWOMEG_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field twomeg_runlen_updt_thr */ +/** + * @defgroup mdm_regs_core_twomeg_runlen_updt_thr_field twomeg_runlen_updt_thr_field + * @brief macros for field twomeg_runlen_updt_thr + * @details Threshold for abs(diff(MF out)) below which the run-length is incremented, 2M version + * @{ + */ +#define MDM_RESETINITCFO_ALT__TWOMEG_RUNLEN_UPDT_THR__SHIFT 17 +#define MDM_RESETINITCFO_ALT__TWOMEG_RUNLEN_UPDT_THR__WIDTH 6 +#define MDM_RESETINITCFO_ALT__TWOMEG_RUNLEN_UPDT_THR__MASK 0x007e0000U +#define MDM_RESETINITCFO_ALT__TWOMEG_RUNLEN_UPDT_THR__READ(src) \ + (((uint32_t)(src)\ + & 0x007e0000U) >> 17) +#define MDM_RESETINITCFO_ALT__TWOMEG_RUNLEN_UPDT_THR__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x007e0000U) +#define MDM_RESETINITCFO_ALT__TWOMEG_RUNLEN_UPDT_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007e0000U) | (((uint32_t)(src) <<\ + 17) & 0x007e0000U) +#define MDM_RESETINITCFO_ALT__TWOMEG_RUNLEN_UPDT_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x007e0000U))) +#define MDM_RESETINITCFO_ALT__TWOMEG_RUNLEN_UPDT_THR__RESET_VALUE 0x00000016U +/** @} */ + +/* macros for field twomeg_runlen_thr_to_reset_cfo */ +/** + * @defgroup mdm_regs_core_twomeg_runlen_thr_to_reset_cfo_field twomeg_runlen_thr_to_reset_cfo_field + * @brief macros for field twomeg_runlen_thr_to_reset_cfo + * @details Threshold for run-length above which assert_reset_freq_sync is asserted, 2M version + * @{ + */ +#define MDM_RESETINITCFO_ALT__TWOMEG_RUNLEN_THR_TO_RESET_CFO__SHIFT 23 +#define MDM_RESETINITCFO_ALT__TWOMEG_RUNLEN_THR_TO_RESET_CFO__WIDTH 6 +#define MDM_RESETINITCFO_ALT__TWOMEG_RUNLEN_THR_TO_RESET_CFO__MASK 0x1f800000U +#define MDM_RESETINITCFO_ALT__TWOMEG_RUNLEN_THR_TO_RESET_CFO__READ(src) \ + (((uint32_t)(src)\ + & 0x1f800000U) >> 23) +#define MDM_RESETINITCFO_ALT__TWOMEG_RUNLEN_THR_TO_RESET_CFO__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x1f800000U) +#define MDM_RESETINITCFO_ALT__TWOMEG_RUNLEN_THR_TO_RESET_CFO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1f800000U) | (((uint32_t)(src) <<\ + 23) & 0x1f800000U) +#define MDM_RESETINITCFO_ALT__TWOMEG_RUNLEN_THR_TO_RESET_CFO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x1f800000U))) +#define MDM_RESETINITCFO_ALT__TWOMEG_RUNLEN_THR_TO_RESET_CFO__RESET_VALUE \ + 0x0000000fU +/** @} */ + +/* macros for field twomeg_use_twosamples_to_updt_runlen */ +/** + * @defgroup mdm_regs_core_twomeg_use_twosamples_to_updt_runlen_field twomeg_use_twosamples_to_updt_runlen_field + * @brief macros for field twomeg_use_twosamples_to_updt_runlen + * @details When 1, use OR of two most recent abs(diff(MF out)). When 0, use just most recent, 2M version + * @{ + */ +#define MDM_RESETINITCFO_ALT__TWOMEG_USE_TWOSAMPLES_TO_UPDT_RUNLEN__SHIFT 29 +#define MDM_RESETINITCFO_ALT__TWOMEG_USE_TWOSAMPLES_TO_UPDT_RUNLEN__WIDTH 1 +#define MDM_RESETINITCFO_ALT__TWOMEG_USE_TWOSAMPLES_TO_UPDT_RUNLEN__MASK \ + 0x20000000U +#define MDM_RESETINITCFO_ALT__TWOMEG_USE_TWOSAMPLES_TO_UPDT_RUNLEN__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define MDM_RESETINITCFO_ALT__TWOMEG_USE_TWOSAMPLES_TO_UPDT_RUNLEN__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define MDM_RESETINITCFO_ALT__TWOMEG_USE_TWOSAMPLES_TO_UPDT_RUNLEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define MDM_RESETINITCFO_ALT__TWOMEG_USE_TWOSAMPLES_TO_UPDT_RUNLEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define MDM_RESETINITCFO_ALT__TWOMEG_USE_TWOSAMPLES_TO_UPDT_RUNLEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define MDM_RESETINITCFO_ALT__TWOMEG_USE_TWOSAMPLES_TO_UPDT_RUNLEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define MDM_RESETINITCFO_ALT__TWOMEG_USE_TWOSAMPLES_TO_UPDT_RUNLEN__RESET_VALUE \ + 0x00000001U +/** @} */ + +/* macros for field twomeg_reset_runlen_on_gainchg_pwrstep_only */ +/** + * @defgroup mdm_regs_core_twomeg_reset_runlen_on_gainchg_pwrstep_only_field twomeg_reset_runlen_on_gainchg_pwrstep_only_field + * @brief macros for field twomeg_reset_runlen_on_gainchg_pwrstep_only + * @details When 1, don't reset run length counter if only run length triggered assert_reset_freq_sync, 2M version + * @{ + */ +#define MDM_RESETINITCFO_ALT__TWOMEG_RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__SHIFT \ + 30 +#define MDM_RESETINITCFO_ALT__TWOMEG_RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__WIDTH \ + 1 +#define MDM_RESETINITCFO_ALT__TWOMEG_RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__MASK \ + 0x40000000U +#define MDM_RESETINITCFO_ALT__TWOMEG_RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define MDM_RESETINITCFO_ALT__TWOMEG_RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define MDM_RESETINITCFO_ALT__TWOMEG_RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define MDM_RESETINITCFO_ALT__TWOMEG_RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define MDM_RESETINITCFO_ALT__TWOMEG_RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define MDM_RESETINITCFO_ALT__TWOMEG_RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define MDM_RESETINITCFO_ALT__TWOMEG_RESET_RUNLEN_ON_GAINCHG_PWRSTEP_ONLY__RESET_VALUE \ + 0x00000001U +/** @} */ +#define MDM_RESETINITCFO_ALT__TYPE uint32_t +#define MDM_RESETINITCFO_ALT__READ 0x7fff7fffU +#define MDM_RESETINITCFO_ALT__WRITE 0x7fff7fffU +#define MDM_RESETINITCFO_ALT__PRESERVED 0x00000000U +#define MDM_RESETINITCFO_ALT__RESET_VALUE 0x67ad67adU + +#endif /* __MDM_RESETINITCFO_ALT_MACRO__ */ + +/** @} end of resetinitcfo_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_intmfreq */ +/** + * @defgroup mdm_regs_core_intmfreq intmfreq + * @brief Intermediate frequency tracking control, uncoded only, between initial estimate and AA found definitions. + * @{ + */ +#ifndef __MDM_INTMFREQ_MACRO__ +#define __MDM_INTMFREQ_MACRO__ + +/* macros for field enable_intmfreq */ +/** + * @defgroup mdm_regs_core_enable_intmfreq_field enable_intmfreq_field + * @brief macros for field enable_intmfreq + * @details Enable for 1 Mb + * @{ + */ +#define MDM_INTMFREQ__ENABLE_INTMFREQ__SHIFT 0 +#define MDM_INTMFREQ__ENABLE_INTMFREQ__WIDTH 1 +#define MDM_INTMFREQ__ENABLE_INTMFREQ__MASK 0x00000001U +#define MDM_INTMFREQ__ENABLE_INTMFREQ__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define MDM_INTMFREQ__ENABLE_INTMFREQ__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define MDM_INTMFREQ__ENABLE_INTMFREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define MDM_INTMFREQ__ENABLE_INTMFREQ__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define MDM_INTMFREQ__ENABLE_INTMFREQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_INTMFREQ__ENABLE_INTMFREQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_INTMFREQ__ENABLE_INTMFREQ__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field twomeg_enable_intmfreq */ +/** + * @defgroup mdm_regs_core_twomeg_enable_intmfreq_field twomeg_enable_intmfreq_field + * @brief macros for field twomeg_enable_intmfreq + * @details Enable for 2 Mb + * @{ + */ +#define MDM_INTMFREQ__TWOMEG_ENABLE_INTMFREQ__SHIFT 1 +#define MDM_INTMFREQ__TWOMEG_ENABLE_INTMFREQ__WIDTH 1 +#define MDM_INTMFREQ__TWOMEG_ENABLE_INTMFREQ__MASK 0x00000002U +#define MDM_INTMFREQ__TWOMEG_ENABLE_INTMFREQ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define MDM_INTMFREQ__TWOMEG_ENABLE_INTMFREQ__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define MDM_INTMFREQ__TWOMEG_ENABLE_INTMFREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define MDM_INTMFREQ__TWOMEG_ENABLE_INTMFREQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define MDM_INTMFREQ__TWOMEG_ENABLE_INTMFREQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define MDM_INTMFREQ__TWOMEG_ENABLE_INTMFREQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define MDM_INTMFREQ__TWOMEG_ENABLE_INTMFREQ__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field alpha1 */ +/** + * @defgroup mdm_regs_core_alpha1_field alpha1_field + * @brief macros for field alpha1 + * @details First gear + * @{ + */ +#define MDM_INTMFREQ__ALPHA1__SHIFT 2 +#define MDM_INTMFREQ__ALPHA1__WIDTH 4 +#define MDM_INTMFREQ__ALPHA1__MASK 0x0000003cU +#define MDM_INTMFREQ__ALPHA1__READ(src) (((uint32_t)(src) & 0x0000003cU) >> 2) +#define MDM_INTMFREQ__ALPHA1__WRITE(src) (((uint32_t)(src) << 2) & 0x0000003cU) +#define MDM_INTMFREQ__ALPHA1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003cU) | (((uint32_t)(src) <<\ + 2) & 0x0000003cU) +#define MDM_INTMFREQ__ALPHA1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000003cU))) +#define MDM_INTMFREQ__ALPHA1__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field alpha2 */ +/** + * @defgroup mdm_regs_core_alpha2_field alpha2_field + * @brief macros for field alpha2 + * @details Second gear + * @{ + */ +#define MDM_INTMFREQ__ALPHA2__SHIFT 6 +#define MDM_INTMFREQ__ALPHA2__WIDTH 4 +#define MDM_INTMFREQ__ALPHA2__MASK 0x000003c0U +#define MDM_INTMFREQ__ALPHA2__READ(src) (((uint32_t)(src) & 0x000003c0U) >> 6) +#define MDM_INTMFREQ__ALPHA2__WRITE(src) (((uint32_t)(src) << 6) & 0x000003c0U) +#define MDM_INTMFREQ__ALPHA2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003c0U) | (((uint32_t)(src) <<\ + 6) & 0x000003c0U) +#define MDM_INTMFREQ__ALPHA2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000003c0U))) +#define MDM_INTMFREQ__ALPHA2__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field alpha3 */ +/** + * @defgroup mdm_regs_core_alpha3_field alpha3_field + * @brief macros for field alpha3 + * @details Third gear + * @{ + */ +#define MDM_INTMFREQ__ALPHA3__SHIFT 10 +#define MDM_INTMFREQ__ALPHA3__WIDTH 4 +#define MDM_INTMFREQ__ALPHA3__MASK 0x00003c00U +#define MDM_INTMFREQ__ALPHA3__READ(src) (((uint32_t)(src) & 0x00003c00U) >> 10) +#define MDM_INTMFREQ__ALPHA3__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00003c00U) +#define MDM_INTMFREQ__ALPHA3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003c00U) | (((uint32_t)(src) <<\ + 10) & 0x00003c00U) +#define MDM_INTMFREQ__ALPHA3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00003c00U))) +#define MDM_INTMFREQ__ALPHA3__RESET_VALUE 0x00000009U +/** @} */ + +/* macros for field alpha_count1 */ +/** + * @defgroup mdm_regs_core_alpha_count1_field alpha_count1_field + * @brief macros for field alpha_count1 + * @details alpha_count1 * 8 = number of phase differences before switching from first to second gear + * @{ + */ +#define MDM_INTMFREQ__ALPHA_COUNT1__SHIFT 14 +#define MDM_INTMFREQ__ALPHA_COUNT1__WIDTH 6 +#define MDM_INTMFREQ__ALPHA_COUNT1__MASK 0x000fc000U +#define MDM_INTMFREQ__ALPHA_COUNT1__READ(src) \ + (((uint32_t)(src)\ + & 0x000fc000U) >> 14) +#define MDM_INTMFREQ__ALPHA_COUNT1__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x000fc000U) +#define MDM_INTMFREQ__ALPHA_COUNT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fc000U) | (((uint32_t)(src) <<\ + 14) & 0x000fc000U) +#define MDM_INTMFREQ__ALPHA_COUNT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x000fc000U))) +#define MDM_INTMFREQ__ALPHA_COUNT1__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field alpha_count2 */ +/** + * @defgroup mdm_regs_core_alpha_count2_field alpha_count2_field + * @brief macros for field alpha_count2 + * @details alpha_count2 * 8 = number of phase differences before switching from second to third gear. Includes first gear as well + * @{ + */ +#define MDM_INTMFREQ__ALPHA_COUNT2__SHIFT 20 +#define MDM_INTMFREQ__ALPHA_COUNT2__WIDTH 6 +#define MDM_INTMFREQ__ALPHA_COUNT2__MASK 0x03f00000U +#define MDM_INTMFREQ__ALPHA_COUNT2__READ(src) \ + (((uint32_t)(src)\ + & 0x03f00000U) >> 20) +#define MDM_INTMFREQ__ALPHA_COUNT2__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x03f00000U) +#define MDM_INTMFREQ__ALPHA_COUNT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03f00000U) | (((uint32_t)(src) <<\ + 20) & 0x03f00000U) +#define MDM_INTMFREQ__ALPHA_COUNT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x03f00000U))) +#define MDM_INTMFREQ__ALPHA_COUNT2__RESET_VALUE 0x00000008U +/** @} */ +#define MDM_INTMFREQ__TYPE uint32_t +#define MDM_INTMFREQ__READ 0x03ffffffU +#define MDM_INTMFREQ__WRITE 0x03ffffffU +#define MDM_INTMFREQ__PRESERVED 0x00000000U +#define MDM_INTMFREQ__RESET_VALUE 0x0081261fU + +#endif /* __MDM_INTMFREQ_MACRO__ */ + +/** @} end of intmfreq */ + +/* macros for BlueprintGlobalNameSpace::MDM_intmfreq_alt */ +/** + * @defgroup mdm_regs_core_intmfreq_alt intmfreq_alt + * @brief Intermediate frequency tracking control, uncoded only, between initial estimate and AA found, alternate set definitions. + * @{ + */ +#ifndef __MDM_INTMFREQ_ALT_MACRO__ +#define __MDM_INTMFREQ_ALT_MACRO__ + +/* macros for field enable_intmfreq */ +/** + * @defgroup mdm_regs_core_enable_intmfreq_field enable_intmfreq_field + * @brief macros for field enable_intmfreq + * @details Enable for 1 Mb + * @{ + */ +#define MDM_INTMFREQ_ALT__ENABLE_INTMFREQ__SHIFT 0 +#define MDM_INTMFREQ_ALT__ENABLE_INTMFREQ__WIDTH 1 +#define MDM_INTMFREQ_ALT__ENABLE_INTMFREQ__MASK 0x00000001U +#define MDM_INTMFREQ_ALT__ENABLE_INTMFREQ__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define MDM_INTMFREQ_ALT__ENABLE_INTMFREQ__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define MDM_INTMFREQ_ALT__ENABLE_INTMFREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define MDM_INTMFREQ_ALT__ENABLE_INTMFREQ__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define MDM_INTMFREQ_ALT__ENABLE_INTMFREQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_INTMFREQ_ALT__ENABLE_INTMFREQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_INTMFREQ_ALT__ENABLE_INTMFREQ__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field twomeg_enable_intmfreq */ +/** + * @defgroup mdm_regs_core_twomeg_enable_intmfreq_field twomeg_enable_intmfreq_field + * @brief macros for field twomeg_enable_intmfreq + * @details Enable for 2 Mb + * @{ + */ +#define MDM_INTMFREQ_ALT__TWOMEG_ENABLE_INTMFREQ__SHIFT 1 +#define MDM_INTMFREQ_ALT__TWOMEG_ENABLE_INTMFREQ__WIDTH 1 +#define MDM_INTMFREQ_ALT__TWOMEG_ENABLE_INTMFREQ__MASK 0x00000002U +#define MDM_INTMFREQ_ALT__TWOMEG_ENABLE_INTMFREQ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define MDM_INTMFREQ_ALT__TWOMEG_ENABLE_INTMFREQ__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define MDM_INTMFREQ_ALT__TWOMEG_ENABLE_INTMFREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define MDM_INTMFREQ_ALT__TWOMEG_ENABLE_INTMFREQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define MDM_INTMFREQ_ALT__TWOMEG_ENABLE_INTMFREQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define MDM_INTMFREQ_ALT__TWOMEG_ENABLE_INTMFREQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define MDM_INTMFREQ_ALT__TWOMEG_ENABLE_INTMFREQ__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field alpha1 */ +/** + * @defgroup mdm_regs_core_alpha1_field alpha1_field + * @brief macros for field alpha1 + * @details First gear + * @{ + */ +#define MDM_INTMFREQ_ALT__ALPHA1__SHIFT 2 +#define MDM_INTMFREQ_ALT__ALPHA1__WIDTH 4 +#define MDM_INTMFREQ_ALT__ALPHA1__MASK 0x0000003cU +#define MDM_INTMFREQ_ALT__ALPHA1__READ(src) \ + (((uint32_t)(src)\ + & 0x0000003cU) >> 2) +#define MDM_INTMFREQ_ALT__ALPHA1__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000003cU) +#define MDM_INTMFREQ_ALT__ALPHA1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003cU) | (((uint32_t)(src) <<\ + 2) & 0x0000003cU) +#define MDM_INTMFREQ_ALT__ALPHA1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000003cU))) +#define MDM_INTMFREQ_ALT__ALPHA1__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field alpha2 */ +/** + * @defgroup mdm_regs_core_alpha2_field alpha2_field + * @brief macros for field alpha2 + * @details Second gear + * @{ + */ +#define MDM_INTMFREQ_ALT__ALPHA2__SHIFT 6 +#define MDM_INTMFREQ_ALT__ALPHA2__WIDTH 4 +#define MDM_INTMFREQ_ALT__ALPHA2__MASK 0x000003c0U +#define MDM_INTMFREQ_ALT__ALPHA2__READ(src) \ + (((uint32_t)(src)\ + & 0x000003c0U) >> 6) +#define MDM_INTMFREQ_ALT__ALPHA2__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000003c0U) +#define MDM_INTMFREQ_ALT__ALPHA2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003c0U) | (((uint32_t)(src) <<\ + 6) & 0x000003c0U) +#define MDM_INTMFREQ_ALT__ALPHA2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000003c0U))) +#define MDM_INTMFREQ_ALT__ALPHA2__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field alpha3 */ +/** + * @defgroup mdm_regs_core_alpha3_field alpha3_field + * @brief macros for field alpha3 + * @details Third gear + * @{ + */ +#define MDM_INTMFREQ_ALT__ALPHA3__SHIFT 10 +#define MDM_INTMFREQ_ALT__ALPHA3__WIDTH 4 +#define MDM_INTMFREQ_ALT__ALPHA3__MASK 0x00003c00U +#define MDM_INTMFREQ_ALT__ALPHA3__READ(src) \ + (((uint32_t)(src)\ + & 0x00003c00U) >> 10) +#define MDM_INTMFREQ_ALT__ALPHA3__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00003c00U) +#define MDM_INTMFREQ_ALT__ALPHA3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003c00U) | (((uint32_t)(src) <<\ + 10) & 0x00003c00U) +#define MDM_INTMFREQ_ALT__ALPHA3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00003c00U))) +#define MDM_INTMFREQ_ALT__ALPHA3__RESET_VALUE 0x00000009U +/** @} */ + +/* macros for field alpha_count1 */ +/** + * @defgroup mdm_regs_core_alpha_count1_field alpha_count1_field + * @brief macros for field alpha_count1 + * @details alpha_count1 * 8 = number of phase differences before switching from first to second gear + * @{ + */ +#define MDM_INTMFREQ_ALT__ALPHA_COUNT1__SHIFT 14 +#define MDM_INTMFREQ_ALT__ALPHA_COUNT1__WIDTH 6 +#define MDM_INTMFREQ_ALT__ALPHA_COUNT1__MASK 0x000fc000U +#define MDM_INTMFREQ_ALT__ALPHA_COUNT1__READ(src) \ + (((uint32_t)(src)\ + & 0x000fc000U) >> 14) +#define MDM_INTMFREQ_ALT__ALPHA_COUNT1__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x000fc000U) +#define MDM_INTMFREQ_ALT__ALPHA_COUNT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fc000U) | (((uint32_t)(src) <<\ + 14) & 0x000fc000U) +#define MDM_INTMFREQ_ALT__ALPHA_COUNT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x000fc000U))) +#define MDM_INTMFREQ_ALT__ALPHA_COUNT1__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field alpha_count2 */ +/** + * @defgroup mdm_regs_core_alpha_count2_field alpha_count2_field + * @brief macros for field alpha_count2 + * @details alpha_count2 * 8 = number of phase differences before switching from second to third gear. Includes first gear as well + * @{ + */ +#define MDM_INTMFREQ_ALT__ALPHA_COUNT2__SHIFT 20 +#define MDM_INTMFREQ_ALT__ALPHA_COUNT2__WIDTH 6 +#define MDM_INTMFREQ_ALT__ALPHA_COUNT2__MASK 0x03f00000U +#define MDM_INTMFREQ_ALT__ALPHA_COUNT2__READ(src) \ + (((uint32_t)(src)\ + & 0x03f00000U) >> 20) +#define MDM_INTMFREQ_ALT__ALPHA_COUNT2__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x03f00000U) +#define MDM_INTMFREQ_ALT__ALPHA_COUNT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03f00000U) | (((uint32_t)(src) <<\ + 20) & 0x03f00000U) +#define MDM_INTMFREQ_ALT__ALPHA_COUNT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x03f00000U))) +#define MDM_INTMFREQ_ALT__ALPHA_COUNT2__RESET_VALUE 0x00000008U +/** @} */ +#define MDM_INTMFREQ_ALT__TYPE uint32_t +#define MDM_INTMFREQ_ALT__READ 0x03ffffffU +#define MDM_INTMFREQ_ALT__WRITE 0x03ffffffU +#define MDM_INTMFREQ_ALT__PRESERVED 0x00000000U +#define MDM_INTMFREQ_ALT__RESET_VALUE 0x0081261fU + +#endif /* __MDM_INTMFREQ_ALT_MACRO__ */ + +/** @} end of intmfreq_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_tstimeout */ +/** + * @defgroup mdm_regs_core_tstimeout tstimeout + * @brief Time sync timeout control definitions. + * @{ + */ +#ifndef __MDM_TSTIMEOUT_MACRO__ +#define __MDM_TSTIMEOUT_MACRO__ + +/* macros for field coded_numsamples */ +/** + * @defgroup mdm_regs_core_coded_numsamples_field coded_numsamples_field + * @brief macros for field coded_numsamples + * @details Number of samples before declaring timeout, coded rates + * @{ + */ +#define MDM_TSTIMEOUT__CODED_NUMSAMPLES__SHIFT 9 +#define MDM_TSTIMEOUT__CODED_NUMSAMPLES__WIDTH 10 +#define MDM_TSTIMEOUT__CODED_NUMSAMPLES__MASK 0x0007fe00U +#define MDM_TSTIMEOUT__CODED_NUMSAMPLES__READ(src) \ + (((uint32_t)(src)\ + & 0x0007fe00U) >> 9) +#define MDM_TSTIMEOUT__CODED_NUMSAMPLES__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0007fe00U) +#define MDM_TSTIMEOUT__CODED_NUMSAMPLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0007fe00U) +#define MDM_TSTIMEOUT__CODED_NUMSAMPLES__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0007fe00U))) +#define MDM_TSTIMEOUT__CODED_NUMSAMPLES__RESET_VALUE 0x00000190U +/** @} */ + +/* macros for field coded_en */ +/** + * @defgroup mdm_regs_core_coded_en_field coded_en_field + * @brief macros for field coded_en + * @details enable timesync timeout, coded rates + * @{ + */ +#define MDM_TSTIMEOUT__CODED_EN__SHIFT 30 +#define MDM_TSTIMEOUT__CODED_EN__WIDTH 1 +#define MDM_TSTIMEOUT__CODED_EN__MASK 0x40000000U +#define MDM_TSTIMEOUT__CODED_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define MDM_TSTIMEOUT__CODED_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define MDM_TSTIMEOUT__CODED_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define MDM_TSTIMEOUT__CODED_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define MDM_TSTIMEOUT__CODED_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define MDM_TSTIMEOUT__CODED_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define MDM_TSTIMEOUT__CODED_EN__RESET_VALUE 0x00000001U +/** @} */ +#define MDM_TSTIMEOUT__TYPE uint32_t +#define MDM_TSTIMEOUT__READ 0x4007fe00U +#define MDM_TSTIMEOUT__WRITE 0x4007fe00U +#define MDM_TSTIMEOUT__PRESERVED 0x00000000U +#define MDM_TSTIMEOUT__RESET_VALUE 0x40032000U + +#endif /* __MDM_TSTIMEOUT_MACRO__ */ + +/** @} end of tstimeout */ + +/* macros for BlueprintGlobalNameSpace::MDM_demod */ +/** + * @defgroup mdm_regs_core_demod demod + * @brief Various demodulation control definitions. + * @{ + */ +#ifndef __MDM_DEMOD_MACRO__ +#define __MDM_DEMOD_MACRO__ + +/* macros for field enable_ffe */ +/** + * @defgroup mdm_regs_core_enable_ffe_field enable_ffe_field + * @brief macros for field enable_ffe + * @details For 1 and 2 Mb/s, enables ffe demod. Not used by coded rates + * @{ + */ +#define MDM_DEMOD__ENABLE_FFE__SHIFT 0 +#define MDM_DEMOD__ENABLE_FFE__WIDTH 1 +#define MDM_DEMOD__ENABLE_FFE__MASK 0x00000001U +#define MDM_DEMOD__ENABLE_FFE__READ(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_DEMOD__ENABLE_FFE__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_DEMOD__ENABLE_FFE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define MDM_DEMOD__ENABLE_FFE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define MDM_DEMOD__ENABLE_FFE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_DEMOD__ENABLE_FFE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_DEMOD__ENABLE_FFE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field uncoded_sat_phase_diff */ +/** + * @defgroup mdm_regs_core_uncoded_sat_phase_diff_field uncoded_sat_phase_diff_field + * @brief macros for field uncoded_sat_phase_diff + * @details Enable saturation of phase differences to range of +/- phase_diff_max. Uncoded rates + * @{ + */ +#define MDM_DEMOD__UNCODED_SAT_PHASE_DIFF__SHIFT 9 +#define MDM_DEMOD__UNCODED_SAT_PHASE_DIFF__WIDTH 1 +#define MDM_DEMOD__UNCODED_SAT_PHASE_DIFF__MASK 0x00000200U +#define MDM_DEMOD__UNCODED_SAT_PHASE_DIFF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define MDM_DEMOD__UNCODED_SAT_PHASE_DIFF__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define MDM_DEMOD__UNCODED_SAT_PHASE_DIFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define MDM_DEMOD__UNCODED_SAT_PHASE_DIFF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define MDM_DEMOD__UNCODED_SAT_PHASE_DIFF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define MDM_DEMOD__UNCODED_SAT_PHASE_DIFF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define MDM_DEMOD__UNCODED_SAT_PHASE_DIFF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field uncoded_max_phase_diff */ +/** + * @defgroup mdm_regs_core_uncoded_max_phase_diff_field uncoded_max_phase_diff_field + * @brief macros for field uncoded_max_phase_diff + * @details Absolute value of maximum phase difference. Uncoded rates + * @{ + */ +#define MDM_DEMOD__UNCODED_MAX_PHASE_DIFF__SHIFT 10 +#define MDM_DEMOD__UNCODED_MAX_PHASE_DIFF__WIDTH 6 +#define MDM_DEMOD__UNCODED_MAX_PHASE_DIFF__MASK 0x0000fc00U +#define MDM_DEMOD__UNCODED_MAX_PHASE_DIFF__READ(src) \ + (((uint32_t)(src)\ + & 0x0000fc00U) >> 10) +#define MDM_DEMOD__UNCODED_MAX_PHASE_DIFF__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x0000fc00U) +#define MDM_DEMOD__UNCODED_MAX_PHASE_DIFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fc00U) | (((uint32_t)(src) <<\ + 10) & 0x0000fc00U) +#define MDM_DEMOD__UNCODED_MAX_PHASE_DIFF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x0000fc00U))) +#define MDM_DEMOD__UNCODED_MAX_PHASE_DIFF__RESET_VALUE 0x00000030U +/** @} */ + +/* macros for field adjust_sat_for_freq_offset */ +/** + * @defgroup mdm_regs_core_adjust_sat_for_freq_offset_field adjust_sat_for_freq_offset_field + * @brief macros for field adjust_sat_for_freq_offset + * @details For each phase_diff sample, adjust saturation range based on current frequency offset estimate + * @{ + */ +#define MDM_DEMOD__ADJUST_SAT_FOR_FREQ_OFFSET__SHIFT 16 +#define MDM_DEMOD__ADJUST_SAT_FOR_FREQ_OFFSET__WIDTH 1 +#define MDM_DEMOD__ADJUST_SAT_FOR_FREQ_OFFSET__MASK 0x00010000U +#define MDM_DEMOD__ADJUST_SAT_FOR_FREQ_OFFSET__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define MDM_DEMOD__ADJUST_SAT_FOR_FREQ_OFFSET__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define MDM_DEMOD__ADJUST_SAT_FOR_FREQ_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define MDM_DEMOD__ADJUST_SAT_FOR_FREQ_OFFSET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define MDM_DEMOD__ADJUST_SAT_FOR_FREQ_OFFSET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define MDM_DEMOD__ADJUST_SAT_FOR_FREQ_OFFSET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define MDM_DEMOD__ADJUST_SAT_FOR_FREQ_OFFSET__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field coded_sat_phase_diff */ +/** + * @defgroup mdm_regs_core_coded_sat_phase_diff_field coded_sat_phase_diff_field + * @brief macros for field coded_sat_phase_diff + * @details Enable saturation of phase differences to range of +/- phase_diff_max. Coded rates + * @{ + */ +#define MDM_DEMOD__CODED_SAT_PHASE_DIFF__SHIFT 25 +#define MDM_DEMOD__CODED_SAT_PHASE_DIFF__WIDTH 1 +#define MDM_DEMOD__CODED_SAT_PHASE_DIFF__MASK 0x02000000U +#define MDM_DEMOD__CODED_SAT_PHASE_DIFF__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define MDM_DEMOD__CODED_SAT_PHASE_DIFF__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define MDM_DEMOD__CODED_SAT_PHASE_DIFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define MDM_DEMOD__CODED_SAT_PHASE_DIFF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define MDM_DEMOD__CODED_SAT_PHASE_DIFF__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define MDM_DEMOD__CODED_SAT_PHASE_DIFF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define MDM_DEMOD__CODED_SAT_PHASE_DIFF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field coded_max_phase_diff */ +/** + * @defgroup mdm_regs_core_coded_max_phase_diff_field coded_max_phase_diff_field + * @brief macros for field coded_max_phase_diff + * @details Absolute value of maximum phase difference. Coded rates + * @{ + */ +#define MDM_DEMOD__CODED_MAX_PHASE_DIFF__SHIFT 26 +#define MDM_DEMOD__CODED_MAX_PHASE_DIFF__WIDTH 6 +#define MDM_DEMOD__CODED_MAX_PHASE_DIFF__MASK 0xfc000000U +#define MDM_DEMOD__CODED_MAX_PHASE_DIFF__READ(src) \ + (((uint32_t)(src)\ + & 0xfc000000U) >> 26) +#define MDM_DEMOD__CODED_MAX_PHASE_DIFF__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0xfc000000U) +#define MDM_DEMOD__CODED_MAX_PHASE_DIFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfc000000U) | (((uint32_t)(src) <<\ + 26) & 0xfc000000U) +#define MDM_DEMOD__CODED_MAX_PHASE_DIFF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0xfc000000U))) +#define MDM_DEMOD__CODED_MAX_PHASE_DIFF__RESET_VALUE 0x00000030U +/** @} */ +#define MDM_DEMOD__TYPE uint32_t +#define MDM_DEMOD__READ 0xfe01fe01U +#define MDM_DEMOD__WRITE 0xfe01fe01U +#define MDM_DEMOD__PRESERVED 0x00000000U +#define MDM_DEMOD__RESET_VALUE 0xc200c201U + +#endif /* __MDM_DEMOD_MACRO__ */ + +/** @} end of demod */ + +/* macros for BlueprintGlobalNameSpace::MDM_dfewithffe */ +/** + * @defgroup mdm_regs_core_dfewithffe dfewithffe + * @brief DFE adjustments to make to demod_threshold when FFE is enabled (enable_ffe_demod set, and uncoded rate) definitions. + * @{ + */ +#ifndef __MDM_DFEWITHFFE_MACRO__ +#define __MDM_DFEWITHFFE_MACRO__ + +/* macros for field adjust1 */ +/** + * @defgroup mdm_regs_core_adjust1_field adjust1_field + * @brief macros for field adjust1 + * @details For immediately previous symbol. Signed + * @{ + */ +#define MDM_DFEWITHFFE__ADJUST1__SHIFT 0 +#define MDM_DFEWITHFFE__ADJUST1__WIDTH 8 +#define MDM_DFEWITHFFE__ADJUST1__MASK 0x000000ffU +#define MDM_DFEWITHFFE__ADJUST1__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_DFEWITHFFE__ADJUST1__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_DFEWITHFFE__ADJUST1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_DFEWITHFFE__ADJUST1__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define MDM_DFEWITHFFE__ADJUST1__RESET_VALUE 0x00000041U +/** @} */ + +/* macros for field adjust2 */ +/** + * @defgroup mdm_regs_core_adjust2_field adjust2_field + * @brief macros for field adjust2 + * @details Looking back two symbols. Signed + * @{ + */ +#define MDM_DFEWITHFFE__ADJUST2__SHIFT 8 +#define MDM_DFEWITHFFE__ADJUST2__WIDTH 8 +#define MDM_DFEWITHFFE__ADJUST2__MASK 0x0000ff00U +#define MDM_DFEWITHFFE__ADJUST2__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_DFEWITHFFE__ADJUST2__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define MDM_DFEWITHFFE__ADJUST2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MDM_DFEWITHFFE__ADJUST2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define MDM_DFEWITHFFE__ADJUST2__RESET_VALUE 0x00000020U +/** @} */ + +/* macros for field adjust3 */ +/** + * @defgroup mdm_regs_core_adjust3_field adjust3_field + * @brief macros for field adjust3 + * @details Looking back three symbols. Signed + * @{ + */ +#define MDM_DFEWITHFFE__ADJUST3__SHIFT 16 +#define MDM_DFEWITHFFE__ADJUST3__WIDTH 8 +#define MDM_DFEWITHFFE__ADJUST3__MASK 0x00ff0000U +#define MDM_DFEWITHFFE__ADJUST3__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MDM_DFEWITHFFE__ADJUST3__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define MDM_DFEWITHFFE__ADJUST3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MDM_DFEWITHFFE__ADJUST3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define MDM_DFEWITHFFE__ADJUST3__RESET_VALUE 0x00000005U +/** @} */ +#define MDM_DFEWITHFFE__TYPE uint32_t +#define MDM_DFEWITHFFE__READ 0x00ffffffU +#define MDM_DFEWITHFFE__WRITE 0x00ffffffU +#define MDM_DFEWITHFFE__PRESERVED 0x00000000U +#define MDM_DFEWITHFFE__RESET_VALUE 0x00052041U + +#endif /* __MDM_DFEWITHFFE_MACRO__ */ + +/** @} end of dfewithffe */ + +/* macros for BlueprintGlobalNameSpace::MDM_dfewithoutffe */ +/** + * @defgroup mdm_regs_core_dfewithoutffe dfewithoutffe + * @brief DFE adjustments to make to demod_threshold when FFE is not used (enable_ffe_demod clear, or coded rate) definitions. + * @{ + */ +#ifndef __MDM_DFEWITHOUTFFE_MACRO__ +#define __MDM_DFEWITHOUTFFE_MACRO__ + +/* macros for field adjust1 */ +/** + * @defgroup mdm_regs_core_adjust1_field adjust1_field + * @brief macros for field adjust1 + * @details For immediately previous symbol. Signed + * @{ + */ +#define MDM_DFEWITHOUTFFE__ADJUST1__SHIFT 0 +#define MDM_DFEWITHOUTFFE__ADJUST1__WIDTH 8 +#define MDM_DFEWITHOUTFFE__ADJUST1__MASK 0x000000ffU +#define MDM_DFEWITHOUTFFE__ADJUST1__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_DFEWITHOUTFFE__ADJUST1__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_DFEWITHOUTFFE__ADJUST1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_DFEWITHOUTFFE__ADJUST1__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define MDM_DFEWITHOUTFFE__ADJUST1__RESET_VALUE 0x00000017U +/** @} */ + +/* macros for field adjust2 */ +/** + * @defgroup mdm_regs_core_adjust2_field adjust2_field + * @brief macros for field adjust2 + * @details Looking back two symbols. Signed + * @{ + */ +#define MDM_DFEWITHOUTFFE__ADJUST2__SHIFT 8 +#define MDM_DFEWITHOUTFFE__ADJUST2__WIDTH 8 +#define MDM_DFEWITHOUTFFE__ADJUST2__MASK 0x0000ff00U +#define MDM_DFEWITHOUTFFE__ADJUST2__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_DFEWITHOUTFFE__ADJUST2__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define MDM_DFEWITHOUTFFE__ADJUST2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MDM_DFEWITHOUTFFE__ADJUST2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define MDM_DFEWITHOUTFFE__ADJUST2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adjust3 */ +/** + * @defgroup mdm_regs_core_adjust3_field adjust3_field + * @brief macros for field adjust3 + * @details Looking back three symbols. Signed + * @{ + */ +#define MDM_DFEWITHOUTFFE__ADJUST3__SHIFT 16 +#define MDM_DFEWITHOUTFFE__ADJUST3__WIDTH 8 +#define MDM_DFEWITHOUTFFE__ADJUST3__MASK 0x00ff0000U +#define MDM_DFEWITHOUTFFE__ADJUST3__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MDM_DFEWITHOUTFFE__ADJUST3__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define MDM_DFEWITHOUTFFE__ADJUST3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MDM_DFEWITHOUTFFE__ADJUST3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define MDM_DFEWITHOUTFFE__ADJUST3__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_DFEWITHOUTFFE__TYPE uint32_t +#define MDM_DFEWITHOUTFFE__READ 0x00ffffffU +#define MDM_DFEWITHOUTFFE__WRITE 0x00ffffffU +#define MDM_DFEWITHOUTFFE__PRESERVED 0x00000000U +#define MDM_DFEWITHOUTFFE__RESET_VALUE 0x00000017U + +#endif /* __MDM_DFEWITHOUTFFE_MACRO__ */ + +/** @} end of dfewithoutffe */ + +/* macros for BlueprintGlobalNameSpace::MDM_twomeg_dfewithffe */ +/** + * @defgroup mdm_regs_core_twomeg_dfewithffe twomeg_dfewithffe + * @brief DFE adjustments to make to demod_threshold when FFE is enabled (enable_ffe_demod set, and uncoded rate) definitions. + * @{ + */ +#ifndef __MDM_TWOMEG_DFEWITHFFE_MACRO__ +#define __MDM_TWOMEG_DFEWITHFFE_MACRO__ + +/* macros for field adjust1 */ +/** + * @defgroup mdm_regs_core_adjust1_field adjust1_field + * @brief macros for field adjust1 + * @details For immediately previous symbol. Signed + * @{ + */ +#define MDM_TWOMEG_DFEWITHFFE__ADJUST1__SHIFT 0 +#define MDM_TWOMEG_DFEWITHFFE__ADJUST1__WIDTH 8 +#define MDM_TWOMEG_DFEWITHFFE__ADJUST1__MASK 0x000000ffU +#define MDM_TWOMEG_DFEWITHFFE__ADJUST1__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_TWOMEG_DFEWITHFFE__ADJUST1__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_TWOMEG_DFEWITHFFE__ADJUST1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_TWOMEG_DFEWITHFFE__ADJUST1__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define MDM_TWOMEG_DFEWITHFFE__ADJUST1__RESET_VALUE 0x00000040U +/** @} */ + +/* macros for field adjust2 */ +/** + * @defgroup mdm_regs_core_adjust2_field adjust2_field + * @brief macros for field adjust2 + * @details Looking back two symbols. Signed + * @{ + */ +#define MDM_TWOMEG_DFEWITHFFE__ADJUST2__SHIFT 8 +#define MDM_TWOMEG_DFEWITHFFE__ADJUST2__WIDTH 8 +#define MDM_TWOMEG_DFEWITHFFE__ADJUST2__MASK 0x0000ff00U +#define MDM_TWOMEG_DFEWITHFFE__ADJUST2__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_TWOMEG_DFEWITHFFE__ADJUST2__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define MDM_TWOMEG_DFEWITHFFE__ADJUST2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MDM_TWOMEG_DFEWITHFFE__ADJUST2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define MDM_TWOMEG_DFEWITHFFE__ADJUST2__RESET_VALUE 0x0000001eU +/** @} */ + +/* macros for field adjust3 */ +/** + * @defgroup mdm_regs_core_adjust3_field adjust3_field + * @brief macros for field adjust3 + * @details Looking back three symbols. Signed + * @{ + */ +#define MDM_TWOMEG_DFEWITHFFE__ADJUST3__SHIFT 16 +#define MDM_TWOMEG_DFEWITHFFE__ADJUST3__WIDTH 8 +#define MDM_TWOMEG_DFEWITHFFE__ADJUST3__MASK 0x00ff0000U +#define MDM_TWOMEG_DFEWITHFFE__ADJUST3__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MDM_TWOMEG_DFEWITHFFE__ADJUST3__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define MDM_TWOMEG_DFEWITHFFE__ADJUST3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MDM_TWOMEG_DFEWITHFFE__ADJUST3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define MDM_TWOMEG_DFEWITHFFE__ADJUST3__RESET_VALUE 0x00000004U +/** @} */ +#define MDM_TWOMEG_DFEWITHFFE__TYPE uint32_t +#define MDM_TWOMEG_DFEWITHFFE__READ 0x00ffffffU +#define MDM_TWOMEG_DFEWITHFFE__WRITE 0x00ffffffU +#define MDM_TWOMEG_DFEWITHFFE__PRESERVED 0x00000000U +#define MDM_TWOMEG_DFEWITHFFE__RESET_VALUE 0x00041e40U + +#endif /* __MDM_TWOMEG_DFEWITHFFE_MACRO__ */ + +/** @} end of twomeg_dfewithffe */ + +/* macros for BlueprintGlobalNameSpace::MDM_twomeg_dfewithoutffe */ +/** + * @defgroup mdm_regs_core_twomeg_dfewithoutffe twomeg_dfewithoutffe + * @brief DFE adjustments to make to demod_threshold when FFE is not used (enable_ffe_demod clear, or coded rate) definitions. + * @{ + */ +#ifndef __MDM_TWOMEG_DFEWITHOUTFFE_MACRO__ +#define __MDM_TWOMEG_DFEWITHOUTFFE_MACRO__ + +/* macros for field adjust1 */ +/** + * @defgroup mdm_regs_core_adjust1_field adjust1_field + * @brief macros for field adjust1 + * @details For immediately previous symbol. Signed + * @{ + */ +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST1__SHIFT 0 +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST1__WIDTH 8 +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST1__MASK 0x000000ffU +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST1__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST1__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST1__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST1__RESET_VALUE 0x00000017U +/** @} */ + +/* macros for field adjust2 */ +/** + * @defgroup mdm_regs_core_adjust2_field adjust2_field + * @brief macros for field adjust2 + * @details Looking back two symbols. Signed + * @{ + */ +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST2__SHIFT 8 +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST2__WIDTH 8 +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST2__MASK 0x0000ff00U +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST2__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST2__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adjust3 */ +/** + * @defgroup mdm_regs_core_adjust3_field adjust3_field + * @brief macros for field adjust3 + * @details Looking back three symbols. Signed + * @{ + */ +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST3__SHIFT 16 +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST3__WIDTH 8 +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST3__MASK 0x00ff0000U +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST3__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST3__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define MDM_TWOMEG_DFEWITHOUTFFE__ADJUST3__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_TWOMEG_DFEWITHOUTFFE__TYPE uint32_t +#define MDM_TWOMEG_DFEWITHOUTFFE__READ 0x00ffffffU +#define MDM_TWOMEG_DFEWITHOUTFFE__WRITE 0x00ffffffU +#define MDM_TWOMEG_DFEWITHOUTFFE__PRESERVED 0x00000000U +#define MDM_TWOMEG_DFEWITHOUTFFE__RESET_VALUE 0x00000017U + +#endif /* __MDM_TWOMEG_DFEWITHOUTFFE_MACRO__ */ + +/** @} end of twomeg_dfewithoutffe */ + +/* macros for BlueprintGlobalNameSpace::MDM_freq */ +/** + * @defgroup mdm_regs_core_freq freq + * @brief Frequency tracking control definitions. + * @{ + */ +#ifndef __MDM_FREQ_MACRO__ +#define __MDM_FREQ_MACRO__ + +/* macros for field enable_track */ +/** + * @defgroup mdm_regs_core_enable_track_field enable_track_field + * @brief macros for field enable_track + * @details 1 is enable frequency tracking. 0 is just use initial estimate from preamble + * @{ + */ +#define MDM_FREQ__ENABLE_TRACK__SHIFT 0 +#define MDM_FREQ__ENABLE_TRACK__WIDTH 1 +#define MDM_FREQ__ENABLE_TRACK__MASK 0x00000001U +#define MDM_FREQ__ENABLE_TRACK__READ(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_FREQ__ENABLE_TRACK__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_FREQ__ENABLE_TRACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define MDM_FREQ__ENABLE_TRACK__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define MDM_FREQ__ENABLE_TRACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_FREQ__ENABLE_TRACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_FREQ__ENABLE_TRACK__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field enable_same_pat */ +/** + * @defgroup mdm_regs_core_enable_same_pat_field enable_same_pat_field + * @brief macros for field enable_same_pat + * @details Perform tracking based on same 3-bit pattern in addition to flipped pattern + * @{ + */ +#define MDM_FREQ__ENABLE_SAME_PAT__SHIFT 1 +#define MDM_FREQ__ENABLE_SAME_PAT__WIDTH 1 +#define MDM_FREQ__ENABLE_SAME_PAT__MASK 0x00000002U +#define MDM_FREQ__ENABLE_SAME_PAT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define MDM_FREQ__ENABLE_SAME_PAT__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define MDM_FREQ__ENABLE_SAME_PAT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define MDM_FREQ__ENABLE_SAME_PAT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define MDM_FREQ__ENABLE_SAME_PAT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define MDM_FREQ__ENABLE_SAME_PAT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define MDM_FREQ__ENABLE_SAME_PAT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mu1 */ +/** + * @defgroup mdm_regs_core_mu1_field mu1_field + * @brief macros for field mu1 + * @details mu to use for first gear. Encoding: 2^(-(mu1+1)) + * @{ + */ +#define MDM_FREQ__MU1__SHIFT 2 +#define MDM_FREQ__MU1__WIDTH 3 +#define MDM_FREQ__MU1__MASK 0x0000001cU +#define MDM_FREQ__MU1__READ(src) (((uint32_t)(src) & 0x0000001cU) >> 2) +#define MDM_FREQ__MU1__WRITE(src) (((uint32_t)(src) << 2) & 0x0000001cU) +#define MDM_FREQ__MU1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((uint32_t)(src) <<\ + 2) & 0x0000001cU) +#define MDM_FREQ__MU1__VERIFY(src) (!((((uint32_t)(src) << 2) & ~0x0000001cU))) +#define MDM_FREQ__MU1__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field mu2 */ +/** + * @defgroup mdm_regs_core_mu2_field mu2_field + * @brief macros for field mu2 + * @details mu to use for second gear. Encoding: 2^(-(mu2+1)) + * @{ + */ +#define MDM_FREQ__MU2__SHIFT 5 +#define MDM_FREQ__MU2__WIDTH 3 +#define MDM_FREQ__MU2__MASK 0x000000e0U +#define MDM_FREQ__MU2__READ(src) (((uint32_t)(src) & 0x000000e0U) >> 5) +#define MDM_FREQ__MU2__WRITE(src) (((uint32_t)(src) << 5) & 0x000000e0U) +#define MDM_FREQ__MU2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((uint32_t)(src) <<\ + 5) & 0x000000e0U) +#define MDM_FREQ__MU2__VERIFY(src) (!((((uint32_t)(src) << 5) & ~0x000000e0U))) +#define MDM_FREQ__MU2__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field mu3 */ +/** + * @defgroup mdm_regs_core_mu3_field mu3_field + * @brief macros for field mu3 + * @details mu to use for third gear. Encoding: 2^(-(mu3+1)) + * @{ + */ +#define MDM_FREQ__MU3__SHIFT 8 +#define MDM_FREQ__MU3__WIDTH 3 +#define MDM_FREQ__MU3__MASK 0x00000700U +#define MDM_FREQ__MU3__READ(src) (((uint32_t)(src) & 0x00000700U) >> 8) +#define MDM_FREQ__MU3__WRITE(src) (((uint32_t)(src) << 8) & 0x00000700U) +#define MDM_FREQ__MU3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((uint32_t)(src) <<\ + 8) & 0x00000700U) +#define MDM_FREQ__MU3__VERIFY(src) (!((((uint32_t)(src) << 8) & ~0x00000700U))) +#define MDM_FREQ__MU3__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field pat_dly */ +/** + * @defgroup mdm_regs_core_pat_dly_field pat_dly_field + * @brief macros for field pat_dly + * @details determines number of symbols for when pattern matching times out. Encoding is 2^(pat_dly+2) + * @{ + */ +#define MDM_FREQ__PAT_DLY__SHIFT 11 +#define MDM_FREQ__PAT_DLY__WIDTH 3 +#define MDM_FREQ__PAT_DLY__MASK 0x00003800U +#define MDM_FREQ__PAT_DLY__READ(src) (((uint32_t)(src) & 0x00003800U) >> 11) +#define MDM_FREQ__PAT_DLY__WRITE(src) (((uint32_t)(src) << 11) & 0x00003800U) +#define MDM_FREQ__PAT_DLY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((uint32_t)(src) <<\ + 11) & 0x00003800U) +#define MDM_FREQ__PAT_DLY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00003800U))) +#define MDM_FREQ__PAT_DLY__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field mu_count1 */ +/** + * @defgroup mdm_regs_core_mu_count1_field mu_count1_field + * @brief macros for field mu_count1 + * @details Number of bytes to process before switching from gear 1 to gear 2 + * @{ + */ +#define MDM_FREQ__MU_COUNT1__SHIFT 14 +#define MDM_FREQ__MU_COUNT1__WIDTH 8 +#define MDM_FREQ__MU_COUNT1__MASK 0x003fc000U +#define MDM_FREQ__MU_COUNT1__READ(src) (((uint32_t)(src) & 0x003fc000U) >> 14) +#define MDM_FREQ__MU_COUNT1__WRITE(src) (((uint32_t)(src) << 14) & 0x003fc000U) +#define MDM_FREQ__MU_COUNT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fc000U) | (((uint32_t)(src) <<\ + 14) & 0x003fc000U) +#define MDM_FREQ__MU_COUNT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x003fc000U))) +#define MDM_FREQ__MU_COUNT1__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field mu_count2 */ +/** + * @defgroup mdm_regs_core_mu_count2_field mu_count2_field + * @brief macros for field mu_count2 + * @details Number of bytes to process before switching to gear 3. (Includes bytes from gear 1 PLUS gear 2) + * @{ + */ +#define MDM_FREQ__MU_COUNT2__SHIFT 22 +#define MDM_FREQ__MU_COUNT2__WIDTH 8 +#define MDM_FREQ__MU_COUNT2__MASK 0x3fc00000U +#define MDM_FREQ__MU_COUNT2__READ(src) (((uint32_t)(src) & 0x3fc00000U) >> 22) +#define MDM_FREQ__MU_COUNT2__WRITE(src) (((uint32_t)(src) << 22) & 0x3fc00000U) +#define MDM_FREQ__MU_COUNT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3fc00000U) | (((uint32_t)(src) <<\ + 22) & 0x3fc00000U) +#define MDM_FREQ__MU_COUNT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x3fc00000U))) +#define MDM_FREQ__MU_COUNT2__RESET_VALUE 0x00000010U +/** @} */ +#define MDM_FREQ__TYPE uint32_t +#define MDM_FREQ__READ 0x3fffffffU +#define MDM_FREQ__WRITE 0x3fffffffU +#define MDM_FREQ__PRESERVED 0x00000000U +#define MDM_FREQ__RESET_VALUE 0x0401248dU + +#endif /* __MDM_FREQ_MACRO__ */ + +/** @} end of freq */ + +/* macros for BlueprintGlobalNameSpace::MDM_freqlim */ +/** + * @defgroup mdm_regs_core_freqlim freqlim + * @brief Specifies range of compensated soft demod values to be used for frequency tracking. Anything outside of this range is discarded. 0 to 512 is the full range of absolute values definitions. + * @{ + */ +#ifndef __MDM_FREQLIM_MACRO__ +#define __MDM_FREQLIM_MACRO__ + +/* macros for field maxwithffe */ +/** + * @defgroup mdm_regs_core_maxwithffe_field maxwithffe_field + * @brief macros for field maxwithffe + * @details max absolute value to be used in tracking + * @{ + */ +#define MDM_FREQLIM__MAXWITHFFE__SHIFT 0 +#define MDM_FREQLIM__MAXWITHFFE__WIDTH 9 +#define MDM_FREQLIM__MAXWITHFFE__MASK 0x000001ffU +#define MDM_FREQLIM__MAXWITHFFE__READ(src) ((uint32_t)(src) & 0x000001ffU) +#define MDM_FREQLIM__MAXWITHFFE__WRITE(src) ((uint32_t)(src) & 0x000001ffU) +#define MDM_FREQLIM__MAXWITHFFE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((uint32_t)(src) &\ + 0x000001ffU) +#define MDM_FREQLIM__MAXWITHFFE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000001ffU))) +#define MDM_FREQLIM__MAXWITHFFE__RESET_VALUE 0x000001ffU +/** @} */ + +/* macros for field minwithffe */ +/** + * @defgroup mdm_regs_core_minwithffe_field minwithffe_field + * @brief macros for field minwithffe + * @details min absolute value to be used in tracking + * @{ + */ +#define MDM_FREQLIM__MINWITHFFE__SHIFT 9 +#define MDM_FREQLIM__MINWITHFFE__WIDTH 7 +#define MDM_FREQLIM__MINWITHFFE__MASK 0x0000fe00U +#define MDM_FREQLIM__MINWITHFFE__READ(src) \ + (((uint32_t)(src)\ + & 0x0000fe00U) >> 9) +#define MDM_FREQLIM__MINWITHFFE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0000fe00U) +#define MDM_FREQLIM__MINWITHFFE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0000fe00U) +#define MDM_FREQLIM__MINWITHFFE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0000fe00U))) +#define MDM_FREQLIM__MINWITHFFE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field maxwithoutffe */ +/** + * @defgroup mdm_regs_core_maxwithoutffe_field maxwithoutffe_field + * @brief macros for field maxwithoutffe + * @details max absolute value to be used in tracking + * @{ + */ +#define MDM_FREQLIM__MAXWITHOUTFFE__SHIFT 16 +#define MDM_FREQLIM__MAXWITHOUTFFE__WIDTH 9 +#define MDM_FREQLIM__MAXWITHOUTFFE__MASK 0x01ff0000U +#define MDM_FREQLIM__MAXWITHOUTFFE__READ(src) \ + (((uint32_t)(src)\ + & 0x01ff0000U) >> 16) +#define MDM_FREQLIM__MAXWITHOUTFFE__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x01ff0000U) +#define MDM_FREQLIM__MAXWITHOUTFFE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x01ff0000U) +#define MDM_FREQLIM__MAXWITHOUTFFE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x01ff0000U))) +#define MDM_FREQLIM__MAXWITHOUTFFE__RESET_VALUE 0x000001ffU +/** @} */ + +/* macros for field minwithoutffe */ +/** + * @defgroup mdm_regs_core_minwithoutffe_field minwithoutffe_field + * @brief macros for field minwithoutffe + * @details min absolute value to be used in tracking + * @{ + */ +#define MDM_FREQLIM__MINWITHOUTFFE__SHIFT 25 +#define MDM_FREQLIM__MINWITHOUTFFE__WIDTH 7 +#define MDM_FREQLIM__MINWITHOUTFFE__MASK 0xfe000000U +#define MDM_FREQLIM__MINWITHOUTFFE__READ(src) \ + (((uint32_t)(src)\ + & 0xfe000000U) >> 25) +#define MDM_FREQLIM__MINWITHOUTFFE__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0xfe000000U) +#define MDM_FREQLIM__MINWITHOUTFFE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfe000000U) | (((uint32_t)(src) <<\ + 25) & 0xfe000000U) +#define MDM_FREQLIM__MINWITHOUTFFE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0xfe000000U))) +#define MDM_FREQLIM__MINWITHOUTFFE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_FREQLIM__TYPE uint32_t +#define MDM_FREQLIM__READ 0xffffffffU +#define MDM_FREQLIM__WRITE 0xffffffffU +#define MDM_FREQLIM__PRESERVED 0x00000000U +#define MDM_FREQLIM__RESET_VALUE 0x01ff01ffU + +#endif /* __MDM_FREQLIM_MACRO__ */ + +/** @} end of freqlim */ + +/* macros for BlueprintGlobalNameSpace::MDM_lr */ +/** + * @defgroup mdm_regs_core_lr lr + * @brief Long-range specific control registers definitions. + * @{ + */ +#ifndef __MDM_LR_MACRO__ +#define __MDM_LR_MACRO__ + +/* macros for field synch_detect_num_exp */ +/** + * @defgroup mdm_regs_core_synch_detect_num_exp_field synch_detect_num_exp_field + * @brief macros for field synch_detect_num_exp + * @details Number of frequency estimates for signal detection. Keep repeating measurement during detection. Encoding: 00 = 16 (10 symbols) 01 = 32 (12 symbols) 10 = 64 (16 symbols) 11 = 128 (24 symbols) + * @{ + */ +#define MDM_LR__SYNCH_DETECT_NUM_EXP__SHIFT 0 +#define MDM_LR__SYNCH_DETECT_NUM_EXP__WIDTH 2 +#define MDM_LR__SYNCH_DETECT_NUM_EXP__MASK 0x00000003U +#define MDM_LR__SYNCH_DETECT_NUM_EXP__READ(src) ((uint32_t)(src) & 0x00000003U) +#define MDM_LR__SYNCH_DETECT_NUM_EXP__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define MDM_LR__SYNCH_DETECT_NUM_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define MDM_LR__SYNCH_DETECT_NUM_EXP__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define MDM_LR__SYNCH_DETECT_NUM_EXP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field synch_num_exp */ +/** + * @defgroup mdm_regs_core_synch_num_exp_field synch_num_exp_field + * @brief macros for field synch_num_exp + * @details Number of frequency estimates for demodulation and number of averages for timing sync. Encoding: 00 = NA 01 = freq: 32; timing averages (1x); (12 symbols) 10 = freq: 64; timing averages (2x); (16 symbols) 11 = freq: 128; timing averages (4x); (24 symbols) + * @{ + */ +#define MDM_LR__SYNCH_NUM_EXP__SHIFT 2 +#define MDM_LR__SYNCH_NUM_EXP__WIDTH 2 +#define MDM_LR__SYNCH_NUM_EXP__MASK 0x0000000cU +#define MDM_LR__SYNCH_NUM_EXP__READ(src) (((uint32_t)(src) & 0x0000000cU) >> 2) +#define MDM_LR__SYNCH_NUM_EXP__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000000cU) +#define MDM_LR__SYNCH_NUM_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((uint32_t)(src) <<\ + 2) & 0x0000000cU) +#define MDM_LR__SYNCH_NUM_EXP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000000cU))) +#define MDM_LR__SYNCH_NUM_EXP__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field num_corr_win */ +/** + * @defgroup mdm_regs_core_num_corr_win_field num_corr_win_field + * @brief macros for field num_corr_win + * @details Number of 4 us windows to include in correlation. Max is 10. + * @{ + */ +#define MDM_LR__NUM_CORR_WIN__SHIFT 4 +#define MDM_LR__NUM_CORR_WIN__WIDTH 4 +#define MDM_LR__NUM_CORR_WIN__MASK 0x000000f0U +#define MDM_LR__NUM_CORR_WIN__READ(src) (((uint32_t)(src) & 0x000000f0U) >> 4) +#define MDM_LR__NUM_CORR_WIN__WRITE(src) (((uint32_t)(src) << 4) & 0x000000f0U) +#define MDM_LR__NUM_CORR_WIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define MDM_LR__NUM_CORR_WIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define MDM_LR__NUM_CORR_WIN__RESET_VALUE 0x00000009U +/** @} */ + +/* macros for field num_corr_avg */ +/** + * @defgroup mdm_regs_core_num_corr_avg_field num_corr_avg_field + * @brief macros for field num_corr_avg + * @details Number of phase differences to include in each 4 us (32 sample) window + * @{ + */ +#define MDM_LR__NUM_CORR_AVG__SHIFT 8 +#define MDM_LR__NUM_CORR_AVG__WIDTH 5 +#define MDM_LR__NUM_CORR_AVG__MASK 0x00001f00U +#define MDM_LR__NUM_CORR_AVG__READ(src) (((uint32_t)(src) & 0x00001f00U) >> 8) +#define MDM_LR__NUM_CORR_AVG__WRITE(src) (((uint32_t)(src) << 8) & 0x00001f00U) +#define MDM_LR__NUM_CORR_AVG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((uint32_t)(src) <<\ + 8) & 0x00001f00U) +#define MDM_LR__NUM_CORR_AVG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00001f00U))) +#define MDM_LR__NUM_CORR_AVG__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field corr_thresh_high */ +/** + * @defgroup mdm_regs_core_corr_thresh_high_field corr_thresh_high_field + * @brief macros for field corr_thresh_high + * @details Declare a detection if number of matches >= corr_thresh_high + * @{ + */ +#define MDM_LR__CORR_THRESH_HIGH__SHIFT 13 +#define MDM_LR__CORR_THRESH_HIGH__WIDTH 9 +#define MDM_LR__CORR_THRESH_HIGH__MASK 0x003fe000U +#define MDM_LR__CORR_THRESH_HIGH__READ(src) \ + (((uint32_t)(src)\ + & 0x003fe000U) >> 13) +#define MDM_LR__CORR_THRESH_HIGH__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x003fe000U) +#define MDM_LR__CORR_THRESH_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fe000U) | (((uint32_t)(src) <<\ + 13) & 0x003fe000U) +#define MDM_LR__CORR_THRESH_HIGH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x003fe000U))) +#define MDM_LR__CORR_THRESH_HIGH__RESET_VALUE 0x00000088U +/** @} */ + +/* macros for field corr_thresh_low */ +/** + * @defgroup mdm_regs_core_corr_thresh_low_field corr_thresh_low_field + * @brief macros for field corr_thresh_low + * @details Declare a detection if number of matches <= corr_thresh_low. Would expect to set to num_corr_win*num_corr_avg - corr_thresh_low + * @{ + */ +#define MDM_LR__CORR_THRESH_LOW__SHIFT 22 +#define MDM_LR__CORR_THRESH_LOW__WIDTH 8 +#define MDM_LR__CORR_THRESH_LOW__MASK 0x3fc00000U +#define MDM_LR__CORR_THRESH_LOW__READ(src) \ + (((uint32_t)(src)\ + & 0x3fc00000U) >> 22) +#define MDM_LR__CORR_THRESH_LOW__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x3fc00000U) +#define MDM_LR__CORR_THRESH_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3fc00000U) | (((uint32_t)(src) <<\ + 22) & 0x3fc00000U) +#define MDM_LR__CORR_THRESH_LOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x3fc00000U))) +#define MDM_LR__CORR_THRESH_LOW__RESET_VALUE 0x00000008U +/** @} */ +#define MDM_LR__TYPE uint32_t +#define MDM_LR__READ 0x3fffffffU +#define MDM_LR__WRITE 0x3fffffffU +#define MDM_LR__PRESERVED 0x00000000U +#define MDM_LR__RESET_VALUE 0x0211109cU + +#endif /* __MDM_LR_MACRO__ */ + +/** @} end of lr */ + +/* macros for BlueprintGlobalNameSpace::MDM_lr_alt */ +/** + * @defgroup mdm_regs_core_lr_alt lr_alt + * @brief Long-range specific control registers, alternate set definitions. + * @{ + */ +#ifndef __MDM_LR_ALT_MACRO__ +#define __MDM_LR_ALT_MACRO__ + +/* macros for field synch_detect_num_exp */ +/** + * @defgroup mdm_regs_core_synch_detect_num_exp_field synch_detect_num_exp_field + * @brief macros for field synch_detect_num_exp + * @details Number of frequency estimates for signal detection. Keep repeating measurement during detection. Encoding: 00 = 16 (10 symbols) 01 = 32 (12 symbols) 10 = 64 (16 symbols) 11 = 128 (24 symbols) + * @{ + */ +#define MDM_LR_ALT__SYNCH_DETECT_NUM_EXP__SHIFT 0 +#define MDM_LR_ALT__SYNCH_DETECT_NUM_EXP__WIDTH 2 +#define MDM_LR_ALT__SYNCH_DETECT_NUM_EXP__MASK 0x00000003U +#define MDM_LR_ALT__SYNCH_DETECT_NUM_EXP__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define MDM_LR_ALT__SYNCH_DETECT_NUM_EXP__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define MDM_LR_ALT__SYNCH_DETECT_NUM_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define MDM_LR_ALT__SYNCH_DETECT_NUM_EXP__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define MDM_LR_ALT__SYNCH_DETECT_NUM_EXP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field synch_num_exp */ +/** + * @defgroup mdm_regs_core_synch_num_exp_field synch_num_exp_field + * @brief macros for field synch_num_exp + * @details Number of frequency estimates for demodulation and number of averages for timing sync. Encoding: 00 = NA 01 = freq: 32; timing averages (1x); (12 symbols) 10 = freq: 64; timing averages (2x); (16 symbols) 11 = freq: 128; timing averages (4x); (24 symbols) + * @{ + */ +#define MDM_LR_ALT__SYNCH_NUM_EXP__SHIFT 2 +#define MDM_LR_ALT__SYNCH_NUM_EXP__WIDTH 2 +#define MDM_LR_ALT__SYNCH_NUM_EXP__MASK 0x0000000cU +#define MDM_LR_ALT__SYNCH_NUM_EXP__READ(src) \ + (((uint32_t)(src)\ + & 0x0000000cU) >> 2) +#define MDM_LR_ALT__SYNCH_NUM_EXP__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000000cU) +#define MDM_LR_ALT__SYNCH_NUM_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((uint32_t)(src) <<\ + 2) & 0x0000000cU) +#define MDM_LR_ALT__SYNCH_NUM_EXP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000000cU))) +#define MDM_LR_ALT__SYNCH_NUM_EXP__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field num_corr_win */ +/** + * @defgroup mdm_regs_core_num_corr_win_field num_corr_win_field + * @brief macros for field num_corr_win + * @details Number of 4 us windows to include in correlation. Max is 10. + * @{ + */ +#define MDM_LR_ALT__NUM_CORR_WIN__SHIFT 4 +#define MDM_LR_ALT__NUM_CORR_WIN__WIDTH 4 +#define MDM_LR_ALT__NUM_CORR_WIN__MASK 0x000000f0U +#define MDM_LR_ALT__NUM_CORR_WIN__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define MDM_LR_ALT__NUM_CORR_WIN__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x000000f0U) +#define MDM_LR_ALT__NUM_CORR_WIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define MDM_LR_ALT__NUM_CORR_WIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define MDM_LR_ALT__NUM_CORR_WIN__RESET_VALUE 0x00000009U +/** @} */ + +/* macros for field num_corr_avg */ +/** + * @defgroup mdm_regs_core_num_corr_avg_field num_corr_avg_field + * @brief macros for field num_corr_avg + * @details Number of phase differences to include in each 4 us (32 sample) window + * @{ + */ +#define MDM_LR_ALT__NUM_CORR_AVG__SHIFT 8 +#define MDM_LR_ALT__NUM_CORR_AVG__WIDTH 5 +#define MDM_LR_ALT__NUM_CORR_AVG__MASK 0x00001f00U +#define MDM_LR_ALT__NUM_CORR_AVG__READ(src) \ + (((uint32_t)(src)\ + & 0x00001f00U) >> 8) +#define MDM_LR_ALT__NUM_CORR_AVG__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00001f00U) +#define MDM_LR_ALT__NUM_CORR_AVG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((uint32_t)(src) <<\ + 8) & 0x00001f00U) +#define MDM_LR_ALT__NUM_CORR_AVG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00001f00U))) +#define MDM_LR_ALT__NUM_CORR_AVG__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field corr_thresh_high */ +/** + * @defgroup mdm_regs_core_corr_thresh_high_field corr_thresh_high_field + * @brief macros for field corr_thresh_high + * @details Declare a detection if number of matches >= corr_thresh_high + * @{ + */ +#define MDM_LR_ALT__CORR_THRESH_HIGH__SHIFT 13 +#define MDM_LR_ALT__CORR_THRESH_HIGH__WIDTH 9 +#define MDM_LR_ALT__CORR_THRESH_HIGH__MASK 0x003fe000U +#define MDM_LR_ALT__CORR_THRESH_HIGH__READ(src) \ + (((uint32_t)(src)\ + & 0x003fe000U) >> 13) +#define MDM_LR_ALT__CORR_THRESH_HIGH__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x003fe000U) +#define MDM_LR_ALT__CORR_THRESH_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fe000U) | (((uint32_t)(src) <<\ + 13) & 0x003fe000U) +#define MDM_LR_ALT__CORR_THRESH_HIGH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x003fe000U))) +#define MDM_LR_ALT__CORR_THRESH_HIGH__RESET_VALUE 0x00000088U +/** @} */ + +/* macros for field corr_thresh_low */ +/** + * @defgroup mdm_regs_core_corr_thresh_low_field corr_thresh_low_field + * @brief macros for field corr_thresh_low + * @details Declare a detection if number of matches <= corr_thresh_low. Would expect to set to num_corr_win*num_corr_avg - corr_thresh_low + * @{ + */ +#define MDM_LR_ALT__CORR_THRESH_LOW__SHIFT 22 +#define MDM_LR_ALT__CORR_THRESH_LOW__WIDTH 8 +#define MDM_LR_ALT__CORR_THRESH_LOW__MASK 0x3fc00000U +#define MDM_LR_ALT__CORR_THRESH_LOW__READ(src) \ + (((uint32_t)(src)\ + & 0x3fc00000U) >> 22) +#define MDM_LR_ALT__CORR_THRESH_LOW__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x3fc00000U) +#define MDM_LR_ALT__CORR_THRESH_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3fc00000U) | (((uint32_t)(src) <<\ + 22) & 0x3fc00000U) +#define MDM_LR_ALT__CORR_THRESH_LOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x3fc00000U))) +#define MDM_LR_ALT__CORR_THRESH_LOW__RESET_VALUE 0x00000008U +/** @} */ +#define MDM_LR_ALT__TYPE uint32_t +#define MDM_LR_ALT__READ 0x3fffffffU +#define MDM_LR_ALT__WRITE 0x3fffffffU +#define MDM_LR_ALT__PRESERVED 0x00000000U +#define MDM_LR_ALT__RESET_VALUE 0x0211109cU + +#endif /* __MDM_LR_ALT_MACRO__ */ + +/** @} end of lr_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_mixer */ +/** + * @defgroup mdm_regs_core_mixer mixer + * @brief Low IF frequency. definitions. + * @{ + */ +#ifndef __MDM_MIXER_MACRO__ +#define __MDM_MIXER_MACRO__ + +/* macros for field low_if_freq */ +/** + * @defgroup mdm_regs_core_low_if_freq_field low_if_freq_field + * @brief macros for field low_if_freq + * @details Units are in 1/1024 MHz. 0.8 / (1/1024) = 819 + * @{ + */ +#define MDM_MIXER__LOW_IF_FREQ__SHIFT 0 +#define MDM_MIXER__LOW_IF_FREQ__WIDTH 14 +#define MDM_MIXER__LOW_IF_FREQ__MASK 0x00003fffU +#define MDM_MIXER__LOW_IF_FREQ__READ(src) ((uint32_t)(src) & 0x00003fffU) +#define MDM_MIXER__LOW_IF_FREQ__WRITE(src) ((uint32_t)(src) & 0x00003fffU) +#define MDM_MIXER__LOW_IF_FREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((uint32_t)(src) &\ + 0x00003fffU) +#define MDM_MIXER__LOW_IF_FREQ__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00003fffU))) +#define MDM_MIXER__LOW_IF_FREQ__RESET_VALUE 0x00000333U +/** @} */ + +/* macros for field twomeg_low_if_freq */ +/** + * @defgroup mdm_regs_core_twomeg_low_if_freq_field twomeg_low_if_freq_field + * @brief macros for field twomeg_low_if_freq + * @details Units are in 1/1024 MHz. 1.6 / (1/1024) = 1638 + * @{ + */ +#define MDM_MIXER__TWOMEG_LOW_IF_FREQ__SHIFT 14 +#define MDM_MIXER__TWOMEG_LOW_IF_FREQ__WIDTH 14 +#define MDM_MIXER__TWOMEG_LOW_IF_FREQ__MASK 0x0fffc000U +#define MDM_MIXER__TWOMEG_LOW_IF_FREQ__READ(src) \ + (((uint32_t)(src)\ + & 0x0fffc000U) >> 14) +#define MDM_MIXER__TWOMEG_LOW_IF_FREQ__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0fffc000U) +#define MDM_MIXER__TWOMEG_LOW_IF_FREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((uint32_t)(src) <<\ + 14) & 0x0fffc000U) +#define MDM_MIXER__TWOMEG_LOW_IF_FREQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define MDM_MIXER__TWOMEG_LOW_IF_FREQ__RESET_VALUE 0x00000666U +/** @} */ +#define MDM_MIXER__TYPE uint32_t +#define MDM_MIXER__READ 0x0fffffffU +#define MDM_MIXER__WRITE 0x0fffffffU +#define MDM_MIXER__PRESERVED 0x00000000U +#define MDM_MIXER__RESET_VALUE 0x01998333U + +#endif /* __MDM_MIXER_MACRO__ */ + +/** @} end of mixer */ + +/* macros for BlueprintGlobalNameSpace::MDM_access_address */ +/** + * @defgroup mdm_regs_core_access_address access_address + * @brief Access address control definitions. + * @{ + */ +#ifndef __MDM_ACCESS_ADDRESS_MACRO__ +#define __MDM_ACCESS_ADDRESS_MACRO__ + +/* macros for field match_thr */ +/** + * @defgroup mdm_regs_core_match_thr_field match_thr_field + * @brief macros for field match_thr + * @details Number of access address bits that need to match. 32 = all. + * @{ + */ +#define MDM_ACCESS_ADDRESS__MATCH_THR__SHIFT 0 +#define MDM_ACCESS_ADDRESS__MATCH_THR__WIDTH 6 +#define MDM_ACCESS_ADDRESS__MATCH_THR__MASK 0x0000003fU +#define MDM_ACCESS_ADDRESS__MATCH_THR__READ(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_ACCESS_ADDRESS__MATCH_THR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_ACCESS_ADDRESS__MATCH_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define MDM_ACCESS_ADDRESS__MATCH_THR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define MDM_ACCESS_ADDRESS__MATCH_THR__RESET_VALUE 0x00000020U +/** @} */ + +/* macros for field lsb_auto_match */ +/** + * @defgroup mdm_regs_core_lsb_auto_match_field lsb_auto_match_field + * @brief macros for field lsb_auto_match + * @details Automatically match the specified bits of the access address. lsb of this field is lsb of access address. msb of this field is bit 3 of access address + * @{ + */ +#define MDM_ACCESS_ADDRESS__LSB_AUTO_MATCH__SHIFT 6 +#define MDM_ACCESS_ADDRESS__LSB_AUTO_MATCH__WIDTH 4 +#define MDM_ACCESS_ADDRESS__LSB_AUTO_MATCH__MASK 0x000003c0U +#define MDM_ACCESS_ADDRESS__LSB_AUTO_MATCH__READ(src) \ + (((uint32_t)(src)\ + & 0x000003c0U) >> 6) +#define MDM_ACCESS_ADDRESS__LSB_AUTO_MATCH__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000003c0U) +#define MDM_ACCESS_ADDRESS__LSB_AUTO_MATCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003c0U) | (((uint32_t)(src) <<\ + 6) & 0x000003c0U) +#define MDM_ACCESS_ADDRESS__LSB_AUTO_MATCH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000003c0U))) +#define MDM_ACCESS_ADDRESS__LSB_AUTO_MATCH__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field enable_coded_timeout */ +/** + * @defgroup mdm_regs_core_enable_coded_timeout_field enable_coded_timeout_field + * @brief macros for field enable_coded_timeout + * @details Timeout after having seen the specified number of symbols after frequency and timing sync, coded rates + * @{ + */ +#define MDM_ACCESS_ADDRESS__ENABLE_CODED_TIMEOUT__SHIFT 10 +#define MDM_ACCESS_ADDRESS__ENABLE_CODED_TIMEOUT__WIDTH 1 +#define MDM_ACCESS_ADDRESS__ENABLE_CODED_TIMEOUT__MASK 0x00000400U +#define MDM_ACCESS_ADDRESS__ENABLE_CODED_TIMEOUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define MDM_ACCESS_ADDRESS__ENABLE_CODED_TIMEOUT__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define MDM_ACCESS_ADDRESS__ENABLE_CODED_TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define MDM_ACCESS_ADDRESS__ENABLE_CODED_TIMEOUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define MDM_ACCESS_ADDRESS__ENABLE_CODED_TIMEOUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define MDM_ACCESS_ADDRESS__ENABLE_CODED_TIMEOUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define MDM_ACCESS_ADDRESS__ENABLE_CODED_TIMEOUT__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field coded_bit_count_timeout */ +/** + * @defgroup mdm_regs_core_coded_bit_count_timeout_field coded_bit_count_timeout_field + * @brief macros for field coded_bit_count_timeout + * @details Number of symbols to declare timeout, coded rates + * @{ + */ +#define MDM_ACCESS_ADDRESS__CODED_BIT_COUNT_TIMEOUT__SHIFT 12 +#define MDM_ACCESS_ADDRESS__CODED_BIT_COUNT_TIMEOUT__WIDTH 12 +#define MDM_ACCESS_ADDRESS__CODED_BIT_COUNT_TIMEOUT__MASK 0x00fff000U +#define MDM_ACCESS_ADDRESS__CODED_BIT_COUNT_TIMEOUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00fff000U) >> 12) +#define MDM_ACCESS_ADDRESS__CODED_BIT_COUNT_TIMEOUT__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00fff000U) +#define MDM_ACCESS_ADDRESS__CODED_BIT_COUNT_TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fff000U) | (((uint32_t)(src) <<\ + 12) & 0x00fff000U) +#define MDM_ACCESS_ADDRESS__CODED_BIT_COUNT_TIMEOUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00fff000U))) +#define MDM_ACCESS_ADDRESS__CODED_BIT_COUNT_TIMEOUT__RESET_VALUE 0x0000017cU +/** @} */ +#define MDM_ACCESS_ADDRESS__TYPE uint32_t +#define MDM_ACCESS_ADDRESS__READ 0x00fff7ffU +#define MDM_ACCESS_ADDRESS__WRITE 0x00fff7ffU +#define MDM_ACCESS_ADDRESS__PRESERVED 0x00000000U +#define MDM_ACCESS_ADDRESS__RESET_VALUE 0x0017c460U + +#endif /* __MDM_ACCESS_ADDRESS_MACRO__ */ + +/** @} end of access_address */ + +/* macros for BlueprintGlobalNameSpace::MDM_mode */ +/** + * @defgroup mdm_regs_core_mode mode + * @brief Mode control definitions. + * @{ + */ +#ifndef __MDM_MODE_MACRO__ +#define __MDM_MODE_MACRO__ + +/* macros for field pmode */ +/** + * @defgroup mdm_regs_core_pmode_field pmode_field + * @brief macros for field pmode + * @details 2'b00 = DUAL, normal mode, dual conversion, both I and Q 2'b01 = SINGLE, single conversion, both I and Q 2'b10 = LP_DUAL, low power mode, dual conversion. Within mdm, only I is used 2'b11 = LP_SINGLE, low power mode, single conversion. Within mdm, only I is used + * @{ + */ +#define MDM_MODE__PMODE__SHIFT 0 +#define MDM_MODE__PMODE__WIDTH 2 +#define MDM_MODE__PMODE__MASK 0x00000003U +#define MDM_MODE__PMODE__READ(src) ((uint32_t)(src) & 0x00000003U) +#define MDM_MODE__PMODE__WRITE(src) ((uint32_t)(src) & 0x00000003U) +#define MDM_MODE__PMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define MDM_MODE__PMODE__VERIFY(src) (!(((uint32_t)(src) & ~0x00000003U))) +#define MDM_MODE__PMODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mod_mode */ +/** + * @defgroup mdm_regs_core_mod_mode_field mod_mode_field + * @brief macros for field mod_mode + * @details TX modulation mode for radio 00 -> No modulation 01 -> use radio LUT like sydney with tx_data[6] 10 -> bypass radio LUT for 15.4, potentially use another LUT 11 -> bypass all LUTs, directly apply tx_data[6:0] for DTOP bypass + * @{ + */ +#define MDM_MODE__MOD_MODE__SHIFT 2 +#define MDM_MODE__MOD_MODE__WIDTH 2 +#define MDM_MODE__MOD_MODE__MASK 0x0000000cU +#define MDM_MODE__MOD_MODE__READ(src) (((uint32_t)(src) & 0x0000000cU) >> 2) +#define MDM_MODE__MOD_MODE__WRITE(src) (((uint32_t)(src) << 2) & 0x0000000cU) +#define MDM_MODE__MOD_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((uint32_t)(src) <<\ + 2) & 0x0000000cU) +#define MDM_MODE__MOD_MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000000cU))) +#define MDM_MODE__MOD_MODE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field force_rx_en */ +/** + * @defgroup mdm_regs_core_force_rx_en_field force_rx_en_field + * @brief macros for field force_rx_en + * @details Ignore rx_en value from LC + * @{ + */ +#define MDM_MODE__FORCE_RX_EN__SHIFT 4 +#define MDM_MODE__FORCE_RX_EN__WIDTH 1 +#define MDM_MODE__FORCE_RX_EN__MASK 0x00000010U +#define MDM_MODE__FORCE_RX_EN__READ(src) (((uint32_t)(src) & 0x00000010U) >> 4) +#define MDM_MODE__FORCE_RX_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define MDM_MODE__FORCE_RX_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define MDM_MODE__FORCE_RX_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define MDM_MODE__FORCE_RX_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define MDM_MODE__FORCE_RX_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define MDM_MODE__FORCE_RX_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field forced_rx_en_value */ +/** + * @defgroup mdm_regs_core_forced_rx_en_value_field forced_rx_en_value_field + * @brief macros for field forced_rx_en_value + * @details If force_rx_en set, use this value instead + * @{ + */ +#define MDM_MODE__FORCED_RX_EN_VALUE__SHIFT 5 +#define MDM_MODE__FORCED_RX_EN_VALUE__WIDTH 1 +#define MDM_MODE__FORCED_RX_EN_VALUE__MASK 0x00000020U +#define MDM_MODE__FORCED_RX_EN_VALUE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define MDM_MODE__FORCED_RX_EN_VALUE__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define MDM_MODE__FORCED_RX_EN_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define MDM_MODE__FORCED_RX_EN_VALUE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define MDM_MODE__FORCED_RX_EN_VALUE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define MDM_MODE__FORCED_RX_EN_VALUE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define MDM_MODE__FORCED_RX_EN_VALUE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field force_reg_bank */ +/** + * @defgroup mdm_regs_core_force_reg_bank_field force_reg_bank_field + * @brief macros for field force_reg_bank + * @details 0: Use lc_select_alt_regs 1: Use reg_bank field + * @{ + */ +#define MDM_MODE__FORCE_REG_BANK__SHIFT 6 +#define MDM_MODE__FORCE_REG_BANK__WIDTH 1 +#define MDM_MODE__FORCE_REG_BANK__MASK 0x00000040U +#define MDM_MODE__FORCE_REG_BANK__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define MDM_MODE__FORCE_REG_BANK__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define MDM_MODE__FORCE_REG_BANK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define MDM_MODE__FORCE_REG_BANK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define MDM_MODE__FORCE_REG_BANK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define MDM_MODE__FORCE_REG_BANK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define MDM_MODE__FORCE_REG_BANK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reg_bank */ +/** + * @defgroup mdm_regs_core_reg_bank_field reg_bank_field + * @brief macros for field reg_bank + * @details Register bank to select if forced. 0 = standard. 1 = alternate + * @{ + */ +#define MDM_MODE__REG_BANK__SHIFT 7 +#define MDM_MODE__REG_BANK__WIDTH 1 +#define MDM_MODE__REG_BANK__MASK 0x00000080U +#define MDM_MODE__REG_BANK__READ(src) (((uint32_t)(src) & 0x00000080U) >> 7) +#define MDM_MODE__REG_BANK__WRITE(src) (((uint32_t)(src) << 7) & 0x00000080U) +#define MDM_MODE__REG_BANK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define MDM_MODE__REG_BANK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define MDM_MODE__REG_BANK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define MDM_MODE__REG_BANK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define MDM_MODE__REG_BANK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field invert_reg_select_from_lc */ +/** + * @defgroup mdm_regs_core_invert_reg_select_from_lc_field invert_reg_select_from_lc_field + * @brief macros for field invert_reg_select_from_lc + * @details If set, invert lc_select_alt_regs + * @{ + */ +#define MDM_MODE__INVERT_REG_SELECT_FROM_LC__SHIFT 8 +#define MDM_MODE__INVERT_REG_SELECT_FROM_LC__WIDTH 1 +#define MDM_MODE__INVERT_REG_SELECT_FROM_LC__MASK 0x00000100U +#define MDM_MODE__INVERT_REG_SELECT_FROM_LC__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define MDM_MODE__INVERT_REG_SELECT_FROM_LC__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define MDM_MODE__INVERT_REG_SELECT_FROM_LC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define MDM_MODE__INVERT_REG_SELECT_FROM_LC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define MDM_MODE__INVERT_REG_SELECT_FROM_LC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define MDM_MODE__INVERT_REG_SELECT_FROM_LC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define MDM_MODE__INVERT_REG_SELECT_FROM_LC__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_MODE__TYPE uint32_t +#define MDM_MODE__READ 0x000001ffU +#define MDM_MODE__WRITE 0x000001ffU +#define MDM_MODE__PRESERVED 0x00000000U +#define MDM_MODE__RESET_VALUE 0x00000004U + +#endif /* __MDM_MODE_MACRO__ */ + +/** @} end of mode */ + +/* macros for BlueprintGlobalNameSpace::MDM_dccal */ +/** + * @defgroup mdm_regs_core_dccal dccal + * @brief DC offset calibration control for TIA for sydney definitions. + * @{ + */ +#ifndef __MDM_DCCAL_MACRO__ +#define __MDM_DCCAL_MACRO__ + +/* macros for field byp */ +/** + * @defgroup mdm_regs_core_byp_field byp_field + * @brief macros for field byp + * @details bypass DC calibration + * @{ + */ +#define MDM_DCCAL__BYP__SHIFT 0 +#define MDM_DCCAL__BYP__WIDTH 1 +#define MDM_DCCAL__BYP__MASK 0x00000001U +#define MDM_DCCAL__BYP__READ(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_DCCAL__BYP__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_DCCAL__BYP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define MDM_DCCAL__BYP__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define MDM_DCCAL__BYP__SET(dst) (dst) = ((dst) & ~0x00000001U) | (uint32_t)(1) +#define MDM_DCCAL__BYP__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (uint32_t)(0) +#define MDM_DCCAL__BYP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field start */ +/** + * @defgroup mdm_regs_core_start_field start_field + * @brief macros for field start + * @details software trigger DC calibration start + * @{ + */ +#define MDM_DCCAL__START__SHIFT 1 +#define MDM_DCCAL__START__WIDTH 1 +#define MDM_DCCAL__START__MASK 0x00000002U +#define MDM_DCCAL__START__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define MDM_DCCAL__START__WRITE(src) (((uint32_t)(src) << 1) & 0x00000002U) +#define MDM_DCCAL__START__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define MDM_DCCAL__START__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define MDM_DCCAL__START__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define MDM_DCCAL__START__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define MDM_DCCAL__START__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field avg_only */ +/** + * @defgroup mdm_regs_core_avg_only_field avg_only_field + * @brief macros for field avg_only + * @details software trigger DC calibration start average only cal + * @{ + */ +#define MDM_DCCAL__AVG_ONLY__SHIFT 2 +#define MDM_DCCAL__AVG_ONLY__WIDTH 1 +#define MDM_DCCAL__AVG_ONLY__MASK 0x00000004U +#define MDM_DCCAL__AVG_ONLY__READ(src) (((uint32_t)(src) & 0x00000004U) >> 2) +#define MDM_DCCAL__AVG_ONLY__WRITE(src) (((uint32_t)(src) << 2) & 0x00000004U) +#define MDM_DCCAL__AVG_ONLY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define MDM_DCCAL__AVG_ONLY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define MDM_DCCAL__AVG_ONLY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define MDM_DCCAL__AVG_ONLY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define MDM_DCCAL__AVG_ONLY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field avg_cnt_exp */ +/** + * @defgroup mdm_regs_core_avg_cnt_exp_field avg_cnt_exp_field + * @brief macros for field avg_cnt_exp + * @details 2's power number of samples to average; valid values [2-6] + * @{ + */ +#define MDM_DCCAL__AVG_CNT_EXP__SHIFT 4 +#define MDM_DCCAL__AVG_CNT_EXP__WIDTH 3 +#define MDM_DCCAL__AVG_CNT_EXP__MASK 0x00000070U +#define MDM_DCCAL__AVG_CNT_EXP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000070U) >> 4) +#define MDM_DCCAL__AVG_CNT_EXP__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000070U) +#define MDM_DCCAL__AVG_CNT_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((uint32_t)(src) <<\ + 4) & 0x00000070U) +#define MDM_DCCAL__AVG_CNT_EXP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000070U))) +#define MDM_DCCAL__AVG_CNT_EXP__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field srch_bit_cnt */ +/** + * @defgroup mdm_regs_core_srch_bit_cnt_field srch_bit_cnt_field + * @brief macros for field srch_bit_cnt + * @details number of DC offset bits to search + * @{ + */ +#define MDM_DCCAL__SRCH_BIT_CNT__SHIFT 7 +#define MDM_DCCAL__SRCH_BIT_CNT__WIDTH 4 +#define MDM_DCCAL__SRCH_BIT_CNT__MASK 0x00000780U +#define MDM_DCCAL__SRCH_BIT_CNT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000780U) >> 7) +#define MDM_DCCAL__SRCH_BIT_CNT__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000780U) +#define MDM_DCCAL__SRCH_BIT_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000780U) | (((uint32_t)(src) <<\ + 7) & 0x00000780U) +#define MDM_DCCAL__SRCH_BIT_CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000780U))) +#define MDM_DCCAL__SRCH_BIT_CNT__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field msb */ +/** + * @defgroup mdm_regs_core_msb_field msb_field + * @brief macros for field msb + * @details 0 => 5, 1 => 6, 2 => 7, 3 => 8 + * @{ + */ +#define MDM_DCCAL__MSB__SHIFT 12 +#define MDM_DCCAL__MSB__WIDTH 3 +#define MDM_DCCAL__MSB__MASK 0x00007000U +#define MDM_DCCAL__MSB__READ(src) (((uint32_t)(src) & 0x00007000U) >> 12) +#define MDM_DCCAL__MSB__WRITE(src) (((uint32_t)(src) << 12) & 0x00007000U) +#define MDM_DCCAL__MSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((uint32_t)(src) <<\ + 12) & 0x00007000U) +#define MDM_DCCAL__MSB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00007000U))) +#define MDM_DCCAL__MSB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field iq_ratio */ +/** + * @defgroup mdm_regs_core_iq_ratio_field iq_ratio_field + * @brief macros for field iq_ratio + * @details cross coupling ratio between i and q channel for 1 Mb/s; valid format u1.7 + * @{ + */ +#define MDM_DCCAL__IQ_RATIO__SHIFT 16 +#define MDM_DCCAL__IQ_RATIO__WIDTH 8 +#define MDM_DCCAL__IQ_RATIO__MASK 0x00ff0000U +#define MDM_DCCAL__IQ_RATIO__READ(src) (((uint32_t)(src) & 0x00ff0000U) >> 16) +#define MDM_DCCAL__IQ_RATIO__WRITE(src) (((uint32_t)(src) << 16) & 0x00ff0000U) +#define MDM_DCCAL__IQ_RATIO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MDM_DCCAL__IQ_RATIO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define MDM_DCCAL__IQ_RATIO__RESET_VALUE 0x000000b2U +/** @} */ + +/* macros for field iq_ratio_twomeg */ +/** + * @defgroup mdm_regs_core_iq_ratio_twomeg_field iq_ratio_twomeg_field + * @brief macros for field iq_ratio_twomeg + * @details cross coupling ratio between i and q channel for 2 Mb/s; valid format u1.7 + * @{ + */ +#define MDM_DCCAL__IQ_RATIO_TWOMEG__SHIFT 24 +#define MDM_DCCAL__IQ_RATIO_TWOMEG__WIDTH 8 +#define MDM_DCCAL__IQ_RATIO_TWOMEG__MASK 0xff000000U +#define MDM_DCCAL__IQ_RATIO_TWOMEG__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define MDM_DCCAL__IQ_RATIO_TWOMEG__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define MDM_DCCAL__IQ_RATIO_TWOMEG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define MDM_DCCAL__IQ_RATIO_TWOMEG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define MDM_DCCAL__IQ_RATIO_TWOMEG__RESET_VALUE 0x000000b2U +/** @} */ +#define MDM_DCCAL__TYPE uint32_t +#define MDM_DCCAL__READ 0xffff77f7U +#define MDM_DCCAL__WRITE 0xffff77f7U +#define MDM_DCCAL__PRESERVED 0x00000000U +#define MDM_DCCAL__RESET_VALUE 0xb2b20330U + +#endif /* __MDM_DCCAL_MACRO__ */ + +/** @} end of dccal */ + +/* macros for BlueprintGlobalNameSpace::MDM_dccal2 */ +/** + * @defgroup mdm_regs_core_dccal2 dccal2 + * @brief DC offset calibration control for TIA, set 2 for sydney definitions. + * @{ + */ +#ifndef __MDM_DCCAL2_MACRO__ +#define __MDM_DCCAL2_MACRO__ + +/* macros for field rf_post_dccal_sttl_cnt */ +/** + * @defgroup mdm_regs_core_rf_post_dccal_sttl_cnt_field rf_post_dccal_sttl_cnt_field + * @brief macros for field rf_post_dccal_sttl_cnt + * @details number of 16 MHz clocks from rf to settle after caldc is deasserted. MUST BE EVEN + * @{ + */ +#define MDM_DCCAL2__RF_POST_DCCAL_STTL_CNT__SHIFT 0 +#define MDM_DCCAL2__RF_POST_DCCAL_STTL_CNT__WIDTH 10 +#define MDM_DCCAL2__RF_POST_DCCAL_STTL_CNT__MASK 0x000003ffU +#define MDM_DCCAL2__RF_POST_DCCAL_STTL_CNT__READ(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define MDM_DCCAL2__RF_POST_DCCAL_STTL_CNT__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define MDM_DCCAL2__RF_POST_DCCAL_STTL_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define MDM_DCCAL2__RF_POST_DCCAL_STTL_CNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define MDM_DCCAL2__RF_POST_DCCAL_STTL_CNT__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field rf_sttl_cnt */ +/** + * @defgroup mdm_regs_core_rf_sttl_cnt_field rf_sttl_cnt_field + * @brief macros for field rf_sttl_cnt + * @details number of 16 MHz clocks from rf to settle after tia gain change for 1 Mb/s. MUST BE EVEN + * @{ + */ +#define MDM_DCCAL2__RF_STTL_CNT__SHIFT 10 +#define MDM_DCCAL2__RF_STTL_CNT__WIDTH 10 +#define MDM_DCCAL2__RF_STTL_CNT__MASK 0x000ffc00U +#define MDM_DCCAL2__RF_STTL_CNT__READ(src) \ + (((uint32_t)(src)\ + & 0x000ffc00U) >> 10) +#define MDM_DCCAL2__RF_STTL_CNT__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x000ffc00U) +#define MDM_DCCAL2__RF_STTL_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define MDM_DCCAL2__RF_STTL_CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define MDM_DCCAL2__RF_STTL_CNT__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field rf_sttl_cnt_twomeg */ +/** + * @defgroup mdm_regs_core_rf_sttl_cnt_twomeg_field rf_sttl_cnt_twomeg_field + * @brief macros for field rf_sttl_cnt_twomeg + * @details number of 16 MHz clocks from rf to settle after tia gain change for 2 Mb/s + * @{ + */ +#define MDM_DCCAL2__RF_STTL_CNT_TWOMEG__SHIFT 20 +#define MDM_DCCAL2__RF_STTL_CNT_TWOMEG__WIDTH 10 +#define MDM_DCCAL2__RF_STTL_CNT_TWOMEG__MASK 0x3ff00000U +#define MDM_DCCAL2__RF_STTL_CNT_TWOMEG__READ(src) \ + (((uint32_t)(src)\ + & 0x3ff00000U) >> 20) +#define MDM_DCCAL2__RF_STTL_CNT_TWOMEG__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x3ff00000U) +#define MDM_DCCAL2__RF_STTL_CNT_TWOMEG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define MDM_DCCAL2__RF_STTL_CNT_TWOMEG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define MDM_DCCAL2__RF_STTL_CNT_TWOMEG__RESET_VALUE 0x00000010U +/** @} */ +#define MDM_DCCAL2__TYPE uint32_t +#define MDM_DCCAL2__READ 0x3fffffffU +#define MDM_DCCAL2__WRITE 0x3fffffffU +#define MDM_DCCAL2__PRESERVED 0x00000000U +#define MDM_DCCAL2__RESET_VALUE 0x01004010U + +#endif /* __MDM_DCCAL2_MACRO__ */ + +/** @} end of dccal2 */ + +/* macros for BlueprintGlobalNameSpace::MDM_dccal_ctrl */ +/** + * @defgroup mdm_regs_core_dccal_ctrl dccal_ctrl + * @brief Global calibration control for paris definitions. + * @{ + */ +#ifndef __MDM_DCCAL_CTRL_MACRO__ +#define __MDM_DCCAL_CTRL_MACRO__ + +/* macros for field byp */ +/** + * @defgroup mdm_regs_core_byp_field byp_field + * @brief macros for field byp + * @details bypass DC calibration + * @{ + */ +#define MDM_DCCAL_CTRL__BYP__SHIFT 0 +#define MDM_DCCAL_CTRL__BYP__WIDTH 1 +#define MDM_DCCAL_CTRL__BYP__MASK 0x00000001U +#define MDM_DCCAL_CTRL__BYP__READ(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_DCCAL_CTRL__BYP__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_DCCAL_CTRL__BYP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define MDM_DCCAL_CTRL__BYP__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define MDM_DCCAL_CTRL__BYP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_DCCAL_CTRL__BYP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_DCCAL_CTRL__BYP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field start */ +/** + * @defgroup mdm_regs_core_start_field start_field + * @brief macros for field start + * @details software trigger DC calibration start + * @{ + */ +#define MDM_DCCAL_CTRL__START__SHIFT 1 +#define MDM_DCCAL_CTRL__START__WIDTH 1 +#define MDM_DCCAL_CTRL__START__MASK 0x00000002U +#define MDM_DCCAL_CTRL__START__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define MDM_DCCAL_CTRL__START__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define MDM_DCCAL_CTRL__START__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define MDM_DCCAL_CTRL__START__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define MDM_DCCAL_CTRL__START__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define MDM_DCCAL_CTRL__START__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define MDM_DCCAL_CTRL__START__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mode */ +/** + * @defgroup mdm_regs_core_mode_field mode_field + * @brief macros for field mode + * @details 0 => TIA cal, 1 => PGA cal, 2 => notch cal + * @{ + */ +#define MDM_DCCAL_CTRL__MODE__SHIFT 2 +#define MDM_DCCAL_CTRL__MODE__WIDTH 3 +#define MDM_DCCAL_CTRL__MODE__MASK 0x0000001cU +#define MDM_DCCAL_CTRL__MODE__READ(src) (((uint32_t)(src) & 0x0000001cU) >> 2) +#define MDM_DCCAL_CTRL__MODE__WRITE(src) (((uint32_t)(src) << 2) & 0x0000001cU) +#define MDM_DCCAL_CTRL__MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((uint32_t)(src) <<\ + 2) & 0x0000001cU) +#define MDM_DCCAL_CTRL__MODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000001cU))) +#define MDM_DCCAL_CTRL__MODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field force_res_corr */ +/** + * @defgroup mdm_regs_core_force_res_corr_field force_res_corr_field + * @brief macros for field force_res_corr + * @details 0 => only go to residue correction when dccal is triggered, 1 => go to residue correction when dccal is bypassed and bb1dcoc and bb2dcoc are latched + * @{ + */ +#define MDM_DCCAL_CTRL__FORCE_RES_CORR__SHIFT 5 +#define MDM_DCCAL_CTRL__FORCE_RES_CORR__WIDTH 1 +#define MDM_DCCAL_CTRL__FORCE_RES_CORR__MASK 0x00000020U +#define MDM_DCCAL_CTRL__FORCE_RES_CORR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define MDM_DCCAL_CTRL__FORCE_RES_CORR__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define MDM_DCCAL_CTRL__FORCE_RES_CORR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define MDM_DCCAL_CTRL__FORCE_RES_CORR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define MDM_DCCAL_CTRL__FORCE_RES_CORR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define MDM_DCCAL_CTRL__FORCE_RES_CORR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define MDM_DCCAL_CTRL__FORCE_RES_CORR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field use_cal_gain_pga_off */ +/** + * @defgroup mdm_regs_core_use_cal_gain_pga_off_field use_cal_gain_pga_off_field + * @brief macros for field use_cal_gain_pga_off + * @details 0 => do not use gain adjusted pga offset, 1 => use gain adjusted pga offset + * @{ + */ +#define MDM_DCCAL_CTRL__USE_CAL_GAIN_PGA_OFF__SHIFT 6 +#define MDM_DCCAL_CTRL__USE_CAL_GAIN_PGA_OFF__WIDTH 1 +#define MDM_DCCAL_CTRL__USE_CAL_GAIN_PGA_OFF__MASK 0x00000040U +#define MDM_DCCAL_CTRL__USE_CAL_GAIN_PGA_OFF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define MDM_DCCAL_CTRL__USE_CAL_GAIN_PGA_OFF__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define MDM_DCCAL_CTRL__USE_CAL_GAIN_PGA_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define MDM_DCCAL_CTRL__USE_CAL_GAIN_PGA_OFF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define MDM_DCCAL_CTRL__USE_CAL_GAIN_PGA_OFF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define MDM_DCCAL_CTRL__USE_CAL_GAIN_PGA_OFF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define MDM_DCCAL_CTRL__USE_CAL_GAIN_PGA_OFF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field use_eq_lp_pga_off */ +/** + * @defgroup mdm_regs_core_use_eq_lp_pga_off_field use_eq_lp_pga_off_field + * @brief macros for field use_eq_lp_pga_off + * @details 0 => do not use equation based lp PGA during cal state, 1 => use equation based lp PGA during cal state + * @{ + */ +#define MDM_DCCAL_CTRL__USE_EQ_LP_PGA_OFF__SHIFT 7 +#define MDM_DCCAL_CTRL__USE_EQ_LP_PGA_OFF__WIDTH 1 +#define MDM_DCCAL_CTRL__USE_EQ_LP_PGA_OFF__MASK 0x00000080U +#define MDM_DCCAL_CTRL__USE_EQ_LP_PGA_OFF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define MDM_DCCAL_CTRL__USE_EQ_LP_PGA_OFF__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define MDM_DCCAL_CTRL__USE_EQ_LP_PGA_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define MDM_DCCAL_CTRL__USE_EQ_LP_PGA_OFF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define MDM_DCCAL_CTRL__USE_EQ_LP_PGA_OFF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define MDM_DCCAL_CTRL__USE_EQ_LP_PGA_OFF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define MDM_DCCAL_CTRL__USE_EQ_LP_PGA_OFF__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_DCCAL_CTRL__TYPE uint32_t +#define MDM_DCCAL_CTRL__READ 0x000000ffU +#define MDM_DCCAL_CTRL__WRITE 0x000000ffU +#define MDM_DCCAL_CTRL__PRESERVED 0x00000000U +#define MDM_DCCAL_CTRL__RESET_VALUE 0x00000040U + +#endif /* __MDM_DCCAL_CTRL_MACRO__ */ + +/** @} end of dccal_ctrl */ + +/* macros for BlueprintGlobalNameSpace::MDM_tia_dccal */ +/** + * @defgroup mdm_regs_core_tia_dccal tia_dccal + * @brief DC offset calibration control for TIA for paris definitions. + * @{ + */ +#ifndef __MDM_TIA_DCCAL_MACRO__ +#define __MDM_TIA_DCCAL_MACRO__ + +/* macros for field avg_only */ +/** + * @defgroup mdm_regs_core_avg_only_field avg_only_field + * @brief macros for field avg_only + * @details software trigger DC calibration start average only cal + * @{ + */ +#define MDM_TIA_DCCAL__AVG_ONLY__SHIFT 2 +#define MDM_TIA_DCCAL__AVG_ONLY__WIDTH 1 +#define MDM_TIA_DCCAL__AVG_ONLY__MASK 0x00000004U +#define MDM_TIA_DCCAL__AVG_ONLY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define MDM_TIA_DCCAL__AVG_ONLY__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define MDM_TIA_DCCAL__AVG_ONLY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define MDM_TIA_DCCAL__AVG_ONLY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define MDM_TIA_DCCAL__AVG_ONLY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define MDM_TIA_DCCAL__AVG_ONLY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define MDM_TIA_DCCAL__AVG_ONLY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field avg_cnt_exp */ +/** + * @defgroup mdm_regs_core_avg_cnt_exp_field avg_cnt_exp_field + * @brief macros for field avg_cnt_exp + * @details 2's power number of samples to average; valid values [2-6] + * @{ + */ +#define MDM_TIA_DCCAL__AVG_CNT_EXP__SHIFT 4 +#define MDM_TIA_DCCAL__AVG_CNT_EXP__WIDTH 3 +#define MDM_TIA_DCCAL__AVG_CNT_EXP__MASK 0x00000070U +#define MDM_TIA_DCCAL__AVG_CNT_EXP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000070U) >> 4) +#define MDM_TIA_DCCAL__AVG_CNT_EXP__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000070U) +#define MDM_TIA_DCCAL__AVG_CNT_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((uint32_t)(src) <<\ + 4) & 0x00000070U) +#define MDM_TIA_DCCAL__AVG_CNT_EXP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000070U))) +#define MDM_TIA_DCCAL__AVG_CNT_EXP__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field srch_bit_cnt */ +/** + * @defgroup mdm_regs_core_srch_bit_cnt_field srch_bit_cnt_field + * @brief macros for field srch_bit_cnt + * @details number of DC offset bits to search + * @{ + */ +#define MDM_TIA_DCCAL__SRCH_BIT_CNT__SHIFT 7 +#define MDM_TIA_DCCAL__SRCH_BIT_CNT__WIDTH 4 +#define MDM_TIA_DCCAL__SRCH_BIT_CNT__MASK 0x00000780U +#define MDM_TIA_DCCAL__SRCH_BIT_CNT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000780U) >> 7) +#define MDM_TIA_DCCAL__SRCH_BIT_CNT__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000780U) +#define MDM_TIA_DCCAL__SRCH_BIT_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000780U) | (((uint32_t)(src) <<\ + 7) & 0x00000780U) +#define MDM_TIA_DCCAL__SRCH_BIT_CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000780U))) +#define MDM_TIA_DCCAL__SRCH_BIT_CNT__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field msb */ +/** + * @defgroup mdm_regs_core_msb_field msb_field + * @brief macros for field msb + * @details 0 => 5, 1 => 6, 2 => 7, 3 => 8 for dcoc width == 0, 0 => 6, 1 => 7, 2 => 8, 3 => 9 for dcoc width == 1, 0 => 7, 1 => 8, 2 => 9, 3 => 10 for dcoc width == 2 + * @{ + */ +#define MDM_TIA_DCCAL__MSB__SHIFT 11 +#define MDM_TIA_DCCAL__MSB__WIDTH 3 +#define MDM_TIA_DCCAL__MSB__MASK 0x00003800U +#define MDM_TIA_DCCAL__MSB__READ(src) (((uint32_t)(src) & 0x00003800U) >> 11) +#define MDM_TIA_DCCAL__MSB__WRITE(src) (((uint32_t)(src) << 11) & 0x00003800U) +#define MDM_TIA_DCCAL__MSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((uint32_t)(src) <<\ + 11) & 0x00003800U) +#define MDM_TIA_DCCAL__MSB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00003800U))) +#define MDM_TIA_DCCAL__MSB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field iq_ratio */ +/** + * @defgroup mdm_regs_core_iq_ratio_field iq_ratio_field + * @brief macros for field iq_ratio + * @details cross coupling ratio between i and q channel for 1 Mb/s; valid format u2.7 2.15 * 2^7 + * @{ + */ +#define MDM_TIA_DCCAL__IQ_RATIO__SHIFT 14 +#define MDM_TIA_DCCAL__IQ_RATIO__WIDTH 9 +#define MDM_TIA_DCCAL__IQ_RATIO__MASK 0x007fc000U +#define MDM_TIA_DCCAL__IQ_RATIO__READ(src) \ + (((uint32_t)(src)\ + & 0x007fc000U) >> 14) +#define MDM_TIA_DCCAL__IQ_RATIO__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x007fc000U) +#define MDM_TIA_DCCAL__IQ_RATIO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007fc000U) | (((uint32_t)(src) <<\ + 14) & 0x007fc000U) +#define MDM_TIA_DCCAL__IQ_RATIO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x007fc000U))) +#define MDM_TIA_DCCAL__IQ_RATIO__RESET_VALUE 0x00000113U +/** @} */ + +/* macros for field iq_ratio_twomeg */ +/** + * @defgroup mdm_regs_core_iq_ratio_twomeg_field iq_ratio_twomeg_field + * @brief macros for field iq_ratio_twomeg + * @details cross coupling ratio between i and q channel for 2 Mb/s; valid format u2.7 2.15 * 2^7 + * @{ + */ +#define MDM_TIA_DCCAL__IQ_RATIO_TWOMEG__SHIFT 23 +#define MDM_TIA_DCCAL__IQ_RATIO_TWOMEG__WIDTH 9 +#define MDM_TIA_DCCAL__IQ_RATIO_TWOMEG__MASK 0xff800000U +#define MDM_TIA_DCCAL__IQ_RATIO_TWOMEG__READ(src) \ + (((uint32_t)(src)\ + & 0xff800000U) >> 23) +#define MDM_TIA_DCCAL__IQ_RATIO_TWOMEG__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0xff800000U) +#define MDM_TIA_DCCAL__IQ_RATIO_TWOMEG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff800000U) | (((uint32_t)(src) <<\ + 23) & 0xff800000U) +#define MDM_TIA_DCCAL__IQ_RATIO_TWOMEG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0xff800000U))) +#define MDM_TIA_DCCAL__IQ_RATIO_TWOMEG__RESET_VALUE 0x00000113U +/** @} */ +#define MDM_TIA_DCCAL__TYPE uint32_t +#define MDM_TIA_DCCAL__READ 0xfffffff4U +#define MDM_TIA_DCCAL__WRITE 0xfffffff4U +#define MDM_TIA_DCCAL__PRESERVED 0x00000000U +#define MDM_TIA_DCCAL__RESET_VALUE 0x89c4c330U + +#endif /* __MDM_TIA_DCCAL_MACRO__ */ + +/** @} end of tia_dccal */ + +/* macros for BlueprintGlobalNameSpace::MDM_tia_dccal2 */ +/** + * @defgroup mdm_regs_core_tia_dccal2 tia_dccal2 + * @brief DC offset calibration control for TIA, set 2 for paris definitions. + * @{ + */ +#ifndef __MDM_TIA_DCCAL2_MACRO__ +#define __MDM_TIA_DCCAL2_MACRO__ + +/* macros for field rf_post_dccal_sttl_cnt */ +/** + * @defgroup mdm_regs_core_rf_post_dccal_sttl_cnt_field rf_post_dccal_sttl_cnt_field + * @brief macros for field rf_post_dccal_sttl_cnt + * @details number of 16 MHz clocks from rf to settle after caldc is deasserted. MUST BE EVEN + * @{ + */ +#define MDM_TIA_DCCAL2__RF_POST_DCCAL_STTL_CNT__SHIFT 0 +#define MDM_TIA_DCCAL2__RF_POST_DCCAL_STTL_CNT__WIDTH 10 +#define MDM_TIA_DCCAL2__RF_POST_DCCAL_STTL_CNT__MASK 0x000003ffU +#define MDM_TIA_DCCAL2__RF_POST_DCCAL_STTL_CNT__READ(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define MDM_TIA_DCCAL2__RF_POST_DCCAL_STTL_CNT__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define MDM_TIA_DCCAL2__RF_POST_DCCAL_STTL_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define MDM_TIA_DCCAL2__RF_POST_DCCAL_STTL_CNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define MDM_TIA_DCCAL2__RF_POST_DCCAL_STTL_CNT__RESET_VALUE 0x00000050U +/** @} */ + +/* macros for field rf_sttl_cnt */ +/** + * @defgroup mdm_regs_core_rf_sttl_cnt_field rf_sttl_cnt_field + * @brief macros for field rf_sttl_cnt + * @details number of 16 MHz clocks from rf to settle after tia gain change for 1 Mb/s. MUST BE EVEN + * @{ + */ +#define MDM_TIA_DCCAL2__RF_STTL_CNT__SHIFT 10 +#define MDM_TIA_DCCAL2__RF_STTL_CNT__WIDTH 10 +#define MDM_TIA_DCCAL2__RF_STTL_CNT__MASK 0x000ffc00U +#define MDM_TIA_DCCAL2__RF_STTL_CNT__READ(src) \ + (((uint32_t)(src)\ + & 0x000ffc00U) >> 10) +#define MDM_TIA_DCCAL2__RF_STTL_CNT__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x000ffc00U) +#define MDM_TIA_DCCAL2__RF_STTL_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define MDM_TIA_DCCAL2__RF_STTL_CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define MDM_TIA_DCCAL2__RF_STTL_CNT__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field rf_sttl_cnt_twomeg */ +/** + * @defgroup mdm_regs_core_rf_sttl_cnt_twomeg_field rf_sttl_cnt_twomeg_field + * @brief macros for field rf_sttl_cnt_twomeg + * @details number of 16 MHz clocks from rf to settle after tia gain change for 2 Mb/s + * @{ + */ +#define MDM_TIA_DCCAL2__RF_STTL_CNT_TWOMEG__SHIFT 20 +#define MDM_TIA_DCCAL2__RF_STTL_CNT_TWOMEG__WIDTH 10 +#define MDM_TIA_DCCAL2__RF_STTL_CNT_TWOMEG__MASK 0x3ff00000U +#define MDM_TIA_DCCAL2__RF_STTL_CNT_TWOMEG__READ(src) \ + (((uint32_t)(src)\ + & 0x3ff00000U) >> 20) +#define MDM_TIA_DCCAL2__RF_STTL_CNT_TWOMEG__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x3ff00000U) +#define MDM_TIA_DCCAL2__RF_STTL_CNT_TWOMEG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define MDM_TIA_DCCAL2__RF_STTL_CNT_TWOMEG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define MDM_TIA_DCCAL2__RF_STTL_CNT_TWOMEG__RESET_VALUE 0x00000010U +/** @} */ +#define MDM_TIA_DCCAL2__TYPE uint32_t +#define MDM_TIA_DCCAL2__READ 0x3fffffffU +#define MDM_TIA_DCCAL2__WRITE 0x3fffffffU +#define MDM_TIA_DCCAL2__PRESERVED 0x00000000U +#define MDM_TIA_DCCAL2__RESET_VALUE 0x01004050U + +#endif /* __MDM_TIA_DCCAL2_MACRO__ */ + +/** @} end of tia_dccal2 */ + +/* macros for BlueprintGlobalNameSpace::MDM_tia_dccal3 */ +/** + * @defgroup mdm_regs_core_tia_dccal3 tia_dccal3 + * @brief DC offset calibration control for TIA, set 3 for paris definitions. + * @{ + */ +#ifndef __MDM_TIA_DCCAL3_MACRO__ +#define __MDM_TIA_DCCAL3_MACRO__ + +/* macros for field rf_post_dccal_lna_prtct_sttl_cnt */ +/** + * @defgroup mdm_regs_core_rf_post_dccal_lna_prtct_sttl_cnt_field rf_post_dccal_lna_prtct_sttl_cnt_field + * @brief macros for field rf_post_dccal_lna_prtct_sttl_cnt + * @details number of 16 MHz clocks for lna protect to deassert. MUST BE EVEN + * @{ + */ +#define MDM_TIA_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__SHIFT 0 +#define MDM_TIA_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__WIDTH 10 +#define MDM_TIA_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__MASK 0x000003ffU +#define MDM_TIA_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__READ(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define MDM_TIA_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define MDM_TIA_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define MDM_TIA_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define MDM_TIA_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__RESET_VALUE \ + 0x00000030U +/** @} */ +#define MDM_TIA_DCCAL3__TYPE uint32_t +#define MDM_TIA_DCCAL3__READ 0x000003ffU +#define MDM_TIA_DCCAL3__WRITE 0x000003ffU +#define MDM_TIA_DCCAL3__PRESERVED 0x00000000U +#define MDM_TIA_DCCAL3__RESET_VALUE 0x00000030U + +#endif /* __MDM_TIA_DCCAL3_MACRO__ */ + +/** @} end of tia_dccal3 */ + +/* macros for BlueprintGlobalNameSpace::MDM_tia_dccal4 */ +/** + * @defgroup mdm_regs_core_tia_dccal4 tia_dccal4 + * @brief DC offset calibration control for TIA, set 4 for paris definitions. + * @{ + */ +#ifndef __MDM_TIA_DCCAL4_MACRO__ +#define __MDM_TIA_DCCAL4_MACRO__ + +/* macros for field iq_ratio */ +/** + * @defgroup mdm_regs_core_iq_ratio_field iq_ratio_field + * @brief macros for field iq_ratio + * @details cross coupling ratio between i and q channel for 1 Mb/s; valid format u2.7 0.3 * 2^7 + * @{ + */ +#define MDM_TIA_DCCAL4__IQ_RATIO__SHIFT 0 +#define MDM_TIA_DCCAL4__IQ_RATIO__WIDTH 9 +#define MDM_TIA_DCCAL4__IQ_RATIO__MASK 0x000001ffU +#define MDM_TIA_DCCAL4__IQ_RATIO__READ(src) ((uint32_t)(src) & 0x000001ffU) +#define MDM_TIA_DCCAL4__IQ_RATIO__WRITE(src) ((uint32_t)(src) & 0x000001ffU) +#define MDM_TIA_DCCAL4__IQ_RATIO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((uint32_t)(src) &\ + 0x000001ffU) +#define MDM_TIA_DCCAL4__IQ_RATIO__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000001ffU))) +#define MDM_TIA_DCCAL4__IQ_RATIO__RESET_VALUE 0x00000026U +/** @} */ + +/* macros for field iq_ratio_twomeg */ +/** + * @defgroup mdm_regs_core_iq_ratio_twomeg_field iq_ratio_twomeg_field + * @brief macros for field iq_ratio_twomeg + * @details cross coupling ratio between i and q channel for 2 Mb/s; valid format u2.7 0.3 * 2^7 + * @{ + */ +#define MDM_TIA_DCCAL4__IQ_RATIO_TWOMEG__SHIFT 9 +#define MDM_TIA_DCCAL4__IQ_RATIO_TWOMEG__WIDTH 9 +#define MDM_TIA_DCCAL4__IQ_RATIO_TWOMEG__MASK 0x0003fe00U +#define MDM_TIA_DCCAL4__IQ_RATIO_TWOMEG__READ(src) \ + (((uint32_t)(src)\ + & 0x0003fe00U) >> 9) +#define MDM_TIA_DCCAL4__IQ_RATIO_TWOMEG__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0003fe00U) +#define MDM_TIA_DCCAL4__IQ_RATIO_TWOMEG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0003fe00U) +#define MDM_TIA_DCCAL4__IQ_RATIO_TWOMEG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0003fe00U))) +#define MDM_TIA_DCCAL4__IQ_RATIO_TWOMEG__RESET_VALUE 0x00000026U +/** @} */ + +/* macros for field dcoc_wdth */ +/** + * @defgroup mdm_regs_core_dcoc_wdth_field dcoc_wdth_field + * @brief macros for field dcoc_wdth + * @details 0 => 6, 1 => 7, 2 => 8 + * @{ + */ +#define MDM_TIA_DCCAL4__DCOC_WDTH__SHIFT 18 +#define MDM_TIA_DCCAL4__DCOC_WDTH__WIDTH 2 +#define MDM_TIA_DCCAL4__DCOC_WDTH__MASK 0x000c0000U +#define MDM_TIA_DCCAL4__DCOC_WDTH__READ(src) \ + (((uint32_t)(src)\ + & 0x000c0000U) >> 18) +#define MDM_TIA_DCCAL4__DCOC_WDTH__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x000c0000U) +#define MDM_TIA_DCCAL4__DCOC_WDTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000c0000U) | (((uint32_t)(src) <<\ + 18) & 0x000c0000U) +#define MDM_TIA_DCCAL4__DCOC_WDTH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x000c0000U))) +#define MDM_TIA_DCCAL4__DCOC_WDTH__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_TIA_DCCAL4__TYPE uint32_t +#define MDM_TIA_DCCAL4__READ 0x000fffffU +#define MDM_TIA_DCCAL4__WRITE 0x000fffffU +#define MDM_TIA_DCCAL4__PRESERVED 0x00000000U +#define MDM_TIA_DCCAL4__RESET_VALUE 0x00004c26U + +#endif /* __MDM_TIA_DCCAL4_MACRO__ */ + +/** @} end of tia_dccal4 */ + +/* macros for BlueprintGlobalNameSpace::MDM_pga_dccal */ +/** + * @defgroup mdm_regs_core_pga_dccal pga_dccal + * @brief DC offset calibration control for PGA definitions. + * @{ + */ +#ifndef __MDM_PGA_DCCAL_MACRO__ +#define __MDM_PGA_DCCAL_MACRO__ + +/* macros for field avg_only */ +/** + * @defgroup mdm_regs_core_avg_only_field avg_only_field + * @brief macros for field avg_only + * @details software trigger DC calibration start average only cal + * @{ + */ +#define MDM_PGA_DCCAL__AVG_ONLY__SHIFT 2 +#define MDM_PGA_DCCAL__AVG_ONLY__WIDTH 1 +#define MDM_PGA_DCCAL__AVG_ONLY__MASK 0x00000004U +#define MDM_PGA_DCCAL__AVG_ONLY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define MDM_PGA_DCCAL__AVG_ONLY__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define MDM_PGA_DCCAL__AVG_ONLY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define MDM_PGA_DCCAL__AVG_ONLY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define MDM_PGA_DCCAL__AVG_ONLY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define MDM_PGA_DCCAL__AVG_ONLY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define MDM_PGA_DCCAL__AVG_ONLY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field avg_cnt_exp */ +/** + * @defgroup mdm_regs_core_avg_cnt_exp_field avg_cnt_exp_field + * @brief macros for field avg_cnt_exp + * @details 2's power number of samples to average; valid values [2-6] + * @{ + */ +#define MDM_PGA_DCCAL__AVG_CNT_EXP__SHIFT 4 +#define MDM_PGA_DCCAL__AVG_CNT_EXP__WIDTH 3 +#define MDM_PGA_DCCAL__AVG_CNT_EXP__MASK 0x00000070U +#define MDM_PGA_DCCAL__AVG_CNT_EXP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000070U) >> 4) +#define MDM_PGA_DCCAL__AVG_CNT_EXP__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000070U) +#define MDM_PGA_DCCAL__AVG_CNT_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((uint32_t)(src) <<\ + 4) & 0x00000070U) +#define MDM_PGA_DCCAL__AVG_CNT_EXP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000070U))) +#define MDM_PGA_DCCAL__AVG_CNT_EXP__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field srch_bit_cnt */ +/** + * @defgroup mdm_regs_core_srch_bit_cnt_field srch_bit_cnt_field + * @brief macros for field srch_bit_cnt + * @details number of DC offset bits to search must be less than or equal to dcoc width + * @{ + */ +#define MDM_PGA_DCCAL__SRCH_BIT_CNT__SHIFT 7 +#define MDM_PGA_DCCAL__SRCH_BIT_CNT__WIDTH 4 +#define MDM_PGA_DCCAL__SRCH_BIT_CNT__MASK 0x00000780U +#define MDM_PGA_DCCAL__SRCH_BIT_CNT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000780U) >> 7) +#define MDM_PGA_DCCAL__SRCH_BIT_CNT__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000780U) +#define MDM_PGA_DCCAL__SRCH_BIT_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000780U) | (((uint32_t)(src) <<\ + 7) & 0x00000780U) +#define MDM_PGA_DCCAL__SRCH_BIT_CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000780U))) +#define MDM_PGA_DCCAL__SRCH_BIT_CNT__RESET_VALUE 0x00000005U +/** @} */ + +/* macros for field msb */ +/** + * @defgroup mdm_regs_core_msb_field msb_field + * @brief macros for field msb + * @details 0 => 4, 1 => 5, 2 => 6, 3 => 7 + * @{ + */ +#define MDM_PGA_DCCAL__MSB__SHIFT 12 +#define MDM_PGA_DCCAL__MSB__WIDTH 3 +#define MDM_PGA_DCCAL__MSB__MASK 0x00007000U +#define MDM_PGA_DCCAL__MSB__READ(src) (((uint32_t)(src) & 0x00007000U) >> 12) +#define MDM_PGA_DCCAL__MSB__WRITE(src) (((uint32_t)(src) << 12) & 0x00007000U) +#define MDM_PGA_DCCAL__MSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((uint32_t)(src) <<\ + 12) & 0x00007000U) +#define MDM_PGA_DCCAL__MSB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00007000U))) +#define MDM_PGA_DCCAL__MSB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field iq_ratio */ +/** + * @defgroup mdm_regs_core_iq_ratio_field iq_ratio_field + * @brief macros for field iq_ratio + * @details cross coupling ratio between i and q channel for 1 Mb/s; valid format u1.7 1.75 * 2^7 + * @{ + */ +#define MDM_PGA_DCCAL__IQ_RATIO__SHIFT 16 +#define MDM_PGA_DCCAL__IQ_RATIO__WIDTH 8 +#define MDM_PGA_DCCAL__IQ_RATIO__MASK 0x00ff0000U +#define MDM_PGA_DCCAL__IQ_RATIO__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MDM_PGA_DCCAL__IQ_RATIO__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define MDM_PGA_DCCAL__IQ_RATIO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MDM_PGA_DCCAL__IQ_RATIO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define MDM_PGA_DCCAL__IQ_RATIO__RESET_VALUE 0x000000e0U +/** @} */ + +/* macros for field iq_ratio_twomeg */ +/** + * @defgroup mdm_regs_core_iq_ratio_twomeg_field iq_ratio_twomeg_field + * @brief macros for field iq_ratio_twomeg + * @details cross coupling ratio between i and q channel for 2 Mb/s; valid format u1.7 1.75 * 2^7 + * @{ + */ +#define MDM_PGA_DCCAL__IQ_RATIO_TWOMEG__SHIFT 24 +#define MDM_PGA_DCCAL__IQ_RATIO_TWOMEG__WIDTH 8 +#define MDM_PGA_DCCAL__IQ_RATIO_TWOMEG__MASK 0xff000000U +#define MDM_PGA_DCCAL__IQ_RATIO_TWOMEG__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define MDM_PGA_DCCAL__IQ_RATIO_TWOMEG__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define MDM_PGA_DCCAL__IQ_RATIO_TWOMEG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define MDM_PGA_DCCAL__IQ_RATIO_TWOMEG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define MDM_PGA_DCCAL__IQ_RATIO_TWOMEG__RESET_VALUE 0x000000e0U +/** @} */ +#define MDM_PGA_DCCAL__TYPE uint32_t +#define MDM_PGA_DCCAL__READ 0xffff77f4U +#define MDM_PGA_DCCAL__WRITE 0xffff77f4U +#define MDM_PGA_DCCAL__PRESERVED 0x00000000U +#define MDM_PGA_DCCAL__RESET_VALUE 0xe0e002b0U + +#endif /* __MDM_PGA_DCCAL_MACRO__ */ + +/** @} end of pga_dccal */ + +/* macros for BlueprintGlobalNameSpace::MDM_pga_dccal2 */ +/** + * @defgroup mdm_regs_core_pga_dccal2 pga_dccal2 + * @brief DC offset calibration control for PGA, set 2 definitions. + * @{ + */ +#ifndef __MDM_PGA_DCCAL2_MACRO__ +#define __MDM_PGA_DCCAL2_MACRO__ + +/* macros for field rf_post_dccal_sttl_cnt */ +/** + * @defgroup mdm_regs_core_rf_post_dccal_sttl_cnt_field rf_post_dccal_sttl_cnt_field + * @brief macros for field rf_post_dccal_sttl_cnt + * @details number of 16 MHz clocks from rf to settle after caldc is deasserted. MUST BE EVEN + * @{ + */ +#define MDM_PGA_DCCAL2__RF_POST_DCCAL_STTL_CNT__SHIFT 0 +#define MDM_PGA_DCCAL2__RF_POST_DCCAL_STTL_CNT__WIDTH 10 +#define MDM_PGA_DCCAL2__RF_POST_DCCAL_STTL_CNT__MASK 0x000003ffU +#define MDM_PGA_DCCAL2__RF_POST_DCCAL_STTL_CNT__READ(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define MDM_PGA_DCCAL2__RF_POST_DCCAL_STTL_CNT__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define MDM_PGA_DCCAL2__RF_POST_DCCAL_STTL_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define MDM_PGA_DCCAL2__RF_POST_DCCAL_STTL_CNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define MDM_PGA_DCCAL2__RF_POST_DCCAL_STTL_CNT__RESET_VALUE 0x00000050U +/** @} */ + +/* macros for field rf_sttl_cnt */ +/** + * @defgroup mdm_regs_core_rf_sttl_cnt_field rf_sttl_cnt_field + * @brief macros for field rf_sttl_cnt + * @details number of 16 MHz clocks from rf to settle after pga gain change for 1 Mb/s. MUST BE EVEN + * @{ + */ +#define MDM_PGA_DCCAL2__RF_STTL_CNT__SHIFT 10 +#define MDM_PGA_DCCAL2__RF_STTL_CNT__WIDTH 10 +#define MDM_PGA_DCCAL2__RF_STTL_CNT__MASK 0x000ffc00U +#define MDM_PGA_DCCAL2__RF_STTL_CNT__READ(src) \ + (((uint32_t)(src)\ + & 0x000ffc00U) >> 10) +#define MDM_PGA_DCCAL2__RF_STTL_CNT__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x000ffc00U) +#define MDM_PGA_DCCAL2__RF_STTL_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define MDM_PGA_DCCAL2__RF_STTL_CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define MDM_PGA_DCCAL2__RF_STTL_CNT__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field rf_sttl_cnt_twomeg */ +/** + * @defgroup mdm_regs_core_rf_sttl_cnt_twomeg_field rf_sttl_cnt_twomeg_field + * @brief macros for field rf_sttl_cnt_twomeg + * @details number of 16 MHz clocks from rf to settle after pga gain change for 2 Mb/s + * @{ + */ +#define MDM_PGA_DCCAL2__RF_STTL_CNT_TWOMEG__SHIFT 20 +#define MDM_PGA_DCCAL2__RF_STTL_CNT_TWOMEG__WIDTH 10 +#define MDM_PGA_DCCAL2__RF_STTL_CNT_TWOMEG__MASK 0x3ff00000U +#define MDM_PGA_DCCAL2__RF_STTL_CNT_TWOMEG__READ(src) \ + (((uint32_t)(src)\ + & 0x3ff00000U) >> 20) +#define MDM_PGA_DCCAL2__RF_STTL_CNT_TWOMEG__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x3ff00000U) +#define MDM_PGA_DCCAL2__RF_STTL_CNT_TWOMEG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define MDM_PGA_DCCAL2__RF_STTL_CNT_TWOMEG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define MDM_PGA_DCCAL2__RF_STTL_CNT_TWOMEG__RESET_VALUE 0x00000010U +/** @} */ +#define MDM_PGA_DCCAL2__TYPE uint32_t +#define MDM_PGA_DCCAL2__READ 0x3fffffffU +#define MDM_PGA_DCCAL2__WRITE 0x3fffffffU +#define MDM_PGA_DCCAL2__PRESERVED 0x00000000U +#define MDM_PGA_DCCAL2__RESET_VALUE 0x01004050U + +#endif /* __MDM_PGA_DCCAL2_MACRO__ */ + +/** @} end of pga_dccal2 */ + +/* macros for BlueprintGlobalNameSpace::MDM_pga_dccal3 */ +/** + * @defgroup mdm_regs_core_pga_dccal3 pga_dccal3 + * @brief DC offset calibration control for PGA, set 3 for paris definitions. + * @{ + */ +#ifndef __MDM_PGA_DCCAL3_MACRO__ +#define __MDM_PGA_DCCAL3_MACRO__ + +/* macros for field rf_post_dccal_lna_prtct_sttl_cnt */ +/** + * @defgroup mdm_regs_core_rf_post_dccal_lna_prtct_sttl_cnt_field rf_post_dccal_lna_prtct_sttl_cnt_field + * @brief macros for field rf_post_dccal_lna_prtct_sttl_cnt + * @details number of 16 MHz clocks for lna protect to deassert. MUST BE EVEN + * @{ + */ +#define MDM_PGA_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__SHIFT 0 +#define MDM_PGA_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__WIDTH 10 +#define MDM_PGA_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__MASK 0x000003ffU +#define MDM_PGA_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__READ(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define MDM_PGA_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define MDM_PGA_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define MDM_PGA_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define MDM_PGA_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__RESET_VALUE \ + 0x00000030U +/** @} */ + +/* macros for field cal_gain_scl */ +/** + * @defgroup mdm_regs_core_cal_gain_scl_field cal_gain_scl_field + * @brief macros for field cal_gain_scl + * @details dc offset scaling factor based on current gain and cal gain; valid format u0.8 yow need to determine the default value round(2^4 * 2^8/(1 + 224/128 + 1014/64)) + * @{ + */ +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL__SHIFT 10 +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL__WIDTH 8 +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL__MASK 0x0003fc00U +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL__READ(src) \ + (((uint32_t)(src)\ + & 0x0003fc00U) >> 10) +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x0003fc00U) +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fc00U) | (((uint32_t)(src) <<\ + 10) & 0x0003fc00U) +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x0003fc00U))) +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL__RESET_VALUE 0x000000d8U +/** @} */ + +/* macros for field cal_gain_scl_ls */ +/** + * @defgroup mdm_regs_core_cal_gain_scl_ls_field cal_gain_scl_ls_field + * @brief macros for field cal_gain_scl_ls + * @details left shift cal_gain_scl to shift the non zero bit to msb; yow need to determine the default value floor(log2(1 + 224/128 + 1014/64)) + * @{ + */ +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LS__SHIFT 18 +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LS__WIDTH 3 +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LS__MASK 0x001c0000U +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LS__READ(src) \ + (((uint32_t)(src)\ + & 0x001c0000U) >> 18) +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LS__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x001c0000U) +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((uint32_t)(src) <<\ + 18) & 0x001c0000U) +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x001c0000U))) +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LS__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field cal_gain_scl_lp */ +/** + * @defgroup mdm_regs_core_cal_gain_scl_lp_field cal_gain_scl_lp_field + * @brief macros for field cal_gain_scl_lp + * @details dc offset scaling factor based on current gain and cal gain in low power mode; valid format u0.8 yow need to determine the default value round(2^4 * 2^8/(1 + 1014/64)) + * @{ + */ +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LP__SHIFT 21 +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LP__WIDTH 8 +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LP__MASK 0x1fe00000U +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LP__READ(src) \ + (((uint32_t)(src)\ + & 0x1fe00000U) >> 21) +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LP__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x1fe00000U) +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1fe00000U) | (((uint32_t)(src) <<\ + 21) & 0x1fe00000U) +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x1fe00000U))) +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LP__RESET_VALUE 0x000000f3U +/** @} */ + +/* macros for field cal_gain_scl_lp_ls */ +/** + * @defgroup mdm_regs_core_cal_gain_scl_lp_ls_field cal_gain_scl_lp_ls_field + * @brief macros for field cal_gain_scl_lp_ls + * @details left shift cal_gain_scl_lp to shift the non zero bit to msb; yow need to determine the default value floor(log2(1 + 1014/64)) + * @{ + */ +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LP_LS__SHIFT 29 +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LP_LS__WIDTH 3 +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LP_LS__MASK 0xe0000000U +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LP_LS__READ(src) \ + (((uint32_t)(src)\ + & 0xe0000000U) >> 29) +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LP_LS__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0xe0000000U) +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LP_LS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((uint32_t)(src) <<\ + 29) & 0xe0000000U) +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LP_LS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0xe0000000U))) +#define MDM_PGA_DCCAL3__CAL_GAIN_SCL_LP_LS__RESET_VALUE 0x00000004U +/** @} */ +#define MDM_PGA_DCCAL3__TYPE uint32_t +#define MDM_PGA_DCCAL3__READ 0xffffffffU +#define MDM_PGA_DCCAL3__WRITE 0xffffffffU +#define MDM_PGA_DCCAL3__PRESERVED 0x00000000U +#define MDM_PGA_DCCAL3__RESET_VALUE 0x9e736030U + +#endif /* __MDM_PGA_DCCAL3_MACRO__ */ + +/** @} end of pga_dccal3 */ + +/* macros for BlueprintGlobalNameSpace::MDM_pga_dccal4 */ +/** + * @defgroup mdm_regs_core_pga_dccal4 pga_dccal4 + * @brief DC offset calibration control for PGA, set 4 for paris definitions. + * @{ + */ +#ifndef __MDM_PGA_DCCAL4_MACRO__ +#define __MDM_PGA_DCCAL4_MACRO__ + +/* macros for field iq_ratio */ +/** + * @defgroup mdm_regs_core_iq_ratio_field iq_ratio_field + * @brief macros for field iq_ratio + * @details cross coupling ratio between i and q channel for 1 Mb/s used during gain based residue dc correction state; valid format s2.7 1.75 * 2^7 + * @{ + */ +#define MDM_PGA_DCCAL4__IQ_RATIO__SHIFT 0 +#define MDM_PGA_DCCAL4__IQ_RATIO__WIDTH 9 +#define MDM_PGA_DCCAL4__IQ_RATIO__MASK 0x000001ffU +#define MDM_PGA_DCCAL4__IQ_RATIO__READ(src) ((uint32_t)(src) & 0x000001ffU) +#define MDM_PGA_DCCAL4__IQ_RATIO__WRITE(src) ((uint32_t)(src) & 0x000001ffU) +#define MDM_PGA_DCCAL4__IQ_RATIO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((uint32_t)(src) &\ + 0x000001ffU) +#define MDM_PGA_DCCAL4__IQ_RATIO__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000001ffU))) +#define MDM_PGA_DCCAL4__IQ_RATIO__RESET_VALUE 0x000000e0U +/** @} */ + +/* macros for field iq_ratio_twomeg */ +/** + * @defgroup mdm_regs_core_iq_ratio_twomeg_field iq_ratio_twomeg_field + * @brief macros for field iq_ratio_twomeg + * @details cross coupling ratio between i and q channel for 2 Mb/s used during gain based residue dc correction state; valid format s2.7 1.75 * 2^7 + * @{ + */ +#define MDM_PGA_DCCAL4__IQ_RATIO_TWOMEG__SHIFT 16 +#define MDM_PGA_DCCAL4__IQ_RATIO_TWOMEG__WIDTH 9 +#define MDM_PGA_DCCAL4__IQ_RATIO_TWOMEG__MASK 0x01ff0000U +#define MDM_PGA_DCCAL4__IQ_RATIO_TWOMEG__READ(src) \ + (((uint32_t)(src)\ + & 0x01ff0000U) >> 16) +#define MDM_PGA_DCCAL4__IQ_RATIO_TWOMEG__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x01ff0000U) +#define MDM_PGA_DCCAL4__IQ_RATIO_TWOMEG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x01ff0000U) +#define MDM_PGA_DCCAL4__IQ_RATIO_TWOMEG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x01ff0000U))) +#define MDM_PGA_DCCAL4__IQ_RATIO_TWOMEG__RESET_VALUE 0x000000e0U +/** @} */ +#define MDM_PGA_DCCAL4__TYPE uint32_t +#define MDM_PGA_DCCAL4__READ 0x01ff01ffU +#define MDM_PGA_DCCAL4__WRITE 0x01ff01ffU +#define MDM_PGA_DCCAL4__PRESERVED 0x00000000U +#define MDM_PGA_DCCAL4__RESET_VALUE 0x00e000e0U + +#endif /* __MDM_PGA_DCCAL4_MACRO__ */ + +/** @} end of pga_dccal4 */ + +/* macros for BlueprintGlobalNameSpace::MDM_pga_dccal5 */ +/** + * @defgroup mdm_regs_core_pga_dccal5 pga_dccal5 + * @brief DC offset calibration control for PGA, set 5 for paris definitions. + * @{ + */ +#ifndef __MDM_PGA_DCCAL5_MACRO__ +#define __MDM_PGA_DCCAL5_MACRO__ + +/* macros for field nm_to_lpm_scl */ +/** + * @defgroup mdm_regs_core_nm_to_lpm_scl_field nm_to_lpm_scl_field + * @brief macros for field nm_to_lpm_scl + * @details dc offset scaling factor based on cal gain and iq_ratio in normal mode; valid format u1.7 yow need to determine the default value round(2^7*(1 + 1014/64)/(1 + 224/128 + 1014/64)) + * @{ + */ +#define MDM_PGA_DCCAL5__NM_TO_LPM_SCL__SHIFT 0 +#define MDM_PGA_DCCAL5__NM_TO_LPM_SCL__WIDTH 8 +#define MDM_PGA_DCCAL5__NM_TO_LPM_SCL__MASK 0x000000ffU +#define MDM_PGA_DCCAL5__NM_TO_LPM_SCL__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_PGA_DCCAL5__NM_TO_LPM_SCL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_PGA_DCCAL5__NM_TO_LPM_SCL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_PGA_DCCAL5__NM_TO_LPM_SCL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define MDM_PGA_DCCAL5__NM_TO_LPM_SCL__RESET_VALUE 0x00000074U +/** @} */ +#define MDM_PGA_DCCAL5__TYPE uint32_t +#define MDM_PGA_DCCAL5__READ 0x000000ffU +#define MDM_PGA_DCCAL5__WRITE 0x000000ffU +#define MDM_PGA_DCCAL5__PRESERVED 0x00000000U +#define MDM_PGA_DCCAL5__RESET_VALUE 0x00000074U + +#endif /* __MDM_PGA_DCCAL5_MACRO__ */ + +/** @} end of pga_dccal5 */ + +/* macros for BlueprintGlobalNameSpace::MDM_notch_dccal */ +/** + * @defgroup mdm_regs_core_notch_dccal notch_dccal + * @brief DC offset calibration control for notch filter definitions. + * @{ + */ +#ifndef __MDM_NOTCH_DCCAL_MACRO__ +#define __MDM_NOTCH_DCCAL_MACRO__ + +/* macros for field avg_only */ +/** + * @defgroup mdm_regs_core_avg_only_field avg_only_field + * @brief macros for field avg_only + * @details software trigger DC calibration start average only cal + * @{ + */ +#define MDM_NOTCH_DCCAL__AVG_ONLY__SHIFT 2 +#define MDM_NOTCH_DCCAL__AVG_ONLY__WIDTH 1 +#define MDM_NOTCH_DCCAL__AVG_ONLY__MASK 0x00000004U +#define MDM_NOTCH_DCCAL__AVG_ONLY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define MDM_NOTCH_DCCAL__AVG_ONLY__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define MDM_NOTCH_DCCAL__AVG_ONLY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define MDM_NOTCH_DCCAL__AVG_ONLY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define MDM_NOTCH_DCCAL__AVG_ONLY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define MDM_NOTCH_DCCAL__AVG_ONLY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define MDM_NOTCH_DCCAL__AVG_ONLY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field avg_cnt_exp */ +/** + * @defgroup mdm_regs_core_avg_cnt_exp_field avg_cnt_exp_field + * @brief macros for field avg_cnt_exp + * @details 2's power number of samples to average; valid values [2-6] + * @{ + */ +#define MDM_NOTCH_DCCAL__AVG_CNT_EXP__SHIFT 4 +#define MDM_NOTCH_DCCAL__AVG_CNT_EXP__WIDTH 3 +#define MDM_NOTCH_DCCAL__AVG_CNT_EXP__MASK 0x00000070U +#define MDM_NOTCH_DCCAL__AVG_CNT_EXP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000070U) >> 4) +#define MDM_NOTCH_DCCAL__AVG_CNT_EXP__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000070U) +#define MDM_NOTCH_DCCAL__AVG_CNT_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((uint32_t)(src) <<\ + 4) & 0x00000070U) +#define MDM_NOTCH_DCCAL__AVG_CNT_EXP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000070U))) +#define MDM_NOTCH_DCCAL__AVG_CNT_EXP__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field srch_bit_cnt */ +/** + * @defgroup mdm_regs_core_srch_bit_cnt_field srch_bit_cnt_field + * @brief macros for field srch_bit_cnt + * @details number of ctune bits to search + * @{ + */ +#define MDM_NOTCH_DCCAL__SRCH_BIT_CNT__SHIFT 7 +#define MDM_NOTCH_DCCAL__SRCH_BIT_CNT__WIDTH 4 +#define MDM_NOTCH_DCCAL__SRCH_BIT_CNT__MASK 0x00000780U +#define MDM_NOTCH_DCCAL__SRCH_BIT_CNT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000780U) >> 7) +#define MDM_NOTCH_DCCAL__SRCH_BIT_CNT__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000780U) +#define MDM_NOTCH_DCCAL__SRCH_BIT_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000780U) | (((uint32_t)(src) <<\ + 7) & 0x00000780U) +#define MDM_NOTCH_DCCAL__SRCH_BIT_CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000780U))) +#define MDM_NOTCH_DCCAL__SRCH_BIT_CNT__RESET_VALUE 0x00000006U +/** @} */ +#define MDM_NOTCH_DCCAL__TYPE uint32_t +#define MDM_NOTCH_DCCAL__READ 0x000007f4U +#define MDM_NOTCH_DCCAL__WRITE 0x000007f4U +#define MDM_NOTCH_DCCAL__PRESERVED 0x00000000U +#define MDM_NOTCH_DCCAL__RESET_VALUE 0x00000330U + +#endif /* __MDM_NOTCH_DCCAL_MACRO__ */ + +/** @} end of notch_dccal */ + +/* macros for BlueprintGlobalNameSpace::MDM_notch_dccal2 */ +/** + * @defgroup mdm_regs_core_notch_dccal2 notch_dccal2 + * @brief DC offset calibration control for notch filter, set 2 definitions. + * @{ + */ +#ifndef __MDM_NOTCH_DCCAL2_MACRO__ +#define __MDM_NOTCH_DCCAL2_MACRO__ + +/* macros for field rf_post_dccal_sttl_cnt */ +/** + * @defgroup mdm_regs_core_rf_post_dccal_sttl_cnt_field rf_post_dccal_sttl_cnt_field + * @brief macros for field rf_post_dccal_sttl_cnt + * @details number of 16 MHz clocks from rf to settle after caldc is deasserted. MUST BE EVEN + * @{ + */ +#define MDM_NOTCH_DCCAL2__RF_POST_DCCAL_STTL_CNT__SHIFT 0 +#define MDM_NOTCH_DCCAL2__RF_POST_DCCAL_STTL_CNT__WIDTH 10 +#define MDM_NOTCH_DCCAL2__RF_POST_DCCAL_STTL_CNT__MASK 0x000003ffU +#define MDM_NOTCH_DCCAL2__RF_POST_DCCAL_STTL_CNT__READ(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define MDM_NOTCH_DCCAL2__RF_POST_DCCAL_STTL_CNT__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define MDM_NOTCH_DCCAL2__RF_POST_DCCAL_STTL_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define MDM_NOTCH_DCCAL2__RF_POST_DCCAL_STTL_CNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define MDM_NOTCH_DCCAL2__RF_POST_DCCAL_STTL_CNT__RESET_VALUE 0x00000050U +/** @} */ + +/* macros for field rf_sttl_cnt */ +/** + * @defgroup mdm_regs_core_rf_sttl_cnt_field rf_sttl_cnt_field + * @brief macros for field rf_sttl_cnt + * @details number of 16 MHz clocks from rf to settle after pga gain change for 1 Mb/s. MUST BE EVEN + * @{ + */ +#define MDM_NOTCH_DCCAL2__RF_STTL_CNT__SHIFT 10 +#define MDM_NOTCH_DCCAL2__RF_STTL_CNT__WIDTH 10 +#define MDM_NOTCH_DCCAL2__RF_STTL_CNT__MASK 0x000ffc00U +#define MDM_NOTCH_DCCAL2__RF_STTL_CNT__READ(src) \ + (((uint32_t)(src)\ + & 0x000ffc00U) >> 10) +#define MDM_NOTCH_DCCAL2__RF_STTL_CNT__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x000ffc00U) +#define MDM_NOTCH_DCCAL2__RF_STTL_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define MDM_NOTCH_DCCAL2__RF_STTL_CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define MDM_NOTCH_DCCAL2__RF_STTL_CNT__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field rf_sttl_cnt_twomeg */ +/** + * @defgroup mdm_regs_core_rf_sttl_cnt_twomeg_field rf_sttl_cnt_twomeg_field + * @brief macros for field rf_sttl_cnt_twomeg + * @details number of 16 MHz clocks from rf to settle after pga gain change for 2 Mb/s + * @{ + */ +#define MDM_NOTCH_DCCAL2__RF_STTL_CNT_TWOMEG__SHIFT 20 +#define MDM_NOTCH_DCCAL2__RF_STTL_CNT_TWOMEG__WIDTH 10 +#define MDM_NOTCH_DCCAL2__RF_STTL_CNT_TWOMEG__MASK 0x3ff00000U +#define MDM_NOTCH_DCCAL2__RF_STTL_CNT_TWOMEG__READ(src) \ + (((uint32_t)(src)\ + & 0x3ff00000U) >> 20) +#define MDM_NOTCH_DCCAL2__RF_STTL_CNT_TWOMEG__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x3ff00000U) +#define MDM_NOTCH_DCCAL2__RF_STTL_CNT_TWOMEG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define MDM_NOTCH_DCCAL2__RF_STTL_CNT_TWOMEG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define MDM_NOTCH_DCCAL2__RF_STTL_CNT_TWOMEG__RESET_VALUE 0x00000010U +/** @} */ +#define MDM_NOTCH_DCCAL2__TYPE uint32_t +#define MDM_NOTCH_DCCAL2__READ 0x3fffffffU +#define MDM_NOTCH_DCCAL2__WRITE 0x3fffffffU +#define MDM_NOTCH_DCCAL2__PRESERVED 0x00000000U +#define MDM_NOTCH_DCCAL2__RESET_VALUE 0x01004050U + +#endif /* __MDM_NOTCH_DCCAL2_MACRO__ */ + +/** @} end of notch_dccal2 */ + +/* macros for BlueprintGlobalNameSpace::MDM_notch_dccal3 */ +/** + * @defgroup mdm_regs_core_notch_dccal3 notch_dccal3 + * @brief DC offset calibration control for notch filter, set 3 for paris definitions. + * @{ + */ +#ifndef __MDM_NOTCH_DCCAL3_MACRO__ +#define __MDM_NOTCH_DCCAL3_MACRO__ + +/* macros for field rf_post_dccal_lna_prtct_sttl_cnt */ +/** + * @defgroup mdm_regs_core_rf_post_dccal_lna_prtct_sttl_cnt_field rf_post_dccal_lna_prtct_sttl_cnt_field + * @brief macros for field rf_post_dccal_lna_prtct_sttl_cnt + * @details number of 16 MHz clocks for lna protect to deassert. MUST BE EVEN + * @{ + */ +#define MDM_NOTCH_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__SHIFT 0 +#define MDM_NOTCH_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__WIDTH 10 +#define MDM_NOTCH_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__MASK 0x000003ffU +#define MDM_NOTCH_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__READ(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define MDM_NOTCH_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define MDM_NOTCH_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define MDM_NOTCH_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define MDM_NOTCH_DCCAL3__RF_POST_DCCAL_LNA_PRTCT_STTL_CNT__RESET_VALUE \ + 0x00000030U +/** @} */ +#define MDM_NOTCH_DCCAL3__TYPE uint32_t +#define MDM_NOTCH_DCCAL3__READ 0x000003ffU +#define MDM_NOTCH_DCCAL3__WRITE 0x000003ffU +#define MDM_NOTCH_DCCAL3__PRESERVED 0x00000000U +#define MDM_NOTCH_DCCAL3__RESET_VALUE 0x00000030U + +#endif /* __MDM_NOTCH_DCCAL3_MACRO__ */ + +/** @} end of notch_dccal3 */ + +/* macros for BlueprintGlobalNameSpace::MDM_dcofftrk */ +/** + * @defgroup mdm_regs_core_dcofftrk dcofftrk + * @brief DC offset tracking definitions. + * @{ + */ +#ifndef __MDM_DCOFFTRK_MACRO__ +#define __MDM_DCOFFTRK_MACRO__ + +/* macros for field en */ +/** + * @defgroup mdm_regs_core_en_field en_field + * @brief macros for field en + * @details Enable tracking + * @{ + */ +#define MDM_DCOFFTRK__EN__SHIFT 0 +#define MDM_DCOFFTRK__EN__WIDTH 1 +#define MDM_DCOFFTRK__EN__MASK 0x00000001U +#define MDM_DCOFFTRK__EN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_DCOFFTRK__EN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_DCOFFTRK__EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define MDM_DCOFFTRK__EN__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define MDM_DCOFFTRK__EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_DCOFFTRK__EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_DCOFFTRK__EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field corr_agc_en */ +/** + * @defgroup mdm_regs_core_corr_agc_en_field corr_agc_en_field + * @brief macros for field corr_agc_en + * @details Enable correction based on tracking + * @{ + */ +#define MDM_DCOFFTRK__CORR_AGC_EN__SHIFT 1 +#define MDM_DCOFFTRK__CORR_AGC_EN__WIDTH 1 +#define MDM_DCOFFTRK__CORR_AGC_EN__MASK 0x00000002U +#define MDM_DCOFFTRK__CORR_AGC_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define MDM_DCOFFTRK__CORR_AGC_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define MDM_DCOFFTRK__CORR_AGC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define MDM_DCOFFTRK__CORR_AGC_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define MDM_DCOFFTRK__CORR_AGC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define MDM_DCOFFTRK__CORR_AGC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define MDM_DCOFFTRK__CORR_AGC_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field corr_syncdemod_en */ +/** + * @defgroup mdm_regs_core_corr_syncdemod_en_field corr_syncdemod_en_field + * @brief macros for field corr_syncdemod_en + * @details Enable correction based on tracking + * @{ + */ +#define MDM_DCOFFTRK__CORR_SYNCDEMOD_EN__SHIFT 2 +#define MDM_DCOFFTRK__CORR_SYNCDEMOD_EN__WIDTH 1 +#define MDM_DCOFFTRK__CORR_SYNCDEMOD_EN__MASK 0x00000004U +#define MDM_DCOFFTRK__CORR_SYNCDEMOD_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define MDM_DCOFFTRK__CORR_SYNCDEMOD_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define MDM_DCOFFTRK__CORR_SYNCDEMOD_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define MDM_DCOFFTRK__CORR_SYNCDEMOD_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define MDM_DCOFFTRK__CORR_SYNCDEMOD_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define MDM_DCOFFTRK__CORR_SYNCDEMOD_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define MDM_DCOFFTRK__CORR_SYNCDEMOD_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field mu1 */ +/** + * @defgroup mdm_regs_core_mu1_field mu1_field + * @brief macros for field mu1 + * @details First gear mu: Encoding is 2^-(mu1+2) + * @{ + */ +#define MDM_DCOFFTRK__MU1__SHIFT 3 +#define MDM_DCOFFTRK__MU1__WIDTH 3 +#define MDM_DCOFFTRK__MU1__MASK 0x00000038U +#define MDM_DCOFFTRK__MU1__READ(src) (((uint32_t)(src) & 0x00000038U) >> 3) +#define MDM_DCOFFTRK__MU1__WRITE(src) (((uint32_t)(src) << 3) & 0x00000038U) +#define MDM_DCOFFTRK__MU1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define MDM_DCOFFTRK__MU1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define MDM_DCOFFTRK__MU1__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field mu2 */ +/** + * @defgroup mdm_regs_core_mu2_field mu2_field + * @brief macros for field mu2 + * @details Second gear mu: Encoding is 2^-(mu2+2) + * @{ + */ +#define MDM_DCOFFTRK__MU2__SHIFT 6 +#define MDM_DCOFFTRK__MU2__WIDTH 3 +#define MDM_DCOFFTRK__MU2__MASK 0x000001c0U +#define MDM_DCOFFTRK__MU2__READ(src) (((uint32_t)(src) & 0x000001c0U) >> 6) +#define MDM_DCOFFTRK__MU2__WRITE(src) (((uint32_t)(src) << 6) & 0x000001c0U) +#define MDM_DCOFFTRK__MU2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((uint32_t)(src) <<\ + 6) & 0x000001c0U) +#define MDM_DCOFFTRK__MU2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000001c0U))) +#define MDM_DCOFFTRK__MU2__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field mu3 */ +/** + * @defgroup mdm_regs_core_mu3_field mu3_field + * @brief macros for field mu3 + * @details Third gear mu: Encoding is 2^-(mu3+2) + * @{ + */ +#define MDM_DCOFFTRK__MU3__SHIFT 9 +#define MDM_DCOFFTRK__MU3__WIDTH 3 +#define MDM_DCOFFTRK__MU3__MASK 0x00000e00U +#define MDM_DCOFFTRK__MU3__READ(src) (((uint32_t)(src) & 0x00000e00U) >> 9) +#define MDM_DCOFFTRK__MU3__WRITE(src) (((uint32_t)(src) << 9) & 0x00000e00U) +#define MDM_DCOFFTRK__MU3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((uint32_t)(src) <<\ + 9) & 0x00000e00U) +#define MDM_DCOFFTRK__MU3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000e00U))) +#define MDM_DCOFFTRK__MU3__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field mu_count1 */ +/** + * @defgroup mdm_regs_core_mu_count1_field mu_count1_field + * @brief macros for field mu_count1 + * @details (mu_count1 * 8) = number of 16 MHz samples to switch to gear 2 + * @{ + */ +#define MDM_DCOFFTRK__MU_COUNT1__SHIFT 12 +#define MDM_DCOFFTRK__MU_COUNT1__WIDTH 6 +#define MDM_DCOFFTRK__MU_COUNT1__MASK 0x0003f000U +#define MDM_DCOFFTRK__MU_COUNT1__READ(src) \ + (((uint32_t)(src)\ + & 0x0003f000U) >> 12) +#define MDM_DCOFFTRK__MU_COUNT1__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0003f000U) +#define MDM_DCOFFTRK__MU_COUNT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((uint32_t)(src) <<\ + 12) & 0x0003f000U) +#define MDM_DCOFFTRK__MU_COUNT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0003f000U))) +#define MDM_DCOFFTRK__MU_COUNT1__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field mu_count2 */ +/** + * @defgroup mdm_regs_core_mu_count2_field mu_count2_field + * @brief macros for field mu_count2 + * @details (mu_count2 * 8) = number of 16 MHz samples to switch to gear 3. (Includes gear1 + gear2). MUST BE GREATER THAN MU_COUNT1 + * @{ + */ +#define MDM_DCOFFTRK__MU_COUNT2__SHIFT 18 +#define MDM_DCOFFTRK__MU_COUNT2__WIDTH 6 +#define MDM_DCOFFTRK__MU_COUNT2__MASK 0x00fc0000U +#define MDM_DCOFFTRK__MU_COUNT2__READ(src) \ + (((uint32_t)(src)\ + & 0x00fc0000U) >> 18) +#define MDM_DCOFFTRK__MU_COUNT2__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00fc0000U) +#define MDM_DCOFFTRK__MU_COUNT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((uint32_t)(src) <<\ + 18) & 0x00fc0000U) +#define MDM_DCOFFTRK__MU_COUNT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00fc0000U))) +#define MDM_DCOFFTRK__MU_COUNT2__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field corr_delay_idx */ +/** + * @defgroup mdm_regs_core_corr_delay_idx_field corr_delay_idx_field + * @brief macros for field corr_delay_idx + * @details Correction is applied (8 * corr_delay_idx) 16 MHz samples after tracking reset is released + * @{ + */ +#define MDM_DCOFFTRK__CORR_DELAY_IDX__SHIFT 24 +#define MDM_DCOFFTRK__CORR_DELAY_IDX__WIDTH 3 +#define MDM_DCOFFTRK__CORR_DELAY_IDX__MASK 0x07000000U +#define MDM_DCOFFTRK__CORR_DELAY_IDX__READ(src) \ + (((uint32_t)(src)\ + & 0x07000000U) >> 24) +#define MDM_DCOFFTRK__CORR_DELAY_IDX__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x07000000U) +#define MDM_DCOFFTRK__CORR_DELAY_IDX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((uint32_t)(src) <<\ + 24) & 0x07000000U) +#define MDM_DCOFFTRK__CORR_DELAY_IDX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x07000000U))) +#define MDM_DCOFFTRK__CORR_DELAY_IDX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field twomeg_en */ +/** + * @defgroup mdm_regs_core_twomeg_en_field twomeg_en_field + * @brief macros for field twomeg_en + * @details Enable tracking + * @{ + */ +#define MDM_DCOFFTRK__TWOMEG_EN__SHIFT 27 +#define MDM_DCOFFTRK__TWOMEG_EN__WIDTH 1 +#define MDM_DCOFFTRK__TWOMEG_EN__MASK 0x08000000U +#define MDM_DCOFFTRK__TWOMEG_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define MDM_DCOFFTRK__TWOMEG_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define MDM_DCOFFTRK__TWOMEG_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define MDM_DCOFFTRK__TWOMEG_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define MDM_DCOFFTRK__TWOMEG_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define MDM_DCOFFTRK__TWOMEG_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define MDM_DCOFFTRK__TWOMEG_EN__RESET_VALUE 0x00000001U +/** @} */ +#define MDM_DCOFFTRK__TYPE uint32_t +#define MDM_DCOFFTRK__READ 0x0fffffffU +#define MDM_DCOFFTRK__WRITE 0x0fffffffU +#define MDM_DCOFFTRK__PRESERVED 0x00000000U +#define MDM_DCOFFTRK__RESET_VALUE 0x08102d17U + +#endif /* __MDM_DCOFFTRK_MACRO__ */ + +/** @} end of dcofftrk */ + +/* macros for BlueprintGlobalNameSpace::MDM_dcofftrk_alt */ +/** + * @defgroup mdm_regs_core_dcofftrk_alt dcofftrk_alt + * @brief DC offset tracking, alternate set definitions. + * @{ + */ +#ifndef __MDM_DCOFFTRK_ALT_MACRO__ +#define __MDM_DCOFFTRK_ALT_MACRO__ + +/* macros for field en */ +/** + * @defgroup mdm_regs_core_en_field en_field + * @brief macros for field en + * @details Enable tracking + * @{ + */ +#define MDM_DCOFFTRK_ALT__EN__SHIFT 0 +#define MDM_DCOFFTRK_ALT__EN__WIDTH 1 +#define MDM_DCOFFTRK_ALT__EN__MASK 0x00000001U +#define MDM_DCOFFTRK_ALT__EN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_DCOFFTRK_ALT__EN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_DCOFFTRK_ALT__EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define MDM_DCOFFTRK_ALT__EN__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define MDM_DCOFFTRK_ALT__EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_DCOFFTRK_ALT__EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_DCOFFTRK_ALT__EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field corr_agc_en */ +/** + * @defgroup mdm_regs_core_corr_agc_en_field corr_agc_en_field + * @brief macros for field corr_agc_en + * @details Enable correction based on tracking + * @{ + */ +#define MDM_DCOFFTRK_ALT__CORR_AGC_EN__SHIFT 1 +#define MDM_DCOFFTRK_ALT__CORR_AGC_EN__WIDTH 1 +#define MDM_DCOFFTRK_ALT__CORR_AGC_EN__MASK 0x00000002U +#define MDM_DCOFFTRK_ALT__CORR_AGC_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define MDM_DCOFFTRK_ALT__CORR_AGC_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define MDM_DCOFFTRK_ALT__CORR_AGC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define MDM_DCOFFTRK_ALT__CORR_AGC_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define MDM_DCOFFTRK_ALT__CORR_AGC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define MDM_DCOFFTRK_ALT__CORR_AGC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define MDM_DCOFFTRK_ALT__CORR_AGC_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field corr_syncdemod_en */ +/** + * @defgroup mdm_regs_core_corr_syncdemod_en_field corr_syncdemod_en_field + * @brief macros for field corr_syncdemod_en + * @details Enable correction based on tracking + * @{ + */ +#define MDM_DCOFFTRK_ALT__CORR_SYNCDEMOD_EN__SHIFT 2 +#define MDM_DCOFFTRK_ALT__CORR_SYNCDEMOD_EN__WIDTH 1 +#define MDM_DCOFFTRK_ALT__CORR_SYNCDEMOD_EN__MASK 0x00000004U +#define MDM_DCOFFTRK_ALT__CORR_SYNCDEMOD_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define MDM_DCOFFTRK_ALT__CORR_SYNCDEMOD_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define MDM_DCOFFTRK_ALT__CORR_SYNCDEMOD_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define MDM_DCOFFTRK_ALT__CORR_SYNCDEMOD_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define MDM_DCOFFTRK_ALT__CORR_SYNCDEMOD_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define MDM_DCOFFTRK_ALT__CORR_SYNCDEMOD_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define MDM_DCOFFTRK_ALT__CORR_SYNCDEMOD_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field mu1 */ +/** + * @defgroup mdm_regs_core_mu1_field mu1_field + * @brief macros for field mu1 + * @details First gear mu: Encoding is 2^-(mu1+2) + * @{ + */ +#define MDM_DCOFFTRK_ALT__MU1__SHIFT 3 +#define MDM_DCOFFTRK_ALT__MU1__WIDTH 3 +#define MDM_DCOFFTRK_ALT__MU1__MASK 0x00000038U +#define MDM_DCOFFTRK_ALT__MU1__READ(src) (((uint32_t)(src) & 0x00000038U) >> 3) +#define MDM_DCOFFTRK_ALT__MU1__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define MDM_DCOFFTRK_ALT__MU1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define MDM_DCOFFTRK_ALT__MU1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define MDM_DCOFFTRK_ALT__MU1__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field mu2 */ +/** + * @defgroup mdm_regs_core_mu2_field mu2_field + * @brief macros for field mu2 + * @details Second gear mu: Encoding is 2^-(mu2+2) + * @{ + */ +#define MDM_DCOFFTRK_ALT__MU2__SHIFT 6 +#define MDM_DCOFFTRK_ALT__MU2__WIDTH 3 +#define MDM_DCOFFTRK_ALT__MU2__MASK 0x000001c0U +#define MDM_DCOFFTRK_ALT__MU2__READ(src) (((uint32_t)(src) & 0x000001c0U) >> 6) +#define MDM_DCOFFTRK_ALT__MU2__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000001c0U) +#define MDM_DCOFFTRK_ALT__MU2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((uint32_t)(src) <<\ + 6) & 0x000001c0U) +#define MDM_DCOFFTRK_ALT__MU2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000001c0U))) +#define MDM_DCOFFTRK_ALT__MU2__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field mu3 */ +/** + * @defgroup mdm_regs_core_mu3_field mu3_field + * @brief macros for field mu3 + * @details Third gear mu: Encoding is 2^-(mu3+2) + * @{ + */ +#define MDM_DCOFFTRK_ALT__MU3__SHIFT 9 +#define MDM_DCOFFTRK_ALT__MU3__WIDTH 3 +#define MDM_DCOFFTRK_ALT__MU3__MASK 0x00000e00U +#define MDM_DCOFFTRK_ALT__MU3__READ(src) (((uint32_t)(src) & 0x00000e00U) >> 9) +#define MDM_DCOFFTRK_ALT__MU3__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000e00U) +#define MDM_DCOFFTRK_ALT__MU3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((uint32_t)(src) <<\ + 9) & 0x00000e00U) +#define MDM_DCOFFTRK_ALT__MU3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000e00U))) +#define MDM_DCOFFTRK_ALT__MU3__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field mu_count1 */ +/** + * @defgroup mdm_regs_core_mu_count1_field mu_count1_field + * @brief macros for field mu_count1 + * @details (mu_count1 * 8) = number of 16 MHz samples to switch to gear 2 + * @{ + */ +#define MDM_DCOFFTRK_ALT__MU_COUNT1__SHIFT 12 +#define MDM_DCOFFTRK_ALT__MU_COUNT1__WIDTH 6 +#define MDM_DCOFFTRK_ALT__MU_COUNT1__MASK 0x0003f000U +#define MDM_DCOFFTRK_ALT__MU_COUNT1__READ(src) \ + (((uint32_t)(src)\ + & 0x0003f000U) >> 12) +#define MDM_DCOFFTRK_ALT__MU_COUNT1__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0003f000U) +#define MDM_DCOFFTRK_ALT__MU_COUNT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((uint32_t)(src) <<\ + 12) & 0x0003f000U) +#define MDM_DCOFFTRK_ALT__MU_COUNT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0003f000U))) +#define MDM_DCOFFTRK_ALT__MU_COUNT1__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field mu_count2 */ +/** + * @defgroup mdm_regs_core_mu_count2_field mu_count2_field + * @brief macros for field mu_count2 + * @details (mu_count2 * 8) = number of 16 MHz samples to switch to gear 3. (Includes gear1 + gear2). MUST BE GREATER THAN MU_COUNT1 + * @{ + */ +#define MDM_DCOFFTRK_ALT__MU_COUNT2__SHIFT 18 +#define MDM_DCOFFTRK_ALT__MU_COUNT2__WIDTH 6 +#define MDM_DCOFFTRK_ALT__MU_COUNT2__MASK 0x00fc0000U +#define MDM_DCOFFTRK_ALT__MU_COUNT2__READ(src) \ + (((uint32_t)(src)\ + & 0x00fc0000U) >> 18) +#define MDM_DCOFFTRK_ALT__MU_COUNT2__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00fc0000U) +#define MDM_DCOFFTRK_ALT__MU_COUNT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((uint32_t)(src) <<\ + 18) & 0x00fc0000U) +#define MDM_DCOFFTRK_ALT__MU_COUNT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00fc0000U))) +#define MDM_DCOFFTRK_ALT__MU_COUNT2__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field corr_delay_idx */ +/** + * @defgroup mdm_regs_core_corr_delay_idx_field corr_delay_idx_field + * @brief macros for field corr_delay_idx + * @details Correction is applied (8 * corr_delay_idx) 16 MHz samples after tracking reset is released + * @{ + */ +#define MDM_DCOFFTRK_ALT__CORR_DELAY_IDX__SHIFT 24 +#define MDM_DCOFFTRK_ALT__CORR_DELAY_IDX__WIDTH 3 +#define MDM_DCOFFTRK_ALT__CORR_DELAY_IDX__MASK 0x07000000U +#define MDM_DCOFFTRK_ALT__CORR_DELAY_IDX__READ(src) \ + (((uint32_t)(src)\ + & 0x07000000U) >> 24) +#define MDM_DCOFFTRK_ALT__CORR_DELAY_IDX__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x07000000U) +#define MDM_DCOFFTRK_ALT__CORR_DELAY_IDX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((uint32_t)(src) <<\ + 24) & 0x07000000U) +#define MDM_DCOFFTRK_ALT__CORR_DELAY_IDX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x07000000U))) +#define MDM_DCOFFTRK_ALT__CORR_DELAY_IDX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field twomeg_en */ +/** + * @defgroup mdm_regs_core_twomeg_en_field twomeg_en_field + * @brief macros for field twomeg_en + * @details Enable tracking + * @{ + */ +#define MDM_DCOFFTRK_ALT__TWOMEG_EN__SHIFT 27 +#define MDM_DCOFFTRK_ALT__TWOMEG_EN__WIDTH 1 +#define MDM_DCOFFTRK_ALT__TWOMEG_EN__MASK 0x08000000U +#define MDM_DCOFFTRK_ALT__TWOMEG_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define MDM_DCOFFTRK_ALT__TWOMEG_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define MDM_DCOFFTRK_ALT__TWOMEG_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define MDM_DCOFFTRK_ALT__TWOMEG_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define MDM_DCOFFTRK_ALT__TWOMEG_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define MDM_DCOFFTRK_ALT__TWOMEG_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define MDM_DCOFFTRK_ALT__TWOMEG_EN__RESET_VALUE 0x00000001U +/** @} */ +#define MDM_DCOFFTRK_ALT__TYPE uint32_t +#define MDM_DCOFFTRK_ALT__READ 0x0fffffffU +#define MDM_DCOFFTRK_ALT__WRITE 0x0fffffffU +#define MDM_DCOFFTRK_ALT__PRESERVED 0x00000000U +#define MDM_DCOFFTRK_ALT__RESET_VALUE 0x08102d17U + +#endif /* __MDM_DCOFFTRK_ALT_MACRO__ */ + +/** @} end of dcofftrk_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_dcofftrk2 */ +/** + * @defgroup mdm_regs_core_dcofftrk2 dcofftrk2 + * @brief DC offset tracking, additional registers definitions. + * @{ + */ +#ifndef __MDM_DCOFFTRK2_MACRO__ +#define __MDM_DCOFFTRK2_MACRO__ + +/* macros for field reset_filt_delay */ +/** + * @defgroup mdm_regs_core_reset_filt_delay_field reset_filt_delay_field + * @brief macros for field reset_filt_delay + * @details Number of 16 clocks to hold DC tracking IIR in reset before releasing in the WAIT_GAIN_SETTLE state. MUST BE EVEN AND NON-ZERO. + * @{ + */ +#define MDM_DCOFFTRK2__RESET_FILT_DELAY__SHIFT 0 +#define MDM_DCOFFTRK2__RESET_FILT_DELAY__WIDTH 6 +#define MDM_DCOFFTRK2__RESET_FILT_DELAY__MASK 0x0000003fU +#define MDM_DCOFFTRK2__RESET_FILT_DELAY__READ(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_DCOFFTRK2__RESET_FILT_DELAY__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_DCOFFTRK2__RESET_FILT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define MDM_DCOFFTRK2__RESET_FILT_DELAY__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define MDM_DCOFFTRK2__RESET_FILT_DELAY__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field twomeg_reset_filt_delay */ +/** + * @defgroup mdm_regs_core_twomeg_reset_filt_delay_field twomeg_reset_filt_delay_field + * @brief macros for field twomeg_reset_filt_delay + * @details Number of 16 clocks to hold DC tracking IIR in reset before releasing in the WAIT_GAIN_SETTLE state, 2 Mb/s version Should be non-zero + * @{ + */ +#define MDM_DCOFFTRK2__TWOMEG_RESET_FILT_DELAY__SHIFT 6 +#define MDM_DCOFFTRK2__TWOMEG_RESET_FILT_DELAY__WIDTH 6 +#define MDM_DCOFFTRK2__TWOMEG_RESET_FILT_DELAY__MASK 0x00000fc0U +#define MDM_DCOFFTRK2__TWOMEG_RESET_FILT_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000fc0U) >> 6) +#define MDM_DCOFFTRK2__TWOMEG_RESET_FILT_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000fc0U) +#define MDM_DCOFFTRK2__TWOMEG_RESET_FILT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((uint32_t)(src) <<\ + 6) & 0x00000fc0U) +#define MDM_DCOFFTRK2__TWOMEG_RESET_FILT_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000fc0U))) +#define MDM_DCOFFTRK2__TWOMEG_RESET_FILT_DELAY__RESET_VALUE 0x0000000aU +/** @} */ + +/* macros for field xlna_reset_filt_delay */ +/** + * @defgroup mdm_regs_core_xlna_reset_filt_delay_field xlna_reset_filt_delay_field + * @brief macros for field xlna_reset_filt_delay + * @details Number of 16 clocks to hold DC tracking IIR in reset before releasing in the WAIT_GAIN_SETTLE state. MUST BE EVEN AND NON-ZERO. + * @{ + */ +#define MDM_DCOFFTRK2__XLNA_RESET_FILT_DELAY__SHIFT 12 +#define MDM_DCOFFTRK2__XLNA_RESET_FILT_DELAY__WIDTH 6 +#define MDM_DCOFFTRK2__XLNA_RESET_FILT_DELAY__MASK 0x0003f000U +#define MDM_DCOFFTRK2__XLNA_RESET_FILT_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x0003f000U) >> 12) +#define MDM_DCOFFTRK2__XLNA_RESET_FILT_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0003f000U) +#define MDM_DCOFFTRK2__XLNA_RESET_FILT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((uint32_t)(src) <<\ + 12) & 0x0003f000U) +#define MDM_DCOFFTRK2__XLNA_RESET_FILT_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0003f000U))) +#define MDM_DCOFFTRK2__XLNA_RESET_FILT_DELAY__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field twomeg_xlna_reset_filt_delay */ +/** + * @defgroup mdm_regs_core_twomeg_xlna_reset_filt_delay_field twomeg_xlna_reset_filt_delay_field + * @brief macros for field twomeg_xlna_reset_filt_delay + * @details Number of 16 clocks to hold DC tracking IIR in reset before releasing in the WAIT_GAIN_SETTLE state, 2 Mb/s version Should be non-zero + * @{ + */ +#define MDM_DCOFFTRK2__TWOMEG_XLNA_RESET_FILT_DELAY__SHIFT 18 +#define MDM_DCOFFTRK2__TWOMEG_XLNA_RESET_FILT_DELAY__WIDTH 6 +#define MDM_DCOFFTRK2__TWOMEG_XLNA_RESET_FILT_DELAY__MASK 0x00fc0000U +#define MDM_DCOFFTRK2__TWOMEG_XLNA_RESET_FILT_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x00fc0000U) >> 18) +#define MDM_DCOFFTRK2__TWOMEG_XLNA_RESET_FILT_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00fc0000U) +#define MDM_DCOFFTRK2__TWOMEG_XLNA_RESET_FILT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((uint32_t)(src) <<\ + 18) & 0x00fc0000U) +#define MDM_DCOFFTRK2__TWOMEG_XLNA_RESET_FILT_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00fc0000U))) +#define MDM_DCOFFTRK2__TWOMEG_XLNA_RESET_FILT_DELAY__RESET_VALUE 0x0000000aU +/** @} */ +#define MDM_DCOFFTRK2__TYPE uint32_t +#define MDM_DCOFFTRK2__READ 0x00ffffffU +#define MDM_DCOFFTRK2__WRITE 0x00ffffffU +#define MDM_DCOFFTRK2__PRESERVED 0x00000000U +#define MDM_DCOFFTRK2__RESET_VALUE 0x00290290U + +#endif /* __MDM_DCOFFTRK2_MACRO__ */ + +/** @} end of dcofftrk2 */ + +/* macros for BlueprintGlobalNameSpace::MDM_dcofftrk2_alt */ +/** + * @defgroup mdm_regs_core_dcofftrk2_alt dcofftrk2_alt + * @brief DC offset tracking, additional registers, alternate set definitions. + * @{ + */ +#ifndef __MDM_DCOFFTRK2_ALT_MACRO__ +#define __MDM_DCOFFTRK2_ALT_MACRO__ + +/* macros for field reset_filt_delay */ +/** + * @defgroup mdm_regs_core_reset_filt_delay_field reset_filt_delay_field + * @brief macros for field reset_filt_delay + * @details Number of 16 clocks to hold DC tracking IIR in reset before releasing in the WAIT_GAIN_SETTLE state. MUST BE EVEN AND NON-ZERO. + * @{ + */ +#define MDM_DCOFFTRK2_ALT__RESET_FILT_DELAY__SHIFT 0 +#define MDM_DCOFFTRK2_ALT__RESET_FILT_DELAY__WIDTH 6 +#define MDM_DCOFFTRK2_ALT__RESET_FILT_DELAY__MASK 0x0000003fU +#define MDM_DCOFFTRK2_ALT__RESET_FILT_DELAY__READ(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_DCOFFTRK2_ALT__RESET_FILT_DELAY__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_DCOFFTRK2_ALT__RESET_FILT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define MDM_DCOFFTRK2_ALT__RESET_FILT_DELAY__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define MDM_DCOFFTRK2_ALT__RESET_FILT_DELAY__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field twomeg_reset_filt_delay */ +/** + * @defgroup mdm_regs_core_twomeg_reset_filt_delay_field twomeg_reset_filt_delay_field + * @brief macros for field twomeg_reset_filt_delay + * @details Number of 16 clocks to hold DC tracking IIR in reset before releasing in the WAIT_GAIN_SETTLE state, 2 Mb/s version Should be non-zero + * @{ + */ +#define MDM_DCOFFTRK2_ALT__TWOMEG_RESET_FILT_DELAY__SHIFT 6 +#define MDM_DCOFFTRK2_ALT__TWOMEG_RESET_FILT_DELAY__WIDTH 6 +#define MDM_DCOFFTRK2_ALT__TWOMEG_RESET_FILT_DELAY__MASK 0x00000fc0U +#define MDM_DCOFFTRK2_ALT__TWOMEG_RESET_FILT_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000fc0U) >> 6) +#define MDM_DCOFFTRK2_ALT__TWOMEG_RESET_FILT_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000fc0U) +#define MDM_DCOFFTRK2_ALT__TWOMEG_RESET_FILT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((uint32_t)(src) <<\ + 6) & 0x00000fc0U) +#define MDM_DCOFFTRK2_ALT__TWOMEG_RESET_FILT_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000fc0U))) +#define MDM_DCOFFTRK2_ALT__TWOMEG_RESET_FILT_DELAY__RESET_VALUE 0x0000000aU +/** @} */ + +/* macros for field xlna_reset_filt_delay */ +/** + * @defgroup mdm_regs_core_xlna_reset_filt_delay_field xlna_reset_filt_delay_field + * @brief macros for field xlna_reset_filt_delay + * @details Number of 16 clocks to hold DC tracking IIR in reset before releasing in the WAIT_GAIN_SETTLE state. MUST BE EVEN AND NON-ZERO. + * @{ + */ +#define MDM_DCOFFTRK2_ALT__XLNA_RESET_FILT_DELAY__SHIFT 12 +#define MDM_DCOFFTRK2_ALT__XLNA_RESET_FILT_DELAY__WIDTH 6 +#define MDM_DCOFFTRK2_ALT__XLNA_RESET_FILT_DELAY__MASK 0x0003f000U +#define MDM_DCOFFTRK2_ALT__XLNA_RESET_FILT_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x0003f000U) >> 12) +#define MDM_DCOFFTRK2_ALT__XLNA_RESET_FILT_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0003f000U) +#define MDM_DCOFFTRK2_ALT__XLNA_RESET_FILT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((uint32_t)(src) <<\ + 12) & 0x0003f000U) +#define MDM_DCOFFTRK2_ALT__XLNA_RESET_FILT_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0003f000U))) +#define MDM_DCOFFTRK2_ALT__XLNA_RESET_FILT_DELAY__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field twomeg_xlna_reset_filt_delay */ +/** + * @defgroup mdm_regs_core_twomeg_xlna_reset_filt_delay_field twomeg_xlna_reset_filt_delay_field + * @brief macros for field twomeg_xlna_reset_filt_delay + * @details Number of 16 clocks to hold DC tracking IIR in reset before releasing in the WAIT_GAIN_SETTLE state, 2 Mb/s version Should be non-zero + * @{ + */ +#define MDM_DCOFFTRK2_ALT__TWOMEG_XLNA_RESET_FILT_DELAY__SHIFT 18 +#define MDM_DCOFFTRK2_ALT__TWOMEG_XLNA_RESET_FILT_DELAY__WIDTH 6 +#define MDM_DCOFFTRK2_ALT__TWOMEG_XLNA_RESET_FILT_DELAY__MASK 0x00fc0000U +#define MDM_DCOFFTRK2_ALT__TWOMEG_XLNA_RESET_FILT_DELAY__READ(src) \ + (((uint32_t)(src)\ + & 0x00fc0000U) >> 18) +#define MDM_DCOFFTRK2_ALT__TWOMEG_XLNA_RESET_FILT_DELAY__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00fc0000U) +#define MDM_DCOFFTRK2_ALT__TWOMEG_XLNA_RESET_FILT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((uint32_t)(src) <<\ + 18) & 0x00fc0000U) +#define MDM_DCOFFTRK2_ALT__TWOMEG_XLNA_RESET_FILT_DELAY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00fc0000U))) +#define MDM_DCOFFTRK2_ALT__TWOMEG_XLNA_RESET_FILT_DELAY__RESET_VALUE \ + 0x0000000aU +/** @} */ +#define MDM_DCOFFTRK2_ALT__TYPE uint32_t +#define MDM_DCOFFTRK2_ALT__READ 0x00ffffffU +#define MDM_DCOFFTRK2_ALT__WRITE 0x00ffffffU +#define MDM_DCOFFTRK2_ALT__PRESERVED 0x00000000U +#define MDM_DCOFFTRK2_ALT__RESET_VALUE 0x00290290U + +#endif /* __MDM_DCOFFTRK2_ALT_MACRO__ */ + +/** @} end of dcofftrk2_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_dfcntl */ +/** + * @defgroup mdm_regs_core_dfcntl dfcntl + * @brief Direction Finding control definitions. + * @{ + */ +#ifndef __MDM_DFCNTL_MACRO__ +#define __MDM_DFCNTL_MACRO__ + +/* macros for field iq_select */ +/** + * @defgroup mdm_regs_core_iq_select_field iq_select_field + * @brief macros for field iq_select + * @details Tap point for RX IQ samples sent to LC. I/Q of tap point are normalized prior to sending. 3'd0 -> rif_i/q 3'd1 -> dcoff_i/q 3'd2 -> iqcorr_i/q 3'd3 -> cic_i/q 3'd4 -> mixer_i/q 3'd5 -> rxfir_i/q + * @{ + */ +#define MDM_DFCNTL__IQ_SELECT__SHIFT 0 +#define MDM_DFCNTL__IQ_SELECT__WIDTH 3 +#define MDM_DFCNTL__IQ_SELECT__MASK 0x00000007U +#define MDM_DFCNTL__IQ_SELECT__READ(src) ((uint32_t)(src) & 0x00000007U) +#define MDM_DFCNTL__IQ_SELECT__WRITE(src) ((uint32_t)(src) & 0x00000007U) +#define MDM_DFCNTL__IQ_SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define MDM_DFCNTL__IQ_SELECT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define MDM_DFCNTL__IQ_SELECT__RESET_VALUE 0x00000005U +/** @} */ + +/* macros for field twomeg_iq_select */ +/** + * @defgroup mdm_regs_core_twomeg_iq_select_field twomeg_iq_select_field + * @brief macros for field twomeg_iq_select + * @details Tap point for RX IQ samples sent to LC. I/Q of tap point are normalized prior to sending. 3'd0 -> rif_i/q 3'd1 -> dcoff_i/q 3'd2 -> iqcorr_i/q 3'd3 -> cic_i/q 3'd4 -> mixer_i/q 3'd5 -> rxfir_i/q + * @{ + */ +#define MDM_DFCNTL__TWOMEG_IQ_SELECT__SHIFT 3 +#define MDM_DFCNTL__TWOMEG_IQ_SELECT__WIDTH 3 +#define MDM_DFCNTL__TWOMEG_IQ_SELECT__MASK 0x00000038U +#define MDM_DFCNTL__TWOMEG_IQ_SELECT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define MDM_DFCNTL__TWOMEG_IQ_SELECT__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define MDM_DFCNTL__TWOMEG_IQ_SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define MDM_DFCNTL__TWOMEG_IQ_SELECT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define MDM_DFCNTL__TWOMEG_IQ_SELECT__RESET_VALUE 0x00000005U +/** @} */ + +/* macros for field left_shift */ +/** + * @defgroup mdm_regs_core_left_shift_field left_shift_field + * @brief macros for field left_shift + * @details The output IQ samples are 8 bits, but the inputs are either 8 bits (rif/dcoff/iqcorr), 9 bits (cic/mixer) or 14 bits (rxfir) left_shift specifies which window of 8 bits to use. 0 means to use the most significant 8 bits available for the chosen field (rif/dcoff/iqcorr/cic/mixer/rxfir). If left_shift is non-zero, then left shift the chosen field by the specified amount. For rif/dcoff/iqcorr, left_shift should be 0 (8 bits in, 8 bits out, easy). For cic/mixer, left_shift should be 0 or 1. For rxfir, left_shift should be between 0 and 6. As the value of left_shift increases, the chance of overflowing also increases. Overflows by 1 bit will be correctly saturated. Overflows by more than 1 bit will not. + * @{ + */ +#define MDM_DFCNTL__LEFT_SHIFT__SHIFT 6 +#define MDM_DFCNTL__LEFT_SHIFT__WIDTH 3 +#define MDM_DFCNTL__LEFT_SHIFT__MASK 0x000001c0U +#define MDM_DFCNTL__LEFT_SHIFT__READ(src) \ + (((uint32_t)(src)\ + & 0x000001c0U) >> 6) +#define MDM_DFCNTL__LEFT_SHIFT__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000001c0U) +#define MDM_DFCNTL__LEFT_SHIFT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((uint32_t)(src) <<\ + 6) & 0x000001c0U) +#define MDM_DFCNTL__LEFT_SHIFT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000001c0U))) +#define MDM_DFCNTL__LEFT_SHIFT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field twomeg_left_shift */ +/** + * @defgroup mdm_regs_core_twomeg_left_shift_field twomeg_left_shift_field + * @brief macros for field twomeg_left_shift + * @details Same as left_shift, but for 2Mb/s + * @{ + */ +#define MDM_DFCNTL__TWOMEG_LEFT_SHIFT__SHIFT 9 +#define MDM_DFCNTL__TWOMEG_LEFT_SHIFT__WIDTH 3 +#define MDM_DFCNTL__TWOMEG_LEFT_SHIFT__MASK 0x00000e00U +#define MDM_DFCNTL__TWOMEG_LEFT_SHIFT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000e00U) >> 9) +#define MDM_DFCNTL__TWOMEG_LEFT_SHIFT__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000e00U) +#define MDM_DFCNTL__TWOMEG_LEFT_SHIFT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((uint32_t)(src) <<\ + 9) & 0x00000e00U) +#define MDM_DFCNTL__TWOMEG_LEFT_SHIFT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000e00U))) +#define MDM_DFCNTL__TWOMEG_LEFT_SHIFT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dynamic_left_shift */ +/** + * @defgroup mdm_regs_core_dynamic_left_shift_field dynamic_left_shift_field + * @brief macros for field dynamic_left_shift + * @details 0 -> Use left_shift/twomeg_left_shift directly 1 -> Use dftable, indexed by baseline_pwr per packet + * @{ + */ +#define MDM_DFCNTL__DYNAMIC_LEFT_SHIFT__SHIFT 12 +#define MDM_DFCNTL__DYNAMIC_LEFT_SHIFT__WIDTH 1 +#define MDM_DFCNTL__DYNAMIC_LEFT_SHIFT__MASK 0x00001000U +#define MDM_DFCNTL__DYNAMIC_LEFT_SHIFT__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define MDM_DFCNTL__DYNAMIC_LEFT_SHIFT__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define MDM_DFCNTL__DYNAMIC_LEFT_SHIFT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define MDM_DFCNTL__DYNAMIC_LEFT_SHIFT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define MDM_DFCNTL__DYNAMIC_LEFT_SHIFT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define MDM_DFCNTL__DYNAMIC_LEFT_SHIFT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define MDM_DFCNTL__DYNAMIC_LEFT_SHIFT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field update_on_cte_only */ +/** + * @defgroup mdm_regs_core_update_on_cte_only_field update_on_cte_only_field + * @brief macros for field update_on_cte_only + * @details When to update the dfstatus register 0 -> Anytime access address found 1 -> Only on CTE packets, when the LC asserts lc_direction_find_enable + * @{ + */ +#define MDM_DFCNTL__UPDATE_ON_CTE_ONLY__SHIFT 13 +#define MDM_DFCNTL__UPDATE_ON_CTE_ONLY__WIDTH 1 +#define MDM_DFCNTL__UPDATE_ON_CTE_ONLY__MASK 0x00002000U +#define MDM_DFCNTL__UPDATE_ON_CTE_ONLY__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define MDM_DFCNTL__UPDATE_ON_CTE_ONLY__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define MDM_DFCNTL__UPDATE_ON_CTE_ONLY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define MDM_DFCNTL__UPDATE_ON_CTE_ONLY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define MDM_DFCNTL__UPDATE_ON_CTE_ONLY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define MDM_DFCNTL__UPDATE_ON_CTE_ONLY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define MDM_DFCNTL__UPDATE_ON_CTE_ONLY__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field antmode */ +/** + * @defgroup mdm_regs_core_antmode_field antmode_field + * @brief macros for field antmode + * @details 2'b00 -> Use 3 LSBs from LC antenna id 2'b01 -> Output LC antenna id directly 2'b10 -> Compare LC antenna id to 8 IDs in antid registers + * @{ + */ +#define MDM_DFCNTL__ANTMODE__SHIFT 14 +#define MDM_DFCNTL__ANTMODE__WIDTH 2 +#define MDM_DFCNTL__ANTMODE__MASK 0x0000c000U +#define MDM_DFCNTL__ANTMODE__READ(src) (((uint32_t)(src) & 0x0000c000U) >> 14) +#define MDM_DFCNTL__ANTMODE__WRITE(src) (((uint32_t)(src) << 14) & 0x0000c000U) +#define MDM_DFCNTL__ANTMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000c000U) | (((uint32_t)(src) <<\ + 14) & 0x0000c000U) +#define MDM_DFCNTL__ANTMODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0000c000U))) +#define MDM_DFCNTL__ANTMODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sw_ant_select */ +/** + * @defgroup mdm_regs_core_sw_ant_select_field sw_ant_select_field + * @brief macros for field sw_ant_select + * @details Antenna table index controlled directly by SW. Which, if any, of these bits that are actively used is determined by the use_sw_antenna_select field + * @{ + */ +#define MDM_DFCNTL__SW_ANT_SELECT__SHIFT 16 +#define MDM_DFCNTL__SW_ANT_SELECT__WIDTH 3 +#define MDM_DFCNTL__SW_ANT_SELECT__MASK 0x00070000U +#define MDM_DFCNTL__SW_ANT_SELECT__READ(src) \ + (((uint32_t)(src)\ + & 0x00070000U) >> 16) +#define MDM_DFCNTL__SW_ANT_SELECT__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00070000U) +#define MDM_DFCNTL__SW_ANT_SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((uint32_t)(src) <<\ + 16) & 0x00070000U) +#define MDM_DFCNTL__SW_ANT_SELECT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00070000U))) +#define MDM_DFCNTL__SW_ANT_SELECT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field use_sw_ant_select */ +/** + * @defgroup mdm_regs_core_use_sw_ant_select_field use_sw_ant_select_field + * @brief macros for field use_sw_ant_select + * @details For each of these three bits, a '1' means to use the corresponding bit from sw_antenna_select for the antenna table index. A '0' means to use the corresponding bit from the LC antenna select as a function of antmode (only for antmode == 0 or 2) + * @{ + */ +#define MDM_DFCNTL__USE_SW_ANT_SELECT__SHIFT 19 +#define MDM_DFCNTL__USE_SW_ANT_SELECT__WIDTH 3 +#define MDM_DFCNTL__USE_SW_ANT_SELECT__MASK 0x00380000U +#define MDM_DFCNTL__USE_SW_ANT_SELECT__READ(src) \ + (((uint32_t)(src)\ + & 0x00380000U) >> 19) +#define MDM_DFCNTL__USE_SW_ANT_SELECT__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00380000U) +#define MDM_DFCNTL__USE_SW_ANT_SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00380000U) | (((uint32_t)(src) <<\ + 19) & 0x00380000U) +#define MDM_DFCNTL__USE_SW_ANT_SELECT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00380000U))) +#define MDM_DFCNTL__USE_SW_ANT_SELECT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field use_default_sw_ant_select_for_cte */ +/** + * @defgroup mdm_regs_core_use_default_sw_ant_select_for_cte_field use_default_sw_ant_select_for_cte_field + * @brief macros for field use_default_sw_ant_select_for_cte + * @details For the CTE portion of packets, the same sequencing of antennas may be wanted regardless of the antenna diversity selection specified by sw_ant_select. If so, this can be accomplished by setting the use_default_sw_ant_select_for_cte bit, which will have the effect of forcing sw_ant_select = sw_ant_select_cte during the CTE portion + * @{ + */ +#define MDM_DFCNTL__USE_DEFAULT_SW_ANT_SELECT_FOR_CTE__SHIFT 22 +#define MDM_DFCNTL__USE_DEFAULT_SW_ANT_SELECT_FOR_CTE__WIDTH 1 +#define MDM_DFCNTL__USE_DEFAULT_SW_ANT_SELECT_FOR_CTE__MASK 0x00400000U +#define MDM_DFCNTL__USE_DEFAULT_SW_ANT_SELECT_FOR_CTE__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define MDM_DFCNTL__USE_DEFAULT_SW_ANT_SELECT_FOR_CTE__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define MDM_DFCNTL__USE_DEFAULT_SW_ANT_SELECT_FOR_CTE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define MDM_DFCNTL__USE_DEFAULT_SW_ANT_SELECT_FOR_CTE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define MDM_DFCNTL__USE_DEFAULT_SW_ANT_SELECT_FOR_CTE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define MDM_DFCNTL__USE_DEFAULT_SW_ANT_SELECT_FOR_CTE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define MDM_DFCNTL__USE_DEFAULT_SW_ANT_SELECT_FOR_CTE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field sw_ant_select_for_cte */ +/** + * @defgroup mdm_regs_core_sw_ant_select_for_cte_field sw_ant_select_for_cte_field + * @brief macros for field sw_ant_select_for_cte + * @details If use_default_sw_ant_select_for_cte is set, force sw_ant_select = sw_ant_select_for_cte during CTE portion + * @{ + */ +#define MDM_DFCNTL__SW_ANT_SELECT_FOR_CTE__SHIFT 23 +#define MDM_DFCNTL__SW_ANT_SELECT_FOR_CTE__WIDTH 3 +#define MDM_DFCNTL__SW_ANT_SELECT_FOR_CTE__MASK 0x03800000U +#define MDM_DFCNTL__SW_ANT_SELECT_FOR_CTE__READ(src) \ + (((uint32_t)(src)\ + & 0x03800000U) >> 23) +#define MDM_DFCNTL__SW_ANT_SELECT_FOR_CTE__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x03800000U) +#define MDM_DFCNTL__SW_ANT_SELECT_FOR_CTE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((uint32_t)(src) <<\ + 23) & 0x03800000U) +#define MDM_DFCNTL__SW_ANT_SELECT_FOR_CTE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x03800000U))) +#define MDM_DFCNTL__SW_ANT_SELECT_FOR_CTE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field update_rd_freq_est_during_cte */ +/** + * @defgroup mdm_regs_core_update_rd_freq_est_during_cte_field update_rd_freq_est_during_cte_field + * @brief macros for field update_rd_freq_est_during_cte + * @details If high, continue to update measfreq_freq_offset even during CTE portion of packet. If low, then do not. + * @{ + */ +#define MDM_DFCNTL__UPDATE_RD_FREQ_EST_DURING_CTE__SHIFT 26 +#define MDM_DFCNTL__UPDATE_RD_FREQ_EST_DURING_CTE__WIDTH 1 +#define MDM_DFCNTL__UPDATE_RD_FREQ_EST_DURING_CTE__MASK 0x04000000U +#define MDM_DFCNTL__UPDATE_RD_FREQ_EST_DURING_CTE__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define MDM_DFCNTL__UPDATE_RD_FREQ_EST_DURING_CTE__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define MDM_DFCNTL__UPDATE_RD_FREQ_EST_DURING_CTE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define MDM_DFCNTL__UPDATE_RD_FREQ_EST_DURING_CTE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define MDM_DFCNTL__UPDATE_RD_FREQ_EST_DURING_CTE__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define MDM_DFCNTL__UPDATE_RD_FREQ_EST_DURING_CTE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define MDM_DFCNTL__UPDATE_RD_FREQ_EST_DURING_CTE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_DFCNTL__TYPE uint32_t +#define MDM_DFCNTL__READ 0x07ffffffU +#define MDM_DFCNTL__WRITE 0x07ffffffU +#define MDM_DFCNTL__PRESERVED 0x00000000U +#define MDM_DFCNTL__RESET_VALUE 0x0040202dU + +#endif /* __MDM_DFCNTL_MACRO__ */ + +/** @} end of dfcntl */ + +/* macros for BlueprintGlobalNameSpace::MDM_dfcntl_alt */ +/** + * @defgroup mdm_regs_core_dfcntl_alt dfcntl_alt + * @brief Direction Finding control, alternate set, but just for one register field definitions. + * @{ + */ +#ifndef __MDM_DFCNTL_ALT_MACRO__ +#define __MDM_DFCNTL_ALT_MACRO__ + +/* macros for field sw_ant_select */ +/** + * @defgroup mdm_regs_core_sw_ant_select_field sw_ant_select_field + * @brief macros for field sw_ant_select + * @details Antenna table index controlled directly by SW. Which, if any, of these bits that are actively used is determined by the use_sw_antenna_select field + * @{ + */ +#define MDM_DFCNTL_ALT__SW_ANT_SELECT__SHIFT 16 +#define MDM_DFCNTL_ALT__SW_ANT_SELECT__WIDTH 3 +#define MDM_DFCNTL_ALT__SW_ANT_SELECT__MASK 0x00070000U +#define MDM_DFCNTL_ALT__SW_ANT_SELECT__READ(src) \ + (((uint32_t)(src)\ + & 0x00070000U) >> 16) +#define MDM_DFCNTL_ALT__SW_ANT_SELECT__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00070000U) +#define MDM_DFCNTL_ALT__SW_ANT_SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((uint32_t)(src) <<\ + 16) & 0x00070000U) +#define MDM_DFCNTL_ALT__SW_ANT_SELECT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00070000U))) +#define MDM_DFCNTL_ALT__SW_ANT_SELECT__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_DFCNTL_ALT__TYPE uint32_t +#define MDM_DFCNTL_ALT__READ 0x00070000U +#define MDM_DFCNTL_ALT__WRITE 0x00070000U +#define MDM_DFCNTL_ALT__PRESERVED 0x00000000U +#define MDM_DFCNTL_ALT__RESET_VALUE 0x00000000U + +#endif /* __MDM_DFCNTL_ALT_MACRO__ */ + +/** @} end of dfcntl_alt */ + +/* macros for BlueprintGlobalNameSpace::MDM_swantctetime */ +/** + * @defgroup mdm_regs_core_swantctetime swantctetime + * @brief If use_default_sw_ant_select_for_cte = 1, then start forcing sw_ant_select = sw_ant_select_for_cte a programmable amount of time after the LC asserts DF_mode_enable. The programmable delay is specified differently for (TX vs RX), and (1 Mb/s vs 2 Mb/s). definitions. + * @{ + */ +#ifndef __MDM_SWANTCTETIME_MACRO__ +#define __MDM_SWANTCTETIME_MACRO__ + +/* macros for field rx */ +/** + * @defgroup mdm_regs_core_rx_field rx_field + * @brief macros for field rx + * @details Delay in 16 MHz clocks for 1M rx + * @{ + */ +#define MDM_SWANTCTETIME__RX__SHIFT 0 +#define MDM_SWANTCTETIME__RX__WIDTH 7 +#define MDM_SWANTCTETIME__RX__MASK 0x0000007fU +#define MDM_SWANTCTETIME__RX__READ(src) ((uint32_t)(src) & 0x0000007fU) +#define MDM_SWANTCTETIME__RX__WRITE(src) ((uint32_t)(src) & 0x0000007fU) +#define MDM_SWANTCTETIME__RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define MDM_SWANTCTETIME__RX__VERIFY(src) (!(((uint32_t)(src) & ~0x0000007fU))) +#define MDM_SWANTCTETIME__RX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tx */ +/** + * @defgroup mdm_regs_core_tx_field tx_field + * @brief macros for field tx + * @details Delay in 16 MHz clocks for 1M tx + * @{ + */ +#define MDM_SWANTCTETIME__TX__SHIFT 7 +#define MDM_SWANTCTETIME__TX__WIDTH 7 +#define MDM_SWANTCTETIME__TX__MASK 0x00003f80U +#define MDM_SWANTCTETIME__TX__READ(src) (((uint32_t)(src) & 0x00003f80U) >> 7) +#define MDM_SWANTCTETIME__TX__WRITE(src) (((uint32_t)(src) << 7) & 0x00003f80U) +#define MDM_SWANTCTETIME__TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((uint32_t)(src) <<\ + 7) & 0x00003f80U) +#define MDM_SWANTCTETIME__TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00003f80U))) +#define MDM_SWANTCTETIME__TX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field twomeg_rx */ +/** + * @defgroup mdm_regs_core_twomeg_rx_field twomeg_rx_field + * @brief macros for field twomeg_rx + * @details Delay in 16 MHz clocks for 2M rx + * @{ + */ +#define MDM_SWANTCTETIME__TWOMEG_RX__SHIFT 14 +#define MDM_SWANTCTETIME__TWOMEG_RX__WIDTH 7 +#define MDM_SWANTCTETIME__TWOMEG_RX__MASK 0x001fc000U +#define MDM_SWANTCTETIME__TWOMEG_RX__READ(src) \ + (((uint32_t)(src)\ + & 0x001fc000U) >> 14) +#define MDM_SWANTCTETIME__TWOMEG_RX__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x001fc000U) +#define MDM_SWANTCTETIME__TWOMEG_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001fc000U) | (((uint32_t)(src) <<\ + 14) & 0x001fc000U) +#define MDM_SWANTCTETIME__TWOMEG_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x001fc000U))) +#define MDM_SWANTCTETIME__TWOMEG_RX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field twomeg_tx */ +/** + * @defgroup mdm_regs_core_twomeg_tx_field twomeg_tx_field + * @brief macros for field twomeg_tx + * @details Delay in 16 MHz clocks for 2M tx + * @{ + */ +#define MDM_SWANTCTETIME__TWOMEG_TX__SHIFT 21 +#define MDM_SWANTCTETIME__TWOMEG_TX__WIDTH 7 +#define MDM_SWANTCTETIME__TWOMEG_TX__MASK 0x0fe00000U +#define MDM_SWANTCTETIME__TWOMEG_TX__READ(src) \ + (((uint32_t)(src)\ + & 0x0fe00000U) >> 21) +#define MDM_SWANTCTETIME__TWOMEG_TX__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x0fe00000U) +#define MDM_SWANTCTETIME__TWOMEG_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fe00000U) | (((uint32_t)(src) <<\ + 21) & 0x0fe00000U) +#define MDM_SWANTCTETIME__TWOMEG_TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x0fe00000U))) +#define MDM_SWANTCTETIME__TWOMEG_TX__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_SWANTCTETIME__TYPE uint32_t +#define MDM_SWANTCTETIME__READ 0x0fffffffU +#define MDM_SWANTCTETIME__WRITE 0x0fffffffU +#define MDM_SWANTCTETIME__PRESERVED 0x00000000U +#define MDM_SWANTCTETIME__RESET_VALUE 0x00000000U + +#endif /* __MDM_SWANTCTETIME_MACRO__ */ + +/** @} end of swantctetime */ + +/* macros for BlueprintGlobalNameSpace::MDM_dftable */ +/** + * @defgroup mdm_regs_core_dftable dftable + * @brief Table for direction finding IQ scaling, indexed by baseline_pwr definitions. + * @{ + */ +#ifndef __MDM_DFTABLE_MACRO__ +#define __MDM_DFTABLE_MACRO__ + +/* macros for field m5to0 */ +/** + * @defgroup mdm_regs_core_m5to0_field m5to0_field + * @brief macros for field m5to0 + * @details left shift for -5 <= baseline_pwr <= 0 + * @{ + */ +#define MDM_DFTABLE__M5TO0__SHIFT 0 +#define MDM_DFTABLE__M5TO0__WIDTH 3 +#define MDM_DFTABLE__M5TO0__MASK 0x00000007U +#define MDM_DFTABLE__M5TO0__READ(src) ((uint32_t)(src) & 0x00000007U) +#define MDM_DFTABLE__M5TO0__WRITE(src) ((uint32_t)(src) & 0x00000007U) +#define MDM_DFTABLE__M5TO0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define MDM_DFTABLE__M5TO0__VERIFY(src) (!(((uint32_t)(src) & ~0x00000007U))) +#define MDM_DFTABLE__M5TO0__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field m11tom6 */ +/** + * @defgroup mdm_regs_core_m11tom6_field m11tom6_field + * @brief macros for field m11tom6 + * @details left shift for -11 <= baseline_pwr <= -6 + * @{ + */ +#define MDM_DFTABLE__M11TOM6__SHIFT 3 +#define MDM_DFTABLE__M11TOM6__WIDTH 3 +#define MDM_DFTABLE__M11TOM6__MASK 0x00000038U +#define MDM_DFTABLE__M11TOM6__READ(src) (((uint32_t)(src) & 0x00000038U) >> 3) +#define MDM_DFTABLE__M11TOM6__WRITE(src) (((uint32_t)(src) << 3) & 0x00000038U) +#define MDM_DFTABLE__M11TOM6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define MDM_DFTABLE__M11TOM6__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define MDM_DFTABLE__M11TOM6__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field m17tom12 */ +/** + * @defgroup mdm_regs_core_m17tom12_field m17tom12_field + * @brief macros for field m17tom12 + * @details left shift for -17 <= baseline_pwr <= -12 + * @{ + */ +#define MDM_DFTABLE__M17TOM12__SHIFT 6 +#define MDM_DFTABLE__M17TOM12__WIDTH 3 +#define MDM_DFTABLE__M17TOM12__MASK 0x000001c0U +#define MDM_DFTABLE__M17TOM12__READ(src) (((uint32_t)(src) & 0x000001c0U) >> 6) +#define MDM_DFTABLE__M17TOM12__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000001c0U) +#define MDM_DFTABLE__M17TOM12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((uint32_t)(src) <<\ + 6) & 0x000001c0U) +#define MDM_DFTABLE__M17TOM12__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000001c0U))) +#define MDM_DFTABLE__M17TOM12__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field m23tom18 */ +/** + * @defgroup mdm_regs_core_m23tom18_field m23tom18_field + * @brief macros for field m23tom18 + * @details left shift for -23 <= baseline_pwr <= -18 + * @{ + */ +#define MDM_DFTABLE__M23TOM18__SHIFT 9 +#define MDM_DFTABLE__M23TOM18__WIDTH 3 +#define MDM_DFTABLE__M23TOM18__MASK 0x00000e00U +#define MDM_DFTABLE__M23TOM18__READ(src) (((uint32_t)(src) & 0x00000e00U) >> 9) +#define MDM_DFTABLE__M23TOM18__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000e00U) +#define MDM_DFTABLE__M23TOM18__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((uint32_t)(src) <<\ + 9) & 0x00000e00U) +#define MDM_DFTABLE__M23TOM18__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000e00U))) +#define MDM_DFTABLE__M23TOM18__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field m29tom24 */ +/** + * @defgroup mdm_regs_core_m29tom24_field m29tom24_field + * @brief macros for field m29tom24 + * @details left shift for -29 <= baseline_pwr <= -24 + * @{ + */ +#define MDM_DFTABLE__M29TOM24__SHIFT 12 +#define MDM_DFTABLE__M29TOM24__WIDTH 3 +#define MDM_DFTABLE__M29TOM24__MASK 0x00007000U +#define MDM_DFTABLE__M29TOM24__READ(src) \ + (((uint32_t)(src)\ + & 0x00007000U) >> 12) +#define MDM_DFTABLE__M29TOM24__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00007000U) +#define MDM_DFTABLE__M29TOM24__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((uint32_t)(src) <<\ + 12) & 0x00007000U) +#define MDM_DFTABLE__M29TOM24__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00007000U))) +#define MDM_DFTABLE__M29TOM24__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field m35tom30 */ +/** + * @defgroup mdm_regs_core_m35tom30_field m35tom30_field + * @brief macros for field m35tom30 + * @details left shift for -35 <= baseline_pwr <= -30 + * @{ + */ +#define MDM_DFTABLE__M35TOM30__SHIFT 15 +#define MDM_DFTABLE__M35TOM30__WIDTH 3 +#define MDM_DFTABLE__M35TOM30__MASK 0x00038000U +#define MDM_DFTABLE__M35TOM30__READ(src) \ + (((uint32_t)(src)\ + & 0x00038000U) >> 15) +#define MDM_DFTABLE__M35TOM30__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00038000U) +#define MDM_DFTABLE__M35TOM30__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((uint32_t)(src) <<\ + 15) & 0x00038000U) +#define MDM_DFTABLE__M35TOM30__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00038000U))) +#define MDM_DFTABLE__M35TOM30__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field m41tom36 */ +/** + * @defgroup mdm_regs_core_m41tom36_field m41tom36_field + * @brief macros for field m41tom36 + * @details left shift for -41 <= baseline_pwr <= -36 + * @{ + */ +#define MDM_DFTABLE__M41TOM36__SHIFT 18 +#define MDM_DFTABLE__M41TOM36__WIDTH 3 +#define MDM_DFTABLE__M41TOM36__MASK 0x001c0000U +#define MDM_DFTABLE__M41TOM36__READ(src) \ + (((uint32_t)(src)\ + & 0x001c0000U) >> 18) +#define MDM_DFTABLE__M41TOM36__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x001c0000U) +#define MDM_DFTABLE__M41TOM36__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((uint32_t)(src) <<\ + 18) & 0x001c0000U) +#define MDM_DFTABLE__M41TOM36__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x001c0000U))) +#define MDM_DFTABLE__M41TOM36__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field belowm41 */ +/** + * @defgroup mdm_regs_core_belowm41_field belowm41_field + * @brief macros for field belowm41 + * @details left shift for baseline_pwr < -41 + * @{ + */ +#define MDM_DFTABLE__BELOWM41__SHIFT 21 +#define MDM_DFTABLE__BELOWM41__WIDTH 3 +#define MDM_DFTABLE__BELOWM41__MASK 0x00e00000U +#define MDM_DFTABLE__BELOWM41__READ(src) \ + (((uint32_t)(src)\ + & 0x00e00000U) >> 21) +#define MDM_DFTABLE__BELOWM41__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00e00000U) +#define MDM_DFTABLE__BELOWM41__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((uint32_t)(src) <<\ + 21) & 0x00e00000U) +#define MDM_DFTABLE__BELOWM41__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00e00000U))) +#define MDM_DFTABLE__BELOWM41__RESET_VALUE 0x00000002U +/** @} */ +#define MDM_DFTABLE__TYPE uint32_t +#define MDM_DFTABLE__READ 0x00ffffffU +#define MDM_DFTABLE__WRITE 0x00ffffffU +#define MDM_DFTABLE__PRESERVED 0x00000000U +#define MDM_DFTABLE__RESET_VALUE 0x00492492U + +#endif /* __MDM_DFTABLE_MACRO__ */ + +/** @} end of dftable */ + +/* macros for BlueprintGlobalNameSpace::MDM_dfstatus */ +/** + * @defgroup mdm_regs_core_dfstatus dfstatus + * @brief Saved state from previous agc operation, but with different update conditions than agcstatus. (See dfcntl->statusmode) definitions. + * @{ + */ +#ifndef __MDM_DFSTATUS_MACRO__ +#define __MDM_DFSTATUS_MACRO__ + +/* macros for field rssi */ +/** + * @defgroup mdm_regs_core_rssi_field rssi_field + * @brief macros for field rssi + * @details Received Signal Strength Indicator, absolute dBm. Signed. + * @{ + */ +#define MDM_DFSTATUS__RSSI__SHIFT 0 +#define MDM_DFSTATUS__RSSI__WIDTH 8 +#define MDM_DFSTATUS__RSSI__MASK 0x000000ffU +#define MDM_DFSTATUS__RSSI__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_DFSTATUS__RSSI__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rxgain */ +/** + * @defgroup mdm_regs_core_rxgain_field rxgain_field + * @brief macros for field rxgain + * @details Receive gain index + * @{ + */ +#define MDM_DFSTATUS__RXGAIN__SHIFT 8 +#define MDM_DFSTATUS__RXGAIN__WIDTH 7 +#define MDM_DFSTATUS__RXGAIN__MASK 0x00007f00U +#define MDM_DFSTATUS__RXGAIN__READ(src) (((uint32_t)(src) & 0x00007f00U) >> 8) +#define MDM_DFSTATUS__RXGAIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field baseline_pwr */ +/** + * @defgroup mdm_regs_core_baseline_pwr_field baseline_pwr_field + * @brief macros for field baseline_pwr + * @details Baseline power, post-RXFIR. Signed + * @{ + */ +#define MDM_DFSTATUS__BASELINE_PWR__SHIFT 15 +#define MDM_DFSTATUS__BASELINE_PWR__WIDTH 8 +#define MDM_DFSTATUS__BASELINE_PWR__MASK 0x007f8000U +#define MDM_DFSTATUS__BASELINE_PWR__READ(src) \ + (((uint32_t)(src)\ + & 0x007f8000U) >> 15) +#define MDM_DFSTATUS__BASELINE_PWR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sat_detected */ +/** + * @defgroup mdm_regs_core_sat_detected_field sat_detected_field + * @brief macros for field sat_detected + * @details Saturation triggered packet detection + * @{ + */ +#define MDM_DFSTATUS__SAT_DETECTED__SHIFT 23 +#define MDM_DFSTATUS__SAT_DETECTED__WIDTH 1 +#define MDM_DFSTATUS__SAT_DETECTED__MASK 0x00800000U +#define MDM_DFSTATUS__SAT_DETECTED__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define MDM_DFSTATUS__SAT_DETECTED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define MDM_DFSTATUS__SAT_DETECTED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define MDM_DFSTATUS__SAT_DETECTED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field peak_detected */ +/** + * @defgroup mdm_regs_core_peak_detected_field peak_detected_field + * @brief macros for field peak_detected + * @details Analog peak triggered packet detection + * @{ + */ +#define MDM_DFSTATUS__PEAK_DETECTED__SHIFT 24 +#define MDM_DFSTATUS__PEAK_DETECTED__WIDTH 1 +#define MDM_DFSTATUS__PEAK_DETECTED__MASK 0x01000000U +#define MDM_DFSTATUS__PEAK_DETECTED__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define MDM_DFSTATUS__PEAK_DETECTED__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define MDM_DFSTATUS__PEAK_DETECTED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define MDM_DFSTATUS__PEAK_DETECTED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field strong_blocker */ +/** + * @defgroup mdm_regs_core_strong_blocker_field strong_blocker_field + * @brief macros for field strong_blocker + * @details strong_blocker = (total_pwr - baseline_pwr) > cf_margin_strong_blocker_thr + * @{ + */ +#define MDM_DFSTATUS__STRONG_BLOCKER__SHIFT 25 +#define MDM_DFSTATUS__STRONG_BLOCKER__WIDTH 1 +#define MDM_DFSTATUS__STRONG_BLOCKER__MASK 0x02000000U +#define MDM_DFSTATUS__STRONG_BLOCKER__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define MDM_DFSTATUS__STRONG_BLOCKER__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define MDM_DFSTATUS__STRONG_BLOCKER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define MDM_DFSTATUS__STRONG_BLOCKER__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_DFSTATUS__TYPE uint32_t +#define MDM_DFSTATUS__READ 0x03ffffffU +#define MDM_DFSTATUS__PRESERVED 0x00000000U +#define MDM_DFSTATUS__RESET_VALUE 0x00000000U + +#endif /* __MDM_DFSTATUS_MACRO__ */ + +/** @} end of dfstatus */ + +/* macros for BlueprintGlobalNameSpace::MDM_antrx3to0 */ +/** + * @defgroup mdm_regs_core_antrx3to0 antrx3to0 + * @brief Antenna table when RX definitions. + * @{ + */ +#ifndef __MDM_ANTRX3TO0_MACRO__ +#define __MDM_ANTRX3TO0_MACRO__ + +/* macros for field table */ +/** + * @defgroup mdm_regs_core_table_field table_field + * @brief macros for field table + * @details [31:24] for ant3, [23:16] for ant2, [15:8] for ant1, [7:0] for ant0 + * @{ + */ +#define MDM_ANTRX3TO0__TABLE__SHIFT 0 +#define MDM_ANTRX3TO0__TABLE__WIDTH 32 +#define MDM_ANTRX3TO0__TABLE__MASK 0xffffffffU +#define MDM_ANTRX3TO0__TABLE__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define MDM_ANTRX3TO0__TABLE__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define MDM_ANTRX3TO0__TABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define MDM_ANTRX3TO0__TABLE__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define MDM_ANTRX3TO0__TABLE__RESET_VALUE 0x08040201U +/** @} */ +#define MDM_ANTRX3TO0__TYPE uint32_t +#define MDM_ANTRX3TO0__READ 0xffffffffU +#define MDM_ANTRX3TO0__WRITE 0xffffffffU +#define MDM_ANTRX3TO0__PRESERVED 0x00000000U +#define MDM_ANTRX3TO0__RESET_VALUE 0x08040201U + +#endif /* __MDM_ANTRX3TO0_MACRO__ */ + +/** @} end of antrx3to0 */ + +/* macros for BlueprintGlobalNameSpace::MDM_anttx3to0 */ +/** + * @defgroup mdm_regs_core_anttx3to0 anttx3to0 + * @brief Antenna table when TX definitions. + * @{ + */ +#ifndef __MDM_ANTTX3TO0_MACRO__ +#define __MDM_ANTTX3TO0_MACRO__ + +/* macros for field table */ +/** + * @defgroup mdm_regs_core_table_field table_field + * @brief macros for field table + * @details [31:24] for ant3, [23:16] for ant2, [15:8] for ant1, [7:0] for ant0 + * @{ + */ +#define MDM_ANTTX3TO0__TABLE__SHIFT 0 +#define MDM_ANTTX3TO0__TABLE__WIDTH 32 +#define MDM_ANTTX3TO0__TABLE__MASK 0xffffffffU +#define MDM_ANTTX3TO0__TABLE__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define MDM_ANTTX3TO0__TABLE__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define MDM_ANTTX3TO0__TABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define MDM_ANTTX3TO0__TABLE__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define MDM_ANTTX3TO0__TABLE__RESET_VALUE 0x08040201U +/** @} */ +#define MDM_ANTTX3TO0__TYPE uint32_t +#define MDM_ANTTX3TO0__READ 0xffffffffU +#define MDM_ANTTX3TO0__WRITE 0xffffffffU +#define MDM_ANTTX3TO0__PRESERVED 0x00000000U +#define MDM_ANTTX3TO0__RESET_VALUE 0x08040201U + +#endif /* __MDM_ANTTX3TO0_MACRO__ */ + +/** @} end of anttx3to0 */ + +/* macros for BlueprintGlobalNameSpace::MDM_antrx7to4 */ +/** + * @defgroup mdm_regs_core_antrx7to4 antrx7to4 + * @brief Antenna table when RX definitions. + * @{ + */ +#ifndef __MDM_ANTRX7TO4_MACRO__ +#define __MDM_ANTRX7TO4_MACRO__ + +/* macros for field table */ +/** + * @defgroup mdm_regs_core_table_field table_field + * @brief macros for field table + * @details [31:24] for ant7, [23:16] for ant6, [15:8] for ant5, [7:0] for ant4 + * @{ + */ +#define MDM_ANTRX7TO4__TABLE__SHIFT 0 +#define MDM_ANTRX7TO4__TABLE__WIDTH 32 +#define MDM_ANTRX7TO4__TABLE__MASK 0xffffffffU +#define MDM_ANTRX7TO4__TABLE__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define MDM_ANTRX7TO4__TABLE__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define MDM_ANTRX7TO4__TABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define MDM_ANTRX7TO4__TABLE__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define MDM_ANTRX7TO4__TABLE__RESET_VALUE 0x80402010U +/** @} */ +#define MDM_ANTRX7TO4__TYPE uint32_t +#define MDM_ANTRX7TO4__READ 0xffffffffU +#define MDM_ANTRX7TO4__WRITE 0xffffffffU +#define MDM_ANTRX7TO4__PRESERVED 0x00000000U +#define MDM_ANTRX7TO4__RESET_VALUE 0x80402010U + +#endif /* __MDM_ANTRX7TO4_MACRO__ */ + +/** @} end of antrx7to4 */ + +/* macros for BlueprintGlobalNameSpace::MDM_anttx7to4 */ +/** + * @defgroup mdm_regs_core_anttx7to4 anttx7to4 + * @brief Antenna table when TX definitions. + * @{ + */ +#ifndef __MDM_ANTTX7TO4_MACRO__ +#define __MDM_ANTTX7TO4_MACRO__ + +/* macros for field table */ +/** + * @defgroup mdm_regs_core_table_field table_field + * @brief macros for field table + * @details [31:24] for ant7, [23:16] for ant6, [15:8] for ant5, [7:0] for ant4 + * @{ + */ +#define MDM_ANTTX7TO4__TABLE__SHIFT 0 +#define MDM_ANTTX7TO4__TABLE__WIDTH 32 +#define MDM_ANTTX7TO4__TABLE__MASK 0xffffffffU +#define MDM_ANTTX7TO4__TABLE__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define MDM_ANTTX7TO4__TABLE__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define MDM_ANTTX7TO4__TABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define MDM_ANTTX7TO4__TABLE__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define MDM_ANTTX7TO4__TABLE__RESET_VALUE 0x80402010U +/** @} */ +#define MDM_ANTTX7TO4__TYPE uint32_t +#define MDM_ANTTX7TO4__READ 0xffffffffU +#define MDM_ANTTX7TO4__WRITE 0xffffffffU +#define MDM_ANTTX7TO4__PRESERVED 0x00000000U +#define MDM_ANTTX7TO4__RESET_VALUE 0x80402010U + +#endif /* __MDM_ANTTX7TO4_MACRO__ */ + +/** @} end of anttx7to4 */ + +/* macros for BlueprintGlobalNameSpace::MDM_antidle */ +/** + * @defgroup mdm_regs_core_antidle antidle + * @brief Antenna table when neither RX or TX definitions. + * @{ + */ +#ifndef __MDM_ANTIDLE_MACRO__ +#define __MDM_ANTIDLE_MACRO__ + +/* macros for field table */ +/** + * @defgroup mdm_regs_core_table_field table_field + * @brief macros for field table + * @details [7:0] for idle, independent of antenna selection + * @{ + */ +#define MDM_ANTIDLE__TABLE__SHIFT 0 +#define MDM_ANTIDLE__TABLE__WIDTH 8 +#define MDM_ANTIDLE__TABLE__MASK 0x000000ffU +#define MDM_ANTIDLE__TABLE__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_ANTIDLE__TABLE__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_ANTIDLE__TABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define MDM_ANTIDLE__TABLE__VERIFY(src) (!(((uint32_t)(src) & ~0x000000ffU))) +#define MDM_ANTIDLE__TABLE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_ANTIDLE__TYPE uint32_t +#define MDM_ANTIDLE__READ 0x000000ffU +#define MDM_ANTIDLE__WRITE 0x000000ffU +#define MDM_ANTIDLE__PRESERVED 0x00000000U +#define MDM_ANTIDLE__RESET_VALUE 0x00000000U + +#endif /* __MDM_ANTIDLE_MACRO__ */ + +/** @} end of antidle */ + +/* macros for BlueprintGlobalNameSpace::MDM_antid3to0 */ +/** + * @defgroup mdm_regs_core_antid3to0 antid3to0 + * @brief Antenna IDs to match when antmode == 2'b10 definitions. + * @{ + */ +#ifndef __MDM_ANTID3TO0_MACRO__ +#define __MDM_ANTID3TO0_MACRO__ + +/* macros for field ant0 */ +/** + * @defgroup mdm_regs_core_ant0_field ant0_field + * @brief macros for field ant0 + * @details ID for ant0 + * @{ + */ +#define MDM_ANTID3TO0__ANT0__SHIFT 0 +#define MDM_ANTID3TO0__ANT0__WIDTH 7 +#define MDM_ANTID3TO0__ANT0__MASK 0x0000007fU +#define MDM_ANTID3TO0__ANT0__READ(src) ((uint32_t)(src) & 0x0000007fU) +#define MDM_ANTID3TO0__ANT0__WRITE(src) ((uint32_t)(src) & 0x0000007fU) +#define MDM_ANTID3TO0__ANT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define MDM_ANTID3TO0__ANT0__VERIFY(src) (!(((uint32_t)(src) & ~0x0000007fU))) +#define MDM_ANTID3TO0__ANT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ant1 */ +/** + * @defgroup mdm_regs_core_ant1_field ant1_field + * @brief macros for field ant1 + * @details ID for ant1 + * @{ + */ +#define MDM_ANTID3TO0__ANT1__SHIFT 8 +#define MDM_ANTID3TO0__ANT1__WIDTH 7 +#define MDM_ANTID3TO0__ANT1__MASK 0x00007f00U +#define MDM_ANTID3TO0__ANT1__READ(src) (((uint32_t)(src) & 0x00007f00U) >> 8) +#define MDM_ANTID3TO0__ANT1__WRITE(src) (((uint32_t)(src) << 8) & 0x00007f00U) +#define MDM_ANTID3TO0__ANT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007f00U) | (((uint32_t)(src) <<\ + 8) & 0x00007f00U) +#define MDM_ANTID3TO0__ANT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00007f00U))) +#define MDM_ANTID3TO0__ANT1__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ant2 */ +/** + * @defgroup mdm_regs_core_ant2_field ant2_field + * @brief macros for field ant2 + * @details ID for ant2 + * @{ + */ +#define MDM_ANTID3TO0__ANT2__SHIFT 16 +#define MDM_ANTID3TO0__ANT2__WIDTH 7 +#define MDM_ANTID3TO0__ANT2__MASK 0x007f0000U +#define MDM_ANTID3TO0__ANT2__READ(src) (((uint32_t)(src) & 0x007f0000U) >> 16) +#define MDM_ANTID3TO0__ANT2__WRITE(src) (((uint32_t)(src) << 16) & 0x007f0000U) +#define MDM_ANTID3TO0__ANT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007f0000U) | (((uint32_t)(src) <<\ + 16) & 0x007f0000U) +#define MDM_ANTID3TO0__ANT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x007f0000U))) +#define MDM_ANTID3TO0__ANT2__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field ant3 */ +/** + * @defgroup mdm_regs_core_ant3_field ant3_field + * @brief macros for field ant3 + * @details ID for ant3 + * @{ + */ +#define MDM_ANTID3TO0__ANT3__SHIFT 24 +#define MDM_ANTID3TO0__ANT3__WIDTH 7 +#define MDM_ANTID3TO0__ANT3__MASK 0x7f000000U +#define MDM_ANTID3TO0__ANT3__READ(src) (((uint32_t)(src) & 0x7f000000U) >> 24) +#define MDM_ANTID3TO0__ANT3__WRITE(src) (((uint32_t)(src) << 24) & 0x7f000000U) +#define MDM_ANTID3TO0__ANT3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((uint32_t)(src) <<\ + 24) & 0x7f000000U) +#define MDM_ANTID3TO0__ANT3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x7f000000U))) +#define MDM_ANTID3TO0__ANT3__RESET_VALUE 0x00000003U +/** @} */ +#define MDM_ANTID3TO0__TYPE uint32_t +#define MDM_ANTID3TO0__READ 0x7f7f7f7fU +#define MDM_ANTID3TO0__WRITE 0x7f7f7f7fU +#define MDM_ANTID3TO0__PRESERVED 0x00000000U +#define MDM_ANTID3TO0__RESET_VALUE 0x03020100U + +#endif /* __MDM_ANTID3TO0_MACRO__ */ + +/** @} end of antid3to0 */ + +/* macros for BlueprintGlobalNameSpace::MDM_antid7to4 */ +/** + * @defgroup mdm_regs_core_antid7to4 antid7to4 + * @brief Antenna IDs to match when antmode == 2'b10 definitions. + * @{ + */ +#ifndef __MDM_ANTID7TO4_MACRO__ +#define __MDM_ANTID7TO4_MACRO__ + +/* macros for field ant4 */ +/** + * @defgroup mdm_regs_core_ant4_field ant4_field + * @brief macros for field ant4 + * @details ID for ant4 + * @{ + */ +#define MDM_ANTID7TO4__ANT4__SHIFT 0 +#define MDM_ANTID7TO4__ANT4__WIDTH 7 +#define MDM_ANTID7TO4__ANT4__MASK 0x0000007fU +#define MDM_ANTID7TO4__ANT4__READ(src) ((uint32_t)(src) & 0x0000007fU) +#define MDM_ANTID7TO4__ANT4__WRITE(src) ((uint32_t)(src) & 0x0000007fU) +#define MDM_ANTID7TO4__ANT4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define MDM_ANTID7TO4__ANT4__VERIFY(src) (!(((uint32_t)(src) & ~0x0000007fU))) +#define MDM_ANTID7TO4__ANT4__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field ant5 */ +/** + * @defgroup mdm_regs_core_ant5_field ant5_field + * @brief macros for field ant5 + * @details ID for ant5 + * @{ + */ +#define MDM_ANTID7TO4__ANT5__SHIFT 8 +#define MDM_ANTID7TO4__ANT5__WIDTH 7 +#define MDM_ANTID7TO4__ANT5__MASK 0x00007f00U +#define MDM_ANTID7TO4__ANT5__READ(src) (((uint32_t)(src) & 0x00007f00U) >> 8) +#define MDM_ANTID7TO4__ANT5__WRITE(src) (((uint32_t)(src) << 8) & 0x00007f00U) +#define MDM_ANTID7TO4__ANT5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007f00U) | (((uint32_t)(src) <<\ + 8) & 0x00007f00U) +#define MDM_ANTID7TO4__ANT5__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00007f00U))) +#define MDM_ANTID7TO4__ANT5__RESET_VALUE 0x00000005U +/** @} */ + +/* macros for field ant6 */ +/** + * @defgroup mdm_regs_core_ant6_field ant6_field + * @brief macros for field ant6 + * @details ID for ant6 + * @{ + */ +#define MDM_ANTID7TO4__ANT6__SHIFT 16 +#define MDM_ANTID7TO4__ANT6__WIDTH 7 +#define MDM_ANTID7TO4__ANT6__MASK 0x007f0000U +#define MDM_ANTID7TO4__ANT6__READ(src) (((uint32_t)(src) & 0x007f0000U) >> 16) +#define MDM_ANTID7TO4__ANT6__WRITE(src) (((uint32_t)(src) << 16) & 0x007f0000U) +#define MDM_ANTID7TO4__ANT6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007f0000U) | (((uint32_t)(src) <<\ + 16) & 0x007f0000U) +#define MDM_ANTID7TO4__ANT6__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x007f0000U))) +#define MDM_ANTID7TO4__ANT6__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field ant7 */ +/** + * @defgroup mdm_regs_core_ant7_field ant7_field + * @brief macros for field ant7 + * @details ID for ant7 + * @{ + */ +#define MDM_ANTID7TO4__ANT7__SHIFT 24 +#define MDM_ANTID7TO4__ANT7__WIDTH 7 +#define MDM_ANTID7TO4__ANT7__MASK 0x7f000000U +#define MDM_ANTID7TO4__ANT7__READ(src) (((uint32_t)(src) & 0x7f000000U) >> 24) +#define MDM_ANTID7TO4__ANT7__WRITE(src) (((uint32_t)(src) << 24) & 0x7f000000U) +#define MDM_ANTID7TO4__ANT7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((uint32_t)(src) <<\ + 24) & 0x7f000000U) +#define MDM_ANTID7TO4__ANT7__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x7f000000U))) +#define MDM_ANTID7TO4__ANT7__RESET_VALUE 0x00000007U +/** @} */ +#define MDM_ANTID7TO4__TYPE uint32_t +#define MDM_ANTID7TO4__READ 0x7f7f7f7fU +#define MDM_ANTID7TO4__WRITE 0x7f7f7f7fU +#define MDM_ANTID7TO4__PRESERVED 0x00000000U +#define MDM_ANTID7TO4__RESET_VALUE 0x07060504U + +#endif /* __MDM_ANTID7TO4_MACRO__ */ + +/** @} end of antid7to4 */ + +/* macros for BlueprintGlobalNameSpace::MDM_wht_ctrl */ +/** + * @defgroup mdm_regs_core_wht_ctrl wht_ctrl + * @brief Whitening control definitions. + * @{ + */ +#ifndef __MDM_WHT_CTRL_MACRO__ +#define __MDM_WHT_CTRL_MACRO__ + +/* macros for field init_en */ +/** + * @defgroup mdm_regs_core_init_en_field init_en_field + * @brief macros for field init_en + * @details enable overriding of the whitening initialization seed + * @{ + */ +#define MDM_WHT_CTRL__INIT_EN__SHIFT 0 +#define MDM_WHT_CTRL__INIT_EN__WIDTH 1 +#define MDM_WHT_CTRL__INIT_EN__MASK 0x00000001U +#define MDM_WHT_CTRL__INIT_EN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_WHT_CTRL__INIT_EN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_WHT_CTRL__INIT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define MDM_WHT_CTRL__INIT_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define MDM_WHT_CTRL__INIT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_WHT_CTRL__INIT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_WHT_CTRL__INIT_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field init_sd */ +/** + * @defgroup mdm_regs_core_init_sd_field init_sd_field + * @brief macros for field init_sd + * @details initialization seed + * @{ + */ +#define MDM_WHT_CTRL__INIT_SD__SHIFT 1 +#define MDM_WHT_CTRL__INIT_SD__WIDTH 7 +#define MDM_WHT_CTRL__INIT_SD__MASK 0x000000feU +#define MDM_WHT_CTRL__INIT_SD__READ(src) (((uint32_t)(src) & 0x000000feU) >> 1) +#define MDM_WHT_CTRL__INIT_SD__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000000feU) +#define MDM_WHT_CTRL__INIT_SD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000feU) | (((uint32_t)(src) <<\ + 1) & 0x000000feU) +#define MDM_WHT_CTRL__INIT_SD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000000feU))) +#define MDM_WHT_CTRL__INIT_SD__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_WHT_CTRL__TYPE uint32_t +#define MDM_WHT_CTRL__READ 0x000000ffU +#define MDM_WHT_CTRL__WRITE 0x000000ffU +#define MDM_WHT_CTRL__PRESERVED 0x00000000U +#define MDM_WHT_CTRL__RESET_VALUE 0x00000000U + +#endif /* __MDM_WHT_CTRL_MACRO__ */ + +/** @} end of wht_ctrl */ + +/* macros for BlueprintGlobalNameSpace::MDM_dccalresults */ +/** + * @defgroup mdm_regs_core_dccalresults dccalresults + * @brief DC offset calibration results for TIA definitions. + * @{ + */ +#ifndef __MDM_DCCALRESULTS_MACRO__ +#define __MDM_DCCALRESULTS_MACRO__ + +/* macros for field q_off */ +/** + * @defgroup mdm_regs_core_q_off_field q_off_field + * @brief macros for field q_off + * @details calculated TIA Q offset + * @{ + */ +#define MDM_DCCALRESULTS__Q_OFF__SHIFT 0 +#define MDM_DCCALRESULTS__Q_OFF__WIDTH 6 +#define MDM_DCCALRESULTS__Q_OFF__MASK 0x0000003fU +#define MDM_DCCALRESULTS__Q_OFF__READ(src) ((uint32_t)(src) & 0x0000003fU) +#define MDM_DCCALRESULTS__Q_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field i_off */ +/** + * @defgroup mdm_regs_core_i_off_field i_off_field + * @brief macros for field i_off + * @details calculated TIA I offset + * @{ + */ +#define MDM_DCCALRESULTS__I_OFF__SHIFT 8 +#define MDM_DCCALRESULTS__I_OFF__WIDTH 6 +#define MDM_DCCALRESULTS__I_OFF__MASK 0x00003f00U +#define MDM_DCCALRESULTS__I_OFF__READ(src) \ + (((uint32_t)(src)\ + & 0x00003f00U) >> 8) +#define MDM_DCCALRESULTS__I_OFF__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_DCCALRESULTS__TYPE uint32_t +#define MDM_DCCALRESULTS__READ 0x00003f3fU +#define MDM_DCCALRESULTS__PRESERVED 0x00000000U +#define MDM_DCCALRESULTS__RESET_VALUE 0x00000000U + +#endif /* __MDM_DCCALRESULTS_MACRO__ */ + +/** @} end of dccalresults */ + +/* macros for BlueprintGlobalNameSpace::MDM_dccalresults2 */ +/** + * @defgroup mdm_regs_core_dccalresults2 dccalresults2 + * @brief DC offset calibration results, averages for TIA definitions. + * @{ + */ +#ifndef __MDM_DCCALRESULTS2_MACRO__ +#define __MDM_DCCALRESULTS2_MACRO__ + +/* macros for field done */ +/** + * @defgroup mdm_regs_core_done_field done_field + * @brief macros for field done + * @details software triiger DC calibration done + * @{ + */ +#define MDM_DCCALRESULTS2__DONE__SHIFT 0 +#define MDM_DCCALRESULTS2__DONE__WIDTH 1 +#define MDM_DCCALRESULTS2__DONE__MASK 0x00000001U +#define MDM_DCCALRESULTS2__DONE__READ(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_DCCALRESULTS2__DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_DCCALRESULTS2__DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_DCCALRESULTS2__DONE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field avg_q */ +/** + * @defgroup mdm_regs_core_avg_q_field avg_q_field + * @brief macros for field avg_q + * @details calculated average of ADC Q samples + * @{ + */ +#define MDM_DCCALRESULTS2__AVG_Q__SHIFT 8 +#define MDM_DCCALRESULTS2__AVG_Q__WIDTH 8 +#define MDM_DCCALRESULTS2__AVG_Q__MASK 0x0000ff00U +#define MDM_DCCALRESULTS2__AVG_Q__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_DCCALRESULTS2__AVG_Q__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field avg_i */ +/** + * @defgroup mdm_regs_core_avg_i_field avg_i_field + * @brief macros for field avg_i + * @details calculated average of ADC I samples + * @{ + */ +#define MDM_DCCALRESULTS2__AVG_I__SHIFT 16 +#define MDM_DCCALRESULTS2__AVG_I__WIDTH 8 +#define MDM_DCCALRESULTS2__AVG_I__MASK 0x00ff0000U +#define MDM_DCCALRESULTS2__AVG_I__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MDM_DCCALRESULTS2__AVG_I__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_DCCALRESULTS2__TYPE uint32_t +#define MDM_DCCALRESULTS2__READ 0x00ffff01U +#define MDM_DCCALRESULTS2__PRESERVED 0x00000000U +#define MDM_DCCALRESULTS2__RESET_VALUE 0x00000000U + +#endif /* __MDM_DCCALRESULTS2_MACRO__ */ + +/** @} end of dccalresults2 */ + +/* macros for BlueprintGlobalNameSpace::MDM_tia_retent_dccalresults */ +/** + * @defgroup mdm_regs_core_tia_retent_dccalresults tia_retent_dccalresults + * @brief DC offset calibration results for TIA for paris definitions. + * @{ + */ +#ifndef __MDM_TIA_RETENT_DCCALRESULTS_MACRO__ +#define __MDM_TIA_RETENT_DCCALRESULTS_MACRO__ + +/* macros for field q_off */ +/** + * @defgroup mdm_regs_core_q_off_field q_off_field + * @brief macros for field q_off + * @details calculated TIA Q offset + * @{ + */ +#define MDM_TIA_RETENT_DCCALRESULTS__Q_OFF__SHIFT 0 +#define MDM_TIA_RETENT_DCCALRESULTS__Q_OFF__WIDTH 8 +#define MDM_TIA_RETENT_DCCALRESULTS__Q_OFF__MASK 0x000000ffU +#define MDM_TIA_RETENT_DCCALRESULTS__Q_OFF__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_TIA_RETENT_DCCALRESULTS__Q_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field i_off */ +/** + * @defgroup mdm_regs_core_i_off_field i_off_field + * @brief macros for field i_off + * @details calculated TIA I offset + * @{ + */ +#define MDM_TIA_RETENT_DCCALRESULTS__I_OFF__SHIFT 8 +#define MDM_TIA_RETENT_DCCALRESULTS__I_OFF__WIDTH 8 +#define MDM_TIA_RETENT_DCCALRESULTS__I_OFF__MASK 0x0000ff00U +#define MDM_TIA_RETENT_DCCALRESULTS__I_OFF__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_TIA_RETENT_DCCALRESULTS__I_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bb2gain */ +/** + * @defgroup mdm_regs_core_bb2gain_field bb2gain_field + * @brief macros for field bb2gain + * @details bb2gain value used in TIA cal + * @{ + */ +#define MDM_TIA_RETENT_DCCALRESULTS__BB2GAIN__SHIFT 16 +#define MDM_TIA_RETENT_DCCALRESULTS__BB2GAIN__WIDTH 5 +#define MDM_TIA_RETENT_DCCALRESULTS__BB2GAIN__MASK 0x001f0000U +#define MDM_TIA_RETENT_DCCALRESULTS__BB2GAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x001f0000U) >> 16) +#define MDM_TIA_RETENT_DCCALRESULTS__BB2GAIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field done */ +/** + * @defgroup mdm_regs_core_done_field done_field + * @brief macros for field done + * @details hardware/software triiger DC calibration done + * @{ + */ +#define MDM_TIA_RETENT_DCCALRESULTS__DONE__SHIFT 31 +#define MDM_TIA_RETENT_DCCALRESULTS__DONE__WIDTH 1 +#define MDM_TIA_RETENT_DCCALRESULTS__DONE__MASK 0x80000000U +#define MDM_TIA_RETENT_DCCALRESULTS__DONE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_TIA_RETENT_DCCALRESULTS__DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_TIA_RETENT_DCCALRESULTS__DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_TIA_RETENT_DCCALRESULTS__DONE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_TIA_RETENT_DCCALRESULTS__TYPE uint32_t +#define MDM_TIA_RETENT_DCCALRESULTS__READ 0x801fffffU +#define MDM_TIA_RETENT_DCCALRESULTS__PRESERVED 0x00000000U +#define MDM_TIA_RETENT_DCCALRESULTS__RESET_VALUE 0x00000000U + +#endif /* __MDM_TIA_RETENT_DCCALRESULTS_MACRO__ */ + +/** @} end of tia_retent_dccalresults */ + +/* macros for BlueprintGlobalNameSpace::MDM_tia_dccalresults2 */ +/** + * @defgroup mdm_regs_core_tia_dccalresults2 tia_dccalresults2 + * @brief DC offset calibration results, averages for TIA for paris definitions. + * @{ + */ +#ifndef __MDM_TIA_DCCALRESULTS2_MACRO__ +#define __MDM_TIA_DCCALRESULTS2_MACRO__ + +/* macros for field avg_q */ +/** + * @defgroup mdm_regs_core_avg_q_field avg_q_field + * @brief macros for field avg_q + * @details calculated average of ADC Q samples + * @{ + */ +#define MDM_TIA_DCCALRESULTS2__AVG_Q__SHIFT 0 +#define MDM_TIA_DCCALRESULTS2__AVG_Q__WIDTH 8 +#define MDM_TIA_DCCALRESULTS2__AVG_Q__MASK 0x000000ffU +#define MDM_TIA_DCCALRESULTS2__AVG_Q__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_TIA_DCCALRESULTS2__AVG_Q__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field avg_i */ +/** + * @defgroup mdm_regs_core_avg_i_field avg_i_field + * @brief macros for field avg_i + * @details calculated average of ADC I samples + * @{ + */ +#define MDM_TIA_DCCALRESULTS2__AVG_I__SHIFT 8 +#define MDM_TIA_DCCALRESULTS2__AVG_I__WIDTH 8 +#define MDM_TIA_DCCALRESULTS2__AVG_I__MASK 0x0000ff00U +#define MDM_TIA_DCCALRESULTS2__AVG_I__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_TIA_DCCALRESULTS2__AVG_I__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field done */ +/** + * @defgroup mdm_regs_core_done_field done_field + * @brief macros for field done + * @details software triiger DC calibration done + * @{ + */ +#define MDM_TIA_DCCALRESULTS2__DONE__SHIFT 31 +#define MDM_TIA_DCCALRESULTS2__DONE__WIDTH 1 +#define MDM_TIA_DCCALRESULTS2__DONE__MASK 0x80000000U +#define MDM_TIA_DCCALRESULTS2__DONE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_TIA_DCCALRESULTS2__DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_TIA_DCCALRESULTS2__DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_TIA_DCCALRESULTS2__DONE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_TIA_DCCALRESULTS2__TYPE uint32_t +#define MDM_TIA_DCCALRESULTS2__READ 0x8000ffffU +#define MDM_TIA_DCCALRESULTS2__PRESERVED 0x00000000U +#define MDM_TIA_DCCALRESULTS2__RESET_VALUE 0x00000000U + +#endif /* __MDM_TIA_DCCALRESULTS2_MACRO__ */ + +/** @} end of tia_dccalresults2 */ + +/* macros for BlueprintGlobalNameSpace::MDM_tia_dccalresults3 */ +/** + * @defgroup mdm_regs_core_tia_dccalresults3 tia_dccalresults3 + * @brief Current offset values being applied definitions. + * @{ + */ +#ifndef __MDM_TIA_DCCALRESULTS3_MACRO__ +#define __MDM_TIA_DCCALRESULTS3_MACRO__ + +/* macros for field bb1q_dcoc */ +/** + * @defgroup mdm_regs_core_bb1q_dcoc_field bb1q_dcoc_field + * @brief macros for field bb1q_dcoc + * @details bb1q_dooc Q driven by mdm + * @{ + */ +#define MDM_TIA_DCCALRESULTS3__BB1Q_DCOC__SHIFT 0 +#define MDM_TIA_DCCALRESULTS3__BB1Q_DCOC__WIDTH 8 +#define MDM_TIA_DCCALRESULTS3__BB1Q_DCOC__MASK 0x000000ffU +#define MDM_TIA_DCCALRESULTS3__BB1Q_DCOC__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_TIA_DCCALRESULTS3__BB1Q_DCOC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bb1i_dcoc */ +/** + * @defgroup mdm_regs_core_bb1i_dcoc_field bb1i_dcoc_field + * @brief macros for field bb1i_dcoc + * @details bb1i_dcoc I driven by mdm + * @{ + */ +#define MDM_TIA_DCCALRESULTS3__BB1I_DCOC__SHIFT 8 +#define MDM_TIA_DCCALRESULTS3__BB1I_DCOC__WIDTH 8 +#define MDM_TIA_DCCALRESULTS3__BB1I_DCOC__MASK 0x0000ff00U +#define MDM_TIA_DCCALRESULTS3__BB1I_DCOC__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_TIA_DCCALRESULTS3__BB1I_DCOC__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_TIA_DCCALRESULTS3__TYPE uint32_t +#define MDM_TIA_DCCALRESULTS3__READ 0x0000ffffU +#define MDM_TIA_DCCALRESULTS3__PRESERVED 0x00000000U +#define MDM_TIA_DCCALRESULTS3__RESET_VALUE 0x00000000U + +#endif /* __MDM_TIA_DCCALRESULTS3_MACRO__ */ + +/** @} end of tia_dccalresults3 */ + +/* macros for BlueprintGlobalNameSpace::MDM_tia_lp_retent_dccalresults */ +/** + * @defgroup mdm_regs_core_tia_lp_retent_dccalresults tia_lp_retent_dccalresults + * @brief DC offset calibration results for TIA for low power mode for paris definitions. + * @{ + */ +#ifndef __MDM_TIA_LP_RETENT_DCCALRESULTS_MACRO__ +#define __MDM_TIA_LP_RETENT_DCCALRESULTS_MACRO__ + +/* macros for field q_off */ +/** + * @defgroup mdm_regs_core_q_off_field q_off_field + * @brief macros for field q_off + * @details calculated TIA Q offset + * @{ + */ +#define MDM_TIA_LP_RETENT_DCCALRESULTS__Q_OFF__SHIFT 0 +#define MDM_TIA_LP_RETENT_DCCALRESULTS__Q_OFF__WIDTH 8 +#define MDM_TIA_LP_RETENT_DCCALRESULTS__Q_OFF__MASK 0x000000ffU +#define MDM_TIA_LP_RETENT_DCCALRESULTS__Q_OFF__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_TIA_LP_RETENT_DCCALRESULTS__Q_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field i_off */ +/** + * @defgroup mdm_regs_core_i_off_field i_off_field + * @brief macros for field i_off + * @details calculated TIA I offset + * @{ + */ +#define MDM_TIA_LP_RETENT_DCCALRESULTS__I_OFF__SHIFT 8 +#define MDM_TIA_LP_RETENT_DCCALRESULTS__I_OFF__WIDTH 8 +#define MDM_TIA_LP_RETENT_DCCALRESULTS__I_OFF__MASK 0x0000ff00U +#define MDM_TIA_LP_RETENT_DCCALRESULTS__I_OFF__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_TIA_LP_RETENT_DCCALRESULTS__I_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bb2gain */ +/** + * @defgroup mdm_regs_core_bb2gain_field bb2gain_field + * @brief macros for field bb2gain + * @details bb2gain value used in TIA cal + * @{ + */ +#define MDM_TIA_LP_RETENT_DCCALRESULTS__BB2GAIN__SHIFT 16 +#define MDM_TIA_LP_RETENT_DCCALRESULTS__BB2GAIN__WIDTH 5 +#define MDM_TIA_LP_RETENT_DCCALRESULTS__BB2GAIN__MASK 0x001f0000U +#define MDM_TIA_LP_RETENT_DCCALRESULTS__BB2GAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x001f0000U) >> 16) +#define MDM_TIA_LP_RETENT_DCCALRESULTS__BB2GAIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field done */ +/** + * @defgroup mdm_regs_core_done_field done_field + * @brief macros for field done + * @details hardware/software triiger DC calibration done + * @{ + */ +#define MDM_TIA_LP_RETENT_DCCALRESULTS__DONE__SHIFT 31 +#define MDM_TIA_LP_RETENT_DCCALRESULTS__DONE__WIDTH 1 +#define MDM_TIA_LP_RETENT_DCCALRESULTS__DONE__MASK 0x80000000U +#define MDM_TIA_LP_RETENT_DCCALRESULTS__DONE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_TIA_LP_RETENT_DCCALRESULTS__DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_TIA_LP_RETENT_DCCALRESULTS__DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_TIA_LP_RETENT_DCCALRESULTS__DONE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_TIA_LP_RETENT_DCCALRESULTS__TYPE uint32_t +#define MDM_TIA_LP_RETENT_DCCALRESULTS__READ 0x801fffffU +#define MDM_TIA_LP_RETENT_DCCALRESULTS__PRESERVED 0x00000000U +#define MDM_TIA_LP_RETENT_DCCALRESULTS__RESET_VALUE 0x00000000U + +#endif /* __MDM_TIA_LP_RETENT_DCCALRESULTS_MACRO__ */ + +/** @} end of tia_lp_retent_dccalresults */ + +/* macros for BlueprintGlobalNameSpace::MDM_tia_lp_dccalresults2 */ +/** + * @defgroup mdm_regs_core_tia_lp_dccalresults2 tia_lp_dccalresults2 + * @brief DC offset calibration results, averages for TIA for low power mode for paris definitions. + * @{ + */ +#ifndef __MDM_TIA_LP_DCCALRESULTS2_MACRO__ +#define __MDM_TIA_LP_DCCALRESULTS2_MACRO__ + +/* macros for field avg_q */ +/** + * @defgroup mdm_regs_core_avg_q_field avg_q_field + * @brief macros for field avg_q + * @details calculated average of ADC Q samples + * @{ + */ +#define MDM_TIA_LP_DCCALRESULTS2__AVG_Q__SHIFT 0 +#define MDM_TIA_LP_DCCALRESULTS2__AVG_Q__WIDTH 8 +#define MDM_TIA_LP_DCCALRESULTS2__AVG_Q__MASK 0x000000ffU +#define MDM_TIA_LP_DCCALRESULTS2__AVG_Q__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_TIA_LP_DCCALRESULTS2__AVG_Q__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field avg_i */ +/** + * @defgroup mdm_regs_core_avg_i_field avg_i_field + * @brief macros for field avg_i + * @details calculated average of ADC I samples + * @{ + */ +#define MDM_TIA_LP_DCCALRESULTS2__AVG_I__SHIFT 8 +#define MDM_TIA_LP_DCCALRESULTS2__AVG_I__WIDTH 8 +#define MDM_TIA_LP_DCCALRESULTS2__AVG_I__MASK 0x0000ff00U +#define MDM_TIA_LP_DCCALRESULTS2__AVG_I__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_TIA_LP_DCCALRESULTS2__AVG_I__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field done */ +/** + * @defgroup mdm_regs_core_done_field done_field + * @brief macros for field done + * @details software triiger DC calibration done + * @{ + */ +#define MDM_TIA_LP_DCCALRESULTS2__DONE__SHIFT 31 +#define MDM_TIA_LP_DCCALRESULTS2__DONE__WIDTH 1 +#define MDM_TIA_LP_DCCALRESULTS2__DONE__MASK 0x80000000U +#define MDM_TIA_LP_DCCALRESULTS2__DONE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_TIA_LP_DCCALRESULTS2__DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_TIA_LP_DCCALRESULTS2__DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_TIA_LP_DCCALRESULTS2__DONE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_TIA_LP_DCCALRESULTS2__TYPE uint32_t +#define MDM_TIA_LP_DCCALRESULTS2__READ 0x8000ffffU +#define MDM_TIA_LP_DCCALRESULTS2__PRESERVED 0x00000000U +#define MDM_TIA_LP_DCCALRESULTS2__RESET_VALUE 0x00000000U + +#endif /* __MDM_TIA_LP_DCCALRESULTS2_MACRO__ */ + +/** @} end of tia_lp_dccalresults2 */ + +/* macros for BlueprintGlobalNameSpace::MDM_pga_retent_dccalresults */ +/** + * @defgroup mdm_regs_core_pga_retent_dccalresults pga_retent_dccalresults + * @brief DC offset calibration results for PGA definitions. + * @{ + */ +#ifndef __MDM_PGA_RETENT_DCCALRESULTS_MACRO__ +#define __MDM_PGA_RETENT_DCCALRESULTS_MACRO__ + +/* macros for field q_off */ +/** + * @defgroup mdm_regs_core_q_off_field q_off_field + * @brief macros for field q_off + * @details calculated PGA Q offset + * @{ + */ +#define MDM_PGA_RETENT_DCCALRESULTS__Q_OFF__SHIFT 0 +#define MDM_PGA_RETENT_DCCALRESULTS__Q_OFF__WIDTH 5 +#define MDM_PGA_RETENT_DCCALRESULTS__Q_OFF__MASK 0x0000001fU +#define MDM_PGA_RETENT_DCCALRESULTS__Q_OFF__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define MDM_PGA_RETENT_DCCALRESULTS__Q_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field i_off */ +/** + * @defgroup mdm_regs_core_i_off_field i_off_field + * @brief macros for field i_off + * @details calculated PGA I offset + * @{ + */ +#define MDM_PGA_RETENT_DCCALRESULTS__I_OFF__SHIFT 8 +#define MDM_PGA_RETENT_DCCALRESULTS__I_OFF__WIDTH 5 +#define MDM_PGA_RETENT_DCCALRESULTS__I_OFF__MASK 0x00001f00U +#define MDM_PGA_RETENT_DCCALRESULTS__I_OFF__READ(src) \ + (((uint32_t)(src)\ + & 0x00001f00U) >> 8) +#define MDM_PGA_RETENT_DCCALRESULTS__I_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bb2gain */ +/** + * @defgroup mdm_regs_core_bb2gain_field bb2gain_field + * @brief macros for field bb2gain + * @details bb2gain value used in PGA cal + * @{ + */ +#define MDM_PGA_RETENT_DCCALRESULTS__BB2GAIN__SHIFT 16 +#define MDM_PGA_RETENT_DCCALRESULTS__BB2GAIN__WIDTH 5 +#define MDM_PGA_RETENT_DCCALRESULTS__BB2GAIN__MASK 0x001f0000U +#define MDM_PGA_RETENT_DCCALRESULTS__BB2GAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x001f0000U) >> 16) +#define MDM_PGA_RETENT_DCCALRESULTS__BB2GAIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field done */ +/** + * @defgroup mdm_regs_core_done_field done_field + * @brief macros for field done + * @details hardware/software triiger DC calibration done + * @{ + */ +#define MDM_PGA_RETENT_DCCALRESULTS__DONE__SHIFT 31 +#define MDM_PGA_RETENT_DCCALRESULTS__DONE__WIDTH 1 +#define MDM_PGA_RETENT_DCCALRESULTS__DONE__MASK 0x80000000U +#define MDM_PGA_RETENT_DCCALRESULTS__DONE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_PGA_RETENT_DCCALRESULTS__DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_PGA_RETENT_DCCALRESULTS__DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_PGA_RETENT_DCCALRESULTS__DONE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_PGA_RETENT_DCCALRESULTS__TYPE uint32_t +#define MDM_PGA_RETENT_DCCALRESULTS__READ 0x801f1f1fU +#define MDM_PGA_RETENT_DCCALRESULTS__PRESERVED 0x00000000U +#define MDM_PGA_RETENT_DCCALRESULTS__RESET_VALUE 0x00000000U + +#endif /* __MDM_PGA_RETENT_DCCALRESULTS_MACRO__ */ + +/** @} end of pga_retent_dccalresults */ + +/* macros for BlueprintGlobalNameSpace::MDM_pga_dccalresults2 */ +/** + * @defgroup mdm_regs_core_pga_dccalresults2 pga_dccalresults2 + * @brief DC offset calibration results, averages for PGA definitions. + * @{ + */ +#ifndef __MDM_PGA_DCCALRESULTS2_MACRO__ +#define __MDM_PGA_DCCALRESULTS2_MACRO__ + +/* macros for field avg_q */ +/** + * @defgroup mdm_regs_core_avg_q_field avg_q_field + * @brief macros for field avg_q + * @details calculated average of ADC Q samples + * @{ + */ +#define MDM_PGA_DCCALRESULTS2__AVG_Q__SHIFT 0 +#define MDM_PGA_DCCALRESULTS2__AVG_Q__WIDTH 8 +#define MDM_PGA_DCCALRESULTS2__AVG_Q__MASK 0x000000ffU +#define MDM_PGA_DCCALRESULTS2__AVG_Q__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_PGA_DCCALRESULTS2__AVG_Q__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field avg_i */ +/** + * @defgroup mdm_regs_core_avg_i_field avg_i_field + * @brief macros for field avg_i + * @details calculated average of ADC I samples + * @{ + */ +#define MDM_PGA_DCCALRESULTS2__AVG_I__SHIFT 8 +#define MDM_PGA_DCCALRESULTS2__AVG_I__WIDTH 8 +#define MDM_PGA_DCCALRESULTS2__AVG_I__MASK 0x0000ff00U +#define MDM_PGA_DCCALRESULTS2__AVG_I__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_PGA_DCCALRESULTS2__AVG_I__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field done */ +/** + * @defgroup mdm_regs_core_done_field done_field + * @brief macros for field done + * @details software triiger DC calibration done + * @{ + */ +#define MDM_PGA_DCCALRESULTS2__DONE__SHIFT 31 +#define MDM_PGA_DCCALRESULTS2__DONE__WIDTH 1 +#define MDM_PGA_DCCALRESULTS2__DONE__MASK 0x80000000U +#define MDM_PGA_DCCALRESULTS2__DONE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_PGA_DCCALRESULTS2__DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_PGA_DCCALRESULTS2__DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_PGA_DCCALRESULTS2__DONE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_PGA_DCCALRESULTS2__TYPE uint32_t +#define MDM_PGA_DCCALRESULTS2__READ 0x8000ffffU +#define MDM_PGA_DCCALRESULTS2__PRESERVED 0x00000000U +#define MDM_PGA_DCCALRESULTS2__RESET_VALUE 0x00000000U + +#endif /* __MDM_PGA_DCCALRESULTS2_MACRO__ */ + +/** @} end of pga_dccalresults2 */ + +/* macros for BlueprintGlobalNameSpace::MDM_pga_dccalresults3 */ +/** + * @defgroup mdm_regs_core_pga_dccalresults3 pga_dccalresults3 + * @brief Current offset values being applied definitions. + * @{ + */ +#ifndef __MDM_PGA_DCCALRESULTS3_MACRO__ +#define __MDM_PGA_DCCALRESULTS3_MACRO__ + +/* macros for field bb2q_dcoc */ +/** + * @defgroup mdm_regs_core_bb2q_dcoc_field bb2q_dcoc_field + * @brief macros for field bb2q_dcoc + * @details bb2q_dooc Q driven by mdm + * @{ + */ +#define MDM_PGA_DCCALRESULTS3__BB2Q_DCOC__SHIFT 0 +#define MDM_PGA_DCCALRESULTS3__BB2Q_DCOC__WIDTH 5 +#define MDM_PGA_DCCALRESULTS3__BB2Q_DCOC__MASK 0x0000001fU +#define MDM_PGA_DCCALRESULTS3__BB2Q_DCOC__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define MDM_PGA_DCCALRESULTS3__BB2Q_DCOC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bb2i_dcoc */ +/** + * @defgroup mdm_regs_core_bb2i_dcoc_field bb2i_dcoc_field + * @brief macros for field bb2i_dcoc + * @details bb2i_dcoc I driven by mdm + * @{ + */ +#define MDM_PGA_DCCALRESULTS3__BB2I_DCOC__SHIFT 8 +#define MDM_PGA_DCCALRESULTS3__BB2I_DCOC__WIDTH 5 +#define MDM_PGA_DCCALRESULTS3__BB2I_DCOC__MASK 0x00001f00U +#define MDM_PGA_DCCALRESULTS3__BB2I_DCOC__READ(src) \ + (((uint32_t)(src)\ + & 0x00001f00U) >> 8) +#define MDM_PGA_DCCALRESULTS3__BB2I_DCOC__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_PGA_DCCALRESULTS3__TYPE uint32_t +#define MDM_PGA_DCCALRESULTS3__READ 0x00001f1fU +#define MDM_PGA_DCCALRESULTS3__PRESERVED 0x00000000U +#define MDM_PGA_DCCALRESULTS3__RESET_VALUE 0x00000000U + +#endif /* __MDM_PGA_DCCALRESULTS3_MACRO__ */ + +/** @} end of pga_dccalresults3 */ + +/* macros for BlueprintGlobalNameSpace::MDM_pga_lp_retent_dccalresults */ +/** + * @defgroup mdm_regs_core_pga_lp_retent_dccalresults pga_lp_retent_dccalresults + * @brief DC offset calibration results for low power mode for PGA definitions. + * @{ + */ +#ifndef __MDM_PGA_LP_RETENT_DCCALRESULTS_MACRO__ +#define __MDM_PGA_LP_RETENT_DCCALRESULTS_MACRO__ + +/* macros for field q_off */ +/** + * @defgroup mdm_regs_core_q_off_field q_off_field + * @brief macros for field q_off + * @details calculated PGA Q offset + * @{ + */ +#define MDM_PGA_LP_RETENT_DCCALRESULTS__Q_OFF__SHIFT 0 +#define MDM_PGA_LP_RETENT_DCCALRESULTS__Q_OFF__WIDTH 5 +#define MDM_PGA_LP_RETENT_DCCALRESULTS__Q_OFF__MASK 0x0000001fU +#define MDM_PGA_LP_RETENT_DCCALRESULTS__Q_OFF__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define MDM_PGA_LP_RETENT_DCCALRESULTS__Q_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field i_off */ +/** + * @defgroup mdm_regs_core_i_off_field i_off_field + * @brief macros for field i_off + * @details calculated PGA I offset + * @{ + */ +#define MDM_PGA_LP_RETENT_DCCALRESULTS__I_OFF__SHIFT 8 +#define MDM_PGA_LP_RETENT_DCCALRESULTS__I_OFF__WIDTH 5 +#define MDM_PGA_LP_RETENT_DCCALRESULTS__I_OFF__MASK 0x00001f00U +#define MDM_PGA_LP_RETENT_DCCALRESULTS__I_OFF__READ(src) \ + (((uint32_t)(src)\ + & 0x00001f00U) >> 8) +#define MDM_PGA_LP_RETENT_DCCALRESULTS__I_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bb2gain */ +/** + * @defgroup mdm_regs_core_bb2gain_field bb2gain_field + * @brief macros for field bb2gain + * @details bb2gain value used in PGA cal + * @{ + */ +#define MDM_PGA_LP_RETENT_DCCALRESULTS__BB2GAIN__SHIFT 16 +#define MDM_PGA_LP_RETENT_DCCALRESULTS__BB2GAIN__WIDTH 5 +#define MDM_PGA_LP_RETENT_DCCALRESULTS__BB2GAIN__MASK 0x001f0000U +#define MDM_PGA_LP_RETENT_DCCALRESULTS__BB2GAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x001f0000U) >> 16) +#define MDM_PGA_LP_RETENT_DCCALRESULTS__BB2GAIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field done */ +/** + * @defgroup mdm_regs_core_done_field done_field + * @brief macros for field done + * @details hardware/software triiger DC calibration done + * @{ + */ +#define MDM_PGA_LP_RETENT_DCCALRESULTS__DONE__SHIFT 31 +#define MDM_PGA_LP_RETENT_DCCALRESULTS__DONE__WIDTH 1 +#define MDM_PGA_LP_RETENT_DCCALRESULTS__DONE__MASK 0x80000000U +#define MDM_PGA_LP_RETENT_DCCALRESULTS__DONE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_PGA_LP_RETENT_DCCALRESULTS__DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_PGA_LP_RETENT_DCCALRESULTS__DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_PGA_LP_RETENT_DCCALRESULTS__DONE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_PGA_LP_RETENT_DCCALRESULTS__TYPE uint32_t +#define MDM_PGA_LP_RETENT_DCCALRESULTS__READ 0x801f1f1fU +#define MDM_PGA_LP_RETENT_DCCALRESULTS__PRESERVED 0x00000000U +#define MDM_PGA_LP_RETENT_DCCALRESULTS__RESET_VALUE 0x00000000U + +#endif /* __MDM_PGA_LP_RETENT_DCCALRESULTS_MACRO__ */ + +/** @} end of pga_lp_retent_dccalresults */ + +/* macros for BlueprintGlobalNameSpace::MDM_pga_lp_dccalresults2 */ +/** + * @defgroup mdm_regs_core_pga_lp_dccalresults2 pga_lp_dccalresults2 + * @brief DC offset calibration results, averages for low power mode for PGA definitions. + * @{ + */ +#ifndef __MDM_PGA_LP_DCCALRESULTS2_MACRO__ +#define __MDM_PGA_LP_DCCALRESULTS2_MACRO__ + +/* macros for field avg_q */ +/** + * @defgroup mdm_regs_core_avg_q_field avg_q_field + * @brief macros for field avg_q + * @details calculated average of ADC Q samples + * @{ + */ +#define MDM_PGA_LP_DCCALRESULTS2__AVG_Q__SHIFT 0 +#define MDM_PGA_LP_DCCALRESULTS2__AVG_Q__WIDTH 8 +#define MDM_PGA_LP_DCCALRESULTS2__AVG_Q__MASK 0x000000ffU +#define MDM_PGA_LP_DCCALRESULTS2__AVG_Q__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define MDM_PGA_LP_DCCALRESULTS2__AVG_Q__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field avg_i */ +/** + * @defgroup mdm_regs_core_avg_i_field avg_i_field + * @brief macros for field avg_i + * @details calculated average of ADC I samples + * @{ + */ +#define MDM_PGA_LP_DCCALRESULTS2__AVG_I__SHIFT 8 +#define MDM_PGA_LP_DCCALRESULTS2__AVG_I__WIDTH 8 +#define MDM_PGA_LP_DCCALRESULTS2__AVG_I__MASK 0x0000ff00U +#define MDM_PGA_LP_DCCALRESULTS2__AVG_I__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MDM_PGA_LP_DCCALRESULTS2__AVG_I__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field done */ +/** + * @defgroup mdm_regs_core_done_field done_field + * @brief macros for field done + * @details software triiger DC calibration done + * @{ + */ +#define MDM_PGA_LP_DCCALRESULTS2__DONE__SHIFT 31 +#define MDM_PGA_LP_DCCALRESULTS2__DONE__WIDTH 1 +#define MDM_PGA_LP_DCCALRESULTS2__DONE__MASK 0x80000000U +#define MDM_PGA_LP_DCCALRESULTS2__DONE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_PGA_LP_DCCALRESULTS2__DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_PGA_LP_DCCALRESULTS2__DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_PGA_LP_DCCALRESULTS2__DONE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_PGA_LP_DCCALRESULTS2__TYPE uint32_t +#define MDM_PGA_LP_DCCALRESULTS2__READ 0x8000ffffU +#define MDM_PGA_LP_DCCALRESULTS2__PRESERVED 0x00000000U +#define MDM_PGA_LP_DCCALRESULTS2__RESET_VALUE 0x00000000U + +#endif /* __MDM_PGA_LP_DCCALRESULTS2_MACRO__ */ + +/** @} end of pga_lp_dccalresults2 */ + +/* macros for BlueprintGlobalNameSpace::MDM_notch_retent_dccalresults */ +/** + * @defgroup mdm_regs_core_notch_retent_dccalresults notch_retent_dccalresults + * @brief DC offset calibration results for notch filter definitions. + * @{ + */ +#ifndef __MDM_NOTCH_RETENT_DCCALRESULTS_MACRO__ +#define __MDM_NOTCH_RETENT_DCCALRESULTS_MACRO__ + +/* macros for field ctn */ +/** + * @defgroup mdm_regs_core_ctn_field ctn_field + * @brief macros for field ctn + * @details calculated notch ctune + * @{ + */ +#define MDM_NOTCH_RETENT_DCCALRESULTS__CTN__SHIFT 0 +#define MDM_NOTCH_RETENT_DCCALRESULTS__CTN__WIDTH 6 +#define MDM_NOTCH_RETENT_DCCALRESULTS__CTN__MASK 0x0000003fU +#define MDM_NOTCH_RETENT_DCCALRESULTS__CTN__READ(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define MDM_NOTCH_RETENT_DCCALRESULTS__CTN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field done */ +/** + * @defgroup mdm_regs_core_done_field done_field + * @brief macros for field done + * @details hardware/software triiger DC calibration done + * @{ + */ +#define MDM_NOTCH_RETENT_DCCALRESULTS__DONE__SHIFT 31 +#define MDM_NOTCH_RETENT_DCCALRESULTS__DONE__WIDTH 1 +#define MDM_NOTCH_RETENT_DCCALRESULTS__DONE__MASK 0x80000000U +#define MDM_NOTCH_RETENT_DCCALRESULTS__DONE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_NOTCH_RETENT_DCCALRESULTS__DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_NOTCH_RETENT_DCCALRESULTS__DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_NOTCH_RETENT_DCCALRESULTS__DONE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_NOTCH_RETENT_DCCALRESULTS__TYPE uint32_t +#define MDM_NOTCH_RETENT_DCCALRESULTS__READ 0x8000003fU +#define MDM_NOTCH_RETENT_DCCALRESULTS__PRESERVED 0x00000000U +#define MDM_NOTCH_RETENT_DCCALRESULTS__RESET_VALUE 0x00000000U + +#endif /* __MDM_NOTCH_RETENT_DCCALRESULTS_MACRO__ */ + +/** @} end of notch_retent_dccalresults */ + +/* macros for BlueprintGlobalNameSpace::MDM_notch_dccalresults2 */ +/** + * @defgroup mdm_regs_core_notch_dccalresults2 notch_dccalresults2 + * @brief DC offset calibration results, averages for notch filter definitions. + * @{ + */ +#ifndef __MDM_NOTCH_DCCALRESULTS2_MACRO__ +#define __MDM_NOTCH_DCCALRESULTS2_MACRO__ + +/* macros for field avg */ +/** + * @defgroup mdm_regs_core_avg_field avg_field + * @brief macros for field avg + * @details calculated average of ADC I and ADC Q samples + * @{ + */ +#define MDM_NOTCH_DCCALRESULTS2__AVG__SHIFT 0 +#define MDM_NOTCH_DCCALRESULTS2__AVG__WIDTH 8 +#define MDM_NOTCH_DCCALRESULTS2__AVG__MASK 0x000000ffU +#define MDM_NOTCH_DCCALRESULTS2__AVG__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_NOTCH_DCCALRESULTS2__AVG__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field done */ +/** + * @defgroup mdm_regs_core_done_field done_field + * @brief macros for field done + * @details software triiger DC calibration done + * @{ + */ +#define MDM_NOTCH_DCCALRESULTS2__DONE__SHIFT 31 +#define MDM_NOTCH_DCCALRESULTS2__DONE__WIDTH 1 +#define MDM_NOTCH_DCCALRESULTS2__DONE__MASK 0x80000000U +#define MDM_NOTCH_DCCALRESULTS2__DONE__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_NOTCH_DCCALRESULTS2__DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_NOTCH_DCCALRESULTS2__DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_NOTCH_DCCALRESULTS2__DONE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_NOTCH_DCCALRESULTS2__TYPE uint32_t +#define MDM_NOTCH_DCCALRESULTS2__READ 0x800000ffU +#define MDM_NOTCH_DCCALRESULTS2__PRESERVED 0x00000000U +#define MDM_NOTCH_DCCALRESULTS2__RESET_VALUE 0x00000000U + +#endif /* __MDM_NOTCH_DCCALRESULTS2_MACRO__ */ + +/** @} end of notch_dccalresults2 */ + +/* macros for BlueprintGlobalNameSpace::MDM_agcstatus */ +/** + * @defgroup mdm_regs_core_agcstatus agcstatus + * @brief Saved state from previous agc operation. Not necessarily a successfully received packet definitions. + * @{ + */ +#ifndef __MDM_AGCSTATUS_MACRO__ +#define __MDM_AGCSTATUS_MACRO__ + +/* macros for field rssi */ +/** + * @defgroup mdm_regs_core_rssi_field rssi_field + * @brief macros for field rssi + * @details Received Signal Strength Indicator, absolute dBm. Signed. + * @{ + */ +#define MDM_AGCSTATUS__RSSI__SHIFT 0 +#define MDM_AGCSTATUS__RSSI__WIDTH 8 +#define MDM_AGCSTATUS__RSSI__MASK 0x000000ffU +#define MDM_AGCSTATUS__RSSI__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define MDM_AGCSTATUS__RSSI__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rxgain */ +/** + * @defgroup mdm_regs_core_rxgain_field rxgain_field + * @brief macros for field rxgain + * @details Receive gain index + * @{ + */ +#define MDM_AGCSTATUS__RXGAIN__SHIFT 8 +#define MDM_AGCSTATUS__RXGAIN__WIDTH 7 +#define MDM_AGCSTATUS__RXGAIN__MASK 0x00007f00U +#define MDM_AGCSTATUS__RXGAIN__READ(src) (((uint32_t)(src) & 0x00007f00U) >> 8) +#define MDM_AGCSTATUS__RXGAIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field baseline_pwr */ +/** + * @defgroup mdm_regs_core_baseline_pwr_field baseline_pwr_field + * @brief macros for field baseline_pwr + * @details Baseline power, post-RXFIR. Signed + * @{ + */ +#define MDM_AGCSTATUS__BASELINE_PWR__SHIFT 15 +#define MDM_AGCSTATUS__BASELINE_PWR__WIDTH 8 +#define MDM_AGCSTATUS__BASELINE_PWR__MASK 0x007f8000U +#define MDM_AGCSTATUS__BASELINE_PWR__READ(src) \ + (((uint32_t)(src)\ + & 0x007f8000U) >> 15) +#define MDM_AGCSTATUS__BASELINE_PWR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sat_detected */ +/** + * @defgroup mdm_regs_core_sat_detected_field sat_detected_field + * @brief macros for field sat_detected + * @details Saturation triggered packet detection + * @{ + */ +#define MDM_AGCSTATUS__SAT_DETECTED__SHIFT 23 +#define MDM_AGCSTATUS__SAT_DETECTED__WIDTH 1 +#define MDM_AGCSTATUS__SAT_DETECTED__MASK 0x00800000U +#define MDM_AGCSTATUS__SAT_DETECTED__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define MDM_AGCSTATUS__SAT_DETECTED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define MDM_AGCSTATUS__SAT_DETECTED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define MDM_AGCSTATUS__SAT_DETECTED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field peak_detected */ +/** + * @defgroup mdm_regs_core_peak_detected_field peak_detected_field + * @brief macros for field peak_detected + * @details Analog peak triggered packet detection + * @{ + */ +#define MDM_AGCSTATUS__PEAK_DETECTED__SHIFT 24 +#define MDM_AGCSTATUS__PEAK_DETECTED__WIDTH 1 +#define MDM_AGCSTATUS__PEAK_DETECTED__MASK 0x01000000U +#define MDM_AGCSTATUS__PEAK_DETECTED__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define MDM_AGCSTATUS__PEAK_DETECTED__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define MDM_AGCSTATUS__PEAK_DETECTED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define MDM_AGCSTATUS__PEAK_DETECTED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field strong_blocker */ +/** + * @defgroup mdm_regs_core_strong_blocker_field strong_blocker_field + * @brief macros for field strong_blocker + * @details strong_blocker = (total_pwr - baseline_pwr) > cf_margin_strong_blocker_thr + * @{ + */ +#define MDM_AGCSTATUS__STRONG_BLOCKER__SHIFT 25 +#define MDM_AGCSTATUS__STRONG_BLOCKER__WIDTH 1 +#define MDM_AGCSTATUS__STRONG_BLOCKER__MASK 0x02000000U +#define MDM_AGCSTATUS__STRONG_BLOCKER__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define MDM_AGCSTATUS__STRONG_BLOCKER__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define MDM_AGCSTATUS__STRONG_BLOCKER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define MDM_AGCSTATUS__STRONG_BLOCKER__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_AGCSTATUS__TYPE uint32_t +#define MDM_AGCSTATUS__READ 0x03ffffffU +#define MDM_AGCSTATUS__PRESERVED 0x00000000U +#define MDM_AGCSTATUS__RESET_VALUE 0x00000000U + +#endif /* __MDM_AGCSTATUS_MACRO__ */ + +/** @} end of agcstatus */ + +/* macros for BlueprintGlobalNameSpace::MDM_measfreq */ +/** + * @defgroup mdm_regs_core_measfreq measfreq + * @brief Frequency offset measured by hardware definitions. + * @{ + */ +#ifndef __MDM_MEASFREQ_MACRO__ +#define __MDM_MEASFREQ_MACRO__ + +/* macros for field freq_offset */ +/** + * @defgroup mdm_regs_core_freq_offset_field freq_offset_field + * @brief macros for field freq_offset + * @details Signed quantity. MSB has weight of -1 MHz. Subsequent bits have weight of 1/2 MHz, 1/4 MHz ... LSB has weight of 1/4096 MHz. Value will be updated at initial frequency estimation, and subsequent updates when tracking, if enabled + * @{ + */ +#define MDM_MEASFREQ__FREQ_OFFSET__SHIFT 0 +#define MDM_MEASFREQ__FREQ_OFFSET__WIDTH 13 +#define MDM_MEASFREQ__FREQ_OFFSET__MASK 0x00001fffU +#define MDM_MEASFREQ__FREQ_OFFSET__READ(src) ((uint32_t)(src) & 0x00001fffU) +#define MDM_MEASFREQ__FREQ_OFFSET__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dcofftrk_i */ +/** + * @defgroup mdm_regs_core_dcofftrk_i_field dcofftrk_i_field + * @brief macros for field dcofftrk_i + * @details DC offset tracking, I side + * @{ + */ +#define MDM_MEASFREQ__DCOFFTRK_I__SHIFT 13 +#define MDM_MEASFREQ__DCOFFTRK_I__WIDTH 8 +#define MDM_MEASFREQ__DCOFFTRK_I__MASK 0x001fe000U +#define MDM_MEASFREQ__DCOFFTRK_I__READ(src) \ + (((uint32_t)(src)\ + & 0x001fe000U) >> 13) +#define MDM_MEASFREQ__DCOFFTRK_I__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dcofftrk_q */ +/** + * @defgroup mdm_regs_core_dcofftrk_q_field dcofftrk_q_field + * @brief macros for field dcofftrk_q + * @details DC offset tracking, Q side + * @{ + */ +#define MDM_MEASFREQ__DCOFFTRK_Q__SHIFT 21 +#define MDM_MEASFREQ__DCOFFTRK_Q__WIDTH 8 +#define MDM_MEASFREQ__DCOFFTRK_Q__MASK 0x1fe00000U +#define MDM_MEASFREQ__DCOFFTRK_Q__READ(src) \ + (((uint32_t)(src)\ + & 0x1fe00000U) >> 21) +#define MDM_MEASFREQ__DCOFFTRK_Q__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_MEASFREQ__TYPE uint32_t +#define MDM_MEASFREQ__READ 0x1fffffffU +#define MDM_MEASFREQ__PRESERVED 0x00000000U +#define MDM_MEASFREQ__RESET_VALUE 0x00000000U + +#endif /* __MDM_MEASFREQ_MACRO__ */ + +/** @} end of measfreq */ + +/* macros for BlueprintGlobalNameSpace::MDM_exper */ +/** + * @defgroup mdm_regs_core_exper exper + * @brief Experimental, not supported in matlab definitions. + * @{ + */ +#ifndef __MDM_EXPER_MACRO__ +#define __MDM_EXPER_MACRO__ + +/* macros for field adjust_to_target_en */ +/** + * @defgroup mdm_regs_core_adjust_to_target_en_field adjust_to_target_en_field + * @brief macros for field adjust_to_target_en + * @details bit 0: After power step bit 1: After sat/peak bit 2: After a previous adjust-to-target + * @{ + */ +#define MDM_EXPER__ADJUST_TO_TARGET_EN__SHIFT 0 +#define MDM_EXPER__ADJUST_TO_TARGET_EN__WIDTH 3 +#define MDM_EXPER__ADJUST_TO_TARGET_EN__MASK 0x00000007U +#define MDM_EXPER__ADJUST_TO_TARGET_EN__READ(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define MDM_EXPER__ADJUST_TO_TARGET_EN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define MDM_EXPER__ADJUST_TO_TARGET_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define MDM_EXPER__ADJUST_TO_TARGET_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define MDM_EXPER__ADJUST_TO_TARGET_EN__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field need_pwr_increase_for_aa */ +/** + * @defgroup mdm_regs_core_need_pwr_increase_for_aa_field need_pwr_increase_for_aa_field + * @brief macros for field need_pwr_increase_for_aa + * @details For uncoded rates only, require a power step, saturation or peak detect before enabling AA search + * @{ + */ +#define MDM_EXPER__NEED_PWR_INCREASE_FOR_AA__SHIFT 3 +#define MDM_EXPER__NEED_PWR_INCREASE_FOR_AA__WIDTH 1 +#define MDM_EXPER__NEED_PWR_INCREASE_FOR_AA__MASK 0x00000008U +#define MDM_EXPER__NEED_PWR_INCREASE_FOR_AA__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define MDM_EXPER__NEED_PWR_INCREASE_FOR_AA__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define MDM_EXPER__NEED_PWR_INCREASE_FOR_AA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define MDM_EXPER__NEED_PWR_INCREASE_FOR_AA__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define MDM_EXPER__NEED_PWR_INCREASE_FOR_AA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define MDM_EXPER__NEED_PWR_INCREASE_FOR_AA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define MDM_EXPER__NEED_PWR_INCREASE_FOR_AA__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rxgain_low_mark */ +/** + * @defgroup mdm_regs_core_rxgain_low_mark_field rxgain_low_mark_field + * @brief macros for field rxgain_low_mark + * @details Unsigned. If (baseline_pwr < baseline_pwr_low_mark) and (rxgain < rxgain_low_mark), then set rxgain to agcgain_start. The intent is to detect when the signal strength has drifted low (for example, a slowly fading interferer) but did not trigger the usual power step detect, and we are stuck at something other than a max rxgain setting, de-sensitized + * @{ + */ +#define MDM_EXPER__RXGAIN_LOW_MARK__SHIFT 4 +#define MDM_EXPER__RXGAIN_LOW_MARK__WIDTH 7 +#define MDM_EXPER__RXGAIN_LOW_MARK__MASK 0x000007f0U +#define MDM_EXPER__RXGAIN_LOW_MARK__READ(src) \ + (((uint32_t)(src)\ + & 0x000007f0U) >> 4) +#define MDM_EXPER__RXGAIN_LOW_MARK__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x000007f0U) +#define MDM_EXPER__RXGAIN_LOW_MARK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007f0U) | (((uint32_t)(src) <<\ + 4) & 0x000007f0U) +#define MDM_EXPER__RXGAIN_LOW_MARK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000007f0U))) +#define MDM_EXPER__RXGAIN_LOW_MARK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field baseline_pwr_low_mark */ +/** + * @defgroup mdm_regs_core_baseline_pwr_low_mark_field baseline_pwr_low_mark_field + * @brief macros for field baseline_pwr_low_mark + * @details Signed. 8'h80 = -128, disabling check + * @{ + */ +#define MDM_EXPER__BASELINE_PWR_LOW_MARK__SHIFT 11 +#define MDM_EXPER__BASELINE_PWR_LOW_MARK__WIDTH 8 +#define MDM_EXPER__BASELINE_PWR_LOW_MARK__MASK 0x0007f800U +#define MDM_EXPER__BASELINE_PWR_LOW_MARK__READ(src) \ + (((uint32_t)(src)\ + & 0x0007f800U) >> 11) +#define MDM_EXPER__BASELINE_PWR_LOW_MARK__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x0007f800U) +#define MDM_EXPER__BASELINE_PWR_LOW_MARK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007f800U) | (((uint32_t)(src) <<\ + 11) & 0x0007f800U) +#define MDM_EXPER__BASELINE_PWR_LOW_MARK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x0007f800U))) +#define MDM_EXPER__BASELINE_PWR_LOW_MARK__RESET_VALUE 0x00000080U +/** @} */ + +/* macros for field force_clkgat_en */ +/** + * @defgroup mdm_regs_core_force_clkgat_en_field force_clkgat_en_field + * @brief macros for field force_clkgat_en + * @details In the FPGA flow, the enable of a few hand-instantiated clock gates is bypassed. This helps FPGA implementation but results in logic that is different than the actual ASIC. This SHOULD be ok, but in case it isn't, also provide a way to do the same bypassing in ASIC, although likely with some hit on power. + * @{ + */ +#define MDM_EXPER__FORCE_CLKGAT_EN__SHIFT 19 +#define MDM_EXPER__FORCE_CLKGAT_EN__WIDTH 1 +#define MDM_EXPER__FORCE_CLKGAT_EN__MASK 0x00080000U +#define MDM_EXPER__FORCE_CLKGAT_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define MDM_EXPER__FORCE_CLKGAT_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define MDM_EXPER__FORCE_CLKGAT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define MDM_EXPER__FORCE_CLKGAT_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define MDM_EXPER__FORCE_CLKGAT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define MDM_EXPER__FORCE_CLKGAT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define MDM_EXPER__FORCE_CLKGAT_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pd_gain_drop_is_relative */ +/** + * @defgroup mdm_regs_core_pd_gain_drop_is_relative_field pd_gain_drop_is_relative_field + * @brief macros for field pd_gain_drop_is_relative + * @details If 1, gain drop for LNA/TIA peak detects is relative to current gain (like Sydney). If 0, gain drop for peak detects is relative to max gain (intended for Paris) + * @{ + */ +#define MDM_EXPER__PD_GAIN_DROP_IS_RELATIVE__SHIFT 20 +#define MDM_EXPER__PD_GAIN_DROP_IS_RELATIVE__WIDTH 1 +#define MDM_EXPER__PD_GAIN_DROP_IS_RELATIVE__MASK 0x00100000U +#define MDM_EXPER__PD_GAIN_DROP_IS_RELATIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define MDM_EXPER__PD_GAIN_DROP_IS_RELATIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define MDM_EXPER__PD_GAIN_DROP_IS_RELATIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define MDM_EXPER__PD_GAIN_DROP_IS_RELATIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define MDM_EXPER__PD_GAIN_DROP_IS_RELATIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define MDM_EXPER__PD_GAIN_DROP_IS_RELATIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define MDM_EXPER__PD_GAIN_DROP_IS_RELATIVE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_EXPER__TYPE uint32_t +#define MDM_EXPER__READ 0x001fffffU +#define MDM_EXPER__WRITE 0x001fffffU +#define MDM_EXPER__PRESERVED 0x00000000U +#define MDM_EXPER__RESET_VALUE 0x00040007U + +#endif /* __MDM_EXPER_MACRO__ */ + +/** @} end of exper */ + +/* macros for BlueprintGlobalNameSpace::MDM_spare0 */ +/** + * @defgroup mdm_regs_core_spare0 spare0 + * @brief spare register 0 definitions. + * @{ + */ +#ifndef __MDM_SPARE0_MACRO__ +#define __MDM_SPARE0_MACRO__ + +/* macros for field val */ +/** + * @defgroup mdm_regs_core_val_field val_field + * @brief macros for field val + * @details spare bits + * @{ + */ +#define MDM_SPARE0__VAL__SHIFT 0 +#define MDM_SPARE0__VAL__WIDTH 32 +#define MDM_SPARE0__VAL__MASK 0xffffffffU +#define MDM_SPARE0__VAL__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define MDM_SPARE0__VAL__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define MDM_SPARE0__VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define MDM_SPARE0__VAL__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define MDM_SPARE0__VAL__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_SPARE0__TYPE uint32_t +#define MDM_SPARE0__READ 0xffffffffU +#define MDM_SPARE0__WRITE 0xffffffffU +#define MDM_SPARE0__PRESERVED 0x00000000U +#define MDM_SPARE0__RESET_VALUE 0x00000000U + +#endif /* __MDM_SPARE0_MACRO__ */ + +/** @} end of spare0 */ + +/* macros for BlueprintGlobalNameSpace::MDM_debug */ +/** + * @defgroup mdm_regs_core_debug debug + * @brief Expose debug signals on mdm_out definitions. + * @{ + */ +#ifndef __MDM_DEBUG_MACRO__ +#define __MDM_DEBUG_MACRO__ + +/* macros for field select */ +/** + * @defgroup mdm_regs_core_select_field select_field + * @brief macros for field select + * @details 0: disable 1: {tia_peakdet_d2, meas_pwr_valid, rfin_peakdet_d2, sat, power_step_detected, r_rxfe_sm[2:0]} 2: {rx_en, rxgain[6:0]} 3: baseline_pwr[7:0] 4: raw_phase[7:0] 5: Upper 8 bits of soft_demod 6: {current_threshold_met, adjust_timing_faster, adjust_timing_slower, pd_out[1:0], r_timesync_sm[2:0]} 7: {enable_syncdemod, update_same, update_flipped, r_freq_mu_ptr[1:0], rx_data_strobe, rx_data_int, access_address_found} 8: {tx_en, tx_data_valid, tx_data, rx_en, rx_data, rx_data_valid, access_address_found, rssi_req} 9: Upper 8 bits of soft_demod_ffe 10: {lr_demap_valid, access_address_found, lr_rate_is_500k, final_flush, lr_rx_data_valid, lr_rx_data, r_vit_sm[1:0]} 11: {coded_corr_det_sign, sat, new_peak, coded_corr_detect, enable_coded_corr_det, r_rxfe_sm[2:0]} 12: rif_i[7:0] 13: rif_q[7:0] 14: {lr_compare_access_address, enable_uncoded for oscorr, match_count0[5:0]} 15: inband_pwr 16: r_last_trg_dbfs 17: {assert_reset_freq_sync, r_made_a_gain_change, adjust_to_target, r_gain_change_adjust_to_target_blocker, c_rfin_pd_meets_thr, c_tia_pd_meets_thr, r_freq_sync_window_select[1:0]} 18: {1'b0, dbg_srch_bit_cntr, dbg_dccal_st} 19: {2'b0, dbg_caldc, dbg_dccal_st} 20: dbg_pga_dcoc_i 21: dbg_pga_dcoc_i 22: {antenna_selected, left_shift, lc_iq_sampling_pulse, lc_direction_find_enable} 23: dbg_rif, which has an upstream mux in rif 24: dccal search value i 25: dccal search value q 26: dccal average i 27: dccal average q 28: dccal bb2 dcoc i 29: dccal bb2 dcoc q 30: dccal bb1 dcoc i 31: dccal bb1 dcoc q 32: cfoest, max range is +/- 0.5 MHz + * @{ + */ +#define MDM_DEBUG__SELECT__SHIFT 0 +#define MDM_DEBUG__SELECT__WIDTH 6 +#define MDM_DEBUG__SELECT__MASK 0x0000003fU +#define MDM_DEBUG__SELECT__READ(src) ((uint32_t)(src) & 0x0000003fU) +#define MDM_DEBUG__SELECT__WRITE(src) ((uint32_t)(src) & 0x0000003fU) +#define MDM_DEBUG__SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define MDM_DEBUG__SELECT__VERIFY(src) (!(((uint32_t)(src) & ~0x0000003fU))) +#define MDM_DEBUG__SELECT__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_DEBUG__TYPE uint32_t +#define MDM_DEBUG__READ 0x0000003fU +#define MDM_DEBUG__WRITE 0x0000003fU +#define MDM_DEBUG__PRESERVED 0x00000000U +#define MDM_DEBUG__RESET_VALUE 0x00000000U + +#endif /* __MDM_DEBUG_MACRO__ */ + +/** @} end of debug */ + +/* macros for BlueprintGlobalNameSpace::MDM_lc2lc */ +/** + * @defgroup mdm_regs_core_lc2lc lc2lc + * @brief LC2LC loop back mode definitions. + * @{ + */ +#ifndef __MDM_LC2LC_MACRO__ +#define __MDM_LC2LC_MACRO__ + +/* macros for field cntl */ +/** + * @defgroup mdm_regs_core_cntl_field cntl_field + * @brief macros for field cntl + * @details Control, 1 to enable loop back + * @{ + */ +#define MDM_LC2LC__CNTL__SHIFT 0 +#define MDM_LC2LC__CNTL__WIDTH 1 +#define MDM_LC2LC__CNTL__MASK 0x00000001U +#define MDM_LC2LC__CNTL__READ(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_LC2LC__CNTL__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_LC2LC__CNTL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define MDM_LC2LC__CNTL__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define MDM_LC2LC__CNTL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_LC2LC__CNTL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_LC2LC__CNTL__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_LC2LC__TYPE uint32_t +#define MDM_LC2LC__READ 0x00000001U +#define MDM_LC2LC__WRITE 0x00000001U +#define MDM_LC2LC__PRESERVED 0x00000000U +#define MDM_LC2LC__RESET_VALUE 0x00000000U + +#endif /* __MDM_LC2LC_MACRO__ */ + +/** @} end of lc2lc */ + +/* macros for BlueprintGlobalNameSpace::MDM_irq */ +/** + * @defgroup mdm_regs_core_irq irq + * @brief interrupt status definitions. + * @{ + */ +#ifndef __MDM_IRQ_MACRO__ +#define __MDM_IRQ_MACRO__ + +/* macros for field dccal_done */ +/** + * @defgroup mdm_regs_core_dccal_done_field dccal_done_field + * @brief macros for field dccal_done + * @details Software triggered dc calibration done + * @{ + */ +#define MDM_IRQ__DCCAL_DONE__SHIFT 0 +#define MDM_IRQ__DCCAL_DONE__WIDTH 1 +#define MDM_IRQ__DCCAL_DONE__MASK 0x00000001U +#define MDM_IRQ__DCCAL_DONE__READ(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_IRQ__DCCAL_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_IRQ__DCCAL_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_IRQ__DCCAL_DONE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_IRQ__TYPE uint32_t +#define MDM_IRQ__READ 0x00000001U +#define MDM_IRQ__PRESERVED 0x00000000U +#define MDM_IRQ__RESET_VALUE 0x00000000U + +#endif /* __MDM_IRQ_MACRO__ */ + +/** @} end of irq */ + +/* macros for BlueprintGlobalNameSpace::MDM_irqm */ +/** + * @defgroup mdm_regs_core_irqm irqm + * @brief interrupt mask definitions. + * @{ + */ +#ifndef __MDM_IRQM_MACRO__ +#define __MDM_IRQM_MACRO__ + +/* macros for field dccal_done */ +/** + * @defgroup mdm_regs_core_dccal_done_field dccal_done_field + * @brief macros for field dccal_done + * @details Software triggered dc calibration done mask + * @{ + */ +#define MDM_IRQM__DCCAL_DONE__SHIFT 0 +#define MDM_IRQM__DCCAL_DONE__WIDTH 1 +#define MDM_IRQM__DCCAL_DONE__MASK 0x00000001U +#define MDM_IRQM__DCCAL_DONE__READ(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_IRQM__DCCAL_DONE__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_IRQM__DCCAL_DONE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define MDM_IRQM__DCCAL_DONE__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define MDM_IRQM__DCCAL_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_IRQM__DCCAL_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_IRQM__DCCAL_DONE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_IRQM__TYPE uint32_t +#define MDM_IRQM__READ 0x00000001U +#define MDM_IRQM__WRITE 0x00000001U +#define MDM_IRQM__PRESERVED 0x00000000U +#define MDM_IRQM__RESET_VALUE 0x00000000U + +#endif /* __MDM_IRQM_MACRO__ */ + +/** @} end of irqm */ + +/* macros for BlueprintGlobalNameSpace::MDM_irqc */ +/** + * @defgroup mdm_regs_core_irqc irqc + * @brief interrupt clear definitions. + * @{ + */ +#ifndef __MDM_IRQC_MACRO__ +#define __MDM_IRQC_MACRO__ + +/* macros for field dccal_done */ +/** + * @defgroup mdm_regs_core_dccal_done_field dccal_done_field + * @brief macros for field dccal_done + * @details Software triggered dc calibration done clear + * @{ + */ +#define MDM_IRQC__DCCAL_DONE__SHIFT 0 +#define MDM_IRQC__DCCAL_DONE__WIDTH 1 +#define MDM_IRQC__DCCAL_DONE__MASK 0x00000001U +#define MDM_IRQC__DCCAL_DONE__READ(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_IRQC__DCCAL_DONE__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_IRQC__DCCAL_DONE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define MDM_IRQC__DCCAL_DONE__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define MDM_IRQC__DCCAL_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_IRQC__DCCAL_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_IRQC__DCCAL_DONE__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_IRQC__TYPE uint32_t +#define MDM_IRQC__READ 0x00000001U +#define MDM_IRQC__WRITE 0x00000001U +#define MDM_IRQC__PRESERVED 0x00000000U +#define MDM_IRQC__RESET_VALUE 0x00000000U + +#endif /* __MDM_IRQC_MACRO__ */ + +/** @} end of irqc */ + +/* macros for BlueprintGlobalNameSpace::MDM_err_inj */ +/** + * @defgroup mdm_regs_core_err_inj err_inj + * @brief error injection control, used for FPGA emulation only definitions. + * @{ + */ +#ifndef __MDM_ERR_INJ_MACRO__ +#define __MDM_ERR_INJ_MACRO__ + +/* macros for field en */ +/** + * @defgroup mdm_regs_core_en_field en_field + * @brief macros for field en + * @details 1 to enable error injection + * @{ + */ +#define MDM_ERR_INJ__EN__SHIFT 0 +#define MDM_ERR_INJ__EN__WIDTH 1 +#define MDM_ERR_INJ__EN__MASK 0x00000001U +#define MDM_ERR_INJ__EN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_ERR_INJ__EN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define MDM_ERR_INJ__EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define MDM_ERR_INJ__EN__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define MDM_ERR_INJ__EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define MDM_ERR_INJ__EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define MDM_ERR_INJ__EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field lfsr_seed */ +/** + * @defgroup mdm_regs_core_lfsr_seed_field lfsr_seed_field + * @brief macros for field lfsr_seed + * @details lfsr seed + * @{ + */ +#define MDM_ERR_INJ__LFSR_SEED__SHIFT 1 +#define MDM_ERR_INJ__LFSR_SEED__WIDTH 16 +#define MDM_ERR_INJ__LFSR_SEED__MASK 0x0001fffeU +#define MDM_ERR_INJ__LFSR_SEED__READ(src) \ + (((uint32_t)(src)\ + & 0x0001fffeU) >> 1) +#define MDM_ERR_INJ__LFSR_SEED__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x0001fffeU) +#define MDM_ERR_INJ__LFSR_SEED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fffeU) | (((uint32_t)(src) <<\ + 1) & 0x0001fffeU) +#define MDM_ERR_INJ__LFSR_SEED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x0001fffeU))) +#define MDM_ERR_INJ__LFSR_SEED__RESET_VALUE 0x00000005U +/** @} */ +#define MDM_ERR_INJ__TYPE uint32_t +#define MDM_ERR_INJ__READ 0x0001ffffU +#define MDM_ERR_INJ__WRITE 0x0001ffffU +#define MDM_ERR_INJ__PRESERVED 0x00000000U +#define MDM_ERR_INJ__RESET_VALUE 0x0000000aU + +#endif /* __MDM_ERR_INJ_MACRO__ */ + +/** @} end of err_inj */ + +/* macros for BlueprintGlobalNameSpace::MDM_debug32 */ +/** + * @defgroup mdm_regs_core_debug32 debug32 + * @brief Expose debug signals on dbg32_out for FPGA emulation only definitions. + * @{ + */ +#ifndef __MDM_DEBUG32_MACRO__ +#define __MDM_DEBUG32_MACRO__ + +/* macros for field select0 */ +/** + * @defgroup mdm_regs_core_select0_field select0_field + * @brief macros for field select0 + * @details select debug out for dbg32_out[7:0] + * @{ + */ +#define MDM_DEBUG32__SELECT0__SHIFT 0 +#define MDM_DEBUG32__SELECT0__WIDTH 5 +#define MDM_DEBUG32__SELECT0__MASK 0x0000001fU +#define MDM_DEBUG32__SELECT0__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define MDM_DEBUG32__SELECT0__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define MDM_DEBUG32__SELECT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define MDM_DEBUG32__SELECT0__VERIFY(src) (!(((uint32_t)(src) & ~0x0000001fU))) +#define MDM_DEBUG32__SELECT0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field select1 */ +/** + * @defgroup mdm_regs_core_select1_field select1_field + * @brief macros for field select1 + * @details select debug out for dbg32_out[7:0] + * @{ + */ +#define MDM_DEBUG32__SELECT1__SHIFT 8 +#define MDM_DEBUG32__SELECT1__WIDTH 5 +#define MDM_DEBUG32__SELECT1__MASK 0x00001f00U +#define MDM_DEBUG32__SELECT1__READ(src) (((uint32_t)(src) & 0x00001f00U) >> 8) +#define MDM_DEBUG32__SELECT1__WRITE(src) (((uint32_t)(src) << 8) & 0x00001f00U) +#define MDM_DEBUG32__SELECT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((uint32_t)(src) <<\ + 8) & 0x00001f00U) +#define MDM_DEBUG32__SELECT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00001f00U))) +#define MDM_DEBUG32__SELECT1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field select2 */ +/** + * @defgroup mdm_regs_core_select2_field select2_field + * @brief macros for field select2 + * @details select debug out for dbg32_out[7:0] + * @{ + */ +#define MDM_DEBUG32__SELECT2__SHIFT 16 +#define MDM_DEBUG32__SELECT2__WIDTH 5 +#define MDM_DEBUG32__SELECT2__MASK 0x001f0000U +#define MDM_DEBUG32__SELECT2__READ(src) (((uint32_t)(src) & 0x001f0000U) >> 16) +#define MDM_DEBUG32__SELECT2__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x001f0000U) +#define MDM_DEBUG32__SELECT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((uint32_t)(src) <<\ + 16) & 0x001f0000U) +#define MDM_DEBUG32__SELECT2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x001f0000U))) +#define MDM_DEBUG32__SELECT2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field select3 */ +/** + * @defgroup mdm_regs_core_select3_field select3_field + * @brief macros for field select3 + * @details select debug out for dbg32_out[7:0] + * @{ + */ +#define MDM_DEBUG32__SELECT3__SHIFT 24 +#define MDM_DEBUG32__SELECT3__WIDTH 5 +#define MDM_DEBUG32__SELECT3__MASK 0x1f000000U +#define MDM_DEBUG32__SELECT3__READ(src) (((uint32_t)(src) & 0x1f000000U) >> 24) +#define MDM_DEBUG32__SELECT3__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x1f000000U) +#define MDM_DEBUG32__SELECT3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1f000000U) | (((uint32_t)(src) <<\ + 24) & 0x1f000000U) +#define MDM_DEBUG32__SELECT3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x1f000000U))) +#define MDM_DEBUG32__SELECT3__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field negedge_q */ +/** + * @defgroup mdm_regs_core_negedge_q_field negedge_q_field + * @brief macros for field negedge_q + * @details latch rif_q on neg edge of clk16_ddr + * @{ + */ +#define MDM_DEBUG32__NEGEDGE_Q__SHIFT 29 +#define MDM_DEBUG32__NEGEDGE_Q__WIDTH 1 +#define MDM_DEBUG32__NEGEDGE_Q__MASK 0x20000000U +#define MDM_DEBUG32__NEGEDGE_Q__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define MDM_DEBUG32__NEGEDGE_Q__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define MDM_DEBUG32__NEGEDGE_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define MDM_DEBUG32__NEGEDGE_Q__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define MDM_DEBUG32__NEGEDGE_Q__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define MDM_DEBUG32__NEGEDGE_Q__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define MDM_DEBUG32__NEGEDGE_Q__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field negedge_txdm */ +/** + * @defgroup mdm_regs_core_negedge_txdm_field negedge_txdm_field + * @brief macros for field negedge_txdm + * @details latch tx data msb on neg edge of clk16_ddr + * @{ + */ +#define MDM_DEBUG32__NEGEDGE_TXDM__SHIFT 30 +#define MDM_DEBUG32__NEGEDGE_TXDM__WIDTH 1 +#define MDM_DEBUG32__NEGEDGE_TXDM__MASK 0x40000000U +#define MDM_DEBUG32__NEGEDGE_TXDM__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define MDM_DEBUG32__NEGEDGE_TXDM__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define MDM_DEBUG32__NEGEDGE_TXDM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define MDM_DEBUG32__NEGEDGE_TXDM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define MDM_DEBUG32__NEGEDGE_TXDM__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define MDM_DEBUG32__NEGEDGE_TXDM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define MDM_DEBUG32__NEGEDGE_TXDM__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field negedge_rxgm */ +/** + * @defgroup mdm_regs_core_negedge_rxgm_field negedge_rxgm_field + * @brief macros for field negedge_rxgm + * @details latch rx gain msb on neg edge of clk16_ddr + * @{ + */ +#define MDM_DEBUG32__NEGEDGE_RXGM__SHIFT 31 +#define MDM_DEBUG32__NEGEDGE_RXGM__WIDTH 1 +#define MDM_DEBUG32__NEGEDGE_RXGM__MASK 0x80000000U +#define MDM_DEBUG32__NEGEDGE_RXGM__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define MDM_DEBUG32__NEGEDGE_RXGM__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define MDM_DEBUG32__NEGEDGE_RXGM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define MDM_DEBUG32__NEGEDGE_RXGM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define MDM_DEBUG32__NEGEDGE_RXGM__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define MDM_DEBUG32__NEGEDGE_RXGM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define MDM_DEBUG32__NEGEDGE_RXGM__RESET_VALUE 0x00000000U +/** @} */ +#define MDM_DEBUG32__TYPE uint32_t +#define MDM_DEBUG32__READ 0xff1f1f1fU +#define MDM_DEBUG32__WRITE 0xff1f1f1fU +#define MDM_DEBUG32__PRESERVED 0x00000000U +#define MDM_DEBUG32__RESET_VALUE 0x00000000U + +#endif /* __MDM_DEBUG32_MACRO__ */ + +/** @} end of debug32 */ + +/* macros for BlueprintGlobalNameSpace::MDM_duo */ +/** + * @defgroup mdm_regs_core_duo duo + * @brief path loss intended for FPGA/ASIC duo definitions. + * @{ + */ +#ifndef __MDM_DUO_MACRO__ +#define __MDM_DUO_MACRO__ + +/* macros for field path_loss */ +/** + * @defgroup mdm_regs_core_path_loss_field path_loss_field + * @brief macros for field path_loss + * @{ + */ +#define MDM_DUO__PATH_LOSS__SHIFT 0 +#define MDM_DUO__PATH_LOSS__WIDTH 7 +#define MDM_DUO__PATH_LOSS__MASK 0x0000007fU +#define MDM_DUO__PATH_LOSS__READ(src) ((uint32_t)(src) & 0x0000007fU) +#define MDM_DUO__PATH_LOSS__WRITE(src) ((uint32_t)(src) & 0x0000007fU) +#define MDM_DUO__PATH_LOSS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define MDM_DUO__PATH_LOSS__VERIFY(src) (!(((uint32_t)(src) & ~0x0000007fU))) +#define MDM_DUO__PATH_LOSS__RESET_VALUE 0x00000046U +/** @} */ +#define MDM_DUO__TYPE uint32_t +#define MDM_DUO__READ 0x0000007fU +#define MDM_DUO__WRITE 0x0000007fU +#define MDM_DUO__PRESERVED 0x00000000U +#define MDM_DUO__RESET_VALUE 0x00000046U + +#endif /* __MDM_DUO_MACRO__ */ + +/** @} end of duo */ + +/* macros for BlueprintGlobalNameSpace::MDM_core_id */ +/** + * @defgroup mdm_regs_core_core_id core_id + * @brief modem ID register definitions. + * @{ + */ +#ifndef __MDM_CORE_ID_MACRO__ +#define __MDM_CORE_ID_MACRO__ + +/* macros for field core_id */ +/** + * @defgroup mdm_regs_core_core_id_field core_id_field + * @brief macros for field core_id + * @details that's MDM in hex + * @{ + */ +#define MDM_CORE_ID__CORE_ID__SHIFT 0 +#define MDM_CORE_ID__CORE_ID__WIDTH 32 +#define MDM_CORE_ID__CORE_ID__MASK 0xffffffffU +#define MDM_CORE_ID__CORE_ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define MDM_CORE_ID__CORE_ID__RESET_VALUE 0x4d444d20U +/** @} */ +#define MDM_CORE_ID__TYPE uint32_t +#define MDM_CORE_ID__READ 0xffffffffU +#define MDM_CORE_ID__PRESERVED 0x00000000U +#define MDM_CORE_ID__RESET_VALUE 0x4d444d20U + +#endif /* __MDM_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of MDM_REGS_CORE */ +#endif /* __REG_MDM_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/pll_regs_core_macro.h b/ATM33xx-5/include/reg/pll_regs_core_macro.h new file mode 100644 index 0000000..2d0d567 --- /dev/null +++ b/ATM33xx-5/include/reg/pll_regs_core_macro.h @@ -0,0 +1,713 @@ +/* */ +/* File: pll_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic pll_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_PLL_REGS_CORE_H__ +#define __REG_PLL_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup PLL_REGS_CORE pll_regs_core + * @ingroup AT_REG + * @brief pll_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::pll_pll */ +/** + * @defgroup pll_regs_core_pll pll + * @brief State machine timing parameters and VCO adjustment definitions. + * @{ + */ +#ifndef __PLL_PLL_MACRO__ +#define __PLL_PLL_MACRO__ + +/* macros for field time_powerOnWait_x500n */ +/** + * @defgroup pll_regs_core_time_powerOnWait_x500n_field time_powerOnWait_x500n_field + * @brief macros for field time_powerOnWait_x500n + * @details Power-on settling time, min 500ns + * @{ + */ +#define PLL_PLL__TIME_POWERONWAIT_X500N__SHIFT 0 +#define PLL_PLL__TIME_POWERONWAIT_X500N__WIDTH 3 +#define PLL_PLL__TIME_POWERONWAIT_X500N__MASK 0x00000007U +#define PLL_PLL__TIME_POWERONWAIT_X500N__READ(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define PLL_PLL__TIME_POWERONWAIT_X500N__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define PLL_PLL__TIME_POWERONWAIT_X500N__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define PLL_PLL__TIME_POWERONWAIT_X500N__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define PLL_PLL__TIME_POWERONWAIT_X500N__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field time_vcoSettling_x250n */ +/** + * @defgroup pll_regs_core_time_vcoSettling_x250n_field time_vcoSettling_x250n_field + * @brief macros for field time_vcoSettling_x250n + * @details VCO settling time, min 250ns + * @{ + */ +#define PLL_PLL__TIME_VCOSETTLING_X250N__SHIFT 3 +#define PLL_PLL__TIME_VCOSETTLING_X250N__WIDTH 3 +#define PLL_PLL__TIME_VCOSETTLING_X250N__MASK 0x00000038U +#define PLL_PLL__TIME_VCOSETTLING_X250N__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define PLL_PLL__TIME_VCOSETTLING_X250N__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define PLL_PLL__TIME_VCOSETTLING_X250N__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define PLL_PLL__TIME_VCOSETTLING_X250N__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define PLL_PLL__TIME_VCOSETTLING_X250N__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field time_vcoCount_x250n */ +/** + * @defgroup pll_regs_core_time_vcoCount_x250n_field time_vcoCount_x250n_field + * @brief macros for field time_vcoCount_x250n + * @details Counting time of VCO cycles during locking, min 250ns + * @{ + */ +#define PLL_PLL__TIME_VCOCOUNT_X250N__SHIFT 6 +#define PLL_PLL__TIME_VCOCOUNT_X250N__WIDTH 3 +#define PLL_PLL__TIME_VCOCOUNT_X250N__MASK 0x000001c0U +#define PLL_PLL__TIME_VCOCOUNT_X250N__READ(src) \ + (((uint32_t)(src)\ + & 0x000001c0U) >> 6) +#define PLL_PLL__TIME_VCOCOUNT_X250N__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000001c0U) +#define PLL_PLL__TIME_VCOCOUNT_X250N__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((uint32_t)(src) <<\ + 6) & 0x000001c0U) +#define PLL_PLL__TIME_VCOCOUNT_X250N__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000001c0U))) +#define PLL_PLL__TIME_VCOCOUNT_X250N__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field time_closeLoop_x500n */ +/** + * @defgroup pll_regs_core_time_closeLoop_x500n_field time_closeLoop_x500n_field + * @brief macros for field time_closeLoop_x500n + * @details Settling time after closing loop, min 500ns + * @{ + */ +#define PLL_PLL__TIME_CLOSELOOP_X500N__SHIFT 9 +#define PLL_PLL__TIME_CLOSELOOP_X500N__WIDTH 3 +#define PLL_PLL__TIME_CLOSELOOP_X500N__MASK 0x00000e00U +#define PLL_PLL__TIME_CLOSELOOP_X500N__READ(src) \ + (((uint32_t)(src)\ + & 0x00000e00U) >> 9) +#define PLL_PLL__TIME_CLOSELOOP_X500N__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000e00U) +#define PLL_PLL__TIME_CLOSELOOP_X500N__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((uint32_t)(src) <<\ + 9) & 0x00000e00U) +#define PLL_PLL__TIME_CLOSELOOP_X500N__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000e00U))) +#define PLL_PLL__TIME_CLOSELOOP_X500N__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field vcoGm */ +/** + * @defgroup pll_regs_core_vcoGm_field vcoGm_field + * @brief macros for field vcoGm + * @details VCO Gm adjustment + * @{ + */ +#define PLL_PLL__VCOGM__SHIFT 12 +#define PLL_PLL__VCOGM__WIDTH 4 +#define PLL_PLL__VCOGM__MASK 0x0000f000U +#define PLL_PLL__VCOGM__READ(src) (((uint32_t)(src) & 0x0000f000U) >> 12) +#define PLL_PLL__VCOGM__WRITE(src) (((uint32_t)(src) << 12) & 0x0000f000U) +#define PLL_PLL__VCOGM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((uint32_t)(src) <<\ + 12) & 0x0000f000U) +#define PLL_PLL__VCOGM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0000f000U))) +#define PLL_PLL__VCOGM__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field vcoLpfR */ +/** + * @defgroup pll_regs_core_vcoLpfR_field vcoLpfR_field + * @brief macros for field vcoLpfR + * @details Corner freq of noise filter in VCO, trade off between period and cycle-cycle jitter + * @{ + */ +#define PLL_PLL__VCOLPFR__SHIFT 16 +#define PLL_PLL__VCOLPFR__WIDTH 4 +#define PLL_PLL__VCOLPFR__MASK 0x000f0000U +#define PLL_PLL__VCOLPFR__READ(src) (((uint32_t)(src) & 0x000f0000U) >> 16) +#define PLL_PLL__VCOLPFR__WRITE(src) (((uint32_t)(src) << 16) & 0x000f0000U) +#define PLL_PLL__VCOLPFR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((uint32_t)(src) <<\ + 16) & 0x000f0000U) +#define PLL_PLL__VCOLPFR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x000f0000U))) +#define PLL_PLL__VCOLPFR__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field vcoKvf */ +/** + * @defgroup pll_regs_core_vcoKvf_field vcoKvf_field + * @brief macros for field vcoKvf + * @details Pin Vc voltage used during locking + * @{ + */ +#define PLL_PLL__VCOKVF__SHIFT 20 +#define PLL_PLL__VCOKVF__WIDTH 2 +#define PLL_PLL__VCOKVF__MASK 0x00300000U +#define PLL_PLL__VCOKVF__READ(src) (((uint32_t)(src) & 0x00300000U) >> 20) +#define PLL_PLL__VCOKVF__WRITE(src) (((uint32_t)(src) << 20) & 0x00300000U) +#define PLL_PLL__VCOKVF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00300000U) | (((uint32_t)(src) <<\ + 20) & 0x00300000U) +#define PLL_PLL__VCOKVF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00300000U))) +#define PLL_PLL__VCOKVF__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field sparebits */ +/** + * @defgroup pll_regs_core_sparebits_field sparebits_field + * @brief macros for field sparebits + * @details spares + * @{ + */ +#define PLL_PLL__SPAREBITS__SHIFT 22 +#define PLL_PLL__SPAREBITS__WIDTH 4 +#define PLL_PLL__SPAREBITS__MASK 0x03c00000U +#define PLL_PLL__SPAREBITS__READ(src) (((uint32_t)(src) & 0x03c00000U) >> 22) +#define PLL_PLL__SPAREBITS__WRITE(src) (((uint32_t)(src) << 22) & 0x03c00000U) +#define PLL_PLL__SPAREBITS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03c00000U) | (((uint32_t)(src) <<\ + 22) & 0x03c00000U) +#define PLL_PLL__SPAREBITS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x03c00000U))) +#define PLL_PLL__SPAREBITS__RESET_VALUE 0x00000000U +/** @} */ +#define PLL_PLL__TYPE uint32_t +#define PLL_PLL__READ 0x03ffffffU +#define PLL_PLL__WRITE 0x03ffffffU +#define PLL_PLL__PRESERVED 0x00000000U +#define PLL_PLL__RESET_VALUE 0x002846c9U + +#endif /* __PLL_PLL_MACRO__ */ + +/** @} end of pll */ + +/* macros for BlueprintGlobalNameSpace::pll_test */ +/** + * @defgroup pll_regs_core_test test + * @brief Debug and testing definitions. + * @{ + */ +#ifndef __PLL_TEST_MACRO__ +#define __PLL_TEST_MACRO__ + +/* macros for field rstPfdB_ovr */ +/** + * @defgroup pll_regs_core_rstPfdB_ovr_field rstPfdB_ovr_field + * @brief macros for field rstPfdB_ovr + * @details Force PFD in reset + * @{ + */ +#define PLL_TEST__RSTPFDB_OVR__SHIFT 0 +#define PLL_TEST__RSTPFDB_OVR__WIDTH 1 +#define PLL_TEST__RSTPFDB_OVR__MASK 0x00000001U +#define PLL_TEST__RSTPFDB_OVR__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PLL_TEST__RSTPFDB_OVR__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PLL_TEST__RSTPFDB_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PLL_TEST__RSTPFDB_OVR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PLL_TEST__RSTPFDB_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PLL_TEST__RSTPFDB_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PLL_TEST__RSTPFDB_OVR__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field rstDivRefB_ovr */ +/** + * @defgroup pll_regs_core_rstDivRefB_ovr_field rstDivRefB_ovr_field + * @brief macros for field rstDivRefB_ovr + * @details Force reference divider in reset if 0 + * @{ + */ +#define PLL_TEST__RSTDIVREFB_OVR__SHIFT 1 +#define PLL_TEST__RSTDIVREFB_OVR__WIDTH 1 +#define PLL_TEST__RSTDIVREFB_OVR__MASK 0x00000002U +#define PLL_TEST__RSTDIVREFB_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PLL_TEST__RSTDIVREFB_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PLL_TEST__RSTDIVREFB_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PLL_TEST__RSTDIVREFB_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PLL_TEST__RSTDIVREFB_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PLL_TEST__RSTDIVREFB_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PLL_TEST__RSTDIVREFB_OVR__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field rstDivOutB_ovr */ +/** + * @defgroup pll_regs_core_rstDivOutB_ovr_field rstDivOutB_ovr_field + * @brief macros for field rstDivOutB_ovr + * @details Force output divider in reset if 0 + * @{ + */ +#define PLL_TEST__RSTDIVOUTB_OVR__SHIFT 2 +#define PLL_TEST__RSTDIVOUTB_OVR__WIDTH 1 +#define PLL_TEST__RSTDIVOUTB_OVR__MASK 0x00000004U +#define PLL_TEST__RSTDIVOUTB_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PLL_TEST__RSTDIVOUTB_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PLL_TEST__RSTDIVOUTB_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PLL_TEST__RSTDIVOUTB_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PLL_TEST__RSTDIVOUTB_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PLL_TEST__RSTDIVOUTB_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PLL_TEST__RSTDIVOUTB_OVR__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field rstDivFbB_ovr */ +/** + * @defgroup pll_regs_core_rstDivFbB_ovr_field rstDivFbB_ovr_field + * @brief macros for field rstDivFbB_ovr + * @details Force feedback divider in reset if 0 + * @{ + */ +#define PLL_TEST__RSTDIVFBB_OVR__SHIFT 3 +#define PLL_TEST__RSTDIVFBB_OVR__WIDTH 1 +#define PLL_TEST__RSTDIVFBB_OVR__MASK 0x00000008U +#define PLL_TEST__RSTDIVFBB_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PLL_TEST__RSTDIVFBB_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PLL_TEST__RSTDIVFBB_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PLL_TEST__RSTDIVFBB_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PLL_TEST__RSTDIVFBB_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PLL_TEST__RSTDIVFBB_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PLL_TEST__RSTDIVFBB_OVR__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field enDivRef_ovr */ +/** + * @defgroup pll_regs_core_enDivRef_ovr_field enDivRef_ovr_field + * @brief macros for field enDivRef_ovr + * @details Force reference divider off if 0 + * @{ + */ +#define PLL_TEST__ENDIVREF_OVR__SHIFT 4 +#define PLL_TEST__ENDIVREF_OVR__WIDTH 1 +#define PLL_TEST__ENDIVREF_OVR__MASK 0x00000010U +#define PLL_TEST__ENDIVREF_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PLL_TEST__ENDIVREF_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PLL_TEST__ENDIVREF_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PLL_TEST__ENDIVREF_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PLL_TEST__ENDIVREF_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PLL_TEST__ENDIVREF_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PLL_TEST__ENDIVREF_OVR__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field enDivOut_ovr */ +/** + * @defgroup pll_regs_core_enDivOut_ovr_field enDivOut_ovr_field + * @brief macros for field enDivOut_ovr + * @details Force output divider off if 0 + * @{ + */ +#define PLL_TEST__ENDIVOUT_OVR__SHIFT 5 +#define PLL_TEST__ENDIVOUT_OVR__WIDTH 1 +#define PLL_TEST__ENDIVOUT_OVR__MASK 0x00000020U +#define PLL_TEST__ENDIVOUT_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PLL_TEST__ENDIVOUT_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define PLL_TEST__ENDIVOUT_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define PLL_TEST__ENDIVOUT_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define PLL_TEST__ENDIVOUT_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PLL_TEST__ENDIVOUT_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PLL_TEST__ENDIVOUT_OVR__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field enDivFb_ovr */ +/** + * @defgroup pll_regs_core_enDivFb_ovr_field enDivFb_ovr_field + * @brief macros for field enDivFb_ovr + * @details Force feedback divider off if 0 + * @{ + */ +#define PLL_TEST__ENDIVFB_OVR__SHIFT 6 +#define PLL_TEST__ENDIVFB_OVR__WIDTH 1 +#define PLL_TEST__ENDIVFB_OVR__MASK 0x00000040U +#define PLL_TEST__ENDIVFB_OVR__READ(src) (((uint32_t)(src) & 0x00000040U) >> 6) +#define PLL_TEST__ENDIVFB_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define PLL_TEST__ENDIVFB_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PLL_TEST__ENDIVFB_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PLL_TEST__ENDIVFB_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PLL_TEST__ENDIVFB_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PLL_TEST__ENDIVFB_OVR__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field gateOutB_en_ov */ +/** + * @defgroup pll_regs_core_gateOutB_en_ov_field gateOutB_en_ov_field + * @brief macros for field gateOutB_en_ov + * @details Enable override for output clock gating during settling, if 1, use gateOutB_ovr value + * @{ + */ +#define PLL_TEST__GATEOUTB_EN_OV__SHIFT 7 +#define PLL_TEST__GATEOUTB_EN_OV__WIDTH 1 +#define PLL_TEST__GATEOUTB_EN_OV__MASK 0x00000080U +#define PLL_TEST__GATEOUTB_EN_OV__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define PLL_TEST__GATEOUTB_EN_OV__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define PLL_TEST__GATEOUTB_EN_OV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define PLL_TEST__GATEOUTB_EN_OV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define PLL_TEST__GATEOUTB_EN_OV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define PLL_TEST__GATEOUTB_EN_OV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define PLL_TEST__GATEOUTB_EN_OV__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field gateOutB_ovr */ +/** + * @defgroup pll_regs_core_gateOutB_ovr_field gateOutB_ovr_field + * @brief macros for field gateOutB_ovr + * @details Value for gateOutB if gateOutB_en_ov is set + * @{ + */ +#define PLL_TEST__GATEOUTB_OVR__SHIFT 8 +#define PLL_TEST__GATEOUTB_OVR__WIDTH 1 +#define PLL_TEST__GATEOUTB_OVR__MASK 0x00000100U +#define PLL_TEST__GATEOUTB_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define PLL_TEST__GATEOUTB_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define PLL_TEST__GATEOUTB_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define PLL_TEST__GATEOUTB_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define PLL_TEST__GATEOUTB_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PLL_TEST__GATEOUTB_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PLL_TEST__GATEOUTB_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field atbsel */ +/** + * @defgroup pll_regs_core_atbsel_field atbsel_field + * @brief macros for field atbsel + * @details ATB selection, 0: high-Z, 1: Cstop, 2: VCO supply (vddx), 3: Core supply (vdd) + * @{ + */ +#define PLL_TEST__ATBSEL__SHIFT 9 +#define PLL_TEST__ATBSEL__WIDTH 2 +#define PLL_TEST__ATBSEL__MASK 0x00000600U +#define PLL_TEST__ATBSEL__READ(src) (((uint32_t)(src) & 0x00000600U) >> 9) +#define PLL_TEST__ATBSEL__WRITE(src) (((uint32_t)(src) << 9) & 0x00000600U) +#define PLL_TEST__ATBSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000600U) | (((uint32_t)(src) <<\ + 9) & 0x00000600U) +#define PLL_TEST__ATBSEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000600U))) +#define PLL_TEST__ATBSEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field forcePinVc */ +/** + * @defgroup pll_regs_core_forcePinVc_field forcePinVc_field + * @brief macros for field forcePinVc + * @details Force pinVc + * @{ + */ +#define PLL_TEST__FORCEPINVC__SHIFT 11 +#define PLL_TEST__FORCEPINVC__WIDTH 1 +#define PLL_TEST__FORCEPINVC__MASK 0x00000800U +#define PLL_TEST__FORCEPINVC__READ(src) (((uint32_t)(src) & 0x00000800U) >> 11) +#define PLL_TEST__FORCEPINVC__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define PLL_TEST__FORCEPINVC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define PLL_TEST__FORCEPINVC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define PLL_TEST__FORCEPINVC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define PLL_TEST__FORCEPINVC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define PLL_TEST__FORCEPINVC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field vcoSetting_ovr */ +/** + * @defgroup pll_regs_core_vcoSetting_ovr_field vcoSetting_ovr_field + * @brief macros for field vcoSetting_ovr + * @details override vcoSetting + * @{ + */ +#define PLL_TEST__VCOSETTING_OVR__SHIFT 12 +#define PLL_TEST__VCOSETTING_OVR__WIDTH 1 +#define PLL_TEST__VCOSETTING_OVR__MASK 0x00001000U +#define PLL_TEST__VCOSETTING_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define PLL_TEST__VCOSETTING_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define PLL_TEST__VCOSETTING_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define PLL_TEST__VCOSETTING_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define PLL_TEST__VCOSETTING_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define PLL_TEST__VCOSETTING_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define PLL_TEST__VCOSETTING_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field vcoSetting_ovrVal */ +/** + * @defgroup pll_regs_core_vcoSetting_ovrVal_field vcoSetting_ovrVal_field + * @brief macros for field vcoSetting_ovrVal + * @details vcoSetting value when vcoSetting_ovr=1 + * @{ + */ +#define PLL_TEST__VCOSETTING_OVRVAL__SHIFT 13 +#define PLL_TEST__VCOSETTING_OVRVAL__WIDTH 4 +#define PLL_TEST__VCOSETTING_OVRVAL__MASK 0x0001e000U +#define PLL_TEST__VCOSETTING_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x0001e000U) >> 13) +#define PLL_TEST__VCOSETTING_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0001e000U) +#define PLL_TEST__VCOSETTING_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001e000U) | (((uint32_t)(src) <<\ + 13) & 0x0001e000U) +#define PLL_TEST__VCOSETTING_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0001e000U))) +#define PLL_TEST__VCOSETTING_OVRVAL__RESET_VALUE 0x00000008U +/** @} */ +#define PLL_TEST__TYPE uint32_t +#define PLL_TEST__READ 0x0001ffffU +#define PLL_TEST__WRITE 0x0001ffffU +#define PLL_TEST__PRESERVED 0x00000000U +#define PLL_TEST__RESET_VALUE 0x0001007fU + +#endif /* __PLL_TEST_MACRO__ */ + +/** @} end of test */ + +/* macros for BlueprintGlobalNameSpace::pll_readout */ +/** + * @defgroup pll_regs_core_readout readout + * @brief readout bits definitions. + * @{ + */ +#ifndef __PLL_READOUT_MACRO__ +#define __PLL_READOUT_MACRO__ + +/* macros for field vcoSetting */ +/** + * @defgroup pll_regs_core_vcoSetting_field vcoSetting_field + * @brief macros for field vcoSetting + * @details the vcoSetting currently applied + * @{ + */ +#define PLL_READOUT__VCOSETTING__SHIFT 0 +#define PLL_READOUT__VCOSETTING__WIDTH 4 +#define PLL_READOUT__VCOSETTING__MASK 0x0000000fU +#define PLL_READOUT__VCOSETTING__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define PLL_READOUT__VCOSETTING__RESET_VALUE 0x00000000U +/** @} */ +#define PLL_READOUT__TYPE uint32_t +#define PLL_READOUT__READ 0x0000000fU +#define PLL_READOUT__PRESERVED 0x00000000U +#define PLL_READOUT__RESET_VALUE 0x00000000U + +#endif /* __PLL_READOUT_MACRO__ */ + +/** @} end of readout */ + +/* macros for BlueprintGlobalNameSpace::pll_core_id */ +/** + * @defgroup pll_regs_core_core_id core_id + * @brief Core ID definitions. + * @{ + */ +#ifndef __PLL_CORE_ID_MACRO__ +#define __PLL_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup pll_regs_core_id_field id_field + * @brief macros for field id + * @details CPLL in ASCII, for CPU PLL + * @{ + */ +#define PLL_CORE_ID__ID__SHIFT 0 +#define PLL_CORE_ID__ID__WIDTH 32 +#define PLL_CORE_ID__ID__MASK 0xffffffffU +#define PLL_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PLL_CORE_ID__ID__RESET_VALUE 0x43504c4cU +/** @} */ +#define PLL_CORE_ID__TYPE uint32_t +#define PLL_CORE_ID__READ 0xffffffffU +#define PLL_CORE_ID__PRESERVED 0x00000000U +#define PLL_CORE_ID__RESET_VALUE 0x43504c4cU + +#endif /* __PLL_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of PLL_REGS_CORE */ +#endif /* __REG_PLL_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/pmu_gadc_regs_core_macro.h b/ATM33xx-5/include/reg/pmu_gadc_regs_core_macro.h new file mode 100644 index 0000000..a9e816d --- /dev/null +++ b/ATM33xx-5/include/reg/pmu_gadc_regs_core_macro.h @@ -0,0 +1,482 @@ +/* */ +/* File: pmu_gadc_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic pmu_gadc_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_PMU_GADC_REGS_CORE_H__ +#define __REG_PMU_GADC_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup PMU_GADC_REGS_CORE pmu_gadc_regs_core + * @ingroup AT_REG + * @brief pmu_gadc_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::GADC_gadc_ctrl */ +/** + * @defgroup pmu_gadc_regs_core_gadc_ctrl gadc_ctrl + * @brief Bias, reference voltage, sampling time settings, ATB definitions. + * @{ + */ +#ifndef __GADC_GADC_CTRL_MACRO__ +#define __GADC_GADC_CTRL_MACRO__ + +/* macros for field bias_ctrl */ +/** + * @defgroup pmu_gadc_regs_core_bias_ctrl_field bias_ctrl_field + * @brief macros for field bias_ctrl + * @details Master bias, all the bias has scaling factor of bias/0.5, I = 0.5/(1+(bias_ctrl-3)/6) uA + * @{ + */ +#define GADC_GADC_CTRL__BIAS_CTRL__SHIFT 0 +#define GADC_GADC_CTRL__BIAS_CTRL__WIDTH 3 +#define GADC_GADC_CTRL__BIAS_CTRL__MASK 0x00000007U +#define GADC_GADC_CTRL__BIAS_CTRL__READ(src) ((uint32_t)(src) & 0x00000007U) +#define GADC_GADC_CTRL__BIAS_CTRL__WRITE(src) ((uint32_t)(src) & 0x00000007U) +#define GADC_GADC_CTRL__BIAS_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define GADC_GADC_CTRL__BIAS_CTRL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define GADC_GADC_CTRL__BIAS_CTRL__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field ir2u_ctrl */ +/** + * @defgroup pmu_gadc_regs_core_ir2u_ctrl_field ir2u_ctrl_field + * @brief macros for field ir2u_ctrl + * @details 2uA bias current for the adc driver opamp, I = 2 + 0.5*(ir2u_ctrl-2) uA + * @{ + */ +#define GADC_GADC_CTRL__IR2U_CTRL__SHIFT 3 +#define GADC_GADC_CTRL__IR2U_CTRL__WIDTH 2 +#define GADC_GADC_CTRL__IR2U_CTRL__MASK 0x00000018U +#define GADC_GADC_CTRL__IR2U_CTRL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000018U) >> 3) +#define GADC_GADC_CTRL__IR2U_CTRL__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000018U) +#define GADC_GADC_CTRL__IR2U_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000018U) | (((uint32_t)(src) <<\ + 3) & 0x00000018U) +#define GADC_GADC_CTRL__IR2U_CTRL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000018U))) +#define GADC_GADC_CTRL__IR2U_CTRL__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field vcmbuf_ctrl */ +/** + * @defgroup pmu_gadc_regs_core_vcmbuf_ctrl_field vcmbuf_ctrl_field + * @brief macros for field vcmbuf_ctrl + * @details ADC driver output common mode control, V = 0.55+0.1375*(vcmbuf_ctrl-1) V + * @{ + */ +#define GADC_GADC_CTRL__VCMBUF_CTRL__SHIFT 5 +#define GADC_GADC_CTRL__VCMBUF_CTRL__WIDTH 2 +#define GADC_GADC_CTRL__VCMBUF_CTRL__MASK 0x00000060U +#define GADC_GADC_CTRL__VCMBUF_CTRL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000060U) >> 5) +#define GADC_GADC_CTRL__VCMBUF_CTRL__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000060U) +#define GADC_GADC_CTRL__VCMBUF_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000060U) | (((uint32_t)(src) <<\ + 5) & 0x00000060U) +#define GADC_GADC_CTRL__VCMBUF_CTRL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000060U))) +#define GADC_GADC_CTRL__VCMBUF_CTRL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field vcmadc_ctrl */ +/** + * @defgroup pmu_gadc_regs_core_vcmadc_ctrl_field vcmadc_ctrl_field + * @brief macros for field vcmadc_ctrl + * @details ADC sampling common mode voltage, V=0.55+0.1375*(vcmadc_ctrl-2) V + * @{ + */ +#define GADC_GADC_CTRL__VCMADC_CTRL__SHIFT 7 +#define GADC_GADC_CTRL__VCMADC_CTRL__WIDTH 2 +#define GADC_GADC_CTRL__VCMADC_CTRL__MASK 0x00000180U +#define GADC_GADC_CTRL__VCMADC_CTRL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000180U) >> 7) +#define GADC_GADC_CTRL__VCMADC_CTRL__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000180U) +#define GADC_GADC_CTRL__VCMADC_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000180U) | (((uint32_t)(src) <<\ + 7) & 0x00000180U) +#define GADC_GADC_CTRL__VCMADC_CTRL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000180U))) +#define GADC_GADC_CTRL__VCMADC_CTRL__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field adcref_ctrl */ +/** + * @defgroup pmu_gadc_regs_core_adcref_ctrl_field adcref_ctrl_field + * @brief macros for field adcref_ctrl + * @details ADC core reference voltage, 0.84V - 1.4V, V = 1 + (-0.4)/(1+6/(adcref_ctrl-3)) V + * @{ + */ +#define GADC_GADC_CTRL__ADCREF_CTRL__SHIFT 9 +#define GADC_GADC_CTRL__ADCREF_CTRL__WIDTH 3 +#define GADC_GADC_CTRL__ADCREF_CTRL__MASK 0x00000e00U +#define GADC_GADC_CTRL__ADCREF_CTRL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000e00U) >> 9) +#define GADC_GADC_CTRL__ADCREF_CTRL__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000e00U) +#define GADC_GADC_CTRL__ADCREF_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((uint32_t)(src) <<\ + 9) & 0x00000e00U) +#define GADC_GADC_CTRL__ADCREF_CTRL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000e00U))) +#define GADC_GADC_CTRL__ADCREF_CTRL__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field delay_ctrl */ +/** + * @defgroup pmu_gadc_regs_core_delay_ctrl_field delay_ctrl_field + * @brief macros for field delay_ctrl + * @details SAR logic delay control bias current, high current is less delay, I = 2 + 0.25*(delay_ctrl-4) uA + * @{ + */ +#define GADC_GADC_CTRL__DELAY_CTRL__SHIFT 12 +#define GADC_GADC_CTRL__DELAY_CTRL__WIDTH 3 +#define GADC_GADC_CTRL__DELAY_CTRL__MASK 0x00007000U +#define GADC_GADC_CTRL__DELAY_CTRL__READ(src) \ + (((uint32_t)(src)\ + & 0x00007000U) >> 12) +#define GADC_GADC_CTRL__DELAY_CTRL__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00007000U) +#define GADC_GADC_CTRL__DELAY_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((uint32_t)(src) <<\ + 12) & 0x00007000U) +#define GADC_GADC_CTRL__DELAY_CTRL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00007000U))) +#define GADC_GADC_CTRL__DELAY_CTRL__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field li_en */ +/** + * @defgroup pmu_gadc_regs_core_li_en_field li_en_field + * @brief macros for field li_en + * @details Enable lithium ion battery voltage measurement + * @{ + */ +#define GADC_GADC_CTRL__LI_EN__SHIFT 15 +#define GADC_GADC_CTRL__LI_EN__WIDTH 1 +#define GADC_GADC_CTRL__LI_EN__MASK 0x00008000U +#define GADC_GADC_CTRL__LI_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define GADC_GADC_CTRL__LI_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define GADC_GADC_CTRL__LI_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define GADC_GADC_CTRL__LI_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define GADC_GADC_CTRL__LI_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define GADC_GADC_CTRL__LI_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define GADC_GADC_CTRL__LI_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bypass */ +/** + * @defgroup pmu_gadc_regs_core_bypass_field bypass_field + * @brief macros for field bypass + * @details Bypass ADC driver + * @{ + */ +#define GADC_GADC_CTRL__BYPASS__SHIFT 16 +#define GADC_GADC_CTRL__BYPASS__WIDTH 1 +#define GADC_GADC_CTRL__BYPASS__MASK 0x00010000U +#define GADC_GADC_CTRL__BYPASS__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define GADC_GADC_CTRL__BYPASS__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define GADC_GADC_CTRL__BYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define GADC_GADC_CTRL__BYPASS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define GADC_GADC_CTRL__BYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define GADC_GADC_CTRL__BYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define GADC_GADC_CTRL__BYPASS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clamp */ +/** + * @defgroup pmu_gadc_regs_core_clamp_field clamp_field + * @brief macros for field clamp + * @details Core circuit protection clamp enable + * @{ + */ +#define GADC_GADC_CTRL__CLAMP__SHIFT 17 +#define GADC_GADC_CTRL__CLAMP__WIDTH 1 +#define GADC_GADC_CTRL__CLAMP__MASK 0x00020000U +#define GADC_GADC_CTRL__CLAMP__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define GADC_GADC_CTRL__CLAMP__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define GADC_GADC_CTRL__CLAMP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define GADC_GADC_CTRL__CLAMP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define GADC_GADC_CTRL__CLAMP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define GADC_GADC_CTRL__CLAMP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define GADC_GADC_CTRL__CLAMP__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field edge_sel */ +/** + * @defgroup pmu_gadc_regs_core_edge_sel_field edge_sel_field + * @brief macros for field edge_sel + * @details ADC digital output edge select, 1 for rising edge + * @{ + */ +#define GADC_GADC_CTRL__EDGE_SEL__SHIFT 18 +#define GADC_GADC_CTRL__EDGE_SEL__WIDTH 1 +#define GADC_GADC_CTRL__EDGE_SEL__MASK 0x00040000U +#define GADC_GADC_CTRL__EDGE_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define GADC_GADC_CTRL__EDGE_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define GADC_GADC_CTRL__EDGE_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define GADC_GADC_CTRL__EDGE_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define GADC_GADC_CTRL__EDGE_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define GADC_GADC_CTRL__EDGE_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define GADC_GADC_CTRL__EDGE_SEL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field atbH_sel */ +/** + * @defgroup pmu_gadc_regs_core_atbH_sel_field atbH_sel_field + * @brief macros for field atbH_sel + * @details atbH control 0: No connect 1: enable-digital 1V 2: iptat1u 3: refp-0.8V 4: nbias_ir2u 5: vcm_ir4u-0.55V 6: vcm_ir1u-0.55V 7: ir2u + * @{ + */ +#define GADC_GADC_CTRL__ATBH_SEL__SHIFT 19 +#define GADC_GADC_CTRL__ATBH_SEL__WIDTH 4 +#define GADC_GADC_CTRL__ATBH_SEL__MASK 0x00780000U +#define GADC_GADC_CTRL__ATBH_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00780000U) >> 19) +#define GADC_GADC_CTRL__ATBH_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00780000U) +#define GADC_GADC_CTRL__ATBH_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00780000U) | (((uint32_t)(src) <<\ + 19) & 0x00780000U) +#define GADC_GADC_CTRL__ATBH_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00780000U))) +#define GADC_GADC_CTRL__ATBH_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_ref */ +/** + * @defgroup pmu_gadc_regs_core_en_ref_field en_ref_field + * @brief macros for field en_ref + * @details enable reference generation circuit + * @{ + */ +#define GADC_GADC_CTRL__EN_REF__SHIFT 23 +#define GADC_GADC_CTRL__EN_REF__WIDTH 1 +#define GADC_GADC_CTRL__EN_REF__MASK 0x00800000U +#define GADC_GADC_CTRL__EN_REF__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define GADC_GADC_CTRL__EN_REF__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define GADC_GADC_CTRL__EN_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define GADC_GADC_CTRL__EN_REF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define GADC_GADC_CTRL__EN_REF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define GADC_GADC_CTRL__EN_REF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define GADC_GADC_CTRL__EN_REF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field en_buffer */ +/** + * @defgroup pmu_gadc_regs_core_en_buffer_field en_buffer_field + * @brief macros for field en_buffer + * @details enable buffer + * @{ + */ +#define GADC_GADC_CTRL__EN_BUFFER__SHIFT 24 +#define GADC_GADC_CTRL__EN_BUFFER__WIDTH 1 +#define GADC_GADC_CTRL__EN_BUFFER__MASK 0x01000000U +#define GADC_GADC_CTRL__EN_BUFFER__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define GADC_GADC_CTRL__EN_BUFFER__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define GADC_GADC_CTRL__EN_BUFFER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define GADC_GADC_CTRL__EN_BUFFER__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define GADC_GADC_CTRL__EN_BUFFER__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define GADC_GADC_CTRL__EN_BUFFER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define GADC_GADC_CTRL__EN_BUFFER__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field en_adc */ +/** + * @defgroup pmu_gadc_regs_core_en_adc_field en_adc_field + * @brief macros for field en_adc + * @details enable adc + * @{ + */ +#define GADC_GADC_CTRL__EN_ADC__SHIFT 25 +#define GADC_GADC_CTRL__EN_ADC__WIDTH 1 +#define GADC_GADC_CTRL__EN_ADC__MASK 0x02000000U +#define GADC_GADC_CTRL__EN_ADC__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define GADC_GADC_CTRL__EN_ADC__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define GADC_GADC_CTRL__EN_ADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define GADC_GADC_CTRL__EN_ADC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define GADC_GADC_CTRL__EN_ADC__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define GADC_GADC_CTRL__EN_ADC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define GADC_GADC_CTRL__EN_ADC__RESET_VALUE 0x00000001U +/** @} */ +#define GADC_GADC_CTRL__TYPE uint32_t +#define GADC_GADC_CTRL__READ 0x03ffffffU +#define GADC_GADC_CTRL__WRITE 0x03ffffffU +#define GADC_GADC_CTRL__PRESERVED 0x00000000U +#define GADC_GADC_CTRL__RESET_VALUE 0x03864733U + +#endif /* __GADC_GADC_CTRL_MACRO__ */ + +/** @} end of gadc_ctrl */ + +/* macros for BlueprintGlobalNameSpace::GADC_core_id */ +/** + * @defgroup pmu_gadc_regs_core_core_id core_id + * @brief Core ID definitions. + * @{ + */ +#ifndef __GADC_CORE_ID_MACRO__ +#define __GADC_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup pmu_gadc_regs_core_id_field id_field + * @brief macros for field id + * @details GADC in ASCII (General ADC) + * @{ + */ +#define GADC_CORE_ID__ID__SHIFT 0 +#define GADC_CORE_ID__ID__WIDTH 32 +#define GADC_CORE_ID__ID__MASK 0xffffffffU +#define GADC_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define GADC_CORE_ID__ID__RESET_VALUE 0x474144c3U +/** @} */ +#define GADC_CORE_ID__TYPE uint32_t +#define GADC_CORE_ID__READ 0xffffffffU +#define GADC_CORE_ID__PRESERVED 0x00000000U +#define GADC_CORE_ID__RESET_VALUE 0x474144c3U + +#endif /* __GADC_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of PMU_GADC_REGS_CORE */ +#endif /* __REG_PMU_GADC_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/pmu_pmuadc_regs_core_macro.h b/ATM33xx-5/include/reg/pmu_pmuadc_regs_core_macro.h new file mode 100644 index 0000000..870d2f9 --- /dev/null +++ b/ATM33xx-5/include/reg/pmu_pmuadc_regs_core_macro.h @@ -0,0 +1,1854 @@ +/* */ +/* File: pmu_pmuadc_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic pmu_pmuadc_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_PMU_PMUADC_REGS_CORE_H__ +#define __REG_PMU_PMUADC_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup PMU_PMUADC_REGS_CORE pmu_pmuadc_regs_core + * @ingroup AT_REG + * @brief pmu_pmuadc_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::PMUADC_reg0 */ +/** + * @defgroup pmu_pmuadc_regs_core_reg0 reg0 + * @brief reg0 pmuadc registers The order of the inputs is 5: Vharv 4: Vstore 3: Vbat 2: Vatb 1: VliIon 0: Vmax definitions. + * @{ + */ +#ifndef __PMUADC_REG0_MACRO__ +#define __PMUADC_REG0_MACRO__ + +/* macros for field settlingTime */ +/** + * @defgroup pmu_pmuadc_regs_core_settlingTime_field settlingTime_field + * @brief macros for field settlingTime + * @details settling time + * @{ + */ +#define PMUADC_REG0__SETTLINGTIME__SHIFT 0 +#define PMUADC_REG0__SETTLINGTIME__WIDTH 7 +#define PMUADC_REG0__SETTLINGTIME__MASK 0x0000007fU +#define PMUADC_REG0__SETTLINGTIME__READ(src) ((uint32_t)(src) & 0x0000007fU) +#define PMUADC_REG0__SETTLINGTIME__WRITE(src) ((uint32_t)(src) & 0x0000007fU) +#define PMUADC_REG0__SETTLINGTIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define PMUADC_REG0__SETTLINGTIME__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000007fU))) +#define PMUADC_REG0__SETTLINGTIME__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field inputSettlingTime */ +/** + * @defgroup pmu_pmuadc_regs_core_inputSettlingTime_field inputSettlingTime_field + * @brief macros for field inputSettlingTime + * @details settling time + * @{ + */ +#define PMUADC_REG0__INPUTSETTLINGTIME__SHIFT 7 +#define PMUADC_REG0__INPUTSETTLINGTIME__WIDTH 7 +#define PMUADC_REG0__INPUTSETTLINGTIME__MASK 0x00003f80U +#define PMUADC_REG0__INPUTSETTLINGTIME__READ(src) \ + (((uint32_t)(src)\ + & 0x00003f80U) >> 7) +#define PMUADC_REG0__INPUTSETTLINGTIME__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00003f80U) +#define PMUADC_REG0__INPUTSETTLINGTIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((uint32_t)(src) <<\ + 7) & 0x00003f80U) +#define PMUADC_REG0__INPUTSETTLINGTIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00003f80U))) +#define PMUADC_REG0__INPUTSETTLINGTIME__RESET_VALUE 0x00000009U +/** @} */ + +/* macros for field longSettlingTime */ +/** + * @defgroup pmu_pmuadc_regs_core_longSettlingTime_field longSettlingTime_field + * @brief macros for field longSettlingTime + * @details settling time + * @{ + */ +#define PMUADC_REG0__LONGSETTLINGTIME__SHIFT 14 +#define PMUADC_REG0__LONGSETTLINGTIME__WIDTH 7 +#define PMUADC_REG0__LONGSETTLINGTIME__MASK 0x001fc000U +#define PMUADC_REG0__LONGSETTLINGTIME__READ(src) \ + (((uint32_t)(src)\ + & 0x001fc000U) >> 14) +#define PMUADC_REG0__LONGSETTLINGTIME__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x001fc000U) +#define PMUADC_REG0__LONGSETTLINGTIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001fc000U) | (((uint32_t)(src) <<\ + 14) & 0x001fc000U) +#define PMUADC_REG0__LONGSETTLINGTIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x001fc000U))) +#define PMUADC_REG0__LONGSETTLINGTIME__RESET_VALUE 0x0000000eU +/** @} */ + +/* macros for field longInputSettlingTime */ +/** + * @defgroup pmu_pmuadc_regs_core_longInputSettlingTime_field longInputSettlingTime_field + * @brief macros for field longInputSettlingTime + * @details settling time + * @{ + */ +#define PMUADC_REG0__LONGINPUTSETTLINGTIME__SHIFT 21 +#define PMUADC_REG0__LONGINPUTSETTLINGTIME__WIDTH 7 +#define PMUADC_REG0__LONGINPUTSETTLINGTIME__MASK 0x0fe00000U +#define PMUADC_REG0__LONGINPUTSETTLINGTIME__READ(src) \ + (((uint32_t)(src)\ + & 0x0fe00000U) >> 21) +#define PMUADC_REG0__LONGINPUTSETTLINGTIME__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x0fe00000U) +#define PMUADC_REG0__LONGINPUTSETTLINGTIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fe00000U) | (((uint32_t)(src) <<\ + 21) & 0x0fe00000U) +#define PMUADC_REG0__LONGINPUTSETTLINGTIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x0fe00000U))) +#define PMUADC_REG0__LONGINPUTSETTLINGTIME__RESET_VALUE 0x00000022U +/** @} */ + +/* macros for field clkFixed */ +/** + * @defgroup pmu_pmuadc_regs_core_clkFixed_field clkFixed_field + * @brief macros for field clkFixed + * @details clock fixed time + * @{ + */ +#define PMUADC_REG0__CLKFIXED__SHIFT 28 +#define PMUADC_REG0__CLKFIXED__WIDTH 2 +#define PMUADC_REG0__CLKFIXED__MASK 0x30000000U +#define PMUADC_REG0__CLKFIXED__READ(src) \ + (((uint32_t)(src)\ + & 0x30000000U) >> 28) +#define PMUADC_REG0__CLKFIXED__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x30000000U) +#define PMUADC_REG0__CLKFIXED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x30000000U) | (((uint32_t)(src) <<\ + 28) & 0x30000000U) +#define PMUADC_REG0__CLKFIXED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x30000000U))) +#define PMUADC_REG0__CLKFIXED__RESET_VALUE 0x00000001U +/** @} */ +#define PMUADC_REG0__TYPE uint32_t +#define PMUADC_REG0__READ 0x3fffffffU +#define PMUADC_REG0__WRITE 0x3fffffffU +#define PMUADC_REG0__PRESERVED 0x00000000U +#define PMUADC_REG0__RESET_VALUE 0x14438487U + +#endif /* __PMUADC_REG0_MACRO__ */ + +/** @} end of reg0 */ + +/* macros for BlueprintGlobalNameSpace::PMUADC_main1 */ +/** + * @defgroup pmu_pmuadc_regs_core_main1 main1 + * @brief reg registers definitions. + * @{ + */ +#ifndef __PMUADC_MAIN1_MACRO__ +#define __PMUADC_MAIN1_MACRO__ + +/* macros for field clkUnitDel1 */ +/** + * @defgroup pmu_pmuadc_regs_core_clkUnitDel1_field clkUnitDel1_field + * @brief macros for field clkUnitDel1 + * @details delay used in the clock fixed time + * @{ + */ +#define PMUADC_MAIN1__CLKUNITDEL1__SHIFT 0 +#define PMUADC_MAIN1__CLKUNITDEL1__WIDTH 3 +#define PMUADC_MAIN1__CLKUNITDEL1__MASK 0x00000007U +#define PMUADC_MAIN1__CLKUNITDEL1__READ(src) ((uint32_t)(src) & 0x00000007U) +#define PMUADC_MAIN1__CLKUNITDEL1__WRITE(src) ((uint32_t)(src) & 0x00000007U) +#define PMUADC_MAIN1__CLKUNITDEL1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define PMUADC_MAIN1__CLKUNITDEL1__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define PMUADC_MAIN1__CLKUNITDEL1__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clkUnitDel2 */ +/** + * @defgroup pmu_pmuadc_regs_core_clkUnitDel2_field clkUnitDel2_field + * @brief macros for field clkUnitDel2 + * @details delay used in the clock extra high time + * @{ + */ +#define PMUADC_MAIN1__CLKUNITDEL2__SHIFT 3 +#define PMUADC_MAIN1__CLKUNITDEL2__WIDTH 5 +#define PMUADC_MAIN1__CLKUNITDEL2__MASK 0x000000f8U +#define PMUADC_MAIN1__CLKUNITDEL2__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f8U) >> 3) +#define PMUADC_MAIN1__CLKUNITDEL2__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x000000f8U) +#define PMUADC_MAIN1__CLKUNITDEL2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f8U) | (((uint32_t)(src) <<\ + 3) & 0x000000f8U) +#define PMUADC_MAIN1__CLKUNITDEL2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x000000f8U))) +#define PMUADC_MAIN1__CLKUNITDEL2__RESET_VALUE 0x0000000fU +/** @} */ + +/* macros for field clockTest */ +/** + * @defgroup pmu_pmuadc_regs_core_clockTest_field clockTest_field + * @brief macros for field clockTest + * @details connects the clock to the analog bus + * @{ + */ +#define PMUADC_MAIN1__CLOCKTEST__SHIFT 8 +#define PMUADC_MAIN1__CLOCKTEST__WIDTH 1 +#define PMUADC_MAIN1__CLOCKTEST__MASK 0x00000100U +#define PMUADC_MAIN1__CLOCKTEST__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define PMUADC_MAIN1__CLOCKTEST__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define PMUADC_MAIN1__CLOCKTEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define PMUADC_MAIN1__CLOCKTEST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define PMUADC_MAIN1__CLOCKTEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PMUADC_MAIN1__CLOCKTEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PMUADC_MAIN1__CLOCKTEST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field measEnable_ovr */ +/** + * @defgroup pmu_pmuadc_regs_core_measEnable_ovr_field measEnable_ovr_field + * @brief macros for field measEnable_ovr + * @details Enable measurement override + * @{ + */ +#define PMUADC_MAIN1__MEASENABLE_OVR__SHIFT 9 +#define PMUADC_MAIN1__MEASENABLE_OVR__WIDTH 1 +#define PMUADC_MAIN1__MEASENABLE_OVR__MASK 0x00000200U +#define PMUADC_MAIN1__MEASENABLE_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PMUADC_MAIN1__MEASENABLE_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define PMUADC_MAIN1__MEASENABLE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define PMUADC_MAIN1__MEASENABLE_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define PMUADC_MAIN1__MEASENABLE_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PMUADC_MAIN1__MEASENABLE_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PMUADC_MAIN1__MEASENABLE_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field measEnable_ovrVal */ +/** + * @defgroup pmu_pmuadc_regs_core_measEnable_ovrVal_field measEnable_ovrVal_field + * @brief macros for field measEnable_ovrVal + * @details Enable measurement override values + * @{ + */ +#define PMUADC_MAIN1__MEASENABLE_OVRVAL__SHIFT 10 +#define PMUADC_MAIN1__MEASENABLE_OVRVAL__WIDTH 6 +#define PMUADC_MAIN1__MEASENABLE_OVRVAL__MASK 0x0000fc00U +#define PMUADC_MAIN1__MEASENABLE_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x0000fc00U) >> 10) +#define PMUADC_MAIN1__MEASENABLE_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x0000fc00U) +#define PMUADC_MAIN1__MEASENABLE_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fc00U) | (((uint32_t)(src) <<\ + 10) & 0x0000fc00U) +#define PMUADC_MAIN1__MEASENABLE_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x0000fc00U))) +#define PMUADC_MAIN1__MEASENABLE_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field freeze */ +/** + * @defgroup pmu_pmuadc_regs_core_freeze_field freeze_field + * @brief macros for field freeze + * @details Freeze pmuadc operation + * @{ + */ +#define PMUADC_MAIN1__FREEZE__SHIFT 16 +#define PMUADC_MAIN1__FREEZE__WIDTH 1 +#define PMUADC_MAIN1__FREEZE__MASK 0x00010000U +#define PMUADC_MAIN1__FREEZE__READ(src) (((uint32_t)(src) & 0x00010000U) >> 16) +#define PMUADC_MAIN1__FREEZE__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define PMUADC_MAIN1__FREEZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define PMUADC_MAIN1__FREEZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define PMUADC_MAIN1__FREEZE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PMUADC_MAIN1__FREEZE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PMUADC_MAIN1__FREEZE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field gate32K */ +/** + * @defgroup pmu_pmuadc_regs_core_gate32K_field gate32K_field + * @brief macros for field gate32K + * @details 32K input clock gating + * @{ + */ +#define PMUADC_MAIN1__GATE32K__SHIFT 17 +#define PMUADC_MAIN1__GATE32K__WIDTH 1 +#define PMUADC_MAIN1__GATE32K__MASK 0x00020000U +#define PMUADC_MAIN1__GATE32K__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define PMUADC_MAIN1__GATE32K__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define PMUADC_MAIN1__GATE32K__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define PMUADC_MAIN1__GATE32K__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define PMUADC_MAIN1__GATE32K__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define PMUADC_MAIN1__GATE32K__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define PMUADC_MAIN1__GATE32K__RESET_VALUE 0x00000000U +/** @} */ +#define PMUADC_MAIN1__TYPE uint32_t +#define PMUADC_MAIN1__READ 0x0003ffffU +#define PMUADC_MAIN1__WRITE 0x0003ffffU +#define PMUADC_MAIN1__PRESERVED 0x00000000U +#define PMUADC_MAIN1__RESET_VALUE 0x00000079U + +#endif /* __PMUADC_MAIN1_MACRO__ */ + +/** @} end of main1 */ + +/* macros for BlueprintGlobalNameSpace::PMUADC_pmuadc_ctrlr */ +/** + * @defgroup pmu_pmuadc_regs_core_pmuadc_ctrlr pmuadc_ctrlr + * @brief pmuadc controller registers definitions. + * @{ + */ +#ifndef __PMUADC_PMUADC_CTRLR_MACRO__ +#define __PMUADC_PMUADC_CTRLR_MACRO__ + +/* macros for field measEnableSet_ovr */ +/** + * @defgroup pmu_pmuadc_regs_core_measEnableSet_ovr_field measEnableSet_ovr_field + * @brief macros for field measEnableSet_ovr + * @details Enable measurement override for each channel + * @{ + */ +#define PMUADC_PMUADC_CTRLR__MEASENABLESET_OVR__SHIFT 0 +#define PMUADC_PMUADC_CTRLR__MEASENABLESET_OVR__WIDTH 6 +#define PMUADC_PMUADC_CTRLR__MEASENABLESET_OVR__MASK 0x0000003fU +#define PMUADC_PMUADC_CTRLR__MEASENABLESET_OVR__READ(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define PMUADC_PMUADC_CTRLR__MEASENABLESET_OVR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define PMUADC_PMUADC_CTRLR__MEASENABLESET_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define PMUADC_PMUADC_CTRLR__MEASENABLESET_OVR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define PMUADC_PMUADC_CTRLR__MEASENABLESET_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field measEnableSet_ovrVal */ +/** + * @defgroup pmu_pmuadc_regs_core_measEnableSet_ovrVal_field measEnableSet_ovrVal_field + * @brief macros for field measEnableSet_ovrVal + * @details Enable measurement override values + * @{ + */ +#define PMUADC_PMUADC_CTRLR__MEASENABLESET_OVRVAL__SHIFT 6 +#define PMUADC_PMUADC_CTRLR__MEASENABLESET_OVRVAL__WIDTH 6 +#define PMUADC_PMUADC_CTRLR__MEASENABLESET_OVRVAL__MASK 0x00000fc0U +#define PMUADC_PMUADC_CTRLR__MEASENABLESET_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000fc0U) >> 6) +#define PMUADC_PMUADC_CTRLR__MEASENABLESET_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000fc0U) +#define PMUADC_PMUADC_CTRLR__MEASENABLESET_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((uint32_t)(src) <<\ + 6) & 0x00000fc0U) +#define PMUADC_PMUADC_CTRLR__MEASENABLESET_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000fc0U))) +#define PMUADC_PMUADC_CTRLR__MEASENABLESET_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field lowVmax_ovr */ +/** + * @defgroup pmu_pmuadc_regs_core_lowVmax_ovr_field lowVmax_ovr_field + * @brief macros for field lowVmax_ovr + * @details Override lowVmax control + * @{ + */ +#define PMUADC_PMUADC_CTRLR__LOWVMAX_OVR__SHIFT 12 +#define PMUADC_PMUADC_CTRLR__LOWVMAX_OVR__WIDTH 1 +#define PMUADC_PMUADC_CTRLR__LOWVMAX_OVR__MASK 0x00001000U +#define PMUADC_PMUADC_CTRLR__LOWVMAX_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define PMUADC_PMUADC_CTRLR__LOWVMAX_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define PMUADC_PMUADC_CTRLR__LOWVMAX_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define PMUADC_PMUADC_CTRLR__LOWVMAX_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define PMUADC_PMUADC_CTRLR__LOWVMAX_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define PMUADC_PMUADC_CTRLR__LOWVMAX_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define PMUADC_PMUADC_CTRLR__LOWVMAX_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field lowVmax_ovrVal */ +/** + * @defgroup pmu_pmuadc_regs_core_lowVmax_ovrVal_field lowVmax_ovrVal_field + * @brief macros for field lowVmax_ovrVal + * @details Override value for lowVmax + * @{ + */ +#define PMUADC_PMUADC_CTRLR__LOWVMAX_OVRVAL__SHIFT 13 +#define PMUADC_PMUADC_CTRLR__LOWVMAX_OVRVAL__WIDTH 1 +#define PMUADC_PMUADC_CTRLR__LOWVMAX_OVRVAL__MASK 0x00002000U +#define PMUADC_PMUADC_CTRLR__LOWVMAX_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define PMUADC_PMUADC_CTRLR__LOWVMAX_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define PMUADC_PMUADC_CTRLR__LOWVMAX_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define PMUADC_PMUADC_CTRLR__LOWVMAX_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define PMUADC_PMUADC_CTRLR__LOWVMAX_OVRVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define PMUADC_PMUADC_CTRLR__LOWVMAX_OVRVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define PMUADC_PMUADC_CTRLR__LOWVMAX_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field alwaysFinish */ +/** + * @defgroup pmu_pmuadc_regs_core_alwaysFinish_field alwaysFinish_field + * @brief macros for field alwaysFinish + * @details Extend clock cycle for slow processing + * @{ + */ +#define PMUADC_PMUADC_CTRLR__ALWAYSFINISH__SHIFT 14 +#define PMUADC_PMUADC_CTRLR__ALWAYSFINISH__WIDTH 1 +#define PMUADC_PMUADC_CTRLR__ALWAYSFINISH__MASK 0x00004000U +#define PMUADC_PMUADC_CTRLR__ALWAYSFINISH__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PMUADC_PMUADC_CTRLR__ALWAYSFINISH__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define PMUADC_PMUADC_CTRLR__ALWAYSFINISH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define PMUADC_PMUADC_CTRLR__ALWAYSFINISH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define PMUADC_PMUADC_CTRLR__ALWAYSFINISH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PMUADC_PMUADC_CTRLR__ALWAYSFINISH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PMUADC_PMUADC_CTRLR__ALWAYSFINISH__RESET_VALUE 0x00000001U +/** @} */ +#define PMUADC_PMUADC_CTRLR__TYPE uint32_t +#define PMUADC_PMUADC_CTRLR__READ 0x00007fffU +#define PMUADC_PMUADC_CTRLR__WRITE 0x00007fffU +#define PMUADC_PMUADC_CTRLR__PRESERVED 0x00000000U +#define PMUADC_PMUADC_CTRLR__RESET_VALUE 0x00004000U + +#endif /* __PMUADC_PMUADC_CTRLR_MACRO__ */ + +/** @} end of pmuadc_ctrlr */ + +/* macros for BlueprintGlobalNameSpace::PMUADC_meas_period0 */ +/** + * @defgroup pmu_pmuadc_regs_core_meas_period0 meas_period0 + * @brief pmuadc measurement period setting registers definitions. + * @{ + */ +#ifndef __PMUADC_MEAS_PERIOD0_MACRO__ +#define __PMUADC_MEAS_PERIOD0_MACRO__ + +/* macros for field x32pstate_VMAX */ +/** + * @defgroup pmu_pmuadc_regs_core_x32pstate_VMAX_field x32pstate_VMAX_field + * @brief macros for field x32pstate_VMAX + * @details VMAX measurement period setting, period = 31.25uS*2^(X+1) + * @{ + */ +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VMAX__SHIFT 0 +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VMAX__WIDTH 8 +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VMAX__MASK 0x000000ffU +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VMAX__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VMAX__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VMAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VMAX__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VMAX__RESET_VALUE 0x0000000bU +/** @} */ + +/* macros for field x32pstate_VLI */ +/** + * @defgroup pmu_pmuadc_regs_core_x32pstate_VLI_field x32pstate_VLI_field + * @brief macros for field x32pstate_VLI + * @details VLI measurement period setting, period = 31.25uS*2^(X+1) + * @{ + */ +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VLI__SHIFT 8 +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VLI__WIDTH 8 +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VLI__MASK 0x0000ff00U +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VLI__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VLI__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VLI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VLI__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VLI__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field x32pstate_VATB */ +/** + * @defgroup pmu_pmuadc_regs_core_x32pstate_VATB_field x32pstate_VATB_field + * @brief macros for field x32pstate_VATB + * @details VATB measurement period setting, no measurement in default when set to larger than 16 + * @{ + */ +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VATB__SHIFT 16 +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VATB__WIDTH 8 +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VATB__MASK 0x00ff0000U +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VATB__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VATB__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VATB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VATB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VATB__RESET_VALUE 0x000000ffU +/** @} */ + +/* macros for field x32pstate_VBAT_0 */ +/** + * @defgroup pmu_pmuadc_regs_core_x32pstate_VBAT_0_field x32pstate_VBAT_0_field + * @brief macros for field x32pstate_VBAT_0 + * @details VBAT measurement period setting for active state, period = 31.25uS*2^(X+1) + * @{ + */ +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VBAT_0__SHIFT 24 +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VBAT_0__WIDTH 8 +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VBAT_0__MASK 0xff000000U +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VBAT_0__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VBAT_0__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VBAT_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VBAT_0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define PMUADC_MEAS_PERIOD0__X32PSTATE_VBAT_0__RESET_VALUE 0x00000001U +/** @} */ +#define PMUADC_MEAS_PERIOD0__TYPE uint32_t +#define PMUADC_MEAS_PERIOD0__READ 0xffffffffU +#define PMUADC_MEAS_PERIOD0__WRITE 0xffffffffU +#define PMUADC_MEAS_PERIOD0__PRESERVED 0x00000000U +#define PMUADC_MEAS_PERIOD0__RESET_VALUE 0x01ff080bU + +#endif /* __PMUADC_MEAS_PERIOD0_MACRO__ */ + +/** @} end of meas_period0 */ + +/* macros for BlueprintGlobalNameSpace::PMUADC_meas_period1 */ +/** + * @defgroup pmu_pmuadc_regs_core_meas_period1 meas_period1 + * @brief pmuadc measurement period setting registers definitions. + * @{ + */ +#ifndef __PMUADC_MEAS_PERIOD1_MACRO__ +#define __PMUADC_MEAS_PERIOD1_MACRO__ + +/* macros for field x32pstate_VBAT_1 */ +/** + * @defgroup pmu_pmuadc_regs_core_x32pstate_VBAT_1_field x32pstate_VBAT_1_field + * @brief macros for field x32pstate_VBAT_1 + * @details VBAT measurement period setting for non-active state, period = 31.25uS*2^(X+1) + * @{ + */ +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VBAT_1__SHIFT 0 +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VBAT_1__WIDTH 8 +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VBAT_1__MASK 0x000000ffU +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VBAT_1__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VBAT_1__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VBAT_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VBAT_1__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VBAT_1__RESET_VALUE 0x0000000dU +/** @} */ + +/* macros for field x32pstate_VSTO_0 */ +/** + * @defgroup pmu_pmuadc_regs_core_x32pstate_VSTO_0_field x32pstate_VSTO_0_field + * @brief macros for field x32pstate_VSTO_0 + * @details VSTO measurement period setting for active state, period = 31.25uS*2^(X+1) + * @{ + */ +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VSTO_0__SHIFT 8 +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VSTO_0__WIDTH 8 +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VSTO_0__MASK 0x0000ff00U +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VSTO_0__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VSTO_0__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VSTO_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VSTO_0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VSTO_0__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field x32pstate_VSTO_1 */ +/** + * @defgroup pmu_pmuadc_regs_core_x32pstate_VSTO_1_field x32pstate_VSTO_1_field + * @brief macros for field x32pstate_VSTO_1 + * @details VSTO measurement period setting for non-active state, period = 31.25uS*2^(X+1) + * @{ + */ +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VSTO_1__SHIFT 16 +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VSTO_1__WIDTH 8 +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VSTO_1__MASK 0x00ff0000U +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VSTO_1__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VSTO_1__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00ff0000U) +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VSTO_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x00ff0000U) +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VSTO_1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VSTO_1__RESET_VALUE 0x0000000bU +/** @} */ + +/* macros for field x32pstate_VHARV */ +/** + * @defgroup pmu_pmuadc_regs_core_x32pstate_VHARV_field x32pstate_VHARV_field + * @brief macros for field x32pstate_VHARV + * @details VHARV measurement period setting for active state, period = 31.25uS*2^(X+1) + * @{ + */ +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VHARV__SHIFT 24 +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VHARV__WIDTH 8 +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VHARV__MASK 0xff000000U +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VHARV__READ(src) \ + (((uint32_t)(src)\ + & 0xff000000U) >> 24) +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VHARV__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0xff000000U) +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VHARV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((uint32_t)(src) <<\ + 24) & 0xff000000U) +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VHARV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0xff000000U))) +#define PMUADC_MEAS_PERIOD1__X32PSTATE_VHARV__RESET_VALUE 0x00000008U +/** @} */ +#define PMUADC_MEAS_PERIOD1__TYPE uint32_t +#define PMUADC_MEAS_PERIOD1__READ 0xffffffffU +#define PMUADC_MEAS_PERIOD1__WRITE 0xffffffffU +#define PMUADC_MEAS_PERIOD1__PRESERVED 0x00000000U +#define PMUADC_MEAS_PERIOD1__RESET_VALUE 0x080b040dU + +#endif /* __PMUADC_MEAS_PERIOD1_MACRO__ */ + +/** @} end of meas_period1 */ + +/* macros for BlueprintGlobalNameSpace::PMUADC_cmpout_param_1 */ +/** + * @defgroup pmu_pmuadc_regs_core_cmpout_param_1 cmpout_param_1 + * @brief pmuadc reference parameters for swreg mode definitions. + * @{ + */ +#ifndef __PMUADC_CMPOUT_PARAM_1_MACRO__ +#define __PMUADC_CMPOUT_PARAM_1_MACRO__ + +/* macros for field c0_bit */ +/** + * @defgroup pmu_pmuadc_regs_core_c0_bit_field c0_bit_field + * @brief macros for field c0_bit + * @details c0 = c0_bit*50mV + * @{ + */ +#define PMUADC_CMPOUT_PARAM_1__C0_BIT__SHIFT 0 +#define PMUADC_CMPOUT_PARAM_1__C0_BIT__WIDTH 4 +#define PMUADC_CMPOUT_PARAM_1__C0_BIT__MASK 0x0000000fU +#define PMUADC_CMPOUT_PARAM_1__C0_BIT__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define PMUADC_CMPOUT_PARAM_1__C0_BIT__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define PMUADC_CMPOUT_PARAM_1__C0_BIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define PMUADC_CMPOUT_PARAM_1__C0_BIT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define PMUADC_CMPOUT_PARAM_1__C0_BIT__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field c1_bit */ +/** + * @defgroup pmu_pmuadc_regs_core_c1_bit_field c1_bit_field + * @brief macros for field c1_bit + * @details c1 = 1+c1_bit/16 + * @{ + */ +#define PMUADC_CMPOUT_PARAM_1__C1_BIT__SHIFT 4 +#define PMUADC_CMPOUT_PARAM_1__C1_BIT__WIDTH 4 +#define PMUADC_CMPOUT_PARAM_1__C1_BIT__MASK 0x000000f0U +#define PMUADC_CMPOUT_PARAM_1__C1_BIT__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define PMUADC_CMPOUT_PARAM_1__C1_BIT__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x000000f0U) +#define PMUADC_CMPOUT_PARAM_1__C1_BIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define PMUADC_CMPOUT_PARAM_1__C1_BIT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define PMUADC_CMPOUT_PARAM_1__C1_BIT__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field c1bo_bit */ +/** + * @defgroup pmu_pmuadc_regs_core_c1bo_bit_field c1bo_bit_field + * @brief macros for field c1bo_bit + * @details c1bo = 1+c1bo_bit/16 + * @{ + */ +#define PMUADC_CMPOUT_PARAM_1__C1BO_BIT__SHIFT 8 +#define PMUADC_CMPOUT_PARAM_1__C1BO_BIT__WIDTH 4 +#define PMUADC_CMPOUT_PARAM_1__C1BO_BIT__MASK 0x00000f00U +#define PMUADC_CMPOUT_PARAM_1__C1BO_BIT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000f00U) >> 8) +#define PMUADC_CMPOUT_PARAM_1__C1BO_BIT__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000f00U) +#define PMUADC_CMPOUT_PARAM_1__C1BO_BIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((uint32_t)(src) <<\ + 8) & 0x00000f00U) +#define PMUADC_CMPOUT_PARAM_1__C1BO_BIT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000f00U))) +#define PMUADC_CMPOUT_PARAM_1__C1BO_BIT__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field c2_bit */ +/** + * @defgroup pmu_pmuadc_regs_core_c2_bit_field c2_bit_field + * @brief macros for field c2_bit + * @details c2 = (11+c2_bit)/16 + * @{ + */ +#define PMUADC_CMPOUT_PARAM_1__C2_BIT__SHIFT 12 +#define PMUADC_CMPOUT_PARAM_1__C2_BIT__WIDTH 2 +#define PMUADC_CMPOUT_PARAM_1__C2_BIT__MASK 0x00003000U +#define PMUADC_CMPOUT_PARAM_1__C2_BIT__READ(src) \ + (((uint32_t)(src)\ + & 0x00003000U) >> 12) +#define PMUADC_CMPOUT_PARAM_1__C2_BIT__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00003000U) +#define PMUADC_CMPOUT_PARAM_1__C2_BIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((uint32_t)(src) <<\ + 12) & 0x00003000U) +#define PMUADC_CMPOUT_PARAM_1__C2_BIT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00003000U))) +#define PMUADC_CMPOUT_PARAM_1__C2_BIT__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field c3_bit */ +/** + * @defgroup pmu_pmuadc_regs_core_c3_bit_field c3_bit_field + * @brief macros for field c3_bit + * @details c3 = (8+c3_bit)*62.5 + * @{ + */ +#define PMUADC_CMPOUT_PARAM_1__C3_BIT__SHIFT 14 +#define PMUADC_CMPOUT_PARAM_1__C3_BIT__WIDTH 3 +#define PMUADC_CMPOUT_PARAM_1__C3_BIT__MASK 0x0001c000U +#define PMUADC_CMPOUT_PARAM_1__C3_BIT__READ(src) \ + (((uint32_t)(src)\ + & 0x0001c000U) >> 14) +#define PMUADC_CMPOUT_PARAM_1__C3_BIT__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0001c000U) +#define PMUADC_CMPOUT_PARAM_1__C3_BIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((uint32_t)(src) <<\ + 14) & 0x0001c000U) +#define PMUADC_CMPOUT_PARAM_1__C3_BIT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0001c000U))) +#define PMUADC_CMPOUT_PARAM_1__C3_BIT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cbyavdd */ +/** + * @defgroup pmu_pmuadc_regs_core_cbyavdd_field cbyavdd_field + * @brief macros for field cbyavdd + * @details Bypass reference voltage + * @{ + */ +#define PMUADC_CMPOUT_PARAM_1__CBYAVDD__SHIFT 17 +#define PMUADC_CMPOUT_PARAM_1__CBYAVDD__WIDTH 2 +#define PMUADC_CMPOUT_PARAM_1__CBYAVDD__MASK 0x00060000U +#define PMUADC_CMPOUT_PARAM_1__CBYAVDD__READ(src) \ + (((uint32_t)(src)\ + & 0x00060000U) >> 17) +#define PMUADC_CMPOUT_PARAM_1__CBYAVDD__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00060000U) +#define PMUADC_CMPOUT_PARAM_1__CBYAVDD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00060000U) | (((uint32_t)(src) <<\ + 17) & 0x00060000U) +#define PMUADC_CMPOUT_PARAM_1__CBYAVDD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00060000U))) +#define PMUADC_CMPOUT_PARAM_1__CBYAVDD__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field cbydvdd */ +/** + * @defgroup pmu_pmuadc_regs_core_cbydvdd_field cbydvdd_field + * @brief macros for field cbydvdd + * @details Bypass reference voltage + * @{ + */ +#define PMUADC_CMPOUT_PARAM_1__CBYDVDD__SHIFT 19 +#define PMUADC_CMPOUT_PARAM_1__CBYDVDD__WIDTH 2 +#define PMUADC_CMPOUT_PARAM_1__CBYDVDD__MASK 0x00180000U +#define PMUADC_CMPOUT_PARAM_1__CBYDVDD__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define PMUADC_CMPOUT_PARAM_1__CBYDVDD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define PMUADC_CMPOUT_PARAM_1__CBYDVDD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define PMUADC_CMPOUT_PARAM_1__CBYDVDD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define PMUADC_CMPOUT_PARAM_1__CBYDVDD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cbyvddio */ +/** + * @defgroup pmu_pmuadc_regs_core_cbyvddio_field cbyvddio_field + * @brief macros for field cbyvddio + * @details Bypass reference voltage + * @{ + */ +#define PMUADC_CMPOUT_PARAM_1__CBYVDDIO__SHIFT 21 +#define PMUADC_CMPOUT_PARAM_1__CBYVDDIO__WIDTH 2 +#define PMUADC_CMPOUT_PARAM_1__CBYVDDIO__MASK 0x00600000U +#define PMUADC_CMPOUT_PARAM_1__CBYVDDIO__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define PMUADC_CMPOUT_PARAM_1__CBYVDDIO__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define PMUADC_CMPOUT_PARAM_1__CBYVDDIO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define PMUADC_CMPOUT_PARAM_1__CBYVDDIO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define PMUADC_CMPOUT_PARAM_1__CBYVDDIO__RESET_VALUE 0x00000001U +/** @} */ +#define PMUADC_CMPOUT_PARAM_1__TYPE uint32_t +#define PMUADC_CMPOUT_PARAM_1__READ 0x007fffffU +#define PMUADC_CMPOUT_PARAM_1__WRITE 0x007fffffU +#define PMUADC_CMPOUT_PARAM_1__PRESERVED 0x00000000U +#define PMUADC_CMPOUT_PARAM_1__RESET_VALUE 0x00221881U + +#endif /* __PMUADC_CMPOUT_PARAM_1_MACRO__ */ + +/** @} end of cmpout_param_1 */ + +/* macros for BlueprintGlobalNameSpace::PMUADC_cmpout_param_2 */ +/** + * @defgroup pmu_pmuadc_regs_core_cmpout_param_2 cmpout_param_2 + * @brief pmuadc reference parameter for comparator output definitions. + * @{ + */ +#ifndef __PMUADC_CMPOUT_PARAM_2_MACRO__ +#define __PMUADC_CMPOUT_PARAM_2_MACRO__ + +/* macros for field ctr_VrefstoGoodToStart */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_VrefstoGoodToStart_field ctr_VrefstoGoodToStart_field + * @brief macros for field ctr_VrefstoGoodToStart + * @details Compares Vstore with VrefstoGoodToStart + * @{ + */ +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFSTOGOODTOSTART__SHIFT 0 +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFSTOGOODTOSTART__WIDTH 2 +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFSTOGOODTOSTART__MASK 0x00000003U +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFSTOGOODTOSTART__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFSTOGOODTOSTART__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFSTOGOODTOSTART__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFSTOGOODTOSTART__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFSTOGOODTOSTART__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ctr_vbattovrvoltage */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_vbattovrvoltage_field ctr_vbattovrvoltage_field + * @brief macros for field ctr_vbattovrvoltage + * @details Compares Vbat with VrefBATovrvoltage + * @{ + */ +#define PMUADC_CMPOUT_PARAM_2__CTR_VBATTOVRVOLTAGE__SHIFT 7 +#define PMUADC_CMPOUT_PARAM_2__CTR_VBATTOVRVOLTAGE__WIDTH 7 +#define PMUADC_CMPOUT_PARAM_2__CTR_VBATTOVRVOLTAGE__MASK 0x00003f80U +#define PMUADC_CMPOUT_PARAM_2__CTR_VBATTOVRVOLTAGE__READ(src) \ + (((uint32_t)(src)\ + & 0x00003f80U) >> 7) +#define PMUADC_CMPOUT_PARAM_2__CTR_VBATTOVRVOLTAGE__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00003f80U) +#define PMUADC_CMPOUT_PARAM_2__CTR_VBATTOVRVOLTAGE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((uint32_t)(src) <<\ + 7) & 0x00003f80U) +#define PMUADC_CMPOUT_PARAM_2__CTR_VBATTOVRVOLTAGE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00003f80U))) +#define PMUADC_CMPOUT_PARAM_2__CTR_VBATTOVRVOLTAGE__RESET_VALUE 0x0000005cU +/** @} */ + +/* macros for field ctr_VrefVSTObrownOut */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_VrefVSTObrownOut_field ctr_VrefVSTObrownOut_field + * @brief macros for field ctr_VrefVSTObrownOut + * @details Comares Vstore with VrefVSTOBrownOut + * @{ + */ +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVSTOBROWNOUT__SHIFT 14 +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVSTOBROWNOUT__WIDTH 5 +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVSTOBROWNOUT__MASK 0x0007c000U +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVSTOBROWNOUT__READ(src) \ + (((uint32_t)(src)\ + & 0x0007c000U) >> 14) +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVSTOBROWNOUT__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0007c000U) +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVSTOBROWNOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007c000U) | (((uint32_t)(src) <<\ + 14) & 0x0007c000U) +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVSTOBROWNOUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0007c000U))) +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVSTOBROWNOUT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_VrefVSTOovrvoltage */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_VrefVSTOovrvoltage_field ctr_VrefVSTOovrvoltage_field + * @brief macros for field ctr_VrefVSTOovrvoltage + * @details Compares Vstore with VrefVSTOovrvoltage + * @{ + */ +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVSTOOVRVOLTAGE__SHIFT 19 +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVSTOOVRVOLTAGE__WIDTH 5 +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVSTOOVRVOLTAGE__MASK 0x00f80000U +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVSTOOVRVOLTAGE__READ(src) \ + (((uint32_t)(src)\ + & 0x00f80000U) >> 19) +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVSTOOVRVOLTAGE__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00f80000U) +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVSTOOVRVOLTAGE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f80000U) | (((uint32_t)(src) <<\ + 19) & 0x00f80000U) +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVSTOOVRVOLTAGE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00f80000U))) +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVSTOOVRVOLTAGE__RESET_VALUE 0x0000001eU +/** @} */ + +/* macros for field ctr_VrefVBATLIbypass */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_VrefVBATLIbypass_field ctr_VrefVBATLIbypass_field + * @brief macros for field ctr_VrefVBATLIbypass + * @details VBATLI level at which to bypass VBATLI to VBATT, 3.25V to 3.4V in 50mV steps + * @{ + */ +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVBATLIBYPASS__SHIFT 24 +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVBATLIBYPASS__WIDTH 2 +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVBATLIBYPASS__MASK 0x03000000U +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVBATLIBYPASS__READ(src) \ + (((uint32_t)(src)\ + & 0x03000000U) >> 24) +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVBATLIBYPASS__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x03000000U) +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVBATLIBYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((uint32_t)(src) <<\ + 24) & 0x03000000U) +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVBATLIBYPASS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x03000000U))) +#define PMUADC_CMPOUT_PARAM_2__CTR_VREFVBATLIBYPASS__RESET_VALUE 0x00000001U +/** @} */ +#define PMUADC_CMPOUT_PARAM_2__TYPE uint32_t +#define PMUADC_CMPOUT_PARAM_2__READ 0x03ffff83U +#define PMUADC_CMPOUT_PARAM_2__WRITE 0x03ffff83U +#define PMUADC_CMPOUT_PARAM_2__PRESERVED 0x00000000U +#define PMUADC_CMPOUT_PARAM_2__RESET_VALUE 0x01f02e01U + +#endif /* __PMUADC_CMPOUT_PARAM_2_MACRO__ */ + +/** @} end of cmpout_param_2 */ + +/* macros for BlueprintGlobalNameSpace::PMUADC_cmpout_param_3 */ +/** + * @defgroup pmu_pmuadc_regs_core_cmpout_param_3 cmpout_param_3 + * @brief pmuadc reference parameter for comparator output definitions. + * @{ + */ +#ifndef __PMUADC_CMPOUT_PARAM_3_MACRO__ +#define __PMUADC_CMPOUT_PARAM_3_MACRO__ + +/* macros for field ctr_vbatgoodtoTX */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_vbatgoodtoTX_field ctr_vbatgoodtoTX_field + * @brief macros for field ctr_vbatgoodtoTX + * @details Good to TX with vbat + * @{ + */ +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATGOODTOTX__SHIFT 0 +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATGOODTOTX__WIDTH 3 +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATGOODTOTX__MASK 0x00000007U +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATGOODTOTX__READ(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATGOODTOTX__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATGOODTOTX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATGOODTOTX__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATGOODTOTX__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field ctr_vstogoodtoTX */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_vstogoodtoTX_field ctr_vstogoodtoTX_field + * @brief macros for field ctr_vstogoodtoTX + * @details Good to TX with vsto + * @{ + */ +#define PMUADC_CMPOUT_PARAM_3__CTR_VSTOGOODTOTX__SHIFT 3 +#define PMUADC_CMPOUT_PARAM_3__CTR_VSTOGOODTOTX__WIDTH 3 +#define PMUADC_CMPOUT_PARAM_3__CTR_VSTOGOODTOTX__MASK 0x00000038U +#define PMUADC_CMPOUT_PARAM_3__CTR_VSTOGOODTOTX__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define PMUADC_CMPOUT_PARAM_3__CTR_VSTOGOODTOTX__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define PMUADC_CMPOUT_PARAM_3__CTR_VSTOGOODTOTX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define PMUADC_CMPOUT_PARAM_3__CTR_VSTOGOODTOTX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define PMUADC_CMPOUT_PARAM_3__CTR_VSTOGOODTOTX__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field ctr_vbatgoodforcpu */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_vbatgoodforcpu_field ctr_vbatgoodforcpu_field + * @brief macros for field ctr_vbatgoodforcpu + * @details Good for cpu with vbat + * @{ + */ +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATGOODFORCPU__SHIFT 6 +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATGOODFORCPU__WIDTH 3 +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATGOODFORCPU__MASK 0x000001c0U +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATGOODFORCPU__READ(src) \ + (((uint32_t)(src)\ + & 0x000001c0U) >> 6) +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATGOODFORCPU__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000001c0U) +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATGOODFORCPU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((uint32_t)(src) <<\ + 6) & 0x000001c0U) +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATGOODFORCPU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000001c0U))) +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATGOODFORCPU__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field ctr_vstogoodforcpu */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_vstogoodforcpu_field ctr_vstogoodforcpu_field + * @brief macros for field ctr_vstogoodforcpu + * @details Good for cpu with vsto + * @{ + */ +#define PMUADC_CMPOUT_PARAM_3__CTR_VSTOGOODFORCPU__SHIFT 9 +#define PMUADC_CMPOUT_PARAM_3__CTR_VSTOGOODFORCPU__WIDTH 3 +#define PMUADC_CMPOUT_PARAM_3__CTR_VSTOGOODFORCPU__MASK 0x00000e00U +#define PMUADC_CMPOUT_PARAM_3__CTR_VSTOGOODFORCPU__READ(src) \ + (((uint32_t)(src)\ + & 0x00000e00U) >> 9) +#define PMUADC_CMPOUT_PARAM_3__CTR_VSTOGOODFORCPU__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000e00U) +#define PMUADC_CMPOUT_PARAM_3__CTR_VSTOGOODFORCPU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((uint32_t)(src) <<\ + 9) & 0x00000e00U) +#define PMUADC_CMPOUT_PARAM_3__CTR_VSTOGOODFORCPU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000e00U))) +#define PMUADC_CMPOUT_PARAM_3__CTR_VSTOGOODFORCPU__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field ctr_atb_compthreshold */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_atb_compthreshold_field ctr_atb_compthreshold_field + * @brief macros for field ctr_atb_compthreshold + * @details Compares ATB with reference voltage + * @{ + */ +#define PMUADC_CMPOUT_PARAM_3__CTR_ATB_COMPTHRESHOLD__SHIFT 12 +#define PMUADC_CMPOUT_PARAM_3__CTR_ATB_COMPTHRESHOLD__WIDTH 3 +#define PMUADC_CMPOUT_PARAM_3__CTR_ATB_COMPTHRESHOLD__MASK 0x00007000U +#define PMUADC_CMPOUT_PARAM_3__CTR_ATB_COMPTHRESHOLD__READ(src) \ + (((uint32_t)(src)\ + & 0x00007000U) >> 12) +#define PMUADC_CMPOUT_PARAM_3__CTR_ATB_COMPTHRESHOLD__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00007000U) +#define PMUADC_CMPOUT_PARAM_3__CTR_ATB_COMPTHRESHOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((uint32_t)(src) <<\ + 12) & 0x00007000U) +#define PMUADC_CMPOUT_PARAM_3__CTR_ATB_COMPTHRESHOLD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00007000U))) +#define PMUADC_CMPOUT_PARAM_3__CTR_ATB_COMPTHRESHOLD__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field c2socoff_bit */ +/** + * @defgroup pmu_pmuadc_regs_core_c2socoff_bit_field c2socoff_bit_field + * @brief macros for field c2socoff_bit + * @details vbat measure for soc off mode 1 + * @{ + */ +#define PMUADC_CMPOUT_PARAM_3__C2SOCOFF_BIT__SHIFT 15 +#define PMUADC_CMPOUT_PARAM_3__C2SOCOFF_BIT__WIDTH 2 +#define PMUADC_CMPOUT_PARAM_3__C2SOCOFF_BIT__MASK 0x00018000U +#define PMUADC_CMPOUT_PARAM_3__C2SOCOFF_BIT__READ(src) \ + (((uint32_t)(src)\ + & 0x00018000U) >> 15) +#define PMUADC_CMPOUT_PARAM_3__C2SOCOFF_BIT__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00018000U) +#define PMUADC_CMPOUT_PARAM_3__C2SOCOFF_BIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00018000U) | (((uint32_t)(src) <<\ + 15) & 0x00018000U) +#define PMUADC_CMPOUT_PARAM_3__C2SOCOFF_BIT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00018000U))) +#define PMUADC_CMPOUT_PARAM_3__C2SOCOFF_BIT__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field ctr_vbatsocoff2 */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_vbatsocoff2_field ctr_vbatsocoff2_field + * @brief macros for field ctr_vbatsocoff2 + * @details vbat measure for soc off mode 2 + * @{ + */ +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATSOCOFF2__SHIFT 17 +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATSOCOFF2__WIDTH 2 +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATSOCOFF2__MASK 0x00060000U +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATSOCOFF2__READ(src) \ + (((uint32_t)(src)\ + & 0x00060000U) >> 17) +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATSOCOFF2__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00060000U) +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATSOCOFF2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00060000U) | (((uint32_t)(src) <<\ + 17) & 0x00060000U) +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATSOCOFF2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00060000U))) +#define PMUADC_CMPOUT_PARAM_3__CTR_VBATSOCOFF2__RESET_VALUE 0x00000002U +/** @} */ +#define PMUADC_CMPOUT_PARAM_3__TYPE uint32_t +#define PMUADC_CMPOUT_PARAM_3__READ 0x0007ffffU +#define PMUADC_CMPOUT_PARAM_3__WRITE 0x0007ffffU +#define PMUADC_CMPOUT_PARAM_3__PRESERVED 0x00000000U +#define PMUADC_CMPOUT_PARAM_3__RESET_VALUE 0x00054924U + +#endif /* __PMUADC_CMPOUT_PARAM_3_MACRO__ */ + +/** @} end of cmpout_param_3 */ + +/* macros for BlueprintGlobalNameSpace::PMUADC_cmpout_param_4 */ +/** + * @defgroup pmu_pmuadc_regs_core_cmpout_param_4 cmpout_param_4 + * @brief pmuadc reference parameter for comparator output definitions. + * @{ + */ +#ifndef __PMUADC_CMPOUT_PARAM_4_MACRO__ +#define __PMUADC_CMPOUT_PARAM_4_MACRO__ + +/* macros for field ctr_dstSup1Pen */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_dstSup1Pen_field ctr_dstSup1Pen_field + * @brief macros for field ctr_dstSup1Pen + * @details Compares vmax with Vref + * @{ + */ +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSUP1PEN__SHIFT 0 +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSUP1PEN__WIDTH 3 +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSUP1PEN__MASK 0x00000007U +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSUP1PEN__READ(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSUP1PEN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSUP1PEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSUP1PEN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSUP1PEN__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field ctr_dstSup4Pen */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_dstSup4Pen_field ctr_dstSup4Pen_field + * @brief macros for field ctr_dstSup4Pen + * @details Compares vmax with Vref + * @{ + */ +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSUP4PEN__SHIFT 3 +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSUP4PEN__WIDTH 3 +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSUP4PEN__MASK 0x00000038U +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSUP4PEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSUP4PEN__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSUP4PEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSUP4PEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSUP4PEN__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field ctr_dstStoreNen */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_dstStoreNen_field ctr_dstStoreNen_field + * @brief macros for field ctr_dstStoreNen + * @details Compares Vstore with Vref + * @{ + */ +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSTORENEN__SHIFT 6 +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSTORENEN__WIDTH 3 +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSTORENEN__MASK 0x000001c0U +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSTORENEN__READ(src) \ + (((uint32_t)(src)\ + & 0x000001c0U) >> 6) +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSTORENEN__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000001c0U) +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSTORENEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((uint32_t)(src) <<\ + 6) & 0x000001c0U) +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSTORENEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000001c0U))) +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSTORENEN__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field ctr_dstStorePen */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_dstStorePen_field ctr_dstStorePen_field + * @brief macros for field ctr_dstStorePen + * @details Compares Vstore with Vref + * @{ + */ +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSTOREPEN__SHIFT 9 +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSTOREPEN__WIDTH 3 +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSTOREPEN__MASK 0x00000e00U +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSTOREPEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000e00U) >> 9) +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSTOREPEN__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000e00U) +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSTOREPEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((uint32_t)(src) <<\ + 9) & 0x00000e00U) +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSTOREPEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000e00U))) +#define PMUADC_CMPOUT_PARAM_4__CTR_DSTSTOREPEN__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field ctr_srcHarvNen */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_srcHarvNen_field ctr_srcHarvNen_field + * @brief macros for field ctr_srcHarvNen + * @details Compares Vharv with Vref + * @{ + */ +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCHARVNEN__SHIFT 12 +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCHARVNEN__WIDTH 3 +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCHARVNEN__MASK 0x00007000U +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCHARVNEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00007000U) >> 12) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCHARVNEN__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00007000U) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCHARVNEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((uint32_t)(src) <<\ + 12) & 0x00007000U) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCHARVNEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00007000U))) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCHARVNEN__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field ctr_srcHarvPen */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_srcHarvPen_field ctr_srcHarvPen_field + * @brief macros for field ctr_srcHarvPen + * @details Compares Vharv with Vref + * @{ + */ +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCHARVPEN__SHIFT 15 +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCHARVPEN__WIDTH 3 +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCHARVPEN__MASK 0x00038000U +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCHARVPEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00038000U) >> 15) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCHARVPEN__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00038000U) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCHARVPEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((uint32_t)(src) <<\ + 15) & 0x00038000U) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCHARVPEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00038000U))) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCHARVPEN__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field ctr_srcStoreNen */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_srcStoreNen_field ctr_srcStoreNen_field + * @brief macros for field ctr_srcStoreNen + * @details Compares Vstore with Vref + * @{ + */ +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCSTORENEN__SHIFT 18 +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCSTORENEN__WIDTH 3 +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCSTORENEN__MASK 0x001c0000U +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCSTORENEN__READ(src) \ + (((uint32_t)(src)\ + & 0x001c0000U) >> 18) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCSTORENEN__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x001c0000U) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCSTORENEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((uint32_t)(src) <<\ + 18) & 0x001c0000U) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCSTORENEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x001c0000U))) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCSTORENEN__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field ctr_srcStorePen */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_srcStorePen_field ctr_srcStorePen_field + * @brief macros for field ctr_srcStorePen + * @details Compares Vstore with Vref + * @{ + */ +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCSTOREPEN__SHIFT 21 +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCSTOREPEN__WIDTH 3 +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCSTOREPEN__MASK 0x00e00000U +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCSTOREPEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00e00000U) >> 21) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCSTOREPEN__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00e00000U) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCSTOREPEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((uint32_t)(src) <<\ + 21) & 0x00e00000U) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCSTOREPEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00e00000U))) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCSTOREPEN__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field ctr_srcBattNen */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_srcBattNen_field ctr_srcBattNen_field + * @brief macros for field ctr_srcBattNen + * @details Compares Vbatt with Vref + * @{ + */ +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCBATTNEN__SHIFT 24 +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCBATTNEN__WIDTH 3 +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCBATTNEN__MASK 0x07000000U +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCBATTNEN__READ(src) \ + (((uint32_t)(src)\ + & 0x07000000U) >> 24) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCBATTNEN__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x07000000U) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCBATTNEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((uint32_t)(src) <<\ + 24) & 0x07000000U) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCBATTNEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x07000000U))) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCBATTNEN__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field ctr_srcBattPen */ +/** + * @defgroup pmu_pmuadc_regs_core_ctr_srcBattPen_field ctr_srcBattPen_field + * @brief macros for field ctr_srcBattPen + * @details Compares Vbatt with Vref + * @{ + */ +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCBATTPEN__SHIFT 27 +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCBATTPEN__WIDTH 3 +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCBATTPEN__MASK 0x38000000U +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCBATTPEN__READ(src) \ + (((uint32_t)(src)\ + & 0x38000000U) >> 27) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCBATTPEN__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x38000000U) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCBATTPEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x38000000U) | (((uint32_t)(src) <<\ + 27) & 0x38000000U) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCBATTPEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x38000000U))) +#define PMUADC_CMPOUT_PARAM_4__CTR_SRCBATTPEN__RESET_VALUE 0x00000004U +/** @} */ +#define PMUADC_CMPOUT_PARAM_4__TYPE uint32_t +#define PMUADC_CMPOUT_PARAM_4__READ 0x3fffffffU +#define PMUADC_CMPOUT_PARAM_4__WRITE 0x3fffffffU +#define PMUADC_CMPOUT_PARAM_4__PRESERVED 0x00000000U +#define PMUADC_CMPOUT_PARAM_4__RESET_VALUE 0x24924924U + +#endif /* __PMUADC_CMPOUT_PARAM_4_MACRO__ */ + +/** @} end of cmpout_param_4 */ + +/* macros for BlueprintGlobalNameSpace::PMUADC_pmuadc_readout0 */ +/** + * @defgroup pmu_pmuadc_regs_core_pmuadc_readout0 pmuadc_readout0 + * @brief readback registers definitions. + * @{ + */ +#ifndef __PMUADC_PMUADC_READOUT0_MACRO__ +#define __PMUADC_PMUADC_READOUT0_MACRO__ + +/* macros for field measComplete */ +/** + * @defgroup pmu_pmuadc_regs_core_measComplete_field measComplete_field + * @brief macros for field measComplete + * @details indicates which measurements where completed + * @{ + */ +#define PMUADC_PMUADC_READOUT0__MEASCOMPLETE__SHIFT 0 +#define PMUADC_PMUADC_READOUT0__MEASCOMPLETE__WIDTH 6 +#define PMUADC_PMUADC_READOUT0__MEASCOMPLETE__MASK 0x0000003fU +#define PMUADC_PMUADC_READOUT0__MEASCOMPLETE__READ(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define PMUADC_PMUADC_READOUT0__MEASCOMPLETE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field finished */ +/** + * @defgroup pmu_pmuadc_regs_core_finished_field finished_field + * @brief macros for field finished + * @details 1 if all measurements were completed + * @{ + */ +#define PMUADC_PMUADC_READOUT0__FINISHED__SHIFT 6 +#define PMUADC_PMUADC_READOUT0__FINISHED__WIDTH 1 +#define PMUADC_PMUADC_READOUT0__FINISHED__MASK 0x00000040U +#define PMUADC_PMUADC_READOUT0__FINISHED__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define PMUADC_PMUADC_READOUT0__FINISHED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PMUADC_PMUADC_READOUT0__FINISHED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PMUADC_PMUADC_READOUT0__FINISHED__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field result_Vharv */ +/** + * @defgroup pmu_pmuadc_regs_core_result_Vharv_field result_Vharv_field + * @brief macros for field result_Vharv + * @details result Vharv + * @{ + */ +#define PMUADC_PMUADC_READOUT0__RESULT_VHARV__SHIFT 7 +#define PMUADC_PMUADC_READOUT0__RESULT_VHARV__WIDTH 7 +#define PMUADC_PMUADC_READOUT0__RESULT_VHARV__MASK 0x00003f80U +#define PMUADC_PMUADC_READOUT0__RESULT_VHARV__READ(src) \ + (((uint32_t)(src)\ + & 0x00003f80U) >> 7) +#define PMUADC_PMUADC_READOUT0__RESULT_VHARV__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field result_Vstore */ +/** + * @defgroup pmu_pmuadc_regs_core_result_Vstore_field result_Vstore_field + * @brief macros for field result_Vstore + * @details result Vstore + * @{ + */ +#define PMUADC_PMUADC_READOUT0__RESULT_VSTORE__SHIFT 14 +#define PMUADC_PMUADC_READOUT0__RESULT_VSTORE__WIDTH 7 +#define PMUADC_PMUADC_READOUT0__RESULT_VSTORE__MASK 0x001fc000U +#define PMUADC_PMUADC_READOUT0__RESULT_VSTORE__READ(src) \ + (((uint32_t)(src)\ + & 0x001fc000U) >> 14) +#define PMUADC_PMUADC_READOUT0__RESULT_VSTORE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field result_Vbat */ +/** + * @defgroup pmu_pmuadc_regs_core_result_Vbat_field result_Vbat_field + * @brief macros for field result_Vbat + * @details result Vbat + * @{ + */ +#define PMUADC_PMUADC_READOUT0__RESULT_VBAT__SHIFT 21 +#define PMUADC_PMUADC_READOUT0__RESULT_VBAT__WIDTH 7 +#define PMUADC_PMUADC_READOUT0__RESULT_VBAT__MASK 0x0fe00000U +#define PMUADC_PMUADC_READOUT0__RESULT_VBAT__READ(src) \ + (((uint32_t)(src)\ + & 0x0fe00000U) >> 21) +#define PMUADC_PMUADC_READOUT0__RESULT_VBAT__RESET_VALUE 0x00000000U +/** @} */ +#define PMUADC_PMUADC_READOUT0__TYPE uint32_t +#define PMUADC_PMUADC_READOUT0__READ 0x0fffffffU +#define PMUADC_PMUADC_READOUT0__PRESERVED 0x00000000U +#define PMUADC_PMUADC_READOUT0__RESET_VALUE 0x00000040U + +#endif /* __PMUADC_PMUADC_READOUT0_MACRO__ */ + +/** @} end of pmuadc_readout0 */ + +/* macros for BlueprintGlobalNameSpace::PMUADC_pmuadc_readout1 */ +/** + * @defgroup pmu_pmuadc_regs_core_pmuadc_readout1 pmuadc_readout1 + * @brief pmuadc readout bits definitions. + * @{ + */ +#ifndef __PMUADC_PMUADC_READOUT1_MACRO__ +#define __PMUADC_PMUADC_READOUT1_MACRO__ + +/* macros for field result_Vatb */ +/** + * @defgroup pmu_pmuadc_regs_core_result_Vatb_field result_Vatb_field + * @brief macros for field result_Vatb + * @details result Vatb + * @{ + */ +#define PMUADC_PMUADC_READOUT1__RESULT_VATB__SHIFT 0 +#define PMUADC_PMUADC_READOUT1__RESULT_VATB__WIDTH 7 +#define PMUADC_PMUADC_READOUT1__RESULT_VATB__MASK 0x0000007fU +#define PMUADC_PMUADC_READOUT1__RESULT_VATB__READ(src) \ + ((uint32_t)(src)\ + & 0x0000007fU) +#define PMUADC_PMUADC_READOUT1__RESULT_VATB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field result_Vliion */ +/** + * @defgroup pmu_pmuadc_regs_core_result_Vliion_field result_Vliion_field + * @brief macros for field result_Vliion + * @details result Vliion + * @{ + */ +#define PMUADC_PMUADC_READOUT1__RESULT_VLIION__SHIFT 7 +#define PMUADC_PMUADC_READOUT1__RESULT_VLIION__WIDTH 7 +#define PMUADC_PMUADC_READOUT1__RESULT_VLIION__MASK 0x00003f80U +#define PMUADC_PMUADC_READOUT1__RESULT_VLIION__READ(src) \ + (((uint32_t)(src)\ + & 0x00003f80U) >> 7) +#define PMUADC_PMUADC_READOUT1__RESULT_VLIION__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field result_Vmax */ +/** + * @defgroup pmu_pmuadc_regs_core_result_Vmax_field result_Vmax_field + * @brief macros for field result_Vmax + * @details result Vmax + * @{ + */ +#define PMUADC_PMUADC_READOUT1__RESULT_VMAX__SHIFT 14 +#define PMUADC_PMUADC_READOUT1__RESULT_VMAX__WIDTH 7 +#define PMUADC_PMUADC_READOUT1__RESULT_VMAX__MASK 0x001fc000U +#define PMUADC_PMUADC_READOUT1__RESULT_VMAX__READ(src) \ + (((uint32_t)(src)\ + & 0x001fc000U) >> 14) +#define PMUADC_PMUADC_READOUT1__RESULT_VMAX__RESET_VALUE 0x00000000U +/** @} */ +#define PMUADC_PMUADC_READOUT1__TYPE uint32_t +#define PMUADC_PMUADC_READOUT1__READ 0x001fffffU +#define PMUADC_PMUADC_READOUT1__PRESERVED 0x00000000U +#define PMUADC_PMUADC_READOUT1__RESET_VALUE 0x00000000U + +#endif /* __PMUADC_PMUADC_READOUT1_MACRO__ */ + +/** @} end of pmuadc_readout1 */ + +/* macros for BlueprintGlobalNameSpace::PMUADC_core_id */ +/** + * @defgroup pmu_pmuadc_regs_core_core_id core_id + * @brief Core ID definitions. + * @{ + */ +#ifndef __PMUADC_CORE_ID_MACRO__ +#define __PMUADC_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup pmu_pmuadc_regs_core_id_field id_field + * @brief macros for field id + * @details PADC in ASCII (PMU ADC) + * @{ + */ +#define PMUADC_CORE_ID__ID__SHIFT 0 +#define PMUADC_CORE_ID__ID__WIDTH 32 +#define PMUADC_CORE_ID__ID__MASK 0xffffffffU +#define PMUADC_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PMUADC_CORE_ID__ID__RESET_VALUE 0x50414443U +/** @} */ +#define PMUADC_CORE_ID__TYPE uint32_t +#define PMUADC_CORE_ID__READ 0xffffffffU +#define PMUADC_CORE_ID__PRESERVED 0x00000000U +#define PMUADC_CORE_ID__RESET_VALUE 0x50414443U + +#endif /* __PMUADC_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of PMU_PMUADC_REGS_CORE */ +#endif /* __REG_PMU_PMUADC_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/pmu_spi.h b/ATM33xx-5/include/reg/pmu_spi.h new file mode 100644 index 0000000..697d51a --- /dev/null +++ b/ATM33xx-5/include/reg/pmu_spi.h @@ -0,0 +1,132 @@ +/** + ***************************************************************************** + * + * @file pmu_spi.h + * + * @brief PMU SPI definitions + * + * Copyright (C) Atmosic 2022-2024 + * + ***************************************************************************** + */ + +#pragma once + +/** + * @defgroup at_pmu_spi pmu_spi + * @ingroup AT_REG + * @brief pmu spi definitions. + * @{ + */ +#define PMU_SPI__DUMMY_CYCLES 3 + +#define SWREG_AON__REG_BLADDR 0 +#define SWREG_AON__AON0_REG_ADDR 0x0 +#define SWREG_AON__AON1_REG_ADDR 0x4 +#define SWREG_AON__AON2_REG_ADDR 0x8 +#define SWREG_AON__AON3_REG_ADDR 0xc +#define SWREG_AON__AON4_REG_ADDR 0x10 +#define SWREG_AON__AON5_REG_ADDR 0x14 +#define SWREG_AON__AON6_REG_ADDR 0x18 +#define SWREG_AON__READOUT_REG_ADDR 0x1c +#define SWREG_AON__CORE_ID_REG_ADDR 0x20 + +#define SWREG_SIMPLE__REG_BLADDR 1 +#define SWREG_SIMPLE__SIMPLE0_REG_ADDR 0x0 +#define SWREG_SIMPLE__SIMPLE1_REG_ADDR 0x4 +#define SWREG_SIMPLE__SIMPLE2_REG_ADDR 0x8 +#define SWREG_SIMPLE__CORE_ID_REG_ADDR 0xc + +#define SWREG_MAIN__REG_BLADDR 2 +#define SWREG_MAIN__MAIN0_REG_ADDR 0x0 +#define SWREG_MAIN__MAIN1_REG_ADDR 0x4 +#define SWREG_MAIN__MAIN2_REG_ADDR 0x8 +#define SWREG_MAIN__MAIN3_REG_ADDR 0xc +#define SWREG_MAIN__MAIN4_REG_ADDR 0x10 +#define SWREG_MAIN__MAIN5_REG_ADDR 0x14 +#define SWREG_MAIN__MAIN6_REG_ADDR 0x18 +#define SWREG_MAIN__MAIN7_REG_ADDR 0x1c +#define SWREG_MAIN__MAIN8_REG_ADDR 0x20 +#define SWREG_MAIN__MAIN9_REG_ADDR 0x24 +#define SWREG_MAIN__MAIN10_REG_ADDR 0x28 +#define SWREG_MAIN__READOUT0_REG_ADDR 0x2c +#define SWREG_MAIN__READOUT1_REG_ADDR 0x30 +#define SWREG_MAIN__READOUT2_REG_ADDR 0x34 +#define SWREG_MAIN__READOUT3_REG_ADDR 0x38 +#define SWREG_MAIN__CORE_ID_REG_ADDR 0x3c + +#define PMU_TOP__REG_BLADDR 9 +#define PMU_TOP__PMU0_REG_ADDR 0x0 +#define PMU_TOP__PMU1_REG_ADDR 0x4 +#define PMU_TOP__PMU1A_REG_ADDR 0x8 +#define PMU_TOP__PMU2_REG_ADDR 0xc +#define PMU_TOP__PMU2A_REG_ADDR 0x10 +#define PMU_TOP__PMU3_REG_ADDR 0x14 +#define PMU_TOP__PMU4_REG_ADDR 0x18 +#define PMU_TOP__PMU5_REG_ADDR 0x1c +#define PMU_TOP__PMU6_REG_ADDR 0x20 +#define PMU_TOP__PMU7_REG_ADDR 0x24 +#define PMU_TOP__PMU8_REG_ADDR 0x28 +#define PMU_TOP__PMU9_REG_ADDR 0x2c +#define PMU_TOP__PMU10_REG_ADDR 0x30 +#define PMU_TOP__PMU11_REG_ADDR 0x34 +#define PMU_TOP__PMU12_REG_ADDR 0x38 +#define PMU_TOP__PMU12A_REG_ADDR 0x3c +#define PMU_TOP__PMU13_REG_ADDR 0x40 +#define PMU_TOP__PMU14_REG_ADDR 0x44 +#define PMU_TOP__PMU14A_REG_ADDR 0x48 +#define PMU_TOP__PMU14B_REG_ADDR 0x4c +#define PMU_TOP__PMU14C_REG_ADDR 0x50 +#define PMU_TOP__PMU15_REG_ADDR 0x54 +#define PMU_TOP__PMU16_REG_ADDR 0x58 +#define PMU_TOP__CHRG_CTRL_REG_ADDR 0x5c +#define PMU_TOP__CHRG_CTRL2_REG_ADDR 0x60 +#define PMU_TOP__PMU17_REG_ADDR 0x64 +#define PMU_TOP__PMU18_REG_ADDR 0x68 +#define PMU_TOP__PMU_RB0_REG_ADDR 0x6c +#define PMU_TOP__PMU_RB1_REG_ADDR 0x70 +#define PMU_TOP__PMU_RB2_REG_ADDR 0x74 +#define PMU_TOP__PMU_RB_MPPT_REG_ADDR 0x78 +#define PMU_TOP__PMU_RB3_REG_ADDR 0x7c +#define PMU_TOP__PMU_RB4_REG_ADDR 0x80 +#define PMU_TOP__PMU_RB5_REG_ADDR 0x84 +#define PMU_TOP__CORE_ID_REG_ADDR 0x88 + +#define PMU_WURX__REG_BLADDR 10 +#define PMU_WURX__WURX_GENERAL_REG_ADDR 0x0 +#define PMU_WURX__WURX_GENERAL2_REG_ADDR 0x4 +#define PMU_WURX__WURX0_0_REG_ADDR 0x8 +#define PMU_WURX__WURX0_1_REG_ADDR 0xc +#define PMU_WURX__WURX0_2_REG_ADDR 0x10 +#define PMU_WURX__WURX0_3_REG_ADDR 0x14 +#define PMU_WURX__WURX0_4_REG_ADDR 0x18 +#define PMU_WURX__WURX1_0_REG_ADDR 0x1c +#define PMU_WURX__WURX1_1_REG_ADDR 0x20 +#define PMU_WURX__WURX1_2_REG_ADDR 0x24 +#define PMU_WURX__WURX1_3_REG_ADDR 0x28 +#define PMU_WURX__WURX1_4_REG_ADDR 0x2c +#define PMU_WURX__WURX_RB0_REG_ADDR 0x30 +#define PMU_WURX__WURX_RB1_REG_ADDR 0x34 +#define PMU_WURX__WURX_RB2_REG_ADDR 0x38 +#define PMU_WURX__WURX_SPARE_REG_ADDR 0x3c +#define PMU_WURX__CORE_ID_REG_ADDR 0x40 + +#define PMU_GADC__REG_BLADDR 11 +#define PMU_GADC__GADC_CTRL_REG_ADDR 0x0 +#define PMU_GADC__CORE_ID_REG_ADDR 0x4 + +#define PMU_PMUADC__REG_BLADDR 13 +#define PMU_PMUADC__REG0_REG_ADDR 0x0 +#define PMU_PMUADC__MAIN1_REG_ADDR 0x4 +#define PMU_PMUADC__PMUADC_CTRLR_REG_ADDR 0x8 +#define PMU_PMUADC__MEAS_PERIOD0_REG_ADDR 0xc +#define PMU_PMUADC__MEAS_PERIOD1_REG_ADDR 0x10 +#define PMU_PMUADC__CMPOUT_PARAM_1_REG_ADDR 0x14 +#define PMU_PMUADC__CMPOUT_PARAM_2_REG_ADDR 0x18 +#define PMU_PMUADC__CMPOUT_PARAM_3_REG_ADDR 0x1c +#define PMU_PMUADC__CMPOUT_PARAM_4_REG_ADDR 0x20 +#define PMU_PMUADC__PMUADC_READOUT0_REG_ADDR 0x24 +#define PMU_PMUADC__PMUADC_READOUT1_REG_ADDR 0x28 +#define PMU_PMUADC__CORE_ID_REG_ADDR 0x2c + +/** @} end of at_pmu_spi */ diff --git a/ATM33xx-5/include/reg/pmu_swreg_regs_core_macro.h b/ATM33xx-5/include/reg/pmu_swreg_regs_core_macro.h new file mode 100644 index 0000000..9d7b1d6 --- /dev/null +++ b/ATM33xx-5/include/reg/pmu_swreg_regs_core_macro.h @@ -0,0 +1,2020 @@ +/* */ +/* File: pmu_swreg_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic pmu_swreg_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2021 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_PMU_SWREG_REGS_CORE_H__ +#define __REG_PMU_SWREG_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup PMU_SWREG_REGS_CORE pmu_swreg_regs_core + * @ingroup AT_REG + * @brief pmu_swreg_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::SWREG_swreg_ctrl_0 */ +/** + * @defgroup pmu_swreg_regs_core_swreg_ctrl_0 swreg_ctrl_0 + * @brief swreg reg 0 For fields that refer to the sources the order is: 2: Battery 1: Store 0: Harvester For fields that refer to the destinations the order is: 4: Store 3: AVDD 2: VDDIO 1: VDDAUX 0: DVDD For fields that refer to the supplies the order is: 3: AVDD 2: VDDIO 1: VDDAUX 0: DVDD For fields that refer to the power transfer modes the order is: 13: None12: Battery -> AVDD11: Battery -> VDDIO10: Battery -> VDDAUX9: Battery -> DVDD8: Store -> AVDD7: Store -> VDDIO6: Store -> VDDAUX5: Store -> DVDD4: Harvester -> AVDD3: Harvester -> VDDIO2: Harvester -> VDDAUX1: Harvester -> DVDD0: Harvester -> Store definitions. + * @{ + */ +#ifndef __SWREG_SWREG_CTRL_0_MACRO__ +#define __SWREG_SWREG_CTRL_0_MACRO__ + +/* macros for field overrideBuckBoost */ +/** + * @defgroup pmu_swreg_regs_core_overrideBuckBoost_field overrideBuckBoost_field + * @brief macros for field overrideBuckBoost + * @details override the default buck-boost mode + * @{ + */ +#define SWREG_SWREG_CTRL_0__OVERRIDEBUCKBOOST__SHIFT 0 +#define SWREG_SWREG_CTRL_0__OVERRIDEBUCKBOOST__WIDTH 1 +#define SWREG_SWREG_CTRL_0__OVERRIDEBUCKBOOST__MASK 0x00000001U +#define SWREG_SWREG_CTRL_0__OVERRIDEBUCKBOOST__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWREG_SWREG_CTRL_0__OVERRIDEBUCKBOOST__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWREG_SWREG_CTRL_0__OVERRIDEBUCKBOOST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SWREG_SWREG_CTRL_0__OVERRIDEBUCKBOOST__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SWREG_SWREG_CTRL_0__OVERRIDEBUCKBOOST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SWREG_SWREG_CTRL_0__OVERRIDEBUCKBOOST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +/** @} */ + +/* macros for field buck_ovr */ +/** + * @defgroup pmu_swreg_regs_core_buck_ovr_field buck_ovr_field + * @brief macros for field buck_ovr + * @details 1 sets the respective mode to buck + * @{ + */ +#define SWREG_SWREG_CTRL_0__BUCK_OVR__SHIFT 1 +#define SWREG_SWREG_CTRL_0__BUCK_OVR__WIDTH 13 +#define SWREG_SWREG_CTRL_0__BUCK_OVR__MASK 0x00003ffeU +#define SWREG_SWREG_CTRL_0__BUCK_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00003ffeU) >> 1) +#define SWREG_SWREG_CTRL_0__BUCK_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00003ffeU) +#define SWREG_SWREG_CTRL_0__BUCK_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003ffeU) | (((uint32_t)(src) <<\ + 1) & 0x00003ffeU) +#define SWREG_SWREG_CTRL_0__BUCK_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00003ffeU))) +/** @} */ + +/* macros for field boost_ovr */ +/** + * @defgroup pmu_swreg_regs_core_boost_ovr_field boost_ovr_field + * @brief macros for field boost_ovr + * @details 1 sets the respective mode to boost + * @{ + */ +#define SWREG_SWREG_CTRL_0__BOOST_OVR__SHIFT 14 +#define SWREG_SWREG_CTRL_0__BOOST_OVR__WIDTH 13 +#define SWREG_SWREG_CTRL_0__BOOST_OVR__MASK 0x07ffc000U +#define SWREG_SWREG_CTRL_0__BOOST_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x07ffc000U) >> 14) +#define SWREG_SWREG_CTRL_0__BOOST_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x07ffc000U) +#define SWREG_SWREG_CTRL_0__BOOST_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07ffc000U) | (((uint32_t)(src) <<\ + 14) & 0x07ffc000U) +#define SWREG_SWREG_CTRL_0__BOOST_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x07ffc000U))) +/** @} */ + +/* macros for field directlyCCM */ +/** + * @defgroup pmu_swreg_regs_core_directlyCCM_field directlyCCM_field + * @brief macros for field directlyCCM + * @details start directly in CCM mode, skipping DCM for this destination + * @{ + */ +#define SWREG_SWREG_CTRL_0__DIRECTLYCCM__SHIFT 27 +#define SWREG_SWREG_CTRL_0__DIRECTLYCCM__WIDTH 5 +#define SWREG_SWREG_CTRL_0__DIRECTLYCCM__MASK 0xf8000000U +#define SWREG_SWREG_CTRL_0__DIRECTLYCCM__READ(src) \ + (((uint32_t)(src)\ + & 0xf8000000U) >> 27) +#define SWREG_SWREG_CTRL_0__DIRECTLYCCM__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0xf8000000U) +#define SWREG_SWREG_CTRL_0__DIRECTLYCCM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((uint32_t)(src) <<\ + 27) & 0xf8000000U) +#define SWREG_SWREG_CTRL_0__DIRECTLYCCM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0xf8000000U))) +/** @} */ +#define SWREG_SWREG_CTRL_0__TYPE uint32_t +#define SWREG_SWREG_CTRL_0__READ 0xffffffffU +#define SWREG_SWREG_CTRL_0__WRITE 0xffffffffU +#define SWREG_SWREG_CTRL_0__PRESERVED 0x00000000U + +#endif /* __SWREG_SWREG_CTRL_0_MACRO__ */ + +/** @} end of swreg_ctrl_0 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_swreg_ctrl_1 */ +/** + * @defgroup pmu_swreg_regs_core_swreg_ctrl_1 swreg_ctrl_1 + * @brief swreg reg 1 definitions. + * @{ + */ +#ifndef __SWREG_SWREG_CTRL_1_MACRO__ +#define __SWREG_SWREG_CTRL_1_MACRO__ + +/* macros for field enableCCM */ +/** + * @defgroup pmu_swreg_regs_core_enableCCM_field enableCCM_field + * @brief macros for field enableCCM + * @details enable CCM for the respective mode + * @{ + */ +#define SWREG_SWREG_CTRL_1__ENABLECCM__SHIFT 0 +#define SWREG_SWREG_CTRL_1__ENABLECCM__WIDTH 13 +#define SWREG_SWREG_CTRL_1__ENABLECCM__MASK 0x00001fffU +#define SWREG_SWREG_CTRL_1__ENABLECCM__READ(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define SWREG_SWREG_CTRL_1__ENABLECCM__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define SWREG_SWREG_CTRL_1__ENABLECCM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fffU) | ((uint32_t)(src) &\ + 0x00001fffU) +#define SWREG_SWREG_CTRL_1__ENABLECCM__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00001fffU))) +/** @} */ + +/* macros for field overridePN */ +/** + * @defgroup pmu_swreg_regs_core_overridePN_field overridePN_field + * @brief macros for field overridePN + * @details override the enables for the P and N part of the switches + * @{ + */ +#define SWREG_SWREG_CTRL_1__OVERRIDEPN__SHIFT 13 +#define SWREG_SWREG_CTRL_1__OVERRIDEPN__WIDTH 1 +#define SWREG_SWREG_CTRL_1__OVERRIDEPN__MASK 0x00002000U +#define SWREG_SWREG_CTRL_1__OVERRIDEPN__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define SWREG_SWREG_CTRL_1__OVERRIDEPN__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define SWREG_SWREG_CTRL_1__OVERRIDEPN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define SWREG_SWREG_CTRL_1__OVERRIDEPN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define SWREG_SWREG_CTRL_1__OVERRIDEPN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define SWREG_SWREG_CTRL_1__OVERRIDEPN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +/** @} */ + +/* macros for field harvNen_ovr */ +/** + * @defgroup pmu_swreg_regs_core_harvNen_ovr_field harvNen_ovr_field + * @brief macros for field harvNen_ovr + * @details enable N for the harvester + * @{ + */ +#define SWREG_SWREG_CTRL_1__HARVNEN_OVR__SHIFT 14 +#define SWREG_SWREG_CTRL_1__HARVNEN_OVR__WIDTH 1 +#define SWREG_SWREG_CTRL_1__HARVNEN_OVR__MASK 0x00004000U +#define SWREG_SWREG_CTRL_1__HARVNEN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define SWREG_SWREG_CTRL_1__HARVNEN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define SWREG_SWREG_CTRL_1__HARVNEN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define SWREG_SWREG_CTRL_1__HARVNEN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define SWREG_SWREG_CTRL_1__HARVNEN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define SWREG_SWREG_CTRL_1__HARVNEN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +/** @} */ + +/* macros for field harvPen_ovr */ +/** + * @defgroup pmu_swreg_regs_core_harvPen_ovr_field harvPen_ovr_field + * @brief macros for field harvPen_ovr + * @details enable P for the harvester + * @{ + */ +#define SWREG_SWREG_CTRL_1__HARVPEN_OVR__SHIFT 15 +#define SWREG_SWREG_CTRL_1__HARVPEN_OVR__WIDTH 1 +#define SWREG_SWREG_CTRL_1__HARVPEN_OVR__MASK 0x00008000U +#define SWREG_SWREG_CTRL_1__HARVPEN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define SWREG_SWREG_CTRL_1__HARVPEN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define SWREG_SWREG_CTRL_1__HARVPEN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define SWREG_SWREG_CTRL_1__HARVPEN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define SWREG_SWREG_CTRL_1__HARVPEN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define SWREG_SWREG_CTRL_1__HARVPEN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +/** @} */ + +/* macros for field storeNen_ovr */ +/** + * @defgroup pmu_swreg_regs_core_storeNen_ovr_field storeNen_ovr_field + * @brief macros for field storeNen_ovr + * @details enable N for the store + * @{ + */ +#define SWREG_SWREG_CTRL_1__STORENEN_OVR__SHIFT 16 +#define SWREG_SWREG_CTRL_1__STORENEN_OVR__WIDTH 1 +#define SWREG_SWREG_CTRL_1__STORENEN_OVR__MASK 0x00010000U +#define SWREG_SWREG_CTRL_1__STORENEN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define SWREG_SWREG_CTRL_1__STORENEN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define SWREG_SWREG_CTRL_1__STORENEN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define SWREG_SWREG_CTRL_1__STORENEN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define SWREG_SWREG_CTRL_1__STORENEN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define SWREG_SWREG_CTRL_1__STORENEN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +/** @} */ + +/* macros for field storePen_ovr */ +/** + * @defgroup pmu_swreg_regs_core_storePen_ovr_field storePen_ovr_field + * @brief macros for field storePen_ovr + * @details enable P for the store + * @{ + */ +#define SWREG_SWREG_CTRL_1__STOREPEN_OVR__SHIFT 17 +#define SWREG_SWREG_CTRL_1__STOREPEN_OVR__WIDTH 1 +#define SWREG_SWREG_CTRL_1__STOREPEN_OVR__MASK 0x00020000U +#define SWREG_SWREG_CTRL_1__STOREPEN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SWREG_SWREG_CTRL_1__STOREPEN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SWREG_SWREG_CTRL_1__STOREPEN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SWREG_SWREG_CTRL_1__STOREPEN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SWREG_SWREG_CTRL_1__STOREPEN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SWREG_SWREG_CTRL_1__STOREPEN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +/** @} */ + +/* macros for field battNen_ovr */ +/** + * @defgroup pmu_swreg_regs_core_battNen_ovr_field battNen_ovr_field + * @brief macros for field battNen_ovr + * @details enable N for the battery + * @{ + */ +#define SWREG_SWREG_CTRL_1__BATTNEN_OVR__SHIFT 18 +#define SWREG_SWREG_CTRL_1__BATTNEN_OVR__WIDTH 1 +#define SWREG_SWREG_CTRL_1__BATTNEN_OVR__MASK 0x00040000U +#define SWREG_SWREG_CTRL_1__BATTNEN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SWREG_SWREG_CTRL_1__BATTNEN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SWREG_SWREG_CTRL_1__BATTNEN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SWREG_SWREG_CTRL_1__BATTNEN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SWREG_SWREG_CTRL_1__BATTNEN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SWREG_SWREG_CTRL_1__BATTNEN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +/** @} */ + +/* macros for field battPen_ovr */ +/** + * @defgroup pmu_swreg_regs_core_battPen_ovr_field battPen_ovr_field + * @brief macros for field battPen_ovr + * @details enable P for the battery + * @{ + */ +#define SWREG_SWREG_CTRL_1__BATTPEN_OVR__SHIFT 19 +#define SWREG_SWREG_CTRL_1__BATTPEN_OVR__WIDTH 1 +#define SWREG_SWREG_CTRL_1__BATTPEN_OVR__MASK 0x00080000U +#define SWREG_SWREG_CTRL_1__BATTPEN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define SWREG_SWREG_CTRL_1__BATTPEN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define SWREG_SWREG_CTRL_1__BATTPEN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define SWREG_SWREG_CTRL_1__BATTPEN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define SWREG_SWREG_CTRL_1__BATTPEN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define SWREG_SWREG_CTRL_1__BATTPEN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +/** @} */ + +/* macros for field dvddPen_ovr */ +/** + * @defgroup pmu_swreg_regs_core_dvddPen_ovr_field dvddPen_ovr_field + * @brief macros for field dvddPen_ovr + * @details enable P for dvdd + * @{ + */ +#define SWREG_SWREG_CTRL_1__DVDDPEN_OVR__SHIFT 20 +#define SWREG_SWREG_CTRL_1__DVDDPEN_OVR__WIDTH 1 +#define SWREG_SWREG_CTRL_1__DVDDPEN_OVR__MASK 0x00100000U +#define SWREG_SWREG_CTRL_1__DVDDPEN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define SWREG_SWREG_CTRL_1__DVDDPEN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define SWREG_SWREG_CTRL_1__DVDDPEN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define SWREG_SWREG_CTRL_1__DVDDPEN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define SWREG_SWREG_CTRL_1__DVDDPEN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define SWREG_SWREG_CTRL_1__DVDDPEN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +/** @} */ + +/* macros for field avddPen_ovr */ +/** + * @defgroup pmu_swreg_regs_core_avddPen_ovr_field avddPen_ovr_field + * @brief macros for field avddPen_ovr + * @details enable P for avdd + * @{ + */ +#define SWREG_SWREG_CTRL_1__AVDDPEN_OVR__SHIFT 21 +#define SWREG_SWREG_CTRL_1__AVDDPEN_OVR__WIDTH 1 +#define SWREG_SWREG_CTRL_1__AVDDPEN_OVR__MASK 0x00200000U +#define SWREG_SWREG_CTRL_1__AVDDPEN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define SWREG_SWREG_CTRL_1__AVDDPEN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define SWREG_SWREG_CTRL_1__AVDDPEN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define SWREG_SWREG_CTRL_1__AVDDPEN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define SWREG_SWREG_CTRL_1__AVDDPEN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define SWREG_SWREG_CTRL_1__AVDDPEN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +/** @} */ + +/* macros for field delEnergDump */ +/** + * @defgroup pmu_swreg_regs_core_delEnergDump_field delEnergDump_field + * @brief macros for field delEnergDump + * @details non-overlap time between energize and dump + * @{ + */ +#define SWREG_SWREG_CTRL_1__DELENERGDUMP__SHIFT 22 +#define SWREG_SWREG_CTRL_1__DELENERGDUMP__WIDTH 4 +#define SWREG_SWREG_CTRL_1__DELENERGDUMP__MASK 0x03c00000U +#define SWREG_SWREG_CTRL_1__DELENERGDUMP__READ(src) \ + (((uint32_t)(src)\ + & 0x03c00000U) >> 22) +#define SWREG_SWREG_CTRL_1__DELENERGDUMP__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x03c00000U) +#define SWREG_SWREG_CTRL_1__DELENERGDUMP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03c00000U) | (((uint32_t)(src) <<\ + 22) & 0x03c00000U) +#define SWREG_SWREG_CTRL_1__DELENERGDUMP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x03c00000U))) +/** @} */ + +/* macros for field delZCD1 */ +/** + * @defgroup pmu_swreg_regs_core_delZCD1_field delZCD1_field + * @brief macros for field delZCD1 + * @details first delay for the Zero Crossing Detection circuit + * @{ + */ +#define SWREG_SWREG_CTRL_1__DELZCD1__SHIFT 26 +#define SWREG_SWREG_CTRL_1__DELZCD1__WIDTH 2 +#define SWREG_SWREG_CTRL_1__DELZCD1__MASK 0x0c000000U +#define SWREG_SWREG_CTRL_1__DELZCD1__READ(src) \ + (((uint32_t)(src)\ + & 0x0c000000U) >> 26) +#define SWREG_SWREG_CTRL_1__DELZCD1__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x0c000000U) +#define SWREG_SWREG_CTRL_1__DELZCD1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((uint32_t)(src) <<\ + 26) & 0x0c000000U) +#define SWREG_SWREG_CTRL_1__DELZCD1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x0c000000U))) +/** @} */ + +/* macros for field delZCD2 */ +/** + * @defgroup pmu_swreg_regs_core_delZCD2_field delZCD2_field + * @brief macros for field delZCD2 + * @details second delay for the Zero Crossing Detection circuit + * @{ + */ +#define SWREG_SWREG_CTRL_1__DELZCD2__SHIFT 28 +#define SWREG_SWREG_CTRL_1__DELZCD2__WIDTH 2 +#define SWREG_SWREG_CTRL_1__DELZCD2__MASK 0x30000000U +#define SWREG_SWREG_CTRL_1__DELZCD2__READ(src) \ + (((uint32_t)(src)\ + & 0x30000000U) >> 28) +#define SWREG_SWREG_CTRL_1__DELZCD2__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x30000000U) +#define SWREG_SWREG_CTRL_1__DELZCD2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x30000000U) | (((uint32_t)(src) <<\ + 28) & 0x30000000U) +#define SWREG_SWREG_CTRL_1__DELZCD2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x30000000U))) +/** @} */ + +/* macros for field size */ +/** + * @defgroup pmu_swreg_regs_core_size_field size_field + * @brief macros for field size + * @details switch size + * @{ + */ +#define SWREG_SWREG_CTRL_1__SIZE__SHIFT 30 +#define SWREG_SWREG_CTRL_1__SIZE__WIDTH 2 +#define SWREG_SWREG_CTRL_1__SIZE__MASK 0xc0000000U +#define SWREG_SWREG_CTRL_1__SIZE__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define SWREG_SWREG_CTRL_1__SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define SWREG_SWREG_CTRL_1__SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define SWREG_SWREG_CTRL_1__SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +/** @} */ +#define SWREG_SWREG_CTRL_1__TYPE uint32_t +#define SWREG_SWREG_CTRL_1__READ 0xffffffffU +#define SWREG_SWREG_CTRL_1__WRITE 0xffffffffU +#define SWREG_SWREG_CTRL_1__PRESERVED 0x00000000U + +#endif /* __SWREG_SWREG_CTRL_1_MACRO__ */ + +/** @} end of swreg_ctrl_1 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_swreg_ctrl_2 */ +/** + * @defgroup pmu_swreg_regs_core_swreg_ctrl_2 swreg_ctrl_2 + * @brief swreg reg 2 definitions. + * @{ + */ +#ifndef __SWREG_SWREG_CTRL_2_MACRO__ +#define __SWREG_SWREG_CTRL_2_MACRO__ + +/* macros for field overrideEnS */ +/** + * @defgroup pmu_swreg_regs_core_overrideEnS_field overrideEnS_field + * @brief macros for field overrideEnS + * @details override enables for the 3 sources + * @{ + */ +#define SWREG_SWREG_CTRL_2__OVERRIDEENS__SHIFT 0 +#define SWREG_SWREG_CTRL_2__OVERRIDEENS__WIDTH 3 +#define SWREG_SWREG_CTRL_2__OVERRIDEENS__MASK 0x00000007U +#define SWREG_SWREG_CTRL_2__OVERRIDEENS__READ(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define SWREG_SWREG_CTRL_2__OVERRIDEENS__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define SWREG_SWREG_CTRL_2__OVERRIDEENS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define SWREG_SWREG_CTRL_2__OVERRIDEENS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +/** @} */ + +/* macros for field enableSource_ovr */ +/** + * @defgroup pmu_swreg_regs_core_enableSource_ovr_field enableSource_ovr_field + * @brief macros for field enableSource_ovr + * @details override enable values for the 3 sources + * @{ + */ +#define SWREG_SWREG_CTRL_2__ENABLESOURCE_OVR__SHIFT 3 +#define SWREG_SWREG_CTRL_2__ENABLESOURCE_OVR__WIDTH 3 +#define SWREG_SWREG_CTRL_2__ENABLESOURCE_OVR__MASK 0x00000038U +#define SWREG_SWREG_CTRL_2__ENABLESOURCE_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define SWREG_SWREG_CTRL_2__ENABLESOURCE_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define SWREG_SWREG_CTRL_2__ENABLESOURCE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define SWREG_SWREG_CTRL_2__ENABLESOURCE_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +/** @} */ + +/* macros for field overrideEnD */ +/** + * @defgroup pmu_swreg_regs_core_overrideEnD_field overrideEnD_field + * @brief macros for field overrideEnD + * @details override enables for the 5 destinations + * @{ + */ +#define SWREG_SWREG_CTRL_2__OVERRIDEEND__SHIFT 6 +#define SWREG_SWREG_CTRL_2__OVERRIDEEND__WIDTH 5 +#define SWREG_SWREG_CTRL_2__OVERRIDEEND__MASK 0x000007c0U +#define SWREG_SWREG_CTRL_2__OVERRIDEEND__READ(src) \ + (((uint32_t)(src)\ + & 0x000007c0U) >> 6) +#define SWREG_SWREG_CTRL_2__OVERRIDEEND__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000007c0U) +#define SWREG_SWREG_CTRL_2__OVERRIDEEND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007c0U) | (((uint32_t)(src) <<\ + 6) & 0x000007c0U) +#define SWREG_SWREG_CTRL_2__OVERRIDEEND__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000007c0U))) +/** @} */ + +/* macros for field enableDest_ovr */ +/** + * @defgroup pmu_swreg_regs_core_enableDest_ovr_field enableDest_ovr_field + * @brief macros for field enableDest_ovr + * @details override enable values for the 5 destinations + * @{ + */ +#define SWREG_SWREG_CTRL_2__ENABLEDEST_OVR__SHIFT 11 +#define SWREG_SWREG_CTRL_2__ENABLEDEST_OVR__WIDTH 5 +#define SWREG_SWREG_CTRL_2__ENABLEDEST_OVR__MASK 0x0000f800U +#define SWREG_SWREG_CTRL_2__ENABLEDEST_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f800U) >> 11) +#define SWREG_SWREG_CTRL_2__ENABLEDEST_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x0000f800U) +#define SWREG_SWREG_CTRL_2__ENABLEDEST_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f800U) | (((uint32_t)(src) <<\ + 11) & 0x0000f800U) +#define SWREG_SWREG_CTRL_2__ENABLEDEST_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x0000f800U))) +/** @} */ + +/* macros for field overrideEnHarv2Sup */ +/** + * @defgroup pmu_swreg_regs_core_overrideEnHarv2Sup_field overrideEnHarv2Sup_field + * @brief macros for field overrideEnHarv2Sup + * @details override enable for the harvester to supply mode + * @{ + */ +#define SWREG_SWREG_CTRL_2__OVERRIDEENHARV2SUP__SHIFT 16 +#define SWREG_SWREG_CTRL_2__OVERRIDEENHARV2SUP__WIDTH 1 +#define SWREG_SWREG_CTRL_2__OVERRIDEENHARV2SUP__MASK 0x00010000U +#define SWREG_SWREG_CTRL_2__OVERRIDEENHARV2SUP__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define SWREG_SWREG_CTRL_2__OVERRIDEENHARV2SUP__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define SWREG_SWREG_CTRL_2__OVERRIDEENHARV2SUP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define SWREG_SWREG_CTRL_2__OVERRIDEENHARV2SUP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define SWREG_SWREG_CTRL_2__OVERRIDEENHARV2SUP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define SWREG_SWREG_CTRL_2__OVERRIDEENHARV2SUP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +/** @} */ + +/* macros for field enableHarv2Sup_ovr */ +/** + * @defgroup pmu_swreg_regs_core_enableHarv2Sup_ovr_field enableHarv2Sup_ovr_field + * @brief macros for field enableHarv2Sup_ovr + * @details override enable value for the harvester to supply mode + * @{ + */ +#define SWREG_SWREG_CTRL_2__ENABLEHARV2SUP_OVR__SHIFT 17 +#define SWREG_SWREG_CTRL_2__ENABLEHARV2SUP_OVR__WIDTH 1 +#define SWREG_SWREG_CTRL_2__ENABLEHARV2SUP_OVR__MASK 0x00020000U +#define SWREG_SWREG_CTRL_2__ENABLEHARV2SUP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SWREG_SWREG_CTRL_2__ENABLEHARV2SUP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SWREG_SWREG_CTRL_2__ENABLEHARV2SUP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SWREG_SWREG_CTRL_2__ENABLEHARV2SUP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SWREG_SWREG_CTRL_2__ENABLEHARV2SUP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SWREG_SWREG_CTRL_2__ENABLEHARV2SUP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +/** @} */ + +/* macros for field dig_test_out_sel */ +/** + * @defgroup pmu_swreg_regs_core_dig_test_out_sel_field dig_test_out_sel_field + * @brief macros for field dig_test_out_sel + * @details digital bus select signal, as follows:9-0: NC1: a 66% duty-cycle test clock, while holding the switcher in reset10: mode: Store -> VSUP1, Buck11: mode: Battery -> VSUP1, Buck12: mode: Battery -> VSUP1, BuckBoost13: swSampleIndCurrent14: swEnergize15: harvesting16: suppliesReady20-17: supReady21: vbattGood22: vstoreGood23: mustHarvest24: canHarvest28-25: vsupLowB29: indCurrentSign30: clk while the switcher is functioning normally31: NC + * @{ + */ +#define SWREG_SWREG_CTRL_2__DIG_TEST_OUT_SEL__SHIFT 18 +#define SWREG_SWREG_CTRL_2__DIG_TEST_OUT_SEL__WIDTH 5 +#define SWREG_SWREG_CTRL_2__DIG_TEST_OUT_SEL__MASK 0x007c0000U +#define SWREG_SWREG_CTRL_2__DIG_TEST_OUT_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x007c0000U) >> 18) +#define SWREG_SWREG_CTRL_2__DIG_TEST_OUT_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x007c0000U) +#define SWREG_SWREG_CTRL_2__DIG_TEST_OUT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007c0000U) | (((uint32_t)(src) <<\ + 18) & 0x007c0000U) +#define SWREG_SWREG_CTRL_2__DIG_TEST_OUT_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x007c0000U))) +/** @} */ + +/* macros for field clkFixedTime */ +/** + * @defgroup pmu_swreg_regs_core_clkFixedTime_field clkFixedTime_field + * @brief macros for field clkFixedTime + * @details the number of delay units for the low time and the minimum up time of the clock + * @{ + */ +#define SWREG_SWREG_CTRL_2__CLKFIXEDTIME__SHIFT 23 +#define SWREG_SWREG_CTRL_2__CLKFIXEDTIME__WIDTH 3 +#define SWREG_SWREG_CTRL_2__CLKFIXEDTIME__MASK 0x03800000U +#define SWREG_SWREG_CTRL_2__CLKFIXEDTIME__READ(src) \ + (((uint32_t)(src)\ + & 0x03800000U) >> 23) +#define SWREG_SWREG_CTRL_2__CLKFIXEDTIME__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x03800000U) +#define SWREG_SWREG_CTRL_2__CLKFIXEDTIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((uint32_t)(src) <<\ + 23) & 0x03800000U) +#define SWREG_SWREG_CTRL_2__CLKFIXEDTIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x03800000U))) +/** @} */ + +/* macros for field clkUnitDel */ +/** + * @defgroup pmu_swreg_regs_core_clkUnitDel_field clkUnitDel_field + * @brief macros for field clkUnitDel + * @details adjusts the unit delay of the clock + * @{ + */ +#define SWREG_SWREG_CTRL_2__CLKUNITDEL__SHIFT 26 +#define SWREG_SWREG_CTRL_2__CLKUNITDEL__WIDTH 3 +#define SWREG_SWREG_CTRL_2__CLKUNITDEL__MASK 0x1c000000U +#define SWREG_SWREG_CTRL_2__CLKUNITDEL__READ(src) \ + (((uint32_t)(src)\ + & 0x1c000000U) >> 26) +#define SWREG_SWREG_CTRL_2__CLKUNITDEL__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x1c000000U) +#define SWREG_SWREG_CTRL_2__CLKUNITDEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((uint32_t)(src) <<\ + 26) & 0x1c000000U) +#define SWREG_SWREG_CTRL_2__CLKUNITDEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x1c000000U))) +/** @} */ + +/* macros for field spareExt0 */ +/** + * @defgroup pmu_swreg_regs_core_spareExt0_field spareExt0_field + * @brief macros for field spareExt0 + * @details spare external 0 + * @{ + */ +#define SWREG_SWREG_CTRL_2__SPAREEXT0__SHIFT 29 +#define SWREG_SWREG_CTRL_2__SPAREEXT0__WIDTH 3 +#define SWREG_SWREG_CTRL_2__SPAREEXT0__MASK 0xe0000000U +#define SWREG_SWREG_CTRL_2__SPAREEXT0__READ(src) \ + (((uint32_t)(src)\ + & 0xe0000000U) >> 29) +#define SWREG_SWREG_CTRL_2__SPAREEXT0__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0xe0000000U) +#define SWREG_SWREG_CTRL_2__SPAREEXT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((uint32_t)(src) <<\ + 29) & 0xe0000000U) +#define SWREG_SWREG_CTRL_2__SPAREEXT0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0xe0000000U))) +/** @} */ +#define SWREG_SWREG_CTRL_2__TYPE uint32_t +#define SWREG_SWREG_CTRL_2__READ 0xffffffffU +#define SWREG_SWREG_CTRL_2__WRITE 0xffffffffU +#define SWREG_SWREG_CTRL_2__PRESERVED 0x00000000U + +#endif /* __SWREG_SWREG_CTRL_2_MACRO__ */ + +/** @} end of swreg_ctrl_2 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_swreg_ctrl_3 */ +/** + * @defgroup pmu_swreg_regs_core_swreg_ctrl_3 swreg_ctrl_3 + * @brief swreg reg 3 definitions. + * @{ + */ +#ifndef __SWREG_SWREG_CTRL_3_MACRO__ +#define __SWREG_SWREG_CTRL_3_MACRO__ + +/* macros for field skipSample */ +/** + * @defgroup pmu_swreg_regs_core_skipSample_field skipSample_field + * @brief macros for field skipSample + * @details skip the sampling state after the idle state + * @{ + */ +#define SWREG_SWREG_CTRL_3__SKIPSAMPLE__SHIFT 0 +#define SWREG_SWREG_CTRL_3__SKIPSAMPLE__WIDTH 1 +#define SWREG_SWREG_CTRL_3__SKIPSAMPLE__MASK 0x00000001U +#define SWREG_SWREG_CTRL_3__SKIPSAMPLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWREG_SWREG_CTRL_3__SKIPSAMPLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWREG_SWREG_CTRL_3__SKIPSAMPLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SWREG_SWREG_CTRL_3__SKIPSAMPLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SWREG_SWREG_CTRL_3__SKIPSAMPLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SWREG_SWREG_CTRL_3__SKIPSAMPLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +/** @} */ + +/* macros for field timePlanLong */ +/** + * @defgroup pmu_swreg_regs_core_timePlanLong_field timePlanLong_field + * @brief macros for field timePlanLong + * @details plan (and sample, if used) state duration after dump. The leftover inductor current is dissipated during this time + * @{ + */ +#define SWREG_SWREG_CTRL_3__TIMEPLANLONG__SHIFT 1 +#define SWREG_SWREG_CTRL_3__TIMEPLANLONG__WIDTH 7 +#define SWREG_SWREG_CTRL_3__TIMEPLANLONG__MASK 0x000000feU +#define SWREG_SWREG_CTRL_3__TIMEPLANLONG__READ(src) \ + (((uint32_t)(src)\ + & 0x000000feU) >> 1) +#define SWREG_SWREG_CTRL_3__TIMEPLANLONG__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000000feU) +#define SWREG_SWREG_CTRL_3__TIMEPLANLONG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000feU) | (((uint32_t)(src) <<\ + 1) & 0x000000feU) +#define SWREG_SWREG_CTRL_3__TIMEPLANLONG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000000feU))) +/** @} */ + +/* macros for field timePlanLong_Start */ +/** + * @defgroup pmu_swreg_regs_core_timePlanLong_Start_field timePlanLong_Start_field + * @brief macros for field timePlanLong_Start + * @details plan (and sample, if used) state duration after dump before the supplies are ready (consider reducing to allow providing higher current at startup) + * @{ + */ +#define SWREG_SWREG_CTRL_3__TIMEPLANLONG_START__SHIFT 8 +#define SWREG_SWREG_CTRL_3__TIMEPLANLONG_START__WIDTH 7 +#define SWREG_SWREG_CTRL_3__TIMEPLANLONG_START__MASK 0x00007f00U +#define SWREG_SWREG_CTRL_3__TIMEPLANLONG_START__READ(src) \ + (((uint32_t)(src)\ + & 0x00007f00U) >> 8) +#define SWREG_SWREG_CTRL_3__TIMEPLANLONG_START__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00007f00U) +#define SWREG_SWREG_CTRL_3__TIMEPLANLONG_START__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007f00U) | (((uint32_t)(src) <<\ + 8) & 0x00007f00U) +#define SWREG_SWREG_CTRL_3__TIMEPLANLONG_START__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00007f00U))) +/** @} */ + +/* macros for field timePlanShort */ +/** + * @defgroup pmu_swreg_regs_core_timePlanShort_field timePlanShort_field + * @brief macros for field timePlanShort + * @details plan (and sample, if used) state duration when the previous state is not dump + * @{ + */ +#define SWREG_SWREG_CTRL_3__TIMEPLANSHORT__SHIFT 15 +#define SWREG_SWREG_CTRL_3__TIMEPLANSHORT__WIDTH 3 +#define SWREG_SWREG_CTRL_3__TIMEPLANSHORT__MASK 0x00038000U +#define SWREG_SWREG_CTRL_3__TIMEPLANSHORT__READ(src) \ + (((uint32_t)(src)\ + & 0x00038000U) >> 15) +#define SWREG_SWREG_CTRL_3__TIMEPLANSHORT__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00038000U) +#define SWREG_SWREG_CTRL_3__TIMEPLANSHORT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((uint32_t)(src) <<\ + 15) & 0x00038000U) +#define SWREG_SWREG_CTRL_3__TIMEPLANSHORT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00038000U))) +/** @} */ + +/* macros for field timeStep_Step */ +/** + * @defgroup pmu_swreg_regs_core_timeStep_Step_field timeStep_Step_field + * @brief macros for field timeStep_Step + * @details step in adjusting the variable timestep + * @{ + */ +#define SWREG_SWREG_CTRL_3__TIMESTEP_STEP__SHIFT 18 +#define SWREG_SWREG_CTRL_3__TIMESTEP_STEP__WIDTH 3 +#define SWREG_SWREG_CTRL_3__TIMESTEP_STEP__MASK 0x001c0000U +#define SWREG_SWREG_CTRL_3__TIMESTEP_STEP__READ(src) \ + (((uint32_t)(src)\ + & 0x001c0000U) >> 18) +#define SWREG_SWREG_CTRL_3__TIMESTEP_STEP__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x001c0000U) +#define SWREG_SWREG_CTRL_3__TIMESTEP_STEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((uint32_t)(src) <<\ + 18) & 0x001c0000U) +#define SWREG_SWREG_CTRL_3__TIMESTEP_STEP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x001c0000U))) +/** @} */ + +/* macros for field timeStep_Max */ +/** + * @defgroup pmu_swreg_regs_core_timeStep_Max_field timeStep_Max_field + * @brief macros for field timeStep_Max + * @details maximum timestep + * @{ + */ +#define SWREG_SWREG_CTRL_3__TIMESTEP_MAX__SHIFT 21 +#define SWREG_SWREG_CTRL_3__TIMESTEP_MAX__WIDTH 5 +#define SWREG_SWREG_CTRL_3__TIMESTEP_MAX__MASK 0x03e00000U +#define SWREG_SWREG_CTRL_3__TIMESTEP_MAX__READ(src) \ + (((uint32_t)(src)\ + & 0x03e00000U) >> 21) +#define SWREG_SWREG_CTRL_3__TIMESTEP_MAX__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x03e00000U) +#define SWREG_SWREG_CTRL_3__TIMESTEP_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03e00000U) | (((uint32_t)(src) <<\ + 21) & 0x03e00000U) +#define SWREG_SWREG_CTRL_3__TIMESTEP_MAX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x03e00000U))) +/** @} */ + +/* macros for field timeStep_FastSettle */ +/** + * @defgroup pmu_swreg_regs_core_timeStep_FastSettle_field timeStep_FastSettle_field + * @brief macros for field timeStep_FastSettle + * @details timeStep during fast settling + * @{ + */ +#define SWREG_SWREG_CTRL_3__TIMESTEP_FASTSETTLE__SHIFT 26 +#define SWREG_SWREG_CTRL_3__TIMESTEP_FASTSETTLE__WIDTH 3 +#define SWREG_SWREG_CTRL_3__TIMESTEP_FASTSETTLE__MASK 0x1c000000U +#define SWREG_SWREG_CTRL_3__TIMESTEP_FASTSETTLE__READ(src) \ + (((uint32_t)(src)\ + & 0x1c000000U) >> 26) +#define SWREG_SWREG_CTRL_3__TIMESTEP_FASTSETTLE__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x1c000000U) +#define SWREG_SWREG_CTRL_3__TIMESTEP_FASTSETTLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((uint32_t)(src) <<\ + 26) & 0x1c000000U) +#define SWREG_SWREG_CTRL_3__TIMESTEP_FASTSETTLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x1c000000U))) +/** @} */ + +/* macros for field spareExt1 */ +/** + * @defgroup pmu_swreg_regs_core_spareExt1_field spareExt1_field + * @brief macros for field spareExt1 + * @details spare external 1 + * @{ + */ +#define SWREG_SWREG_CTRL_3__SPAREEXT1__SHIFT 29 +#define SWREG_SWREG_CTRL_3__SPAREEXT1__WIDTH 3 +#define SWREG_SWREG_CTRL_3__SPAREEXT1__MASK 0xe0000000U +#define SWREG_SWREG_CTRL_3__SPAREEXT1__READ(src) \ + (((uint32_t)(src)\ + & 0xe0000000U) >> 29) +#define SWREG_SWREG_CTRL_3__SPAREEXT1__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0xe0000000U) +#define SWREG_SWREG_CTRL_3__SPAREEXT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((uint32_t)(src) <<\ + 29) & 0xe0000000U) +#define SWREG_SWREG_CTRL_3__SPAREEXT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0xe0000000U))) +/** @} */ +#define SWREG_SWREG_CTRL_3__TYPE uint32_t +#define SWREG_SWREG_CTRL_3__READ 0xffffffffU +#define SWREG_SWREG_CTRL_3__WRITE 0xffffffffU +#define SWREG_SWREG_CTRL_3__PRESERVED 0x00000000U + +#endif /* __SWREG_SWREG_CTRL_3_MACRO__ */ + +/** @} end of swreg_ctrl_3 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_swreg_ctrl_4 */ +/** + * @defgroup pmu_swreg_regs_core_swreg_ctrl_4 swreg_ctrl_4 + * @brief swreg reg 4 definitions. + * @{ + */ +#ifndef __SWREG_SWREG_CTRL_4_MACRO__ +#define __SWREG_SWREG_CTRL_4_MACRO__ + +/* macros for field attempt_Enter_CCM */ +/** + * @defgroup pmu_swreg_regs_core_attempt_Enter_CCM_field attempt_Enter_CCM_field + * @brief macros for field attempt_Enter_CCM + * @details number of DCM consecutive attempts after which if the supply is still low CCM mode starts + * @{ + */ +#define SWREG_SWREG_CTRL_4__ATTEMPT_ENTER_CCM__SHIFT 0 +#define SWREG_SWREG_CTRL_4__ATTEMPT_ENTER_CCM__WIDTH 4 +#define SWREG_SWREG_CTRL_4__ATTEMPT_ENTER_CCM__MASK 0x0000000fU +#define SWREG_SWREG_CTRL_4__ATTEMPT_ENTER_CCM__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define SWREG_SWREG_CTRL_4__ATTEMPT_ENTER_CCM__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define SWREG_SWREG_CTRL_4__ATTEMPT_ENTER_CCM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define SWREG_SWREG_CTRL_4__ATTEMPT_ENTER_CCM__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +/** @} */ + +/* macros for field attempt_Shift_CCM_Gear */ +/** + * @defgroup pmu_swreg_regs_core_attempt_Shift_CCM_Gear_field attempt_Shift_CCM_Gear_field + * @brief macros for field attempt_Shift_CCM_Gear + * @details number of CCM consecutive attempts after which if the supply is still low the CCM gear increases + * @{ + */ +#define SWREG_SWREG_CTRL_4__ATTEMPT_SHIFT_CCM_GEAR__SHIFT 4 +#define SWREG_SWREG_CTRL_4__ATTEMPT_SHIFT_CCM_GEAR__WIDTH 4 +#define SWREG_SWREG_CTRL_4__ATTEMPT_SHIFT_CCM_GEAR__MASK 0x000000f0U +#define SWREG_SWREG_CTRL_4__ATTEMPT_SHIFT_CCM_GEAR__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define SWREG_SWREG_CTRL_4__ATTEMPT_SHIFT_CCM_GEAR__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x000000f0U) +#define SWREG_SWREG_CTRL_4__ATTEMPT_SHIFT_CCM_GEAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define SWREG_SWREG_CTRL_4__ATTEMPT_SHIFT_CCM_GEAR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +/** @} */ + +/* macros for field CCM_CyclesMax */ +/** + * @defgroup pmu_swreg_regs_core_CCM_CyclesMax_field CCM_CyclesMax_field + * @brief macros for field CCM_CyclesMax + * @details maximum number of energize-dump cycles in the same CCM session (consider increasing for higher output power) + * @{ + */ +#define SWREG_SWREG_CTRL_4__CCM_CYCLESMAX__SHIFT 8 +#define SWREG_SWREG_CTRL_4__CCM_CYCLESMAX__WIDTH 3 +#define SWREG_SWREG_CTRL_4__CCM_CYCLESMAX__MASK 0x00000700U +#define SWREG_SWREG_CTRL_4__CCM_CYCLESMAX__READ(src) \ + (((uint32_t)(src)\ + & 0x00000700U) >> 8) +#define SWREG_SWREG_CTRL_4__CCM_CYCLESMAX__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000700U) +#define SWREG_SWREG_CTRL_4__CCM_CYCLESMAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((uint32_t)(src) <<\ + 8) & 0x00000700U) +#define SWREG_SWREG_CTRL_4__CCM_CYCLESMAX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000700U))) +/** @} */ + +/* macros for field CCM_CyclesMin */ +/** + * @defgroup pmu_swreg_regs_core_CCM_CyclesMin_field CCM_CyclesMin_field + * @brief macros for field CCM_CyclesMin + * @details minimum number of energize-dump cycles in the same CCM session + * @{ + */ +#define SWREG_SWREG_CTRL_4__CCM_CYCLESMIN__SHIFT 11 +#define SWREG_SWREG_CTRL_4__CCM_CYCLESMIN__WIDTH 3 +#define SWREG_SWREG_CTRL_4__CCM_CYCLESMIN__MASK 0x00003800U +#define SWREG_SWREG_CTRL_4__CCM_CYCLESMIN__READ(src) \ + (((uint32_t)(src)\ + & 0x00003800U) >> 11) +#define SWREG_SWREG_CTRL_4__CCM_CYCLESMIN__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00003800U) +#define SWREG_SWREG_CTRL_4__CCM_CYCLESMIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((uint32_t)(src) <<\ + 11) & 0x00003800U) +#define SWREG_SWREG_CTRL_4__CCM_CYCLESMIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00003800U))) +/** @} */ + +/* macros for field CCM_GearInit */ +/** + * @defgroup pmu_swreg_regs_core_CCM_GearInit_field CCM_GearInit_field + * @brief macros for field CCM_GearInit + * @details initial CCM gear + * @{ + */ +#define SWREG_SWREG_CTRL_4__CCM_GEARINIT__SHIFT 14 +#define SWREG_SWREG_CTRL_4__CCM_GEARINIT__WIDTH 4 +#define SWREG_SWREG_CTRL_4__CCM_GEARINIT__MASK 0x0003c000U +#define SWREG_SWREG_CTRL_4__CCM_GEARINIT__READ(src) \ + (((uint32_t)(src)\ + & 0x0003c000U) >> 14) +#define SWREG_SWREG_CTRL_4__CCM_GEARINIT__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0003c000U) +#define SWREG_SWREG_CTRL_4__CCM_GEARINIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003c000U) | (((uint32_t)(src) <<\ + 14) & 0x0003c000U) +#define SWREG_SWREG_CTRL_4__CCM_GEARINIT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0003c000U))) +/** @} */ + +/* macros for field easierEnterCCM */ +/** + * @defgroup pmu_swreg_regs_core_easierEnterCCM_field easierEnterCCM_field + * @brief macros for field easierEnterCCM + * @details relaxes the requirements on settling to steady-steaty to allow entering CCM + * @{ + */ +#define SWREG_SWREG_CTRL_4__EASIERENTERCCM__SHIFT 18 +#define SWREG_SWREG_CTRL_4__EASIERENTERCCM__WIDTH 1 +#define SWREG_SWREG_CTRL_4__EASIERENTERCCM__MASK 0x00040000U +#define SWREG_SWREG_CTRL_4__EASIERENTERCCM__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SWREG_SWREG_CTRL_4__EASIERENTERCCM__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SWREG_SWREG_CTRL_4__EASIERENTERCCM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SWREG_SWREG_CTRL_4__EASIERENTERCCM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SWREG_SWREG_CTRL_4__EASIERENTERCCM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SWREG_SWREG_CTRL_4__EASIERENTERCCM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +/** @} */ + +/* macros for field ateTest */ +/** + * @defgroup pmu_swreg_regs_core_ateTest_field ateTest_field + * @brief macros for field ateTest + * @details turns on ATE testing To close a pair source and destination switch, set ateTest=1, select the desired mode by setting ateModeSel, ateBuck, ateBoost and set ateEnerg=1/0 for energize/dump + * @{ + */ +#define SWREG_SWREG_CTRL_4__ATETEST__SHIFT 19 +#define SWREG_SWREG_CTRL_4__ATETEST__WIDTH 1 +#define SWREG_SWREG_CTRL_4__ATETEST__MASK 0x00080000U +#define SWREG_SWREG_CTRL_4__ATETEST__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define SWREG_SWREG_CTRL_4__ATETEST__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define SWREG_SWREG_CTRL_4__ATETEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define SWREG_SWREG_CTRL_4__ATETEST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define SWREG_SWREG_CTRL_4__ATETEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define SWREG_SWREG_CTRL_4__ATETEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +/** @} */ + +/* macros for field ateModeSel */ +/** + * @defgroup pmu_swreg_regs_core_ateModeSel_field ateModeSel_field + * @brief macros for field ateModeSel + * @details the power transfer mode activated in ate testing (Better to change the default to 4'b1111 which corresponds to none) + * @{ + */ +#define SWREG_SWREG_CTRL_4__ATEMODESEL__SHIFT 20 +#define SWREG_SWREG_CTRL_4__ATEMODESEL__WIDTH 4 +#define SWREG_SWREG_CTRL_4__ATEMODESEL__MASK 0x00f00000U +#define SWREG_SWREG_CTRL_4__ATEMODESEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00f00000U) >> 20) +#define SWREG_SWREG_CTRL_4__ATEMODESEL__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00f00000U) +#define SWREG_SWREG_CTRL_4__ATEMODESEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f00000U) | (((uint32_t)(src) <<\ + 20) & 0x00f00000U) +#define SWREG_SWREG_CTRL_4__ATEMODESEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00f00000U))) +/** @} */ + +/* macros for field ateBuck */ +/** + * @defgroup pmu_swreg_regs_core_ateBuck_field ateBuck_field + * @brief macros for field ateBuck + * @details buck mode in ate testing + * @{ + */ +#define SWREG_SWREG_CTRL_4__ATEBUCK__SHIFT 24 +#define SWREG_SWREG_CTRL_4__ATEBUCK__WIDTH 1 +#define SWREG_SWREG_CTRL_4__ATEBUCK__MASK 0x01000000U +#define SWREG_SWREG_CTRL_4__ATEBUCK__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SWREG_SWREG_CTRL_4__ATEBUCK__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define SWREG_SWREG_CTRL_4__ATEBUCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define SWREG_SWREG_CTRL_4__ATEBUCK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define SWREG_SWREG_CTRL_4__ATEBUCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SWREG_SWREG_CTRL_4__ATEBUCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +/** @} */ + +/* macros for field ateBoost */ +/** + * @defgroup pmu_swreg_regs_core_ateBoost_field ateBoost_field + * @brief macros for field ateBoost + * @details boost mode in ate testing + * @{ + */ +#define SWREG_SWREG_CTRL_4__ATEBOOST__SHIFT 25 +#define SWREG_SWREG_CTRL_4__ATEBOOST__WIDTH 1 +#define SWREG_SWREG_CTRL_4__ATEBOOST__MASK 0x02000000U +#define SWREG_SWREG_CTRL_4__ATEBOOST__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define SWREG_SWREG_CTRL_4__ATEBOOST__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define SWREG_SWREG_CTRL_4__ATEBOOST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define SWREG_SWREG_CTRL_4__ATEBOOST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define SWREG_SWREG_CTRL_4__ATEBOOST__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define SWREG_SWREG_CTRL_4__ATEBOOST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +/** @} */ + +/* macros for field ateEnerg */ +/** + * @defgroup pmu_swreg_regs_core_ateEnerg_field ateEnerg_field + * @brief macros for field ateEnerg + * @details energize in ate testing + * @{ + */ +#define SWREG_SWREG_CTRL_4__ATEENERG__SHIFT 26 +#define SWREG_SWREG_CTRL_4__ATEENERG__WIDTH 1 +#define SWREG_SWREG_CTRL_4__ATEENERG__MASK 0x04000000U +#define SWREG_SWREG_CTRL_4__ATEENERG__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define SWREG_SWREG_CTRL_4__ATEENERG__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define SWREG_SWREG_CTRL_4__ATEENERG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define SWREG_SWREG_CTRL_4__ATEENERG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define SWREG_SWREG_CTRL_4__ATEENERG__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define SWREG_SWREG_CTRL_4__ATEENERG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +/** @} */ + +/* macros for field ateSampleIndCurrent */ +/** + * @defgroup pmu_swreg_regs_core_ateSampleIndCurrent_field ateSampleIndCurrent_field + * @brief macros for field ateSampleIndCurrent + * @details sample inductor current sign in ate testing. To test the Zero Current Crossing comparator Activate a mode with ateModeSel, ateBuck in dump configuration with ateEnerg=0. It can be buck-boost or buck, but not boost. Set ateSampleIndCurrent=1. Apply a small positive/negative current to the source terminal of the inductor, which is grounded during dump. Terminate the mode by setting ateModeSel=4'd13, which will make the current flow through the internal sense resistor Read the indCurrentSign bit in the readout register, it should be 0/1 + * @{ + */ +#define SWREG_SWREG_CTRL_4__ATESAMPLEINDCURRENT__SHIFT 27 +#define SWREG_SWREG_CTRL_4__ATESAMPLEINDCURRENT__WIDTH 1 +#define SWREG_SWREG_CTRL_4__ATESAMPLEINDCURRENT__MASK 0x08000000U +#define SWREG_SWREG_CTRL_4__ATESAMPLEINDCURRENT__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define SWREG_SWREG_CTRL_4__ATESAMPLEINDCURRENT__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define SWREG_SWREG_CTRL_4__ATESAMPLEINDCURRENT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define SWREG_SWREG_CTRL_4__ATESAMPLEINDCURRENT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define SWREG_SWREG_CTRL_4__ATESAMPLEINDCURRENT__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define SWREG_SWREG_CTRL_4__ATESAMPLEINDCURRENT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +/** @} */ +#define SWREG_SWREG_CTRL_4__TYPE uint32_t +#define SWREG_SWREG_CTRL_4__READ 0x0fffffffU +#define SWREG_SWREG_CTRL_4__WRITE 0x0fffffffU +#define SWREG_SWREG_CTRL_4__PRESERVED 0x00000000U + +#endif /* __SWREG_SWREG_CTRL_4_MACRO__ */ + +/** @} end of swreg_ctrl_4 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_swreg_ctrl_5 */ +/** + * @defgroup pmu_swreg_regs_core_swreg_ctrl_5 swreg_ctrl_5 + * @brief swreg reg 5 definitions. + * @{ + */ +#ifndef __SWREG_SWREG_CTRL_5_MACRO__ +#define __SWREG_SWREG_CTRL_5_MACRO__ + +/* macros for field timeEnergStart_Harvest */ +/** + * @defgroup pmu_swreg_regs_core_timeEnergStart_Harvest_field timeEnergStart_Harvest_field + * @brief macros for field timeEnergStart_Harvest + * @details initial energize time when the source is the harvester, before the distination is ready, common for all destinations + * @{ + */ +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_HARVEST__SHIFT 0 +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_HARVEST__WIDTH 7 +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_HARVEST__MASK 0x0000007fU +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_HARVEST__READ(src) \ + ((uint32_t)(src)\ + & 0x0000007fU) +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_HARVEST__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000007fU) +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_HARVEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_HARVEST__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000007fU))) +/** @} */ + +/* macros for field timeEnergStart_Store */ +/** + * @defgroup pmu_swreg_regs_core_timeEnergStart_Store_field timeEnergStart_Store_field + * @brief macros for field timeEnergStart_Store + * @details initial energize time when the source is the store, before the distination is ready, common for all destinations + * @{ + */ +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_STORE__SHIFT 7 +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_STORE__WIDTH 7 +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_STORE__MASK 0x00003f80U +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_STORE__READ(src) \ + (((uint32_t)(src)\ + & 0x00003f80U) >> 7) +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_STORE__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00003f80U) +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_STORE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((uint32_t)(src) <<\ + 7) & 0x00003f80U) +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_STORE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00003f80U))) +/** @} */ + +/* macros for field timeEnergStart_Battery */ +/** + * @defgroup pmu_swreg_regs_core_timeEnergStart_Battery_field timeEnergStart_Battery_field + * @brief macros for field timeEnergStart_Battery + * @details initial energize time when the source is the battery, before the distination is ready, common for all destinations + * @{ + */ +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_BATTERY__SHIFT 14 +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_BATTERY__WIDTH 7 +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_BATTERY__MASK 0x001fc000U +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_BATTERY__READ(src) \ + (((uint32_t)(src)\ + & 0x001fc000U) >> 14) +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_BATTERY__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x001fc000U) +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_BATTERY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001fc000U) | (((uint32_t)(src) <<\ + 14) & 0x001fc000U) +#define SWREG_SWREG_CTRL_5__TIMEENERGSTART_BATTERY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x001fc000U))) +/** @} */ + +/* macros for field timeTarget_Harvest_Store */ +/** + * @defgroup pmu_swreg_regs_core_timeTarget_Harvest_Store_field timeTarget_Harvest_Store_field + * @brief macros for field timeTarget_Harvest_Store + * @details target time in Steady State for the Harvester->Store mode + * @{ + */ +#define SWREG_SWREG_CTRL_5__TIMETARGET_HARVEST_STORE__SHIFT 21 +#define SWREG_SWREG_CTRL_5__TIMETARGET_HARVEST_STORE__WIDTH 7 +#define SWREG_SWREG_CTRL_5__TIMETARGET_HARVEST_STORE__MASK 0x0fe00000U +#define SWREG_SWREG_CTRL_5__TIMETARGET_HARVEST_STORE__READ(src) \ + (((uint32_t)(src)\ + & 0x0fe00000U) >> 21) +#define SWREG_SWREG_CTRL_5__TIMETARGET_HARVEST_STORE__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x0fe00000U) +#define SWREG_SWREG_CTRL_5__TIMETARGET_HARVEST_STORE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fe00000U) | (((uint32_t)(src) <<\ + 21) & 0x0fe00000U) +#define SWREG_SWREG_CTRL_5__TIMETARGET_HARVEST_STORE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x0fe00000U))) +/** @} */ +#define SWREG_SWREG_CTRL_5__TYPE uint32_t +#define SWREG_SWREG_CTRL_5__READ 0x0fffffffU +#define SWREG_SWREG_CTRL_5__WRITE 0x0fffffffU +#define SWREG_SWREG_CTRL_5__PRESERVED 0x00000000U + +#endif /* __SWREG_SWREG_CTRL_5_MACRO__ */ + +/** @} end of swreg_ctrl_5 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_swreg_ctrl_6 */ +/** + * @defgroup pmu_swreg_regs_core_swreg_ctrl_6 swreg_ctrl_6 + * @brief swreg reg 6 definitions. + * @{ + */ +#ifndef __SWREG_SWREG_CTRL_6_MACRO__ +#define __SWREG_SWREG_CTRL_6_MACRO__ + +/* macros for field fixDumpTime_Harvest_Store */ +/** + * @defgroup pmu_swreg_regs_core_fixDumpTime_Harvest_Store_field fixDumpTime_Harvest_Store_field + * @brief macros for field fixDumpTime_Harvest_Store + * @details if 1 the dump time is fixed otherwise the energize time is fixed in steady state for the Harvester->Store mode + * @{ + */ +#define SWREG_SWREG_CTRL_6__FIXDUMPTIME_HARVEST_STORE__SHIFT 0 +#define SWREG_SWREG_CTRL_6__FIXDUMPTIME_HARVEST_STORE__WIDTH 1 +#define SWREG_SWREG_CTRL_6__FIXDUMPTIME_HARVEST_STORE__MASK 0x00000001U +#define SWREG_SWREG_CTRL_6__FIXDUMPTIME_HARVEST_STORE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWREG_SWREG_CTRL_6__FIXDUMPTIME_HARVEST_STORE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWREG_SWREG_CTRL_6__FIXDUMPTIME_HARVEST_STORE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SWREG_SWREG_CTRL_6__FIXDUMPTIME_HARVEST_STORE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SWREG_SWREG_CTRL_6__FIXDUMPTIME_HARVEST_STORE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SWREG_SWREG_CTRL_6__FIXDUMPTIME_HARVEST_STORE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +/** @} */ + +/* macros for field timeDumpTarget_dvdd */ +/** + * @defgroup pmu_swreg_regs_core_timeDumpTarget_dvdd_field timeDumpTarget_dvdd_field + * @brief macros for field timeDumpTarget_dvdd + * @details target dump time in Steady State for dvdd, all sources + * @{ + */ +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_DVDD__SHIFT 1 +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_DVDD__WIDTH 7 +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_DVDD__MASK 0x000000feU +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_DVDD__READ(src) \ + (((uint32_t)(src)\ + & 0x000000feU) >> 1) +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_DVDD__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000000feU) +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_DVDD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000feU) | (((uint32_t)(src) <<\ + 1) & 0x000000feU) +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_DVDD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000000feU))) +/** @} */ + +/* macros for field timeDumpTarget_vddaux */ +/** + * @defgroup pmu_swreg_regs_core_timeDumpTarget_vddaux_field timeDumpTarget_vddaux_field + * @brief macros for field timeDumpTarget_vddaux + * @details target dump time in Steady State for vddaux, all sources + * @{ + */ +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_VDDAUX__SHIFT 8 +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_VDDAUX__WIDTH 7 +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_VDDAUX__MASK 0x00007f00U +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_VDDAUX__READ(src) \ + (((uint32_t)(src)\ + & 0x00007f00U) >> 8) +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_VDDAUX__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00007f00U) +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_VDDAUX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007f00U) | (((uint32_t)(src) <<\ + 8) & 0x00007f00U) +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_VDDAUX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00007f00U))) +/** @} */ + +/* macros for field timeDumpTarget_vddio */ +/** + * @defgroup pmu_swreg_regs_core_timeDumpTarget_vddio_field timeDumpTarget_vddio_field + * @brief macros for field timeDumpTarget_vddio + * @details target dump time in Steady State for vddio, all sources + * @{ + */ +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_VDDIO__SHIFT 15 +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_VDDIO__WIDTH 7 +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_VDDIO__MASK 0x003f8000U +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_VDDIO__READ(src) \ + (((uint32_t)(src)\ + & 0x003f8000U) >> 15) +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_VDDIO__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x003f8000U) +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_VDDIO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f8000U) | (((uint32_t)(src) <<\ + 15) & 0x003f8000U) +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_VDDIO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x003f8000U))) +/** @} */ + +/* macros for field timeDumpTarget_avdd */ +/** + * @defgroup pmu_swreg_regs_core_timeDumpTarget_avdd_field timeDumpTarget_avdd_field + * @brief macros for field timeDumpTarget_avdd + * @details target dump time in Steady State for avdd, all sources + * @{ + */ +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_AVDD__SHIFT 22 +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_AVDD__WIDTH 7 +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_AVDD__MASK 0x1fc00000U +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_AVDD__READ(src) \ + (((uint32_t)(src)\ + & 0x1fc00000U) >> 22) +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_AVDD__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x1fc00000U) +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_AVDD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1fc00000U) | (((uint32_t)(src) <<\ + 22) & 0x1fc00000U) +#define SWREG_SWREG_CTRL_6__TIMEDUMPTARGET_AVDD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x1fc00000U))) +/** @} */ + +/* macros for field timeMin */ +/** + * @defgroup pmu_swreg_regs_core_timeMin_field timeMin_field + * @brief macros for field timeMin + * @details The min energize or dump time allowed. Does not apply to CCM mode. + * @{ + */ +#define SWREG_SWREG_CTRL_6__TIMEMIN__SHIFT 29 +#define SWREG_SWREG_CTRL_6__TIMEMIN__WIDTH 3 +#define SWREG_SWREG_CTRL_6__TIMEMIN__MASK 0xe0000000U +#define SWREG_SWREG_CTRL_6__TIMEMIN__READ(src) \ + (((uint32_t)(src)\ + & 0xe0000000U) >> 29) +#define SWREG_SWREG_CTRL_6__TIMEMIN__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0xe0000000U) +#define SWREG_SWREG_CTRL_6__TIMEMIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((uint32_t)(src) <<\ + 29) & 0xe0000000U) +#define SWREG_SWREG_CTRL_6__TIMEMIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0xe0000000U))) +/** @} */ +#define SWREG_SWREG_CTRL_6__TYPE uint32_t +#define SWREG_SWREG_CTRL_6__READ 0xffffffffU +#define SWREG_SWREG_CTRL_6__WRITE 0xffffffffU +#define SWREG_SWREG_CTRL_6__PRESERVED 0x00000000U + +#endif /* __SWREG_SWREG_CTRL_6_MACRO__ */ + +/** @} end of swreg_ctrl_6 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_swreg_ctrl_7 */ +/** + * @defgroup pmu_swreg_regs_core_swreg_ctrl_7 swreg_ctrl_7 + * @brief swreg reg 7 definitions. + * @{ + */ +#ifndef __SWREG_SWREG_CTRL_7_MACRO__ +#define __SWREG_SWREG_CTRL_7_MACRO__ + +/* macros for field timeMax */ +/** + * @defgroup pmu_swreg_regs_core_timeMax_field timeMax_field + * @brief macros for field timeMax + * @details The max energize or dump time allowed. Does not apply to CCM mode. + * @{ + */ +#define SWREG_SWREG_CTRL_7__TIMEMAX__SHIFT 0 +#define SWREG_SWREG_CTRL_7__TIMEMAX__WIDTH 9 +#define SWREG_SWREG_CTRL_7__TIMEMAX__MASK 0x000001ffU +#define SWREG_SWREG_CTRL_7__TIMEMAX__READ(src) ((uint32_t)(src) & 0x000001ffU) +#define SWREG_SWREG_CTRL_7__TIMEMAX__WRITE(src) ((uint32_t)(src) & 0x000001ffU) +#define SWREG_SWREG_CTRL_7__TIMEMAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((uint32_t)(src) &\ + 0x000001ffU) +#define SWREG_SWREG_CTRL_7__TIMEMAX__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000001ffU))) +/** @} */ + +/* macros for field spareInt */ +/** + * @defgroup pmu_swreg_regs_core_spareInt_field spareInt_field + * @brief macros for field spareInt + * @details spare internal 0: when set to 1 gates the harvesting signal with (canHarvest & !mustHarvest) 1: if 1, the PMOS device is used for the dvdd switch (can be overriden with overridePN) 2: if 1, the PMOS device is used for the avdd switch (can be overriden with overridePN) + * @{ + */ +#define SWREG_SWREG_CTRL_7__SPAREINT__SHIFT 10 +#define SWREG_SWREG_CTRL_7__SPAREINT__WIDTH 22 +#define SWREG_SWREG_CTRL_7__SPAREINT__MASK 0xfffffc00U +#define SWREG_SWREG_CTRL_7__SPAREINT__READ(src) \ + (((uint32_t)(src)\ + & 0xfffffc00U) >> 10) +#define SWREG_SWREG_CTRL_7__SPAREINT__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0xfffffc00U) +#define SWREG_SWREG_CTRL_7__SPAREINT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffffc00U) | (((uint32_t)(src) <<\ + 10) & 0xfffffc00U) +#define SWREG_SWREG_CTRL_7__SPAREINT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0xfffffc00U))) +/** @} */ +#define SWREG_SWREG_CTRL_7__TYPE uint32_t +#define SWREG_SWREG_CTRL_7__READ 0xfffffdffU +#define SWREG_SWREG_CTRL_7__WRITE 0xfffffdffU +#define SWREG_SWREG_CTRL_7__PRESERVED 0x00000000U + +#endif /* __SWREG_SWREG_CTRL_7_MACRO__ */ + +/** @} end of swreg_ctrl_7 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_swreg_readout */ +/** + * @defgroup pmu_swreg_regs_core_swreg_readout swreg_readout + * @brief swreg readout bits definitions. + * @{ + */ +#ifndef __SWREG_SWREG_READOUT_MACRO__ +#define __SWREG_SWREG_READOUT_MACRO__ + +/* macros for field vsupLowB */ +/** + * @defgroup pmu_swreg_regs_core_vsupLowB_field vsupLowB_field + * @brief macros for field vsupLowB + * @details supply sensing comparators for the four supplies + * @{ + */ +#define SWREG_SWREG_READOUT__VSUPLOWB__SHIFT 0 +#define SWREG_SWREG_READOUT__VSUPLOWB__WIDTH 4 +#define SWREG_SWREG_READOUT__VSUPLOWB__MASK 0x0000000fU +#define SWREG_SWREG_READOUT__VSUPLOWB__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +/** @} */ + +/* macros for field vbattGood */ +/** + * @defgroup pmu_swreg_regs_core_vbattGood_field vbattGood_field + * @brief macros for field vbattGood + * @details vbatt good comparator + * @{ + */ +#define SWREG_SWREG_READOUT__VBATTGOOD__SHIFT 4 +#define SWREG_SWREG_READOUT__VBATTGOOD__WIDTH 1 +#define SWREG_SWREG_READOUT__VBATTGOOD__MASK 0x00000010U +#define SWREG_SWREG_READOUT__VBATTGOOD__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define SWREG_SWREG_READOUT__VBATTGOOD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define SWREG_SWREG_READOUT__VBATTGOOD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +/** @} */ + +/* macros for field vstoreGood */ +/** + * @defgroup pmu_swreg_regs_core_vstoreGood_field vstoreGood_field + * @brief macros for field vstoreGood + * @details vstore good comparator + * @{ + */ +#define SWREG_SWREG_READOUT__VSTOREGOOD__SHIFT 5 +#define SWREG_SWREG_READOUT__VSTOREGOOD__WIDTH 1 +#define SWREG_SWREG_READOUT__VSTOREGOOD__MASK 0x00000020U +#define SWREG_SWREG_READOUT__VSTOREGOOD__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define SWREG_SWREG_READOUT__VSTOREGOOD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define SWREG_SWREG_READOUT__VSTOREGOOD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +/** @} */ + +/* macros for field canHarvest */ +/** + * @defgroup pmu_swreg_regs_core_canHarvest_field canHarvest_field + * @brief macros for field canHarvest + * @details can harvest comparator + * @{ + */ +#define SWREG_SWREG_READOUT__CANHARVEST__SHIFT 6 +#define SWREG_SWREG_READOUT__CANHARVEST__WIDTH 1 +#define SWREG_SWREG_READOUT__CANHARVEST__MASK 0x00000040U +#define SWREG_SWREG_READOUT__CANHARVEST__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define SWREG_SWREG_READOUT__CANHARVEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define SWREG_SWREG_READOUT__CANHARVEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +/** @} */ + +/* macros for field mustHarvest */ +/** + * @defgroup pmu_swreg_regs_core_mustHarvest_field mustHarvest_field + * @brief macros for field mustHarvest + * @details must harvest comparator + * @{ + */ +#define SWREG_SWREG_READOUT__MUSTHARVEST__SHIFT 7 +#define SWREG_SWREG_READOUT__MUSTHARVEST__WIDTH 1 +#define SWREG_SWREG_READOUT__MUSTHARVEST__MASK 0x00000080U +#define SWREG_SWREG_READOUT__MUSTHARVEST__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define SWREG_SWREG_READOUT__MUSTHARVEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define SWREG_SWREG_READOUT__MUSTHARVEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +/** @} */ + +/* macros for field indCurrentSign */ +/** + * @defgroup pmu_swreg_regs_core_indCurrentSign_field indCurrentSign_field + * @brief macros for field indCurrentSign + * @details inductor current sign + * @{ + */ +#define SWREG_SWREG_READOUT__INDCURRENTSIGN__SHIFT 8 +#define SWREG_SWREG_READOUT__INDCURRENTSIGN__WIDTH 1 +#define SWREG_SWREG_READOUT__INDCURRENTSIGN__MASK 0x00000100U +#define SWREG_SWREG_READOUT__INDCURRENTSIGN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define SWREG_SWREG_READOUT__INDCURRENTSIGN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define SWREG_SWREG_READOUT__INDCURRENTSIGN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +/** @} */ + +/* macros for field supReady */ +/** + * @defgroup pmu_swreg_regs_core_supReady_field supReady_field + * @brief macros for field supReady + * @details the 4 supply ready signals + * @{ + */ +#define SWREG_SWREG_READOUT__SUPREADY__SHIFT 9 +#define SWREG_SWREG_READOUT__SUPREADY__WIDTH 4 +#define SWREG_SWREG_READOUT__SUPREADY__MASK 0x00001e00U +#define SWREG_SWREG_READOUT__SUPREADY__READ(src) \ + (((uint32_t)(src)\ + & 0x00001e00U) >> 9) +/** @} */ + +/* macros for field suppliesReady */ +/** + * @defgroup pmu_swreg_regs_core_suppliesReady_field suppliesReady_field + * @brief macros for field suppliesReady + * @details suppliesReady signal + * @{ + */ +#define SWREG_SWREG_READOUT__SUPPLIESREADY__SHIFT 13 +#define SWREG_SWREG_READOUT__SUPPLIESREADY__WIDTH 1 +#define SWREG_SWREG_READOUT__SUPPLIESREADY__MASK 0x00002000U +#define SWREG_SWREG_READOUT__SUPPLIESREADY__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define SWREG_SWREG_READOUT__SUPPLIESREADY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define SWREG_SWREG_READOUT__SUPPLIESREADY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +/** @} */ + +/* macros for field harvesting */ +/** + * @defgroup pmu_swreg_regs_core_harvesting_field harvesting_field + * @brief macros for field harvesting + * @details harvesting signal + * @{ + */ +#define SWREG_SWREG_READOUT__HARVESTING__SHIFT 14 +#define SWREG_SWREG_READOUT__HARVESTING__WIDTH 1 +#define SWREG_SWREG_READOUT__HARVESTING__MASK 0x00004000U +#define SWREG_SWREG_READOUT__HARVESTING__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define SWREG_SWREG_READOUT__HARVESTING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define SWREG_SWREG_READOUT__HARVESTING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +/** @} */ + +/* macros for field state */ +/** + * @defgroup pmu_swreg_regs_core_state_field state_field + * @brief macros for field state + * @details the fsm state + * @{ + */ +#define SWREG_SWREG_READOUT__STATE__SHIFT 15 +#define SWREG_SWREG_READOUT__STATE__WIDTH 3 +#define SWREG_SWREG_READOUT__STATE__MASK 0x00038000U +#define SWREG_SWREG_READOUT__STATE__READ(src) \ + (((uint32_t)(src)\ + & 0x00038000U) >> 15) +/** @} */ +#define SWREG_SWREG_READOUT__TYPE uint32_t +#define SWREG_SWREG_READOUT__READ 0x0003ffffU +#define SWREG_SWREG_READOUT__PRESERVED 0x00000000U + +#endif /* __SWREG_SWREG_READOUT_MACRO__ */ + +/** @} end of swreg_readout */ + +/* macros for BlueprintGlobalNameSpace::SWREG_core_id */ +/** + * @defgroup pmu_swreg_regs_core_core_id core_id + * @brief Contains register fields associated with core_id. definitions. + * @{ + */ +#ifndef __SWREG_CORE_ID_MACRO__ +#define __SWREG_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup pmu_swreg_regs_core_id_field id_field + * @brief macros for field id + * @details SWRG in ASCII + * @{ + */ +#define SWREG_CORE_ID__ID__SHIFT 0 +#define SWREG_CORE_ID__ID__WIDTH 32 +#define SWREG_CORE_ID__ID__MASK 0xffffffffU +#define SWREG_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +/** @} */ +#define SWREG_CORE_ID__TYPE uint32_t +#define SWREG_CORE_ID__READ 0xffffffffU +#define SWREG_CORE_ID__PRESERVED 0x00000000U + +#endif /* __SWREG_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of PMU_SWREG_REGS_CORE */ +#endif /* __REG_PMU_SWREG_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/pmu_top_regs_core_macro.h b/ATM33xx-5/include/reg/pmu_top_regs_core_macro.h new file mode 100644 index 0000000..701878d --- /dev/null +++ b/ATM33xx-5/include/reg/pmu_top_regs_core_macro.h @@ -0,0 +1,13030 @@ +/* */ +/* File: pmu_top_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic pmu_top_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_PMU_TOP_REGS_CORE_H__ +#define __REG_PMU_TOP_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup PMU_TOP_REGS_CORE pmu_top_regs_core + * @ingroup AT_REG + * @brief pmu_top_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu0 */ +/** + * @defgroup pmu_top_regs_core_pmu0 pmu0 + * @brief timer_target_lsb - written by software definitions. + * @{ + */ +#ifndef __PMU_PMU0_MACRO__ +#define __PMU_PMU0_MACRO__ + +/* macros for field timer_target_lsb */ +/** + * @defgroup pmu_top_regs_core_timer_target_lsb_field timer_target_lsb_field + * @brief macros for field timer_target_lsb + * @details written by software, target value to wake up from in soc-off mode pmu starts from 0 and counts 32KHz clock cycles until it reaches this value to come out of soc-off mode if how2wkup reg is set to 1xx 31 lsb bits + * @{ + */ +#define PMU_PMU0__TIMER_TARGET_LSB__SHIFT 0 +#define PMU_PMU0__TIMER_TARGET_LSB__WIDTH 32 +#define PMU_PMU0__TIMER_TARGET_LSB__MASK 0xffffffffU +#define PMU_PMU0__TIMER_TARGET_LSB__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PMU_PMU0__TIMER_TARGET_LSB__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define PMU_PMU0__TIMER_TARGET_LSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define PMU_PMU0__TIMER_TARGET_LSB__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0xffffffffU))) +#define PMU_PMU0__TIMER_TARGET_LSB__RESET_VALUE 0x00000001U +/** @} */ +#define PMU_PMU0__TYPE uint32_t +#define PMU_PMU0__READ 0xffffffffU +#define PMU_PMU0__WRITE 0xffffffffU +#define PMU_PMU0__PRESERVED 0x00000000U +#define PMU_PMU0__RESET_VALUE 0x00000001U + +#endif /* __PMU_PMU0_MACRO__ */ + +/** @} end of pmu0 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu1 */ +/** + * @defgroup pmu_top_regs_core_pmu1 pmu1 + * @brief software controlled registers definitions. + * @{ + */ +#ifndef __PMU_PMU1_MACRO__ +#define __PMU_PMU1_MACRO__ + +/* macros for field timer_target_msb */ +/** + * @defgroup pmu_top_regs_core_timer_target_msb_field timer_target_msb_field + * @brief macros for field timer_target_msb + * @details written by software, target value to wake up from in soc-off mode pmu starts from 0 and counts 32KHz clock cycles until it reaches this value to come out of soc-off mode if how2wkup reg is set to 1xx 8 msb bits + * @{ + */ +#define PMU_PMU1__TIMER_TARGET_MSB__SHIFT 0 +#define PMU_PMU1__TIMER_TARGET_MSB__WIDTH 8 +#define PMU_PMU1__TIMER_TARGET_MSB__MASK 0x000000ffU +#define PMU_PMU1__TIMER_TARGET_MSB__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define PMU_PMU1__TIMER_TARGET_MSB__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define PMU_PMU1__TIMER_TARGET_MSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define PMU_PMU1__TIMER_TARGET_MSB__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define PMU_PMU1__TIMER_TARGET_MSB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field how2wkup_pin */ +/** + * @defgroup pmu_top_regs_core_how2wkup_pin_field how2wkup_pin_field + * @brief macros for field how2wkup_pin + * @details written by software - xx1: pin, x1x: lpcomp, 1xx: timer, write back to 0 after determining wake up cause to clear, write desired bits to 1 before entering low-power state, wait at least two 32KHz cycles between clearing and setting + * @{ + */ +#define PMU_PMU1__HOW2WKUP_PIN__SHIFT 8 +#define PMU_PMU1__HOW2WKUP_PIN__WIDTH 1 +#define PMU_PMU1__HOW2WKUP_PIN__MASK 0x00000100U +#define PMU_PMU1__HOW2WKUP_PIN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define PMU_PMU1__HOW2WKUP_PIN__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define PMU_PMU1__HOW2WKUP_PIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define PMU_PMU1__HOW2WKUP_PIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define PMU_PMU1__HOW2WKUP_PIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PMU_PMU1__HOW2WKUP_PIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PMU_PMU1__HOW2WKUP_PIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field how2wkup_lpcomp */ +/** + * @defgroup pmu_top_regs_core_how2wkup_lpcomp_field how2wkup_lpcomp_field + * @brief macros for field how2wkup_lpcomp + * @details written by software - xx1: pin, x1x: lpcomp, 1xx: timer, write back to 0 after determining wake up cause to clear, write desired bits to 1 before entering low-power state, wait at least two 32KHz cycles between clearing and setting + * @{ + */ +#define PMU_PMU1__HOW2WKUP_LPCOMP__SHIFT 9 +#define PMU_PMU1__HOW2WKUP_LPCOMP__WIDTH 1 +#define PMU_PMU1__HOW2WKUP_LPCOMP__MASK 0x00000200U +#define PMU_PMU1__HOW2WKUP_LPCOMP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PMU_PMU1__HOW2WKUP_LPCOMP__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define PMU_PMU1__HOW2WKUP_LPCOMP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define PMU_PMU1__HOW2WKUP_LPCOMP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define PMU_PMU1__HOW2WKUP_LPCOMP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PMU_PMU1__HOW2WKUP_LPCOMP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PMU_PMU1__HOW2WKUP_LPCOMP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field how2wkup_timer */ +/** + * @defgroup pmu_top_regs_core_how2wkup_timer_field how2wkup_timer_field + * @brief macros for field how2wkup_timer + * @details written by software - xx1: pin, x1x: lpcomp, 1xx: timer, write back to 0 after determining wake up cause to clear, write desired bits to 1 before entering low-power state, wait at least two 32KHz cycles between clearing and setting + * @{ + */ +#define PMU_PMU1__HOW2WKUP_TIMER__SHIFT 10 +#define PMU_PMU1__HOW2WKUP_TIMER__WIDTH 1 +#define PMU_PMU1__HOW2WKUP_TIMER__MASK 0x00000400U +#define PMU_PMU1__HOW2WKUP_TIMER__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define PMU_PMU1__HOW2WKUP_TIMER__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define PMU_PMU1__HOW2WKUP_TIMER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define PMU_PMU1__HOW2WKUP_TIMER__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define PMU_PMU1__HOW2WKUP_TIMER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define PMU_PMU1__HOW2WKUP_TIMER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define PMU_PMU1__HOW2WKUP_TIMER__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field lpcomp_in_sel */ +/** + * @defgroup pmu_top_regs_core_lpcomp_in_sel_field lpcomp_in_sel_field + * @brief macros for field lpcomp_in_sel + * @details 0: P3, 1: P4 + * @{ + */ +#define PMU_PMU1__LPCOMP_IN_SEL__SHIFT 11 +#define PMU_PMU1__LPCOMP_IN_SEL__WIDTH 1 +#define PMU_PMU1__LPCOMP_IN_SEL__MASK 0x00000800U +#define PMU_PMU1__LPCOMP_IN_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define PMU_PMU1__LPCOMP_IN_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define PMU_PMU1__LPCOMP_IN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define PMU_PMU1__LPCOMP_IN_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define PMU_PMU1__LPCOMP_IN_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define PMU_PMU1__LPCOMP_IN_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define PMU_PMU1__LPCOMP_IN_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field compout_mux_sel */ +/** + * @defgroup pmu_top_regs_core_compout_mux_sel_field compout_mux_sel_field + * @brief macros for field compout_mux_sel + * @details select which test signal goes to pin_mux 3'b001: BrownOutVbat 3'b010: VstoreGoodtoEner 3'b011: VstoreHarvStop 3'b100: mpptstartvharv 3'b101: reconfharvstage 3'b110: lpcomp_out 3'b111: pinedge_det + * @{ + */ +#define PMU_PMU1__COMPOUT_MUX_SEL__SHIFT 12 +#define PMU_PMU1__COMPOUT_MUX_SEL__WIDTH 3 +#define PMU_PMU1__COMPOUT_MUX_SEL__MASK 0x00007000U +#define PMU_PMU1__COMPOUT_MUX_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00007000U) >> 12) +#define PMU_PMU1__COMPOUT_MUX_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00007000U) +#define PMU_PMU1__COMPOUT_MUX_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((uint32_t)(src) <<\ + 12) & 0x00007000U) +#define PMU_PMU1__COMPOUT_MUX_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00007000U))) +#define PMU_PMU1__COMPOUT_MUX_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field atb_pad_en */ +/** + * @defgroup pmu_top_regs_core_atb_pad_en_field atb_pad_en_field + * @brief macros for field atb_pad_en + * @details atb pad enable + * @{ + */ +#define PMU_PMU1__ATB_PAD_EN__SHIFT 15 +#define PMU_PMU1__ATB_PAD_EN__WIDTH 1 +#define PMU_PMU1__ATB_PAD_EN__MASK 0x00008000U +#define PMU_PMU1__ATB_PAD_EN__READ(src) (((uint32_t)(src) & 0x00008000U) >> 15) +#define PMU_PMU1__ATB_PAD_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define PMU_PMU1__ATB_PAD_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define PMU_PMU1__ATB_PAD_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define PMU_PMU1__ATB_PAD_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PMU_PMU1__ATB_PAD_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PMU_PMU1__ATB_PAD_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field xofaststart */ +/** + * @defgroup pmu_top_regs_core_xofaststart_field xofaststart_field + * @brief macros for field xofaststart + * @details enable fast start for xtal + * @{ + */ +#define PMU_PMU1__XOFASTSTART__SHIFT 16 +#define PMU_PMU1__XOFASTSTART__WIDTH 3 +#define PMU_PMU1__XOFASTSTART__MASK 0x00070000U +#define PMU_PMU1__XOFASTSTART__READ(src) \ + (((uint32_t)(src)\ + & 0x00070000U) >> 16) +#define PMU_PMU1__XOFASTSTART__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00070000U) +#define PMU_PMU1__XOFASTSTART__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((uint32_t)(src) <<\ + 16) & 0x00070000U) +#define PMU_PMU1__XOFASTSTART__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00070000U))) +#define PMU_PMU1__XOFASTSTART__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field xosettle */ +/** + * @defgroup pmu_top_regs_core_xosettle_field xosettle_field + * @brief macros for field xosettle + * @details settling time for xtal + * @{ + */ +#define PMU_PMU1__XOSETTLE__SHIFT 19 +#define PMU_PMU1__XOSETTLE__WIDTH 6 +#define PMU_PMU1__XOSETTLE__MASK 0x01f80000U +#define PMU_PMU1__XOSETTLE__READ(src) (((uint32_t)(src) & 0x01f80000U) >> 19) +#define PMU_PMU1__XOSETTLE__WRITE(src) (((uint32_t)(src) << 19) & 0x01f80000U) +#define PMU_PMU1__XOSETTLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f80000U) | (((uint32_t)(src) <<\ + 19) & 0x01f80000U) +#define PMU_PMU1__XOSETTLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x01f80000U))) +#define PMU_PMU1__XOSETTLE__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field xtal_pwd */ +/** + * @defgroup pmu_top_regs_core_xtal_pwd_field xtal_pwd_field + * @brief macros for field xtal_pwd + * @details default is always on unless this is set or ext pwd is set + * @{ + */ +#define PMU_PMU1__XTAL_PWD__SHIFT 25 +#define PMU_PMU1__XTAL_PWD__WIDTH 1 +#define PMU_PMU1__XTAL_PWD__MASK 0x02000000U +#define PMU_PMU1__XTAL_PWD__READ(src) (((uint32_t)(src) & 0x02000000U) >> 25) +#define PMU_PMU1__XTAL_PWD__WRITE(src) (((uint32_t)(src) << 25) & 0x02000000U) +#define PMU_PMU1__XTAL_PWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define PMU_PMU1__XTAL_PWD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define PMU_PMU1__XTAL_PWD__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define PMU_PMU1__XTAL_PWD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define PMU_PMU1__XTAL_PWD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field use16MforPSEQ */ +/** + * @defgroup pmu_top_regs_core_use16MforPSEQ_field use16MforPSEQ_field + * @brief macros for field use16MforPSEQ + * @details keep 16MHz on and use it as the clock source for 32KHz timers in PMU + * @{ + */ +#define PMU_PMU1__USE16MFORPSEQ__SHIFT 26 +#define PMU_PMU1__USE16MFORPSEQ__WIDTH 1 +#define PMU_PMU1__USE16MFORPSEQ__MASK 0x04000000U +#define PMU_PMU1__USE16MFORPSEQ__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define PMU_PMU1__USE16MFORPSEQ__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define PMU_PMU1__USE16MFORPSEQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define PMU_PMU1__USE16MFORPSEQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define PMU_PMU1__USE16MFORPSEQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define PMU_PMU1__USE16MFORPSEQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define PMU_PMU1__USE16MFORPSEQ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field doRCoscCal */ +/** + * @defgroup pmu_top_regs_core_doRCoscCal_field doRCoscCal_field + * @brief macros for field doRCoscCal + * @details set to 1 before entering low power state to do HW measurement in that state, clear after next wake up and read calCountRC value + * @{ + */ +#define PMU_PMU1__DORCOSCCAL__SHIFT 27 +#define PMU_PMU1__DORCOSCCAL__WIDTH 1 +#define PMU_PMU1__DORCOSCCAL__MASK 0x08000000U +#define PMU_PMU1__DORCOSCCAL__READ(src) (((uint32_t)(src) & 0x08000000U) >> 27) +#define PMU_PMU1__DORCOSCCAL__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define PMU_PMU1__DORCOSCCAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define PMU_PMU1__DORCOSCCAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define PMU_PMU1__DORCOSCCAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define PMU_PMU1__DORCOSCCAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define PMU_PMU1__DORCOSCCAL__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU1__TYPE uint32_t +#define PMU_PMU1__READ 0x0fffffffU +#define PMU_PMU1__WRITE 0x0fffffffU +#define PMU_PMU1__PRESERVED 0x00000000U +#define PMU_PMU1__RESET_VALUE 0x00860400U + +#endif /* __PMU_PMU1_MACRO__ */ + +/** @} end of pmu1 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu1a */ +/** + * @defgroup pmu_top_regs_core_pmu1a pmu1a + * @brief software controlled xtal related definitions. + * @{ + */ +#ifndef __PMU_PMU1A_MACRO__ +#define __PMU_PMU1A_MACRO__ + +/* macros for field RCoscCalPeriods */ +/** + * @defgroup pmu_top_regs_core_RCoscCalPeriods_field RCoscCalPeriods_field + * @brief macros for field RCoscCalPeriods + * @details how many RCosc periods to run calibration + * @{ + */ +#define PMU_PMU1A__RCOSCCALPERIODS__SHIFT 0 +#define PMU_PMU1A__RCOSCCALPERIODS__WIDTH 11 +#define PMU_PMU1A__RCOSCCALPERIODS__MASK 0x000007ffU +#define PMU_PMU1A__RCOSCCALPERIODS__READ(src) ((uint32_t)(src) & 0x000007ffU) +#define PMU_PMU1A__RCOSCCALPERIODS__WRITE(src) ((uint32_t)(src) & 0x000007ffU) +#define PMU_PMU1A__RCOSCCALPERIODS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007ffU) | ((uint32_t)(src) &\ + 0x000007ffU) +#define PMU_PMU1A__RCOSCCALPERIODS__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000007ffU))) +#define PMU_PMU1A__RCOSCCALPERIODS__RESET_VALUE 0x00000040U +/** @} */ + +/* macros for field RCoscCalWait */ +/** + * @defgroup pmu_top_regs_core_RCoscCalWait_field RCoscCalWait_field + * @brief macros for field RCoscCalWait + * @details how long to wait for supply settling after entering low power state to start counting, ~1ms resolution + * @{ + */ +#define PMU_PMU1A__RCOSCCALWAIT__SHIFT 11 +#define PMU_PMU1A__RCOSCCALWAIT__WIDTH 8 +#define PMU_PMU1A__RCOSCCALWAIT__MASK 0x0007f800U +#define PMU_PMU1A__RCOSCCALWAIT__READ(src) \ + (((uint32_t)(src)\ + & 0x0007f800U) >> 11) +#define PMU_PMU1A__RCOSCCALWAIT__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x0007f800U) +#define PMU_PMU1A__RCOSCCALWAIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007f800U) | (((uint32_t)(src) <<\ + 11) & 0x0007f800U) +#define PMU_PMU1A__RCOSCCALWAIT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x0007f800U))) +#define PMU_PMU1A__RCOSCCALWAIT__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field xohysn */ +/** + * @defgroup pmu_top_regs_core_xohysn_field xohysn_field + * @brief macros for field xohysn + * @details 32KHz RC buffer N-side hysteresis, tune to reduce frequency variation to supply sensitivity + * @{ + */ +#define PMU_PMU1A__XOHYSN__SHIFT 19 +#define PMU_PMU1A__XOHYSN__WIDTH 3 +#define PMU_PMU1A__XOHYSN__MASK 0x00380000U +#define PMU_PMU1A__XOHYSN__READ(src) (((uint32_t)(src) & 0x00380000U) >> 19) +#define PMU_PMU1A__XOHYSN__WRITE(src) (((uint32_t)(src) << 19) & 0x00380000U) +#define PMU_PMU1A__XOHYSN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00380000U) | (((uint32_t)(src) <<\ + 19) & 0x00380000U) +#define PMU_PMU1A__XOHYSN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00380000U))) +#define PMU_PMU1A__XOHYSN__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field xohysp_b */ +/** + * @defgroup pmu_top_regs_core_xohysp_b_field xohysp_b_field + * @brief macros for field xohysp_b + * @details 32KHz RC buffer P-side hysteresis, tune to reduce frequency variation to supply sensitivity + * @{ + */ +#define PMU_PMU1A__XOHYSP_B__SHIFT 22 +#define PMU_PMU1A__XOHYSP_B__WIDTH 3 +#define PMU_PMU1A__XOHYSP_B__MASK 0x01c00000U +#define PMU_PMU1A__XOHYSP_B__READ(src) (((uint32_t)(src) & 0x01c00000U) >> 22) +#define PMU_PMU1A__XOHYSP_B__WRITE(src) (((uint32_t)(src) << 22) & 0x01c00000U) +#define PMU_PMU1A__XOHYSP_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01c00000U) | (((uint32_t)(src) <<\ + 22) & 0x01c00000U) +#define PMU_PMU1A__XOHYSP_B__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x01c00000U))) +#define PMU_PMU1A__XOHYSP_B__RESET_VALUE 0x00000004U +/** @} */ +#define PMU_PMU1A__TYPE uint32_t +#define PMU_PMU1A__READ 0x01ffffffU +#define PMU_PMU1A__WRITE 0x01ffffffU +#define PMU_PMU1A__PRESERVED 0x00000000U +#define PMU_PMU1A__RESET_VALUE 0x01182040U + +#endif /* __PMU_PMU1A_MACRO__ */ + +/** @} end of pmu1a */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu2 */ +/** + * @defgroup pmu_top_regs_core_pmu2 pmu2 + * @brief customer writes definitions. + * @{ + */ +#ifndef __PMU_PMU2_MACRO__ +#define __PMU_PMU2_MACRO__ + +/* macros for field xocapout */ +/** + * @defgroup pmu_top_regs_core_xocapout_field xocapout_field + * @brief macros for field xocapout + * @details cap on board + * @{ + */ +#define PMU_PMU2__XOCAPOUT__SHIFT 0 +#define PMU_PMU2__XOCAPOUT__WIDTH 5 +#define PMU_PMU2__XOCAPOUT__MASK 0x0000001fU +#define PMU_PMU2__XOCAPOUT__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define PMU_PMU2__XOCAPOUT__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define PMU_PMU2__XOCAPOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define PMU_PMU2__XOCAPOUT__VERIFY(src) (!(((uint32_t)(src) & ~0x0000001fU))) +#define PMU_PMU2__XOCAPOUT__RESET_VALUE 0x0000001bU +/** @} */ + +/* macros for field xocapin */ +/** + * @defgroup pmu_top_regs_core_xocapin_field xocapin_field + * @brief macros for field xocapin + * @details cap on board + * @{ + */ +#define PMU_PMU2__XOCAPIN__SHIFT 5 +#define PMU_PMU2__XOCAPIN__WIDTH 5 +#define PMU_PMU2__XOCAPIN__MASK 0x000003e0U +#define PMU_PMU2__XOCAPIN__READ(src) (((uint32_t)(src) & 0x000003e0U) >> 5) +#define PMU_PMU2__XOCAPIN__WRITE(src) (((uint32_t)(src) << 5) & 0x000003e0U) +#define PMU_PMU2__XOCAPIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((uint32_t)(src) <<\ + 5) & 0x000003e0U) +#define PMU_PMU2__XOCAPIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000003e0U))) +#define PMU_PMU2__XOCAPIN__RESET_VALUE 0x0000001bU +/** @} */ + +/* macros for field RGuserconf */ +/** + * @defgroup pmu_top_regs_core_RGuserconf_field RGuserconf_field + * @brief macros for field RGuserconf + * @details unused + * @{ + */ +#define PMU_PMU2__RGUSERCONF__SHIFT 10 +#define PMU_PMU2__RGUSERCONF__WIDTH 1 +#define PMU_PMU2__RGUSERCONF__MASK 0x00000400U +#define PMU_PMU2__RGUSERCONF__READ(src) (((uint32_t)(src) & 0x00000400U) >> 10) +#define PMU_PMU2__RGUSERCONF__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define PMU_PMU2__RGUSERCONF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define PMU_PMU2__RGUSERCONF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define PMU_PMU2__RGUSERCONF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define PMU_PMU2__RGUSERCONF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define PMU_PMU2__RGUSERCONF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field rect_stage_default */ +/** + * @defgroup pmu_top_regs_core_rect_stage_default_field rect_stage_default_field + * @brief macros for field rect_stage_default + * @details default number of rectifier stages: 2^i, i=0:3 + * @{ + */ +#define PMU_PMU2__RECT_STAGE_DEFAULT__SHIFT 11 +#define PMU_PMU2__RECT_STAGE_DEFAULT__WIDTH 2 +#define PMU_PMU2__RECT_STAGE_DEFAULT__MASK 0x00001800U +#define PMU_PMU2__RECT_STAGE_DEFAULT__READ(src) \ + (((uint32_t)(src)\ + & 0x00001800U) >> 11) +#define PMU_PMU2__RECT_STAGE_DEFAULT__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00001800U) +#define PMU_PMU2__RECT_STAGE_DEFAULT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001800U) | (((uint32_t)(src) <<\ + 11) & 0x00001800U) +#define PMU_PMU2__RECT_STAGE_DEFAULT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00001800U))) +#define PMU_PMU2__RECT_STAGE_DEFAULT__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field rect_counter_disable */ +/** + * @defgroup pmu_top_regs_core_rect_counter_disable_field rect_counter_disable_field + * @brief macros for field rect_counter_disable + * @details disable dynamic control of rectifier stages + * @{ + */ +#define PMU_PMU2__RECT_COUNTER_DISABLE__SHIFT 13 +#define PMU_PMU2__RECT_COUNTER_DISABLE__WIDTH 1 +#define PMU_PMU2__RECT_COUNTER_DISABLE__MASK 0x00002000U +#define PMU_PMU2__RECT_COUNTER_DISABLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define PMU_PMU2__RECT_COUNTER_DISABLE__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define PMU_PMU2__RECT_COUNTER_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define PMU_PMU2__RECT_COUNTER_DISABLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define PMU_PMU2__RECT_COUNTER_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define PMU_PMU2__RECT_COUNTER_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define PMU_PMU2__RECT_COUNTER_DISABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field disable_store */ +/** + * @defgroup pmu_top_regs_core_disable_store_field disable_store_field + * @brief macros for field disable_store + * @details disable store as a source + * @{ + */ +#define PMU_PMU2__DISABLE_STORE__SHIFT 14 +#define PMU_PMU2__DISABLE_STORE__WIDTH 1 +#define PMU_PMU2__DISABLE_STORE__MASK 0x00004000U +#define PMU_PMU2__DISABLE_STORE__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PMU_PMU2__DISABLE_STORE__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define PMU_PMU2__DISABLE_STORE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define PMU_PMU2__DISABLE_STORE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define PMU_PMU2__DISABLE_STORE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PMU_PMU2__DISABLE_STORE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PMU_PMU2__DISABLE_STORE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field use_ext32k */ +/** + * @defgroup pmu_top_regs_core_use_ext32k_field use_ext32k_field + * @brief macros for field use_ext32k + * @details use external 32K clock source + * @{ + */ +#define PMU_PMU2__USE_EXT32K__SHIFT 15 +#define PMU_PMU2__USE_EXT32K__WIDTH 1 +#define PMU_PMU2__USE_EXT32K__MASK 0x00008000U +#define PMU_PMU2__USE_EXT32K__READ(src) (((uint32_t)(src) & 0x00008000U) >> 15) +#define PMU_PMU2__USE_EXT32K__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define PMU_PMU2__USE_EXT32K__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define PMU_PMU2__USE_EXT32K__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define PMU_PMU2__USE_EXT32K__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PMU_PMU2__USE_EXT32K__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PMU_PMU2__USE_EXT32K__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU2__TYPE uint32_t +#define PMU_PMU2__READ 0x0000ffffU +#define PMU_PMU2__WRITE 0x0000ffffU +#define PMU_PMU2__PRESERVED 0x00000000U +#define PMU_PMU2__RESET_VALUE 0x00001f7bU + +#endif /* __PMU_PMU2_MACRO__ */ + +/** @} end of pmu2 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu2a */ +/** + * @defgroup pmu_top_regs_core_pmu2a pmu2a + * @brief ate definitions. + * @{ + */ +#ifndef __PMU_PMU2A_MACRO__ +#define __PMU_PMU2A_MACRO__ + +/* macros for field xoagc_en */ +/** + * @defgroup pmu_top_regs_core_xoagc_en_field xoagc_en_field + * @brief macros for field xoagc_en + * @details Enable 32KHz xtal AGC + * @{ + */ +#define PMU_PMU2A__XOAGC_EN__SHIFT 0 +#define PMU_PMU2A__XOAGC_EN__WIDTH 1 +#define PMU_PMU2A__XOAGC_EN__MASK 0x00000001U +#define PMU_PMU2A__XOAGC_EN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PMU_PMU2A__XOAGC_EN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PMU_PMU2A__XOAGC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PMU_PMU2A__XOAGC_EN__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define PMU_PMU2A__XOAGC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PMU_PMU2A__XOAGC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PMU_PMU2A__XOAGC_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field xobias */ +/** + * @defgroup pmu_top_regs_core_xobias_field xobias_field + * @brief macros for field xobias + * @details 32KHz xtal bias current or AGC target + * @{ + */ +#define PMU_PMU2A__XOBIAS__SHIFT 1 +#define PMU_PMU2A__XOBIAS__WIDTH 4 +#define PMU_PMU2A__XOBIAS__MASK 0x0000001eU +#define PMU_PMU2A__XOBIAS__READ(src) (((uint32_t)(src) & 0x0000001eU) >> 1) +#define PMU_PMU2A__XOBIAS__WRITE(src) (((uint32_t)(src) << 1) & 0x0000001eU) +#define PMU_PMU2A__XOBIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001eU) | (((uint32_t)(src) <<\ + 1) & 0x0000001eU) +#define PMU_PMU2A__XOBIAS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x0000001eU))) +#define PMU_PMU2A__XOBIAS__RESET_VALUE 0x0000000cU +/** @} */ + +/* macros for field rcosc32Kfreq */ +/** + * @defgroup pmu_top_regs_core_rcosc32Kfreq_field rcosc32Kfreq_field + * @brief macros for field rcosc32Kfreq + * @details 32KHz RC osc freq tuning + * @{ + */ +#define PMU_PMU2A__RCOSC32KFREQ__SHIFT 5 +#define PMU_PMU2A__RCOSC32KFREQ__WIDTH 4 +#define PMU_PMU2A__RCOSC32KFREQ__MASK 0x000001e0U +#define PMU_PMU2A__RCOSC32KFREQ__READ(src) \ + (((uint32_t)(src)\ + & 0x000001e0U) >> 5) +#define PMU_PMU2A__RCOSC32KFREQ__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x000001e0U) +#define PMU_PMU2A__RCOSC32KFREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001e0U) | (((uint32_t)(src) <<\ + 5) & 0x000001e0U) +#define PMU_PMU2A__RCOSC32KFREQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000001e0U))) +#define PMU_PMU2A__RCOSC32KFREQ__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field rcosc32Kmode */ +/** + * @defgroup pmu_top_regs_core_rcosc32Kmode_field rcosc32Kmode_field + * @brief macros for field rcosc32Kmode + * @details 32KHz RC osc mode/topology select + * @{ + */ +#define PMU_PMU2A__RCOSC32KMODE__SHIFT 9 +#define PMU_PMU2A__RCOSC32KMODE__WIDTH 1 +#define PMU_PMU2A__RCOSC32KMODE__MASK 0x00000200U +#define PMU_PMU2A__RCOSC32KMODE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PMU_PMU2A__RCOSC32KMODE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define PMU_PMU2A__RCOSC32KMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define PMU_PMU2A__RCOSC32KMODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define PMU_PMU2A__RCOSC32KMODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PMU_PMU2A__RCOSC32KMODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PMU_PMU2A__RCOSC32KMODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_refBG_ldo */ +/** + * @defgroup pmu_top_regs_core_ctr_refBG_ldo_field ctr_refBG_ldo_field + * @brief macros for field ctr_refBG_ldo + * @details ref level for ldo: Vref=25*(24+i)mV, i=0:15 + * @{ + */ +#define PMU_PMU2A__CTR_REFBG_LDO__SHIFT 10 +#define PMU_PMU2A__CTR_REFBG_LDO__WIDTH 4 +#define PMU_PMU2A__CTR_REFBG_LDO__MASK 0x00003c00U +#define PMU_PMU2A__CTR_REFBG_LDO__READ(src) \ + (((uint32_t)(src)\ + & 0x00003c00U) >> 10) +#define PMU_PMU2A__CTR_REFBG_LDO__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00003c00U) +#define PMU_PMU2A__CTR_REFBG_LDO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003c00U) | (((uint32_t)(src) <<\ + 10) & 0x00003c00U) +#define PMU_PMU2A__CTR_REFBG_LDO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00003c00U))) +#define PMU_PMU2A__CTR_REFBG_LDO__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field ctr_refldo */ +/** + * @defgroup pmu_top_regs_core_ctr_refldo_field ctr_refldo_field + * @brief macros for field ctr_refldo + * @details ref sel for ldo0: From refgen (BG/native). Use ctr_refBG_ldo to adjust1: From tracking reference + * @{ + */ +#define PMU_PMU2A__CTR_REFLDO__SHIFT 14 +#define PMU_PMU2A__CTR_REFLDO__WIDTH 1 +#define PMU_PMU2A__CTR_REFLDO__MASK 0x00004000U +#define PMU_PMU2A__CTR_REFLDO__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PMU_PMU2A__CTR_REFLDO__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define PMU_PMU2A__CTR_REFLDO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define PMU_PMU2A__CTR_REFLDO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define PMU_PMU2A__CTR_REFLDO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PMU_PMU2A__CTR_REFLDO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PMU_PMU2A__CTR_REFLDO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_refInsel_nat */ +/** + * @defgroup pmu_top_regs_core_ctr_refInsel_nat_field ctr_refInsel_nat_field + * @brief macros for field ctr_refInsel_nat + * @details refgen feedback tap select for native. For reference=600mV 3: 625mV reflad<25>2: 600mV reflad<24>1: 575mV reflad<23>0: 550mV reflad<22> + * @{ + */ +#define PMU_PMU2A__CTR_REFINSEL_NAT__SHIFT 15 +#define PMU_PMU2A__CTR_REFINSEL_NAT__WIDTH 2 +#define PMU_PMU2A__CTR_REFINSEL_NAT__MASK 0x00018000U +#define PMU_PMU2A__CTR_REFINSEL_NAT__READ(src) \ + (((uint32_t)(src)\ + & 0x00018000U) >> 15) +#define PMU_PMU2A__CTR_REFINSEL_NAT__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00018000U) +#define PMU_PMU2A__CTR_REFINSEL_NAT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00018000U) | (((uint32_t)(src) <<\ + 15) & 0x00018000U) +#define PMU_PMU2A__CTR_REFINSEL_NAT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00018000U))) +#define PMU_PMU2A__CTR_REFINSEL_NAT__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field ctr_refInsel_pmubg */ +/** + * @defgroup pmu_top_regs_core_ctr_refInsel_pmubg_field ctr_refInsel_pmubg_field + * @brief macros for field ctr_refInsel_pmubg + * @details refgen feedback tap select for main bg. For reference=600mV 3: 625mV reflad<25>2: 600mV reflad<24>1: 575mV reflad<23>0: 550mV reflad<22> + * @{ + */ +#define PMU_PMU2A__CTR_REFINSEL_PMUBG__SHIFT 17 +#define PMU_PMU2A__CTR_REFINSEL_PMUBG__WIDTH 2 +#define PMU_PMU2A__CTR_REFINSEL_PMUBG__MASK 0x00060000U +#define PMU_PMU2A__CTR_REFINSEL_PMUBG__READ(src) \ + (((uint32_t)(src)\ + & 0x00060000U) >> 17) +#define PMU_PMU2A__CTR_REFINSEL_PMUBG__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00060000U) +#define PMU_PMU2A__CTR_REFINSEL_PMUBG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00060000U) | (((uint32_t)(src) <<\ + 17) & 0x00060000U) +#define PMU_PMU2A__CTR_REFINSEL_PMUBG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00060000U))) +#define PMU_PMU2A__CTR_REFINSEL_PMUBG__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field ctr_ref_vddioint */ +/** + * @defgroup pmu_top_regs_core_ctr_ref_vddioint_field ctr_ref_vddioint_field + * @brief macros for field ctr_ref_vddioint + * @details internally generated vddio level. vddioint=25*(64+2*i)mV, i=0:7 for otp_vddio_range = 0, otp_noind=025*(86+2*i)mV, i=0:7 for otp_vddio_range = 1, otp_noind=025*(32+1*i)mV, i=0:7 for otp_vddio_range = 0, otp_noind=125*(43+1*i)mV, i=0:7 for otp_vddio_range = 1, otp_noind=1 + * @{ + */ +#define PMU_PMU2A__CTR_REF_VDDIOINT__SHIFT 19 +#define PMU_PMU2A__CTR_REF_VDDIOINT__WIDTH 3 +#define PMU_PMU2A__CTR_REF_VDDIOINT__MASK 0x00380000U +#define PMU_PMU2A__CTR_REF_VDDIOINT__READ(src) \ + (((uint32_t)(src)\ + & 0x00380000U) >> 19) +#define PMU_PMU2A__CTR_REF_VDDIOINT__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00380000U) +#define PMU_PMU2A__CTR_REF_VDDIOINT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00380000U) | (((uint32_t)(src) <<\ + 19) & 0x00380000U) +#define PMU_PMU2A__CTR_REF_VDDIOINT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00380000U))) +#define PMU_PMU2A__CTR_REF_VDDIOINT__RESET_VALUE 0x00000004U +/** @} */ +#define PMU_PMU2A__TYPE uint32_t +#define PMU_PMU2A__READ 0x003fffffU +#define PMU_PMU2A__WRITE 0x003fffffU +#define PMU_PMU2A__PRESERVED 0x00000000U +#define PMU_PMU2A__RESET_VALUE 0x00251c99U + +#endif /* __PMU_PMU2A_MACRO__ */ + +/** @} end of pmu2a */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu3 */ +/** + * @defgroup pmu_top_regs_core_pmu3 pmu3 + * @brief more ate definitions. + * @{ + */ +#ifndef __PMU_PMU3_MACRO__ +#define __PMU_PMU3_MACRO__ + +/* macros for field ctr_ref_vddaux */ +/** + * @defgroup pmu_top_regs_core_ctr_ref_vddaux_field ctr_ref_vddaux_field + * @brief macros for field ctr_ref_vddaux + * @details level of aux supply. vddaux=2*25*(50+5*i)mV, i=0:22*25*66mV, i=3 + * @{ + */ +#define PMU_PMU3__CTR_REF_VDDAUX__SHIFT 0 +#define PMU_PMU3__CTR_REF_VDDAUX__WIDTH 2 +#define PMU_PMU3__CTR_REF_VDDAUX__MASK 0x00000003U +#define PMU_PMU3__CTR_REF_VDDAUX__READ(src) ((uint32_t)(src) & 0x00000003U) +#define PMU_PMU3__CTR_REF_VDDAUX__WRITE(src) ((uint32_t)(src) & 0x00000003U) +#define PMU_PMU3__CTR_REF_VDDAUX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define PMU_PMU3__CTR_REF_VDDAUX__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define PMU_PMU3__CTR_REF_VDDAUX__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field ctr_ref_avdd_active */ +/** + * @defgroup pmu_top_regs_core_ctr_ref_avdd_active_field ctr_ref_avdd_active_field + * @brief macros for field ctr_ref_avdd_active + * @details avdd level active. avdd=25*(37+i)mV, i=1:725*36mV, i=0 + * @{ + */ +#define PMU_PMU3__CTR_REF_AVDD_ACTIVE__SHIFT 2 +#define PMU_PMU3__CTR_REF_AVDD_ACTIVE__WIDTH 3 +#define PMU_PMU3__CTR_REF_AVDD_ACTIVE__MASK 0x0000001cU +#define PMU_PMU3__CTR_REF_AVDD_ACTIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x0000001cU) >> 2) +#define PMU_PMU3__CTR_REF_AVDD_ACTIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000001cU) +#define PMU_PMU3__CTR_REF_AVDD_ACTIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((uint32_t)(src) <<\ + 2) & 0x0000001cU) +#define PMU_PMU3__CTR_REF_AVDD_ACTIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000001cU))) +#define PMU_PMU3__CTR_REF_AVDD_ACTIVE__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field ctr_ref_avdd_hibernate */ +/** + * @defgroup pmu_top_regs_core_ctr_ref_avdd_hibernate_field ctr_ref_avdd_hibernate_field + * @brief macros for field ctr_ref_avdd_hibernate + * @details avdd level hibernate. avdd=25*(37+i)mV, i=1:725*36mV, i=0 + * @{ + */ +#define PMU_PMU3__CTR_REF_AVDD_HIBERNATE__SHIFT 5 +#define PMU_PMU3__CTR_REF_AVDD_HIBERNATE__WIDTH 3 +#define PMU_PMU3__CTR_REF_AVDD_HIBERNATE__MASK 0x000000e0U +#define PMU_PMU3__CTR_REF_AVDD_HIBERNATE__READ(src) \ + (((uint32_t)(src)\ + & 0x000000e0U) >> 5) +#define PMU_PMU3__CTR_REF_AVDD_HIBERNATE__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x000000e0U) +#define PMU_PMU3__CTR_REF_AVDD_HIBERNATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((uint32_t)(src) <<\ + 5) & 0x000000e0U) +#define PMU_PMU3__CTR_REF_AVDD_HIBERNATE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000000e0U))) +#define PMU_PMU3__CTR_REF_AVDD_HIBERNATE__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field ctr_ref_avdd_retain */ +/** + * @defgroup pmu_top_regs_core_ctr_ref_avdd_retain_field ctr_ref_avdd_retain_field + * @brief macros for field ctr_ref_avdd_retain + * @details avdd level retain. avdd=25*(37+i)mV, i=1:725*36mV, i=0 + * @{ + */ +#define PMU_PMU3__CTR_REF_AVDD_RETAIN__SHIFT 8 +#define PMU_PMU3__CTR_REF_AVDD_RETAIN__WIDTH 3 +#define PMU_PMU3__CTR_REF_AVDD_RETAIN__MASK 0x00000700U +#define PMU_PMU3__CTR_REF_AVDD_RETAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000700U) >> 8) +#define PMU_PMU3__CTR_REF_AVDD_RETAIN__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000700U) +#define PMU_PMU3__CTR_REF_AVDD_RETAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((uint32_t)(src) <<\ + 8) & 0x00000700U) +#define PMU_PMU3__CTR_REF_AVDD_RETAIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000700U))) +#define PMU_PMU3__CTR_REF_AVDD_RETAIN__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field ctr_ref_avdd_socoff */ +/** + * @defgroup pmu_top_regs_core_ctr_ref_avdd_socoff_field ctr_ref_avdd_socoff_field + * @brief macros for field ctr_ref_avdd_socoff + * @details avdd level socoff. avdd=25*(37+i)mV, i=1:725*36mV, i=0 + * @{ + */ +#define PMU_PMU3__CTR_REF_AVDD_SOCOFF__SHIFT 11 +#define PMU_PMU3__CTR_REF_AVDD_SOCOFF__WIDTH 3 +#define PMU_PMU3__CTR_REF_AVDD_SOCOFF__MASK 0x00003800U +#define PMU_PMU3__CTR_REF_AVDD_SOCOFF__READ(src) \ + (((uint32_t)(src)\ + & 0x00003800U) >> 11) +#define PMU_PMU3__CTR_REF_AVDD_SOCOFF__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00003800U) +#define PMU_PMU3__CTR_REF_AVDD_SOCOFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((uint32_t)(src) <<\ + 11) & 0x00003800U) +#define PMU_PMU3__CTR_REF_AVDD_SOCOFF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00003800U))) +#define PMU_PMU3__CTR_REF_AVDD_SOCOFF__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field ctr_ref_avdd */ +/** + * @defgroup pmu_top_regs_core_ctr_ref_avdd_field ctr_ref_avdd_field + * @brief macros for field ctr_ref_avdd + * @details avdd level for L2 ldo, 25*(43+i), i=0:7 + * @{ + */ +#define PMU_PMU3__CTR_REF_AVDD__SHIFT 14 +#define PMU_PMU3__CTR_REF_AVDD__WIDTH 3 +#define PMU_PMU3__CTR_REF_AVDD__MASK 0x0001c000U +#define PMU_PMU3__CTR_REF_AVDD__READ(src) \ + (((uint32_t)(src)\ + & 0x0001c000U) >> 14) +#define PMU_PMU3__CTR_REF_AVDD__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0001c000U) +#define PMU_PMU3__CTR_REF_AVDD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((uint32_t)(src) <<\ + 14) & 0x0001c000U) +#define PMU_PMU3__CTR_REF_AVDD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0001c000U))) +#define PMU_PMU3__CTR_REF_AVDD__RESET_VALUE 0x00000005U +/** @} */ + +/* macros for field ctr_ldoavdd_enftr */ +/** + * @defgroup pmu_top_regs_core_ctr_ldoavdd_enftr_field ctr_ldoavdd_enftr_field + * @brief macros for field ctr_ldoavdd_enftr + * @details enable fast settling for avdd L2 LDO + * @{ + */ +#define PMU_PMU3__CTR_LDOAVDD_ENFTR__SHIFT 17 +#define PMU_PMU3__CTR_LDOAVDD_ENFTR__WIDTH 1 +#define PMU_PMU3__CTR_LDOAVDD_ENFTR__MASK 0x00020000U +#define PMU_PMU3__CTR_LDOAVDD_ENFTR__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define PMU_PMU3__CTR_LDOAVDD_ENFTR__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define PMU_PMU3__CTR_LDOAVDD_ENFTR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define PMU_PMU3__CTR_LDOAVDD_ENFTR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define PMU_PMU3__CTR_LDOAVDD_ENFTR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define PMU_PMU3__CTR_LDOAVDD_ENFTR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define PMU_PMU3__CTR_LDOAVDD_ENFTR__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field swResavdd_ctrcu */ +/** + * @defgroup pmu_top_regs_core_swResavdd_ctrcu_field swResavdd_ctrcu_field + * @brief macros for field swResavdd_ctrcu + * @details control swResavdd comparator current ctr_cuLow with <1:0>, ctr_cuMid with <3:2>, ctr_cuMidx2 with <4> + * @{ + */ +#define PMU_PMU3__SWRESAVDD_CTRCU__SHIFT 18 +#define PMU_PMU3__SWRESAVDD_CTRCU__WIDTH 5 +#define PMU_PMU3__SWRESAVDD_CTRCU__MASK 0x007c0000U +#define PMU_PMU3__SWRESAVDD_CTRCU__READ(src) \ + (((uint32_t)(src)\ + & 0x007c0000U) >> 18) +#define PMU_PMU3__SWRESAVDD_CTRCU__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x007c0000U) +#define PMU_PMU3__SWRESAVDD_CTRCU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007c0000U) | (((uint32_t)(src) <<\ + 18) & 0x007c0000U) +#define PMU_PMU3__SWRESAVDD_CTRCU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x007c0000U))) +#define PMU_PMU3__SWRESAVDD_CTRCU__RESET_VALUE 0x0000001fU +/** @} */ + +/* macros for field swResavdd_ctrsamecurr */ +/** + * @defgroup pmu_top_regs_core_swResavdd_ctrsamecurr_field swResavdd_ctrsamecurr_field + * @brief macros for field swResavdd_ctrsamecurr + * @details control slow current in swResavdd comparator0: decrease the slow current1: keep the slow current equal to the fast + * @{ + */ +#define PMU_PMU3__SWRESAVDD_CTRSAMECURR__SHIFT 23 +#define PMU_PMU3__SWRESAVDD_CTRSAMECURR__WIDTH 1 +#define PMU_PMU3__SWRESAVDD_CTRSAMECURR__MASK 0x00800000U +#define PMU_PMU3__SWRESAVDD_CTRSAMECURR__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PMU_PMU3__SWRESAVDD_CTRSAMECURR__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define PMU_PMU3__SWRESAVDD_CTRSAMECURR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define PMU_PMU3__SWRESAVDD_CTRSAMECURR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define PMU_PMU3__SWRESAVDD_CTRSAMECURR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PMU_PMU3__SWRESAVDD_CTRSAMECURR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PMU_PMU3__SWRESAVDD_CTRSAMECURR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enampldoavdd_ovr */ +/** + * @defgroup pmu_top_regs_core_enampldoavdd_ovr_field enampldoavdd_ovr_field + * @brief macros for field enampldoavdd_ovr + * @details override enamp_ldoavdd + * @{ + */ +#define PMU_PMU3__ENAMPLDOAVDD_OVR__SHIFT 24 +#define PMU_PMU3__ENAMPLDOAVDD_OVR__WIDTH 1 +#define PMU_PMU3__ENAMPLDOAVDD_OVR__MASK 0x01000000U +#define PMU_PMU3__ENAMPLDOAVDD_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define PMU_PMU3__ENAMPLDOAVDD_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define PMU_PMU3__ENAMPLDOAVDD_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define PMU_PMU3__ENAMPLDOAVDD_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define PMU_PMU3__ENAMPLDOAVDD_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define PMU_PMU3__ENAMPLDOAVDD_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define PMU_PMU3__ENAMPLDOAVDD_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enampldoavdd_ovr_val */ +/** + * @defgroup pmu_top_regs_core_enampldoavdd_ovr_val_field enampldoavdd_ovr_val_field + * @brief macros for field enampldoavdd_ovr_val + * @details override enamp_ldoavdd val: enable the L2 avdd LDO opamp + * @{ + */ +#define PMU_PMU3__ENAMPLDOAVDD_OVR_VAL__SHIFT 25 +#define PMU_PMU3__ENAMPLDOAVDD_OVR_VAL__WIDTH 1 +#define PMU_PMU3__ENAMPLDOAVDD_OVR_VAL__MASK 0x02000000U +#define PMU_PMU3__ENAMPLDOAVDD_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define PMU_PMU3__ENAMPLDOAVDD_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define PMU_PMU3__ENAMPLDOAVDD_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define PMU_PMU3__ENAMPLDOAVDD_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define PMU_PMU3__ENAMPLDOAVDD_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define PMU_PMU3__ENAMPLDOAVDD_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define PMU_PMU3__ENAMPLDOAVDD_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_ldoavdd_ovr */ +/** + * @defgroup pmu_top_regs_core_en_ldoavdd_ovr_field en_ldoavdd_ovr_field + * @brief macros for field en_ldoavdd_ovr + * @details override en_ldoavdd + * @{ + */ +#define PMU_PMU3__EN_LDOAVDD_OVR__SHIFT 26 +#define PMU_PMU3__EN_LDOAVDD_OVR__WIDTH 1 +#define PMU_PMU3__EN_LDOAVDD_OVR__MASK 0x04000000U +#define PMU_PMU3__EN_LDOAVDD_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define PMU_PMU3__EN_LDOAVDD_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define PMU_PMU3__EN_LDOAVDD_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define PMU_PMU3__EN_LDOAVDD_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define PMU_PMU3__EN_LDOAVDD_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define PMU_PMU3__EN_LDOAVDD_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define PMU_PMU3__EN_LDOAVDD_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_ldoavdd_ovr_val */ +/** + * @defgroup pmu_top_regs_core_en_ldoavdd_ovr_val_field en_ldoavdd_ovr_val_field + * @brief macros for field en_ldoavdd_ovr_val + * @details override en_ldoavdd val<0> enables the L2 avdd LDO output regulation<1> controls the L2 avdd LDO output current + * @{ + */ +#define PMU_PMU3__EN_LDOAVDD_OVR_VAL__SHIFT 27 +#define PMU_PMU3__EN_LDOAVDD_OVR_VAL__WIDTH 2 +#define PMU_PMU3__EN_LDOAVDD_OVR_VAL__MASK 0x18000000U +#define PMU_PMU3__EN_LDOAVDD_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x18000000U) >> 27) +#define PMU_PMU3__EN_LDOAVDD_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x18000000U) +#define PMU_PMU3__EN_LDOAVDD_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x18000000U) | (((uint32_t)(src) <<\ + 27) & 0x18000000U) +#define PMU_PMU3__EN_LDOAVDD_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x18000000U))) +#define PMU_PMU3__EN_LDOAVDD_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field swResavdd_encomp_ovr */ +/** + * @defgroup pmu_top_regs_core_swResavdd_encomp_ovr_field swResavdd_encomp_ovr_field + * @brief macros for field swResavdd_encomp_ovr + * @details override swResavdd_encomp + * @{ + */ +#define PMU_PMU3__SWRESAVDD_ENCOMP_OVR__SHIFT 29 +#define PMU_PMU3__SWRESAVDD_ENCOMP_OVR__WIDTH 1 +#define PMU_PMU3__SWRESAVDD_ENCOMP_OVR__MASK 0x20000000U +#define PMU_PMU3__SWRESAVDD_ENCOMP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define PMU_PMU3__SWRESAVDD_ENCOMP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define PMU_PMU3__SWRESAVDD_ENCOMP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define PMU_PMU3__SWRESAVDD_ENCOMP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define PMU_PMU3__SWRESAVDD_ENCOMP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define PMU_PMU3__SWRESAVDD_ENCOMP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define PMU_PMU3__SWRESAVDD_ENCOMP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field swResavdd_encomp_ovr_val */ +/** + * @defgroup pmu_top_regs_core_swResavdd_encomp_ovr_val_field swResavdd_encomp_ovr_val_field + * @brief macros for field swResavdd_encomp_ovr_val + * @details override swResavdd_encomp val: enable L2 avdd swres for idle modes + * @{ + */ +#define PMU_PMU3__SWRESAVDD_ENCOMP_OVR_VAL__SHIFT 30 +#define PMU_PMU3__SWRESAVDD_ENCOMP_OVR_VAL__WIDTH 1 +#define PMU_PMU3__SWRESAVDD_ENCOMP_OVR_VAL__MASK 0x40000000U +#define PMU_PMU3__SWRESAVDD_ENCOMP_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define PMU_PMU3__SWRESAVDD_ENCOMP_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define PMU_PMU3__SWRESAVDD_ENCOMP_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define PMU_PMU3__SWRESAVDD_ENCOMP_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define PMU_PMU3__SWRESAVDD_ENCOMP_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define PMU_PMU3__SWRESAVDD_ENCOMP_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define PMU_PMU3__SWRESAVDD_ENCOMP_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU3__TYPE uint32_t +#define PMU_PMU3__READ 0x7fffffffU +#define PMU_PMU3__WRITE 0x7fffffffU +#define PMU_PMU3__PRESERVED 0x00000000U +#define PMU_PMU3__RESET_VALUE 0x007f5b6fU + +#endif /* __PMU_PMU3_MACRO__ */ + +/** @} end of pmu3 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu4 */ +/** + * @defgroup pmu_top_regs_core_pmu4 pmu4 + * @brief more ate controls definitions. + * @{ + */ +#ifndef __PMU_PMU4_MACRO__ +#define __PMU_PMU4_MACRO__ + +/* macros for field ctr_refBG_dvdd075 */ +/** + * @defgroup pmu_top_regs_core_ctr_refBG_dvdd075_field ctr_refBG_dvdd075_field + * @brief macros for field ctr_refBG_dvdd075 + * @details dvdd ref from refgen startup. dvdd=25*(25+i)mV, i=0:3 + * @{ + */ +#define PMU_PMU4__CTR_REFBG_DVDD075__SHIFT 0 +#define PMU_PMU4__CTR_REFBG_DVDD075__WIDTH 2 +#define PMU_PMU4__CTR_REFBG_DVDD075__MASK 0x00000003U +#define PMU_PMU4__CTR_REFBG_DVDD075__READ(src) ((uint32_t)(src) & 0x00000003U) +#define PMU_PMU4__CTR_REFBG_DVDD075__WRITE(src) ((uint32_t)(src) & 0x00000003U) +#define PMU_PMU4__CTR_REFBG_DVDD075__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define PMU_PMU4__CTR_REFBG_DVDD075__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define PMU_PMU4__CTR_REFBG_DVDD075__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field ctr_refBG_dvdd_active */ +/** + * @defgroup pmu_top_regs_core_ctr_refBG_dvdd_active_field ctr_refBG_dvdd_active_field + * @brief macros for field ctr_refBG_dvdd_active + * @details dvdd ref from refgen active. dvdd=25*(24+i)mV, i=0:24 + * @{ + */ +#define PMU_PMU4__CTR_REFBG_DVDD_ACTIVE__SHIFT 2 +#define PMU_PMU4__CTR_REFBG_DVDD_ACTIVE__WIDTH 5 +#define PMU_PMU4__CTR_REFBG_DVDD_ACTIVE__MASK 0x0000007cU +#define PMU_PMU4__CTR_REFBG_DVDD_ACTIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x0000007cU) >> 2) +#define PMU_PMU4__CTR_REFBG_DVDD_ACTIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000007cU) +#define PMU_PMU4__CTR_REFBG_DVDD_ACTIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007cU) | (((uint32_t)(src) <<\ + 2) & 0x0000007cU) +#define PMU_PMU4__CTR_REFBG_DVDD_ACTIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000007cU))) +#define PMU_PMU4__CTR_REFBG_DVDD_ACTIVE__RESET_VALUE 0x00000014U +/** @} */ + +/* macros for field ctr_refBG_dvdd_hibernate */ +/** + * @defgroup pmu_top_regs_core_ctr_refBG_dvdd_hibernate_field ctr_refBG_dvdd_hibernate_field + * @brief macros for field ctr_refBG_dvdd_hibernate + * @details dvdd ref from refgen hiberate. dvdd=25*(24+i)mV, i=0:24 + * @{ + */ +#define PMU_PMU4__CTR_REFBG_DVDD_HIBERNATE__SHIFT 7 +#define PMU_PMU4__CTR_REFBG_DVDD_HIBERNATE__WIDTH 5 +#define PMU_PMU4__CTR_REFBG_DVDD_HIBERNATE__MASK 0x00000f80U +#define PMU_PMU4__CTR_REFBG_DVDD_HIBERNATE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000f80U) >> 7) +#define PMU_PMU4__CTR_REFBG_DVDD_HIBERNATE__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000f80U) +#define PMU_PMU4__CTR_REFBG_DVDD_HIBERNATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f80U) | (((uint32_t)(src) <<\ + 7) & 0x00000f80U) +#define PMU_PMU4__CTR_REFBG_DVDD_HIBERNATE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000f80U))) +#define PMU_PMU4__CTR_REFBG_DVDD_HIBERNATE__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field ctr_refBG_dvdd_retain */ +/** + * @defgroup pmu_top_regs_core_ctr_refBG_dvdd_retain_field ctr_refBG_dvdd_retain_field + * @brief macros for field ctr_refBG_dvdd_retain + * @details dvdd ref from refgen retain. dvdd=25*(24+i)mV, i=0:24 + * @{ + */ +#define PMU_PMU4__CTR_REFBG_DVDD_RETAIN__SHIFT 12 +#define PMU_PMU4__CTR_REFBG_DVDD_RETAIN__WIDTH 5 +#define PMU_PMU4__CTR_REFBG_DVDD_RETAIN__MASK 0x0001f000U +#define PMU_PMU4__CTR_REFBG_DVDD_RETAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x0001f000U) >> 12) +#define PMU_PMU4__CTR_REFBG_DVDD_RETAIN__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0001f000U) +#define PMU_PMU4__CTR_REFBG_DVDD_RETAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((uint32_t)(src) <<\ + 12) & 0x0001f000U) +#define PMU_PMU4__CTR_REFBG_DVDD_RETAIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0001f000U))) +#define PMU_PMU4__CTR_REFBG_DVDD_RETAIN__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field ctr_refBG_dvdd_socoff */ +/** + * @defgroup pmu_top_regs_core_ctr_refBG_dvdd_socoff_field ctr_refBG_dvdd_socoff_field + * @brief macros for field ctr_refBG_dvdd_socoff + * @details dvdd ref from refgen socoff. dvdd=25*(24+i)mV, i=0:24 + * @{ + */ +#define PMU_PMU4__CTR_REFBG_DVDD_SOCOFF__SHIFT 17 +#define PMU_PMU4__CTR_REFBG_DVDD_SOCOFF__WIDTH 5 +#define PMU_PMU4__CTR_REFBG_DVDD_SOCOFF__MASK 0x003e0000U +#define PMU_PMU4__CTR_REFBG_DVDD_SOCOFF__READ(src) \ + (((uint32_t)(src)\ + & 0x003e0000U) >> 17) +#define PMU_PMU4__CTR_REFBG_DVDD_SOCOFF__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x003e0000U) +#define PMU_PMU4__CTR_REFBG_DVDD_SOCOFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((uint32_t)(src) <<\ + 17) & 0x003e0000U) +#define PMU_PMU4__CTR_REFBG_DVDD_SOCOFF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x003e0000U))) +#define PMU_PMU4__CTR_REFBG_DVDD_SOCOFF__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field ctr_cpuldo_lvl */ +/** + * @defgroup pmu_top_regs_core_ctr_cpuldo_lvl_field ctr_cpuldo_lvl_field + * @brief macros for field ctr_cpuldo_lvl + * @details control cpu LDO output level from 650mV to 1068mV through the fieldsctr_ldocpufbsel[2:0],ctr_refBG_cpuldo[0],ctr_ldocpu_finestp + * @{ + */ +#define PMU_PMU4__CTR_CPULDO_LVL__SHIFT 22 +#define PMU_PMU4__CTR_CPULDO_LVL__WIDTH 5 +#define PMU_PMU4__CTR_CPULDO_LVL__MASK 0x07c00000U +#define PMU_PMU4__CTR_CPULDO_LVL__READ(src) \ + (((uint32_t)(src)\ + & 0x07c00000U) >> 22) +#define PMU_PMU4__CTR_CPULDO_LVL__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x07c00000U) +#define PMU_PMU4__CTR_CPULDO_LVL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((uint32_t)(src) <<\ + 22) & 0x07c00000U) +#define PMU_PMU4__CTR_CPULDO_LVL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x07c00000U))) +#define PMU_PMU4__CTR_CPULDO_LVL__RESET_VALUE 0x00000014U +/** @} */ +#define PMU_PMU4__TYPE uint32_t +#define PMU_PMU4__READ 0x07ffffffU +#define PMU_PMU4__WRITE 0x07ffffffU +#define PMU_PMU4__PRESERVED 0x00000000U +#define PMU_PMU4__RESET_VALUE 0x05210852U + +#endif /* __PMU_PMU4_MACRO__ */ + +/** @} end of pmu4 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu5 */ +/** + * @defgroup pmu_top_regs_core_pmu5 pmu5 + * @brief more pmu controls definitions. + * @{ + */ +#ifndef __PMU_PMU5_MACRO__ +#define __PMU_PMU5_MACRO__ + +/* macros for field socoff_swon_vauxon_ovr */ +/** + * @defgroup pmu_top_regs_core_socoff_swon_vauxon_ovr_field socoff_swon_vauxon_ovr_field + * @brief macros for field socoff_swon_vauxon_ovr + * @details override socoff_swon_vauxon + * @{ + */ +#define PMU_PMU5__SOCOFF_SWON_VAUXON_OVR__SHIFT 0 +#define PMU_PMU5__SOCOFF_SWON_VAUXON_OVR__WIDTH 1 +#define PMU_PMU5__SOCOFF_SWON_VAUXON_OVR__MASK 0x00000001U +#define PMU_PMU5__SOCOFF_SWON_VAUXON_OVR__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PMU_PMU5__SOCOFF_SWON_VAUXON_OVR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PMU_PMU5__SOCOFF_SWON_VAUXON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PMU_PMU5__SOCOFF_SWON_VAUXON_OVR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PMU_PMU5__SOCOFF_SWON_VAUXON_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PMU_PMU5__SOCOFF_SWON_VAUXON_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PMU_PMU5__SOCOFF_SWON_VAUXON_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field socoff_swon_vauxon_ovr_val */ +/** + * @defgroup pmu_top_regs_core_socoff_swon_vauxon_ovr_val_field socoff_swon_vauxon_ovr_val_field + * @brief macros for field socoff_swon_vauxon_ovr_val + * @details override socoff_swon_vauxon val: maintain vaux with switcher in socoff + * @{ + */ +#define PMU_PMU5__SOCOFF_SWON_VAUXON_OVR_VAL__SHIFT 1 +#define PMU_PMU5__SOCOFF_SWON_VAUXON_OVR_VAL__WIDTH 1 +#define PMU_PMU5__SOCOFF_SWON_VAUXON_OVR_VAL__MASK 0x00000002U +#define PMU_PMU5__SOCOFF_SWON_VAUXON_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PMU_PMU5__SOCOFF_SWON_VAUXON_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PMU_PMU5__SOCOFF_SWON_VAUXON_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PMU_PMU5__SOCOFF_SWON_VAUXON_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PMU_PMU5__SOCOFF_SWON_VAUXON_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PMU_PMU5__SOCOFF_SWON_VAUXON_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PMU_PMU5__SOCOFF_SWON_VAUXON_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field socoff_swon_dvddonly_ovr */ +/** + * @defgroup pmu_top_regs_core_socoff_swon_dvddonly_ovr_field socoff_swon_dvddonly_ovr_field + * @brief macros for field socoff_swon_dvddonly_ovr + * @details override socoff_swon_dvddonly + * @{ + */ +#define PMU_PMU5__SOCOFF_SWON_DVDDONLY_OVR__SHIFT 2 +#define PMU_PMU5__SOCOFF_SWON_DVDDONLY_OVR__WIDTH 1 +#define PMU_PMU5__SOCOFF_SWON_DVDDONLY_OVR__MASK 0x00000004U +#define PMU_PMU5__SOCOFF_SWON_DVDDONLY_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PMU_PMU5__SOCOFF_SWON_DVDDONLY_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PMU_PMU5__SOCOFF_SWON_DVDDONLY_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PMU_PMU5__SOCOFF_SWON_DVDDONLY_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PMU_PMU5__SOCOFF_SWON_DVDDONLY_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PMU_PMU5__SOCOFF_SWON_DVDDONLY_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PMU_PMU5__SOCOFF_SWON_DVDDONLY_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field socoff_swon_dvddonly_ovr_val */ +/** + * @defgroup pmu_top_regs_core_socoff_swon_dvddonly_ovr_val_field socoff_swon_dvddonly_ovr_val_field + * @brief macros for field socoff_swon_dvddonly_ovr_val + * @details override socoff_swon_dvddonly val: maintail only dvdd with switcher in socoff + * @{ + */ +#define PMU_PMU5__SOCOFF_SWON_DVDDONLY_OVR_VAL__SHIFT 3 +#define PMU_PMU5__SOCOFF_SWON_DVDDONLY_OVR_VAL__WIDTH 1 +#define PMU_PMU5__SOCOFF_SWON_DVDDONLY_OVR_VAL__MASK 0x00000008U +#define PMU_PMU5__SOCOFF_SWON_DVDDONLY_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PMU_PMU5__SOCOFF_SWON_DVDDONLY_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PMU_PMU5__SOCOFF_SWON_DVDDONLY_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PMU_PMU5__SOCOFF_SWON_DVDDONLY_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PMU_PMU5__SOCOFF_SWON_DVDDONLY_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PMU_PMU5__SOCOFF_SWON_DVDDONLY_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PMU_PMU5__SOCOFF_SWON_DVDDONLY_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reg_scaleEnerg */ +/** + * @defgroup pmu_top_regs_core_reg_scaleEnerg_field reg_scaleEnerg_field + * @brief macros for field reg_scaleEnerg + * @details control scaleEnerg of switcher when the pmuadc output is not available + * @{ + */ +#define PMU_PMU5__REG_SCALEENERG__SHIFT 4 +#define PMU_PMU5__REG_SCALEENERG__WIDTH 9 +#define PMU_PMU5__REG_SCALEENERG__MASK 0x00001ff0U +#define PMU_PMU5__REG_SCALEENERG__READ(src) \ + (((uint32_t)(src)\ + & 0x00001ff0U) >> 4) +#define PMU_PMU5__REG_SCALEENERG__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00001ff0U) +#define PMU_PMU5__REG_SCALEENERG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001ff0U) | (((uint32_t)(src) <<\ + 4) & 0x00001ff0U) +#define PMU_PMU5__REG_SCALEENERG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00001ff0U))) +#define PMU_PMU5__REG_SCALEENERG__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_ldocpu_ovr */ +/** + * @defgroup pmu_top_regs_core_en_ldocpu_ovr_field en_ldocpu_ovr_field + * @brief macros for field en_ldocpu_ovr + * @details override CPU LDO enable + * @{ + */ +#define PMU_PMU5__EN_LDOCPU_OVR__SHIFT 13 +#define PMU_PMU5__EN_LDOCPU_OVR__WIDTH 1 +#define PMU_PMU5__EN_LDOCPU_OVR__MASK 0x00002000U +#define PMU_PMU5__EN_LDOCPU_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define PMU_PMU5__EN_LDOCPU_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define PMU_PMU5__EN_LDOCPU_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define PMU_PMU5__EN_LDOCPU_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define PMU_PMU5__EN_LDOCPU_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define PMU_PMU5__EN_LDOCPU_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define PMU_PMU5__EN_LDOCPU_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_ldocpu_ovr_val */ +/** + * @defgroup pmu_top_regs_core_en_ldocpu_ovr_val_field en_ldocpu_ovr_val_field + * @brief macros for field en_ldocpu_ovr_val + * @details Use CPU LDO when SOC wants a CPU supply or used when override is set + * @{ + */ +#define PMU_PMU5__EN_LDOCPU_OVR_VAL__SHIFT 14 +#define PMU_PMU5__EN_LDOCPU_OVR_VAL__WIDTH 1 +#define PMU_PMU5__EN_LDOCPU_OVR_VAL__MASK 0x00004000U +#define PMU_PMU5__EN_LDOCPU_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PMU_PMU5__EN_LDOCPU_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define PMU_PMU5__EN_LDOCPU_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define PMU_PMU5__EN_LDOCPU_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define PMU_PMU5__EN_LDOCPU_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PMU_PMU5__EN_LDOCPU_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PMU_PMU5__EN_LDOCPU_OVR_VAL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ctr_ldocpu_bypass */ +/** + * @defgroup pmu_top_regs_core_ctr_ldocpu_bypass_field ctr_ldocpu_bypass_field + * @brief macros for field ctr_ldocpu_bypass + * @details Bypass CPU LDO to DVDDmain when SOC wants a CPU supply + * @{ + */ +#define PMU_PMU5__CTR_LDOCPU_BYPASS__SHIFT 15 +#define PMU_PMU5__CTR_LDOCPU_BYPASS__WIDTH 1 +#define PMU_PMU5__CTR_LDOCPU_BYPASS__MASK 0x00008000U +#define PMU_PMU5__CTR_LDOCPU_BYPASS__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define PMU_PMU5__CTR_LDOCPU_BYPASS__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define PMU_PMU5__CTR_LDOCPU_BYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define PMU_PMU5__CTR_LDOCPU_BYPASS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define PMU_PMU5__CTR_LDOCPU_BYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PMU_PMU5__CTR_LDOCPU_BYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PMU_PMU5__CTR_LDOCPU_BYPASS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_ldocpuhf */ +/** + * @defgroup pmu_top_regs_core_en_ldocpuhf_field en_ldocpuhf_field + * @brief macros for field en_ldocpuhf + * @details Enable fast transient response + * @{ + */ +#define PMU_PMU5__EN_LDOCPUHF__SHIFT 16 +#define PMU_PMU5__EN_LDOCPUHF__WIDTH 1 +#define PMU_PMU5__EN_LDOCPUHF__MASK 0x00010000U +#define PMU_PMU5__EN_LDOCPUHF__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define PMU_PMU5__EN_LDOCPUHF__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define PMU_PMU5__EN_LDOCPUHF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define PMU_PMU5__EN_LDOCPUHF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define PMU_PMU5__EN_LDOCPUHF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PMU_PMU5__EN_LDOCPUHF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PMU_PMU5__EN_LDOCPUHF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ctr_ldocpu_hfcurr */ +/** + * @defgroup pmu_top_regs_core_ctr_ldocpu_hfcurr_field ctr_ldocpu_hfcurr_field + * @brief macros for field ctr_ldocpu_hfcurr + * @details Bias current for fast transient circuit + * @{ + */ +#define PMU_PMU5__CTR_LDOCPU_HFCURR__SHIFT 17 +#define PMU_PMU5__CTR_LDOCPU_HFCURR__WIDTH 2 +#define PMU_PMU5__CTR_LDOCPU_HFCURR__MASK 0x00060000U +#define PMU_PMU5__CTR_LDOCPU_HFCURR__READ(src) \ + (((uint32_t)(src)\ + & 0x00060000U) >> 17) +#define PMU_PMU5__CTR_LDOCPU_HFCURR__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00060000U) +#define PMU_PMU5__CTR_LDOCPU_HFCURR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00060000U) | (((uint32_t)(src) <<\ + 17) & 0x00060000U) +#define PMU_PMU5__CTR_LDOCPU_HFCURR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00060000U))) +#define PMU_PMU5__CTR_LDOCPU_HFCURR__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ctr_ldocpucuout */ +/** + * @defgroup pmu_top_regs_core_ctr_ldocpucuout_field ctr_ldocpucuout_field + * @brief macros for field ctr_ldocpucuout + * @details CPU LDO output stage bias current, 0 = 16uA, 1 = 60uA, 2 = 240uA, 3 = 466uA, need at least 70uA total = output stage bias + CPU leakage for stability + * @{ + */ +#define PMU_PMU5__CTR_LDOCPUCUOUT__SHIFT 19 +#define PMU_PMU5__CTR_LDOCPUCUOUT__WIDTH 2 +#define PMU_PMU5__CTR_LDOCPUCUOUT__MASK 0x00180000U +#define PMU_PMU5__CTR_LDOCPUCUOUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define PMU_PMU5__CTR_LDOCPUCUOUT__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define PMU_PMU5__CTR_LDOCPUCUOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define PMU_PMU5__CTR_LDOCPUCUOUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define PMU_PMU5__CTR_LDOCPUCUOUT__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field ctr_ldocpulowcu */ +/** + * @defgroup pmu_top_regs_core_ctr_ldocpulowcu_field ctr_ldocpulowcu_field + * @brief macros for field ctr_ldocpulowcu + * @details Reduce CPU LDO amplifier current for PM, needed for values of ctr_ldocpucuout < 2 + * @{ + */ +#define PMU_PMU5__CTR_LDOCPULOWCU__SHIFT 21 +#define PMU_PMU5__CTR_LDOCPULOWCU__WIDTH 1 +#define PMU_PMU5__CTR_LDOCPULOWCU__MASK 0x00200000U +#define PMU_PMU5__CTR_LDOCPULOWCU__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define PMU_PMU5__CTR_LDOCPULOWCU__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define PMU_PMU5__CTR_LDOCPULOWCU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define PMU_PMU5__CTR_LDOCPULOWCU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define PMU_PMU5__CTR_LDOCPULOWCU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define PMU_PMU5__CTR_LDOCPULOWCU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define PMU_PMU5__CTR_LDOCPULOWCU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_bypstorecpu */ +/** + * @defgroup pmu_top_regs_core_ctr_bypstorecpu_field ctr_bypstorecpu_field + * @brief macros for field ctr_bypstorecpu + * @details Bypass VSTORE to DVDDcpu + * @{ + */ +#define PMU_PMU5__CTR_BYPSTORECPU__SHIFT 22 +#define PMU_PMU5__CTR_BYPSTORECPU__WIDTH 1 +#define PMU_PMU5__CTR_BYPSTORECPU__MASK 0x00400000U +#define PMU_PMU5__CTR_BYPSTORECPU__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define PMU_PMU5__CTR_BYPSTORECPU__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define PMU_PMU5__CTR_BYPSTORECPU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define PMU_PMU5__CTR_BYPSTORECPU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define PMU_PMU5__CTR_BYPSTORECPU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define PMU_PMU5__CTR_BYPSTORECPU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define PMU_PMU5__CTR_BYPSTORECPU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enable_mppt */ +/** + * @defgroup pmu_top_regs_core_enable_mppt_field enable_mppt_field + * @brief macros for field enable_mppt + * @details enable mppt + * @{ + */ +#define PMU_PMU5__ENABLE_MPPT__SHIFT 23 +#define PMU_PMU5__ENABLE_MPPT__WIDTH 1 +#define PMU_PMU5__ENABLE_MPPT__MASK 0x00800000U +#define PMU_PMU5__ENABLE_MPPT__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PMU_PMU5__ENABLE_MPPT__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define PMU_PMU5__ENABLE_MPPT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define PMU_PMU5__ENABLE_MPPT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define PMU_PMU5__ENABLE_MPPT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PMU_PMU5__ENABLE_MPPT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PMU_PMU5__ENABLE_MPPT__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field use_pmuAdc_buckboost */ +/** + * @defgroup pmu_top_regs_core_use_pmuAdc_buckboost_field use_pmuAdc_buckboost_field + * @brief macros for field use_pmuAdc_buckboost + * @details pmu adc buck boost enable + * @{ + */ +#define PMU_PMU5__USE_PMUADC_BUCKBOOST__SHIFT 24 +#define PMU_PMU5__USE_PMUADC_BUCKBOOST__WIDTH 1 +#define PMU_PMU5__USE_PMUADC_BUCKBOOST__MASK 0x01000000U +#define PMU_PMU5__USE_PMUADC_BUCKBOOST__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define PMU_PMU5__USE_PMUADC_BUCKBOOST__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define PMU_PMU5__USE_PMUADC_BUCKBOOST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define PMU_PMU5__USE_PMUADC_BUCKBOOST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define PMU_PMU5__USE_PMUADC_BUCKBOOST__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define PMU_PMU5__USE_PMUADC_BUCKBOOST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define PMU_PMU5__USE_PMUADC_BUCKBOOST__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field use_pmuAdc_ldoctrls */ +/** + * @defgroup pmu_top_regs_core_use_pmuAdc_ldoctrls_field use_pmuAdc_ldoctrls_field + * @brief macros for field use_pmuAdc_ldoctrls + * @details pmu adc ldo control enable + * @{ + */ +#define PMU_PMU5__USE_PMUADC_LDOCTRLS__SHIFT 25 +#define PMU_PMU5__USE_PMUADC_LDOCTRLS__WIDTH 1 +#define PMU_PMU5__USE_PMUADC_LDOCTRLS__MASK 0x02000000U +#define PMU_PMU5__USE_PMUADC_LDOCTRLS__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define PMU_PMU5__USE_PMUADC_LDOCTRLS__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define PMU_PMU5__USE_PMUADC_LDOCTRLS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define PMU_PMU5__USE_PMUADC_LDOCTRLS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define PMU_PMU5__USE_PMUADC_LDOCTRLS__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define PMU_PMU5__USE_PMUADC_LDOCTRLS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define PMU_PMU5__USE_PMUADC_LDOCTRLS__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field use_pmuAdc_chrg */ +/** + * @defgroup pmu_top_regs_core_use_pmuAdc_chrg_field use_pmuAdc_chrg_field + * @brief macros for field use_pmuAdc_chrg + * @details pmu adc charger control enable + * @{ + */ +#define PMU_PMU5__USE_PMUADC_CHRG__SHIFT 26 +#define PMU_PMU5__USE_PMUADC_CHRG__WIDTH 1 +#define PMU_PMU5__USE_PMUADC_CHRG__MASK 0x04000000U +#define PMU_PMU5__USE_PMUADC_CHRG__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define PMU_PMU5__USE_PMUADC_CHRG__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define PMU_PMU5__USE_PMUADC_CHRG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define PMU_PMU5__USE_PMUADC_CHRG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define PMU_PMU5__USE_PMUADC_CHRG__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define PMU_PMU5__USE_PMUADC_CHRG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define PMU_PMU5__USE_PMUADC_CHRG__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field use_pmuAdc_buckboostharv */ +/** + * @defgroup pmu_top_regs_core_use_pmuAdc_buckboostharv_field use_pmuAdc_buckboostharv_field + * @brief macros for field use_pmuAdc_buckboostharv + * @details pmu adc buck boost enable for harv + * @{ + */ +#define PMU_PMU5__USE_PMUADC_BUCKBOOSTHARV__SHIFT 27 +#define PMU_PMU5__USE_PMUADC_BUCKBOOSTHARV__WIDTH 1 +#define PMU_PMU5__USE_PMUADC_BUCKBOOSTHARV__MASK 0x08000000U +#define PMU_PMU5__USE_PMUADC_BUCKBOOSTHARV__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define PMU_PMU5__USE_PMUADC_BUCKBOOSTHARV__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define PMU_PMU5__USE_PMUADC_BUCKBOOSTHARV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define PMU_PMU5__USE_PMUADC_BUCKBOOSTHARV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define PMU_PMU5__USE_PMUADC_BUCKBOOSTHARV__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define PMU_PMU5__USE_PMUADC_BUCKBOOSTHARV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define PMU_PMU5__USE_PMUADC_BUCKBOOSTHARV__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field use_pmuAdc_pn */ +/** + * @defgroup pmu_top_regs_core_use_pmuAdc_pn_field use_pmuAdc_pn_field + * @brief macros for field use_pmuAdc_pn + * @details pmu adc pn control enable + * @{ + */ +#define PMU_PMU5__USE_PMUADC_PN__SHIFT 28 +#define PMU_PMU5__USE_PMUADC_PN__WIDTH 1 +#define PMU_PMU5__USE_PMUADC_PN__MASK 0x10000000U +#define PMU_PMU5__USE_PMUADC_PN__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define PMU_PMU5__USE_PMUADC_PN__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define PMU_PMU5__USE_PMUADC_PN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define PMU_PMU5__USE_PMUADC_PN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define PMU_PMU5__USE_PMUADC_PN__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define PMU_PMU5__USE_PMUADC_PN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define PMU_PMU5__USE_PMUADC_PN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field force_pmuAdc_rst */ +/** + * @defgroup pmu_top_regs_core_force_pmuAdc_rst_field force_pmuAdc_rst_field + * @brief macros for field force_pmuAdc_rst + * @details 0: enable pmuadc, 1: disable pmuadc + * @{ + */ +#define PMU_PMU5__FORCE_PMUADC_RST__SHIFT 29 +#define PMU_PMU5__FORCE_PMUADC_RST__WIDTH 1 +#define PMU_PMU5__FORCE_PMUADC_RST__MASK 0x20000000U +#define PMU_PMU5__FORCE_PMUADC_RST__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define PMU_PMU5__FORCE_PMUADC_RST__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define PMU_PMU5__FORCE_PMUADC_RST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define PMU_PMU5__FORCE_PMUADC_RST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define PMU_PMU5__FORCE_PMUADC_RST__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define PMU_PMU5__FORCE_PMUADC_RST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define PMU_PMU5__FORCE_PMUADC_RST__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field boost_vbat_vaux_reg */ +/** + * @defgroup pmu_top_regs_core_boost_vbat_vaux_reg_field boost_vbat_vaux_reg_field + * @brief macros for field boost_vbat_vaux_reg + * @details keep disabled at startup. Software will enable after cold start + * @{ + */ +#define PMU_PMU5__BOOST_VBAT_VAUX_REG__SHIFT 30 +#define PMU_PMU5__BOOST_VBAT_VAUX_REG__WIDTH 1 +#define PMU_PMU5__BOOST_VBAT_VAUX_REG__MASK 0x40000000U +#define PMU_PMU5__BOOST_VBAT_VAUX_REG__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define PMU_PMU5__BOOST_VBAT_VAUX_REG__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define PMU_PMU5__BOOST_VBAT_VAUX_REG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define PMU_PMU5__BOOST_VBAT_VAUX_REG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define PMU_PMU5__BOOST_VBAT_VAUX_REG__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define PMU_PMU5__BOOST_VBAT_VAUX_REG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define PMU_PMU5__BOOST_VBAT_VAUX_REG__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU5__TYPE uint32_t +#define PMU_PMU5__READ 0x7fffffffU +#define PMU_PMU5__WRITE 0x7fffffffU +#define PMU_PMU5__PRESERVED 0x00000000U +#define PMU_PMU5__RESET_VALUE 0x3f934000U + +#endif /* __PMU_PMU5_MACRO__ */ + +/** @} end of pmu5 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu6 */ +/** + * @defgroup pmu_top_regs_core_pmu6 pmu6 + * @brief comparator current controls definitions. + * @{ + */ +#ifndef __PMU_PMU6_MACRO__ +#define __PMU_PMU6_MACRO__ + +/* macros for field ctrcuLow0 */ +/** + * @defgroup pmu_top_regs_core_ctrcuLow0_field ctrcuLow0_field + * @brief macros for field ctrcuLow0 + * @details reset/vstore/vbat/vharv comp current for SOCOFF/HIBERNATE + * @{ + */ +#define PMU_PMU6__CTRCULOW0__SHIFT 0 +#define PMU_PMU6__CTRCULOW0__WIDTH 2 +#define PMU_PMU6__CTRCULOW0__MASK 0x00000003U +#define PMU_PMU6__CTRCULOW0__READ(src) ((uint32_t)(src) & 0x00000003U) +#define PMU_PMU6__CTRCULOW0__WRITE(src) ((uint32_t)(src) & 0x00000003U) +#define PMU_PMU6__CTRCULOW0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define PMU_PMU6__CTRCULOW0__VERIFY(src) (!(((uint32_t)(src) & ~0x00000003U))) +#define PMU_PMU6__CTRCULOW0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctrcuLow1 */ +/** + * @defgroup pmu_top_regs_core_ctrcuLow1_field ctrcuLow1_field + * @brief macros for field ctrcuLow1 + * @details reset/vstore/vbat/vharv comp current for RETAIN + * @{ + */ +#define PMU_PMU6__CTRCULOW1__SHIFT 2 +#define PMU_PMU6__CTRCULOW1__WIDTH 2 +#define PMU_PMU6__CTRCULOW1__MASK 0x0000000cU +#define PMU_PMU6__CTRCULOW1__READ(src) (((uint32_t)(src) & 0x0000000cU) >> 2) +#define PMU_PMU6__CTRCULOW1__WRITE(src) (((uint32_t)(src) << 2) & 0x0000000cU) +#define PMU_PMU6__CTRCULOW1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((uint32_t)(src) <<\ + 2) & 0x0000000cU) +#define PMU_PMU6__CTRCULOW1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000000cU))) +#define PMU_PMU6__CTRCULOW1__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field ctrcuLow2 */ +/** + * @defgroup pmu_top_regs_core_ctrcuLow2_field ctrcuLow2_field + * @brief macros for field ctrcuLow2 + * @details reset/vstore/vbat/vharv comp current for startup/ACTIVE + * @{ + */ +#define PMU_PMU6__CTRCULOW2__SHIFT 4 +#define PMU_PMU6__CTRCULOW2__WIDTH 2 +#define PMU_PMU6__CTRCULOW2__MASK 0x00000030U +#define PMU_PMU6__CTRCULOW2__READ(src) (((uint32_t)(src) & 0x00000030U) >> 4) +#define PMU_PMU6__CTRCULOW2__WRITE(src) (((uint32_t)(src) << 4) & 0x00000030U) +#define PMU_PMU6__CTRCULOW2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((uint32_t)(src) <<\ + 4) & 0x00000030U) +#define PMU_PMU6__CTRCULOW2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000030U))) +#define PMU_PMU6__CTRCULOW2__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field swRes_ctrcu0 */ +/** + * @defgroup pmu_top_regs_core_swRes_ctrcu0_field swRes_ctrcu0_field + * @brief macros for field swRes_ctrcu0 + * @details swres fast current for startup + * @{ + */ +#define PMU_PMU6__SWRES_CTRCU0__SHIFT 6 +#define PMU_PMU6__SWRES_CTRCU0__WIDTH 5 +#define PMU_PMU6__SWRES_CTRCU0__MASK 0x000007c0U +#define PMU_PMU6__SWRES_CTRCU0__READ(src) \ + (((uint32_t)(src)\ + & 0x000007c0U) >> 6) +#define PMU_PMU6__SWRES_CTRCU0__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000007c0U) +#define PMU_PMU6__SWRES_CTRCU0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007c0U) | (((uint32_t)(src) <<\ + 6) & 0x000007c0U) +#define PMU_PMU6__SWRES_CTRCU0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000007c0U))) +#define PMU_PMU6__SWRES_CTRCU0__RESET_VALUE 0x00000017U +/** @} */ + +/* macros for field SwchReqDVDD_ctrcu2 */ +/** + * @defgroup pmu_top_regs_core_SwchReqDVDD_ctrcu2_field SwchReqDVDD_ctrcu2_field + * @brief macros for field SwchReqDVDD_ctrcu2 + * @details SwchReqDVDD comp current for startup/ACTIVE + * @{ + */ +#define PMU_PMU6__SWCHREQDVDD_CTRCU2__SHIFT 11 +#define PMU_PMU6__SWCHREQDVDD_CTRCU2__WIDTH 2 +#define PMU_PMU6__SWCHREQDVDD_CTRCU2__MASK 0x00001800U +#define PMU_PMU6__SWCHREQDVDD_CTRCU2__READ(src) \ + (((uint32_t)(src)\ + & 0x00001800U) >> 11) +#define PMU_PMU6__SWCHREQDVDD_CTRCU2__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00001800U) +#define PMU_PMU6__SWCHREQDVDD_CTRCU2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001800U) | (((uint32_t)(src) <<\ + 11) & 0x00001800U) +#define PMU_PMU6__SWCHREQDVDD_CTRCU2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00001800U))) +#define PMU_PMU6__SWCHREQDVDD_CTRCU2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqDVDD_ctrcu1 */ +/** + * @defgroup pmu_top_regs_core_SwchReqDVDD_ctrcu1_field SwchReqDVDD_ctrcu1_field + * @brief macros for field SwchReqDVDD_ctrcu1 + * @details SwchReqDVDD comp current for RETAIN + * @{ + */ +#define PMU_PMU6__SWCHREQDVDD_CTRCU1__SHIFT 13 +#define PMU_PMU6__SWCHREQDVDD_CTRCU1__WIDTH 3 +#define PMU_PMU6__SWCHREQDVDD_CTRCU1__MASK 0x0000e000U +#define PMU_PMU6__SWCHREQDVDD_CTRCU1__READ(src) \ + (((uint32_t)(src)\ + & 0x0000e000U) >> 13) +#define PMU_PMU6__SWCHREQDVDD_CTRCU1__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0000e000U) +#define PMU_PMU6__SWCHREQDVDD_CTRCU1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((uint32_t)(src) <<\ + 13) & 0x0000e000U) +#define PMU_PMU6__SWCHREQDVDD_CTRCU1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0000e000U))) +#define PMU_PMU6__SWCHREQDVDD_CTRCU1__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field SwchReqDVDD_ctrcu0 */ +/** + * @defgroup pmu_top_regs_core_SwchReqDVDD_ctrcu0_field SwchReqDVDD_ctrcu0_field + * @brief macros for field SwchReqDVDD_ctrcu0 + * @details SwchReqDVDD comp current for SOCOFF/HIBERNATE + * @{ + */ +#define PMU_PMU6__SWCHREQDVDD_CTRCU0__SHIFT 16 +#define PMU_PMU6__SWCHREQDVDD_CTRCU0__WIDTH 3 +#define PMU_PMU6__SWCHREQDVDD_CTRCU0__MASK 0x00070000U +#define PMU_PMU6__SWCHREQDVDD_CTRCU0__READ(src) \ + (((uint32_t)(src)\ + & 0x00070000U) >> 16) +#define PMU_PMU6__SWCHREQDVDD_CTRCU0__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00070000U) +#define PMU_PMU6__SWCHREQDVDD_CTRCU0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((uint32_t)(src) <<\ + 16) & 0x00070000U) +#define PMU_PMU6__SWCHREQDVDD_CTRCU0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00070000U))) +#define PMU_PMU6__SWCHREQDVDD_CTRCU0__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field SwchReqDVDD_ctrcures1 */ +/** + * @defgroup pmu_top_regs_core_SwchReqDVDD_ctrcures1_field SwchReqDVDD_ctrcures1_field + * @brief macros for field SwchReqDVDD_ctrcures1 + * @details SwchReqDVDD comp current to control L1 dvdd swres for RETAIN + * @{ + */ +#define PMU_PMU6__SWCHREQDVDD_CTRCURES1__SHIFT 19 +#define PMU_PMU6__SWCHREQDVDD_CTRCURES1__WIDTH 3 +#define PMU_PMU6__SWCHREQDVDD_CTRCURES1__MASK 0x00380000U +#define PMU_PMU6__SWCHREQDVDD_CTRCURES1__READ(src) \ + (((uint32_t)(src)\ + & 0x00380000U) >> 19) +#define PMU_PMU6__SWCHREQDVDD_CTRCURES1__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00380000U) +#define PMU_PMU6__SWCHREQDVDD_CTRCURES1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00380000U) | (((uint32_t)(src) <<\ + 19) & 0x00380000U) +#define PMU_PMU6__SWCHREQDVDD_CTRCURES1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00380000U))) +#define PMU_PMU6__SWCHREQDVDD_CTRCURES1__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field SwchReqDVDD_ctrcures0 */ +/** + * @defgroup pmu_top_regs_core_SwchReqDVDD_ctrcures0_field SwchReqDVDD_ctrcures0_field + * @brief macros for field SwchReqDVDD_ctrcures0 + * @details SwchReqDVDD comp current to control L1 dvdd swres for SOCOFF/HIBERNATE + * @{ + */ +#define PMU_PMU6__SWCHREQDVDD_CTRCURES0__SHIFT 22 +#define PMU_PMU6__SWCHREQDVDD_CTRCURES0__WIDTH 3 +#define PMU_PMU6__SWCHREQDVDD_CTRCURES0__MASK 0x01c00000U +#define PMU_PMU6__SWCHREQDVDD_CTRCURES0__READ(src) \ + (((uint32_t)(src)\ + & 0x01c00000U) >> 22) +#define PMU_PMU6__SWCHREQDVDD_CTRCURES0__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x01c00000U) +#define PMU_PMU6__SWCHREQDVDD_CTRCURES0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01c00000U) | (((uint32_t)(src) <<\ + 22) & 0x01c00000U) +#define PMU_PMU6__SWCHREQDVDD_CTRCURES0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x01c00000U))) +#define PMU_PMU6__SWCHREQDVDD_CTRCURES0__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field en_protect_avdd_reg */ +/** + * @defgroup pmu_top_regs_core_en_protect_avdd_reg_field en_protect_avdd_reg_field + * @brief macros for field en_protect_avdd_reg + * @details to enable leak path on avdd if too much input power + * @{ + */ +#define PMU_PMU6__EN_PROTECT_AVDD_REG__SHIFT 25 +#define PMU_PMU6__EN_PROTECT_AVDD_REG__WIDTH 1 +#define PMU_PMU6__EN_PROTECT_AVDD_REG__MASK 0x02000000U +#define PMU_PMU6__EN_PROTECT_AVDD_REG__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define PMU_PMU6__EN_PROTECT_AVDD_REG__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define PMU_PMU6__EN_PROTECT_AVDD_REG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define PMU_PMU6__EN_PROTECT_AVDD_REG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define PMU_PMU6__EN_PROTECT_AVDD_REG__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define PMU_PMU6__EN_PROTECT_AVDD_REG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define PMU_PMU6__EN_PROTECT_AVDD_REG__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_protect_dvdd_reg */ +/** + * @defgroup pmu_top_regs_core_en_protect_dvdd_reg_field en_protect_dvdd_reg_field + * @brief macros for field en_protect_dvdd_reg + * @details to enable leak path on dvdd if too much input power + * @{ + */ +#define PMU_PMU6__EN_PROTECT_DVDD_REG__SHIFT 26 +#define PMU_PMU6__EN_PROTECT_DVDD_REG__WIDTH 1 +#define PMU_PMU6__EN_PROTECT_DVDD_REG__MASK 0x04000000U +#define PMU_PMU6__EN_PROTECT_DVDD_REG__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define PMU_PMU6__EN_PROTECT_DVDD_REG__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define PMU_PMU6__EN_PROTECT_DVDD_REG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define PMU_PMU6__EN_PROTECT_DVDD_REG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define PMU_PMU6__EN_PROTECT_DVDD_REG__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define PMU_PMU6__EN_PROTECT_DVDD_REG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define PMU_PMU6__EN_PROTECT_DVDD_REG__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_protect_vddio_reg */ +/** + * @defgroup pmu_top_regs_core_en_protect_vddio_reg_field en_protect_vddio_reg_field + * @brief macros for field en_protect_vddio_reg + * @details to enable leak path on vddio if too much input power + * @{ + */ +#define PMU_PMU6__EN_PROTECT_VDDIO_REG__SHIFT 27 +#define PMU_PMU6__EN_PROTECT_VDDIO_REG__WIDTH 1 +#define PMU_PMU6__EN_PROTECT_VDDIO_REG__MASK 0x08000000U +#define PMU_PMU6__EN_PROTECT_VDDIO_REG__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define PMU_PMU6__EN_PROTECT_VDDIO_REG__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define PMU_PMU6__EN_PROTECT_VDDIO_REG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define PMU_PMU6__EN_PROTECT_VDDIO_REG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define PMU_PMU6__EN_PROTECT_VDDIO_REG__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define PMU_PMU6__EN_PROTECT_VDDIO_REG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define PMU_PMU6__EN_PROTECT_VDDIO_REG__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU6__TYPE uint32_t +#define PMU_PMU6__READ 0x0fffffffU +#define PMU_PMU6__WRITE 0x0fffffffU +#define PMU_PMU6__PRESERVED 0x00000000U +#define PMU_PMU6__RESET_VALUE 0x004925f8U + +#endif /* __PMU_PMU6_MACRO__ */ + +/** @} end of pmu6 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu7 */ +/** + * @defgroup pmu_top_regs_core_pmu7 pmu7 + * @brief more comparator_current controls definitions. + * @{ + */ +#ifndef __PMU_PMU7_MACRO__ +#define __PMU_PMU7_MACRO__ + +/* macros for field SwchReqVDDIO_ctrcu2 */ +/** + * @defgroup pmu_top_regs_core_SwchReqVDDIO_ctrcu2_field SwchReqVDDIO_ctrcu2_field + * @brief macros for field SwchReqVDDIO_ctrcu2 + * @details SwchReqVDDIO comp current for startup/ACTIVE + * @{ + */ +#define PMU_PMU7__SWCHREQVDDIO_CTRCU2__SHIFT 0 +#define PMU_PMU7__SWCHREQVDDIO_CTRCU2__WIDTH 2 +#define PMU_PMU7__SWCHREQVDDIO_CTRCU2__MASK 0x00000003U +#define PMU_PMU7__SWCHREQVDDIO_CTRCU2__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PMU_PMU7__SWCHREQVDDIO_CTRCU2__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define PMU_PMU7__SWCHREQVDDIO_CTRCU2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define PMU_PMU7__SWCHREQVDDIO_CTRCU2__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define PMU_PMU7__SWCHREQVDDIO_CTRCU2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqVDDIO_ctrcu1 */ +/** + * @defgroup pmu_top_regs_core_SwchReqVDDIO_ctrcu1_field SwchReqVDDIO_ctrcu1_field + * @brief macros for field SwchReqVDDIO_ctrcu1 + * @details SwchReqVDDIO comp current for RETAIN + * @{ + */ +#define PMU_PMU7__SWCHREQVDDIO_CTRCU1__SHIFT 2 +#define PMU_PMU7__SWCHREQVDDIO_CTRCU1__WIDTH 3 +#define PMU_PMU7__SWCHREQVDDIO_CTRCU1__MASK 0x0000001cU +#define PMU_PMU7__SWCHREQVDDIO_CTRCU1__READ(src) \ + (((uint32_t)(src)\ + & 0x0000001cU) >> 2) +#define PMU_PMU7__SWCHREQVDDIO_CTRCU1__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000001cU) +#define PMU_PMU7__SWCHREQVDDIO_CTRCU1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((uint32_t)(src) <<\ + 2) & 0x0000001cU) +#define PMU_PMU7__SWCHREQVDDIO_CTRCU1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000001cU))) +#define PMU_PMU7__SWCHREQVDDIO_CTRCU1__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field SwchReqVDDIO_ctrcu0 */ +/** + * @defgroup pmu_top_regs_core_SwchReqVDDIO_ctrcu0_field SwchReqVDDIO_ctrcu0_field + * @brief macros for field SwchReqVDDIO_ctrcu0 + * @details SwchReqVDDIO comp current for SOCOFF/HIBERNATE + * @{ + */ +#define PMU_PMU7__SWCHREQVDDIO_CTRCU0__SHIFT 5 +#define PMU_PMU7__SWCHREQVDDIO_CTRCU0__WIDTH 3 +#define PMU_PMU7__SWCHREQVDDIO_CTRCU0__MASK 0x000000e0U +#define PMU_PMU7__SWCHREQVDDIO_CTRCU0__READ(src) \ + (((uint32_t)(src)\ + & 0x000000e0U) >> 5) +#define PMU_PMU7__SWCHREQVDDIO_CTRCU0__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x000000e0U) +#define PMU_PMU7__SWCHREQVDDIO_CTRCU0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((uint32_t)(src) <<\ + 5) & 0x000000e0U) +#define PMU_PMU7__SWCHREQVDDIO_CTRCU0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000000e0U))) +#define PMU_PMU7__SWCHREQVDDIO_CTRCU0__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field SwchReqVDDIO_ctrcures1 */ +/** + * @defgroup pmu_top_regs_core_SwchReqVDDIO_ctrcures1_field SwchReqVDDIO_ctrcures1_field + * @brief macros for field SwchReqVDDIO_ctrcures1 + * @details SwchReqVDDIO comp current to control L1 vddio swres for RETAIN + * @{ + */ +#define PMU_PMU7__SWCHREQVDDIO_CTRCURES1__SHIFT 8 +#define PMU_PMU7__SWCHREQVDDIO_CTRCURES1__WIDTH 3 +#define PMU_PMU7__SWCHREQVDDIO_CTRCURES1__MASK 0x00000700U +#define PMU_PMU7__SWCHREQVDDIO_CTRCURES1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000700U) >> 8) +#define PMU_PMU7__SWCHREQVDDIO_CTRCURES1__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000700U) +#define PMU_PMU7__SWCHREQVDDIO_CTRCURES1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((uint32_t)(src) <<\ + 8) & 0x00000700U) +#define PMU_PMU7__SWCHREQVDDIO_CTRCURES1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000700U))) +#define PMU_PMU7__SWCHREQVDDIO_CTRCURES1__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field SwchReqVDDIO_ctrcures0 */ +/** + * @defgroup pmu_top_regs_core_SwchReqVDDIO_ctrcures0_field SwchReqVDDIO_ctrcures0_field + * @brief macros for field SwchReqVDDIO_ctrcures0 + * @details SwchReqVDDIO comp current to control L1 vddio swres for SOCOFF/HIBERNATE + * @{ + */ +#define PMU_PMU7__SWCHREQVDDIO_CTRCURES0__SHIFT 11 +#define PMU_PMU7__SWCHREQVDDIO_CTRCURES0__WIDTH 3 +#define PMU_PMU7__SWCHREQVDDIO_CTRCURES0__MASK 0x00003800U +#define PMU_PMU7__SWCHREQVDDIO_CTRCURES0__READ(src) \ + (((uint32_t)(src)\ + & 0x00003800U) >> 11) +#define PMU_PMU7__SWCHREQVDDIO_CTRCURES0__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00003800U) +#define PMU_PMU7__SWCHREQVDDIO_CTRCURES0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((uint32_t)(src) <<\ + 11) & 0x00003800U) +#define PMU_PMU7__SWCHREQVDDIO_CTRCURES0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00003800U))) +#define PMU_PMU7__SWCHREQVDDIO_CTRCURES0__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field SwchReqAVDD_ctrcu2 */ +/** + * @defgroup pmu_top_regs_core_SwchReqAVDD_ctrcu2_field SwchReqAVDD_ctrcu2_field + * @brief macros for field SwchReqAVDD_ctrcu2 + * @details SwchReqAVDD comp current for startup/ACTIVE + * @{ + */ +#define PMU_PMU7__SWCHREQAVDD_CTRCU2__SHIFT 14 +#define PMU_PMU7__SWCHREQAVDD_CTRCU2__WIDTH 2 +#define PMU_PMU7__SWCHREQAVDD_CTRCU2__MASK 0x0000c000U +#define PMU_PMU7__SWCHREQAVDD_CTRCU2__READ(src) \ + (((uint32_t)(src)\ + & 0x0000c000U) >> 14) +#define PMU_PMU7__SWCHREQAVDD_CTRCU2__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0000c000U) +#define PMU_PMU7__SWCHREQAVDD_CTRCU2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000c000U) | (((uint32_t)(src) <<\ + 14) & 0x0000c000U) +#define PMU_PMU7__SWCHREQAVDD_CTRCU2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0000c000U))) +#define PMU_PMU7__SWCHREQAVDD_CTRCU2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqAVDD_ctrcu1 */ +/** + * @defgroup pmu_top_regs_core_SwchReqAVDD_ctrcu1_field SwchReqAVDD_ctrcu1_field + * @brief macros for field SwchReqAVDD_ctrcu1 + * @details SwchReqAVDD comp current for RETAIN + * @{ + */ +#define PMU_PMU7__SWCHREQAVDD_CTRCU1__SHIFT 16 +#define PMU_PMU7__SWCHREQAVDD_CTRCU1__WIDTH 3 +#define PMU_PMU7__SWCHREQAVDD_CTRCU1__MASK 0x00070000U +#define PMU_PMU7__SWCHREQAVDD_CTRCU1__READ(src) \ + (((uint32_t)(src)\ + & 0x00070000U) >> 16) +#define PMU_PMU7__SWCHREQAVDD_CTRCU1__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00070000U) +#define PMU_PMU7__SWCHREQAVDD_CTRCU1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((uint32_t)(src) <<\ + 16) & 0x00070000U) +#define PMU_PMU7__SWCHREQAVDD_CTRCU1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00070000U))) +#define PMU_PMU7__SWCHREQAVDD_CTRCU1__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field SwchReqAVDD_ctrcu0 */ +/** + * @defgroup pmu_top_regs_core_SwchReqAVDD_ctrcu0_field SwchReqAVDD_ctrcu0_field + * @brief macros for field SwchReqAVDD_ctrcu0 + * @details SwchReqAVDD comp current for SOCOFF/HIBERNATE + * @{ + */ +#define PMU_PMU7__SWCHREQAVDD_CTRCU0__SHIFT 19 +#define PMU_PMU7__SWCHREQAVDD_CTRCU0__WIDTH 3 +#define PMU_PMU7__SWCHREQAVDD_CTRCU0__MASK 0x00380000U +#define PMU_PMU7__SWCHREQAVDD_CTRCU0__READ(src) \ + (((uint32_t)(src)\ + & 0x00380000U) >> 19) +#define PMU_PMU7__SWCHREQAVDD_CTRCU0__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00380000U) +#define PMU_PMU7__SWCHREQAVDD_CTRCU0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00380000U) | (((uint32_t)(src) <<\ + 19) & 0x00380000U) +#define PMU_PMU7__SWCHREQAVDD_CTRCU0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00380000U))) +#define PMU_PMU7__SWCHREQAVDD_CTRCU0__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field SwchReqVAUX_ctrcu2 */ +/** + * @defgroup pmu_top_regs_core_SwchReqVAUX_ctrcu2_field SwchReqVAUX_ctrcu2_field + * @brief macros for field SwchReqVAUX_ctrcu2 + * @details SwchReqVAUX comp current for startup/ACTIVE + * @{ + */ +#define PMU_PMU7__SWCHREQVAUX_CTRCU2__SHIFT 22 +#define PMU_PMU7__SWCHREQVAUX_CTRCU2__WIDTH 2 +#define PMU_PMU7__SWCHREQVAUX_CTRCU2__MASK 0x00c00000U +#define PMU_PMU7__SWCHREQVAUX_CTRCU2__READ(src) \ + (((uint32_t)(src)\ + & 0x00c00000U) >> 22) +#define PMU_PMU7__SWCHREQVAUX_CTRCU2__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00c00000U) +#define PMU_PMU7__SWCHREQVAUX_CTRCU2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00c00000U) | (((uint32_t)(src) <<\ + 22) & 0x00c00000U) +#define PMU_PMU7__SWCHREQVAUX_CTRCU2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00c00000U))) +#define PMU_PMU7__SWCHREQVAUX_CTRCU2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqVAUX_ctrcu1 */ +/** + * @defgroup pmu_top_regs_core_SwchReqVAUX_ctrcu1_field SwchReqVAUX_ctrcu1_field + * @brief macros for field SwchReqVAUX_ctrcu1 + * @details SwchReqVAUX comp current for RETAIN + * @{ + */ +#define PMU_PMU7__SWCHREQVAUX_CTRCU1__SHIFT 24 +#define PMU_PMU7__SWCHREQVAUX_CTRCU1__WIDTH 3 +#define PMU_PMU7__SWCHREQVAUX_CTRCU1__MASK 0x07000000U +#define PMU_PMU7__SWCHREQVAUX_CTRCU1__READ(src) \ + (((uint32_t)(src)\ + & 0x07000000U) >> 24) +#define PMU_PMU7__SWCHREQVAUX_CTRCU1__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x07000000U) +#define PMU_PMU7__SWCHREQVAUX_CTRCU1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((uint32_t)(src) <<\ + 24) & 0x07000000U) +#define PMU_PMU7__SWCHREQVAUX_CTRCU1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x07000000U))) +#define PMU_PMU7__SWCHREQVAUX_CTRCU1__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field SwchReqVAUX_ctrcu0 */ +/** + * @defgroup pmu_top_regs_core_SwchReqVAUX_ctrcu0_field SwchReqVAUX_ctrcu0_field + * @brief macros for field SwchReqVAUX_ctrcu0 + * @details SwchReqVAUX comp current for SOCOFF/HIBERNATE + * @{ + */ +#define PMU_PMU7__SWCHREQVAUX_CTRCU0__SHIFT 27 +#define PMU_PMU7__SWCHREQVAUX_CTRCU0__WIDTH 3 +#define PMU_PMU7__SWCHREQVAUX_CTRCU0__MASK 0x38000000U +#define PMU_PMU7__SWCHREQVAUX_CTRCU0__READ(src) \ + (((uint32_t)(src)\ + & 0x38000000U) >> 27) +#define PMU_PMU7__SWCHREQVAUX_CTRCU0__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x38000000U) +#define PMU_PMU7__SWCHREQVAUX_CTRCU0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x38000000U) | (((uint32_t)(src) <<\ + 27) & 0x38000000U) +#define PMU_PMU7__SWCHREQVAUX_CTRCU0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x38000000U))) +#define PMU_PMU7__SWCHREQVAUX_CTRCU0__RESET_VALUE 0x00000001U +/** @} */ +#define PMU_PMU7__TYPE uint32_t +#define PMU_PMU7__READ 0x3fffffffU +#define PMU_PMU7__WRITE 0x3fffffffU +#define PMU_PMU7__PRESERVED 0x00000000U +#define PMU_PMU7__RESET_VALUE 0x09090924U + +#endif /* __PMU_PMU7_MACRO__ */ + +/** @} end of pmu7 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu8 */ +/** + * @defgroup pmu_top_regs_core_pmu8 pmu8 + * @brief comparator current controls/ other controls definitions. + * @{ + */ +#ifndef __PMU_PMU8_MACRO__ +#define __PMU_PMU8_MACRO__ + +/* macros for field ctr_trackref1_active */ +/** + * @defgroup pmu_top_regs_core_ctr_trackref1_active_field ctr_trackref1_active_field + * @brief macros for field ctr_trackref1_active + * @details DVDD reference from trackref in active10:0.78V16:0.88V26:1V31:1.06V + * @{ + */ +#define PMU_PMU8__CTR_TRACKREF1_ACTIVE__SHIFT 0 +#define PMU_PMU8__CTR_TRACKREF1_ACTIVE__WIDTH 5 +#define PMU_PMU8__CTR_TRACKREF1_ACTIVE__MASK 0x0000001fU +#define PMU_PMU8__CTR_TRACKREF1_ACTIVE__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define PMU_PMU8__CTR_TRACKREF1_ACTIVE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define PMU_PMU8__CTR_TRACKREF1_ACTIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define PMU_PMU8__CTR_TRACKREF1_ACTIVE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define PMU_PMU8__CTR_TRACKREF1_ACTIVE__RESET_VALUE 0x0000001cU +/** @} */ + +/* macros for field ctr_trackref1_hibernate */ +/** + * @defgroup pmu_top_regs_core_ctr_trackref1_hibernate_field ctr_trackref1_hibernate_field + * @brief macros for field ctr_trackref1_hibernate + * @details DVDD reference from trackref in TRACK1 hibernate10:0.78V16:0.88V26:1V31:1.06V + * @{ + */ +#define PMU_PMU8__CTR_TRACKREF1_HIBERNATE__SHIFT 5 +#define PMU_PMU8__CTR_TRACKREF1_HIBERNATE__WIDTH 5 +#define PMU_PMU8__CTR_TRACKREF1_HIBERNATE__MASK 0x000003e0U +#define PMU_PMU8__CTR_TRACKREF1_HIBERNATE__READ(src) \ + (((uint32_t)(src)\ + & 0x000003e0U) >> 5) +#define PMU_PMU8__CTR_TRACKREF1_HIBERNATE__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x000003e0U) +#define PMU_PMU8__CTR_TRACKREF1_HIBERNATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((uint32_t)(src) <<\ + 5) & 0x000003e0U) +#define PMU_PMU8__CTR_TRACKREF1_HIBERNATE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000003e0U))) +#define PMU_PMU8__CTR_TRACKREF1_HIBERNATE__RESET_VALUE 0x0000001cU +/** @} */ + +/* macros for field ctr_trackref1_retain */ +/** + * @defgroup pmu_top_regs_core_ctr_trackref1_retain_field ctr_trackref1_retain_field + * @brief macros for field ctr_trackref1_retain + * @details DVDD reference from trackref in TRACK1 retain10:0.78V16:0.88V26:1V31:1.06V + * @{ + */ +#define PMU_PMU8__CTR_TRACKREF1_RETAIN__SHIFT 10 +#define PMU_PMU8__CTR_TRACKREF1_RETAIN__WIDTH 5 +#define PMU_PMU8__CTR_TRACKREF1_RETAIN__MASK 0x00007c00U +#define PMU_PMU8__CTR_TRACKREF1_RETAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x00007c00U) >> 10) +#define PMU_PMU8__CTR_TRACKREF1_RETAIN__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00007c00U) +#define PMU_PMU8__CTR_TRACKREF1_RETAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((uint32_t)(src) <<\ + 10) & 0x00007c00U) +#define PMU_PMU8__CTR_TRACKREF1_RETAIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00007c00U))) +#define PMU_PMU8__CTR_TRACKREF1_RETAIN__RESET_VALUE 0x0000001cU +/** @} */ + +/* macros for field ctr_trackref1_socoff */ +/** + * @defgroup pmu_top_regs_core_ctr_trackref1_socoff_field ctr_trackref1_socoff_field + * @brief macros for field ctr_trackref1_socoff + * @details DVDD reference from trackref in TRACK1 socoff10:0.78V16:0.88V26:1V31:1.06V + * @{ + */ +#define PMU_PMU8__CTR_TRACKREF1_SOCOFF__SHIFT 15 +#define PMU_PMU8__CTR_TRACKREF1_SOCOFF__WIDTH 5 +#define PMU_PMU8__CTR_TRACKREF1_SOCOFF__MASK 0x000f8000U +#define PMU_PMU8__CTR_TRACKREF1_SOCOFF__READ(src) \ + (((uint32_t)(src)\ + & 0x000f8000U) >> 15) +#define PMU_PMU8__CTR_TRACKREF1_SOCOFF__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x000f8000U) +#define PMU_PMU8__CTR_TRACKREF1_SOCOFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((uint32_t)(src) <<\ + 15) & 0x000f8000U) +#define PMU_PMU8__CTR_TRACKREF1_SOCOFF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x000f8000U))) +#define PMU_PMU8__CTR_TRACKREF1_SOCOFF__RESET_VALUE 0x0000001cU +/** @} */ + +/* macros for field ctr_trackref07 */ +/** + * @defgroup pmu_top_regs_core_ctr_trackref07_field ctr_trackref07_field + * @brief macros for field ctr_trackref07 + * @details DVDD reference from trackref in TRACK07 hibernate12:0.7V16:0.74V19:0.78V31:0.89V + * @{ + */ +#define PMU_PMU8__CTR_TRACKREF07__SHIFT 20 +#define PMU_PMU8__CTR_TRACKREF07__WIDTH 5 +#define PMU_PMU8__CTR_TRACKREF07__MASK 0x01f00000U +#define PMU_PMU8__CTR_TRACKREF07__READ(src) \ + (((uint32_t)(src)\ + & 0x01f00000U) >> 20) +#define PMU_PMU8__CTR_TRACKREF07__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x01f00000U) +#define PMU_PMU8__CTR_TRACKREF07__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((uint32_t)(src) <<\ + 20) & 0x01f00000U) +#define PMU_PMU8__CTR_TRACKREF07__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x01f00000U))) +#define PMU_PMU8__CTR_TRACKREF07__RESET_VALUE 0x0000000eU +/** @} */ + +/* macros for field ctr_Vrectrepl */ +/** + * @defgroup pmu_top_regs_core_ctr_Vrectrepl_field ctr_Vrectrepl_field + * @brief macros for field ctr_Vrectrepl + * @details Turn ON the resistive divider of the analog mppt ref generatorCan set it to zero if analog mppt is disabled. + * @{ + */ +#define PMU_PMU8__CTR_VRECTREPL__SHIFT 25 +#define PMU_PMU8__CTR_VRECTREPL__WIDTH 1 +#define PMU_PMU8__CTR_VRECTREPL__MASK 0x02000000U +#define PMU_PMU8__CTR_VRECTREPL__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define PMU_PMU8__CTR_VRECTREPL__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define PMU_PMU8__CTR_VRECTREPL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define PMU_PMU8__CTR_VRECTREPL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define PMU_PMU8__CTR_VRECTREPL__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define PMU_PMU8__CTR_VRECTREPL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define PMU_PMU8__CTR_VRECTREPL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ctr_increctstreg1 */ +/** + * @defgroup pmu_top_regs_core_ctr_increctstreg1_field ctr_increctstreg1_field + * @brief macros for field ctr_increctstreg1 + * @details control Vrefchpu_increctst for chpuhsw_increctstage comparator25*(29 + 5*i)mV, i=1:225* 19 mV, i=0 + * @{ + */ +#define PMU_PMU8__CTR_INCRECTSTREG1__SHIFT 26 +#define PMU_PMU8__CTR_INCRECTSTREG1__WIDTH 2 +#define PMU_PMU8__CTR_INCRECTSTREG1__MASK 0x0c000000U +#define PMU_PMU8__CTR_INCRECTSTREG1__READ(src) \ + (((uint32_t)(src)\ + & 0x0c000000U) >> 26) +#define PMU_PMU8__CTR_INCRECTSTREG1__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x0c000000U) +#define PMU_PMU8__CTR_INCRECTSTREG1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((uint32_t)(src) <<\ + 26) & 0x0c000000U) +#define PMU_PMU8__CTR_INCRECTSTREG1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x0c000000U))) +#define PMU_PMU8__CTR_INCRECTSTREG1__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field ctr_increctstreg2 */ +/** + * @defgroup pmu_top_regs_core_ctr_increctstreg2_field ctr_increctstreg2_field + * @brief macros for field ctr_increctstreg2 + * @details control Vrefchpu_increctst for chpuhsw_increctstage comparator25*(29 + 5*i)mV, i=1:225* 19 mV, i=0 + * @{ + */ +#define PMU_PMU8__CTR_INCRECTSTREG2__SHIFT 28 +#define PMU_PMU8__CTR_INCRECTSTREG2__WIDTH 2 +#define PMU_PMU8__CTR_INCRECTSTREG2__MASK 0x30000000U +#define PMU_PMU8__CTR_INCRECTSTREG2__READ(src) \ + (((uint32_t)(src)\ + & 0x30000000U) >> 28) +#define PMU_PMU8__CTR_INCRECTSTREG2__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x30000000U) +#define PMU_PMU8__CTR_INCRECTSTREG2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x30000000U) | (((uint32_t)(src) <<\ + 28) & 0x30000000U) +#define PMU_PMU8__CTR_INCRECTSTREG2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x30000000U))) +#define PMU_PMU8__CTR_INCRECTSTREG2__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field boost_vsto_vaux_reg */ +/** + * @defgroup pmu_top_regs_core_boost_vsto_vaux_reg_field boost_vsto_vaux_reg_field + * @brief macros for field boost_vsto_vaux_reg + * @details Use software to enable boost in this mode + * @{ + */ +#define PMU_PMU8__BOOST_VSTO_VAUX_REG__SHIFT 30 +#define PMU_PMU8__BOOST_VSTO_VAUX_REG__WIDTH 1 +#define PMU_PMU8__BOOST_VSTO_VAUX_REG__MASK 0x40000000U +#define PMU_PMU8__BOOST_VSTO_VAUX_REG__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define PMU_PMU8__BOOST_VSTO_VAUX_REG__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define PMU_PMU8__BOOST_VSTO_VAUX_REG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define PMU_PMU8__BOOST_VSTO_VAUX_REG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define PMU_PMU8__BOOST_VSTO_VAUX_REG__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define PMU_PMU8__BOOST_VSTO_VAUX_REG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define PMU_PMU8__BOOST_VSTO_VAUX_REG__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU8__TYPE uint32_t +#define PMU_PMU8__READ 0x7fffffffU +#define PMU_PMU8__WRITE 0x7fffffffU +#define PMU_PMU8__PRESERVED 0x00000000U +#define PMU_PMU8__RESET_VALUE 0x0aee739cU + +#endif /* __PMU_PMU8_MACRO__ */ + +/** @} end of pmu8 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu9 */ +/** + * @defgroup pmu_top_regs_core_pmu9 pmu9 + * @brief more pmu controls definitions. + * @{ + */ +#ifndef __PMU_PMU9_MACRO__ +#define __PMU_PMU9_MACRO__ + +/* macros for field ctr_refenergbohy */ +/** + * @defgroup pmu_top_regs_core_ctr_refenergbohy_field ctr_refenergbohy_field + * @brief macros for field ctr_refenergbohy + * @details VrefstogoodtoEner hyst level. VSTOR=25*[56,39,32,26] for i=[3:0] + * @{ + */ +#define PMU_PMU9__CTR_REFENERGBOHY__SHIFT 0 +#define PMU_PMU9__CTR_REFENERGBOHY__WIDTH 2 +#define PMU_PMU9__CTR_REFENERGBOHY__MASK 0x00000003U +#define PMU_PMU9__CTR_REFENERGBOHY__READ(src) ((uint32_t)(src) & 0x00000003U) +#define PMU_PMU9__CTR_REFENERGBOHY__WRITE(src) ((uint32_t)(src) & 0x00000003U) +#define PMU_PMU9__CTR_REFENERGBOHY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define PMU_PMU9__CTR_REFENERGBOHY__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define PMU_PMU9__CTR_REFENERGBOHY__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ctr_mpptstartvharv */ +/** + * @defgroup pmu_top_regs_core_ctr_mpptstartvharv_field ctr_mpptstartvharv_field + * @brief macros for field ctr_mpptstartvharv + * @details unused + * @{ + */ +#define PMU_PMU9__CTR_MPPTSTARTVHARV__SHIFT 2 +#define PMU_PMU9__CTR_MPPTSTARTVHARV__WIDTH 2 +#define PMU_PMU9__CTR_MPPTSTARTVHARV__MASK 0x0000000cU +#define PMU_PMU9__CTR_MPPTSTARTVHARV__READ(src) \ + (((uint32_t)(src)\ + & 0x0000000cU) >> 2) +#define PMU_PMU9__CTR_MPPTSTARTVHARV__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000000cU) +#define PMU_PMU9__CTR_MPPTSTARTVHARV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((uint32_t)(src) <<\ + 2) & 0x0000000cU) +#define PMU_PMU9__CTR_MPPTSTARTVHARV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000000cU))) +#define PMU_PMU9__CTR_MPPTSTARTVHARV__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ctr_rectreplmpp */ +/** + * @defgroup pmu_top_regs_core_ctr_rectreplmpp_field ctr_rectreplmpp_field + * @brief macros for field ctr_rectreplmpp + * @details mppt dynamic reference for SwchReqCanHarv comp + * @{ + */ +#define PMU_PMU9__CTR_RECTREPLMPP__SHIFT 4 +#define PMU_PMU9__CTR_RECTREPLMPP__WIDTH 2 +#define PMU_PMU9__CTR_RECTREPLMPP__MASK 0x00000030U +#define PMU_PMU9__CTR_RECTREPLMPP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000030U) >> 4) +#define PMU_PMU9__CTR_RECTREPLMPP__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000030U) +#define PMU_PMU9__CTR_RECTREPLMPP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((uint32_t)(src) <<\ + 4) & 0x00000030U) +#define PMU_PMU9__CTR_RECTREPLMPP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000030U))) +#define PMU_PMU9__CTR_RECTREPLMPP__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field ctr_rectreplmpp2 */ +/** + * @defgroup pmu_top_regs_core_ctr_rectreplmpp2_field ctr_rectreplmpp2_field + * @brief macros for field ctr_rectreplmpp2 + * @details mppt dynamic reference for SwchReqMustHarv comp + * @{ + */ +#define PMU_PMU9__CTR_RECTREPLMPP2__SHIFT 6 +#define PMU_PMU9__CTR_RECTREPLMPP2__WIDTH 2 +#define PMU_PMU9__CTR_RECTREPLMPP2__MASK 0x000000c0U +#define PMU_PMU9__CTR_RECTREPLMPP2__READ(src) \ + (((uint32_t)(src)\ + & 0x000000c0U) >> 6) +#define PMU_PMU9__CTR_RECTREPLMPP2__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000000c0U) +#define PMU_PMU9__CTR_RECTREPLMPP2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((uint32_t)(src) <<\ + 6) & 0x000000c0U) +#define PMU_PMU9__CTR_RECTREPLMPP2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000000c0U))) +#define PMU_PMU9__CTR_RECTREPLMPP2__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field ctr_ldo_lowpow */ +/** + * @defgroup pmu_top_regs_core_ctr_ldo_lowpow_field ctr_ldo_lowpow_field + * @brief macros for field ctr_ldo_lowpow + * @details ctr_ldomem_lowref: enable the native amplifier for VrefBGdvddmem<700mV + * @{ + */ +#define PMU_PMU9__CTR_LDO_LOWPOW__SHIFT 8 +#define PMU_PMU9__CTR_LDO_LOWPOW__WIDTH 1 +#define PMU_PMU9__CTR_LDO_LOWPOW__MASK 0x00000100U +#define PMU_PMU9__CTR_LDO_LOWPOW__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define PMU_PMU9__CTR_LDO_LOWPOW__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define PMU_PMU9__CTR_LDO_LOWPOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define PMU_PMU9__CTR_LDO_LOWPOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define PMU_PMU9__CTR_LDO_LOWPOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PMU_PMU9__CTR_LDO_LOWPOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PMU_PMU9__CTR_LDO_LOWPOW__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_ldo_smallPMOS */ +/** + * @defgroup pmu_top_regs_core_ctr_ldo_smallPMOS_field ctr_ldo_smallPMOS_field + * @brief macros for field ctr_ldo_smallPMOS + * @details ctr_ldomem_smallPMOS: enable the small PMOS output stage if leakage dominates at minimum DVDDmem load + * @{ + */ +#define PMU_PMU9__CTR_LDO_SMALLPMOS__SHIFT 9 +#define PMU_PMU9__CTR_LDO_SMALLPMOS__WIDTH 1 +#define PMU_PMU9__CTR_LDO_SMALLPMOS__MASK 0x00000200U +#define PMU_PMU9__CTR_LDO_SMALLPMOS__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PMU_PMU9__CTR_LDO_SMALLPMOS__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define PMU_PMU9__CTR_LDO_SMALLPMOS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define PMU_PMU9__CTR_LDO_SMALLPMOS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define PMU_PMU9__CTR_LDO_SMALLPMOS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PMU_PMU9__CTR_LDO_SMALLPMOS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PMU_PMU9__CTR_LDO_SMALLPMOS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_ldo_enftr */ +/** + * @defgroup pmu_top_regs_core_ctr_ldo_enftr_field ctr_ldo_enftr_field + * @brief macros for field ctr_ldo_enftr + * @details ctr_ldomem_enftr: enable ldo_fast settling + * @{ + */ +#define PMU_PMU9__CTR_LDO_ENFTR__SHIFT 10 +#define PMU_PMU9__CTR_LDO_ENFTR__WIDTH 1 +#define PMU_PMU9__CTR_LDO_ENFTR__MASK 0x00000400U +#define PMU_PMU9__CTR_LDO_ENFTR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define PMU_PMU9__CTR_LDO_ENFTR__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define PMU_PMU9__CTR_LDO_ENFTR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define PMU_PMU9__CTR_LDO_ENFTR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define PMU_PMU9__CTR_LDO_ENFTR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define PMU_PMU9__CTR_LDO_ENFTR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define PMU_PMU9__CTR_LDO_ENFTR__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field trans_wait_reg */ +/** + * @defgroup pmu_top_regs_core_trans_wait_reg_field trans_wait_reg_field + * @brief macros for field trans_wait_reg + * @details wait time in transient state when going from low power to active + * @{ + */ +#define PMU_PMU9__TRANS_WAIT_REG__SHIFT 11 +#define PMU_PMU9__TRANS_WAIT_REG__WIDTH 7 +#define PMU_PMU9__TRANS_WAIT_REG__MASK 0x0003f800U +#define PMU_PMU9__TRANS_WAIT_REG__READ(src) \ + (((uint32_t)(src)\ + & 0x0003f800U) >> 11) +#define PMU_PMU9__TRANS_WAIT_REG__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x0003f800U) +#define PMU_PMU9__TRANS_WAIT_REG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f800U) | (((uint32_t)(src) <<\ + 11) & 0x0003f800U) +#define PMU_PMU9__TRANS_WAIT_REG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x0003f800U))) +#define PMU_PMU9__TRANS_WAIT_REG__RESET_VALUE 0x00000014U +/** @} */ + +/* macros for field ctr_swresdvdd_bypass_ovr */ +/** + * @defgroup pmu_top_regs_core_ctr_swresdvdd_bypass_ovr_field ctr_swresdvdd_bypass_ovr_field + * @brief macros for field ctr_swresdvdd_bypass_ovr + * @details override ctr_swresdvdd_bypass + * @{ + */ +#define PMU_PMU9__CTR_SWRESDVDD_BYPASS_OVR__SHIFT 18 +#define PMU_PMU9__CTR_SWRESDVDD_BYPASS_OVR__WIDTH 1 +#define PMU_PMU9__CTR_SWRESDVDD_BYPASS_OVR__MASK 0x00040000U +#define PMU_PMU9__CTR_SWRESDVDD_BYPASS_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define PMU_PMU9__CTR_SWRESDVDD_BYPASS_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define PMU_PMU9__CTR_SWRESDVDD_BYPASS_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define PMU_PMU9__CTR_SWRESDVDD_BYPASS_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define PMU_PMU9__CTR_SWRESDVDD_BYPASS_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define PMU_PMU9__CTR_SWRESDVDD_BYPASS_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define PMU_PMU9__CTR_SWRESDVDD_BYPASS_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_swresdvdd_bypass_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ctr_swresdvdd_bypass_ovr_val_field ctr_swresdvdd_bypass_ovr_val_field + * @brief macros for field ctr_swresdvdd_bypass_ovr_val + * @details override ctr_swresdvdd_bypass val: bypass L1 dvdd swres + * @{ + */ +#define PMU_PMU9__CTR_SWRESDVDD_BYPASS_OVR_VAL__SHIFT 19 +#define PMU_PMU9__CTR_SWRESDVDD_BYPASS_OVR_VAL__WIDTH 1 +#define PMU_PMU9__CTR_SWRESDVDD_BYPASS_OVR_VAL__MASK 0x00080000U +#define PMU_PMU9__CTR_SWRESDVDD_BYPASS_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define PMU_PMU9__CTR_SWRESDVDD_BYPASS_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define PMU_PMU9__CTR_SWRESDVDD_BYPASS_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define PMU_PMU9__CTR_SWRESDVDD_BYPASS_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define PMU_PMU9__CTR_SWRESDVDD_BYPASS_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define PMU_PMU9__CTR_SWRESDVDD_BYPASS_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define PMU_PMU9__CTR_SWRESDVDD_BYPASS_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_ldoL1avdd_bypass_ovr */ +/** + * @defgroup pmu_top_regs_core_ctr_ldoL1avdd_bypass_ovr_field ctr_ldoL1avdd_bypass_ovr_field + * @brief macros for field ctr_ldoL1avdd_bypass_ovr + * @details override ctr_ldoL1avdd_bypass + * @{ + */ +#define PMU_PMU9__CTR_LDOL1AVDD_BYPASS_OVR__SHIFT 20 +#define PMU_PMU9__CTR_LDOL1AVDD_BYPASS_OVR__WIDTH 1 +#define PMU_PMU9__CTR_LDOL1AVDD_BYPASS_OVR__MASK 0x00100000U +#define PMU_PMU9__CTR_LDOL1AVDD_BYPASS_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define PMU_PMU9__CTR_LDOL1AVDD_BYPASS_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define PMU_PMU9__CTR_LDOL1AVDD_BYPASS_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define PMU_PMU9__CTR_LDOL1AVDD_BYPASS_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define PMU_PMU9__CTR_LDOL1AVDD_BYPASS_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define PMU_PMU9__CTR_LDOL1AVDD_BYPASS_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define PMU_PMU9__CTR_LDOL1AVDD_BYPASS_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_ldoL1avdd_bypass_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ctr_ldoL1avdd_bypass_ovr_val_field ctr_ldoL1avdd_bypass_ovr_val_field + * @brief macros for field ctr_ldoL1avdd_bypass_ovr_val + * @details override ctr_ldoL1avdd_bypass val: bypass L1 avdd LDO + * @{ + */ +#define PMU_PMU9__CTR_LDOL1AVDD_BYPASS_OVR_VAL__SHIFT 21 +#define PMU_PMU9__CTR_LDOL1AVDD_BYPASS_OVR_VAL__WIDTH 1 +#define PMU_PMU9__CTR_LDOL1AVDD_BYPASS_OVR_VAL__MASK 0x00200000U +#define PMU_PMU9__CTR_LDOL1AVDD_BYPASS_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define PMU_PMU9__CTR_LDOL1AVDD_BYPASS_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define PMU_PMU9__CTR_LDOL1AVDD_BYPASS_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define PMU_PMU9__CTR_LDOL1AVDD_BYPASS_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define PMU_PMU9__CTR_LDOL1AVDD_BYPASS_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define PMU_PMU9__CTR_LDOL1AVDD_BYPASS_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define PMU_PMU9__CTR_LDOL1AVDD_BYPASS_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_swresavdd_bypass_ovr */ +/** + * @defgroup pmu_top_regs_core_ctr_swresavdd_bypass_ovr_field ctr_swresavdd_bypass_ovr_field + * @brief macros for field ctr_swresavdd_bypass_ovr + * @details override ctr_swresavdd_bypass + * @{ + */ +#define PMU_PMU9__CTR_SWRESAVDD_BYPASS_OVR__SHIFT 22 +#define PMU_PMU9__CTR_SWRESAVDD_BYPASS_OVR__WIDTH 1 +#define PMU_PMU9__CTR_SWRESAVDD_BYPASS_OVR__MASK 0x00400000U +#define PMU_PMU9__CTR_SWRESAVDD_BYPASS_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define PMU_PMU9__CTR_SWRESAVDD_BYPASS_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define PMU_PMU9__CTR_SWRESAVDD_BYPASS_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define PMU_PMU9__CTR_SWRESAVDD_BYPASS_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define PMU_PMU9__CTR_SWRESAVDD_BYPASS_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define PMU_PMU9__CTR_SWRESAVDD_BYPASS_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define PMU_PMU9__CTR_SWRESAVDD_BYPASS_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_swresavdd_bypass_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ctr_swresavdd_bypass_ovr_val_field ctr_swresavdd_bypass_ovr_val_field + * @brief macros for field ctr_swresavdd_bypass_ovr_val + * @details override ctr_swresavdd_bypass val: bypass L1 avdd swres + * @{ + */ +#define PMU_PMU9__CTR_SWRESAVDD_BYPASS_OVR_VAL__SHIFT 23 +#define PMU_PMU9__CTR_SWRESAVDD_BYPASS_OVR_VAL__WIDTH 1 +#define PMU_PMU9__CTR_SWRESAVDD_BYPASS_OVR_VAL__MASK 0x00800000U +#define PMU_PMU9__CTR_SWRESAVDD_BYPASS_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PMU_PMU9__CTR_SWRESAVDD_BYPASS_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define PMU_PMU9__CTR_SWRESAVDD_BYPASS_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define PMU_PMU9__CTR_SWRESAVDD_BYPASS_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define PMU_PMU9__CTR_SWRESAVDD_BYPASS_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PMU_PMU9__CTR_SWRESAVDD_BYPASS_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PMU_PMU9__CTR_SWRESAVDD_BYPASS_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_ldoL1dvdd_bypass_ovr */ +/** + * @defgroup pmu_top_regs_core_ctr_ldoL1dvdd_bypass_ovr_field ctr_ldoL1dvdd_bypass_ovr_field + * @brief macros for field ctr_ldoL1dvdd_bypass_ovr + * @details override ctr_ldoL1dvdd_bypass + * @{ + */ +#define PMU_PMU9__CTR_LDOL1DVDD_BYPASS_OVR__SHIFT 24 +#define PMU_PMU9__CTR_LDOL1DVDD_BYPASS_OVR__WIDTH 1 +#define PMU_PMU9__CTR_LDOL1DVDD_BYPASS_OVR__MASK 0x01000000U +#define PMU_PMU9__CTR_LDOL1DVDD_BYPASS_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define PMU_PMU9__CTR_LDOL1DVDD_BYPASS_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define PMU_PMU9__CTR_LDOL1DVDD_BYPASS_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define PMU_PMU9__CTR_LDOL1DVDD_BYPASS_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define PMU_PMU9__CTR_LDOL1DVDD_BYPASS_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define PMU_PMU9__CTR_LDOL1DVDD_BYPASS_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define PMU_PMU9__CTR_LDOL1DVDD_BYPASS_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_ldoL1dvdd_bypass_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ctr_ldoL1dvdd_bypass_ovr_val_field ctr_ldoL1dvdd_bypass_ovr_val_field + * @brief macros for field ctr_ldoL1dvdd_bypass_ovr_val + * @details override ctr_ldoL1dvdd_bypass val: bypass L1 dvdd LDO + * @{ + */ +#define PMU_PMU9__CTR_LDOL1DVDD_BYPASS_OVR_VAL__SHIFT 25 +#define PMU_PMU9__CTR_LDOL1DVDD_BYPASS_OVR_VAL__WIDTH 1 +#define PMU_PMU9__CTR_LDOL1DVDD_BYPASS_OVR_VAL__MASK 0x02000000U +#define PMU_PMU9__CTR_LDOL1DVDD_BYPASS_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define PMU_PMU9__CTR_LDOL1DVDD_BYPASS_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define PMU_PMU9__CTR_LDOL1DVDD_BYPASS_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define PMU_PMU9__CTR_LDOL1DVDD_BYPASS_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define PMU_PMU9__CTR_LDOL1DVDD_BYPASS_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define PMU_PMU9__CTR_LDOL1DVDD_BYPASS_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define PMU_PMU9__CTR_LDOL1DVDD_BYPASS_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_ldoL1vddio_bypass_ovr */ +/** + * @defgroup pmu_top_regs_core_ctr_ldoL1vddio_bypass_ovr_field ctr_ldoL1vddio_bypass_ovr_field + * @brief macros for field ctr_ldoL1vddio_bypass_ovr + * @details override ctr_ldoL1vddio_bypass + * @{ + */ +#define PMU_PMU9__CTR_LDOL1VDDIO_BYPASS_OVR__SHIFT 26 +#define PMU_PMU9__CTR_LDOL1VDDIO_BYPASS_OVR__WIDTH 1 +#define PMU_PMU9__CTR_LDOL1VDDIO_BYPASS_OVR__MASK 0x04000000U +#define PMU_PMU9__CTR_LDOL1VDDIO_BYPASS_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define PMU_PMU9__CTR_LDOL1VDDIO_BYPASS_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define PMU_PMU9__CTR_LDOL1VDDIO_BYPASS_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define PMU_PMU9__CTR_LDOL1VDDIO_BYPASS_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define PMU_PMU9__CTR_LDOL1VDDIO_BYPASS_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define PMU_PMU9__CTR_LDOL1VDDIO_BYPASS_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define PMU_PMU9__CTR_LDOL1VDDIO_BYPASS_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_ldoL1vddio_bypass_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ctr_ldoL1vddio_bypass_ovr_val_field ctr_ldoL1vddio_bypass_ovr_val_field + * @brief macros for field ctr_ldoL1vddio_bypass_ovr_val + * @details override ctr_ldoL1vddio_bypass val: bypass L1 vddio LDO + * @{ + */ +#define PMU_PMU9__CTR_LDOL1VDDIO_BYPASS_OVR_VAL__SHIFT 27 +#define PMU_PMU9__CTR_LDOL1VDDIO_BYPASS_OVR_VAL__WIDTH 1 +#define PMU_PMU9__CTR_LDOL1VDDIO_BYPASS_OVR_VAL__MASK 0x08000000U +#define PMU_PMU9__CTR_LDOL1VDDIO_BYPASS_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define PMU_PMU9__CTR_LDOL1VDDIO_BYPASS_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define PMU_PMU9__CTR_LDOL1VDDIO_BYPASS_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define PMU_PMU9__CTR_LDOL1VDDIO_BYPASS_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define PMU_PMU9__CTR_LDOL1VDDIO_BYPASS_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define PMU_PMU9__CTR_LDOL1VDDIO_BYPASS_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define PMU_PMU9__CTR_LDOL1VDDIO_BYPASS_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_swresvddio_bypass_ovr */ +/** + * @defgroup pmu_top_regs_core_ctr_swresvddio_bypass_ovr_field ctr_swresvddio_bypass_ovr_field + * @brief macros for field ctr_swresvddio_bypass_ovr + * @details override ctr_swresvddio_bypass + * @{ + */ +#define PMU_PMU9__CTR_SWRESVDDIO_BYPASS_OVR__SHIFT 28 +#define PMU_PMU9__CTR_SWRESVDDIO_BYPASS_OVR__WIDTH 1 +#define PMU_PMU9__CTR_SWRESVDDIO_BYPASS_OVR__MASK 0x10000000U +#define PMU_PMU9__CTR_SWRESVDDIO_BYPASS_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define PMU_PMU9__CTR_SWRESVDDIO_BYPASS_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define PMU_PMU9__CTR_SWRESVDDIO_BYPASS_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define PMU_PMU9__CTR_SWRESVDDIO_BYPASS_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define PMU_PMU9__CTR_SWRESVDDIO_BYPASS_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define PMU_PMU9__CTR_SWRESVDDIO_BYPASS_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define PMU_PMU9__CTR_SWRESVDDIO_BYPASS_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_swresvddio_bypass_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ctr_swresvddio_bypass_ovr_val_field ctr_swresvddio_bypass_ovr_val_field + * @brief macros for field ctr_swresvddio_bypass_ovr_val + * @details override ctr_swresvddio_bypass val: bypass L1 vddio swres + * @{ + */ +#define PMU_PMU9__CTR_SWRESVDDIO_BYPASS_OVR_VAL__SHIFT 29 +#define PMU_PMU9__CTR_SWRESVDDIO_BYPASS_OVR_VAL__WIDTH 1 +#define PMU_PMU9__CTR_SWRESVDDIO_BYPASS_OVR_VAL__MASK 0x20000000U +#define PMU_PMU9__CTR_SWRESVDDIO_BYPASS_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define PMU_PMU9__CTR_SWRESVDDIO_BYPASS_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define PMU_PMU9__CTR_SWRESVDDIO_BYPASS_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define PMU_PMU9__CTR_SWRESVDDIO_BYPASS_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define PMU_PMU9__CTR_SWRESVDDIO_BYPASS_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define PMU_PMU9__CTR_SWRESVDDIO_BYPASS_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define PMU_PMU9__CTR_SWRESVDDIO_BYPASS_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU9__TYPE uint32_t +#define PMU_PMU9__READ 0x3fffffffU +#define PMU_PMU9__WRITE 0x3fffffffU +#define PMU_PMU9__PRESERVED 0x00000000U +#define PMU_PMU9__RESET_VALUE 0x0000a4f5U + +#endif /* __PMU_PMU9_MACRO__ */ + +/** @} end of pmu9 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu10 */ +/** + * @defgroup pmu_top_regs_core_pmu10 pmu10 + * @brief more pmu controls/ reference selects definitions. + * @{ + */ +#ifndef __PMU_PMU10_MACRO__ +#define __PMU_PMU10_MACRO__ + +/* macros for field harv_ctrcu */ +/** + * @defgroup pmu_top_regs_core_harv_ctrcu_field harv_ctrcu_field + * @brief macros for field harv_ctrcu + * @details current control for can/mustharv comparators + * @{ + */ +#define PMU_PMU10__HARV_CTRCU__SHIFT 0 +#define PMU_PMU10__HARV_CTRCU__WIDTH 7 +#define PMU_PMU10__HARV_CTRCU__MASK 0x0000007fU +#define PMU_PMU10__HARV_CTRCU__READ(src) ((uint32_t)(src) & 0x0000007fU) +#define PMU_PMU10__HARV_CTRCU__WRITE(src) ((uint32_t)(src) & 0x0000007fU) +#define PMU_PMU10__HARV_CTRCU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define PMU_PMU10__HARV_CTRCU__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000007fU))) +#define PMU_PMU10__HARV_CTRCU__RESET_VALUE 0x0000000bU +/** @} */ + +/* macros for field bg_active */ +/** + * @defgroup pmu_top_regs_core_bg_active_field bg_active_field + * @brief macros for field bg_active + * @details bandgap ref for active mode, 0 for NATIVE, 1 for PMUBG + * @{ + */ +#define PMU_PMU10__BG_ACTIVE__SHIFT 7 +#define PMU_PMU10__BG_ACTIVE__WIDTH 1 +#define PMU_PMU10__BG_ACTIVE__MASK 0x00000080U +#define PMU_PMU10__BG_ACTIVE__READ(src) (((uint32_t)(src) & 0x00000080U) >> 7) +#define PMU_PMU10__BG_ACTIVE__WRITE(src) (((uint32_t)(src) << 7) & 0x00000080U) +#define PMU_PMU10__BG_ACTIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define PMU_PMU10__BG_ACTIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define PMU_PMU10__BG_ACTIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define PMU_PMU10__BG_ACTIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define PMU_PMU10__BG_ACTIVE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field bg_socoff */ +/** + * @defgroup pmu_top_regs_core_bg_socoff_field bg_socoff_field + * @brief macros for field bg_socoff + * @details bandgap ref for soc-off mode, 0 for NATIVE, 1 for PMUBG + * @{ + */ +#define PMU_PMU10__BG_SOCOFF__SHIFT 8 +#define PMU_PMU10__BG_SOCOFF__WIDTH 1 +#define PMU_PMU10__BG_SOCOFF__MASK 0x00000100U +#define PMU_PMU10__BG_SOCOFF__READ(src) (((uint32_t)(src) & 0x00000100U) >> 8) +#define PMU_PMU10__BG_SOCOFF__WRITE(src) (((uint32_t)(src) << 8) & 0x00000100U) +#define PMU_PMU10__BG_SOCOFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define PMU_PMU10__BG_SOCOFF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define PMU_PMU10__BG_SOCOFF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PMU_PMU10__BG_SOCOFF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PMU_PMU10__BG_SOCOFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bg_hibernate */ +/** + * @defgroup pmu_top_regs_core_bg_hibernate_field bg_hibernate_field + * @brief macros for field bg_hibernate + * @details bandgap ref for hibernate mode, 0 for NATIVE, 1 for PMUBG + * @{ + */ +#define PMU_PMU10__BG_HIBERNATE__SHIFT 9 +#define PMU_PMU10__BG_HIBERNATE__WIDTH 1 +#define PMU_PMU10__BG_HIBERNATE__MASK 0x00000200U +#define PMU_PMU10__BG_HIBERNATE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PMU_PMU10__BG_HIBERNATE__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define PMU_PMU10__BG_HIBERNATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define PMU_PMU10__BG_HIBERNATE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define PMU_PMU10__BG_HIBERNATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PMU_PMU10__BG_HIBERNATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PMU_PMU10__BG_HIBERNATE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bg_retain */ +/** + * @defgroup pmu_top_regs_core_bg_retain_field bg_retain_field + * @brief macros for field bg_retain + * @details bandgap ref for retention mode, 0 for NATIVE, 1 for PMUBG + * @{ + */ +#define PMU_PMU10__BG_RETAIN__SHIFT 10 +#define PMU_PMU10__BG_RETAIN__WIDTH 1 +#define PMU_PMU10__BG_RETAIN__MASK 0x00000400U +#define PMU_PMU10__BG_RETAIN__READ(src) (((uint32_t)(src) & 0x00000400U) >> 10) +#define PMU_PMU10__BG_RETAIN__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define PMU_PMU10__BG_RETAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define PMU_PMU10__BG_RETAIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define PMU_PMU10__BG_RETAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define PMU_PMU10__BG_RETAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define PMU_PMU10__BG_RETAIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field vtrack_hibernate */ +/** + * @defgroup pmu_top_regs_core_vtrack_hibernate_field vtrack_hibernate_field + * @brief macros for field vtrack_hibernate + * @details tracking selected for hibernate , 0 for TRACK07, 1 for TRACK1 + * @{ + */ +#define PMU_PMU10__VTRACK_HIBERNATE__SHIFT 11 +#define PMU_PMU10__VTRACK_HIBERNATE__WIDTH 1 +#define PMU_PMU10__VTRACK_HIBERNATE__MASK 0x00000800U +#define PMU_PMU10__VTRACK_HIBERNATE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define PMU_PMU10__VTRACK_HIBERNATE__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define PMU_PMU10__VTRACK_HIBERNATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define PMU_PMU10__VTRACK_HIBERNATE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define PMU_PMU10__VTRACK_HIBERNATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define PMU_PMU10__VTRACK_HIBERNATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define PMU_PMU10__VTRACK_HIBERNATE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field unused */ +/** + * @defgroup pmu_top_regs_core_unused_field unused_field + * @brief macros for field unused + * @details unused spare, pmu_spares[6] + * @{ + */ +#define PMU_PMU10__UNUSED__SHIFT 12 +#define PMU_PMU10__UNUSED__WIDTH 1 +#define PMU_PMU10__UNUSED__MASK 0x00001000U +#define PMU_PMU10__UNUSED__READ(src) (((uint32_t)(src) & 0x00001000U) >> 12) +#define PMU_PMU10__UNUSED__WRITE(src) (((uint32_t)(src) << 12) & 0x00001000U) +#define PMU_PMU10__UNUSED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define PMU_PMU10__UNUSED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define PMU_PMU10__UNUSED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define PMU_PMU10__UNUSED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define PMU_PMU10__UNUSED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dvddref_active */ +/** + * @defgroup pmu_top_regs_core_dvddref_active_field dvddref_active_field + * @brief macros for field dvddref_active + * @details which ref to be used in active mode, 1 for REFGEN, 0 for TRACK + * @{ + */ +#define PMU_PMU10__DVDDREF_ACTIVE__SHIFT 13 +#define PMU_PMU10__DVDDREF_ACTIVE__WIDTH 1 +#define PMU_PMU10__DVDDREF_ACTIVE__MASK 0x00002000U +#define PMU_PMU10__DVDDREF_ACTIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define PMU_PMU10__DVDDREF_ACTIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define PMU_PMU10__DVDDREF_ACTIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define PMU_PMU10__DVDDREF_ACTIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define PMU_PMU10__DVDDREF_ACTIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define PMU_PMU10__DVDDREF_ACTIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define PMU_PMU10__DVDDREF_ACTIVE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field dvddref_socoff */ +/** + * @defgroup pmu_top_regs_core_dvddref_socoff_field dvddref_socoff_field + * @brief macros for field dvddref_socoff + * @details which ref to be used in soc-off mode, 1 for REFGEN, 0 for TRACK + * @{ + */ +#define PMU_PMU10__DVDDREF_SOCOFF__SHIFT 14 +#define PMU_PMU10__DVDDREF_SOCOFF__WIDTH 1 +#define PMU_PMU10__DVDDREF_SOCOFF__MASK 0x00004000U +#define PMU_PMU10__DVDDREF_SOCOFF__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PMU_PMU10__DVDDREF_SOCOFF__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define PMU_PMU10__DVDDREF_SOCOFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define PMU_PMU10__DVDDREF_SOCOFF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define PMU_PMU10__DVDDREF_SOCOFF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PMU_PMU10__DVDDREF_SOCOFF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PMU_PMU10__DVDDREF_SOCOFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dvddref_hibernate */ +/** + * @defgroup pmu_top_regs_core_dvddref_hibernate_field dvddref_hibernate_field + * @brief macros for field dvddref_hibernate + * @details which ref to be used in hibernate mode, 1 for REFGEN, 0 for TRACK + * @{ + */ +#define PMU_PMU10__DVDDREF_HIBERNATE__SHIFT 15 +#define PMU_PMU10__DVDDREF_HIBERNATE__WIDTH 1 +#define PMU_PMU10__DVDDREF_HIBERNATE__MASK 0x00008000U +#define PMU_PMU10__DVDDREF_HIBERNATE__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define PMU_PMU10__DVDDREF_HIBERNATE__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define PMU_PMU10__DVDDREF_HIBERNATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define PMU_PMU10__DVDDREF_HIBERNATE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define PMU_PMU10__DVDDREF_HIBERNATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PMU_PMU10__DVDDREF_HIBERNATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PMU_PMU10__DVDDREF_HIBERNATE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field dvddref_retain */ +/** + * @defgroup pmu_top_regs_core_dvddref_retain_field dvddref_retain_field + * @brief macros for field dvddref_retain + * @details which ref to be used in retain mode, 1 for REFGEN, 0 for TRACK + * @{ + */ +#define PMU_PMU10__DVDDREF_RETAIN__SHIFT 16 +#define PMU_PMU10__DVDDREF_RETAIN__WIDTH 1 +#define PMU_PMU10__DVDDREF_RETAIN__MASK 0x00010000U +#define PMU_PMU10__DVDDREF_RETAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define PMU_PMU10__DVDDREF_RETAIN__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define PMU_PMU10__DVDDREF_RETAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define PMU_PMU10__DVDDREF_RETAIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define PMU_PMU10__DVDDREF_RETAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PMU_PMU10__DVDDREF_RETAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PMU_PMU10__DVDDREF_RETAIN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field enableHarv2Sup_ovr */ +/** + * @defgroup pmu_top_regs_core_enableHarv2Sup_ovr_field enableHarv2Sup_ovr_field + * @brief macros for field enableHarv2Sup_ovr + * @details override enableHarv2Sup + * @{ + */ +#define PMU_PMU10__ENABLEHARV2SUP_OVR__SHIFT 17 +#define PMU_PMU10__ENABLEHARV2SUP_OVR__WIDTH 1 +#define PMU_PMU10__ENABLEHARV2SUP_OVR__MASK 0x00020000U +#define PMU_PMU10__ENABLEHARV2SUP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define PMU_PMU10__ENABLEHARV2SUP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define PMU_PMU10__ENABLEHARV2SUP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define PMU_PMU10__ENABLEHARV2SUP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define PMU_PMU10__ENABLEHARV2SUP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define PMU_PMU10__ENABLEHARV2SUP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define PMU_PMU10__ENABLEHARV2SUP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enableHarv2Sup_ovr_val */ +/** + * @defgroup pmu_top_regs_core_enableHarv2Sup_ovr_val_field enableHarv2Sup_ovr_val_field + * @brief macros for field enableHarv2Sup_ovr_val + * @details override enableHarv2Sup val: enable harv to supply. If disabled it is only harv to vstore + * @{ + */ +#define PMU_PMU10__ENABLEHARV2SUP_OVR_VAL__SHIFT 18 +#define PMU_PMU10__ENABLEHARV2SUP_OVR_VAL__WIDTH 1 +#define PMU_PMU10__ENABLEHARV2SUP_OVR_VAL__MASK 0x00040000U +#define PMU_PMU10__ENABLEHARV2SUP_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define PMU_PMU10__ENABLEHARV2SUP_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define PMU_PMU10__ENABLEHARV2SUP_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define PMU_PMU10__ENABLEHARV2SUP_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define PMU_PMU10__ENABLEHARV2SUP_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define PMU_PMU10__ENABLEHARV2SUP_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define PMU_PMU10__ENABLEHARV2SUP_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field manual_harv_disable */ +/** + * @defgroup pmu_top_regs_core_manual_harv_disable_field manual_harv_disable_field + * @brief macros for field manual_harv_disable + * @details manually disable harvesters + * @{ + */ +#define PMU_PMU10__MANUAL_HARV_DISABLE__SHIFT 19 +#define PMU_PMU10__MANUAL_HARV_DISABLE__WIDTH 1 +#define PMU_PMU10__MANUAL_HARV_DISABLE__MASK 0x00080000U +#define PMU_PMU10__MANUAL_HARV_DISABLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define PMU_PMU10__MANUAL_HARV_DISABLE__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define PMU_PMU10__MANUAL_HARV_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define PMU_PMU10__MANUAL_HARV_DISABLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define PMU_PMU10__MANUAL_HARV_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define PMU_PMU10__MANUAL_HARV_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define PMU_PMU10__MANUAL_HARV_DISABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dvddlow */ +/** + * @defgroup pmu_top_regs_core_dvddlow_field dvddlow_field + * @brief macros for field dvddlow + * @details connect DVDDmem and DVDDmain both to a lower dvdd + * @{ + */ +#define PMU_PMU10__DVDDLOW__SHIFT 20 +#define PMU_PMU10__DVDDLOW__WIDTH 1 +#define PMU_PMU10__DVDDLOW__MASK 0x00100000U +#define PMU_PMU10__DVDDLOW__READ(src) (((uint32_t)(src) & 0x00100000U) >> 20) +#define PMU_PMU10__DVDDLOW__WRITE(src) (((uint32_t)(src) << 20) & 0x00100000U) +#define PMU_PMU10__DVDDLOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define PMU_PMU10__DVDDLOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define PMU_PMU10__DVDDLOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define PMU_PMU10__DVDDLOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define PMU_PMU10__DVDDLOW__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqDVDD_enswres_ovr */ +/** + * @defgroup pmu_top_regs_core_SwchReqDVDD_enswres_ovr_field SwchReqDVDD_enswres_ovr_field + * @brief macros for field SwchReqDVDD_enswres_ovr + * @details override SwchReqDVDD_enswres + * @{ + */ +#define PMU_PMU10__SWCHREQDVDD_ENSWRES_OVR__SHIFT 21 +#define PMU_PMU10__SWCHREQDVDD_ENSWRES_OVR__WIDTH 1 +#define PMU_PMU10__SWCHREQDVDD_ENSWRES_OVR__MASK 0x00200000U +#define PMU_PMU10__SWCHREQDVDD_ENSWRES_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define PMU_PMU10__SWCHREQDVDD_ENSWRES_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define PMU_PMU10__SWCHREQDVDD_ENSWRES_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define PMU_PMU10__SWCHREQDVDD_ENSWRES_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define PMU_PMU10__SWCHREQDVDD_ENSWRES_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define PMU_PMU10__SWCHREQDVDD_ENSWRES_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define PMU_PMU10__SWCHREQDVDD_ENSWRES_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqDVDD_enswres_ovr_val */ +/** + * @defgroup pmu_top_regs_core_SwchReqDVDD_enswres_ovr_val_field SwchReqDVDD_enswres_ovr_val_field + * @brief macros for field SwchReqDVDD_enswres_ovr_val + * @details override SwchReqDVDD_enswres val: dvdd request comparator drives the swres instead of the switcher + * @{ + */ +#define PMU_PMU10__SWCHREQDVDD_ENSWRES_OVR_VAL__SHIFT 22 +#define PMU_PMU10__SWCHREQDVDD_ENSWRES_OVR_VAL__WIDTH 1 +#define PMU_PMU10__SWCHREQDVDD_ENSWRES_OVR_VAL__MASK 0x00400000U +#define PMU_PMU10__SWCHREQDVDD_ENSWRES_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define PMU_PMU10__SWCHREQDVDD_ENSWRES_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define PMU_PMU10__SWCHREQDVDD_ENSWRES_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define PMU_PMU10__SWCHREQDVDD_ENSWRES_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define PMU_PMU10__SWCHREQDVDD_ENSWRES_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define PMU_PMU10__SWCHREQDVDD_ENSWRES_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define PMU_PMU10__SWCHREQDVDD_ENSWRES_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqAVDD_enswres_ovr */ +/** + * @defgroup pmu_top_regs_core_SwchReqAVDD_enswres_ovr_field SwchReqAVDD_enswres_ovr_field + * @brief macros for field SwchReqAVDD_enswres_ovr + * @details override SwchReqAVDD_enswres + * @{ + */ +#define PMU_PMU10__SWCHREQAVDD_ENSWRES_OVR__SHIFT 23 +#define PMU_PMU10__SWCHREQAVDD_ENSWRES_OVR__WIDTH 1 +#define PMU_PMU10__SWCHREQAVDD_ENSWRES_OVR__MASK 0x00800000U +#define PMU_PMU10__SWCHREQAVDD_ENSWRES_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PMU_PMU10__SWCHREQAVDD_ENSWRES_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define PMU_PMU10__SWCHREQAVDD_ENSWRES_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define PMU_PMU10__SWCHREQAVDD_ENSWRES_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define PMU_PMU10__SWCHREQAVDD_ENSWRES_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PMU_PMU10__SWCHREQAVDD_ENSWRES_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PMU_PMU10__SWCHREQAVDD_ENSWRES_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqAVDD_enswres_ovr_val */ +/** + * @defgroup pmu_top_regs_core_SwchReqAVDD_enswres_ovr_val_field SwchReqAVDD_enswres_ovr_val_field + * @brief macros for field SwchReqAVDD_enswres_ovr_val + * @details override SwchReqAVDD_enswres val: avdd request comparator drives the swres instead of the switcher + * @{ + */ +#define PMU_PMU10__SWCHREQAVDD_ENSWRES_OVR_VAL__SHIFT 24 +#define PMU_PMU10__SWCHREQAVDD_ENSWRES_OVR_VAL__WIDTH 1 +#define PMU_PMU10__SWCHREQAVDD_ENSWRES_OVR_VAL__MASK 0x01000000U +#define PMU_PMU10__SWCHREQAVDD_ENSWRES_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define PMU_PMU10__SWCHREQAVDD_ENSWRES_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define PMU_PMU10__SWCHREQAVDD_ENSWRES_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define PMU_PMU10__SWCHREQAVDD_ENSWRES_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define PMU_PMU10__SWCHREQAVDD_ENSWRES_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define PMU_PMU10__SWCHREQAVDD_ENSWRES_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define PMU_PMU10__SWCHREQAVDD_ENSWRES_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqVDDIO_enswres_ovr */ +/** + * @defgroup pmu_top_regs_core_SwchReqVDDIO_enswres_ovr_field SwchReqVDDIO_enswres_ovr_field + * @brief macros for field SwchReqVDDIO_enswres_ovr + * @details override SwchReqVDDIO_enswres + * @{ + */ +#define PMU_PMU10__SWCHREQVDDIO_ENSWRES_OVR__SHIFT 25 +#define PMU_PMU10__SWCHREQVDDIO_ENSWRES_OVR__WIDTH 1 +#define PMU_PMU10__SWCHREQVDDIO_ENSWRES_OVR__MASK 0x02000000U +#define PMU_PMU10__SWCHREQVDDIO_ENSWRES_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define PMU_PMU10__SWCHREQVDDIO_ENSWRES_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define PMU_PMU10__SWCHREQVDDIO_ENSWRES_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define PMU_PMU10__SWCHREQVDDIO_ENSWRES_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define PMU_PMU10__SWCHREQVDDIO_ENSWRES_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define PMU_PMU10__SWCHREQVDDIO_ENSWRES_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define PMU_PMU10__SWCHREQVDDIO_ENSWRES_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqVDDIO_enswres_ovr_val */ +/** + * @defgroup pmu_top_regs_core_SwchReqVDDIO_enswres_ovr_val_field SwchReqVDDIO_enswres_ovr_val_field + * @brief macros for field SwchReqVDDIO_enswres_ovr_val + * @details override SwchReqVDDIO_enswres val: vddio request comparator drives the swres instead of the switcher + * @{ + */ +#define PMU_PMU10__SWCHREQVDDIO_ENSWRES_OVR_VAL__SHIFT 26 +#define PMU_PMU10__SWCHREQVDDIO_ENSWRES_OVR_VAL__WIDTH 1 +#define PMU_PMU10__SWCHREQVDDIO_ENSWRES_OVR_VAL__MASK 0x04000000U +#define PMU_PMU10__SWCHREQVDDIO_ENSWRES_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define PMU_PMU10__SWCHREQVDDIO_ENSWRES_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define PMU_PMU10__SWCHREQVDDIO_ENSWRES_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define PMU_PMU10__SWCHREQVDDIO_ENSWRES_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define PMU_PMU10__SWCHREQVDDIO_ENSWRES_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define PMU_PMU10__SWCHREQVDDIO_ENSWRES_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define PMU_PMU10__SWCHREQVDDIO_ENSWRES_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field disableb_L1_ldos */ +/** + * @defgroup pmu_top_regs_core_disableb_L1_ldos_field disableb_L1_ldos_field + * @brief macros for field disableb_L1_ldos + * @details enable using the L1 LDOs based on pmuadc control + * @{ + */ +#define PMU_PMU10__DISABLEB_L1_LDOS__SHIFT 27 +#define PMU_PMU10__DISABLEB_L1_LDOS__WIDTH 1 +#define PMU_PMU10__DISABLEB_L1_LDOS__MASK 0x08000000U +#define PMU_PMU10__DISABLEB_L1_LDOS__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define PMU_PMU10__DISABLEB_L1_LDOS__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define PMU_PMU10__DISABLEB_L1_LDOS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define PMU_PMU10__DISABLEB_L1_LDOS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define PMU_PMU10__DISABLEB_L1_LDOS__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define PMU_PMU10__DISABLEB_L1_LDOS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define PMU_PMU10__DISABLEB_L1_LDOS__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field tinySourceStore_ovr */ +/** + * @defgroup pmu_top_regs_core_tinySourceStore_ovr_field tinySourceStore_ovr_field + * @brief macros for field tinySourceStore_ovr + * @details override and assert tinySourceStore, use store as source with tiny FSM + * @{ + */ +#define PMU_PMU10__TINYSOURCESTORE_OVR__SHIFT 28 +#define PMU_PMU10__TINYSOURCESTORE_OVR__WIDTH 1 +#define PMU_PMU10__TINYSOURCESTORE_OVR__MASK 0x10000000U +#define PMU_PMU10__TINYSOURCESTORE_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define PMU_PMU10__TINYSOURCESTORE_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define PMU_PMU10__TINYSOURCESTORE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define PMU_PMU10__TINYSOURCESTORE_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define PMU_PMU10__TINYSOURCESTORE_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define PMU_PMU10__TINYSOURCESTORE_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define PMU_PMU10__TINYSOURCESTORE_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field increctst_encomp_ovr */ +/** + * @defgroup pmu_top_regs_core_increctst_encomp_ovr_field increctst_encomp_ovr_field + * @brief macros for field increctst_encomp_ovr + * @details override increctst_encomp + * @{ + */ +#define PMU_PMU10__INCRECTST_ENCOMP_OVR__SHIFT 29 +#define PMU_PMU10__INCRECTST_ENCOMP_OVR__WIDTH 1 +#define PMU_PMU10__INCRECTST_ENCOMP_OVR__MASK 0x20000000U +#define PMU_PMU10__INCRECTST_ENCOMP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define PMU_PMU10__INCRECTST_ENCOMP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define PMU_PMU10__INCRECTST_ENCOMP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define PMU_PMU10__INCRECTST_ENCOMP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define PMU_PMU10__INCRECTST_ENCOMP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define PMU_PMU10__INCRECTST_ENCOMP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define PMU_PMU10__INCRECTST_ENCOMP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field increctst_encomp_ovr_val */ +/** + * @defgroup pmu_top_regs_core_increctst_encomp_ovr_val_field increctst_encomp_ovr_val_field + * @brief macros for field increctst_encomp_ovr_val + * @details override increctst_encomp val: enable chpuhsw_increctstage comparator + * @{ + */ +#define PMU_PMU10__INCRECTST_ENCOMP_OVR_VAL__SHIFT 30 +#define PMU_PMU10__INCRECTST_ENCOMP_OVR_VAL__WIDTH 1 +#define PMU_PMU10__INCRECTST_ENCOMP_OVR_VAL__MASK 0x40000000U +#define PMU_PMU10__INCRECTST_ENCOMP_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define PMU_PMU10__INCRECTST_ENCOMP_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define PMU_PMU10__INCRECTST_ENCOMP_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define PMU_PMU10__INCRECTST_ENCOMP_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define PMU_PMU10__INCRECTST_ENCOMP_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define PMU_PMU10__INCRECTST_ENCOMP_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define PMU_PMU10__INCRECTST_ENCOMP_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU10__TYPE uint32_t +#define PMU_PMU10__READ 0x7fffffffU +#define PMU_PMU10__WRITE 0x7fffffffU +#define PMU_PMU10__PRESERVED 0x00000000U +#define PMU_PMU10__RESET_VALUE 0x0801a08bU + +#endif /* __PMU_PMU10_MACRO__ */ + +/** @} end of pmu10 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu11 */ +/** + * @defgroup pmu_top_regs_core_pmu11 pmu11 + * @brief atb and clocks definitions. + * @{ + */ +#ifndef __PMU_PMU11_MACRO__ +#define __PMU_PMU11_MACRO__ + +/* macros for field wurx_clk_en */ +/** + * @defgroup pmu_top_regs_core_wurx_clk_en_field wurx_clk_en_field + * @brief macros for field wurx_clk_en + * @details clk enable for wurx 32KHz clk + * @{ + */ +#define PMU_PMU11__WURX_CLK_EN__SHIFT 0 +#define PMU_PMU11__WURX_CLK_EN__WIDTH 1 +#define PMU_PMU11__WURX_CLK_EN__MASK 0x00000001U +#define PMU_PMU11__WURX_CLK_EN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PMU_PMU11__WURX_CLK_EN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PMU_PMU11__WURX_CLK_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PMU_PMU11__WURX_CLK_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PMU_PMU11__WURX_CLK_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PMU_PMU11__WURX_CLK_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PMU_PMU11__WURX_CLK_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dig_clk_en */ +/** + * @defgroup pmu_top_regs_core_dig_clk_en_field dig_clk_en_field + * @brief macros for field dig_clk_en + * @details clk enable for digital 32KHz clk + * @{ + */ +#define PMU_PMU11__DIG_CLK_EN__SHIFT 1 +#define PMU_PMU11__DIG_CLK_EN__WIDTH 1 +#define PMU_PMU11__DIG_CLK_EN__MASK 0x00000002U +#define PMU_PMU11__DIG_CLK_EN__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define PMU_PMU11__DIG_CLK_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PMU_PMU11__DIG_CLK_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PMU_PMU11__DIG_CLK_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PMU_PMU11__DIG_CLK_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PMU_PMU11__DIG_CLK_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PMU_PMU11__DIG_CLK_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field atb_en */ +/** + * @defgroup pmu_top_regs_core_atb_en_field atb_en_field + * @brief macros for field atb_en + * @details atb enable for pmu + * @{ + */ +#define PMU_PMU11__ATB_EN__SHIFT 2 +#define PMU_PMU11__ATB_EN__WIDTH 1 +#define PMU_PMU11__ATB_EN__MASK 0x00000004U +#define PMU_PMU11__ATB_EN__READ(src) (((uint32_t)(src) & 0x00000004U) >> 2) +#define PMU_PMU11__ATB_EN__WRITE(src) (((uint32_t)(src) << 2) & 0x00000004U) +#define PMU_PMU11__ATB_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PMU_PMU11__ATB_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PMU_PMU11__ATB_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PMU_PMU11__ATB_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PMU_PMU11__ATB_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field atb_select */ +/** + * @defgroup pmu_top_regs_core_atb_select_field atb_select_field + * @brief macros for field atb_select + * @details atb selects for pmu11010 VBG600mT11001 vrefnat600T11000 vrefnat900T10111 refladT210110 refladT110101 refladT010100 refladfastT110011 refladfastT010010 VrefdvddmemT10001 VrefdvddcpuT10000 VrefBGdvddT01111 vrefporpmuT01110 VrefvbattgoodT01101 vrefstogoodtoEnerST01100 DVDDmem01011 DVDDcpu01010 avddldoint01001 VrefTRdvddTVrefTRdvddT01000 VrectstagerepldivlowT00111 VrectstagerepldivhighT00110 vrefcanharvT00101 vrefmustharvT00100 porb_vddpmu_HT00011 Vreflpc000010 Vreflpc100001 refi_reconfT00000 vrefcalpmuadcT + * @{ + */ +#define PMU_PMU11__ATB_SELECT__SHIFT 3 +#define PMU_PMU11__ATB_SELECT__WIDTH 5 +#define PMU_PMU11__ATB_SELECT__MASK 0x000000f8U +#define PMU_PMU11__ATB_SELECT__READ(src) (((uint32_t)(src) & 0x000000f8U) >> 3) +#define PMU_PMU11__ATB_SELECT__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x000000f8U) +#define PMU_PMU11__ATB_SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f8U) | (((uint32_t)(src) <<\ + 3) & 0x000000f8U) +#define PMU_PMU11__ATB_SELECT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x000000f8U))) +#define PMU_PMU11__ATB_SELECT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field lpcomp_ref_fall */ +/** + * @defgroup pmu_top_regs_core_lpcomp_ref_fall_field lpcomp_ref_fall_field + * @brief macros for field lpcomp_ref_fall + * @details falling edge reference select for lpcomp hysteresis, should be set lower than lpcomp_ref_rise25*[65,61,57,53,49,45,41,37,33,29,25,21,17,13,9,5] for i=[15:0] + * @{ + */ +#define PMU_PMU11__LPCOMP_REF_FALL__SHIFT 8 +#define PMU_PMU11__LPCOMP_REF_FALL__WIDTH 4 +#define PMU_PMU11__LPCOMP_REF_FALL__MASK 0x00000f00U +#define PMU_PMU11__LPCOMP_REF_FALL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000f00U) >> 8) +#define PMU_PMU11__LPCOMP_REF_FALL__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000f00U) +#define PMU_PMU11__LPCOMP_REF_FALL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((uint32_t)(src) <<\ + 8) & 0x00000f00U) +#define PMU_PMU11__LPCOMP_REF_FALL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000f00U))) +#define PMU_PMU11__LPCOMP_REF_FALL__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field lpcomp_ref */ +/** + * @defgroup pmu_top_regs_core_lpcomp_ref_field lpcomp_ref_field + * @brief macros for field lpcomp_ref + * @details rising edge reference select for lpcomp25*[66,62,58,54,50,46,42,38,34,30,26,22,18,14,10,6] for i=[15:0] + * @{ + */ +#define PMU_PMU11__LPCOMP_REF__SHIFT 12 +#define PMU_PMU11__LPCOMP_REF__WIDTH 4 +#define PMU_PMU11__LPCOMP_REF__MASK 0x0000f000U +#define PMU_PMU11__LPCOMP_REF__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f000U) >> 12) +#define PMU_PMU11__LPCOMP_REF__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0000f000U) +#define PMU_PMU11__LPCOMP_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((uint32_t)(src) <<\ + 12) & 0x0000f000U) +#define PMU_PMU11__LPCOMP_REF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0000f000U))) +#define PMU_PMU11__LPCOMP_REF__RESET_VALUE 0x00000009U +/** @} */ + +/* macros for field lpcomp_atb_sel */ +/** + * @defgroup pmu_top_regs_core_lpcomp_atb_sel_field lpcomp_atb_sel_field + * @brief macros for field lpcomp_atb_sel + * @details atbselect for lpcomp + * @{ + */ +#define PMU_PMU11__LPCOMP_ATB_SEL__SHIFT 16 +#define PMU_PMU11__LPCOMP_ATB_SEL__WIDTH 1 +#define PMU_PMU11__LPCOMP_ATB_SEL__MASK 0x00010000U +#define PMU_PMU11__LPCOMP_ATB_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define PMU_PMU11__LPCOMP_ATB_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define PMU_PMU11__LPCOMP_ATB_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define PMU_PMU11__LPCOMP_ATB_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define PMU_PMU11__LPCOMP_ATB_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PMU_PMU11__LPCOMP_ATB_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PMU_PMU11__LPCOMP_ATB_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pmu_pin_mux_sel */ +/** + * @defgroup pmu_top_regs_core_pmu_pin_mux_sel_field pmu_pin_mux_sel_field + * @brief macros for field pmu_pin_mux_sel + * @details pin mux select from analog + * @{ + */ +#define PMU_PMU11__PMU_PIN_MUX_SEL__SHIFT 17 +#define PMU_PMU11__PMU_PIN_MUX_SEL__WIDTH 2 +#define PMU_PMU11__PMU_PIN_MUX_SEL__MASK 0x00060000U +#define PMU_PMU11__PMU_PIN_MUX_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00060000U) >> 17) +#define PMU_PMU11__PMU_PIN_MUX_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00060000U) +#define PMU_PMU11__PMU_PIN_MUX_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00060000U) | (((uint32_t)(src) <<\ + 17) & 0x00060000U) +#define PMU_PMU11__PMU_PIN_MUX_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00060000U))) +#define PMU_PMU11__PMU_PIN_MUX_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_ref_gadc */ +/** + * @defgroup pmu_top_regs_core_ctr_ref_gadc_field ctr_ref_gadc_field + * @brief macros for field ctr_ref_gadc + * @details reference for gadc25*(24+i)mV, i=0:3 + * @{ + */ +#define PMU_PMU11__CTR_REF_GADC__SHIFT 19 +#define PMU_PMU11__CTR_REF_GADC__WIDTH 2 +#define PMU_PMU11__CTR_REF_GADC__MASK 0x00180000U +#define PMU_PMU11__CTR_REF_GADC__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define PMU_PMU11__CTR_REF_GADC__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define PMU_PMU11__CTR_REF_GADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define PMU_PMU11__CTR_REF_GADC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define PMU_PMU11__CTR_REF_GADC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field gadc_cutvdd_b_ovr */ +/** + * @defgroup pmu_top_regs_core_gadc_cutvdd_b_ovr_field gadc_cutvdd_b_ovr_field + * @brief macros for field gadc_cutvdd_b_ovr + * @details override gadc_cutvdd_b + * @{ + */ +#define PMU_PMU11__GADC_CUTVDD_B_OVR__SHIFT 21 +#define PMU_PMU11__GADC_CUTVDD_B_OVR__WIDTH 1 +#define PMU_PMU11__GADC_CUTVDD_B_OVR__MASK 0x00200000U +#define PMU_PMU11__GADC_CUTVDD_B_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define PMU_PMU11__GADC_CUTVDD_B_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define PMU_PMU11__GADC_CUTVDD_B_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define PMU_PMU11__GADC_CUTVDD_B_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define PMU_PMU11__GADC_CUTVDD_B_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define PMU_PMU11__GADC_CUTVDD_B_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define PMU_PMU11__GADC_CUTVDD_B_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field gadc_cutvdd_b_ovr_val */ +/** + * @defgroup pmu_top_regs_core_gadc_cutvdd_b_ovr_val_field gadc_cutvdd_b_ovr_val_field + * @brief macros for field gadc_cutvdd_b_ovr_val + * @details override gadc_cutvdd_b val: Turn ON the gadc hsw + * @{ + */ +#define PMU_PMU11__GADC_CUTVDD_B_OVR_VAL__SHIFT 22 +#define PMU_PMU11__GADC_CUTVDD_B_OVR_VAL__WIDTH 1 +#define PMU_PMU11__GADC_CUTVDD_B_OVR_VAL__MASK 0x00400000U +#define PMU_PMU11__GADC_CUTVDD_B_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define PMU_PMU11__GADC_CUTVDD_B_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define PMU_PMU11__GADC_CUTVDD_B_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define PMU_PMU11__GADC_CUTVDD_B_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define PMU_PMU11__GADC_CUTVDD_B_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define PMU_PMU11__GADC_CUTVDD_B_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define PMU_PMU11__GADC_CUTVDD_B_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_disable_xtal32K_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_disable_xtal32K_ovr_val_field otp_disable_xtal32K_ovr_val_field + * @brief macros for field otp_disable_xtal32K_ovr_val + * @details override for xtal32K + * @{ + */ +#define PMU_PMU11__OTP_DISABLE_XTAL32K_OVR_VAL__SHIFT 23 +#define PMU_PMU11__OTP_DISABLE_XTAL32K_OVR_VAL__WIDTH 1 +#define PMU_PMU11__OTP_DISABLE_XTAL32K_OVR_VAL__MASK 0x00800000U +#define PMU_PMU11__OTP_DISABLE_XTAL32K_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PMU_PMU11__OTP_DISABLE_XTAL32K_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define PMU_PMU11__OTP_DISABLE_XTAL32K_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define PMU_PMU11__OTP_DISABLE_XTAL32K_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define PMU_PMU11__OTP_DISABLE_XTAL32K_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PMU_PMU11__OTP_DISABLE_XTAL32K_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PMU_PMU11__OTP_DISABLE_XTAL32K_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_spare_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_spare_ovr_val_field otp_spare_ovr_val_field + * @brief macros for field otp_spare_ovr_val + * @details new for paris + * @{ + */ +#define PMU_PMU11__OTP_SPARE_OVR_VAL__SHIFT 24 +#define PMU_PMU11__OTP_SPARE_OVR_VAL__WIDTH 1 +#define PMU_PMU11__OTP_SPARE_OVR_VAL__MASK 0x01000000U +#define PMU_PMU11__OTP_SPARE_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define PMU_PMU11__OTP_SPARE_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define PMU_PMU11__OTP_SPARE_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define PMU_PMU11__OTP_SPARE_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define PMU_PMU11__OTP_SPARE_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define PMU_PMU11__OTP_SPARE_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define PMU_PMU11__OTP_SPARE_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_ldo_ovr */ +/** + * @defgroup pmu_top_regs_core_otp_ldo_ovr_field otp_ldo_ovr_field + * @brief macros for field otp_ldo_ovr + * @details override otp_use_ldo + * @{ + */ +#define PMU_PMU11__OTP_LDO_OVR__SHIFT 25 +#define PMU_PMU11__OTP_LDO_OVR__WIDTH 1 +#define PMU_PMU11__OTP_LDO_OVR__MASK 0x02000000U +#define PMU_PMU11__OTP_LDO_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define PMU_PMU11__OTP_LDO_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define PMU_PMU11__OTP_LDO_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define PMU_PMU11__OTP_LDO_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define PMU_PMU11__OTP_LDO_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define PMU_PMU11__OTP_LDO_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define PMU_PMU11__OTP_LDO_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_brownout_ovr */ +/** + * @defgroup pmu_top_regs_core_otp_brownout_ovr_field otp_brownout_ovr_field + * @brief macros for field otp_brownout_ovr + * @details override otp_vbatt_brownout + * @{ + */ +#define PMU_PMU11__OTP_BROWNOUT_OVR__SHIFT 26 +#define PMU_PMU11__OTP_BROWNOUT_OVR__WIDTH 1 +#define PMU_PMU11__OTP_BROWNOUT_OVR__MASK 0x04000000U +#define PMU_PMU11__OTP_BROWNOUT_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define PMU_PMU11__OTP_BROWNOUT_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define PMU_PMU11__OTP_BROWNOUT_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define PMU_PMU11__OTP_BROWNOUT_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define PMU_PMU11__OTP_BROWNOUT_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define PMU_PMU11__OTP_BROWNOUT_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define PMU_PMU11__OTP_BROWNOUT_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_vddio_ovr */ +/** + * @defgroup pmu_top_regs_core_otp_vddio_ovr_field otp_vddio_ovr_field + * @brief macros for field otp_vddio_ovr + * @details override otp_vddio_range + * @{ + */ +#define PMU_PMU11__OTP_VDDIO_OVR__SHIFT 27 +#define PMU_PMU11__OTP_VDDIO_OVR__WIDTH 1 +#define PMU_PMU11__OTP_VDDIO_OVR__MASK 0x08000000U +#define PMU_PMU11__OTP_VDDIO_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define PMU_PMU11__OTP_VDDIO_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define PMU_PMU11__OTP_VDDIO_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define PMU_PMU11__OTP_VDDIO_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define PMU_PMU11__OTP_VDDIO_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define PMU_PMU11__OTP_VDDIO_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define PMU_PMU11__OTP_VDDIO_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_mem_hsw_b_late_ovr */ +/** + * @defgroup pmu_top_regs_core_en_mem_hsw_b_late_ovr_field en_mem_hsw_b_late_ovr_field + * @brief macros for field en_mem_hsw_b_late_ovr + * @details override for en_mem_hsw_b_late + * @{ + */ +#define PMU_PMU11__EN_MEM_HSW_B_LATE_OVR__SHIFT 28 +#define PMU_PMU11__EN_MEM_HSW_B_LATE_OVR__WIDTH 1 +#define PMU_PMU11__EN_MEM_HSW_B_LATE_OVR__MASK 0x10000000U +#define PMU_PMU11__EN_MEM_HSW_B_LATE_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define PMU_PMU11__EN_MEM_HSW_B_LATE_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define PMU_PMU11__EN_MEM_HSW_B_LATE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define PMU_PMU11__EN_MEM_HSW_B_LATE_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define PMU_PMU11__EN_MEM_HSW_B_LATE_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define PMU_PMU11__EN_MEM_HSW_B_LATE_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define PMU_PMU11__EN_MEM_HSW_B_LATE_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_mem_hsw_b_late_ovr_val */ +/** + * @defgroup pmu_top_regs_core_en_mem_hsw_b_late_ovr_val_field en_mem_hsw_b_late_ovr_val_field + * @brief macros for field en_mem_hsw_b_late_ovr_val + * @details override for en_mem_hsw_b_late val: Turn OFF memory late hsw + * @{ + */ +#define PMU_PMU11__EN_MEM_HSW_B_LATE_OVR_VAL__SHIFT 29 +#define PMU_PMU11__EN_MEM_HSW_B_LATE_OVR_VAL__WIDTH 1 +#define PMU_PMU11__EN_MEM_HSW_B_LATE_OVR_VAL__MASK 0x20000000U +#define PMU_PMU11__EN_MEM_HSW_B_LATE_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define PMU_PMU11__EN_MEM_HSW_B_LATE_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define PMU_PMU11__EN_MEM_HSW_B_LATE_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define PMU_PMU11__EN_MEM_HSW_B_LATE_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define PMU_PMU11__EN_MEM_HSW_B_LATE_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define PMU_PMU11__EN_MEM_HSW_B_LATE_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define PMU_PMU11__EN_MEM_HSW_B_LATE_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_sw_hsw_b_late_ovr */ +/** + * @defgroup pmu_top_regs_core_en_sw_hsw_b_late_ovr_field en_sw_hsw_b_late_ovr_field + * @brief macros for field en_sw_hsw_b_late_ovr + * @details override en_sw_hsw_b_late + * @{ + */ +#define PMU_PMU11__EN_SW_HSW_B_LATE_OVR__SHIFT 30 +#define PMU_PMU11__EN_SW_HSW_B_LATE_OVR__WIDTH 1 +#define PMU_PMU11__EN_SW_HSW_B_LATE_OVR__MASK 0x40000000U +#define PMU_PMU11__EN_SW_HSW_B_LATE_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define PMU_PMU11__EN_SW_HSW_B_LATE_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define PMU_PMU11__EN_SW_HSW_B_LATE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define PMU_PMU11__EN_SW_HSW_B_LATE_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define PMU_PMU11__EN_SW_HSW_B_LATE_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define PMU_PMU11__EN_SW_HSW_B_LATE_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define PMU_PMU11__EN_SW_HSW_B_LATE_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_sw_hsw_b_late_ovr_val */ +/** + * @defgroup pmu_top_regs_core_en_sw_hsw_b_late_ovr_val_field en_sw_hsw_b_late_ovr_val_field + * @brief macros for field en_sw_hsw_b_late_ovr_val + * @details override en_sw_hsw_b_late val: Turn OFF switcher late hsw + * @{ + */ +#define PMU_PMU11__EN_SW_HSW_B_LATE_OVR_VAL__SHIFT 31 +#define PMU_PMU11__EN_SW_HSW_B_LATE_OVR_VAL__WIDTH 1 +#define PMU_PMU11__EN_SW_HSW_B_LATE_OVR_VAL__MASK 0x80000000U +#define PMU_PMU11__EN_SW_HSW_B_LATE_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define PMU_PMU11__EN_SW_HSW_B_LATE_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define PMU_PMU11__EN_SW_HSW_B_LATE_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define PMU_PMU11__EN_SW_HSW_B_LATE_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define PMU_PMU11__EN_SW_HSW_B_LATE_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PMU_PMU11__EN_SW_HSW_B_LATE_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PMU_PMU11__EN_SW_HSW_B_LATE_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU11__TYPE uint32_t +#define PMU_PMU11__READ 0xffffffffU +#define PMU_PMU11__WRITE 0xffffffffU +#define PMU_PMU11__PRESERVED 0x00000000U +#define PMU_PMU11__RESET_VALUE 0x00009802U + +#endif /* __PMU_PMU11_MACRO__ */ + +/** @} end of pmu11 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu12 */ +/** + * @defgroup pmu_top_regs_core_pmu12 pmu12 + * @brief test registers and overrides definitions. + * @{ + */ +#ifndef __PMU_PMU12_MACRO__ +#define __PMU_PMU12_MACRO__ + +/* macros for field otp_ovr */ +/** + * @defgroup pmu_top_regs_core_otp_ovr_field otp_ovr_field + * @brief macros for field otp_ovr + * @details 1: overriding otp values for test + * @{ + */ +#define PMU_PMU12__OTP_OVR__SHIFT 0 +#define PMU_PMU12__OTP_OVR__WIDTH 1 +#define PMU_PMU12__OTP_OVR__MASK 0x00000001U +#define PMU_PMU12__OTP_OVR__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PMU_PMU12__OTP_OVR__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PMU_PMU12__OTP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PMU_PMU12__OTP_OVR__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define PMU_PMU12__OTP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PMU_PMU12__OTP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PMU_PMU12__OTP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_batt_type_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_batt_type_ovr_val_field otp_batt_type_ovr_val_field + * @brief macros for field otp_batt_type_ovr_val + * @details 0: LiIon, 1: rechargeable, 2: no batt, 3: non-rechargable + * @{ + */ +#define PMU_PMU12__OTP_BATT_TYPE_OVR_VAL__SHIFT 1 +#define PMU_PMU12__OTP_BATT_TYPE_OVR_VAL__WIDTH 2 +#define PMU_PMU12__OTP_BATT_TYPE_OVR_VAL__MASK 0x00000006U +#define PMU_PMU12__OTP_BATT_TYPE_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000006U) >> 1) +#define PMU_PMU12__OTP_BATT_TYPE_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000006U) +#define PMU_PMU12__OTP_BATT_TYPE_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000006U) | (((uint32_t)(src) <<\ + 1) & 0x00000006U) +#define PMU_PMU12__OTP_BATT_TYPE_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000006U))) +#define PMU_PMU12__OTP_BATT_TYPE_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_mppt_type_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_mppt_type_ovr_val_field otp_mppt_type_ovr_val_field + * @brief macros for field otp_mppt_type_ovr_val + * @details 0: digital mppt1: RF only+analog MPPT2: voltage regulation (all mppt disabled) + * @{ + */ +#define PMU_PMU12__OTP_MPPT_TYPE_OVR_VAL__SHIFT 3 +#define PMU_PMU12__OTP_MPPT_TYPE_OVR_VAL__WIDTH 2 +#define PMU_PMU12__OTP_MPPT_TYPE_OVR_VAL__MASK 0x00000018U +#define PMU_PMU12__OTP_MPPT_TYPE_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000018U) >> 3) +#define PMU_PMU12__OTP_MPPT_TYPE_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000018U) +#define PMU_PMU12__OTP_MPPT_TYPE_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000018U) | (((uint32_t)(src) <<\ + 3) & 0x00000018U) +#define PMU_PMU12__OTP_MPPT_TYPE_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000018U))) +#define PMU_PMU12__OTP_MPPT_TYPE_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_disable_vddIO_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_disable_vddIO_ovr_val_field otp_disable_vddIO_ovr_val_field + * @brief macros for field otp_disable_vddIO_ovr_val + * @details 1: need to provide vddIO externally + * @{ + */ +#define PMU_PMU12__OTP_DISABLE_VDDIO_OVR_VAL__SHIFT 5 +#define PMU_PMU12__OTP_DISABLE_VDDIO_OVR_VAL__WIDTH 1 +#define PMU_PMU12__OTP_DISABLE_VDDIO_OVR_VAL__MASK 0x00000020U +#define PMU_PMU12__OTP_DISABLE_VDDIO_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PMU_PMU12__OTP_DISABLE_VDDIO_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define PMU_PMU12__OTP_DISABLE_VDDIO_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define PMU_PMU12__OTP_DISABLE_VDDIO_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define PMU_PMU12__OTP_DISABLE_VDDIO_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PMU_PMU12__OTP_DISABLE_VDDIO_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PMU_PMU12__OTP_DISABLE_VDDIO_OVR_VAL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field otp_disable_vdd_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_disable_vdd_ovr_val_field otp_disable_vdd_ovr_val_field + * @brief macros for field otp_disable_vdd_ovr_val + * @details 1: need to provide vdd externally + * @{ + */ +#define PMU_PMU12__OTP_DISABLE_VDD_OVR_VAL__SHIFT 6 +#define PMU_PMU12__OTP_DISABLE_VDD_OVR_VAL__WIDTH 1 +#define PMU_PMU12__OTP_DISABLE_VDD_OVR_VAL__MASK 0x00000040U +#define PMU_PMU12__OTP_DISABLE_VDD_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define PMU_PMU12__OTP_DISABLE_VDD_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define PMU_PMU12__OTP_DISABLE_VDD_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PMU_PMU12__OTP_DISABLE_VDD_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PMU_PMU12__OTP_DISABLE_VDD_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PMU_PMU12__OTP_DISABLE_VDD_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PMU_PMU12__OTP_DISABLE_VDD_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_nabg_trim_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_nabg_trim_ovr_val_field otp_nabg_trim_ovr_val_field + * @brief macros for field otp_nabg_trim_ovr_val + * @details trimming bits for native bandgap + * @{ + */ +#define PMU_PMU12__OTP_NABG_TRIM_OVR_VAL__SHIFT 7 +#define PMU_PMU12__OTP_NABG_TRIM_OVR_VAL__WIDTH 9 +#define PMU_PMU12__OTP_NABG_TRIM_OVR_VAL__MASK 0x0000ff80U +#define PMU_PMU12__OTP_NABG_TRIM_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff80U) >> 7) +#define PMU_PMU12__OTP_NABG_TRIM_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x0000ff80U) +#define PMU_PMU12__OTP_NABG_TRIM_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff80U) | (((uint32_t)(src) <<\ + 7) & 0x0000ff80U) +#define PMU_PMU12__OTP_NABG_TRIM_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x0000ff80U))) +#define PMU_PMU12__OTP_NABG_TRIM_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field unused */ +/** + * @defgroup pmu_top_regs_core_unused_field unused_field + * @brief macros for field unused + * @details unused spare, pmu_spares[7] + * @{ + */ +#define PMU_PMU12__UNUSED__SHIFT 16 +#define PMU_PMU12__UNUSED__WIDTH 1 +#define PMU_PMU12__UNUSED__MASK 0x00010000U +#define PMU_PMU12__UNUSED__READ(src) (((uint32_t)(src) & 0x00010000U) >> 16) +#define PMU_PMU12__UNUSED__WRITE(src) (((uint32_t)(src) << 16) & 0x00010000U) +#define PMU_PMU12__UNUSED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define PMU_PMU12__UNUSED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define PMU_PMU12__UNUSED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PMU_PMU12__UNUSED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PMU_PMU12__UNUSED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bypassLiion_ovr */ +/** + * @defgroup pmu_top_regs_core_bypassLiion_ovr_field bypassLiion_ovr_field + * @brief macros for field bypassLiion_ovr + * @details override bypassLiion + * @{ + */ +#define PMU_PMU12__BYPASSLIION_OVR__SHIFT 17 +#define PMU_PMU12__BYPASSLIION_OVR__WIDTH 1 +#define PMU_PMU12__BYPASSLIION_OVR__MASK 0x00020000U +#define PMU_PMU12__BYPASSLIION_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define PMU_PMU12__BYPASSLIION_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define PMU_PMU12__BYPASSLIION_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define PMU_PMU12__BYPASSLIION_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define PMU_PMU12__BYPASSLIION_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define PMU_PMU12__BYPASSLIION_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define PMU_PMU12__BYPASSLIION_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bypassLiion_ovr_val */ +/** + * @defgroup pmu_top_regs_core_bypassLiion_ovr_val_field bypassLiion_ovr_val_field + * @brief macros for field bypassLiion_ovr_val + * @details override bypassLiion val: 1 to bypass VBATLI to VBATT + * @{ + */ +#define PMU_PMU12__BYPASSLIION_OVR_VAL__SHIFT 18 +#define PMU_PMU12__BYPASSLIION_OVR_VAL__WIDTH 1 +#define PMU_PMU12__BYPASSLIION_OVR_VAL__MASK 0x00040000U +#define PMU_PMU12__BYPASSLIION_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define PMU_PMU12__BYPASSLIION_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define PMU_PMU12__BYPASSLIION_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define PMU_PMU12__BYPASSLIION_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define PMU_PMU12__BYPASSLIION_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define PMU_PMU12__BYPASSLIION_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define PMU_PMU12__BYPASSLIION_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field disable_sw_timer */ +/** + * @defgroup pmu_top_regs_core_disable_sw_timer_field disable_sw_timer_field + * @brief macros for field disable_sw_timer + * @details disable sw timer and enable soc headswitch when sw is enabled + * @{ + */ +#define PMU_PMU12__DISABLE_SW_TIMER__SHIFT 19 +#define PMU_PMU12__DISABLE_SW_TIMER__WIDTH 1 +#define PMU_PMU12__DISABLE_SW_TIMER__MASK 0x00080000U +#define PMU_PMU12__DISABLE_SW_TIMER__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define PMU_PMU12__DISABLE_SW_TIMER__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define PMU_PMU12__DISABLE_SW_TIMER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define PMU_PMU12__DISABLE_SW_TIMER__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define PMU_PMU12__DISABLE_SW_TIMER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define PMU_PMU12__DISABLE_SW_TIMER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define PMU_PMU12__DISABLE_SW_TIMER__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_mem_hsw_b_ovr */ +/** + * @defgroup pmu_top_regs_core_en_mem_hsw_b_ovr_field en_mem_hsw_b_ovr_field + * @brief macros for field en_mem_hsw_b_ovr + * @details override en_mem_hsw_b + * @{ + */ +#define PMU_PMU12__EN_MEM_HSW_B_OVR__SHIFT 20 +#define PMU_PMU12__EN_MEM_HSW_B_OVR__WIDTH 1 +#define PMU_PMU12__EN_MEM_HSW_B_OVR__MASK 0x00100000U +#define PMU_PMU12__EN_MEM_HSW_B_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define PMU_PMU12__EN_MEM_HSW_B_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define PMU_PMU12__EN_MEM_HSW_B_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define PMU_PMU12__EN_MEM_HSW_B_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define PMU_PMU12__EN_MEM_HSW_B_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define PMU_PMU12__EN_MEM_HSW_B_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define PMU_PMU12__EN_MEM_HSW_B_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_mem_hsw_b_ovr_val */ +/** + * @defgroup pmu_top_regs_core_en_mem_hsw_b_ovr_val_field en_mem_hsw_b_ovr_val_field + * @brief macros for field en_mem_hsw_b_ovr_val + * @details override en_mem_hsw_b val: Turn OFF mem hsw + * @{ + */ +#define PMU_PMU12__EN_MEM_HSW_B_OVR_VAL__SHIFT 21 +#define PMU_PMU12__EN_MEM_HSW_B_OVR_VAL__WIDTH 1 +#define PMU_PMU12__EN_MEM_HSW_B_OVR_VAL__MASK 0x00200000U +#define PMU_PMU12__EN_MEM_HSW_B_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define PMU_PMU12__EN_MEM_HSW_B_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define PMU_PMU12__EN_MEM_HSW_B_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define PMU_PMU12__EN_MEM_HSW_B_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define PMU_PMU12__EN_MEM_HSW_B_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define PMU_PMU12__EN_MEM_HSW_B_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define PMU_PMU12__EN_MEM_HSW_B_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_sw_hsw_b_ovr */ +/** + * @defgroup pmu_top_regs_core_en_sw_hsw_b_ovr_field en_sw_hsw_b_ovr_field + * @brief macros for field en_sw_hsw_b_ovr + * @details enable switcher headswitch override + * @{ + */ +#define PMU_PMU12__EN_SW_HSW_B_OVR__SHIFT 22 +#define PMU_PMU12__EN_SW_HSW_B_OVR__WIDTH 1 +#define PMU_PMU12__EN_SW_HSW_B_OVR__MASK 0x00400000U +#define PMU_PMU12__EN_SW_HSW_B_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define PMU_PMU12__EN_SW_HSW_B_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define PMU_PMU12__EN_SW_HSW_B_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define PMU_PMU12__EN_SW_HSW_B_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define PMU_PMU12__EN_SW_HSW_B_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define PMU_PMU12__EN_SW_HSW_B_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define PMU_PMU12__EN_SW_HSW_B_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_sw_hsw_b_ovr_val */ +/** + * @defgroup pmu_top_regs_core_en_sw_hsw_b_ovr_val_field en_sw_hsw_b_ovr_val_field + * @brief macros for field en_sw_hsw_b_ovr_val + * @details override val for switcher head switch + * @{ + */ +#define PMU_PMU12__EN_SW_HSW_B_OVR_VAL__SHIFT 23 +#define PMU_PMU12__EN_SW_HSW_B_OVR_VAL__WIDTH 1 +#define PMU_PMU12__EN_SW_HSW_B_OVR_VAL__MASK 0x00800000U +#define PMU_PMU12__EN_SW_HSW_B_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PMU_PMU12__EN_SW_HSW_B_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define PMU_PMU12__EN_SW_HSW_B_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define PMU_PMU12__EN_SW_HSW_B_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define PMU_PMU12__EN_SW_HSW_B_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PMU_PMU12__EN_SW_HSW_B_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PMU_PMU12__EN_SW_HSW_B_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sw_rstb_ovr */ +/** + * @defgroup pmu_top_regs_core_sw_rstb_ovr_field sw_rstb_ovr_field + * @brief macros for field sw_rstb_ovr + * @details enable override for switcher rstb + * @{ + */ +#define PMU_PMU12__SW_RSTB_OVR__SHIFT 24 +#define PMU_PMU12__SW_RSTB_OVR__WIDTH 1 +#define PMU_PMU12__SW_RSTB_OVR__MASK 0x01000000U +#define PMU_PMU12__SW_RSTB_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define PMU_PMU12__SW_RSTB_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define PMU_PMU12__SW_RSTB_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define PMU_PMU12__SW_RSTB_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define PMU_PMU12__SW_RSTB_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define PMU_PMU12__SW_RSTB_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define PMU_PMU12__SW_RSTB_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sw_rstb_ovr_val */ +/** + * @defgroup pmu_top_regs_core_sw_rstb_ovr_val_field sw_rstb_ovr_val_field + * @brief macros for field sw_rstb_ovr_val + * @details override val for switcher rstb + * @{ + */ +#define PMU_PMU12__SW_RSTB_OVR_VAL__SHIFT 25 +#define PMU_PMU12__SW_RSTB_OVR_VAL__WIDTH 1 +#define PMU_PMU12__SW_RSTB_OVR_VAL__MASK 0x02000000U +#define PMU_PMU12__SW_RSTB_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define PMU_PMU12__SW_RSTB_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define PMU_PMU12__SW_RSTB_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define PMU_PMU12__SW_RSTB_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define PMU_PMU12__SW_RSTB_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define PMU_PMU12__SW_RSTB_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define PMU_PMU12__SW_RSTB_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_soc_hsw_b_ovr */ +/** + * @defgroup pmu_top_regs_core_en_soc_hsw_b_ovr_field en_soc_hsw_b_ovr_field + * @brief macros for field en_soc_hsw_b_ovr + * @details enable soc headswitch override + * @{ + */ +#define PMU_PMU12__EN_SOC_HSW_B_OVR__SHIFT 26 +#define PMU_PMU12__EN_SOC_HSW_B_OVR__WIDTH 1 +#define PMU_PMU12__EN_SOC_HSW_B_OVR__MASK 0x04000000U +#define PMU_PMU12__EN_SOC_HSW_B_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define PMU_PMU12__EN_SOC_HSW_B_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define PMU_PMU12__EN_SOC_HSW_B_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define PMU_PMU12__EN_SOC_HSW_B_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define PMU_PMU12__EN_SOC_HSW_B_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define PMU_PMU12__EN_SOC_HSW_B_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define PMU_PMU12__EN_SOC_HSW_B_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_soc_hsw_b_ovr_val */ +/** + * @defgroup pmu_top_regs_core_en_soc_hsw_b_ovr_val_field en_soc_hsw_b_ovr_val_field + * @brief macros for field en_soc_hsw_b_ovr_val + * @details override_val for soc headswitch + * @{ + */ +#define PMU_PMU12__EN_SOC_HSW_B_OVR_VAL__SHIFT 27 +#define PMU_PMU12__EN_SOC_HSW_B_OVR_VAL__WIDTH 1 +#define PMU_PMU12__EN_SOC_HSW_B_OVR_VAL__MASK 0x08000000U +#define PMU_PMU12__EN_SOC_HSW_B_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define PMU_PMU12__EN_SOC_HSW_B_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define PMU_PMU12__EN_SOC_HSW_B_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define PMU_PMU12__EN_SOC_HSW_B_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define PMU_PMU12__EN_SOC_HSW_B_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define PMU_PMU12__EN_SOC_HSW_B_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define PMU_PMU12__EN_SOC_HSW_B_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sel_avdd1_ovr */ +/** + * @defgroup pmu_top_regs_core_sel_avdd1_ovr_field sel_avdd1_ovr_field + * @brief macros for field sel_avdd1_ovr + * @details enable override for pmu avdd/dvdd switch + * @{ + */ +#define PMU_PMU12__SEL_AVDD1_OVR__SHIFT 28 +#define PMU_PMU12__SEL_AVDD1_OVR__WIDTH 1 +#define PMU_PMU12__SEL_AVDD1_OVR__MASK 0x10000000U +#define PMU_PMU12__SEL_AVDD1_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define PMU_PMU12__SEL_AVDD1_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define PMU_PMU12__SEL_AVDD1_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define PMU_PMU12__SEL_AVDD1_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define PMU_PMU12__SEL_AVDD1_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define PMU_PMU12__SEL_AVDD1_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define PMU_PMU12__SEL_AVDD1_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sel_avdd1_ovr_val */ +/** + * @defgroup pmu_top_regs_core_sel_avdd1_ovr_val_field sel_avdd1_ovr_val_field + * @brief macros for field sel_avdd1_ovr_val + * @details override_val for pmu avdd/dvdd switch + * @{ + */ +#define PMU_PMU12__SEL_AVDD1_OVR_VAL__SHIFT 29 +#define PMU_PMU12__SEL_AVDD1_OVR_VAL__WIDTH 1 +#define PMU_PMU12__SEL_AVDD1_OVR_VAL__MASK 0x20000000U +#define PMU_PMU12__SEL_AVDD1_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define PMU_PMU12__SEL_AVDD1_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define PMU_PMU12__SEL_AVDD1_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define PMU_PMU12__SEL_AVDD1_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define PMU_PMU12__SEL_AVDD1_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define PMU_PMU12__SEL_AVDD1_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define PMU_PMU12__SEL_AVDD1_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field swRes_encomp_ovr */ +/** + * @defgroup pmu_top_regs_core_swRes_encomp_ovr_field swRes_encomp_ovr_field + * @brief macros for field swRes_encomp_ovr + * @details override swRes_encomp + * @{ + */ +#define PMU_PMU12__SWRES_ENCOMP_OVR__SHIFT 30 +#define PMU_PMU12__SWRES_ENCOMP_OVR__WIDTH 1 +#define PMU_PMU12__SWRES_ENCOMP_OVR__MASK 0x40000000U +#define PMU_PMU12__SWRES_ENCOMP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define PMU_PMU12__SWRES_ENCOMP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define PMU_PMU12__SWRES_ENCOMP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define PMU_PMU12__SWRES_ENCOMP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define PMU_PMU12__SWRES_ENCOMP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define PMU_PMU12__SWRES_ENCOMP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define PMU_PMU12__SWRES_ENCOMP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field swRes_encomp_ovr_val */ +/** + * @defgroup pmu_top_regs_core_swRes_encomp_ovr_val_field swRes_encomp_ovr_val_field + * @brief macros for field swRes_encomp_ovr_val + * @details override swRes_encomp val: Enable dvdd swRes + * @{ + */ +#define PMU_PMU12__SWRES_ENCOMP_OVR_VAL__SHIFT 31 +#define PMU_PMU12__SWRES_ENCOMP_OVR_VAL__WIDTH 1 +#define PMU_PMU12__SWRES_ENCOMP_OVR_VAL__MASK 0x80000000U +#define PMU_PMU12__SWRES_ENCOMP_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define PMU_PMU12__SWRES_ENCOMP_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define PMU_PMU12__SWRES_ENCOMP_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define PMU_PMU12__SWRES_ENCOMP_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define PMU_PMU12__SWRES_ENCOMP_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PMU_PMU12__SWRES_ENCOMP_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PMU_PMU12__SWRES_ENCOMP_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU12__TYPE uint32_t +#define PMU_PMU12__READ 0xffffffffU +#define PMU_PMU12__WRITE 0xffffffffU +#define PMU_PMU12__PRESERVED 0x00000000U +#define PMU_PMU12__RESET_VALUE 0x00000020U + +#endif /* __PMU_PMU12_MACRO__ */ + +/** @} end of pmu12 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu12a */ +/** + * @defgroup pmu_top_regs_core_pmu12a pmu12a + * @brief more test registers and overrides definitions. + * @{ + */ +#ifndef __PMU_PMU12A_MACRO__ +#define __PMU_PMU12A_MACRO__ + +/* macros for field otp_int_ovr */ +/** + * @defgroup pmu_top_regs_core_otp_int_ovr_field otp_int_ovr_field + * @brief macros for field otp_int_ovr + * @details enables override for native, charge pump, rect_ctune otp bits + * @{ + */ +#define PMU_PMU12A__OTP_INT_OVR__SHIFT 0 +#define PMU_PMU12A__OTP_INT_OVR__WIDTH 1 +#define PMU_PMU12A__OTP_INT_OVR__MASK 0x00000001U +#define PMU_PMU12A__OTP_INT_OVR__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PMU_PMU12A__OTP_INT_OVR__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PMU_PMU12A__OTP_INT_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PMU_PMU12A__OTP_INT_OVR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PMU_PMU12A__OTP_INT_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PMU_PMU12A__OTP_INT_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PMU_PMU12A__OTP_INT_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_use_ldo_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_use_ldo_ovr_val_field otp_use_ldo_ovr_val_field + * @brief macros for field otp_use_ldo_ovr_val + * @details override val for otp_use_ldo + * @{ + */ +#define PMU_PMU12A__OTP_USE_LDO_OVR_VAL__SHIFT 1 +#define PMU_PMU12A__OTP_USE_LDO_OVR_VAL__WIDTH 1 +#define PMU_PMU12A__OTP_USE_LDO_OVR_VAL__MASK 0x00000002U +#define PMU_PMU12A__OTP_USE_LDO_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PMU_PMU12A__OTP_USE_LDO_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PMU_PMU12A__OTP_USE_LDO_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PMU_PMU12A__OTP_USE_LDO_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PMU_PMU12A__OTP_USE_LDO_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PMU_PMU12A__OTP_USE_LDO_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PMU_PMU12A__OTP_USE_LDO_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_disable_chpu_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_disable_chpu_ovr_val_field otp_disable_chpu_ovr_val_field + * @brief macros for field otp_disable_chpu_ovr_val + * @details override val for otp_disable_chpu + * @{ + */ +#define PMU_PMU12A__OTP_DISABLE_CHPU_OVR_VAL__SHIFT 2 +#define PMU_PMU12A__OTP_DISABLE_CHPU_OVR_VAL__WIDTH 1 +#define PMU_PMU12A__OTP_DISABLE_CHPU_OVR_VAL__MASK 0x00000004U +#define PMU_PMU12A__OTP_DISABLE_CHPU_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PMU_PMU12A__OTP_DISABLE_CHPU_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PMU_PMU12A__OTP_DISABLE_CHPU_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PMU_PMU12A__OTP_DISABLE_CHPU_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PMU_PMU12A__OTP_DISABLE_CHPU_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PMU_PMU12A__OTP_DISABLE_CHPU_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PMU_PMU12A__OTP_DISABLE_CHPU_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_rect_ctune_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_rect_ctune_ovr_val_field otp_rect_ctune_ovr_val_field + * @brief macros for field otp_rect_ctune_ovr_val + * @details override val for otp_rect_ctune + * @{ + */ +#define PMU_PMU12A__OTP_RECT_CTUNE_OVR_VAL__SHIFT 3 +#define PMU_PMU12A__OTP_RECT_CTUNE_OVR_VAL__WIDTH 3 +#define PMU_PMU12A__OTP_RECT_CTUNE_OVR_VAL__MASK 0x00000038U +#define PMU_PMU12A__OTP_RECT_CTUNE_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define PMU_PMU12A__OTP_RECT_CTUNE_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define PMU_PMU12A__OTP_RECT_CTUNE_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define PMU_PMU12A__OTP_RECT_CTUNE_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define PMU_PMU12A__OTP_RECT_CTUNE_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_internal_spare_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_internal_spare_ovr_val_field otp_internal_spare_ovr_val_field + * @brief macros for field otp_internal_spare_ovr_val + * @details override val for otp_internal_spare + * @{ + */ +#define PMU_PMU12A__OTP_INTERNAL_SPARE_OVR_VAL__SHIFT 6 +#define PMU_PMU12A__OTP_INTERNAL_SPARE_OVR_VAL__WIDTH 4 +#define PMU_PMU12A__OTP_INTERNAL_SPARE_OVR_VAL__MASK 0x000003c0U +#define PMU_PMU12A__OTP_INTERNAL_SPARE_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x000003c0U) >> 6) +#define PMU_PMU12A__OTP_INTERNAL_SPARE_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000003c0U) +#define PMU_PMU12A__OTP_INTERNAL_SPARE_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003c0U) | (((uint32_t)(src) <<\ + 6) & 0x000003c0U) +#define PMU_PMU12A__OTP_INTERNAL_SPARE_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000003c0U))) +#define PMU_PMU12A__OTP_INTERNAL_SPARE_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_noind_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_noind_ovr_val_field otp_noind_ovr_val_field + * @brief macros for field otp_noind_ovr_val + * @details override val for otp_noind + * @{ + */ +#define PMU_PMU12A__OTP_NOIND_OVR_VAL__SHIFT 10 +#define PMU_PMU12A__OTP_NOIND_OVR_VAL__WIDTH 1 +#define PMU_PMU12A__OTP_NOIND_OVR_VAL__MASK 0x00000400U +#define PMU_PMU12A__OTP_NOIND_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define PMU_PMU12A__OTP_NOIND_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define PMU_PMU12A__OTP_NOIND_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define PMU_PMU12A__OTP_NOIND_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define PMU_PMU12A__OTP_NOIND_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define PMU_PMU12A__OTP_NOIND_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define PMU_PMU12A__OTP_NOIND_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_disable_5v_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_disable_5v_ovr_val_field otp_disable_5v_ovr_val_field + * @brief macros for field otp_disable_5v_ovr_val + * @details override val for otp_disable_5v + * @{ + */ +#define PMU_PMU12A__OTP_DISABLE_5V_OVR_VAL__SHIFT 11 +#define PMU_PMU12A__OTP_DISABLE_5V_OVR_VAL__WIDTH 1 +#define PMU_PMU12A__OTP_DISABLE_5V_OVR_VAL__MASK 0x00000800U +#define PMU_PMU12A__OTP_DISABLE_5V_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define PMU_PMU12A__OTP_DISABLE_5V_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define PMU_PMU12A__OTP_DISABLE_5V_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define PMU_PMU12A__OTP_DISABLE_5V_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define PMU_PMU12A__OTP_DISABLE_5V_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define PMU_PMU12A__OTP_DISABLE_5V_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define PMU_PMU12A__OTP_DISABLE_5V_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_vbatt_level_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_vbatt_level_ovr_val_field otp_vbatt_level_ovr_val_field + * @brief macros for field otp_vbatt_level_ovr_val + * @details override val for otp_vbatt_level + * @{ + */ +#define PMU_PMU12A__OTP_VBATT_LEVEL_OVR_VAL__SHIFT 12 +#define PMU_PMU12A__OTP_VBATT_LEVEL_OVR_VAL__WIDTH 1 +#define PMU_PMU12A__OTP_VBATT_LEVEL_OVR_VAL__MASK 0x00001000U +#define PMU_PMU12A__OTP_VBATT_LEVEL_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define PMU_PMU12A__OTP_VBATT_LEVEL_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define PMU_PMU12A__OTP_VBATT_LEVEL_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define PMU_PMU12A__OTP_VBATT_LEVEL_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define PMU_PMU12A__OTP_VBATT_LEVEL_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define PMU_PMU12A__OTP_VBATT_LEVEL_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define PMU_PMU12A__OTP_VBATT_LEVEL_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_vbatt_good_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_vbatt_good_ovr_val_field otp_vbatt_good_ovr_val_field + * @brief macros for field otp_vbatt_good_ovr_val + * @details override val for otp_vbatt_good + * @{ + */ +#define PMU_PMU12A__OTP_VBATT_GOOD_OVR_VAL__SHIFT 13 +#define PMU_PMU12A__OTP_VBATT_GOOD_OVR_VAL__WIDTH 3 +#define PMU_PMU12A__OTP_VBATT_GOOD_OVR_VAL__MASK 0x0000e000U +#define PMU_PMU12A__OTP_VBATT_GOOD_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x0000e000U) >> 13) +#define PMU_PMU12A__OTP_VBATT_GOOD_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0000e000U) +#define PMU_PMU12A__OTP_VBATT_GOOD_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((uint32_t)(src) <<\ + 13) & 0x0000e000U) +#define PMU_PMU12A__OTP_VBATT_GOOD_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0000e000U))) +#define PMU_PMU12A__OTP_VBATT_GOOD_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_vbatt_brownout_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_vbatt_brownout_ovr_val_field otp_vbatt_brownout_ovr_val_field + * @brief macros for field otp_vbatt_brownout_ovr_val + * @details override val for otp_vbatt_brownout + * @{ + */ +#define PMU_PMU12A__OTP_VBATT_BROWNOUT_OVR_VAL__SHIFT 16 +#define PMU_PMU12A__OTP_VBATT_BROWNOUT_OVR_VAL__WIDTH 5 +#define PMU_PMU12A__OTP_VBATT_BROWNOUT_OVR_VAL__MASK 0x001f0000U +#define PMU_PMU12A__OTP_VBATT_BROWNOUT_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x001f0000U) >> 16) +#define PMU_PMU12A__OTP_VBATT_BROWNOUT_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x001f0000U) +#define PMU_PMU12A__OTP_VBATT_BROWNOUT_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((uint32_t)(src) <<\ + 16) & 0x001f0000U) +#define PMU_PMU12A__OTP_VBATT_BROWNOUT_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x001f0000U))) +#define PMU_PMU12A__OTP_VBATT_BROWNOUT_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_vddio_range_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_vddio_range_ovr_val_field otp_vddio_range_ovr_val_field + * @brief macros for field otp_vddio_range_ovr_val + * @details override val for otp_vddio_range + * @{ + */ +#define PMU_PMU12A__OTP_VDDIO_RANGE_OVR_VAL__SHIFT 21 +#define PMU_PMU12A__OTP_VDDIO_RANGE_OVR_VAL__WIDTH 1 +#define PMU_PMU12A__OTP_VDDIO_RANGE_OVR_VAL__MASK 0x00200000U +#define PMU_PMU12A__OTP_VDDIO_RANGE_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define PMU_PMU12A__OTP_VDDIO_RANGE_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define PMU_PMU12A__OTP_VDDIO_RANGE_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define PMU_PMU12A__OTP_VDDIO_RANGE_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define PMU_PMU12A__OTP_VDDIO_RANGE_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define PMU_PMU12A__OTP_VDDIO_RANGE_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define PMU_PMU12A__OTP_VDDIO_RANGE_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_reserved_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_reserved_ovr_val_field otp_reserved_ovr_val_field + * @brief macros for field otp_reserved_ovr_val + * @details override val for otp_reserved + * @{ + */ +#define PMU_PMU12A__OTP_RESERVED_OVR_VAL__SHIFT 22 +#define PMU_PMU12A__OTP_RESERVED_OVR_VAL__WIDTH 1 +#define PMU_PMU12A__OTP_RESERVED_OVR_VAL__MASK 0x00400000U +#define PMU_PMU12A__OTP_RESERVED_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define PMU_PMU12A__OTP_RESERVED_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define PMU_PMU12A__OTP_RESERVED_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define PMU_PMU12A__OTP_RESERVED_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define PMU_PMU12A__OTP_RESERVED_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define PMU_PMU12A__OTP_RESERVED_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define PMU_PMU12A__OTP_RESERVED_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_disable_rfharv_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_disable_rfharv_ovr_val_field otp_disable_rfharv_ovr_val_field + * @brief macros for field otp_disable_rfharv_ovr_val + * @details override val for otp_disable_rfharv + * @{ + */ +#define PMU_PMU12A__OTP_DISABLE_RFHARV_OVR_VAL__SHIFT 23 +#define PMU_PMU12A__OTP_DISABLE_RFHARV_OVR_VAL__WIDTH 1 +#define PMU_PMU12A__OTP_DISABLE_RFHARV_OVR_VAL__MASK 0x00800000U +#define PMU_PMU12A__OTP_DISABLE_RFHARV_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PMU_PMU12A__OTP_DISABLE_RFHARV_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define PMU_PMU12A__OTP_DISABLE_RFHARV_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define PMU_PMU12A__OTP_DISABLE_RFHARV_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define PMU_PMU12A__OTP_DISABLE_RFHARV_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PMU_PMU12A__OTP_DISABLE_RFHARV_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PMU_PMU12A__OTP_DISABLE_RFHARV_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_vharv_start_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_vharv_start_ovr_val_field otp_vharv_start_ovr_val_field + * @brief macros for field otp_vharv_start_ovr_val + * @details override val for otp_vharv_start + * @{ + */ +#define PMU_PMU12A__OTP_VHARV_START_OVR_VAL__SHIFT 24 +#define PMU_PMU12A__OTP_VHARV_START_OVR_VAL__WIDTH 2 +#define PMU_PMU12A__OTP_VHARV_START_OVR_VAL__MASK 0x03000000U +#define PMU_PMU12A__OTP_VHARV_START_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x03000000U) >> 24) +#define PMU_PMU12A__OTP_VHARV_START_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x03000000U) +#define PMU_PMU12A__OTP_VHARV_START_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((uint32_t)(src) <<\ + 24) & 0x03000000U) +#define PMU_PMU12A__OTP_VHARV_START_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x03000000U))) +#define PMU_PMU12A__OTP_VHARV_START_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_vstore_good_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_vstore_good_ovr_val_field otp_vstore_good_ovr_val_field + * @brief macros for field otp_vstore_good_ovr_val + * @details override val for otp_vstore_good + * @{ + */ +#define PMU_PMU12A__OTP_VSTORE_GOOD_OVR_VAL__SHIFT 26 +#define PMU_PMU12A__OTP_VSTORE_GOOD_OVR_VAL__WIDTH 2 +#define PMU_PMU12A__OTP_VSTORE_GOOD_OVR_VAL__MASK 0x0c000000U +#define PMU_PMU12A__OTP_VSTORE_GOOD_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x0c000000U) >> 26) +#define PMU_PMU12A__OTP_VSTORE_GOOD_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x0c000000U) +#define PMU_PMU12A__OTP_VSTORE_GOOD_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((uint32_t)(src) <<\ + 26) & 0x0c000000U) +#define PMU_PMU12A__OTP_VSTORE_GOOD_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x0c000000U))) +#define PMU_PMU12A__OTP_VSTORE_GOOD_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_vstore_max_ovr_val */ +/** + * @defgroup pmu_top_regs_core_otp_vstore_max_ovr_val_field otp_vstore_max_ovr_val_field + * @brief macros for field otp_vstore_max_ovr_val + * @details override val for otp_vstore_max + * @{ + */ +#define PMU_PMU12A__OTP_VSTORE_MAX_OVR_VAL__SHIFT 28 +#define PMU_PMU12A__OTP_VSTORE_MAX_OVR_VAL__WIDTH 3 +#define PMU_PMU12A__OTP_VSTORE_MAX_OVR_VAL__MASK 0x70000000U +#define PMU_PMU12A__OTP_VSTORE_MAX_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x70000000U) >> 28) +#define PMU_PMU12A__OTP_VSTORE_MAX_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x70000000U) +#define PMU_PMU12A__OTP_VSTORE_MAX_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x70000000U) | (((uint32_t)(src) <<\ + 28) & 0x70000000U) +#define PMU_PMU12A__OTP_VSTORE_MAX_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x70000000U))) +#define PMU_PMU12A__OTP_VSTORE_MAX_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU12A__TYPE uint32_t +#define PMU_PMU12A__READ 0x7fffffffU +#define PMU_PMU12A__WRITE 0x7fffffffU +#define PMU_PMU12A__PRESERVED 0x00000000U +#define PMU_PMU12A__RESET_VALUE 0x00000000U + +#endif /* __PMU_PMU12A_MACRO__ */ + +/** @} end of pmu12a */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu13 */ +/** + * @defgroup pmu_top_regs_core_pmu13 pmu13 + * @brief test overrides definitions. + * @{ + */ +#ifndef __PMU_PMU13_MACRO__ +#define __PMU_PMU13_MACRO__ + +/* macros for field SwchReqDVDD_encomp_ovr */ +/** + * @defgroup pmu_top_regs_core_SwchReqDVDD_encomp_ovr_field SwchReqDVDD_encomp_ovr_field + * @brief macros for field SwchReqDVDD_encomp_ovr + * @details override + * @{ + */ +#define PMU_PMU13__SWCHREQDVDD_ENCOMP_OVR__SHIFT 0 +#define PMU_PMU13__SWCHREQDVDD_ENCOMP_OVR__WIDTH 1 +#define PMU_PMU13__SWCHREQDVDD_ENCOMP_OVR__MASK 0x00000001U +#define PMU_PMU13__SWCHREQDVDD_ENCOMP_OVR__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PMU_PMU13__SWCHREQDVDD_ENCOMP_OVR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PMU_PMU13__SWCHREQDVDD_ENCOMP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PMU_PMU13__SWCHREQDVDD_ENCOMP_OVR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PMU_PMU13__SWCHREQDVDD_ENCOMP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PMU_PMU13__SWCHREQDVDD_ENCOMP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PMU_PMU13__SWCHREQDVDD_ENCOMP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqDVDD_encomp_ovr_val */ +/** + * @defgroup pmu_top_regs_core_SwchReqDVDD_encomp_ovr_val_field SwchReqDVDD_encomp_ovr_val_field + * @brief macros for field SwchReqDVDD_encomp_ovr_val + * @details override_val + * @{ + */ +#define PMU_PMU13__SWCHREQDVDD_ENCOMP_OVR_VAL__SHIFT 1 +#define PMU_PMU13__SWCHREQDVDD_ENCOMP_OVR_VAL__WIDTH 1 +#define PMU_PMU13__SWCHREQDVDD_ENCOMP_OVR_VAL__MASK 0x00000002U +#define PMU_PMU13__SWCHREQDVDD_ENCOMP_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PMU_PMU13__SWCHREQDVDD_ENCOMP_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PMU_PMU13__SWCHREQDVDD_ENCOMP_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PMU_PMU13__SWCHREQDVDD_ENCOMP_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PMU_PMU13__SWCHREQDVDD_ENCOMP_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PMU_PMU13__SWCHREQDVDD_ENCOMP_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PMU_PMU13__SWCHREQDVDD_ENCOMP_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqVDDIO_encomp_ovr */ +/** + * @defgroup pmu_top_regs_core_SwchReqVDDIO_encomp_ovr_field SwchReqVDDIO_encomp_ovr_field + * @brief macros for field SwchReqVDDIO_encomp_ovr + * @details override + * @{ + */ +#define PMU_PMU13__SWCHREQVDDIO_ENCOMP_OVR__SHIFT 2 +#define PMU_PMU13__SWCHREQVDDIO_ENCOMP_OVR__WIDTH 1 +#define PMU_PMU13__SWCHREQVDDIO_ENCOMP_OVR__MASK 0x00000004U +#define PMU_PMU13__SWCHREQVDDIO_ENCOMP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PMU_PMU13__SWCHREQVDDIO_ENCOMP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PMU_PMU13__SWCHREQVDDIO_ENCOMP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PMU_PMU13__SWCHREQVDDIO_ENCOMP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PMU_PMU13__SWCHREQVDDIO_ENCOMP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PMU_PMU13__SWCHREQVDDIO_ENCOMP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PMU_PMU13__SWCHREQVDDIO_ENCOMP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqVDDIO_encomp_ovr_val */ +/** + * @defgroup pmu_top_regs_core_SwchReqVDDIO_encomp_ovr_val_field SwchReqVDDIO_encomp_ovr_val_field + * @brief macros for field SwchReqVDDIO_encomp_ovr_val + * @details override_val + * @{ + */ +#define PMU_PMU13__SWCHREQVDDIO_ENCOMP_OVR_VAL__SHIFT 3 +#define PMU_PMU13__SWCHREQVDDIO_ENCOMP_OVR_VAL__WIDTH 1 +#define PMU_PMU13__SWCHREQVDDIO_ENCOMP_OVR_VAL__MASK 0x00000008U +#define PMU_PMU13__SWCHREQVDDIO_ENCOMP_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PMU_PMU13__SWCHREQVDDIO_ENCOMP_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PMU_PMU13__SWCHREQVDDIO_ENCOMP_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PMU_PMU13__SWCHREQVDDIO_ENCOMP_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PMU_PMU13__SWCHREQVDDIO_ENCOMP_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PMU_PMU13__SWCHREQVDDIO_ENCOMP_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PMU_PMU13__SWCHREQVDDIO_ENCOMP_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqAVDD_encomp_ovr */ +/** + * @defgroup pmu_top_regs_core_SwchReqAVDD_encomp_ovr_field SwchReqAVDD_encomp_ovr_field + * @brief macros for field SwchReqAVDD_encomp_ovr + * @details override + * @{ + */ +#define PMU_PMU13__SWCHREQAVDD_ENCOMP_OVR__SHIFT 4 +#define PMU_PMU13__SWCHREQAVDD_ENCOMP_OVR__WIDTH 1 +#define PMU_PMU13__SWCHREQAVDD_ENCOMP_OVR__MASK 0x00000010U +#define PMU_PMU13__SWCHREQAVDD_ENCOMP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PMU_PMU13__SWCHREQAVDD_ENCOMP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PMU_PMU13__SWCHREQAVDD_ENCOMP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PMU_PMU13__SWCHREQAVDD_ENCOMP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PMU_PMU13__SWCHREQAVDD_ENCOMP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PMU_PMU13__SWCHREQAVDD_ENCOMP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PMU_PMU13__SWCHREQAVDD_ENCOMP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqAVDD_encomp_ovr_val */ +/** + * @defgroup pmu_top_regs_core_SwchReqAVDD_encomp_ovr_val_field SwchReqAVDD_encomp_ovr_val_field + * @brief macros for field SwchReqAVDD_encomp_ovr_val + * @details override_val + * @{ + */ +#define PMU_PMU13__SWCHREQAVDD_ENCOMP_OVR_VAL__SHIFT 5 +#define PMU_PMU13__SWCHREQAVDD_ENCOMP_OVR_VAL__WIDTH 1 +#define PMU_PMU13__SWCHREQAVDD_ENCOMP_OVR_VAL__MASK 0x00000020U +#define PMU_PMU13__SWCHREQAVDD_ENCOMP_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PMU_PMU13__SWCHREQAVDD_ENCOMP_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define PMU_PMU13__SWCHREQAVDD_ENCOMP_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define PMU_PMU13__SWCHREQAVDD_ENCOMP_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define PMU_PMU13__SWCHREQAVDD_ENCOMP_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PMU_PMU13__SWCHREQAVDD_ENCOMP_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PMU_PMU13__SWCHREQAVDD_ENCOMP_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqVAUX_encomp_ovr */ +/** + * @defgroup pmu_top_regs_core_SwchReqVAUX_encomp_ovr_field SwchReqVAUX_encomp_ovr_field + * @brief macros for field SwchReqVAUX_encomp_ovr + * @details override + * @{ + */ +#define PMU_PMU13__SWCHREQVAUX_ENCOMP_OVR__SHIFT 6 +#define PMU_PMU13__SWCHREQVAUX_ENCOMP_OVR__WIDTH 1 +#define PMU_PMU13__SWCHREQVAUX_ENCOMP_OVR__MASK 0x00000040U +#define PMU_PMU13__SWCHREQVAUX_ENCOMP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define PMU_PMU13__SWCHREQVAUX_ENCOMP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define PMU_PMU13__SWCHREQVAUX_ENCOMP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PMU_PMU13__SWCHREQVAUX_ENCOMP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PMU_PMU13__SWCHREQVAUX_ENCOMP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PMU_PMU13__SWCHREQVAUX_ENCOMP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PMU_PMU13__SWCHREQVAUX_ENCOMP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqVAUX_encomp_ovr_val */ +/** + * @defgroup pmu_top_regs_core_SwchReqVAUX_encomp_ovr_val_field SwchReqVAUX_encomp_ovr_val_field + * @brief macros for field SwchReqVAUX_encomp_ovr_val + * @details override_val + * @{ + */ +#define PMU_PMU13__SWCHREQVAUX_ENCOMP_OVR_VAL__SHIFT 7 +#define PMU_PMU13__SWCHREQVAUX_ENCOMP_OVR_VAL__WIDTH 1 +#define PMU_PMU13__SWCHREQVAUX_ENCOMP_OVR_VAL__MASK 0x00000080U +#define PMU_PMU13__SWCHREQVAUX_ENCOMP_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define PMU_PMU13__SWCHREQVAUX_ENCOMP_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define PMU_PMU13__SWCHREQVAUX_ENCOMP_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define PMU_PMU13__SWCHREQVAUX_ENCOMP_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define PMU_PMU13__SWCHREQVAUX_ENCOMP_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define PMU_PMU13__SWCHREQVAUX_ENCOMP_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define PMU_PMU13__SWCHREQVAUX_ENCOMP_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field porbsocdvdd_encomp_ovr */ +/** + * @defgroup pmu_top_regs_core_porbsocdvdd_encomp_ovr_field porbsocdvdd_encomp_ovr_field + * @brief macros for field porbsocdvdd_encomp_ovr + * @details override + * @{ + */ +#define PMU_PMU13__PORBSOCDVDD_ENCOMP_OVR__SHIFT 8 +#define PMU_PMU13__PORBSOCDVDD_ENCOMP_OVR__WIDTH 1 +#define PMU_PMU13__PORBSOCDVDD_ENCOMP_OVR__MASK 0x00000100U +#define PMU_PMU13__PORBSOCDVDD_ENCOMP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define PMU_PMU13__PORBSOCDVDD_ENCOMP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define PMU_PMU13__PORBSOCDVDD_ENCOMP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define PMU_PMU13__PORBSOCDVDD_ENCOMP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define PMU_PMU13__PORBSOCDVDD_ENCOMP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PMU_PMU13__PORBSOCDVDD_ENCOMP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PMU_PMU13__PORBSOCDVDD_ENCOMP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field porbsocdvdd_encomp_ovr_val */ +/** + * @defgroup pmu_top_regs_core_porbsocdvdd_encomp_ovr_val_field porbsocdvdd_encomp_ovr_val_field + * @brief macros for field porbsocdvdd_encomp_ovr_val + * @details override_val + * @{ + */ +#define PMU_PMU13__PORBSOCDVDD_ENCOMP_OVR_VAL__SHIFT 9 +#define PMU_PMU13__PORBSOCDVDD_ENCOMP_OVR_VAL__WIDTH 1 +#define PMU_PMU13__PORBSOCDVDD_ENCOMP_OVR_VAL__MASK 0x00000200U +#define PMU_PMU13__PORBSOCDVDD_ENCOMP_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PMU_PMU13__PORBSOCDVDD_ENCOMP_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define PMU_PMU13__PORBSOCDVDD_ENCOMP_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define PMU_PMU13__PORBSOCDVDD_ENCOMP_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define PMU_PMU13__PORBSOCDVDD_ENCOMP_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PMU_PMU13__PORBSOCDVDD_ENCOMP_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PMU_PMU13__PORBSOCDVDD_ENCOMP_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field porbsocvddio_encomp_ovr */ +/** + * @defgroup pmu_top_regs_core_porbsocvddio_encomp_ovr_field porbsocvddio_encomp_ovr_field + * @brief macros for field porbsocvddio_encomp_ovr + * @details override + * @{ + */ +#define PMU_PMU13__PORBSOCVDDIO_ENCOMP_OVR__SHIFT 10 +#define PMU_PMU13__PORBSOCVDDIO_ENCOMP_OVR__WIDTH 1 +#define PMU_PMU13__PORBSOCVDDIO_ENCOMP_OVR__MASK 0x00000400U +#define PMU_PMU13__PORBSOCVDDIO_ENCOMP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define PMU_PMU13__PORBSOCVDDIO_ENCOMP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define PMU_PMU13__PORBSOCVDDIO_ENCOMP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define PMU_PMU13__PORBSOCVDDIO_ENCOMP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define PMU_PMU13__PORBSOCVDDIO_ENCOMP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define PMU_PMU13__PORBSOCVDDIO_ENCOMP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define PMU_PMU13__PORBSOCVDDIO_ENCOMP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field porbsocvddio_encomp_ovr_val */ +/** + * @defgroup pmu_top_regs_core_porbsocvddio_encomp_ovr_val_field porbsocvddio_encomp_ovr_val_field + * @brief macros for field porbsocvddio_encomp_ovr_val + * @details override_val + * @{ + */ +#define PMU_PMU13__PORBSOCVDDIO_ENCOMP_OVR_VAL__SHIFT 11 +#define PMU_PMU13__PORBSOCVDDIO_ENCOMP_OVR_VAL__WIDTH 1 +#define PMU_PMU13__PORBSOCVDDIO_ENCOMP_OVR_VAL__MASK 0x00000800U +#define PMU_PMU13__PORBSOCVDDIO_ENCOMP_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define PMU_PMU13__PORBSOCVDDIO_ENCOMP_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define PMU_PMU13__PORBSOCVDDIO_ENCOMP_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define PMU_PMU13__PORBSOCVDDIO_ENCOMP_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define PMU_PMU13__PORBSOCVDDIO_ENCOMP_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define PMU_PMU13__PORBSOCVDDIO_ENCOMP_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define PMU_PMU13__PORBSOCVDDIO_ENCOMP_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field stoGoodtoEner_encomp_ovr */ +/** + * @defgroup pmu_top_regs_core_stoGoodtoEner_encomp_ovr_field stoGoodtoEner_encomp_ovr_field + * @brief macros for field stoGoodtoEner_encomp_ovr + * @details override + * @{ + */ +#define PMU_PMU13__STOGOODTOENER_ENCOMP_OVR__SHIFT 12 +#define PMU_PMU13__STOGOODTOENER_ENCOMP_OVR__WIDTH 1 +#define PMU_PMU13__STOGOODTOENER_ENCOMP_OVR__MASK 0x00001000U +#define PMU_PMU13__STOGOODTOENER_ENCOMP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define PMU_PMU13__STOGOODTOENER_ENCOMP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define PMU_PMU13__STOGOODTOENER_ENCOMP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define PMU_PMU13__STOGOODTOENER_ENCOMP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define PMU_PMU13__STOGOODTOENER_ENCOMP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define PMU_PMU13__STOGOODTOENER_ENCOMP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define PMU_PMU13__STOGOODTOENER_ENCOMP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field stoGoodtoEner_encomp_ovr_val */ +/** + * @defgroup pmu_top_regs_core_stoGoodtoEner_encomp_ovr_val_field stoGoodtoEner_encomp_ovr_val_field + * @brief macros for field stoGoodtoEner_encomp_ovr_val + * @details override_val + * @{ + */ +#define PMU_PMU13__STOGOODTOENER_ENCOMP_OVR_VAL__SHIFT 13 +#define PMU_PMU13__STOGOODTOENER_ENCOMP_OVR_VAL__WIDTH 1 +#define PMU_PMU13__STOGOODTOENER_ENCOMP_OVR_VAL__MASK 0x00002000U +#define PMU_PMU13__STOGOODTOENER_ENCOMP_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define PMU_PMU13__STOGOODTOENER_ENCOMP_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define PMU_PMU13__STOGOODTOENER_ENCOMP_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define PMU_PMU13__STOGOODTOENER_ENCOMP_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define PMU_PMU13__STOGOODTOENER_ENCOMP_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define PMU_PMU13__STOGOODTOENER_ENCOMP_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define PMU_PMU13__STOGOODTOENER_ENCOMP_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field stoGoodtoTX_encomp_ovr */ +/** + * @defgroup pmu_top_regs_core_stoGoodtoTX_encomp_ovr_field stoGoodtoTX_encomp_ovr_field + * @brief macros for field stoGoodtoTX_encomp_ovr + * @details override + * @{ + */ +#define PMU_PMU13__STOGOODTOTX_ENCOMP_OVR__SHIFT 14 +#define PMU_PMU13__STOGOODTOTX_ENCOMP_OVR__WIDTH 1 +#define PMU_PMU13__STOGOODTOTX_ENCOMP_OVR__MASK 0x00004000U +#define PMU_PMU13__STOGOODTOTX_ENCOMP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PMU_PMU13__STOGOODTOTX_ENCOMP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define PMU_PMU13__STOGOODTOTX_ENCOMP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define PMU_PMU13__STOGOODTOTX_ENCOMP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define PMU_PMU13__STOGOODTOTX_ENCOMP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PMU_PMU13__STOGOODTOTX_ENCOMP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PMU_PMU13__STOGOODTOTX_ENCOMP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field stoGoodtoTX_encomp_ovr_val */ +/** + * @defgroup pmu_top_regs_core_stoGoodtoTX_encomp_ovr_val_field stoGoodtoTX_encomp_ovr_val_field + * @brief macros for field stoGoodtoTX_encomp_ovr_val + * @details override_val + * @{ + */ +#define PMU_PMU13__STOGOODTOTX_ENCOMP_OVR_VAL__SHIFT 15 +#define PMU_PMU13__STOGOODTOTX_ENCOMP_OVR_VAL__WIDTH 1 +#define PMU_PMU13__STOGOODTOTX_ENCOMP_OVR_VAL__MASK 0x00008000U +#define PMU_PMU13__STOGOODTOTX_ENCOMP_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define PMU_PMU13__STOGOODTOTX_ENCOMP_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define PMU_PMU13__STOGOODTOTX_ENCOMP_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define PMU_PMU13__STOGOODTOTX_ENCOMP_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define PMU_PMU13__STOGOODTOTX_ENCOMP_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PMU_PMU13__STOGOODTOTX_ENCOMP_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PMU_PMU13__STOGOODTOTX_ENCOMP_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field srvevaux_encomp_ovr */ +/** + * @defgroup pmu_top_regs_core_srvevaux_encomp_ovr_field srvevaux_encomp_ovr_field + * @brief macros for field srvevaux_encomp_ovr + * @details unused + * @{ + */ +#define PMU_PMU13__SRVEVAUX_ENCOMP_OVR__SHIFT 16 +#define PMU_PMU13__SRVEVAUX_ENCOMP_OVR__WIDTH 1 +#define PMU_PMU13__SRVEVAUX_ENCOMP_OVR__MASK 0x00010000U +#define PMU_PMU13__SRVEVAUX_ENCOMP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define PMU_PMU13__SRVEVAUX_ENCOMP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define PMU_PMU13__SRVEVAUX_ENCOMP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define PMU_PMU13__SRVEVAUX_ENCOMP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define PMU_PMU13__SRVEVAUX_ENCOMP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PMU_PMU13__SRVEVAUX_ENCOMP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PMU_PMU13__SRVEVAUX_ENCOMP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field srvevaux_encomp_ovr_val */ +/** + * @defgroup pmu_top_regs_core_srvevaux_encomp_ovr_val_field srvevaux_encomp_ovr_val_field + * @brief macros for field srvevaux_encomp_ovr_val + * @details unused + * @{ + */ +#define PMU_PMU13__SRVEVAUX_ENCOMP_OVR_VAL__SHIFT 17 +#define PMU_PMU13__SRVEVAUX_ENCOMP_OVR_VAL__WIDTH 1 +#define PMU_PMU13__SRVEVAUX_ENCOMP_OVR_VAL__MASK 0x00020000U +#define PMU_PMU13__SRVEVAUX_ENCOMP_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define PMU_PMU13__SRVEVAUX_ENCOMP_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define PMU_PMU13__SRVEVAUX_ENCOMP_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define PMU_PMU13__SRVEVAUX_ENCOMP_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define PMU_PMU13__SRVEVAUX_ENCOMP_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define PMU_PMU13__SRVEVAUX_ENCOMP_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define PMU_PMU13__SRVEVAUX_ENCOMP_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field harvstop_encomp_ovr */ +/** + * @defgroup pmu_top_regs_core_harvstop_encomp_ovr_field harvstop_encomp_ovr_field + * @brief macros for field harvstop_encomp_ovr + * @details override + * @{ + */ +#define PMU_PMU13__HARVSTOP_ENCOMP_OVR__SHIFT 18 +#define PMU_PMU13__HARVSTOP_ENCOMP_OVR__WIDTH 1 +#define PMU_PMU13__HARVSTOP_ENCOMP_OVR__MASK 0x00040000U +#define PMU_PMU13__HARVSTOP_ENCOMP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define PMU_PMU13__HARVSTOP_ENCOMP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define PMU_PMU13__HARVSTOP_ENCOMP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define PMU_PMU13__HARVSTOP_ENCOMP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define PMU_PMU13__HARVSTOP_ENCOMP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define PMU_PMU13__HARVSTOP_ENCOMP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define PMU_PMU13__HARVSTOP_ENCOMP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field harvstop_encomp_ovr_val */ +/** + * @defgroup pmu_top_regs_core_harvstop_encomp_ovr_val_field harvstop_encomp_ovr_val_field + * @brief macros for field harvstop_encomp_ovr_val + * @details override_val + * @{ + */ +#define PMU_PMU13__HARVSTOP_ENCOMP_OVR_VAL__SHIFT 19 +#define PMU_PMU13__HARVSTOP_ENCOMP_OVR_VAL__WIDTH 1 +#define PMU_PMU13__HARVSTOP_ENCOMP_OVR_VAL__MASK 0x00080000U +#define PMU_PMU13__HARVSTOP_ENCOMP_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define PMU_PMU13__HARVSTOP_ENCOMP_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define PMU_PMU13__HARVSTOP_ENCOMP_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define PMU_PMU13__HARVSTOP_ENCOMP_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define PMU_PMU13__HARVSTOP_ENCOMP_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define PMU_PMU13__HARVSTOP_ENCOMP_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define PMU_PMU13__HARVSTOP_ENCOMP_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field browovbat_encomp_ovr */ +/** + * @defgroup pmu_top_regs_core_browovbat_encomp_ovr_field browovbat_encomp_ovr_field + * @brief macros for field browovbat_encomp_ovr + * @details override + * @{ + */ +#define PMU_PMU13__BROWOVBAT_ENCOMP_OVR__SHIFT 20 +#define PMU_PMU13__BROWOVBAT_ENCOMP_OVR__WIDTH 1 +#define PMU_PMU13__BROWOVBAT_ENCOMP_OVR__MASK 0x00100000U +#define PMU_PMU13__BROWOVBAT_ENCOMP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define PMU_PMU13__BROWOVBAT_ENCOMP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define PMU_PMU13__BROWOVBAT_ENCOMP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define PMU_PMU13__BROWOVBAT_ENCOMP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define PMU_PMU13__BROWOVBAT_ENCOMP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define PMU_PMU13__BROWOVBAT_ENCOMP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define PMU_PMU13__BROWOVBAT_ENCOMP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field browovbat_encomp_ovr_val */ +/** + * @defgroup pmu_top_regs_core_browovbat_encomp_ovr_val_field browovbat_encomp_ovr_val_field + * @brief macros for field browovbat_encomp_ovr_val + * @details override_val + * @{ + */ +#define PMU_PMU13__BROWOVBAT_ENCOMP_OVR_VAL__SHIFT 21 +#define PMU_PMU13__BROWOVBAT_ENCOMP_OVR_VAL__WIDTH 1 +#define PMU_PMU13__BROWOVBAT_ENCOMP_OVR_VAL__MASK 0x00200000U +#define PMU_PMU13__BROWOVBAT_ENCOMP_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define PMU_PMU13__BROWOVBAT_ENCOMP_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define PMU_PMU13__BROWOVBAT_ENCOMP_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define PMU_PMU13__BROWOVBAT_ENCOMP_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define PMU_PMU13__BROWOVBAT_ENCOMP_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define PMU_PMU13__BROWOVBAT_ENCOMP_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define PMU_PMU13__BROWOVBAT_ENCOMP_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field harv_encomp_ovr */ +/** + * @defgroup pmu_top_regs_core_harv_encomp_ovr_field harv_encomp_ovr_field + * @brief macros for field harv_encomp_ovr + * @details override + * @{ + */ +#define PMU_PMU13__HARV_ENCOMP_OVR__SHIFT 22 +#define PMU_PMU13__HARV_ENCOMP_OVR__WIDTH 1 +#define PMU_PMU13__HARV_ENCOMP_OVR__MASK 0x00400000U +#define PMU_PMU13__HARV_ENCOMP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define PMU_PMU13__HARV_ENCOMP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define PMU_PMU13__HARV_ENCOMP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define PMU_PMU13__HARV_ENCOMP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define PMU_PMU13__HARV_ENCOMP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define PMU_PMU13__HARV_ENCOMP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define PMU_PMU13__HARV_ENCOMP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field harv_encomp_ovr_val */ +/** + * @defgroup pmu_top_regs_core_harv_encomp_ovr_val_field harv_encomp_ovr_val_field + * @brief macros for field harv_encomp_ovr_val + * @details override_val: enable can/must harv enable comparators + * @{ + */ +#define PMU_PMU13__HARV_ENCOMP_OVR_VAL__SHIFT 23 +#define PMU_PMU13__HARV_ENCOMP_OVR_VAL__WIDTH 1 +#define PMU_PMU13__HARV_ENCOMP_OVR_VAL__MASK 0x00800000U +#define PMU_PMU13__HARV_ENCOMP_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PMU_PMU13__HARV_ENCOMP_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define PMU_PMU13__HARV_ENCOMP_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define PMU_PMU13__HARV_ENCOMP_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define PMU_PMU13__HARV_ENCOMP_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PMU_PMU13__HARV_ENCOMP_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PMU_PMU13__HARV_ENCOMP_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mpptstart_encomp_ovr */ +/** + * @defgroup pmu_top_regs_core_mpptstart_encomp_ovr_field mpptstart_encomp_ovr_field + * @brief macros for field mpptstart_encomp_ovr + * @details unused + * @{ + */ +#define PMU_PMU13__MPPTSTART_ENCOMP_OVR__SHIFT 24 +#define PMU_PMU13__MPPTSTART_ENCOMP_OVR__WIDTH 1 +#define PMU_PMU13__MPPTSTART_ENCOMP_OVR__MASK 0x01000000U +#define PMU_PMU13__MPPTSTART_ENCOMP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define PMU_PMU13__MPPTSTART_ENCOMP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define PMU_PMU13__MPPTSTART_ENCOMP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define PMU_PMU13__MPPTSTART_ENCOMP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define PMU_PMU13__MPPTSTART_ENCOMP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define PMU_PMU13__MPPTSTART_ENCOMP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define PMU_PMU13__MPPTSTART_ENCOMP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mpptstart_encomp_ovr_val */ +/** + * @defgroup pmu_top_regs_core_mpptstart_encomp_ovr_val_field mpptstart_encomp_ovr_val_field + * @brief macros for field mpptstart_encomp_ovr_val + * @details unused + * @{ + */ +#define PMU_PMU13__MPPTSTART_ENCOMP_OVR_VAL__SHIFT 25 +#define PMU_PMU13__MPPTSTART_ENCOMP_OVR_VAL__WIDTH 1 +#define PMU_PMU13__MPPTSTART_ENCOMP_OVR_VAL__MASK 0x02000000U +#define PMU_PMU13__MPPTSTART_ENCOMP_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define PMU_PMU13__MPPTSTART_ENCOMP_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define PMU_PMU13__MPPTSTART_ENCOMP_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define PMU_PMU13__MPPTSTART_ENCOMP_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define PMU_PMU13__MPPTSTART_ENCOMP_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define PMU_PMU13__MPPTSTART_ENCOMP_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define PMU_PMU13__MPPTSTART_ENCOMP_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reconfharv_encomp_ovr */ +/** + * @defgroup pmu_top_regs_core_reconfharv_encomp_ovr_field reconfharv_encomp_ovr_field + * @brief macros for field reconfharv_encomp_ovr + * @details override decrectst_encomp + * @{ + */ +#define PMU_PMU13__RECONFHARV_ENCOMP_OVR__SHIFT 26 +#define PMU_PMU13__RECONFHARV_ENCOMP_OVR__WIDTH 1 +#define PMU_PMU13__RECONFHARV_ENCOMP_OVR__MASK 0x04000000U +#define PMU_PMU13__RECONFHARV_ENCOMP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define PMU_PMU13__RECONFHARV_ENCOMP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define PMU_PMU13__RECONFHARV_ENCOMP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define PMU_PMU13__RECONFHARV_ENCOMP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define PMU_PMU13__RECONFHARV_ENCOMP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define PMU_PMU13__RECONFHARV_ENCOMP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define PMU_PMU13__RECONFHARV_ENCOMP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reconfharv_encomp_ovr_val */ +/** + * @defgroup pmu_top_regs_core_reconfharv_encomp_ovr_val_field reconfharv_encomp_ovr_val_field + * @brief macros for field reconfharv_encomp_ovr_val + * @details override decrectst_encomp val: enable decrectstage_prtVharv comparator + * @{ + */ +#define PMU_PMU13__RECONFHARV_ENCOMP_OVR_VAL__SHIFT 27 +#define PMU_PMU13__RECONFHARV_ENCOMP_OVR_VAL__WIDTH 1 +#define PMU_PMU13__RECONFHARV_ENCOMP_OVR_VAL__MASK 0x08000000U +#define PMU_PMU13__RECONFHARV_ENCOMP_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define PMU_PMU13__RECONFHARV_ENCOMP_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define PMU_PMU13__RECONFHARV_ENCOMP_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define PMU_PMU13__RECONFHARV_ENCOMP_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define PMU_PMU13__RECONFHARV_ENCOMP_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define PMU_PMU13__RECONFHARV_ENCOMP_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define PMU_PMU13__RECONFHARV_ENCOMP_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_ldo_en_ovr */ +/** + * @defgroup pmu_top_regs_core_ctr_ldo_en_ovr_field ctr_ldo_en_ovr_field + * @brief macros for field ctr_ldo_en_ovr + * @details override ctr_ldomem_en + * @{ + */ +#define PMU_PMU13__CTR_LDO_EN_OVR__SHIFT 28 +#define PMU_PMU13__CTR_LDO_EN_OVR__WIDTH 1 +#define PMU_PMU13__CTR_LDO_EN_OVR__MASK 0x10000000U +#define PMU_PMU13__CTR_LDO_EN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define PMU_PMU13__CTR_LDO_EN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define PMU_PMU13__CTR_LDO_EN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define PMU_PMU13__CTR_LDO_EN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define PMU_PMU13__CTR_LDO_EN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define PMU_PMU13__CTR_LDO_EN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define PMU_PMU13__CTR_LDO_EN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_ldo_en_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ctr_ldo_en_ovr_val_field ctr_ldo_en_ovr_val_field + * @brief macros for field ctr_ldo_en_ovr_val + * @details override ctr_ldomem_en val + * @{ + */ +#define PMU_PMU13__CTR_LDO_EN_OVR_VAL__SHIFT 29 +#define PMU_PMU13__CTR_LDO_EN_OVR_VAL__WIDTH 1 +#define PMU_PMU13__CTR_LDO_EN_OVR_VAL__MASK 0x20000000U +#define PMU_PMU13__CTR_LDO_EN_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define PMU_PMU13__CTR_LDO_EN_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define PMU_PMU13__CTR_LDO_EN_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define PMU_PMU13__CTR_LDO_EN_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define PMU_PMU13__CTR_LDO_EN_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define PMU_PMU13__CTR_LDO_EN_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define PMU_PMU13__CTR_LDO_EN_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_ldo_bypass_ovr */ +/** + * @defgroup pmu_top_regs_core_ctr_ldo_bypass_ovr_field ctr_ldo_bypass_ovr_field + * @brief macros for field ctr_ldo_bypass_ovr + * @details override ctr_ldomem_bypass + * @{ + */ +#define PMU_PMU13__CTR_LDO_BYPASS_OVR__SHIFT 30 +#define PMU_PMU13__CTR_LDO_BYPASS_OVR__WIDTH 1 +#define PMU_PMU13__CTR_LDO_BYPASS_OVR__MASK 0x40000000U +#define PMU_PMU13__CTR_LDO_BYPASS_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define PMU_PMU13__CTR_LDO_BYPASS_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define PMU_PMU13__CTR_LDO_BYPASS_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define PMU_PMU13__CTR_LDO_BYPASS_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define PMU_PMU13__CTR_LDO_BYPASS_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define PMU_PMU13__CTR_LDO_BYPASS_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define PMU_PMU13__CTR_LDO_BYPASS_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_ldo_bypass_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ctr_ldo_bypass_ovr_val_field ctr_ldo_bypass_ovr_val_field + * @brief macros for field ctr_ldo_bypass_ovr_val + * @details override ctr_ldomem_bypass val + * @{ + */ +#define PMU_PMU13__CTR_LDO_BYPASS_OVR_VAL__SHIFT 31 +#define PMU_PMU13__CTR_LDO_BYPASS_OVR_VAL__WIDTH 1 +#define PMU_PMU13__CTR_LDO_BYPASS_OVR_VAL__MASK 0x80000000U +#define PMU_PMU13__CTR_LDO_BYPASS_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define PMU_PMU13__CTR_LDO_BYPASS_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define PMU_PMU13__CTR_LDO_BYPASS_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define PMU_PMU13__CTR_LDO_BYPASS_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define PMU_PMU13__CTR_LDO_BYPASS_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PMU_PMU13__CTR_LDO_BYPASS_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PMU_PMU13__CTR_LDO_BYPASS_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU13__TYPE uint32_t +#define PMU_PMU13__READ 0xffffffffU +#define PMU_PMU13__WRITE 0xffffffffU +#define PMU_PMU13__PRESERVED 0x00000000U +#define PMU_PMU13__RESET_VALUE 0x00000000U + +#endif /* __PMU_PMU13_MACRO__ */ + +/** @} end of pmu13 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu14 */ +/** + * @defgroup pmu_top_regs_core_pmu14 pmu14 + * @brief source/destination overrides definitions. + * @{ + */ +#ifndef __PMU_PMU14_MACRO__ +#define __PMU_PMU14_MACRO__ + +/* macros for field src2_ovr */ +/** + * @defgroup pmu_top_regs_core_src2_ovr_field src2_ovr_field + * @brief macros for field src2_ovr + * @details override + * @{ + */ +#define PMU_PMU14__SRC2_OVR__SHIFT 0 +#define PMU_PMU14__SRC2_OVR__WIDTH 1 +#define PMU_PMU14__SRC2_OVR__MASK 0x00000001U +#define PMU_PMU14__SRC2_OVR__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PMU_PMU14__SRC2_OVR__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PMU_PMU14__SRC2_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PMU_PMU14__SRC2_OVR__VERIFY(src) (!(((uint32_t)(src) & ~0x00000001U))) +#define PMU_PMU14__SRC2_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PMU_PMU14__SRC2_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PMU_PMU14__SRC2_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field src2_ovr_val */ +/** + * @defgroup pmu_top_regs_core_src2_ovr_val_field src2_ovr_val_field + * @brief macros for field src2_ovr_val + * @details override val + * @{ + */ +#define PMU_PMU14__SRC2_OVR_VAL__SHIFT 1 +#define PMU_PMU14__SRC2_OVR_VAL__WIDTH 1 +#define PMU_PMU14__SRC2_OVR_VAL__MASK 0x00000002U +#define PMU_PMU14__SRC2_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PMU_PMU14__SRC2_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PMU_PMU14__SRC2_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PMU_PMU14__SRC2_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PMU_PMU14__SRC2_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PMU_PMU14__SRC2_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PMU_PMU14__SRC2_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dest1_ovr */ +/** + * @defgroup pmu_top_regs_core_dest1_ovr_field dest1_ovr_field + * @brief macros for field dest1_ovr + * @details override + * @{ + */ +#define PMU_PMU14__DEST1_OVR__SHIFT 2 +#define PMU_PMU14__DEST1_OVR__WIDTH 1 +#define PMU_PMU14__DEST1_OVR__MASK 0x00000004U +#define PMU_PMU14__DEST1_OVR__READ(src) (((uint32_t)(src) & 0x00000004U) >> 2) +#define PMU_PMU14__DEST1_OVR__WRITE(src) (((uint32_t)(src) << 2) & 0x00000004U) +#define PMU_PMU14__DEST1_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PMU_PMU14__DEST1_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PMU_PMU14__DEST1_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PMU_PMU14__DEST1_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PMU_PMU14__DEST1_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dest1_ovr_val */ +/** + * @defgroup pmu_top_regs_core_dest1_ovr_val_field dest1_ovr_val_field + * @brief macros for field dest1_ovr_val + * @details override val + * @{ + */ +#define PMU_PMU14__DEST1_OVR_VAL__SHIFT 3 +#define PMU_PMU14__DEST1_OVR_VAL__WIDTH 1 +#define PMU_PMU14__DEST1_OVR_VAL__MASK 0x00000008U +#define PMU_PMU14__DEST1_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PMU_PMU14__DEST1_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PMU_PMU14__DEST1_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PMU_PMU14__DEST1_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PMU_PMU14__DEST1_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PMU_PMU14__DEST1_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PMU_PMU14__DEST1_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dest2_ovr */ +/** + * @defgroup pmu_top_regs_core_dest2_ovr_field dest2_ovr_field + * @brief macros for field dest2_ovr + * @details override + * @{ + */ +#define PMU_PMU14__DEST2_OVR__SHIFT 4 +#define PMU_PMU14__DEST2_OVR__WIDTH 1 +#define PMU_PMU14__DEST2_OVR__MASK 0x00000010U +#define PMU_PMU14__DEST2_OVR__READ(src) (((uint32_t)(src) & 0x00000010U) >> 4) +#define PMU_PMU14__DEST2_OVR__WRITE(src) (((uint32_t)(src) << 4) & 0x00000010U) +#define PMU_PMU14__DEST2_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PMU_PMU14__DEST2_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PMU_PMU14__DEST2_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PMU_PMU14__DEST2_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PMU_PMU14__DEST2_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dest2_ovr_val */ +/** + * @defgroup pmu_top_regs_core_dest2_ovr_val_field dest2_ovr_val_field + * @brief macros for field dest2_ovr_val + * @details override val + * @{ + */ +#define PMU_PMU14__DEST2_OVR_VAL__SHIFT 5 +#define PMU_PMU14__DEST2_OVR_VAL__WIDTH 1 +#define PMU_PMU14__DEST2_OVR_VAL__MASK 0x00000020U +#define PMU_PMU14__DEST2_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PMU_PMU14__DEST2_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define PMU_PMU14__DEST2_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define PMU_PMU14__DEST2_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define PMU_PMU14__DEST2_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PMU_PMU14__DEST2_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PMU_PMU14__DEST2_OVR_VAL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field dest3_ovr */ +/** + * @defgroup pmu_top_regs_core_dest3_ovr_field dest3_ovr_field + * @brief macros for field dest3_ovr + * @details override + * @{ + */ +#define PMU_PMU14__DEST3_OVR__SHIFT 6 +#define PMU_PMU14__DEST3_OVR__WIDTH 1 +#define PMU_PMU14__DEST3_OVR__MASK 0x00000040U +#define PMU_PMU14__DEST3_OVR__READ(src) (((uint32_t)(src) & 0x00000040U) >> 6) +#define PMU_PMU14__DEST3_OVR__WRITE(src) (((uint32_t)(src) << 6) & 0x00000040U) +#define PMU_PMU14__DEST3_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PMU_PMU14__DEST3_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PMU_PMU14__DEST3_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PMU_PMU14__DEST3_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PMU_PMU14__DEST3_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dest3_ovr_val */ +/** + * @defgroup pmu_top_regs_core_dest3_ovr_val_field dest3_ovr_val_field + * @brief macros for field dest3_ovr_val + * @details override val + * @{ + */ +#define PMU_PMU14__DEST3_OVR_VAL__SHIFT 7 +#define PMU_PMU14__DEST3_OVR_VAL__WIDTH 1 +#define PMU_PMU14__DEST3_OVR_VAL__MASK 0x00000080U +#define PMU_PMU14__DEST3_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define PMU_PMU14__DEST3_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define PMU_PMU14__DEST3_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define PMU_PMU14__DEST3_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define PMU_PMU14__DEST3_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define PMU_PMU14__DEST3_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define PMU_PMU14__DEST3_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dest4_ovr */ +/** + * @defgroup pmu_top_regs_core_dest4_ovr_field dest4_ovr_field + * @brief macros for field dest4_ovr + * @details override + * @{ + */ +#define PMU_PMU14__DEST4_OVR__SHIFT 8 +#define PMU_PMU14__DEST4_OVR__WIDTH 1 +#define PMU_PMU14__DEST4_OVR__MASK 0x00000100U +#define PMU_PMU14__DEST4_OVR__READ(src) (((uint32_t)(src) & 0x00000100U) >> 8) +#define PMU_PMU14__DEST4_OVR__WRITE(src) (((uint32_t)(src) << 8) & 0x00000100U) +#define PMU_PMU14__DEST4_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define PMU_PMU14__DEST4_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define PMU_PMU14__DEST4_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PMU_PMU14__DEST4_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PMU_PMU14__DEST4_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dest4_ovr_val */ +/** + * @defgroup pmu_top_regs_core_dest4_ovr_val_field dest4_ovr_val_field + * @brief macros for field dest4_ovr_val + * @details override val + * @{ + */ +#define PMU_PMU14__DEST4_OVR_VAL__SHIFT 9 +#define PMU_PMU14__DEST4_OVR_VAL__WIDTH 1 +#define PMU_PMU14__DEST4_OVR_VAL__MASK 0x00000200U +#define PMU_PMU14__DEST4_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PMU_PMU14__DEST4_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define PMU_PMU14__DEST4_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define PMU_PMU14__DEST4_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define PMU_PMU14__DEST4_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PMU_PMU14__DEST4_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PMU_PMU14__DEST4_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field state_ovr */ +/** + * @defgroup pmu_top_regs_core_state_ovr_field state_ovr_field + * @brief macros for field state_ovr + * @details override pmu state for test + * @{ + */ +#define PMU_PMU14__STATE_OVR__SHIFT 10 +#define PMU_PMU14__STATE_OVR__WIDTH 1 +#define PMU_PMU14__STATE_OVR__MASK 0x00000400U +#define PMU_PMU14__STATE_OVR__READ(src) (((uint32_t)(src) & 0x00000400U) >> 10) +#define PMU_PMU14__STATE_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define PMU_PMU14__STATE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define PMU_PMU14__STATE_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define PMU_PMU14__STATE_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define PMU_PMU14__STATE_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define PMU_PMU14__STATE_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field test_state */ +/** + * @defgroup pmu_top_regs_core_test_state_field test_state_field + * @brief macros for field test_state + * @details force the pmu state to be this state + * @{ + */ +#define PMU_PMU14__TEST_STATE__SHIFT 11 +#define PMU_PMU14__TEST_STATE__WIDTH 3 +#define PMU_PMU14__TEST_STATE__MASK 0x00003800U +#define PMU_PMU14__TEST_STATE__READ(src) \ + (((uint32_t)(src)\ + & 0x00003800U) >> 11) +#define PMU_PMU14__TEST_STATE__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00003800U) +#define PMU_PMU14__TEST_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((uint32_t)(src) <<\ + 11) & 0x00003800U) +#define PMU_PMU14__TEST_STATE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00003800U))) +#define PMU_PMU14__TEST_STATE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pwr_mode_ovr */ +/** + * @defgroup pmu_top_regs_core_pwr_mode_ovr_field pwr_mode_ovr_field + * @brief macros for field pwr_mode_ovr + * @details override power mode for testing + * @{ + */ +#define PMU_PMU14__PWR_MODE_OVR__SHIFT 14 +#define PMU_PMU14__PWR_MODE_OVR__WIDTH 1 +#define PMU_PMU14__PWR_MODE_OVR__MASK 0x00004000U +#define PMU_PMU14__PWR_MODE_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PMU_PMU14__PWR_MODE_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define PMU_PMU14__PWR_MODE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define PMU_PMU14__PWR_MODE_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define PMU_PMU14__PWR_MODE_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PMU_PMU14__PWR_MODE_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PMU_PMU14__PWR_MODE_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pwr_mode_val */ +/** + * @defgroup pmu_top_regs_core_pwr_mode_val_field pwr_mode_val_field + * @brief macros for field pwr_mode_val + * @details pwr_mode override value + * @{ + */ +#define PMU_PMU14__PWR_MODE_VAL__SHIFT 15 +#define PMU_PMU14__PWR_MODE_VAL__WIDTH 3 +#define PMU_PMU14__PWR_MODE_VAL__MASK 0x00038000U +#define PMU_PMU14__PWR_MODE_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00038000U) >> 15) +#define PMU_PMU14__PWR_MODE_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00038000U) +#define PMU_PMU14__PWR_MODE_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((uint32_t)(src) <<\ + 15) & 0x00038000U) +#define PMU_PMU14__PWR_MODE_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00038000U))) +#define PMU_PMU14__PWR_MODE_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wkup_timer_en_ovr */ +/** + * @defgroup pmu_top_regs_core_wkup_timer_en_ovr_field wkup_timer_en_ovr_field + * @brief macros for field wkup_timer_en_ovr + * @details override + * @{ + */ +#define PMU_PMU14__WKUP_TIMER_EN_OVR__SHIFT 18 +#define PMU_PMU14__WKUP_TIMER_EN_OVR__WIDTH 1 +#define PMU_PMU14__WKUP_TIMER_EN_OVR__MASK 0x00040000U +#define PMU_PMU14__WKUP_TIMER_EN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define PMU_PMU14__WKUP_TIMER_EN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define PMU_PMU14__WKUP_TIMER_EN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define PMU_PMU14__WKUP_TIMER_EN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define PMU_PMU14__WKUP_TIMER_EN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define PMU_PMU14__WKUP_TIMER_EN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define PMU_PMU14__WKUP_TIMER_EN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wkup_timer_en_val */ +/** + * @defgroup pmu_top_regs_core_wkup_timer_en_val_field wkup_timer_en_val_field + * @brief macros for field wkup_timer_en_val + * @details override val + * @{ + */ +#define PMU_PMU14__WKUP_TIMER_EN_VAL__SHIFT 19 +#define PMU_PMU14__WKUP_TIMER_EN_VAL__WIDTH 1 +#define PMU_PMU14__WKUP_TIMER_EN_VAL__MASK 0x00080000U +#define PMU_PMU14__WKUP_TIMER_EN_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define PMU_PMU14__WKUP_TIMER_EN_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define PMU_PMU14__WKUP_TIMER_EN_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define PMU_PMU14__WKUP_TIMER_EN_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define PMU_PMU14__WKUP_TIMER_EN_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define PMU_PMU14__WKUP_TIMER_EN_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define PMU_PMU14__WKUP_TIMER_EN_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field lpcomp_en_ovr */ +/** + * @defgroup pmu_top_regs_core_lpcomp_en_ovr_field lpcomp_en_ovr_field + * @brief macros for field lpcomp_en_ovr + * @details override + * @{ + */ +#define PMU_PMU14__LPCOMP_EN_OVR__SHIFT 20 +#define PMU_PMU14__LPCOMP_EN_OVR__WIDTH 1 +#define PMU_PMU14__LPCOMP_EN_OVR__MASK 0x00100000U +#define PMU_PMU14__LPCOMP_EN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define PMU_PMU14__LPCOMP_EN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define PMU_PMU14__LPCOMP_EN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define PMU_PMU14__LPCOMP_EN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define PMU_PMU14__LPCOMP_EN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define PMU_PMU14__LPCOMP_EN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define PMU_PMU14__LPCOMP_EN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field lpcomp_en_ovr_val */ +/** + * @defgroup pmu_top_regs_core_lpcomp_en_ovr_val_field lpcomp_en_ovr_val_field + * @brief macros for field lpcomp_en_ovr_val + * @details override val + * @{ + */ +#define PMU_PMU14__LPCOMP_EN_OVR_VAL__SHIFT 21 +#define PMU_PMU14__LPCOMP_EN_OVR_VAL__WIDTH 1 +#define PMU_PMU14__LPCOMP_EN_OVR_VAL__MASK 0x00200000U +#define PMU_PMU14__LPCOMP_EN_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define PMU_PMU14__LPCOMP_EN_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define PMU_PMU14__LPCOMP_EN_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define PMU_PMU14__LPCOMP_EN_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define PMU_PMU14__LPCOMP_EN_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define PMU_PMU14__LPCOMP_EN_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define PMU_PMU14__LPCOMP_EN_OVR_VAL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pinedge_en_ovr */ +/** + * @defgroup pmu_top_regs_core_pinedge_en_ovr_field pinedge_en_ovr_field + * @brief macros for field pinedge_en_ovr + * @details override + * @{ + */ +#define PMU_PMU14__PINEDGE_EN_OVR__SHIFT 22 +#define PMU_PMU14__PINEDGE_EN_OVR__WIDTH 1 +#define PMU_PMU14__PINEDGE_EN_OVR__MASK 0x00400000U +#define PMU_PMU14__PINEDGE_EN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define PMU_PMU14__PINEDGE_EN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define PMU_PMU14__PINEDGE_EN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define PMU_PMU14__PINEDGE_EN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define PMU_PMU14__PINEDGE_EN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define PMU_PMU14__PINEDGE_EN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define PMU_PMU14__PINEDGE_EN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pinedge_en_ovr_val */ +/** + * @defgroup pmu_top_regs_core_pinedge_en_ovr_val_field pinedge_en_ovr_val_field + * @brief macros for field pinedge_en_ovr_val + * @details override val + * @{ + */ +#define PMU_PMU14__PINEDGE_EN_OVR_VAL__SHIFT 23 +#define PMU_PMU14__PINEDGE_EN_OVR_VAL__WIDTH 1 +#define PMU_PMU14__PINEDGE_EN_OVR_VAL__MASK 0x00800000U +#define PMU_PMU14__PINEDGE_EN_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PMU_PMU14__PINEDGE_EN_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define PMU_PMU14__PINEDGE_EN_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define PMU_PMU14__PINEDGE_EN_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define PMU_PMU14__PINEDGE_EN_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PMU_PMU14__PINEDGE_EN_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PMU_PMU14__PINEDGE_EN_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_5Vldo_ovr */ +/** + * @defgroup pmu_top_regs_core_en_5Vldo_ovr_field en_5Vldo_ovr_field + * @brief macros for field en_5Vldo_ovr + * @details override en_5Vldo + * @{ + */ +#define PMU_PMU14__EN_5VLDO_OVR__SHIFT 24 +#define PMU_PMU14__EN_5VLDO_OVR__WIDTH 1 +#define PMU_PMU14__EN_5VLDO_OVR__MASK 0x01000000U +#define PMU_PMU14__EN_5VLDO_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define PMU_PMU14__EN_5VLDO_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define PMU_PMU14__EN_5VLDO_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define PMU_PMU14__EN_5VLDO_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define PMU_PMU14__EN_5VLDO_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define PMU_PMU14__EN_5VLDO_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define PMU_PMU14__EN_5VLDO_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_5Vldo_ovr_val */ +/** + * @defgroup pmu_top_regs_core_en_5Vldo_ovr_val_field en_5Vldo_ovr_val_field + * @brief macros for field en_5Vldo_ovr_val + * @details override en_5Vldo val: Enable 5LI LDO + * @{ + */ +#define PMU_PMU14__EN_5VLDO_OVR_VAL__SHIFT 25 +#define PMU_PMU14__EN_5VLDO_OVR_VAL__WIDTH 1 +#define PMU_PMU14__EN_5VLDO_OVR_VAL__MASK 0x02000000U +#define PMU_PMU14__EN_5VLDO_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define PMU_PMU14__EN_5VLDO_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define PMU_PMU14__EN_5VLDO_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define PMU_PMU14__EN_5VLDO_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define PMU_PMU14__EN_5VLDO_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define PMU_PMU14__EN_5VLDO_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define PMU_PMU14__EN_5VLDO_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_swResVbat_ovr */ +/** + * @defgroup pmu_top_regs_core_en_swResVbat_ovr_field en_swResVbat_ovr_field + * @brief macros for field en_swResVbat_ovr + * @details override en_swResVbat + * @{ + */ +#define PMU_PMU14__EN_SWRESVBAT_OVR__SHIFT 26 +#define PMU_PMU14__EN_SWRESVBAT_OVR__WIDTH 1 +#define PMU_PMU14__EN_SWRESVBAT_OVR__MASK 0x04000000U +#define PMU_PMU14__EN_SWRESVBAT_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define PMU_PMU14__EN_SWRESVBAT_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define PMU_PMU14__EN_SWRESVBAT_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define PMU_PMU14__EN_SWRESVBAT_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define PMU_PMU14__EN_SWRESVBAT_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define PMU_PMU14__EN_SWRESVBAT_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define PMU_PMU14__EN_SWRESVBAT_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_swResVbat_ovr_val */ +/** + * @defgroup pmu_top_regs_core_en_swResVbat_ovr_val_field en_swResVbat_ovr_val_field + * @brief macros for field en_swResVbat_ovr_val + * @details override en_swResVbat val: Enable VBATLI to VBAT swres + * @{ + */ +#define PMU_PMU14__EN_SWRESVBAT_OVR_VAL__SHIFT 27 +#define PMU_PMU14__EN_SWRESVBAT_OVR_VAL__WIDTH 1 +#define PMU_PMU14__EN_SWRESVBAT_OVR_VAL__MASK 0x08000000U +#define PMU_PMU14__EN_SWRESVBAT_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define PMU_PMU14__EN_SWRESVBAT_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define PMU_PMU14__EN_SWRESVBAT_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define PMU_PMU14__EN_SWRESVBAT_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define PMU_PMU14__EN_SWRESVBAT_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define PMU_PMU14__EN_SWRESVBAT_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define PMU_PMU14__EN_SWRESVBAT_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_ref_5Vldo_ovr */ +/** + * @defgroup pmu_top_regs_core_ctr_ref_5Vldo_ovr_field ctr_ref_5Vldo_ovr_field + * @brief macros for field ctr_ref_5Vldo_ovr + * @details override ctr_ref_5Vldo + * @{ + */ +#define PMU_PMU14__CTR_REF_5VLDO_OVR__SHIFT 28 +#define PMU_PMU14__CTR_REF_5VLDO_OVR__WIDTH 1 +#define PMU_PMU14__CTR_REF_5VLDO_OVR__MASK 0x10000000U +#define PMU_PMU14__CTR_REF_5VLDO_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define PMU_PMU14__CTR_REF_5VLDO_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define PMU_PMU14__CTR_REF_5VLDO_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define PMU_PMU14__CTR_REF_5VLDO_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define PMU_PMU14__CTR_REF_5VLDO_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define PMU_PMU14__CTR_REF_5VLDO_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define PMU_PMU14__CTR_REF_5VLDO_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_ref_5Vldo_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ctr_ref_5Vldo_ovr_val_field ctr_ref_5Vldo_ovr_val_field + * @brief macros for field ctr_ref_5Vldo_ovr_val + * @details override ctr_ref_5Vldo val0: Locally generated reference from 5LI domain1: refgen reference for 5LI VBAT LDO reference + * @{ + */ +#define PMU_PMU14__CTR_REF_5VLDO_OVR_VAL__SHIFT 29 +#define PMU_PMU14__CTR_REF_5VLDO_OVR_VAL__WIDTH 1 +#define PMU_PMU14__CTR_REF_5VLDO_OVR_VAL__MASK 0x20000000U +#define PMU_PMU14__CTR_REF_5VLDO_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define PMU_PMU14__CTR_REF_5VLDO_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define PMU_PMU14__CTR_REF_5VLDO_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define PMU_PMU14__CTR_REF_5VLDO_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define PMU_PMU14__CTR_REF_5VLDO_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define PMU_PMU14__CTR_REF_5VLDO_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define PMU_PMU14__CTR_REF_5VLDO_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field buck_store_batt */ +/** + * @defgroup pmu_top_regs_core_buck_store_batt_field buck_store_batt_field + * @brief macros for field buck_store_batt + * @details use sw to change to buck (paris2) + * @{ + */ +#define PMU_PMU14__BUCK_STORE_BATT__SHIFT 30 +#define PMU_PMU14__BUCK_STORE_BATT__WIDTH 1 +#define PMU_PMU14__BUCK_STORE_BATT__MASK 0x40000000U +#define PMU_PMU14__BUCK_STORE_BATT__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define PMU_PMU14__BUCK_STORE_BATT__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define PMU_PMU14__BUCK_STORE_BATT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define PMU_PMU14__BUCK_STORE_BATT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define PMU_PMU14__BUCK_STORE_BATT__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define PMU_PMU14__BUCK_STORE_BATT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define PMU_PMU14__BUCK_STORE_BATT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field boost_store_batt */ +/** + * @defgroup pmu_top_regs_core_boost_store_batt_field boost_store_batt_field + * @brief macros for field boost_store_batt + * @details use sw to change to boost (paris2) + * @{ + */ +#define PMU_PMU14__BOOST_STORE_BATT__SHIFT 31 +#define PMU_PMU14__BOOST_STORE_BATT__WIDTH 1 +#define PMU_PMU14__BOOST_STORE_BATT__MASK 0x80000000U +#define PMU_PMU14__BOOST_STORE_BATT__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define PMU_PMU14__BOOST_STORE_BATT__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define PMU_PMU14__BOOST_STORE_BATT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define PMU_PMU14__BOOST_STORE_BATT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define PMU_PMU14__BOOST_STORE_BATT__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PMU_PMU14__BOOST_STORE_BATT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PMU_PMU14__BOOST_STORE_BATT__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU14__TYPE uint32_t +#define PMU_PMU14__READ 0xffffffffU +#define PMU_PMU14__WRITE 0xffffffffU +#define PMU_PMU14__PRESERVED 0x00000000U +#define PMU_PMU14__RESET_VALUE 0x00200020U + +#endif /* __PMU_PMU14_MACRO__ */ + +/** @} end of pmu14 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu14a */ +/** + * @defgroup pmu_top_regs_core_pmu14a pmu14a + * @brief ldo overrides definitions. + * @{ + */ +#ifndef __PMU_PMU14A_MACRO__ +#define __PMU_PMU14A_MACRO__ + +/* macros for field en_ldoL1dvdd_ovr */ +/** + * @defgroup pmu_top_regs_core_en_ldoL1dvdd_ovr_field en_ldoL1dvdd_ovr_field + * @brief macros for field en_ldoL1dvdd_ovr + * @details override en_ldoL1dvdd + * @{ + */ +#define PMU_PMU14A__EN_LDOL1DVDD_OVR__SHIFT 0 +#define PMU_PMU14A__EN_LDOL1DVDD_OVR__WIDTH 1 +#define PMU_PMU14A__EN_LDOL1DVDD_OVR__MASK 0x00000001U +#define PMU_PMU14A__EN_LDOL1DVDD_OVR__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PMU_PMU14A__EN_LDOL1DVDD_OVR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PMU_PMU14A__EN_LDOL1DVDD_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PMU_PMU14A__EN_LDOL1DVDD_OVR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PMU_PMU14A__EN_LDOL1DVDD_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PMU_PMU14A__EN_LDOL1DVDD_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PMU_PMU14A__EN_LDOL1DVDD_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_ldoL1dvdd_ovr_val */ +/** + * @defgroup pmu_top_regs_core_en_ldoL1dvdd_ovr_val_field en_ldoL1dvdd_ovr_val_field + * @brief macros for field en_ldoL1dvdd_ovr_val + * @details override en_ldoL1dvdd val: Enable L1 dvdd LDO + * @{ + */ +#define PMU_PMU14A__EN_LDOL1DVDD_OVR_VAL__SHIFT 1 +#define PMU_PMU14A__EN_LDOL1DVDD_OVR_VAL__WIDTH 1 +#define PMU_PMU14A__EN_LDOL1DVDD_OVR_VAL__MASK 0x00000002U +#define PMU_PMU14A__EN_LDOL1DVDD_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PMU_PMU14A__EN_LDOL1DVDD_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PMU_PMU14A__EN_LDOL1DVDD_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PMU_PMU14A__EN_LDOL1DVDD_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PMU_PMU14A__EN_LDOL1DVDD_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PMU_PMU14A__EN_LDOL1DVDD_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PMU_PMU14A__EN_LDOL1DVDD_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_ldoL1vddio_ovr */ +/** + * @defgroup pmu_top_regs_core_en_ldoL1vddio_ovr_field en_ldoL1vddio_ovr_field + * @brief macros for field en_ldoL1vddio_ovr + * @details override en_ldoL1vddio + * @{ + */ +#define PMU_PMU14A__EN_LDOL1VDDIO_OVR__SHIFT 2 +#define PMU_PMU14A__EN_LDOL1VDDIO_OVR__WIDTH 1 +#define PMU_PMU14A__EN_LDOL1VDDIO_OVR__MASK 0x00000004U +#define PMU_PMU14A__EN_LDOL1VDDIO_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PMU_PMU14A__EN_LDOL1VDDIO_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PMU_PMU14A__EN_LDOL1VDDIO_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PMU_PMU14A__EN_LDOL1VDDIO_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PMU_PMU14A__EN_LDOL1VDDIO_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PMU_PMU14A__EN_LDOL1VDDIO_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PMU_PMU14A__EN_LDOL1VDDIO_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_ldoL1vddio_ovr_val */ +/** + * @defgroup pmu_top_regs_core_en_ldoL1vddio_ovr_val_field en_ldoL1vddio_ovr_val_field + * @brief macros for field en_ldoL1vddio_ovr_val + * @details override en_ldoL1vddio val: Enable L1 vddio LDO + * @{ + */ +#define PMU_PMU14A__EN_LDOL1VDDIO_OVR_VAL__SHIFT 3 +#define PMU_PMU14A__EN_LDOL1VDDIO_OVR_VAL__WIDTH 1 +#define PMU_PMU14A__EN_LDOL1VDDIO_OVR_VAL__MASK 0x00000008U +#define PMU_PMU14A__EN_LDOL1VDDIO_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define PMU_PMU14A__EN_LDOL1VDDIO_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define PMU_PMU14A__EN_LDOL1VDDIO_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define PMU_PMU14A__EN_LDOL1VDDIO_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define PMU_PMU14A__EN_LDOL1VDDIO_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define PMU_PMU14A__EN_LDOL1VDDIO_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define PMU_PMU14A__EN_LDOL1VDDIO_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_ldoL1avdd_ovr */ +/** + * @defgroup pmu_top_regs_core_en_ldoL1avdd_ovr_field en_ldoL1avdd_ovr_field + * @brief macros for field en_ldoL1avdd_ovr + * @details override en_ldoL1avdd + * @{ + */ +#define PMU_PMU14A__EN_LDOL1AVDD_OVR__SHIFT 4 +#define PMU_PMU14A__EN_LDOL1AVDD_OVR__WIDTH 1 +#define PMU_PMU14A__EN_LDOL1AVDD_OVR__MASK 0x00000010U +#define PMU_PMU14A__EN_LDOL1AVDD_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define PMU_PMU14A__EN_LDOL1AVDD_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define PMU_PMU14A__EN_LDOL1AVDD_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define PMU_PMU14A__EN_LDOL1AVDD_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define PMU_PMU14A__EN_LDOL1AVDD_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define PMU_PMU14A__EN_LDOL1AVDD_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define PMU_PMU14A__EN_LDOL1AVDD_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_ldoL1avdd_ovr_val */ +/** + * @defgroup pmu_top_regs_core_en_ldoL1avdd_ovr_val_field en_ldoL1avdd_ovr_val_field + * @brief macros for field en_ldoL1avdd_ovr_val + * @details override en_ldoL1avdd val: Enable L1 avdd LDO + * @{ + */ +#define PMU_PMU14A__EN_LDOL1AVDD_OVR_VAL__SHIFT 5 +#define PMU_PMU14A__EN_LDOL1AVDD_OVR_VAL__WIDTH 1 +#define PMU_PMU14A__EN_LDOL1AVDD_OVR_VAL__MASK 0x00000020U +#define PMU_PMU14A__EN_LDOL1AVDD_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define PMU_PMU14A__EN_LDOL1AVDD_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define PMU_PMU14A__EN_LDOL1AVDD_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define PMU_PMU14A__EN_LDOL1AVDD_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define PMU_PMU14A__EN_LDOL1AVDD_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define PMU_PMU14A__EN_LDOL1AVDD_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define PMU_PMU14A__EN_LDOL1AVDD_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mppt_test_state_ovr_val */ +/** + * @defgroup pmu_top_regs_core_mppt_test_state_ovr_val_field mppt_test_state_ovr_val_field + * @brief macros for field mppt_test_state_ovr_val + * @details mppt test state + * @{ + */ +#define PMU_PMU14A__MPPT_TEST_STATE_OVR_VAL__SHIFT 6 +#define PMU_PMU14A__MPPT_TEST_STATE_OVR_VAL__WIDTH 4 +#define PMU_PMU14A__MPPT_TEST_STATE_OVR_VAL__MASK 0x000003c0U +#define PMU_PMU14A__MPPT_TEST_STATE_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x000003c0U) >> 6) +#define PMU_PMU14A__MPPT_TEST_STATE_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000003c0U) +#define PMU_PMU14A__MPPT_TEST_STATE_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003c0U) | (((uint32_t)(src) <<\ + 6) & 0x000003c0U) +#define PMU_PMU14A__MPPT_TEST_STATE_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000003c0U))) +#define PMU_PMU14A__MPPT_TEST_STATE_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mppt_test_state_ovr */ +/** + * @defgroup pmu_top_regs_core_mppt_test_state_ovr_field mppt_test_state_ovr_field + * @brief macros for field mppt_test_state_ovr + * @details ovr value for mppt test state + * @{ + */ +#define PMU_PMU14A__MPPT_TEST_STATE_OVR__SHIFT 10 +#define PMU_PMU14A__MPPT_TEST_STATE_OVR__WIDTH 1 +#define PMU_PMU14A__MPPT_TEST_STATE_OVR__MASK 0x00000400U +#define PMU_PMU14A__MPPT_TEST_STATE_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define PMU_PMU14A__MPPT_TEST_STATE_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define PMU_PMU14A__MPPT_TEST_STATE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define PMU_PMU14A__MPPT_TEST_STATE_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define PMU_PMU14A__MPPT_TEST_STATE_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define PMU_PMU14A__MPPT_TEST_STATE_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define PMU_PMU14A__MPPT_TEST_STATE_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_mustharvfa_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ctr_mustharvfa_ovr_val_field ctr_mustharvfa_ovr_val_field + * @brief macros for field ctr_mustharvfa_ovr_val + * @details override ctr_mustharvfa val: fast refgen tap selection for mustharv regulation + * @{ + */ +#define PMU_PMU14A__CTR_MUSTHARVFA_OVR_VAL__SHIFT 11 +#define PMU_PMU14A__CTR_MUSTHARVFA_OVR_VAL__WIDTH 4 +#define PMU_PMU14A__CTR_MUSTHARVFA_OVR_VAL__MASK 0x00007800U +#define PMU_PMU14A__CTR_MUSTHARVFA_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00007800U) >> 11) +#define PMU_PMU14A__CTR_MUSTHARVFA_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00007800U) +#define PMU_PMU14A__CTR_MUSTHARVFA_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007800U) | (((uint32_t)(src) <<\ + 11) & 0x00007800U) +#define PMU_PMU14A__CTR_MUSTHARVFA_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00007800U))) +#define PMU_PMU14A__CTR_MUSTHARVFA_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_mustharvfa_ovr */ +/** + * @defgroup pmu_top_regs_core_ctr_mustharvfa_ovr_field ctr_mustharvfa_ovr_field + * @brief macros for field ctr_mustharvfa_ovr + * @details override ctr_mustharvfa + * @{ + */ +#define PMU_PMU14A__CTR_MUSTHARVFA_OVR__SHIFT 15 +#define PMU_PMU14A__CTR_MUSTHARVFA_OVR__WIDTH 1 +#define PMU_PMU14A__CTR_MUSTHARVFA_OVR__MASK 0x00008000U +#define PMU_PMU14A__CTR_MUSTHARVFA_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define PMU_PMU14A__CTR_MUSTHARVFA_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define PMU_PMU14A__CTR_MUSTHARVFA_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define PMU_PMU14A__CTR_MUSTHARVFA_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define PMU_PMU14A__CTR_MUSTHARVFA_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PMU_PMU14A__CTR_MUSTHARVFA_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PMU_PMU14A__CTR_MUSTHARVFA_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_mustharvsl_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ctr_mustharvsl_ovr_val_field ctr_mustharvsl_ovr_val_field + * @brief macros for field ctr_mustharvsl_ovr_val + * @details override ctr_mustharvsl val: refgen tap selection for mustharv regulation + * @{ + */ +#define PMU_PMU14A__CTR_MUSTHARVSL_OVR_VAL__SHIFT 16 +#define PMU_PMU14A__CTR_MUSTHARVSL_OVR_VAL__WIDTH 4 +#define PMU_PMU14A__CTR_MUSTHARVSL_OVR_VAL__MASK 0x000f0000U +#define PMU_PMU14A__CTR_MUSTHARVSL_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x000f0000U) >> 16) +#define PMU_PMU14A__CTR_MUSTHARVSL_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x000f0000U) +#define PMU_PMU14A__CTR_MUSTHARVSL_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((uint32_t)(src) <<\ + 16) & 0x000f0000U) +#define PMU_PMU14A__CTR_MUSTHARVSL_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x000f0000U))) +#define PMU_PMU14A__CTR_MUSTHARVSL_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_mustharvsl_ovr */ +/** + * @defgroup pmu_top_regs_core_ctr_mustharvsl_ovr_field ctr_mustharvsl_ovr_field + * @brief macros for field ctr_mustharvsl_ovr + * @details override ctr_mustharvsl + * @{ + */ +#define PMU_PMU14A__CTR_MUSTHARVSL_OVR__SHIFT 20 +#define PMU_PMU14A__CTR_MUSTHARVSL_OVR__WIDTH 1 +#define PMU_PMU14A__CTR_MUSTHARVSL_OVR__MASK 0x00100000U +#define PMU_PMU14A__CTR_MUSTHARVSL_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define PMU_PMU14A__CTR_MUSTHARVSL_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define PMU_PMU14A__CTR_MUSTHARVSL_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define PMU_PMU14A__CTR_MUSTHARVSL_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define PMU_PMU14A__CTR_MUSTHARVSL_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define PMU_PMU14A__CTR_MUSTHARVSL_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define PMU_PMU14A__CTR_MUSTHARVSL_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_mustharvfastsel_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ctr_mustharvfastsel_ovr_val_field ctr_mustharvfastsel_ovr_val_field + * @brief macros for field ctr_mustharvfastsel_ovr_val + * @details override ctr_mustharvfastsel val: select fast refgen instead of refgen for mustharv regulation + * @{ + */ +#define PMU_PMU14A__CTR_MUSTHARVFASTSEL_OVR_VAL__SHIFT 21 +#define PMU_PMU14A__CTR_MUSTHARVFASTSEL_OVR_VAL__WIDTH 1 +#define PMU_PMU14A__CTR_MUSTHARVFASTSEL_OVR_VAL__MASK 0x00200000U +#define PMU_PMU14A__CTR_MUSTHARVFASTSEL_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define PMU_PMU14A__CTR_MUSTHARVFASTSEL_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define PMU_PMU14A__CTR_MUSTHARVFASTSEL_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define PMU_PMU14A__CTR_MUSTHARVFASTSEL_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define PMU_PMU14A__CTR_MUSTHARVFASTSEL_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define PMU_PMU14A__CTR_MUSTHARVFASTSEL_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define PMU_PMU14A__CTR_MUSTHARVFASTSEL_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_mustharvfastsel_ovr */ +/** + * @defgroup pmu_top_regs_core_ctr_mustharvfastsel_ovr_field ctr_mustharvfastsel_ovr_field + * @brief macros for field ctr_mustharvfastsel_ovr + * @details override ctr_mustharvfastsel + * @{ + */ +#define PMU_PMU14A__CTR_MUSTHARVFASTSEL_OVR__SHIFT 22 +#define PMU_PMU14A__CTR_MUSTHARVFASTSEL_OVR__WIDTH 1 +#define PMU_PMU14A__CTR_MUSTHARVFASTSEL_OVR__MASK 0x00400000U +#define PMU_PMU14A__CTR_MUSTHARVFASTSEL_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define PMU_PMU14A__CTR_MUSTHARVFASTSEL_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define PMU_PMU14A__CTR_MUSTHARVFASTSEL_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define PMU_PMU14A__CTR_MUSTHARVFASTSEL_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define PMU_PMU14A__CTR_MUSTHARVFASTSEL_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define PMU_PMU14A__CTR_MUSTHARVFASTSEL_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define PMU_PMU14A__CTR_MUSTHARVFASTSEL_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_refcurr1u_ovr */ +/** + * @defgroup pmu_top_regs_core_en_refcurr1u_ovr_field en_refcurr1u_ovr_field + * @brief macros for field en_refcurr1u_ovr + * @details override en_refcurr1u + * @{ + */ +#define PMU_PMU14A__EN_REFCURR1U_OVR__SHIFT 23 +#define PMU_PMU14A__EN_REFCURR1U_OVR__WIDTH 1 +#define PMU_PMU14A__EN_REFCURR1U_OVR__MASK 0x00800000U +#define PMU_PMU14A__EN_REFCURR1U_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PMU_PMU14A__EN_REFCURR1U_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define PMU_PMU14A__EN_REFCURR1U_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define PMU_PMU14A__EN_REFCURR1U_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define PMU_PMU14A__EN_REFCURR1U_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PMU_PMU14A__EN_REFCURR1U_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PMU_PMU14A__EN_REFCURR1U_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_refcurr1u_ovr_val */ +/** + * @defgroup pmu_top_regs_core_en_refcurr1u_ovr_val_field en_refcurr1u_ovr_val_field + * @brief macros for field en_refcurr1u_ovr_val + * @details override en_refcurr1u val: Enable the 1uA current reference + * @{ + */ +#define PMU_PMU14A__EN_REFCURR1U_OVR_VAL__SHIFT 24 +#define PMU_PMU14A__EN_REFCURR1U_OVR_VAL__WIDTH 1 +#define PMU_PMU14A__EN_REFCURR1U_OVR_VAL__MASK 0x01000000U +#define PMU_PMU14A__EN_REFCURR1U_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define PMU_PMU14A__EN_REFCURR1U_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define PMU_PMU14A__EN_REFCURR1U_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define PMU_PMU14A__EN_REFCURR1U_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define PMU_PMU14A__EN_REFCURR1U_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define PMU_PMU14A__EN_REFCURR1U_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define PMU_PMU14A__EN_REFCURR1U_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_harvst_ovr */ +/** + * @defgroup pmu_top_regs_core_ctr_harvst_ovr_field ctr_harvst_ovr_field + * @brief macros for field ctr_harvst_ovr + * @details override ctr_harvst + * @{ + */ +#define PMU_PMU14A__CTR_HARVST_OVR__SHIFT 25 +#define PMU_PMU14A__CTR_HARVST_OVR__WIDTH 1 +#define PMU_PMU14A__CTR_HARVST_OVR__MASK 0x02000000U +#define PMU_PMU14A__CTR_HARVST_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define PMU_PMU14A__CTR_HARVST_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define PMU_PMU14A__CTR_HARVST_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define PMU_PMU14A__CTR_HARVST_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define PMU_PMU14A__CTR_HARVST_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define PMU_PMU14A__CTR_HARVST_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define PMU_PMU14A__CTR_HARVST_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_harvst_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ctr_harvst_ovr_val_field ctr_harvst_ovr_val_field + * @brief macros for field ctr_harvst_ovr_val + * @details override ctr_harvst val: Select the mustharv regulation level at cold start while vaux ramps upSelects the Vrefharv075 referenceVharv regulated at: 25 * (48,29,21,14)/0.75 + * @{ + */ +#define PMU_PMU14A__CTR_HARVST_OVR_VAL__SHIFT 26 +#define PMU_PMU14A__CTR_HARVST_OVR_VAL__WIDTH 2 +#define PMU_PMU14A__CTR_HARVST_OVR_VAL__MASK 0x0c000000U +#define PMU_PMU14A__CTR_HARVST_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x0c000000U) >> 26) +#define PMU_PMU14A__CTR_HARVST_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x0c000000U) +#define PMU_PMU14A__CTR_HARVST_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((uint32_t)(src) <<\ + 26) & 0x0c000000U) +#define PMU_PMU14A__CTR_HARVST_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x0c000000U))) +#define PMU_PMU14A__CTR_HARVST_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_chrg_ovr */ +/** + * @defgroup pmu_top_regs_core_en_chrg_ovr_field en_chrg_ovr_field + * @brief macros for field en_chrg_ovr + * @details override en_chrg + * @{ + */ +#define PMU_PMU14A__EN_CHRG_OVR__SHIFT 28 +#define PMU_PMU14A__EN_CHRG_OVR__WIDTH 1 +#define PMU_PMU14A__EN_CHRG_OVR__MASK 0x10000000U +#define PMU_PMU14A__EN_CHRG_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define PMU_PMU14A__EN_CHRG_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define PMU_PMU14A__EN_CHRG_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define PMU_PMU14A__EN_CHRG_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define PMU_PMU14A__EN_CHRG_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define PMU_PMU14A__EN_CHRG_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define PMU_PMU14A__EN_CHRG_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_chrg_ovr_val */ +/** + * @defgroup pmu_top_regs_core_en_chrg_ovr_val_field en_chrg_ovr_val_field + * @brief macros for field en_chrg_ovr_val + * @details override en_chrg val: Enables the VSTO->VBAT charger + * @{ + */ +#define PMU_PMU14A__EN_CHRG_OVR_VAL__SHIFT 29 +#define PMU_PMU14A__EN_CHRG_OVR_VAL__WIDTH 1 +#define PMU_PMU14A__EN_CHRG_OVR_VAL__MASK 0x20000000U +#define PMU_PMU14A__EN_CHRG_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define PMU_PMU14A__EN_CHRG_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define PMU_PMU14A__EN_CHRG_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define PMU_PMU14A__EN_CHRG_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define PMU_PMU14A__EN_CHRG_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define PMU_PMU14A__EN_CHRG_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define PMU_PMU14A__EN_CHRG_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_scaleEnerg */ +/** + * @defgroup pmu_top_regs_core_override_scaleEnerg_field override_scaleEnerg_field + * @brief macros for field override_scaleEnerg + * @details overrides the scaleEnerg from pmuadc with that of reg_scaleEnerg + * @{ + */ +#define PMU_PMU14A__OVERRIDE_SCALEENERG__SHIFT 30 +#define PMU_PMU14A__OVERRIDE_SCALEENERG__WIDTH 1 +#define PMU_PMU14A__OVERRIDE_SCALEENERG__MASK 0x40000000U +#define PMU_PMU14A__OVERRIDE_SCALEENERG__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define PMU_PMU14A__OVERRIDE_SCALEENERG__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define PMU_PMU14A__OVERRIDE_SCALEENERG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define PMU_PMU14A__OVERRIDE_SCALEENERG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define PMU_PMU14A__OVERRIDE_SCALEENERG__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define PMU_PMU14A__OVERRIDE_SCALEENERG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define PMU_PMU14A__OVERRIDE_SCALEENERG__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU14A__TYPE uint32_t +#define PMU_PMU14A__READ 0x7fffffffU +#define PMU_PMU14A__WRITE 0x7fffffffU +#define PMU_PMU14A__PRESERVED 0x00000000U +#define PMU_PMU14A__RESET_VALUE 0x00000000U + +#endif /* __PMU_PMU14A_MACRO__ */ + +/** @} end of pmu14a */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu14b */ +/** + * @defgroup pmu_top_regs_core_pmu14b pmu14b + * @brief mppt regs definitions. + * @{ + */ +#ifndef __PMU_PMU14B_MACRO__ +#define __PMU_PMU14B_MACRO__ + +/* macros for field mpptEventsTarget_reg */ +/** + * @defgroup pmu_top_regs_core_mpptEventsTarget_reg_field mpptEventsTarget_reg_field + * @brief macros for field mpptEventsTarget_reg + * @details number of events within the measured number of periods during GET_PERIODCNT + * @{ + */ +#define PMU_PMU14B__MPPTEVENTSTARGET_REG__SHIFT 0 +#define PMU_PMU14B__MPPTEVENTSTARGET_REG__WIDTH 10 +#define PMU_PMU14B__MPPTEVENTSTARGET_REG__MASK 0x000003ffU +#define PMU_PMU14B__MPPTEVENTSTARGET_REG__READ(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define PMU_PMU14B__MPPTEVENTSTARGET_REG__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define PMU_PMU14B__MPPTEVENTSTARGET_REG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define PMU_PMU14B__MPPTEVENTSTARGET_REG__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define PMU_PMU14B__MPPTEVENTSTARGET_REG__RESET_VALUE 0x000000c8U +/** @} */ + +/* macros for field mpptPeriodCnt_max */ +/** + * @defgroup pmu_top_regs_core_mpptPeriodCnt_max_field mpptPeriodCnt_max_field + * @brief macros for field mpptPeriodCnt_max + * @details upper limit on measured number of periods during GET_PERIODCNT + * @{ + */ +#define PMU_PMU14B__MPPTPERIODCNT_MAX__SHIFT 10 +#define PMU_PMU14B__MPPTPERIODCNT_MAX__WIDTH 10 +#define PMU_PMU14B__MPPTPERIODCNT_MAX__MASK 0x000ffc00U +#define PMU_PMU14B__MPPTPERIODCNT_MAX__READ(src) \ + (((uint32_t)(src)\ + & 0x000ffc00U) >> 10) +#define PMU_PMU14B__MPPTPERIODCNT_MAX__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x000ffc00U) +#define PMU_PMU14B__MPPTPERIODCNT_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define PMU_PMU14B__MPPTPERIODCNT_MAX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define PMU_PMU14B__MPPTPERIODCNT_MAX__RESET_VALUE 0x00000320U +/** @} */ + +/* macros for field ref_settle_cnt */ +/** + * @defgroup pmu_top_regs_core_ref_settle_cnt_field ref_settle_cnt_field + * @brief macros for field ref_settle_cnt + * @details settling time of fast refgen when the reference is changed + * @{ + */ +#define PMU_PMU14B__REF_SETTLE_CNT__SHIFT 20 +#define PMU_PMU14B__REF_SETTLE_CNT__WIDTH 3 +#define PMU_PMU14B__REF_SETTLE_CNT__MASK 0x00700000U +#define PMU_PMU14B__REF_SETTLE_CNT__READ(src) \ + (((uint32_t)(src)\ + & 0x00700000U) >> 20) +#define PMU_PMU14B__REF_SETTLE_CNT__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00700000U) +#define PMU_PMU14B__REF_SETTLE_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((uint32_t)(src) <<\ + 20) & 0x00700000U) +#define PMU_PMU14B__REF_SETTLE_CNT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00700000U))) +#define PMU_PMU14B__REF_SETTLE_CNT__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field EventsCnt_thr */ +/** + * @defgroup pmu_top_regs_core_EventsCnt_thr_field EventsCnt_thr_field + * @brief macros for field EventsCnt_thr + * @details event threshold to recalculate optimum Vharv during MPPT_TRACK + * @{ + */ +#define PMU_PMU14B__EVENTSCNT_THR__SHIFT 23 +#define PMU_PMU14B__EVENTSCNT_THR__WIDTH 5 +#define PMU_PMU14B__EVENTSCNT_THR__MASK 0x0f800000U +#define PMU_PMU14B__EVENTSCNT_THR__READ(src) \ + (((uint32_t)(src)\ + & 0x0f800000U) >> 23) +#define PMU_PMU14B__EVENTSCNT_THR__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x0f800000U) +#define PMU_PMU14B__EVENTSCNT_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f800000U) | (((uint32_t)(src) <<\ + 23) & 0x0f800000U) +#define PMU_PMU14B__EVENTSCNT_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x0f800000U))) +#define PMU_PMU14B__EVENTSCNT_THR__RESET_VALUE 0x00000014U +/** @} */ + +/* macros for field swResavddldo_ctr */ +/** + * @defgroup pmu_top_regs_core_swResavddldo_ctr_field swResavddldo_ctr_field + * @brief macros for field swResavddldo_ctr + * @details control L2 avdd swres resistance, 0:200k, 1:100k + * @{ + */ +#define PMU_PMU14B__SWRESAVDDLDO_CTR__SHIFT 28 +#define PMU_PMU14B__SWRESAVDDLDO_CTR__WIDTH 1 +#define PMU_PMU14B__SWRESAVDDLDO_CTR__MASK 0x10000000U +#define PMU_PMU14B__SWRESAVDDLDO_CTR__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define PMU_PMU14B__SWRESAVDDLDO_CTR__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define PMU_PMU14B__SWRESAVDDLDO_CTR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define PMU_PMU14B__SWRESAVDDLDO_CTR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define PMU_PMU14B__SWRESAVDDLDO_CTR__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define PMU_PMU14B__SWRESAVDDLDO_CTR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define PMU_PMU14B__SWRESAVDDLDO_CTR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ovr_bypstop */ +/** + * @defgroup pmu_top_regs_core_ovr_bypstop_field ovr_bypstop_field + * @brief macros for field ovr_bypstop + * @details For L1 LDO bypass mode1: prevent disabling the bypass when a high load current is detected0: allow the high current protection disable the bypass + * @{ + */ +#define PMU_PMU14B__OVR_BYPSTOP__SHIFT 29 +#define PMU_PMU14B__OVR_BYPSTOP__WIDTH 1 +#define PMU_PMU14B__OVR_BYPSTOP__MASK 0x20000000U +#define PMU_PMU14B__OVR_BYPSTOP__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define PMU_PMU14B__OVR_BYPSTOP__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define PMU_PMU14B__OVR_BYPSTOP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define PMU_PMU14B__OVR_BYPSTOP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define PMU_PMU14B__OVR_BYPSTOP__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define PMU_PMU14B__OVR_BYPSTOP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define PMU_PMU14B__OVR_BYPSTOP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enableHarv2Sup_active_reg */ +/** + * @defgroup pmu_top_regs_core_enableHarv2Sup_active_reg_field enableHarv2Sup_active_reg_field + * @brief macros for field enableHarv2Sup_active_reg + * @details sw can program whether in active we disable harv2sup or not0: Allow only Vstore to load in active if the load is very high1: Allow also Vharv to load in active to avoid double conversion loss + * @{ + */ +#define PMU_PMU14B__ENABLEHARV2SUP_ACTIVE_REG__SHIFT 30 +#define PMU_PMU14B__ENABLEHARV2SUP_ACTIVE_REG__WIDTH 1 +#define PMU_PMU14B__ENABLEHARV2SUP_ACTIVE_REG__MASK 0x40000000U +#define PMU_PMU14B__ENABLEHARV2SUP_ACTIVE_REG__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define PMU_PMU14B__ENABLEHARV2SUP_ACTIVE_REG__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define PMU_PMU14B__ENABLEHARV2SUP_ACTIVE_REG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define PMU_PMU14B__ENABLEHARV2SUP_ACTIVE_REG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define PMU_PMU14B__ENABLEHARV2SUP_ACTIVE_REG__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define PMU_PMU14B__ENABLEHARV2SUP_ACTIVE_REG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define PMU_PMU14B__ENABLEHARV2SUP_ACTIVE_REG__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU14B__TYPE uint32_t +#define PMU_PMU14B__READ 0x7fffffffU +#define PMU_PMU14B__WRITE 0x7fffffffU +#define PMU_PMU14B__PRESERVED 0x00000000U +#define PMU_PMU14B__RESET_VALUE 0x0a4c80c8U + +#endif /* __PMU_PMU14B_MACRO__ */ + +/** @} end of pmu14b */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu14c */ +/** + * @defgroup pmu_top_regs_core_pmu14c pmu14c + * @brief more mppt regs definitions. + * @{ + */ +#ifndef __PMU_PMU14C_MACRO__ +#define __PMU_PMU14C_MACRO__ + +/* macros for field idle_cnt */ +/** + * @defgroup pmu_top_regs_core_idle_cnt_field idle_cnt_field + * @brief macros for field idle_cnt + * @details how many cycles to wait in idle before running mppt tracking, {idle_cnt,8'd0} + * @{ + */ +#define PMU_PMU14C__IDLE_CNT__SHIFT 0 +#define PMU_PMU14C__IDLE_CNT__WIDTH 10 +#define PMU_PMU14C__IDLE_CNT__MASK 0x000003ffU +#define PMU_PMU14C__IDLE_CNT__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define PMU_PMU14C__IDLE_CNT__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define PMU_PMU14C__IDLE_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define PMU_PMU14C__IDLE_CNT__VERIFY(src) (!(((uint32_t)(src) & ~0x000003ffU))) +#define PMU_PMU14C__IDLE_CNT__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field chargeStore */ +/** + * @defgroup pmu_top_regs_core_chargeStore_field chargeStore_field + * @brief macros for field chargeStore + * @details charge store from the battery + * @{ + */ +#define PMU_PMU14C__CHARGESTORE__SHIFT 10 +#define PMU_PMU14C__CHARGESTORE__WIDTH 1 +#define PMU_PMU14C__CHARGESTORE__MASK 0x00000400U +#define PMU_PMU14C__CHARGESTORE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define PMU_PMU14C__CHARGESTORE__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define PMU_PMU14C__CHARGESTORE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define PMU_PMU14C__CHARGESTORE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define PMU_PMU14C__CHARGESTORE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define PMU_PMU14C__CHARGESTORE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define PMU_PMU14C__CHARGESTORE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fixHarvEnerg_ovr */ +/** + * @defgroup pmu_top_regs_core_fixHarvEnerg_ovr_field fixHarvEnerg_ovr_field + * @brief macros for field fixHarvEnerg_ovr + * @details override fixHarvEnerg + * @{ + */ +#define PMU_PMU14C__FIXHARVENERG_OVR__SHIFT 11 +#define PMU_PMU14C__FIXHARVENERG_OVR__WIDTH 1 +#define PMU_PMU14C__FIXHARVENERG_OVR__MASK 0x00000800U +#define PMU_PMU14C__FIXHARVENERG_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define PMU_PMU14C__FIXHARVENERG_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define PMU_PMU14C__FIXHARVENERG_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define PMU_PMU14C__FIXHARVENERG_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define PMU_PMU14C__FIXHARVENERG_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define PMU_PMU14C__FIXHARVENERG_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define PMU_PMU14C__FIXHARVENERG_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fixHarvEnerg_ovr_val */ +/** + * @defgroup pmu_top_regs_core_fixHarvEnerg_ovr_val_field fixHarvEnerg_ovr_val_field + * @brief macros for field fixHarvEnerg_ovr_val + * @details override fixHarvEnerg val: Fix the energize time for all destinations when the source is theharvester. If fixHarvEnerg=1 the target for the harvest to supply modes is the energize time(timeTargetHarv2Store_SH to set the energize time),otherwise it is the dump time. + * @{ + */ +#define PMU_PMU14C__FIXHARVENERG_OVR_VAL__SHIFT 12 +#define PMU_PMU14C__FIXHARVENERG_OVR_VAL__WIDTH 1 +#define PMU_PMU14C__FIXHARVENERG_OVR_VAL__MASK 0x00001000U +#define PMU_PMU14C__FIXHARVENERG_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define PMU_PMU14C__FIXHARVENERG_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define PMU_PMU14C__FIXHARVENERG_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define PMU_PMU14C__FIXHARVENERG_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define PMU_PMU14C__FIXHARVENERG_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define PMU_PMU14C__FIXHARVENERG_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define PMU_PMU14C__FIXHARVENERG_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field force_zerompptref_encomp_off_inv */ +/** + * @defgroup pmu_top_regs_core_force_zerompptref_encomp_off_inv_field force_zerompptref_encomp_off_inv_field + * @brief macros for field force_zerompptref_encomp_off_inv + * @details enable the zerompptref comparator, 1: zerompptref_encomp=1 + * @{ + */ +#define PMU_PMU14C__FORCE_ZEROMPPTREF_ENCOMP_OFF_INV__SHIFT 13 +#define PMU_PMU14C__FORCE_ZEROMPPTREF_ENCOMP_OFF_INV__WIDTH 1 +#define PMU_PMU14C__FORCE_ZEROMPPTREF_ENCOMP_OFF_INV__MASK 0x00002000U +#define PMU_PMU14C__FORCE_ZEROMPPTREF_ENCOMP_OFF_INV__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define PMU_PMU14C__FORCE_ZEROMPPTREF_ENCOMP_OFF_INV__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define PMU_PMU14C__FORCE_ZEROMPPTREF_ENCOMP_OFF_INV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define PMU_PMU14C__FORCE_ZEROMPPTREF_ENCOMP_OFF_INV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define PMU_PMU14C__FORCE_ZEROMPPTREF_ENCOMP_OFF_INV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define PMU_PMU14C__FORCE_ZEROMPPTREF_ENCOMP_OFF_INV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define PMU_PMU14C__FORCE_ZEROMPPTREF_ENCOMP_OFF_INV__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field force_ovr_encompb_zeromppt_off_inv */ +/** + * @defgroup pmu_top_regs_core_force_ovr_encompb_zeromppt_off_inv_field force_ovr_encompb_zeromppt_off_inv_field + * @brief macros for field force_ovr_encompb_zeromppt_off_inv + * @details same with ovr_encompb_zeromppt. When deasserted, zerompptref disables the can/mustharv comparators + * @{ + */ +#define PMU_PMU14C__FORCE_OVR_ENCOMPB_ZEROMPPT_OFF_INV__SHIFT 14 +#define PMU_PMU14C__FORCE_OVR_ENCOMPB_ZEROMPPT_OFF_INV__WIDTH 1 +#define PMU_PMU14C__FORCE_OVR_ENCOMPB_ZEROMPPT_OFF_INV__MASK 0x00004000U +#define PMU_PMU14C__FORCE_OVR_ENCOMPB_ZEROMPPT_OFF_INV__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PMU_PMU14C__FORCE_OVR_ENCOMPB_ZEROMPPT_OFF_INV__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define PMU_PMU14C__FORCE_OVR_ENCOMPB_ZEROMPPT_OFF_INV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define PMU_PMU14C__FORCE_OVR_ENCOMPB_ZEROMPPT_OFF_INV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define PMU_PMU14C__FORCE_OVR_ENCOMPB_ZEROMPPT_OFF_INV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PMU_PMU14C__FORCE_OVR_ENCOMPB_ZEROMPPT_OFF_INV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PMU_PMU14C__FORCE_OVR_ENCOMPB_ZEROMPPT_OFF_INV__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field force_ovr_encompb_increctst_off_inv */ +/** + * @defgroup pmu_top_regs_core_force_ovr_encompb_increctst_off_inv_field force_ovr_encompb_increctst_off_inv_field + * @brief macros for field force_ovr_encompb_increctst_off_inv + * @details same with ovr_encompb_increctst. When deasserted, chpuhswoff_increctst disables the can/mustharv comparators + * @{ + */ +#define PMU_PMU14C__FORCE_OVR_ENCOMPB_INCRECTST_OFF_INV__SHIFT 15 +#define PMU_PMU14C__FORCE_OVR_ENCOMPB_INCRECTST_OFF_INV__WIDTH 1 +#define PMU_PMU14C__FORCE_OVR_ENCOMPB_INCRECTST_OFF_INV__MASK 0x00008000U +#define PMU_PMU14C__FORCE_OVR_ENCOMPB_INCRECTST_OFF_INV__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define PMU_PMU14C__FORCE_OVR_ENCOMPB_INCRECTST_OFF_INV__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define PMU_PMU14C__FORCE_OVR_ENCOMPB_INCRECTST_OFF_INV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define PMU_PMU14C__FORCE_OVR_ENCOMPB_INCRECTST_OFF_INV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define PMU_PMU14C__FORCE_OVR_ENCOMPB_INCRECTST_OFF_INV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PMU_PMU14C__FORCE_OVR_ENCOMPB_INCRECTST_OFF_INV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PMU_PMU14C__FORCE_OVR_ENCOMPB_INCRECTST_OFF_INV__RESET_VALUE \ + 0x00000001U +/** @} */ + +/* macros for field refbuf_ovr */ +/** + * @defgroup pmu_top_regs_core_refbuf_ovr_field refbuf_ovr_field + * @brief macros for field refbuf_ovr + * @details overrides the reference buffer enable and bypass + * @{ + */ +#define PMU_PMU14C__REFBUF_OVR__SHIFT 16 +#define PMU_PMU14C__REFBUF_OVR__WIDTH 1 +#define PMU_PMU14C__REFBUF_OVR__MASK 0x00010000U +#define PMU_PMU14C__REFBUF_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define PMU_PMU14C__REFBUF_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define PMU_PMU14C__REFBUF_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define PMU_PMU14C__REFBUF_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define PMU_PMU14C__REFBUF_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PMU_PMU14C__REFBUF_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PMU_PMU14C__REFBUF_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqDVDD_enrefbuf_ovr_val */ +/** + * @defgroup pmu_top_regs_core_SwchReqDVDD_enrefbuf_ovr_val_field SwchReqDVDD_enrefbuf_ovr_val_field + * @brief macros for field SwchReqDVDD_enrefbuf_ovr_val + * @details override SwchReqDVDD_enrefbuf val: The corresponding reference is buffered at the comparator input + * @{ + */ +#define PMU_PMU14C__SWCHREQDVDD_ENREFBUF_OVR_VAL__SHIFT 17 +#define PMU_PMU14C__SWCHREQDVDD_ENREFBUF_OVR_VAL__WIDTH 1 +#define PMU_PMU14C__SWCHREQDVDD_ENREFBUF_OVR_VAL__MASK 0x00020000U +#define PMU_PMU14C__SWCHREQDVDD_ENREFBUF_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define PMU_PMU14C__SWCHREQDVDD_ENREFBUF_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define PMU_PMU14C__SWCHREQDVDD_ENREFBUF_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define PMU_PMU14C__SWCHREQDVDD_ENREFBUF_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define PMU_PMU14C__SWCHREQDVDD_ENREFBUF_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define PMU_PMU14C__SWCHREQDVDD_ENREFBUF_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define PMU_PMU14C__SWCHREQDVDD_ENREFBUF_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqvaux_enrefbuf_ovr_val */ +/** + * @defgroup pmu_top_regs_core_SwchReqvaux_enrefbuf_ovr_val_field SwchReqvaux_enrefbuf_ovr_val_field + * @brief macros for field SwchReqvaux_enrefbuf_ovr_val + * @details override SwchReqvaux_enrefbuf val: The corresponding reference is buffered at the comparator input + * @{ + */ +#define PMU_PMU14C__SWCHREQVAUX_ENREFBUF_OVR_VAL__SHIFT 18 +#define PMU_PMU14C__SWCHREQVAUX_ENREFBUF_OVR_VAL__WIDTH 1 +#define PMU_PMU14C__SWCHREQVAUX_ENREFBUF_OVR_VAL__MASK 0x00040000U +#define PMU_PMU14C__SWCHREQVAUX_ENREFBUF_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define PMU_PMU14C__SWCHREQVAUX_ENREFBUF_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define PMU_PMU14C__SWCHREQVAUX_ENREFBUF_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define PMU_PMU14C__SWCHREQVAUX_ENREFBUF_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define PMU_PMU14C__SWCHREQVAUX_ENREFBUF_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define PMU_PMU14C__SWCHREQVAUX_ENREFBUF_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define PMU_PMU14C__SWCHREQVAUX_ENREFBUF_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqAVDD_enrefbuf_ovr_val */ +/** + * @defgroup pmu_top_regs_core_SwchReqAVDD_enrefbuf_ovr_val_field SwchReqAVDD_enrefbuf_ovr_val_field + * @brief macros for field SwchReqAVDD_enrefbuf_ovr_val + * @details override SwchReqAVDD_enrefbuf val: The corresponding reference is buffered at the comparator input + * @{ + */ +#define PMU_PMU14C__SWCHREQAVDD_ENREFBUF_OVR_VAL__SHIFT 19 +#define PMU_PMU14C__SWCHREQAVDD_ENREFBUF_OVR_VAL__WIDTH 1 +#define PMU_PMU14C__SWCHREQAVDD_ENREFBUF_OVR_VAL__MASK 0x00080000U +#define PMU_PMU14C__SWCHREQAVDD_ENREFBUF_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define PMU_PMU14C__SWCHREQAVDD_ENREFBUF_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define PMU_PMU14C__SWCHREQAVDD_ENREFBUF_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define PMU_PMU14C__SWCHREQAVDD_ENREFBUF_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define PMU_PMU14C__SWCHREQAVDD_ENREFBUF_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define PMU_PMU14C__SWCHREQAVDD_ENREFBUF_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define PMU_PMU14C__SWCHREQAVDD_ENREFBUF_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field harvstop_enrefbuf_ovr_val */ +/** + * @defgroup pmu_top_regs_core_harvstop_enrefbuf_ovr_val_field harvstop_enrefbuf_ovr_val_field + * @brief macros for field harvstop_enrefbuf_ovr_val + * @details override harvstop_enrefbuf val: The corresponding reference is buffered at the comparator input + * @{ + */ +#define PMU_PMU14C__HARVSTOP_ENREFBUF_OVR_VAL__SHIFT 20 +#define PMU_PMU14C__HARVSTOP_ENREFBUF_OVR_VAL__WIDTH 1 +#define PMU_PMU14C__HARVSTOP_ENREFBUF_OVR_VAL__MASK 0x00100000U +#define PMU_PMU14C__HARVSTOP_ENREFBUF_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define PMU_PMU14C__HARVSTOP_ENREFBUF_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define PMU_PMU14C__HARVSTOP_ENREFBUF_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define PMU_PMU14C__HARVSTOP_ENREFBUF_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define PMU_PMU14C__HARVSTOP_ENREFBUF_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define PMU_PMU14C__HARVSTOP_ENREFBUF_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define PMU_PMU14C__HARVSTOP_ENREFBUF_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqVSTO_enrefbuf_ovr_val */ +/** + * @defgroup pmu_top_regs_core_SwchReqVSTO_enrefbuf_ovr_val_field SwchReqVSTO_enrefbuf_ovr_val_field + * @brief macros for field SwchReqVSTO_enrefbuf_ovr_val + * @details override SwchReqVSTO_enrefbuf val: The corresponding reference is buffered at the comparator input + * @{ + */ +#define PMU_PMU14C__SWCHREQVSTO_ENREFBUF_OVR_VAL__SHIFT 21 +#define PMU_PMU14C__SWCHREQVSTO_ENREFBUF_OVR_VAL__WIDTH 1 +#define PMU_PMU14C__SWCHREQVSTO_ENREFBUF_OVR_VAL__MASK 0x00200000U +#define PMU_PMU14C__SWCHREQVSTO_ENREFBUF_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define PMU_PMU14C__SWCHREQVSTO_ENREFBUF_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define PMU_PMU14C__SWCHREQVSTO_ENREFBUF_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define PMU_PMU14C__SWCHREQVSTO_ENREFBUF_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define PMU_PMU14C__SWCHREQVSTO_ENREFBUF_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define PMU_PMU14C__SWCHREQVSTO_ENREFBUF_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define PMU_PMU14C__SWCHREQVSTO_ENREFBUF_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqDVDD_byrefbuf_ovr_val */ +/** + * @defgroup pmu_top_regs_core_SwchReqDVDD_byrefbuf_ovr_val_field SwchReqDVDD_byrefbuf_ovr_val_field + * @brief macros for field SwchReqDVDD_byrefbuf_ovr_val + * @details override SwchReqDVDD_byrefbuf val: The corresponding reference is bypassed to the comparator input + * @{ + */ +#define PMU_PMU14C__SWCHREQDVDD_BYREFBUF_OVR_VAL__SHIFT 22 +#define PMU_PMU14C__SWCHREQDVDD_BYREFBUF_OVR_VAL__WIDTH 1 +#define PMU_PMU14C__SWCHREQDVDD_BYREFBUF_OVR_VAL__MASK 0x00400000U +#define PMU_PMU14C__SWCHREQDVDD_BYREFBUF_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define PMU_PMU14C__SWCHREQDVDD_BYREFBUF_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define PMU_PMU14C__SWCHREQDVDD_BYREFBUF_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define PMU_PMU14C__SWCHREQDVDD_BYREFBUF_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define PMU_PMU14C__SWCHREQDVDD_BYREFBUF_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define PMU_PMU14C__SWCHREQDVDD_BYREFBUF_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define PMU_PMU14C__SWCHREQDVDD_BYREFBUF_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqvaux_byrefbuf_ovr_val */ +/** + * @defgroup pmu_top_regs_core_SwchReqvaux_byrefbuf_ovr_val_field SwchReqvaux_byrefbuf_ovr_val_field + * @brief macros for field SwchReqvaux_byrefbuf_ovr_val + * @details override SwchReqvaux_byrefbuf val: The corresponding reference is bypassed to the comparator input + * @{ + */ +#define PMU_PMU14C__SWCHREQVAUX_BYREFBUF_OVR_VAL__SHIFT 23 +#define PMU_PMU14C__SWCHREQVAUX_BYREFBUF_OVR_VAL__WIDTH 1 +#define PMU_PMU14C__SWCHREQVAUX_BYREFBUF_OVR_VAL__MASK 0x00800000U +#define PMU_PMU14C__SWCHREQVAUX_BYREFBUF_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PMU_PMU14C__SWCHREQVAUX_BYREFBUF_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define PMU_PMU14C__SWCHREQVAUX_BYREFBUF_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define PMU_PMU14C__SWCHREQVAUX_BYREFBUF_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define PMU_PMU14C__SWCHREQVAUX_BYREFBUF_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PMU_PMU14C__SWCHREQVAUX_BYREFBUF_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PMU_PMU14C__SWCHREQVAUX_BYREFBUF_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqAVDD_byrefbuf_ovr_val */ +/** + * @defgroup pmu_top_regs_core_SwchReqAVDD_byrefbuf_ovr_val_field SwchReqAVDD_byrefbuf_ovr_val_field + * @brief macros for field SwchReqAVDD_byrefbuf_ovr_val + * @details override SwchReqAVDD_byrefbuf val: The corresponding reference is bypassed to the comparator input + * @{ + */ +#define PMU_PMU14C__SWCHREQAVDD_BYREFBUF_OVR_VAL__SHIFT 24 +#define PMU_PMU14C__SWCHREQAVDD_BYREFBUF_OVR_VAL__WIDTH 1 +#define PMU_PMU14C__SWCHREQAVDD_BYREFBUF_OVR_VAL__MASK 0x01000000U +#define PMU_PMU14C__SWCHREQAVDD_BYREFBUF_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define PMU_PMU14C__SWCHREQAVDD_BYREFBUF_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define PMU_PMU14C__SWCHREQAVDD_BYREFBUF_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define PMU_PMU14C__SWCHREQAVDD_BYREFBUF_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define PMU_PMU14C__SWCHREQAVDD_BYREFBUF_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define PMU_PMU14C__SWCHREQAVDD_BYREFBUF_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define PMU_PMU14C__SWCHREQAVDD_BYREFBUF_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field harvstop_byrefbuf_ovr_val */ +/** + * @defgroup pmu_top_regs_core_harvstop_byrefbuf_ovr_val_field harvstop_byrefbuf_ovr_val_field + * @brief macros for field harvstop_byrefbuf_ovr_val + * @details override harvstop_byrefbuf val: The corresponding reference is bypassed to the comparator input + * @{ + */ +#define PMU_PMU14C__HARVSTOP_BYREFBUF_OVR_VAL__SHIFT 25 +#define PMU_PMU14C__HARVSTOP_BYREFBUF_OVR_VAL__WIDTH 1 +#define PMU_PMU14C__HARVSTOP_BYREFBUF_OVR_VAL__MASK 0x02000000U +#define PMU_PMU14C__HARVSTOP_BYREFBUF_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define PMU_PMU14C__HARVSTOP_BYREFBUF_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define PMU_PMU14C__HARVSTOP_BYREFBUF_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define PMU_PMU14C__HARVSTOP_BYREFBUF_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define PMU_PMU14C__HARVSTOP_BYREFBUF_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define PMU_PMU14C__HARVSTOP_BYREFBUF_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define PMU_PMU14C__HARVSTOP_BYREFBUF_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field SwchReqVSTO_byrefbuf_ovr_val */ +/** + * @defgroup pmu_top_regs_core_SwchReqVSTO_byrefbuf_ovr_val_field SwchReqVSTO_byrefbuf_ovr_val_field + * @brief macros for field SwchReqVSTO_byrefbuf_ovr_val + * @details override SwchReqVSTO_byrefbuf val: The corresponding reference is bypassed to the comparator input + * @{ + */ +#define PMU_PMU14C__SWCHREQVSTO_BYREFBUF_OVR_VAL__SHIFT 26 +#define PMU_PMU14C__SWCHREQVSTO_BYREFBUF_OVR_VAL__WIDTH 1 +#define PMU_PMU14C__SWCHREQVSTO_BYREFBUF_OVR_VAL__MASK 0x04000000U +#define PMU_PMU14C__SWCHREQVSTO_BYREFBUF_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define PMU_PMU14C__SWCHREQVSTO_BYREFBUF_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define PMU_PMU14C__SWCHREQVSTO_BYREFBUF_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define PMU_PMU14C__SWCHREQVSTO_BYREFBUF_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define PMU_PMU14C__SWCHREQVSTO_BYREFBUF_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define PMU_PMU14C__SWCHREQVSTO_BYREFBUF_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define PMU_PMU14C__SWCHREQVSTO_BYREFBUF_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_prtsatcurr_ovr */ +/** + * @defgroup pmu_top_regs_core_ctr_prtsatcurr_ovr_field ctr_prtsatcurr_ovr_field + * @brief macros for field ctr_prtsatcurr_ovr + * @details override ctr_prtsatcurr + * @{ + */ +#define PMU_PMU14C__CTR_PRTSATCURR_OVR__SHIFT 27 +#define PMU_PMU14C__CTR_PRTSATCURR_OVR__WIDTH 1 +#define PMU_PMU14C__CTR_PRTSATCURR_OVR__MASK 0x08000000U +#define PMU_PMU14C__CTR_PRTSATCURR_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define PMU_PMU14C__CTR_PRTSATCURR_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define PMU_PMU14C__CTR_PRTSATCURR_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define PMU_PMU14C__CTR_PRTSATCURR_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define PMU_PMU14C__CTR_PRTSATCURR_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define PMU_PMU14C__CTR_PRTSATCURR_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define PMU_PMU14C__CTR_PRTSATCURR_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_prtsatcurr_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ctr_prtsatcurr_ovr_val_field ctr_prtsatcurr_ovr_val_field + * @brief macros for field ctr_prtsatcurr_ovr_val + * @details override ctr_prtsatcurr val: enables the L1 LDO current protection when in regulating mode. Enabled by default + * @{ + */ +#define PMU_PMU14C__CTR_PRTSATCURR_OVR_VAL__SHIFT 28 +#define PMU_PMU14C__CTR_PRTSATCURR_OVR_VAL__WIDTH 1 +#define PMU_PMU14C__CTR_PRTSATCURR_OVR_VAL__MASK 0x10000000U +#define PMU_PMU14C__CTR_PRTSATCURR_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define PMU_PMU14C__CTR_PRTSATCURR_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define PMU_PMU14C__CTR_PRTSATCURR_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define PMU_PMU14C__CTR_PRTSATCURR_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define PMU_PMU14C__CTR_PRTSATCURR_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define PMU_PMU14C__CTR_PRTSATCURR_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define PMU_PMU14C__CTR_PRTSATCURR_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reg_swreg_clkcal_ctrl */ +/** + * @defgroup pmu_top_regs_core_reg_swreg_clkcal_ctrl_field reg_swreg_clkcal_ctrl_field + * @brief macros for field reg_swreg_clkcal_ctrl + * @details when asserted can set reg_swreg_clkcal into updateUnitDel + * @{ + */ +#define PMU_PMU14C__REG_SWREG_CLKCAL_CTRL__SHIFT 29 +#define PMU_PMU14C__REG_SWREG_CLKCAL_CTRL__WIDTH 1 +#define PMU_PMU14C__REG_SWREG_CLKCAL_CTRL__MASK 0x20000000U +#define PMU_PMU14C__REG_SWREG_CLKCAL_CTRL__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define PMU_PMU14C__REG_SWREG_CLKCAL_CTRL__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define PMU_PMU14C__REG_SWREG_CLKCAL_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define PMU_PMU14C__REG_SWREG_CLKCAL_CTRL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define PMU_PMU14C__REG_SWREG_CLKCAL_CTRL__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define PMU_PMU14C__REG_SWREG_CLKCAL_CTRL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define PMU_PMU14C__REG_SWREG_CLKCAL_CTRL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reg_swreg_clkcal */ +/** + * @defgroup pmu_top_regs_core_reg_swreg_clkcal_field reg_swreg_clkcal_field + * @brief macros for field reg_swreg_clkcal + * @details set updateUnitDel + * @{ + */ +#define PMU_PMU14C__REG_SWREG_CLKCAL__SHIFT 30 +#define PMU_PMU14C__REG_SWREG_CLKCAL__WIDTH 1 +#define PMU_PMU14C__REG_SWREG_CLKCAL__MASK 0x40000000U +#define PMU_PMU14C__REG_SWREG_CLKCAL__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define PMU_PMU14C__REG_SWREG_CLKCAL__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define PMU_PMU14C__REG_SWREG_CLKCAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define PMU_PMU14C__REG_SWREG_CLKCAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define PMU_PMU14C__REG_SWREG_CLKCAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define PMU_PMU14C__REG_SWREG_CLKCAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define PMU_PMU14C__REG_SWREG_CLKCAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field stoclamp_encomp */ +/** + * @defgroup pmu_top_regs_core_stoclamp_encomp_field stoclamp_encomp_field + * @brief macros for field stoclamp_encomp + * @details enable Vstore clamp comparator for Vstore overdrive protection + * @{ + */ +#define PMU_PMU14C__STOCLAMP_ENCOMP__SHIFT 31 +#define PMU_PMU14C__STOCLAMP_ENCOMP__WIDTH 1 +#define PMU_PMU14C__STOCLAMP_ENCOMP__MASK 0x80000000U +#define PMU_PMU14C__STOCLAMP_ENCOMP__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define PMU_PMU14C__STOCLAMP_ENCOMP__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define PMU_PMU14C__STOCLAMP_ENCOMP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define PMU_PMU14C__STOCLAMP_ENCOMP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define PMU_PMU14C__STOCLAMP_ENCOMP__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PMU_PMU14C__STOCLAMP_ENCOMP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PMU_PMU14C__STOCLAMP_ENCOMP__RESET_VALUE 0x00000001U +/** @} */ +#define PMU_PMU14C__TYPE uint32_t +#define PMU_PMU14C__READ 0xffffffffU +#define PMU_PMU14C__WRITE 0xffffffffU +#define PMU_PMU14C__PRESERVED 0x00000000U +#define PMU_PMU14C__RESET_VALUE 0x8000e004U + +#endif /* __PMU_PMU14C_MACRO__ */ + +/** @} end of pmu14c */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu15 */ +/** + * @defgroup pmu_top_regs_core_pmu15 pmu15 + * @brief more pmu controls definitions. + * @{ + */ +#ifndef __PMU_PMU15_MACRO__ +#define __PMU_PMU15_MACRO__ + +/* macros for field ctr_reffstInsel */ +/** + * @defgroup pmu_top_regs_core_ctr_reffstInsel_field ctr_reffstInsel_field + * @brief macros for field ctr_reffstInsel + * @details fast refgen feedback tap select. For reference=600mV3: 625mV reflad<25>2: 600mV reflad<24>1: 575mV reflad<23>0: 550mV reflad<22> + * @{ + */ +#define PMU_PMU15__CTR_REFFSTINSEL__SHIFT 0 +#define PMU_PMU15__CTR_REFFSTINSEL__WIDTH 2 +#define PMU_PMU15__CTR_REFFSTINSEL__MASK 0x00000003U +#define PMU_PMU15__CTR_REFFSTINSEL__READ(src) ((uint32_t)(src) & 0x00000003U) +#define PMU_PMU15__CTR_REFFSTINSEL__WRITE(src) ((uint32_t)(src) & 0x00000003U) +#define PMU_PMU15__CTR_REFFSTINSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define PMU_PMU15__CTR_REFFSTINSEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define PMU_PMU15__CTR_REFFSTINSEL__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field ctr_refgenfastcurr */ +/** + * @defgroup pmu_top_regs_core_ctr_refgenfastcurr_field ctr_refgenfastcurr_field + * @brief macros for field ctr_refgenfastcurr + * @details control current of fast refgen + * @{ + */ +#define PMU_PMU15__CTR_REFGENFASTCURR__SHIFT 2 +#define PMU_PMU15__CTR_REFGENFASTCURR__WIDTH 1 +#define PMU_PMU15__CTR_REFGENFASTCURR__MASK 0x00000004U +#define PMU_PMU15__CTR_REFGENFASTCURR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define PMU_PMU15__CTR_REFGENFASTCURR__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define PMU_PMU15__CTR_REFGENFASTCURR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define PMU_PMU15__CTR_REFGENFASTCURR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define PMU_PMU15__CTR_REFGENFASTCURR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define PMU_PMU15__CTR_REFGENFASTCURR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define PMU_PMU15__CTR_REFGENFASTCURR__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ctr_refvstoreq */ +/** + * @defgroup pmu_top_regs_core_ctr_refvstoreq_field ctr_refvstoreq_field + * @brief macros for field ctr_refvstoreq + * @details control VrefvstoReq= 25*(16+i*8), i=7:0 + * @{ + */ +#define PMU_PMU15__CTR_REFVSTOREQ__SHIFT 3 +#define PMU_PMU15__CTR_REFVSTOREQ__WIDTH 3 +#define PMU_PMU15__CTR_REFVSTOREQ__MASK 0x00000038U +#define PMU_PMU15__CTR_REFVSTOREQ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define PMU_PMU15__CTR_REFVSTOREQ__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define PMU_PMU15__CTR_REFVSTOREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define PMU_PMU15__CTR_REFVSTOREQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define PMU_PMU15__CTR_REFVSTOREQ__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field ctr_refvstoreq_lowR */ +/** + * @defgroup pmu_top_regs_core_ctr_refvstoreq_lowR_field ctr_refvstoreq_lowR_field + * @brief macros for field ctr_refvstoreq_lowR + * @details Selects different vstore comparator reference1: reference generated by the lowR resistor in the pmuparef0: reference generated by refgen + * @{ + */ +#define PMU_PMU15__CTR_REFVSTOREQ_LOWR__SHIFT 6 +#define PMU_PMU15__CTR_REFVSTOREQ_LOWR__WIDTH 1 +#define PMU_PMU15__CTR_REFVSTOREQ_LOWR__MASK 0x00000040U +#define PMU_PMU15__CTR_REFVSTOREQ_LOWR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define PMU_PMU15__CTR_REFVSTOREQ_LOWR__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define PMU_PMU15__CTR_REFVSTOREQ_LOWR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PMU_PMU15__CTR_REFVSTOREQ_LOWR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PMU_PMU15__CTR_REFVSTOREQ_LOWR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PMU_PMU15__CTR_REFVSTOREQ_LOWR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PMU_PMU15__CTR_REFVSTOREQ_LOWR__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ctr_zerompptref */ +/** + * @defgroup pmu_top_regs_core_ctr_zerompptref_field ctr_zerompptref_field + * @brief macros for field ctr_zerompptref + * @details control Vrefzerompptref used by the zerompptref comparator25*[9,8,6,4], i=3:0 + * @{ + */ +#define PMU_PMU15__CTR_ZEROMPPTREF__SHIFT 7 +#define PMU_PMU15__CTR_ZEROMPPTREF__WIDTH 2 +#define PMU_PMU15__CTR_ZEROMPPTREF__MASK 0x00000180U +#define PMU_PMU15__CTR_ZEROMPPTREF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000180U) >> 7) +#define PMU_PMU15__CTR_ZEROMPPTREF__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000180U) +#define PMU_PMU15__CTR_ZEROMPPTREF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000180U) | (((uint32_t)(src) <<\ + 7) & 0x00000180U) +#define PMU_PMU15__CTR_ZEROMPPTREF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000180U))) +#define PMU_PMU15__CTR_ZEROMPPTREF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ctr_refshreg */ +/** + * @defgroup pmu_top_regs_core_ctr_refshreg_field ctr_refshreg_field + * @brief macros for field ctr_refshreg + * @details Control Vrefshreg used by the rectifier shunt regulator,25*(36+i*4), i=3:0 + * @{ + */ +#define PMU_PMU15__CTR_REFSHREG__SHIFT 9 +#define PMU_PMU15__CTR_REFSHREG__WIDTH 2 +#define PMU_PMU15__CTR_REFSHREG__MASK 0x00000600U +#define PMU_PMU15__CTR_REFSHREG__READ(src) \ + (((uint32_t)(src)\ + & 0x00000600U) >> 9) +#define PMU_PMU15__CTR_REFSHREG__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000600U) +#define PMU_PMU15__CTR_REFSHREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000600U) | (((uint32_t)(src) <<\ + 9) & 0x00000600U) +#define PMU_PMU15__CTR_REFSHREG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000600U))) +#define PMU_PMU15__CTR_REFSHREG__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field ctr_pmuadcref */ +/** + * @defgroup pmu_top_regs_core_ctr_pmuadcref_field ctr_pmuadcref_field + * @brief macros for field ctr_pmuadcref + * @details Control pmuadcref, 25*(23+i-1) for i=3:1, vrefnat600 for i=0 + * @{ + */ +#define PMU_PMU15__CTR_PMUADCREF__SHIFT 11 +#define PMU_PMU15__CTR_PMUADCREF__WIDTH 2 +#define PMU_PMU15__CTR_PMUADCREF__MASK 0x00001800U +#define PMU_PMU15__CTR_PMUADCREF__READ(src) \ + (((uint32_t)(src)\ + & 0x00001800U) >> 11) +#define PMU_PMU15__CTR_PMUADCREF__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00001800U) +#define PMU_PMU15__CTR_PMUADCREF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001800U) | (((uint32_t)(src) <<\ + 11) & 0x00001800U) +#define PMU_PMU15__CTR_PMUADCREF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00001800U))) +#define PMU_PMU15__CTR_PMUADCREF__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field ctr_usevsto4avddreq */ +/** + * @defgroup pmu_top_regs_core_ctr_usevsto4avddreq_field ctr_usevsto4avddreq_field + * @brief macros for field ctr_usevsto4avddreq + * @details Use the Vstore request comparator to sense avdd and generate avdd requestsIt takes over the avdd request comparator thanks to its NMOS+PMOS full scale input. + * @{ + */ +#define PMU_PMU15__CTR_USEVSTO4AVDDREQ__SHIFT 13 +#define PMU_PMU15__CTR_USEVSTO4AVDDREQ__WIDTH 1 +#define PMU_PMU15__CTR_USEVSTO4AVDDREQ__MASK 0x00002000U +#define PMU_PMU15__CTR_USEVSTO4AVDDREQ__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define PMU_PMU15__CTR_USEVSTO4AVDDREQ__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define PMU_PMU15__CTR_USEVSTO4AVDDREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define PMU_PMU15__CTR_USEVSTO4AVDDREQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define PMU_PMU15__CTR_USEVSTO4AVDDREQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define PMU_PMU15__CTR_USEVSTO4AVDDREQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define PMU_PMU15__CTR_USEVSTO4AVDDREQ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field decrectst_enhy */ +/** + * @defgroup pmu_top_regs_core_decrectst_enhy_field decrectst_enhy_field + * @brief macros for field decrectst_enhy + * @details enable hysteresis in the decrectstage_prtVharv comparator1: When used to protect Vharv at ~3V during solar harvesting0: During RF mppt that we want to regulate efficiently Vharv till the number of rectifier stages change + * @{ + */ +#define PMU_PMU15__DECRECTST_ENHY__SHIFT 14 +#define PMU_PMU15__DECRECTST_ENHY__WIDTH 1 +#define PMU_PMU15__DECRECTST_ENHY__MASK 0x00004000U +#define PMU_PMU15__DECRECTST_ENHY__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PMU_PMU15__DECRECTST_ENHY__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define PMU_PMU15__DECRECTST_ENHY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define PMU_PMU15__DECRECTST_ENHY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define PMU_PMU15__DECRECTST_ENHY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PMU_PMU15__DECRECTST_ENHY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PMU_PMU15__DECRECTST_ENHY__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field zerompptref_ctrcu */ +/** + * @defgroup pmu_top_regs_core_zerompptref_ctrcu_field zerompptref_ctrcu_field + * @brief macros for field zerompptref_ctrcu + * @details control the fast current of zerompptref comparator + * @{ + */ +#define PMU_PMU15__ZEROMPPTREF_CTRCU__SHIFT 15 +#define PMU_PMU15__ZEROMPPTREF_CTRCU__WIDTH 5 +#define PMU_PMU15__ZEROMPPTREF_CTRCU__MASK 0x000f8000U +#define PMU_PMU15__ZEROMPPTREF_CTRCU__READ(src) \ + (((uint32_t)(src)\ + & 0x000f8000U) >> 15) +#define PMU_PMU15__ZEROMPPTREF_CTRCU__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x000f8000U) +#define PMU_PMU15__ZEROMPPTREF_CTRCU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((uint32_t)(src) <<\ + 15) & 0x000f8000U) +#define PMU_PMU15__ZEROMPPTREF_CTRCU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x000f8000U))) +#define PMU_PMU15__ZEROMPPTREF_CTRCU__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field en_compshreg */ +/** + * @defgroup pmu_top_regs_core_en_compshreg_field en_compshreg_field + * @brief macros for field en_compshreg + * @details Enable the shunt regulator on RFHARV input + * @{ + */ +#define PMU_PMU15__EN_COMPSHREG__SHIFT 20 +#define PMU_PMU15__EN_COMPSHREG__WIDTH 1 +#define PMU_PMU15__EN_COMPSHREG__MASK 0x00100000U +#define PMU_PMU15__EN_COMPSHREG__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define PMU_PMU15__EN_COMPSHREG__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define PMU_PMU15__EN_COMPSHREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define PMU_PMU15__EN_COMPSHREG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define PMU_PMU15__EN_COMPSHREG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define PMU_PMU15__EN_COMPSHREG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define PMU_PMU15__EN_COMPSHREG__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field en_shuntrf */ +/** + * @defgroup pmu_top_regs_core_en_shuntrf_field en_shuntrf_field + * @brief macros for field en_shuntrf + * @details Shunt the RFHARV input to ground to check the maximum shunting ability of shunt regulator + * @{ + */ +#define PMU_PMU15__EN_SHUNTRF__SHIFT 21 +#define PMU_PMU15__EN_SHUNTRF__WIDTH 1 +#define PMU_PMU15__EN_SHUNTRF__MASK 0x00200000U +#define PMU_PMU15__EN_SHUNTRF__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define PMU_PMU15__EN_SHUNTRF__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define PMU_PMU15__EN_SHUNTRF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define PMU_PMU15__EN_SHUNTRF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define PMU_PMU15__EN_SHUNTRF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define PMU_PMU15__EN_SHUNTRF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define PMU_PMU15__EN_SHUNTRF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_pmurectleakcu */ +/** + * @defgroup pmu_top_regs_core_en_pmurectleakcu_field en_pmurectleakcu_field + * @brief macros for field en_pmurectleakcu + * @details add an imbalance current into the RF harvesting rectifiers to make sure they latch when OFFto help prevent any stress issue in the rectifier core devices + * @{ + */ +#define PMU_PMU15__EN_PMURECTLEAKCU__SHIFT 22 +#define PMU_PMU15__EN_PMURECTLEAKCU__WIDTH 1 +#define PMU_PMU15__EN_PMURECTLEAKCU__MASK 0x00400000U +#define PMU_PMU15__EN_PMURECTLEAKCU__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define PMU_PMU15__EN_PMURECTLEAKCU__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define PMU_PMU15__EN_PMURECTLEAKCU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define PMU_PMU15__EN_PMURECTLEAKCU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define PMU_PMU15__EN_PMURECTLEAKCU__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define PMU_PMU15__EN_PMURECTLEAKCU__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define PMU_PMU15__EN_PMURECTLEAKCU__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_prtbypcurr_ovr */ +/** + * @defgroup pmu_top_regs_core_ctr_prtbypcurr_ovr_field ctr_prtbypcurr_ovr_field + * @brief macros for field ctr_prtbypcurr_ovr + * @details unused + * @{ + */ +#define PMU_PMU15__CTR_PRTBYPCURR_OVR__SHIFT 23 +#define PMU_PMU15__CTR_PRTBYPCURR_OVR__WIDTH 1 +#define PMU_PMU15__CTR_PRTBYPCURR_OVR__MASK 0x00800000U +#define PMU_PMU15__CTR_PRTBYPCURR_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PMU_PMU15__CTR_PRTBYPCURR_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define PMU_PMU15__CTR_PRTBYPCURR_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define PMU_PMU15__CTR_PRTBYPCURR_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define PMU_PMU15__CTR_PRTBYPCURR_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PMU_PMU15__CTR_PRTBYPCURR_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PMU_PMU15__CTR_PRTBYPCURR_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_prtbypcurr_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ctr_prtbypcurr_ovr_val_field ctr_prtbypcurr_ovr_val_field + * @brief macros for field ctr_prtbypcurr_ovr_val + * @details unused + * @{ + */ +#define PMU_PMU15__CTR_PRTBYPCURR_OVR_VAL__SHIFT 24 +#define PMU_PMU15__CTR_PRTBYPCURR_OVR_VAL__WIDTH 1 +#define PMU_PMU15__CTR_PRTBYPCURR_OVR_VAL__MASK 0x01000000U +#define PMU_PMU15__CTR_PRTBYPCURR_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define PMU_PMU15__CTR_PRTBYPCURR_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define PMU_PMU15__CTR_PRTBYPCURR_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define PMU_PMU15__CTR_PRTBYPCURR_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define PMU_PMU15__CTR_PRTBYPCURR_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define PMU_PMU15__CTR_PRTBYPCURR_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define PMU_PMU15__CTR_PRTBYPCURR_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field swResVbat_ctrcu */ +/** + * @defgroup pmu_top_regs_core_swResVbat_ctrcu_field swResVbat_ctrcu_field + * @brief macros for field swResVbat_ctrcu + * @details control the swResVbat comparator currentctr_cuLow with <1:0>, ctr_cuMid with <3:2>, ctr_cuMidx2 with <4> + * @{ + */ +#define PMU_PMU15__SWRESVBAT_CTRCU__SHIFT 25 +#define PMU_PMU15__SWRESVBAT_CTRCU__WIDTH 5 +#define PMU_PMU15__SWRESVBAT_CTRCU__MASK 0x3e000000U +#define PMU_PMU15__SWRESVBAT_CTRCU__READ(src) \ + (((uint32_t)(src)\ + & 0x3e000000U) >> 25) +#define PMU_PMU15__SWRESVBAT_CTRCU__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x3e000000U) +#define PMU_PMU15__SWRESVBAT_CTRCU__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((uint32_t)(src) <<\ + 25) & 0x3e000000U) +#define PMU_PMU15__SWRESVBAT_CTRCU__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x3e000000U))) +#define PMU_PMU15__SWRESVBAT_CTRCU__RESET_VALUE 0x0000001fU +/** @} */ + +/* macros for field swResVbat_ctrsamecurr */ +/** + * @defgroup pmu_top_regs_core_swResVbat_ctrsamecurr_field swResVbat_ctrsamecurr_field + * @brief macros for field swResVbat_ctrsamecurr + * @details control slow current in swResVbat comparator0: decrease the slow current1: keep the slow current equal to the fast + * @{ + */ +#define PMU_PMU15__SWRESVBAT_CTRSAMECURR__SHIFT 30 +#define PMU_PMU15__SWRESVBAT_CTRSAMECURR__WIDTH 1 +#define PMU_PMU15__SWRESVBAT_CTRSAMECURR__MASK 0x40000000U +#define PMU_PMU15__SWRESVBAT_CTRSAMECURR__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define PMU_PMU15__SWRESVBAT_CTRSAMECURR__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define PMU_PMU15__SWRESVBAT_CTRSAMECURR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define PMU_PMU15__SWRESVBAT_CTRSAMECURR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define PMU_PMU15__SWRESVBAT_CTRSAMECURR__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define PMU_PMU15__SWRESVBAT_CTRSAMECURR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define PMU_PMU15__SWRESVBAT_CTRSAMECURR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field swRes_ctrsamecurr */ +/** + * @defgroup pmu_top_regs_core_swRes_ctrsamecurr_field swRes_ctrsamecurr_field + * @brief macros for field swRes_ctrsamecurr + * @details control slow current in swRes comparator used in cold start0: decrease the slow current1: keep the slow current equal to the fast + * @{ + */ +#define PMU_PMU15__SWRES_CTRSAMECURR__SHIFT 31 +#define PMU_PMU15__SWRES_CTRSAMECURR__WIDTH 1 +#define PMU_PMU15__SWRES_CTRSAMECURR__MASK 0x80000000U +#define PMU_PMU15__SWRES_CTRSAMECURR__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define PMU_PMU15__SWRES_CTRSAMECURR__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define PMU_PMU15__SWRES_CTRSAMECURR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define PMU_PMU15__SWRES_CTRSAMECURR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define PMU_PMU15__SWRES_CTRSAMECURR__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PMU_PMU15__SWRES_CTRSAMECURR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PMU_PMU15__SWRES_CTRSAMECURR__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU15__TYPE uint32_t +#define PMU_PMU15__READ 0xffffffffU +#define PMU_PMU15__WRITE 0xffffffffU +#define PMU_PMU15__PRESERVED 0x00000000U +#define PMU_PMU15__RESET_VALUE 0x3e13d4deU + +#endif /* __PMU_PMU15_MACRO__ */ + +/** @} end of pmu15 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu16 */ +/** + * @defgroup pmu_top_regs_core_pmu16 pmu16 + * @brief more config bits definitions. + * @{ + */ +#ifndef __PMU_PMU16_MACRO__ +#define __PMU_PMU16_MACRO__ + +/* macros for field paRef */ +/** + * @defgroup pmu_top_regs_core_paRef_field paRef_field + * @brief macros for field paRef + * @details control the pa supply ref + * @{ + */ +#define PMU_PMU16__PAREF__SHIFT 0 +#define PMU_PMU16__PAREF__WIDTH 6 +#define PMU_PMU16__PAREF__MASK 0x0000003fU +#define PMU_PMU16__PAREF__READ(src) ((uint32_t)(src) & 0x0000003fU) +#define PMU_PMU16__PAREF__WRITE(src) ((uint32_t)(src) & 0x0000003fU) +#define PMU_PMU16__PAREF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define PMU_PMU16__PAREF__VERIFY(src) (!(((uint32_t)(src) & ~0x0000003fU))) +#define PMU_PMU16__PAREF__RESET_VALUE 0x00000039U +/** @} */ + +/* macros for field swreg_fsmToUse_ovr */ +/** + * @defgroup pmu_top_regs_core_swreg_fsmToUse_ovr_field swreg_fsmToUse_ovr_field + * @brief macros for field swreg_fsmToUse_ovr + * @details override swreg_fsmToUse + * @{ + */ +#define PMU_PMU16__SWREG_FSMTOUSE_OVR__SHIFT 6 +#define PMU_PMU16__SWREG_FSMTOUSE_OVR__WIDTH 1 +#define PMU_PMU16__SWREG_FSMTOUSE_OVR__MASK 0x00000040U +#define PMU_PMU16__SWREG_FSMTOUSE_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define PMU_PMU16__SWREG_FSMTOUSE_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define PMU_PMU16__SWREG_FSMTOUSE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define PMU_PMU16__SWREG_FSMTOUSE_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define PMU_PMU16__SWREG_FSMTOUSE_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define PMU_PMU16__SWREG_FSMTOUSE_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define PMU_PMU16__SWREG_FSMTOUSE_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field swreg_fsmToUse_ovr_val */ +/** + * @defgroup pmu_top_regs_core_swreg_fsmToUse_ovr_val_field swreg_fsmToUse_ovr_val_field + * @brief macros for field swreg_fsmToUse_ovr_val + * @details override swreg_fsmToUse val: can force the FSM to use + * @{ + */ +#define PMU_PMU16__SWREG_FSMTOUSE_OVR_VAL__SHIFT 7 +#define PMU_PMU16__SWREG_FSMTOUSE_OVR_VAL__WIDTH 2 +#define PMU_PMU16__SWREG_FSMTOUSE_OVR_VAL__MASK 0x00000180U +#define PMU_PMU16__SWREG_FSMTOUSE_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000180U) >> 7) +#define PMU_PMU16__SWREG_FSMTOUSE_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000180U) +#define PMU_PMU16__SWREG_FSMTOUSE_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000180U) | (((uint32_t)(src) <<\ + 7) & 0x00000180U) +#define PMU_PMU16__SWREG_FSMTOUSE_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000180U))) +#define PMU_PMU16__SWREG_FSMTOUSE_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fsm_lp_harv_reg */ +/** + * @defgroup pmu_top_regs_core_fsm_lp_harv_reg_field fsm_lp_harv_reg_field + * @brief macros for field fsm_lp_harv_reg + * @details selects idle state FSM if no harvsting, 0: FSM is tiny, 1: FSM is simple + * @{ + */ +#define PMU_PMU16__FSM_LP_HARV_REG__SHIFT 9 +#define PMU_PMU16__FSM_LP_HARV_REG__WIDTH 2 +#define PMU_PMU16__FSM_LP_HARV_REG__MASK 0x00000600U +#define PMU_PMU16__FSM_LP_HARV_REG__READ(src) \ + (((uint32_t)(src)\ + & 0x00000600U) >> 9) +#define PMU_PMU16__FSM_LP_HARV_REG__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000600U) +#define PMU_PMU16__FSM_LP_HARV_REG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000600U) | (((uint32_t)(src) <<\ + 9) & 0x00000600U) +#define PMU_PMU16__FSM_LP_HARV_REG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000600U))) +#define PMU_PMU16__FSM_LP_HARV_REG__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field storeIsSup */ +/** + * @defgroup pmu_top_regs_core_storeIsSup_field storeIsSup_field + * @brief macros for field storeIsSup + * @details When set the Vstore is a supply used ie for the PA. + * @{ + */ +#define PMU_PMU16__STOREISSUP__SHIFT 11 +#define PMU_PMU16__STOREISSUP__WIDTH 1 +#define PMU_PMU16__STOREISSUP__MASK 0x00000800U +#define PMU_PMU16__STOREISSUP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define PMU_PMU16__STOREISSUP__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define PMU_PMU16__STOREISSUP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define PMU_PMU16__STOREISSUP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define PMU_PMU16__STOREISSUP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define PMU_PMU16__STOREISSUP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define PMU_PMU16__STOREISSUP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ovr_decrectstage_prtVharv_ovr */ +/** + * @defgroup pmu_top_regs_core_ovr_decrectstage_prtVharv_ovr_field ovr_decrectstage_prtVharv_ovr_field + * @brief macros for field ovr_decrectstage_prtVharv_ovr + * @details override ovr_decrectstage_prtVharv. The ovr_decrectstage_prtVharv is controlled by the analog mppt algorithm. + * @{ + */ +#define PMU_PMU16__OVR_DECRECTSTAGE_PRTVHARV_OVR__SHIFT 12 +#define PMU_PMU16__OVR_DECRECTSTAGE_PRTVHARV_OVR__WIDTH 1 +#define PMU_PMU16__OVR_DECRECTSTAGE_PRTVHARV_OVR__MASK 0x00001000U +#define PMU_PMU16__OVR_DECRECTSTAGE_PRTVHARV_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define PMU_PMU16__OVR_DECRECTSTAGE_PRTVHARV_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define PMU_PMU16__OVR_DECRECTSTAGE_PRTVHARV_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define PMU_PMU16__OVR_DECRECTSTAGE_PRTVHARV_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define PMU_PMU16__OVR_DECRECTSTAGE_PRTVHARV_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define PMU_PMU16__OVR_DECRECTSTAGE_PRTVHARV_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define PMU_PMU16__OVR_DECRECTSTAGE_PRTVHARV_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ovr_decrectstage_prtVharv_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ovr_decrectstage_prtVharv_ovr_val_field ovr_decrectstage_prtVharv_ovr_val_field + * @brief macros for field ovr_decrectstage_prtVharv_ovr_val + * @details override ovr_decrectstage_prtVharv val:0: the decrectstage_prtVharv forces can/mustharv to requestImportant to be applied right after the number of stages is decreased during analog mppt1: the decrectstage_prtVharv has no effect on can/mustharv + * @{ + */ +#define PMU_PMU16__OVR_DECRECTSTAGE_PRTVHARV_OVR_VAL__SHIFT 13 +#define PMU_PMU16__OVR_DECRECTSTAGE_PRTVHARV_OVR_VAL__WIDTH 1 +#define PMU_PMU16__OVR_DECRECTSTAGE_PRTVHARV_OVR_VAL__MASK 0x00002000U +#define PMU_PMU16__OVR_DECRECTSTAGE_PRTVHARV_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define PMU_PMU16__OVR_DECRECTSTAGE_PRTVHARV_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define PMU_PMU16__OVR_DECRECTSTAGE_PRTVHARV_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define PMU_PMU16__OVR_DECRECTSTAGE_PRTVHARV_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define PMU_PMU16__OVR_DECRECTSTAGE_PRTVHARV_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define PMU_PMU16__OVR_DECRECTSTAGE_PRTVHARV_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define PMU_PMU16__OVR_DECRECTSTAGE_PRTVHARV_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field increctst_ctrcuMid0 */ +/** + * @defgroup pmu_top_regs_core_increctst_ctrcuMid0_field increctst_ctrcuMid0_field + * @brief macros for field increctst_ctrcuMid0 + * @details Mid current setting of chpuhsw_increctstage comparator when churge pump is disabled. + * @{ + */ +#define PMU_PMU16__INCRECTST_CTRCUMID0__SHIFT 14 +#define PMU_PMU16__INCRECTST_CTRCUMID0__WIDTH 1 +#define PMU_PMU16__INCRECTST_CTRCUMID0__MASK 0x00004000U +#define PMU_PMU16__INCRECTST_CTRCUMID0__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PMU_PMU16__INCRECTST_CTRCUMID0__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define PMU_PMU16__INCRECTST_CTRCUMID0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define PMU_PMU16__INCRECTST_CTRCUMID0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define PMU_PMU16__INCRECTST_CTRCUMID0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PMU_PMU16__INCRECTST_CTRCUMID0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PMU_PMU16__INCRECTST_CTRCUMID0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field increctst_ctrcuMid1 */ +/** + * @defgroup pmu_top_regs_core_increctst_ctrcuMid1_field increctst_ctrcuMid1_field + * @brief macros for field increctst_ctrcuMid1 + * @details Mid current setting of chpuhsw_increctstage comparator when churge pump is enabledNeed faster comparator response for Vharv protection. + * @{ + */ +#define PMU_PMU16__INCRECTST_CTRCUMID1__SHIFT 15 +#define PMU_PMU16__INCRECTST_CTRCUMID1__WIDTH 1 +#define PMU_PMU16__INCRECTST_CTRCUMID1__MASK 0x00008000U +#define PMU_PMU16__INCRECTST_CTRCUMID1__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define PMU_PMU16__INCRECTST_CTRCUMID1__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define PMU_PMU16__INCRECTST_CTRCUMID1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define PMU_PMU16__INCRECTST_CTRCUMID1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define PMU_PMU16__INCRECTST_CTRCUMID1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PMU_PMU16__INCRECTST_CTRCUMID1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PMU_PMU16__INCRECTST_CTRCUMID1__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field decrectst_ctrcuMid */ +/** + * @defgroup pmu_top_regs_core_decrectst_ctrcuMid_field decrectst_ctrcuMid_field + * @brief macros for field decrectst_ctrcuMid + * @details Mid current setting of decrectstage_prtVharv comparator + * @{ + */ +#define PMU_PMU16__DECRECTST_CTRCUMID__SHIFT 16 +#define PMU_PMU16__DECRECTST_CTRCUMID__WIDTH 1 +#define PMU_PMU16__DECRECTST_CTRCUMID__MASK 0x00010000U +#define PMU_PMU16__DECRECTST_CTRCUMID__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define PMU_PMU16__DECRECTST_CTRCUMID__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define PMU_PMU16__DECRECTST_CTRCUMID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define PMU_PMU16__DECRECTST_CTRCUMID__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define PMU_PMU16__DECRECTST_CTRCUMID__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PMU_PMU16__DECRECTST_CTRCUMID__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PMU_PMU16__DECRECTST_CTRCUMID__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field allowChrgInActive */ +/** + * @defgroup pmu_top_regs_core_allowChrgInActive_field allowChrgInActive_field + * @brief macros for field allowChrgInActive + * @details If set, the Vstore->Vbat charging can take place also in active state + * @{ + */ +#define PMU_PMU16__ALLOWCHRGINACTIVE__SHIFT 17 +#define PMU_PMU16__ALLOWCHRGINACTIVE__WIDTH 1 +#define PMU_PMU16__ALLOWCHRGINACTIVE__MASK 0x00020000U +#define PMU_PMU16__ALLOWCHRGINACTIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define PMU_PMU16__ALLOWCHRGINACTIVE__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define PMU_PMU16__ALLOWCHRGINACTIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define PMU_PMU16__ALLOWCHRGINACTIVE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define PMU_PMU16__ALLOWCHRGINACTIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define PMU_PMU16__ALLOWCHRGINACTIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define PMU_PMU16__ALLOWCHRGINACTIVE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ovr_ReqCanMustHarvb_zeromppt_ovr */ +/** + * @defgroup pmu_top_regs_core_ovr_ReqCanMustHarvb_zeromppt_ovr_field ovr_ReqCanMustHarvb_zeromppt_ovr_field + * @brief macros for field ovr_ReqCanMustHarvb_zeromppt_ovr + * @details override ovr_ReqCanMustHarvb_zeromppt + * @{ + */ +#define PMU_PMU16__OVR_REQCANMUSTHARVB_ZEROMPPT_OVR__SHIFT 18 +#define PMU_PMU16__OVR_REQCANMUSTHARVB_ZEROMPPT_OVR__WIDTH 1 +#define PMU_PMU16__OVR_REQCANMUSTHARVB_ZEROMPPT_OVR__MASK 0x00040000U +#define PMU_PMU16__OVR_REQCANMUSTHARVB_ZEROMPPT_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define PMU_PMU16__OVR_REQCANMUSTHARVB_ZEROMPPT_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define PMU_PMU16__OVR_REQCANMUSTHARVB_ZEROMPPT_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define PMU_PMU16__OVR_REQCANMUSTHARVB_ZEROMPPT_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define PMU_PMU16__OVR_REQCANMUSTHARVB_ZEROMPPT_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define PMU_PMU16__OVR_REQCANMUSTHARVB_ZEROMPPT_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define PMU_PMU16__OVR_REQCANMUSTHARVB_ZEROMPPT_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ovr_ReqCanMustHarvb_zeromppt_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ovr_ReqCanMustHarvb_zeromppt_ovr_val_field ovr_ReqCanMustHarvb_zeromppt_ovr_val_field + * @brief macros for field ovr_ReqCanMustHarvb_zeromppt_ovr_val + * @details override ovr_ReqCanMustHarvb_zeromppt val0: When the zerompptref is high, it forces can/mustharv requests to zero1: zerompptref has no effect on an/mustharv requests + * @{ + */ +#define PMU_PMU16__OVR_REQCANMUSTHARVB_ZEROMPPT_OVR_VAL__SHIFT 19 +#define PMU_PMU16__OVR_REQCANMUSTHARVB_ZEROMPPT_OVR_VAL__WIDTH 1 +#define PMU_PMU16__OVR_REQCANMUSTHARVB_ZEROMPPT_OVR_VAL__MASK 0x00080000U +#define PMU_PMU16__OVR_REQCANMUSTHARVB_ZEROMPPT_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define PMU_PMU16__OVR_REQCANMUSTHARVB_ZEROMPPT_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define PMU_PMU16__OVR_REQCANMUSTHARVB_ZEROMPPT_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define PMU_PMU16__OVR_REQCANMUSTHARVB_ZEROMPPT_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define PMU_PMU16__OVR_REQCANMUSTHARVB_ZEROMPPT_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define PMU_PMU16__OVR_REQCANMUSTHARVB_ZEROMPPT_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define PMU_PMU16__OVR_REQCANMUSTHARVB_ZEROMPPT_OVR_VAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field ovr_ReqHarvb_increcst_ovr */ +/** + * @defgroup pmu_top_regs_core_ovr_ReqHarvb_increcst_ovr_field ovr_ReqHarvb_increcst_ovr_field + * @brief macros for field ovr_ReqHarvb_increcst_ovr + * @details override ovr_ReqCanMustHarvb_increctst + * @{ + */ +#define PMU_PMU16__OVR_REQHARVB_INCRECST_OVR__SHIFT 20 +#define PMU_PMU16__OVR_REQHARVB_INCRECST_OVR__WIDTH 1 +#define PMU_PMU16__OVR_REQHARVB_INCRECST_OVR__MASK 0x00100000U +#define PMU_PMU16__OVR_REQHARVB_INCRECST_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define PMU_PMU16__OVR_REQHARVB_INCRECST_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define PMU_PMU16__OVR_REQHARVB_INCRECST_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define PMU_PMU16__OVR_REQHARVB_INCRECST_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define PMU_PMU16__OVR_REQHARVB_INCRECST_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define PMU_PMU16__OVR_REQHARVB_INCRECST_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define PMU_PMU16__OVR_REQHARVB_INCRECST_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ovr_ReqHarvb_increctst_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ovr_ReqHarvb_increctst_ovr_val_field ovr_ReqHarvb_increctst_ovr_val_field + * @brief macros for field ovr_ReqHarvb_increctst_ovr_val + * @details override ovr_ReqCanMustHarvb_increctst val0: When the chpuhswoff_increctstb is low, it forces can/mustharv requests to zero1: chpuhswoff_increctstb has no effect on an/mustharv requests + * @{ + */ +#define PMU_PMU16__OVR_REQHARVB_INCRECTST_OVR_VAL__SHIFT 21 +#define PMU_PMU16__OVR_REQHARVB_INCRECTST_OVR_VAL__WIDTH 1 +#define PMU_PMU16__OVR_REQHARVB_INCRECTST_OVR_VAL__MASK 0x00200000U +#define PMU_PMU16__OVR_REQHARVB_INCRECTST_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define PMU_PMU16__OVR_REQHARVB_INCRECTST_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define PMU_PMU16__OVR_REQHARVB_INCRECTST_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define PMU_PMU16__OVR_REQHARVB_INCRECTST_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define PMU_PMU16__OVR_REQHARVB_INCRECTST_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define PMU_PMU16__OVR_REQHARVB_INCRECTST_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define PMU_PMU16__OVR_REQHARVB_INCRECTST_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_ref_vbatreg_ovr */ +/** + * @defgroup pmu_top_regs_core_ctr_ref_vbatreg_ovr_field ctr_ref_vbatreg_ovr_field + * @brief macros for field ctr_ref_vbatreg_ovr + * @details override ctr_ref_vbatreg level + * @{ + */ +#define PMU_PMU16__CTR_REF_VBATREG_OVR__SHIFT 22 +#define PMU_PMU16__CTR_REF_VBATREG_OVR__WIDTH 1 +#define PMU_PMU16__CTR_REF_VBATREG_OVR__MASK 0x00400000U +#define PMU_PMU16__CTR_REF_VBATREG_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define PMU_PMU16__CTR_REF_VBATREG_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define PMU_PMU16__CTR_REF_VBATREG_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define PMU_PMU16__CTR_REF_VBATREG_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define PMU_PMU16__CTR_REF_VBATREG_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define PMU_PMU16__CTR_REF_VBATREG_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define PMU_PMU16__CTR_REF_VBATREG_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_ref_vbatreg_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ctr_ref_vbatreg_ovr_val_field ctr_ref_vbatreg_ovr_val_field + * @brief macros for field ctr_ref_vbatreg_ovr_val + * @details override value for VBATLI to VBATT LDO output level, 3.0V to 3.3V in 0.1V steps + * @{ + */ +#define PMU_PMU16__CTR_REF_VBATREG_OVR_VAL__SHIFT 23 +#define PMU_PMU16__CTR_REF_VBATREG_OVR_VAL__WIDTH 2 +#define PMU_PMU16__CTR_REF_VBATREG_OVR_VAL__MASK 0x01800000U +#define PMU_PMU16__CTR_REF_VBATREG_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x01800000U) >> 23) +#define PMU_PMU16__CTR_REF_VBATREG_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x01800000U) +#define PMU_PMU16__CTR_REF_VBATREG_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01800000U) | (((uint32_t)(src) <<\ + 23) & 0x01800000U) +#define PMU_PMU16__CTR_REF_VBATREG_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x01800000U))) +#define PMU_PMU16__CTR_REF_VBATREG_OVR_VAL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ctr_refcalpmuadc */ +/** + * @defgroup pmu_top_regs_core_ctr_refcalpmuadc_field ctr_refcalpmuadc_field + * @brief macros for field ctr_refcalpmuadc + * @details calibrate the output of the pmuadc reference buffer + * @{ + */ +#define PMU_PMU16__CTR_REFCALPMUADC__SHIFT 25 +#define PMU_PMU16__CTR_REFCALPMUADC__WIDTH 4 +#define PMU_PMU16__CTR_REFCALPMUADC__MASK 0x1e000000U +#define PMU_PMU16__CTR_REFCALPMUADC__READ(src) \ + (((uint32_t)(src)\ + & 0x1e000000U) >> 25) +#define PMU_PMU16__CTR_REFCALPMUADC__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x1e000000U) +#define PMU_PMU16__CTR_REFCALPMUADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1e000000U) | (((uint32_t)(src) <<\ + 25) & 0x1e000000U) +#define PMU_PMU16__CTR_REFCALPMUADC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x1e000000U))) +#define PMU_PMU16__CTR_REFCALPMUADC__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field pmuadc_enrefbuf */ +/** + * @defgroup pmu_top_regs_core_pmuadc_enrefbuf_field pmuadc_enrefbuf_field + * @brief macros for field pmuadc_enrefbuf + * @details enable the pmuadc reference buffer + * @{ + */ +#define PMU_PMU16__PMUADC_ENREFBUF__SHIFT 29 +#define PMU_PMU16__PMUADC_ENREFBUF__WIDTH 1 +#define PMU_PMU16__PMUADC_ENREFBUF__MASK 0x20000000U +#define PMU_PMU16__PMUADC_ENREFBUF__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define PMU_PMU16__PMUADC_ENREFBUF__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define PMU_PMU16__PMUADC_ENREFBUF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define PMU_PMU16__PMUADC_ENREFBUF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define PMU_PMU16__PMUADC_ENREFBUF__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define PMU_PMU16__PMUADC_ENREFBUF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define PMU_PMU16__PMUADC_ENREFBUF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pmuadc_byrefbuf */ +/** + * @defgroup pmu_top_regs_core_pmuadc_byrefbuf_field pmuadc_byrefbuf_field + * @brief macros for field pmuadc_byrefbuf + * @details bypass the pmuadc reference buffer + * @{ + */ +#define PMU_PMU16__PMUADC_BYREFBUF__SHIFT 30 +#define PMU_PMU16__PMUADC_BYREFBUF__WIDTH 1 +#define PMU_PMU16__PMUADC_BYREFBUF__MASK 0x40000000U +#define PMU_PMU16__PMUADC_BYREFBUF__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define PMU_PMU16__PMUADC_BYREFBUF__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define PMU_PMU16__PMUADC_BYREFBUF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define PMU_PMU16__PMUADC_BYREFBUF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define PMU_PMU16__PMUADC_BYREFBUF__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define PMU_PMU16__PMUADC_BYREFBUF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define PMU_PMU16__PMUADC_BYREFBUF__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field chargeBatt */ +/** + * @defgroup pmu_top_regs_core_chargeBatt_field chargeBatt_field + * @brief macros for field chargeBatt + * @details Enable the VSTO->VBAT mode. Also unmasks the pmuadc indicator to set buck, boost for VSTO->VBAT. + * @{ + */ +#define PMU_PMU16__CHARGEBATT__SHIFT 31 +#define PMU_PMU16__CHARGEBATT__WIDTH 1 +#define PMU_PMU16__CHARGEBATT__MASK 0x80000000U +#define PMU_PMU16__CHARGEBATT__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define PMU_PMU16__CHARGEBATT__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define PMU_PMU16__CHARGEBATT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define PMU_PMU16__CHARGEBATT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define PMU_PMU16__CHARGEBATT__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define PMU_PMU16__CHARGEBATT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define PMU_PMU16__CHARGEBATT__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU16__TYPE uint32_t +#define PMU_PMU16__READ 0xffffffffU +#define PMU_PMU16__WRITE 0xffffffffU +#define PMU_PMU16__PRESERVED 0x00000000U +#define PMU_PMU16__RESET_VALUE 0x4e808039U + +#endif /* __PMU_PMU16_MACRO__ */ + +/** @} end of pmu16 */ + +/* macros for BlueprintGlobalNameSpace::PMU_chrg_ctrl */ +/** + * @defgroup pmu_top_regs_core_chrg_ctrl chrg_ctrl + * @brief Charger control bits definitions. + * @{ + */ +#ifndef __PMU_CHRG_CTRL_MACRO__ +#define __PMU_CHRG_CTRL_MACRO__ + +/* macros for field disable_chrg_ovr */ +/** + * @defgroup pmu_top_regs_core_disable_chrg_ovr_field disable_chrg_ovr_field + * @brief macros for field disable_chrg_ovr + * @details force disable all charging controls + * @{ + */ +#define PMU_CHRG_CTRL__DISABLE_CHRG_OVR__SHIFT 0 +#define PMU_CHRG_CTRL__DISABLE_CHRG_OVR__WIDTH 1 +#define PMU_CHRG_CTRL__DISABLE_CHRG_OVR__MASK 0x00000001U +#define PMU_CHRG_CTRL__DISABLE_CHRG_OVR__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PMU_CHRG_CTRL__DISABLE_CHRG_OVR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PMU_CHRG_CTRL__DISABLE_CHRG_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PMU_CHRG_CTRL__DISABLE_CHRG_OVR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PMU_CHRG_CTRL__DISABLE_CHRG_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PMU_CHRG_CTRL__DISABLE_CHRG_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PMU_CHRG_CTRL__DISABLE_CHRG_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field chrg_timer_start */ +/** + * @defgroup pmu_top_regs_core_chrg_timer_start_field chrg_timer_start_field + * @brief macros for field chrg_timer_start + * @details Set high for at least 50us and then clear to restart timeout counterThis will start charging and make the configuration settings below take effectSW needs to toggle this bit before charger timeout countdown timer expires to keep charging going + * @{ + */ +#define PMU_CHRG_CTRL__CHRG_TIMER_START__SHIFT 1 +#define PMU_CHRG_CTRL__CHRG_TIMER_START__WIDTH 1 +#define PMU_CHRG_CTRL__CHRG_TIMER_START__MASK 0x00000002U +#define PMU_CHRG_CTRL__CHRG_TIMER_START__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define PMU_CHRG_CTRL__CHRG_TIMER_START__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define PMU_CHRG_CTRL__CHRG_TIMER_START__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define PMU_CHRG_CTRL__CHRG_TIMER_START__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define PMU_CHRG_CTRL__CHRG_TIMER_START__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define PMU_CHRG_CTRL__CHRG_TIMER_START__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define PMU_CHRG_CTRL__CHRG_TIMER_START__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field chrg_timeout */ +/** + * @defgroup pmu_top_regs_core_chrg_timeout_field chrg_timeout_field + * @brief macros for field chrg_timeout + * @details Charger timeout countdown timer value in seconds, should be set longer than any battery measurement/charger settings update rate + * @{ + */ +#define PMU_CHRG_CTRL__CHRG_TIMEOUT__SHIFT 2 +#define PMU_CHRG_CTRL__CHRG_TIMEOUT__WIDTH 11 +#define PMU_CHRG_CTRL__CHRG_TIMEOUT__MASK 0x00001ffcU +#define PMU_CHRG_CTRL__CHRG_TIMEOUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00001ffcU) >> 2) +#define PMU_CHRG_CTRL__CHRG_TIMEOUT__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00001ffcU) +#define PMU_CHRG_CTRL__CHRG_TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001ffcU) | (((uint32_t)(src) <<\ + 2) & 0x00001ffcU) +#define PMU_CHRG_CTRL__CHRG_TIMEOUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00001ffcU))) +#define PMU_CHRG_CTRL__CHRG_TIMEOUT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_chrg_curr */ +/** + * @defgroup pmu_top_regs_core_en_chrg_curr_field en_chrg_curr_field + * @brief macros for field en_chrg_curr + * @details Enable charger current source from VSTORE->VBATT + * @{ + */ +#define PMU_CHRG_CTRL__EN_CHRG_CURR__SHIFT 13 +#define PMU_CHRG_CTRL__EN_CHRG_CURR__WIDTH 1 +#define PMU_CHRG_CTRL__EN_CHRG_CURR__MASK 0x00002000U +#define PMU_CHRG_CTRL__EN_CHRG_CURR__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define PMU_CHRG_CTRL__EN_CHRG_CURR__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define PMU_CHRG_CTRL__EN_CHRG_CURR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define PMU_CHRG_CTRL__EN_CHRG_CURR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define PMU_CHRG_CTRL__EN_CHRG_CURR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define PMU_CHRG_CTRL__EN_CHRG_CURR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define PMU_CHRG_CTRL__EN_CHRG_CURR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_chrgcurr */ +/** + * @defgroup pmu_top_regs_core_ctr_chrgcurr_field ctr_chrgcurr_field + * @brief macros for field ctr_chrgcurr + * @details Charge current source value, approx 60uA to 15mA in 60uA steps for VSTORE->VBATT path + * @{ + */ +#define PMU_CHRG_CTRL__CTR_CHRGCURR__SHIFT 14 +#define PMU_CHRG_CTRL__CTR_CHRGCURR__WIDTH 8 +#define PMU_CHRG_CTRL__CTR_CHRGCURR__MASK 0x003fc000U +#define PMU_CHRG_CTRL__CTR_CHRGCURR__READ(src) \ + (((uint32_t)(src)\ + & 0x003fc000U) >> 14) +#define PMU_CHRG_CTRL__CTR_CHRGCURR__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x003fc000U) +#define PMU_CHRG_CTRL__CTR_CHRGCURR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fc000U) | (((uint32_t)(src) <<\ + 14) & 0x003fc000U) +#define PMU_CHRG_CTRL__CTR_CHRGCURR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x003fc000U))) +#define PMU_CHRG_CTRL__CTR_CHRGCURR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_VstoVbat */ +/** + * @defgroup pmu_top_regs_core_en_VstoVbat_field en_VstoVbat_field + * @brief macros for field en_VstoVbat + * @details Enable VSTORE->VBATT charger current source path + * @{ + */ +#define PMU_CHRG_CTRL__EN_VSTOVBAT__SHIFT 22 +#define PMU_CHRG_CTRL__EN_VSTOVBAT__WIDTH 1 +#define PMU_CHRG_CTRL__EN_VSTOVBAT__MASK 0x00400000U +#define PMU_CHRG_CTRL__EN_VSTOVBAT__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define PMU_CHRG_CTRL__EN_VSTOVBAT__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define PMU_CHRG_CTRL__EN_VSTOVBAT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define PMU_CHRG_CTRL__EN_VSTOVBAT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define PMU_CHRG_CTRL__EN_VSTOVBAT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define PMU_CHRG_CTRL__EN_VSTOVBAT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define PMU_CHRG_CTRL__EN_VSTOVBAT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field unused */ +/** + * @defgroup pmu_top_regs_core_unused_field unused_field + * @brief macros for field unused + * @details Unused + * @{ + */ +#define PMU_CHRG_CTRL__UNUSED__SHIFT 23 +#define PMU_CHRG_CTRL__UNUSED__WIDTH 1 +#define PMU_CHRG_CTRL__UNUSED__MASK 0x00800000U +#define PMU_CHRG_CTRL__UNUSED__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PMU_CHRG_CTRL__UNUSED__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define PMU_CHRG_CTRL__UNUSED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define PMU_CHRG_CTRL__UNUSED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define PMU_CHRG_CTRL__UNUSED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PMU_CHRG_CTRL__UNUSED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PMU_CHRG_CTRL__UNUSED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enampchrg */ +/** + * @defgroup pmu_top_regs_core_enampchrg_field enampchrg_field + * @brief macros for field enampchrg + * @details Unused + * @{ + */ +#define PMU_CHRG_CTRL__ENAMPCHRG__SHIFT 24 +#define PMU_CHRG_CTRL__ENAMPCHRG__WIDTH 1 +#define PMU_CHRG_CTRL__ENAMPCHRG__MASK 0x01000000U +#define PMU_CHRG_CTRL__ENAMPCHRG__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define PMU_CHRG_CTRL__ENAMPCHRG__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define PMU_CHRG_CTRL__ENAMPCHRG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define PMU_CHRG_CTRL__ENAMPCHRG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define PMU_CHRG_CTRL__ENAMPCHRG__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define PMU_CHRG_CTRL__ENAMPCHRG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define PMU_CHRG_CTRL__ENAMPCHRG__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bypvstovbatli */ +/** + * @defgroup pmu_top_regs_core_bypvstovbatli_field bypvstovbatli_field + * @brief macros for field bypvstovbatli + * @details Short VSTORE to VBATLI, should only be enabled if VBATLI is within OV and UV ranges + * @{ + */ +#define PMU_CHRG_CTRL__BYPVSTOVBATLI__SHIFT 25 +#define PMU_CHRG_CTRL__BYPVSTOVBATLI__WIDTH 1 +#define PMU_CHRG_CTRL__BYPVSTOVBATLI__MASK 0x02000000U +#define PMU_CHRG_CTRL__BYPVSTOVBATLI__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define PMU_CHRG_CTRL__BYPVSTOVBATLI__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define PMU_CHRG_CTRL__BYPVSTOVBATLI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define PMU_CHRG_CTRL__BYPVSTOVBATLI__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define PMU_CHRG_CTRL__BYPVSTOVBATLI__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define PMU_CHRG_CTRL__BYPVSTOVBATLI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define PMU_CHRG_CTRL__BYPVSTOVBATLI__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_chrgpmosbyp */ +/** + * @defgroup pmu_top_regs_core_ctr_chrgpmosbyp_field ctr_chrgpmosbyp_field + * @brief macros for field ctr_chrgpmosbyp + * @details Short VSTORE to VBATT and bypass charger current source + * @{ + */ +#define PMU_CHRG_CTRL__CTR_CHRGPMOSBYP__SHIFT 26 +#define PMU_CHRG_CTRL__CTR_CHRGPMOSBYP__WIDTH 1 +#define PMU_CHRG_CTRL__CTR_CHRGPMOSBYP__MASK 0x04000000U +#define PMU_CHRG_CTRL__CTR_CHRGPMOSBYP__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define PMU_CHRG_CTRL__CTR_CHRGPMOSBYP__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define PMU_CHRG_CTRL__CTR_CHRGPMOSBYP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define PMU_CHRG_CTRL__CTR_CHRGPMOSBYP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define PMU_CHRG_CTRL__CTR_CHRGPMOSBYP__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define PMU_CHRG_CTRL__CTR_CHRGPMOSBYP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define PMU_CHRG_CTRL__CTR_CHRGPMOSBYP__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_CHRG_CTRL__TYPE uint32_t +#define PMU_CHRG_CTRL__READ 0x07ffffffU +#define PMU_CHRG_CTRL__WRITE 0x07ffffffU +#define PMU_CHRG_CTRL__PRESERVED 0x00000000U +#define PMU_CHRG_CTRL__RESET_VALUE 0x00000000U + +#endif /* __PMU_CHRG_CTRL_MACRO__ */ + +/** @} end of chrg_ctrl */ + +/* macros for BlueprintGlobalNameSpace::PMU_chrg_ctrl2 */ +/** + * @defgroup pmu_top_regs_core_chrg_ctrl2 chrg_ctrl2 + * @brief More charger control bits definitions. + * @{ + */ +#ifndef __PMU_CHRG_CTRL2_MACRO__ +#define __PMU_CHRG_CTRL2_MACRO__ + +/* macros for field ctr_VrefstoGoodToChrg */ +/** + * @defgroup pmu_top_regs_core_ctr_VrefstoGoodToChrg_field ctr_VrefstoGoodToChrg_field + * @brief macros for field ctr_VrefstoGoodToChrg + * @details VSTORE level above which to enable external charge pump clock in pmuadc units, = round[(vstore voltage - 600mv)/25mv]There will be another 100mV rising hysteresis included in the comparisonDefault setting for VSTORE = 3.0V with 100mV hysteresis = charge pump turns on at 3.1V and shuts off at 3.0V + * @{ + */ +#define PMU_CHRG_CTRL2__CTR_VREFSTOGOODTOCHRG__SHIFT 0 +#define PMU_CHRG_CTRL2__CTR_VREFSTOGOODTOCHRG__WIDTH 7 +#define PMU_CHRG_CTRL2__CTR_VREFSTOGOODTOCHRG__MASK 0x0000007fU +#define PMU_CHRG_CTRL2__CTR_VREFSTOGOODTOCHRG__READ(src) \ + ((uint32_t)(src)\ + & 0x0000007fU) +#define PMU_CHRG_CTRL2__CTR_VREFSTOGOODTOCHRG__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000007fU) +#define PMU_CHRG_CTRL2__CTR_VREFSTOGOODTOCHRG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define PMU_CHRG_CTRL2__CTR_VREFSTOGOODTOCHRG__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000007fU))) +#define PMU_CHRG_CTRL2__CTR_VREFSTOGOODTOCHRG__RESET_VALUE 0x00000060U +/** @} */ + +/* macros for field en_clk_cp */ +/** + * @defgroup pmu_top_regs_core_en_clk_cp_field en_clk_cp_field + * @brief macros for field en_clk_cp + * @details Enable clock to drive external charge pump, this clock needs to be separately brought out to a GPIO through pin mux settingClock only actually runs if VSTORE is above ctr_VrefstoGoodToChrg level when this bit is enabled + * @{ + */ +#define PMU_CHRG_CTRL2__EN_CLK_CP__SHIFT 7 +#define PMU_CHRG_CTRL2__EN_CLK_CP__WIDTH 1 +#define PMU_CHRG_CTRL2__EN_CLK_CP__MASK 0x00000080U +#define PMU_CHRG_CTRL2__EN_CLK_CP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define PMU_CHRG_CTRL2__EN_CLK_CP__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define PMU_CHRG_CTRL2__EN_CLK_CP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define PMU_CHRG_CTRL2__EN_CLK_CP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define PMU_CHRG_CTRL2__EN_CLK_CP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define PMU_CHRG_CTRL2__EN_CLK_CP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define PMU_CHRG_CTRL2__EN_CLK_CP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field unused */ +/** + * @defgroup pmu_top_regs_core_unused_field unused_field + * @brief macros for field unused + * @details unused, pmu_spares[5:0] + * @{ + */ +#define PMU_CHRG_CTRL2__UNUSED__SHIFT 8 +#define PMU_CHRG_CTRL2__UNUSED__WIDTH 6 +#define PMU_CHRG_CTRL2__UNUSED__MASK 0x00003f00U +#define PMU_CHRG_CTRL2__UNUSED__READ(src) \ + (((uint32_t)(src)\ + & 0x00003f00U) >> 8) +#define PMU_CHRG_CTRL2__UNUSED__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00003f00U) +#define PMU_CHRG_CTRL2__UNUSED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((uint32_t)(src) <<\ + 8) & 0x00003f00U) +#define PMU_CHRG_CTRL2__UNUSED__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00003f00U))) +#define PMU_CHRG_CTRL2__UNUSED__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_CHRG_CTRL2__TYPE uint32_t +#define PMU_CHRG_CTRL2__READ 0x00003fffU +#define PMU_CHRG_CTRL2__WRITE 0x00003fffU +#define PMU_CHRG_CTRL2__PRESERVED 0x00000000U +#define PMU_CHRG_CTRL2__RESET_VALUE 0x00000060U + +#endif /* __PMU_CHRG_CTRL2_MACRO__ */ + +/** @} end of chrg_ctrl2 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu17 */ +/** + * @defgroup pmu_top_regs_core_pmu17 pmu17 + * @brief spares definitions. + * @{ + */ +#ifndef __PMU_PMU17_MACRO__ +#define __PMU_PMU17_MACRO__ + +/* macros for field off_trans_wait_reg */ +/** + * @defgroup pmu_top_regs_core_off_trans_wait_reg_field off_trans_wait_reg_field + * @brief macros for field off_trans_wait_reg + * @details spare bits6..0 off_trans_wait_reg7 override en_refgen_pre8 override val for en_refgen_pre9 override Harvest 1 rectifier enable10 override val for Harvest 1 resctifier enable11 override ctr_refextend_out12 override val for ctr_refextend_out13 override for isolate_b_pre, not used on paris14 override for wake_only_if_enough_energy15 override for energyGood_out1, not used in paris + * @{ + */ +#define PMU_PMU17__OFF_TRANS_WAIT_REG__SHIFT 0 +#define PMU_PMU17__OFF_TRANS_WAIT_REG__WIDTH 7 +#define PMU_PMU17__OFF_TRANS_WAIT_REG__MASK 0x0000007fU +#define PMU_PMU17__OFF_TRANS_WAIT_REG__READ(src) \ + ((uint32_t)(src)\ + & 0x0000007fU) +#define PMU_PMU17__OFF_TRANS_WAIT_REG__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000007fU) +#define PMU_PMU17__OFF_TRANS_WAIT_REG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define PMU_PMU17__OFF_TRANS_WAIT_REG__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000007fU))) +#define PMU_PMU17__OFF_TRANS_WAIT_REG__RESET_VALUE 0x0000006eU +/** @} */ + +/* macros for field en_refgen_pre_ovr */ +/** + * @defgroup pmu_top_regs_core_en_refgen_pre_ovr_field en_refgen_pre_ovr_field + * @brief macros for field en_refgen_pre_ovr + * @details spare bits6..0 off_trans_wait_reg7 override en_refgen_pre8 override val for en_refgen_pre9 override Harvest 1 rectifier enable10 override val for Harvest 1 resctifier enable11 override ctr_refextend_out12 override val for ctr_refextend_out13 override for isolate_b_pre, not used on paris14 override for wake_only_if_enough_energy15 override for energyGood_out1, not used in paris + * @{ + */ +#define PMU_PMU17__EN_REFGEN_PRE_OVR__SHIFT 7 +#define PMU_PMU17__EN_REFGEN_PRE_OVR__WIDTH 1 +#define PMU_PMU17__EN_REFGEN_PRE_OVR__MASK 0x00000080U +#define PMU_PMU17__EN_REFGEN_PRE_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define PMU_PMU17__EN_REFGEN_PRE_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define PMU_PMU17__EN_REFGEN_PRE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define PMU_PMU17__EN_REFGEN_PRE_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define PMU_PMU17__EN_REFGEN_PRE_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define PMU_PMU17__EN_REFGEN_PRE_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define PMU_PMU17__EN_REFGEN_PRE_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_refgen_pre_ovr_val */ +/** + * @defgroup pmu_top_regs_core_en_refgen_pre_ovr_val_field en_refgen_pre_ovr_val_field + * @brief macros for field en_refgen_pre_ovr_val + * @details spare bits6..0 off_trans_wait_reg7 override en_refgen_pre8 override val for en_refgen_pre9 override Harvest 1 rectifier enable10 override val for Harvest 1 resctifier enable11 override ctr_refextend_out12 override val for ctr_refextend_out13 override for isolate_b_pre, not used on paris14 override for wake_only_if_enough_energy15 override for energyGood_out1, not used in paris + * @{ + */ +#define PMU_PMU17__EN_REFGEN_PRE_OVR_VAL__SHIFT 8 +#define PMU_PMU17__EN_REFGEN_PRE_OVR_VAL__WIDTH 1 +#define PMU_PMU17__EN_REFGEN_PRE_OVR_VAL__MASK 0x00000100U +#define PMU_PMU17__EN_REFGEN_PRE_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define PMU_PMU17__EN_REFGEN_PRE_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define PMU_PMU17__EN_REFGEN_PRE_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define PMU_PMU17__EN_REFGEN_PRE_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define PMU_PMU17__EN_REFGEN_PRE_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define PMU_PMU17__EN_REFGEN_PRE_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define PMU_PMU17__EN_REFGEN_PRE_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field harv1_rect_en_ovr */ +/** + * @defgroup pmu_top_regs_core_harv1_rect_en_ovr_field harv1_rect_en_ovr_field + * @brief macros for field harv1_rect_en_ovr + * @details spare bits6..0 off_trans_wait_reg7 override en_refgen_pre8 override val for en_refgen_pre9 override Harvest 1 rectifier enable10 override val for Harvest 1 resctifier enable11 override ctr_refextend_out12 override val for ctr_refextend_out13 override for isolate_b_pre, not used on paris14 override for wake_only_if_enough_energy15 override for energyGood_out1, not used in paris + * @{ + */ +#define PMU_PMU17__HARV1_RECT_EN_OVR__SHIFT 9 +#define PMU_PMU17__HARV1_RECT_EN_OVR__WIDTH 1 +#define PMU_PMU17__HARV1_RECT_EN_OVR__MASK 0x00000200U +#define PMU_PMU17__HARV1_RECT_EN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define PMU_PMU17__HARV1_RECT_EN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define PMU_PMU17__HARV1_RECT_EN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define PMU_PMU17__HARV1_RECT_EN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define PMU_PMU17__HARV1_RECT_EN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define PMU_PMU17__HARV1_RECT_EN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define PMU_PMU17__HARV1_RECT_EN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field harv1_rect_en_ovr_val */ +/** + * @defgroup pmu_top_regs_core_harv1_rect_en_ovr_val_field harv1_rect_en_ovr_val_field + * @brief macros for field harv1_rect_en_ovr_val + * @details spare bits6..0 off_trans_wait_reg7 override en_refgen_pre8 override val for en_refgen_pre9 override Harvest 1 rectifier enable10 override val for Harvest 1 resctifier enable11 override ctr_refextend_out12 override val for ctr_refextend_out13 override for isolate_b_pre, not used on paris14 override for wake_only_if_enough_energy15 override for energyGood_out1, not used in paris + * @{ + */ +#define PMU_PMU17__HARV1_RECT_EN_OVR_VAL__SHIFT 10 +#define PMU_PMU17__HARV1_RECT_EN_OVR_VAL__WIDTH 1 +#define PMU_PMU17__HARV1_RECT_EN_OVR_VAL__MASK 0x00000400U +#define PMU_PMU17__HARV1_RECT_EN_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define PMU_PMU17__HARV1_RECT_EN_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define PMU_PMU17__HARV1_RECT_EN_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define PMU_PMU17__HARV1_RECT_EN_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define PMU_PMU17__HARV1_RECT_EN_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define PMU_PMU17__HARV1_RECT_EN_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define PMU_PMU17__HARV1_RECT_EN_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_refextend_out_ovr */ +/** + * @defgroup pmu_top_regs_core_ctr_refextend_out_ovr_field ctr_refextend_out_ovr_field + * @brief macros for field ctr_refextend_out_ovr + * @details spare bits6..0 off_trans_wait_reg7 override en_refgen_pre8 override val for en_refgen_pre9 override Harvest 1 rectifier enable10 override val for Harvest 1 resctifier enable11 override ctr_refextend_out12 override val for ctr_refextend_out13 override for isolate_b_pre, not used on paris14 override for wake_only_if_enough_energy15 override for energyGood_out1, not used in paris + * @{ + */ +#define PMU_PMU17__CTR_REFEXTEND_OUT_OVR__SHIFT 11 +#define PMU_PMU17__CTR_REFEXTEND_OUT_OVR__WIDTH 1 +#define PMU_PMU17__CTR_REFEXTEND_OUT_OVR__MASK 0x00000800U +#define PMU_PMU17__CTR_REFEXTEND_OUT_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define PMU_PMU17__CTR_REFEXTEND_OUT_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define PMU_PMU17__CTR_REFEXTEND_OUT_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define PMU_PMU17__CTR_REFEXTEND_OUT_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define PMU_PMU17__CTR_REFEXTEND_OUT_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define PMU_PMU17__CTR_REFEXTEND_OUT_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define PMU_PMU17__CTR_REFEXTEND_OUT_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_refextend_out_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ctr_refextend_out_ovr_val_field ctr_refextend_out_ovr_val_field + * @brief macros for field ctr_refextend_out_ovr_val + * @details spare bits6..0 off_trans_wait_reg7 override en_refgen_pre8 override val for en_refgen_pre9 override Harvest 1 rectifier enable10 override val for Harvest 1 resctifier enable11 override ctr_refextend_out12 override val for ctr_refextend_out13 override for isolate_b_pre, not used on paris14 override for wake_only_if_enough_energy15 override for energyGood_out1, not used in paris + * @{ + */ +#define PMU_PMU17__CTR_REFEXTEND_OUT_OVR_VAL__SHIFT 12 +#define PMU_PMU17__CTR_REFEXTEND_OUT_OVR_VAL__WIDTH 1 +#define PMU_PMU17__CTR_REFEXTEND_OUT_OVR_VAL__MASK 0x00001000U +#define PMU_PMU17__CTR_REFEXTEND_OUT_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define PMU_PMU17__CTR_REFEXTEND_OUT_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define PMU_PMU17__CTR_REFEXTEND_OUT_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define PMU_PMU17__CTR_REFEXTEND_OUT_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define PMU_PMU17__CTR_REFEXTEND_OUT_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define PMU_PMU17__CTR_REFEXTEND_OUT_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define PMU_PMU17__CTR_REFEXTEND_OUT_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field force_isolate_b_pre */ +/** + * @defgroup pmu_top_regs_core_force_isolate_b_pre_field force_isolate_b_pre_field + * @brief macros for field force_isolate_b_pre + * @details spare bits6..0 off_trans_wait_reg7 override en_refgen_pre8 override val for en_refgen_pre9 override Harvest 1 rectifier enable10 override val for Harvest 1 resctifier enable11 override ctr_refextend_out12 override val for ctr_refextend_out13 override for isolate_b_pre, not used on paris14 override for wake_only_if_enough_energy15 override for energyGood_out1, not used in paris + * @{ + */ +#define PMU_PMU17__FORCE_ISOLATE_B_PRE__SHIFT 13 +#define PMU_PMU17__FORCE_ISOLATE_B_PRE__WIDTH 1 +#define PMU_PMU17__FORCE_ISOLATE_B_PRE__MASK 0x00002000U +#define PMU_PMU17__FORCE_ISOLATE_B_PRE__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define PMU_PMU17__FORCE_ISOLATE_B_PRE__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define PMU_PMU17__FORCE_ISOLATE_B_PRE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define PMU_PMU17__FORCE_ISOLATE_B_PRE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define PMU_PMU17__FORCE_ISOLATE_B_PRE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define PMU_PMU17__FORCE_ISOLATE_B_PRE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define PMU_PMU17__FORCE_ISOLATE_B_PRE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wake_only_if_enough_energy */ +/** + * @defgroup pmu_top_regs_core_wake_only_if_enough_energy_field wake_only_if_enough_energy_field + * @brief macros for field wake_only_if_enough_energy + * @details spare bits6..0 off_trans_wait_reg7 override en_refgen_pre8 override val for en_refgen_pre9 override Harvest 1 rectifier enable10 override val for Harvest 1 resctifier enable11 override ctr_refextend_out12 override val for ctr_refextend_out13 override for isolate_b_pre, not used on paris14 override for wake_only_if_enough_energy15 override for energyGood_out1, not used in paris + * @{ + */ +#define PMU_PMU17__WAKE_ONLY_IF_ENOUGH_ENERGY__SHIFT 14 +#define PMU_PMU17__WAKE_ONLY_IF_ENOUGH_ENERGY__WIDTH 1 +#define PMU_PMU17__WAKE_ONLY_IF_ENOUGH_ENERGY__MASK 0x00004000U +#define PMU_PMU17__WAKE_ONLY_IF_ENOUGH_ENERGY__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PMU_PMU17__WAKE_ONLY_IF_ENOUGH_ENERGY__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define PMU_PMU17__WAKE_ONLY_IF_ENOUGH_ENERGY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define PMU_PMU17__WAKE_ONLY_IF_ENOUGH_ENERGY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define PMU_PMU17__WAKE_ONLY_IF_ENOUGH_ENERGY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PMU_PMU17__WAKE_ONLY_IF_ENOUGH_ENERGY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PMU_PMU17__WAKE_ONLY_IF_ENOUGH_ENERGY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field force_energyGood_out1 */ +/** + * @defgroup pmu_top_regs_core_force_energyGood_out1_field force_energyGood_out1_field + * @brief macros for field force_energyGood_out1 + * @details spare bits6..0 off_trans_wait_reg7 override en_refgen_pre8 override val for en_refgen_pre9 override Harvest 1 rectifier enable10 override val for Harvest 1 resctifier enable11 override ctr_refextend_out12 override val for ctr_refextend_out13 override for isolate_b_pre, not used on paris14 override for wake_only_if_enough_energy15 override for energyGood_out1, not used in paris + * @{ + */ +#define PMU_PMU17__FORCE_ENERGYGOOD_OUT1__SHIFT 15 +#define PMU_PMU17__FORCE_ENERGYGOOD_OUT1__WIDTH 1 +#define PMU_PMU17__FORCE_ENERGYGOOD_OUT1__MASK 0x00008000U +#define PMU_PMU17__FORCE_ENERGYGOOD_OUT1__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define PMU_PMU17__FORCE_ENERGYGOOD_OUT1__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define PMU_PMU17__FORCE_ENERGYGOOD_OUT1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define PMU_PMU17__FORCE_ENERGYGOOD_OUT1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define PMU_PMU17__FORCE_ENERGYGOOD_OUT1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PMU_PMU17__FORCE_ENERGYGOOD_OUT1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PMU_PMU17__FORCE_ENERGYGOOD_OUT1__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field zerompptref_forceb */ +/** + * @defgroup pmu_top_regs_core_zerompptref_forceb_field zerompptref_forceb_field + * @brief macros for field zerompptref_forceb + * @details new sparebits0 zerompptref_forceb1 override ctr_maxref1v32 override val for ctr_maxref1v33 override en_refgenfast4 override val for en_refgenfast6:5 00 = mpptDone, 01 = mpptStart, 10 = zerompptref, 11 = mppt_freeze7 mpptStart_ovr8 mpptStart_ovr_val9 ctr_cuFast_ovr11:10 ctr_cuFast_ovr_val12 Software_mpptEvent + * @{ + */ +#define PMU_PMU17__ZEROMPPTREF_FORCEB__SHIFT 16 +#define PMU_PMU17__ZEROMPPTREF_FORCEB__WIDTH 1 +#define PMU_PMU17__ZEROMPPTREF_FORCEB__MASK 0x00010000U +#define PMU_PMU17__ZEROMPPTREF_FORCEB__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define PMU_PMU17__ZEROMPPTREF_FORCEB__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define PMU_PMU17__ZEROMPPTREF_FORCEB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define PMU_PMU17__ZEROMPPTREF_FORCEB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define PMU_PMU17__ZEROMPPTREF_FORCEB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PMU_PMU17__ZEROMPPTREF_FORCEB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PMU_PMU17__ZEROMPPTREF_FORCEB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_maxref1v3_ovr */ +/** + * @defgroup pmu_top_regs_core_ctr_maxref1v3_ovr_field ctr_maxref1v3_ovr_field + * @brief macros for field ctr_maxref1v3_ovr + * @details new sparebits0 zerompptref_forceb1 override ctr_maxref1v32 override val for ctr_maxref1v33 override en_refgenfast4 override val for en_refgenfast6:5 00 = mpptDone, 01 = mpptStart, 10 = zerompptref, 11 = mppt_freeze7 mpptStart_ovr8 mpptStart_ovr_val9 ctr_cuFast_ovr11:10 ctr_cuFast_ovr_val12 Software_mpptEvent + * @{ + */ +#define PMU_PMU17__CTR_MAXREF1V3_OVR__SHIFT 17 +#define PMU_PMU17__CTR_MAXREF1V3_OVR__WIDTH 1 +#define PMU_PMU17__CTR_MAXREF1V3_OVR__MASK 0x00020000U +#define PMU_PMU17__CTR_MAXREF1V3_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define PMU_PMU17__CTR_MAXREF1V3_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define PMU_PMU17__CTR_MAXREF1V3_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define PMU_PMU17__CTR_MAXREF1V3_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define PMU_PMU17__CTR_MAXREF1V3_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define PMU_PMU17__CTR_MAXREF1V3_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define PMU_PMU17__CTR_MAXREF1V3_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_maxref1v3_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ctr_maxref1v3_ovr_val_field ctr_maxref1v3_ovr_val_field + * @brief macros for field ctr_maxref1v3_ovr_val + * @details new sparebits0 zerompptref_forceb1 override ctr_maxref1v32 override val for ctr_maxref1v33 override en_refgenfast4 override val for en_refgenfast6:5 00 = mpptDone, 01 = mpptStart, 10 = zerompptref, 11 = mppt_freeze7 mpptStart_ovr8 mpptStart_ovr_val9 ctr_cuFast_ovr11:10 ctr_cuFast_ovr_val12 Software_mpptEvent + * @{ + */ +#define PMU_PMU17__CTR_MAXREF1V3_OVR_VAL__SHIFT 18 +#define PMU_PMU17__CTR_MAXREF1V3_OVR_VAL__WIDTH 1 +#define PMU_PMU17__CTR_MAXREF1V3_OVR_VAL__MASK 0x00040000U +#define PMU_PMU17__CTR_MAXREF1V3_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define PMU_PMU17__CTR_MAXREF1V3_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define PMU_PMU17__CTR_MAXREF1V3_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define PMU_PMU17__CTR_MAXREF1V3_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define PMU_PMU17__CTR_MAXREF1V3_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define PMU_PMU17__CTR_MAXREF1V3_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define PMU_PMU17__CTR_MAXREF1V3_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_refgenfast_ovr */ +/** + * @defgroup pmu_top_regs_core_en_refgenfast_ovr_field en_refgenfast_ovr_field + * @brief macros for field en_refgenfast_ovr + * @details new sparebits0 zerompptref_forceb1 override ctr_maxref1v32 override val for ctr_maxref1v33 override en_refgenfast4 override val for en_refgenfast6:5 00 = mpptDone, 01 = mpptStart, 10 = zerompptref, 11 = mppt_freeze7 mpptStart_ovr8 mpptStart_ovr_val9 ctr_cuFast_ovr11:10 ctr_cuFast_ovr_val12 Software_mpptEvent + * @{ + */ +#define PMU_PMU17__EN_REFGENFAST_OVR__SHIFT 19 +#define PMU_PMU17__EN_REFGENFAST_OVR__WIDTH 1 +#define PMU_PMU17__EN_REFGENFAST_OVR__MASK 0x00080000U +#define PMU_PMU17__EN_REFGENFAST_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define PMU_PMU17__EN_REFGENFAST_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define PMU_PMU17__EN_REFGENFAST_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define PMU_PMU17__EN_REFGENFAST_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define PMU_PMU17__EN_REFGENFAST_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define PMU_PMU17__EN_REFGENFAST_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define PMU_PMU17__EN_REFGENFAST_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_refgenfast_ovr_val */ +/** + * @defgroup pmu_top_regs_core_en_refgenfast_ovr_val_field en_refgenfast_ovr_val_field + * @brief macros for field en_refgenfast_ovr_val + * @details new sparebits0 zerompptref_forceb1 override ctr_maxref1v32 override val for ctr_maxref1v33 override en_refgenfast4 override val for en_refgenfast6:5 00 = mpptDone, 01 = mpptStart, 10 = zerompptref, 11 = mppt_freeze7 mpptStart_ovr8 mpptStart_ovr_val9 ctr_cuFast_ovr11:10 ctr_cuFast_ovr_val12 Software_mpptEvent + * @{ + */ +#define PMU_PMU17__EN_REFGENFAST_OVR_VAL__SHIFT 20 +#define PMU_PMU17__EN_REFGENFAST_OVR_VAL__WIDTH 1 +#define PMU_PMU17__EN_REFGENFAST_OVR_VAL__MASK 0x00100000U +#define PMU_PMU17__EN_REFGENFAST_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define PMU_PMU17__EN_REFGENFAST_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define PMU_PMU17__EN_REFGENFAST_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define PMU_PMU17__EN_REFGENFAST_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define PMU_PMU17__EN_REFGENFAST_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define PMU_PMU17__EN_REFGENFAST_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define PMU_PMU17__EN_REFGENFAST_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mppt_debug */ +/** + * @defgroup pmu_top_regs_core_mppt_debug_field mppt_debug_field + * @brief macros for field mppt_debug + * @details new sparebits0 zerompptref_forceb1 override ctr_maxref1v32 override val for ctr_maxref1v33 override en_refgenfast4 override val for en_refgenfast6:5 00 = mpptDone, 01 = mpptStart, 10 = zerompptref, 11 = mppt_freeze7 mpptStart_ovr8 mpptStart_ovr_val9 ctr_cuFast_ovr11:10 ctr_cuFast_ovr_val12 Software_mpptEvent + * @{ + */ +#define PMU_PMU17__MPPT_DEBUG__SHIFT 21 +#define PMU_PMU17__MPPT_DEBUG__WIDTH 2 +#define PMU_PMU17__MPPT_DEBUG__MASK 0x00600000U +#define PMU_PMU17__MPPT_DEBUG__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define PMU_PMU17__MPPT_DEBUG__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define PMU_PMU17__MPPT_DEBUG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define PMU_PMU17__MPPT_DEBUG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define PMU_PMU17__MPPT_DEBUG__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mpptStart_ovr */ +/** + * @defgroup pmu_top_regs_core_mpptStart_ovr_field mpptStart_ovr_field + * @brief macros for field mpptStart_ovr + * @details new sparebits0 zerompptref_forceb1 override ctr_maxref1v32 override val for ctr_maxref1v33 override en_refgenfast4 override val for en_refgenfast6:5 00 = mpptDone, 01 = mpptStart, 10 = zerompptref, 11 = mppt_freeze7 mpptStart_ovr8 mpptStart_ovr_val9 ctr_cuFast_ovr11:10 ctr_cuFast_ovr_val12 Software_mpptEvent + * @{ + */ +#define PMU_PMU17__MPPTSTART_OVR__SHIFT 23 +#define PMU_PMU17__MPPTSTART_OVR__WIDTH 1 +#define PMU_PMU17__MPPTSTART_OVR__MASK 0x00800000U +#define PMU_PMU17__MPPTSTART_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define PMU_PMU17__MPPTSTART_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define PMU_PMU17__MPPTSTART_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define PMU_PMU17__MPPTSTART_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define PMU_PMU17__MPPTSTART_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define PMU_PMU17__MPPTSTART_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define PMU_PMU17__MPPTSTART_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mpptStart_ovr_val */ +/** + * @defgroup pmu_top_regs_core_mpptStart_ovr_val_field mpptStart_ovr_val_field + * @brief macros for field mpptStart_ovr_val + * @details new sparebits0 zerompptref_forceb1 override ctr_maxref1v32 override val for ctr_maxref1v33 override en_refgenfast4 override val for en_refgenfast6:5 00 = mpptDone, 01 = mpptStart, 10 = zerompptref, 11 = mppt_freeze7 mpptStart_ovr8 mpptStart_ovr_val9 ctr_cuFast_ovr11:10 ctr_cuFast_ovr_val12 Software_mpptEvent + * @{ + */ +#define PMU_PMU17__MPPTSTART_OVR_VAL__SHIFT 24 +#define PMU_PMU17__MPPTSTART_OVR_VAL__WIDTH 1 +#define PMU_PMU17__MPPTSTART_OVR_VAL__MASK 0x01000000U +#define PMU_PMU17__MPPTSTART_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define PMU_PMU17__MPPTSTART_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define PMU_PMU17__MPPTSTART_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define PMU_PMU17__MPPTSTART_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define PMU_PMU17__MPPTSTART_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define PMU_PMU17__MPPTSTART_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define PMU_PMU17__MPPTSTART_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_cuFast_ovr */ +/** + * @defgroup pmu_top_regs_core_ctr_cuFast_ovr_field ctr_cuFast_ovr_field + * @brief macros for field ctr_cuFast_ovr + * @details new sparebits0 zerompptref_forceb1 override ctr_maxref1v32 override val for ctr_maxref1v33 override en_refgenfast4 override val for en_refgenfast6:5 00 = mpptDone, 01 = mpptStart, 10 = zerompptref, 11 = mppt_freeze7 mpptStart_ovr8 mpptStart_ovr_val9 ctr_cuFast_ovr11:10 ctr_cuFast_ovr_val12 Software_mpptEvent + * @{ + */ +#define PMU_PMU17__CTR_CUFAST_OVR__SHIFT 25 +#define PMU_PMU17__CTR_CUFAST_OVR__WIDTH 1 +#define PMU_PMU17__CTR_CUFAST_OVR__MASK 0x02000000U +#define PMU_PMU17__CTR_CUFAST_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define PMU_PMU17__CTR_CUFAST_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define PMU_PMU17__CTR_CUFAST_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define PMU_PMU17__CTR_CUFAST_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define PMU_PMU17__CTR_CUFAST_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define PMU_PMU17__CTR_CUFAST_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define PMU_PMU17__CTR_CUFAST_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_cuFast_ovr_val */ +/** + * @defgroup pmu_top_regs_core_ctr_cuFast_ovr_val_field ctr_cuFast_ovr_val_field + * @brief macros for field ctr_cuFast_ovr_val + * @details new sparebits0 zerompptref_forceb1 override ctr_maxref1v32 override val for ctr_maxref1v33 override en_refgenfast4 override val for en_refgenfast6:5 00 = mpptDone, 01 = mpptStart, 10 = zerompptref, 11 = mppt_freeze7 mpptStart_ovr8 mpptStart_ovr_val9 ctr_cuFast_ovr11:10 ctr_cuFast_ovr_val12 Software_mpptEvent + * @{ + */ +#define PMU_PMU17__CTR_CUFAST_OVR_VAL__SHIFT 26 +#define PMU_PMU17__CTR_CUFAST_OVR_VAL__WIDTH 2 +#define PMU_PMU17__CTR_CUFAST_OVR_VAL__MASK 0x0c000000U +#define PMU_PMU17__CTR_CUFAST_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x0c000000U) >> 26) +#define PMU_PMU17__CTR_CUFAST_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x0c000000U) +#define PMU_PMU17__CTR_CUFAST_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((uint32_t)(src) <<\ + 26) & 0x0c000000U) +#define PMU_PMU17__CTR_CUFAST_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x0c000000U))) +#define PMU_PMU17__CTR_CUFAST_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sw_mpptEvent */ +/** + * @defgroup pmu_top_regs_core_sw_mpptEvent_field sw_mpptEvent_field + * @brief macros for field sw_mpptEvent + * @details new sparebits0 zerompptref_forceb1 override ctr_maxref1v32 override val for ctr_maxref1v33 override en_refgenfast4 override val for en_refgenfast6:5 00 = mpptDone, 01 = mpptStart, 10 = zerompptref, 11 = mppt_freeze7 mpptStart_ovr8 mpptStart_ovr_val9 ctr_cuFast_ovr11:10 ctr_cuFast_ovr_val12 Software_mpptEvent + * @{ + */ +#define PMU_PMU17__SW_MPPTEVENT__SHIFT 28 +#define PMU_PMU17__SW_MPPTEVENT__WIDTH 1 +#define PMU_PMU17__SW_MPPTEVENT__MASK 0x10000000U +#define PMU_PMU17__SW_MPPTEVENT__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define PMU_PMU17__SW_MPPTEVENT__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define PMU_PMU17__SW_MPPTEVENT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define PMU_PMU17__SW_MPPTEVENT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define PMU_PMU17__SW_MPPTEVENT__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define PMU_PMU17__SW_MPPTEVENT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define PMU_PMU17__SW_MPPTEVENT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field new_sparebits */ +/** + * @defgroup pmu_top_regs_core_new_sparebits_field new_sparebits_field + * @brief macros for field new_sparebits + * @details new sparebits0 zerompptref_forceb1 override ctr_maxref1v32 override val for ctr_maxref1v33 override en_refgenfast4 override val for en_refgenfast6:5 00 = mpptDone, 01 = mpptStart, 10 = zerompptref, 11 = mppt_freeze7 mpptStart_ovr8 mpptStart_ovr_val9 ctr_cuFast_ovr11:10 ctr_cuFast_ovr_val12 Software_mpptEvent + * @{ + */ +#define PMU_PMU17__NEW_SPAREBITS__SHIFT 29 +#define PMU_PMU17__NEW_SPAREBITS__WIDTH 3 +#define PMU_PMU17__NEW_SPAREBITS__MASK 0xe0000000U +#define PMU_PMU17__NEW_SPAREBITS__READ(src) \ + (((uint32_t)(src)\ + & 0xe0000000U) >> 29) +#define PMU_PMU17__NEW_SPAREBITS__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0xe0000000U) +#define PMU_PMU17__NEW_SPAREBITS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((uint32_t)(src) <<\ + 29) & 0xe0000000U) +#define PMU_PMU17__NEW_SPAREBITS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0xe0000000U))) +#define PMU_PMU17__NEW_SPAREBITS__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU17__TYPE uint32_t +#define PMU_PMU17__READ 0xffffffffU +#define PMU_PMU17__WRITE 0xffffffffU +#define PMU_PMU17__PRESERVED 0x00000000U +#define PMU_PMU17__RESET_VALUE 0x0000006eU + +#endif /* __PMU_PMU17_MACRO__ */ + +/** @} end of pmu17 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu18 */ +/** + * @defgroup pmu_top_regs_core_pmu18 pmu18 + * @brief more mppt regs definitions. + * @{ + */ +#ifndef __PMU_PMU18_MACRO__ +#define __PMU_PMU18_MACRO__ + +/* macros for field mpptEventCount_max */ +/** + * @defgroup pmu_top_regs_core_mpptEventCount_max_field mpptEventCount_max_field + * @brief macros for field mpptEventCount_max + * @{ + */ +#define PMU_PMU18__MPPTEVENTCOUNT_MAX__SHIFT 0 +#define PMU_PMU18__MPPTEVENTCOUNT_MAX__WIDTH 11 +#define PMU_PMU18__MPPTEVENTCOUNT_MAX__MASK 0x000007ffU +#define PMU_PMU18__MPPTEVENTCOUNT_MAX__READ(src) \ + ((uint32_t)(src)\ + & 0x000007ffU) +#define PMU_PMU18__MPPTEVENTCOUNT_MAX__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000007ffU) +#define PMU_PMU18__MPPTEVENTCOUNT_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007ffU) | ((uint32_t)(src) &\ + 0x000007ffU) +#define PMU_PMU18__MPPTEVENTCOUNT_MAX__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000007ffU))) +#define PMU_PMU18__MPPTEVENTCOUNT_MAX__RESET_VALUE 0x00000320U +/** @} */ + +/* macros for field maxMpptPeriods_sel */ +/** + * @defgroup pmu_top_regs_core_maxMpptPeriods_sel_field maxMpptPeriods_sel_field + * @brief macros for field maxMpptPeriods_sel + * @{ + */ +#define PMU_PMU18__MAXMPPTPERIODS_SEL__SHIFT 11 +#define PMU_PMU18__MAXMPPTPERIODS_SEL__WIDTH 2 +#define PMU_PMU18__MAXMPPTPERIODS_SEL__MASK 0x00001800U +#define PMU_PMU18__MAXMPPTPERIODS_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00001800U) >> 11) +#define PMU_PMU18__MAXMPPTPERIODS_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00001800U) +#define PMU_PMU18__MAXMPPTPERIODS_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001800U) | (((uint32_t)(src) <<\ + 11) & 0x00001800U) +#define PMU_PMU18__MAXMPPTPERIODS_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00001800U))) +#define PMU_PMU18__MAXMPPTPERIODS_SEL__RESET_VALUE 0x00000001U +/** @} */ +#define PMU_PMU18__TYPE uint32_t +#define PMU_PMU18__READ 0x00001fffU +#define PMU_PMU18__WRITE 0x00001fffU +#define PMU_PMU18__PRESERVED 0x00000000U +#define PMU_PMU18__RESET_VALUE 0x00000b20U + +#endif /* __PMU_PMU18_MACRO__ */ + +/** @} end of pmu18 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu_rb0 */ +/** + * @defgroup pmu_top_regs_core_pmu_rb0 pmu_rb0 + * @brief readback registers definitions. + * @{ + */ +#ifndef __PMU_PMU_RB0_MACRO__ +#define __PMU_PMU_RB0_MACRO__ + +/* macros for field timer_out_lsb */ +/** + * @defgroup pmu_top_regs_core_timer_out_lsb_field timer_out_lsb_field + * @brief macros for field timer_out_lsb + * @details 32 lsb bits of timer_(# of 32KHz clock cycles) + * @{ + */ +#define PMU_PMU_RB0__TIMER_OUT_LSB__SHIFT 0 +#define PMU_PMU_RB0__TIMER_OUT_LSB__WIDTH 32 +#define PMU_PMU_RB0__TIMER_OUT_LSB__MASK 0xffffffffU +#define PMU_PMU_RB0__TIMER_OUT_LSB__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PMU_PMU_RB0__TIMER_OUT_LSB__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU_RB0__TYPE uint32_t +#define PMU_PMU_RB0__READ 0xffffffffU +#define PMU_PMU_RB0__PRESERVED 0x00000000U +#define PMU_PMU_RB0__RESET_VALUE 0x00000000U + +#endif /* __PMU_PMU_RB0_MACRO__ */ + +/** @} end of pmu_rb0 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu_rb1 */ +/** + * @defgroup pmu_top_regs_core_pmu_rb1 pmu_rb1 + * @brief readback registers definitions. + * @{ + */ +#ifndef __PMU_PMU_RB1_MACRO__ +#define __PMU_PMU_RB1_MACRO__ + +/* macros for field timer_out_msb */ +/** + * @defgroup pmu_top_regs_core_timer_out_msb_field timer_out_msb_field + * @brief macros for field timer_out_msb + * @details 8 msb bits of timer_(# of 32KHz clock cycles) + * @{ + */ +#define PMU_PMU_RB1__TIMER_OUT_MSB__SHIFT 0 +#define PMU_PMU_RB1__TIMER_OUT_MSB__WIDTH 8 +#define PMU_PMU_RB1__TIMER_OUT_MSB__MASK 0x000000ffU +#define PMU_PMU_RB1__TIMER_OUT_MSB__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define PMU_PMU_RB1__TIMER_OUT_MSB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wkup_det */ +/** + * @defgroup pmu_top_regs_core_wkup_det_field wkup_det_field + * @brief macros for field wkup_det + * @details determine how soc is waking up + * @{ + */ +#define PMU_PMU_RB1__WKUP_DET__SHIFT 8 +#define PMU_PMU_RB1__WKUP_DET__WIDTH 3 +#define PMU_PMU_RB1__WKUP_DET__MASK 0x00000700U +#define PMU_PMU_RB1__WKUP_DET__READ(src) (((uint32_t)(src) & 0x00000700U) >> 8) +#define PMU_PMU_RB1__WKUP_DET__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pmu_state */ +/** + * @defgroup pmu_top_regs_core_pmu_state_field pmu_state_field + * @brief macros for field pmu_state + * @details readback pmu state + * @{ + */ +#define PMU_PMU_RB1__PMU_STATE__SHIFT 11 +#define PMU_PMU_RB1__PMU_STATE__WIDTH 3 +#define PMU_PMU_RB1__PMU_STATE__MASK 0x00003800U +#define PMU_PMU_RB1__PMU_STATE__READ(src) \ + (((uint32_t)(src)\ + & 0x00003800U) >> 11) +#define PMU_PMU_RB1__PMU_STATE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field lpcomp_out */ +/** + * @defgroup pmu_top_regs_core_lpcomp_out_field lpcomp_out_field + * @brief macros for field lpcomp_out + * @details low power comparator output + * @{ + */ +#define PMU_PMU_RB1__LPCOMP_OUT__SHIFT 14 +#define PMU_PMU_RB1__LPCOMP_OUT__WIDTH 1 +#define PMU_PMU_RB1__LPCOMP_OUT__MASK 0x00004000U +#define PMU_PMU_RB1__LPCOMP_OUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define PMU_PMU_RB1__LPCOMP_OUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define PMU_PMU_RB1__LPCOMP_OUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define PMU_PMU_RB1__LPCOMP_OUT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enrc */ +/** + * @defgroup pmu_top_regs_core_enrc_field enrc_field + * @brief macros for field enrc + * @details readback for rc osc + * @{ + */ +#define PMU_PMU_RB1__ENRC__SHIFT 15 +#define PMU_PMU_RB1__ENRC__WIDTH 1 +#define PMU_PMU_RB1__ENRC__MASK 0x00008000U +#define PMU_PMU_RB1__ENRC__READ(src) (((uint32_t)(src) & 0x00008000U) >> 15) +#define PMU_PMU_RB1__ENRC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define PMU_PMU_RB1__ENRC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define PMU_PMU_RB1__ENRC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enxtal */ +/** + * @defgroup pmu_top_regs_core_enxtal_field enxtal_field + * @brief macros for field enxtal + * @details readback for xtal osc + * @{ + */ +#define PMU_PMU_RB1__ENXTAL__SHIFT 16 +#define PMU_PMU_RB1__ENXTAL__WIDTH 1 +#define PMU_PMU_RB1__ENXTAL__MASK 0x00010000U +#define PMU_PMU_RB1__ENXTAL__READ(src) (((uint32_t)(src) & 0x00010000U) >> 16) +#define PMU_PMU_RB1__ENXTAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PMU_PMU_RB1__ENXTAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PMU_PMU_RB1__ENXTAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field VstoreGoodtoTX */ +/** + * @defgroup pmu_top_regs_core_VstoreGoodtoTX_field VstoreGoodtoTX_field + * @brief macros for field VstoreGoodtoTX + * @details readback comp output + * @{ + */ +#define PMU_PMU_RB1__VSTOREGOODTOTX__SHIFT 17 +#define PMU_PMU_RB1__VSTOREGOODTOTX__WIDTH 1 +#define PMU_PMU_RB1__VSTOREGOODTOTX__MASK 0x00020000U +#define PMU_PMU_RB1__VSTOREGOODTOTX__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define PMU_PMU_RB1__VSTOREGOODTOTX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define PMU_PMU_RB1__VSTOREGOODTOTX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define PMU_PMU_RB1__VSTOREGOODTOTX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field BrownOutVbat */ +/** + * @defgroup pmu_top_regs_core_BrownOutVbat_field BrownOutVbat_field + * @brief macros for field BrownOutVbat + * @details readback comp output + * @{ + */ +#define PMU_PMU_RB1__BROWNOUTVBAT__SHIFT 18 +#define PMU_PMU_RB1__BROWNOUTVBAT__WIDTH 1 +#define PMU_PMU_RB1__BROWNOUTVBAT__MASK 0x00040000U +#define PMU_PMU_RB1__BROWNOUTVBAT__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define PMU_PMU_RB1__BROWNOUTVBAT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define PMU_PMU_RB1__BROWNOUTVBAT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define PMU_PMU_RB1__BROWNOUTVBAT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field VstoreGoodtoEner */ +/** + * @defgroup pmu_top_regs_core_VstoreGoodtoEner_field VstoreGoodtoEner_field + * @brief macros for field VstoreGoodtoEner + * @details readback comp output + * @{ + */ +#define PMU_PMU_RB1__VSTOREGOODTOENER__SHIFT 19 +#define PMU_PMU_RB1__VSTOREGOODTOENER__WIDTH 1 +#define PMU_PMU_RB1__VSTOREGOODTOENER__MASK 0x00080000U +#define PMU_PMU_RB1__VSTOREGOODTOENER__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define PMU_PMU_RB1__VSTOREGOODTOENER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define PMU_PMU_RB1__VSTOREGOODTOENER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define PMU_PMU_RB1__VSTOREGOODTOENER__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field VstoreHarvStop */ +/** + * @defgroup pmu_top_regs_core_VstoreHarvStop_field VstoreHarvStop_field + * @brief macros for field VstoreHarvStop + * @details readback comp output + * @{ + */ +#define PMU_PMU_RB1__VSTOREHARVSTOP__SHIFT 20 +#define PMU_PMU_RB1__VSTOREHARVSTOP__WIDTH 1 +#define PMU_PMU_RB1__VSTOREHARVSTOP__MASK 0x00100000U +#define PMU_PMU_RB1__VSTOREHARVSTOP__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define PMU_PMU_RB1__VSTOREHARVSTOP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define PMU_PMU_RB1__VSTOREHARVSTOP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define PMU_PMU_RB1__VSTOREHARVSTOP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mpptstartvharv */ +/** + * @defgroup pmu_top_regs_core_mpptstartvharv_field mpptstartvharv_field + * @brief macros for field mpptstartvharv + * @details readback comp output + * @{ + */ +#define PMU_PMU_RB1__MPPTSTARTVHARV__SHIFT 21 +#define PMU_PMU_RB1__MPPTSTARTVHARV__WIDTH 1 +#define PMU_PMU_RB1__MPPTSTARTVHARV__MASK 0x00200000U +#define PMU_PMU_RB1__MPPTSTARTVHARV__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define PMU_PMU_RB1__MPPTSTARTVHARV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define PMU_PMU_RB1__MPPTSTARTVHARV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define PMU_PMU_RB1__MPPTSTARTVHARV__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field reconfharvstage */ +/** + * @defgroup pmu_top_regs_core_reconfharvstage_field reconfharvstage_field + * @brief macros for field reconfharvstage + * @details readback comp output + * @{ + */ +#define PMU_PMU_RB1__RECONFHARVSTAGE__SHIFT 22 +#define PMU_PMU_RB1__RECONFHARVSTAGE__WIDTH 1 +#define PMU_PMU_RB1__RECONFHARVSTAGE__MASK 0x00400000U +#define PMU_PMU_RB1__RECONFHARVSTAGE__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define PMU_PMU_RB1__RECONFHARVSTAGE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define PMU_PMU_RB1__RECONFHARVSTAGE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define PMU_PMU_RB1__RECONFHARVSTAGE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mppt_state */ +/** + * @defgroup pmu_top_regs_core_mppt_state_field mppt_state_field + * @brief macros for field mppt_state + * @details readback mppt state + * @{ + */ +#define PMU_PMU_RB1__MPPT_STATE__SHIFT 23 +#define PMU_PMU_RB1__MPPT_STATE__WIDTH 4 +#define PMU_PMU_RB1__MPPT_STATE__MASK 0x07800000U +#define PMU_PMU_RB1__MPPT_STATE__READ(src) \ + (((uint32_t)(src)\ + & 0x07800000U) >> 23) +#define PMU_PMU_RB1__MPPT_STATE__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU_RB1__TYPE uint32_t +#define PMU_PMU_RB1__READ 0x07ffffffU +#define PMU_PMU_RB1__PRESERVED 0x00000000U +#define PMU_PMU_RB1__RESET_VALUE 0x00000000U + +#endif /* __PMU_PMU_RB1_MACRO__ */ + +/** @} end of pmu_rb1 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu_rb2 */ +/** + * @defgroup pmu_top_regs_core_pmu_rb2 pmu_rb2 + * @brief readback registers definitions. + * @{ + */ +#ifndef __PMU_PMU_RB2_MACRO__ +#define __PMU_PMU_RB2_MACRO__ + +/* macros for field mppt_Pestimate */ +/** + * @defgroup pmu_top_regs_core_mppt_Pestimate_field mppt_Pestimate_field + * @brief macros for field mppt_Pestimate + * @details readback Pestimate value + * @{ + */ +#define PMU_PMU_RB2__MPPT_PESTIMATE__SHIFT 0 +#define PMU_PMU_RB2__MPPT_PESTIMATE__WIDTH 20 +#define PMU_PMU_RB2__MPPT_PESTIMATE__MASK 0x000fffffU +#define PMU_PMU_RB2__MPPT_PESTIMATE__READ(src) ((uint32_t)(src) & 0x000fffffU) +#define PMU_PMU_RB2__MPPT_PESTIMATE__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU_RB2__TYPE uint32_t +#define PMU_PMU_RB2__READ 0x000fffffU +#define PMU_PMU_RB2__PRESERVED 0x00000000U +#define PMU_PMU_RB2__RESET_VALUE 0x00000000U + +#endif /* __PMU_PMU_RB2_MACRO__ */ + +/** @} end of pmu_rb2 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu_rb_mppt */ +/** + * @defgroup pmu_top_regs_core_pmu_rb_mppt pmu_rb_mppt + * @brief readback registers for customers definitions. + * @{ + */ +#ifndef __PMU_PMU_RB_MPPT_MACRO__ +#define __PMU_PMU_RB_MPPT_MACRO__ + +/* macros for field mpptPeriodCount */ +/** + * @defgroup pmu_top_regs_core_mpptPeriodCount_field mpptPeriodCount_field + * @brief macros for field mpptPeriodCount + * @details readback mpptPeriodCount value + * @{ + */ +#define PMU_PMU_RB_MPPT__MPPTPERIODCOUNT__SHIFT 0 +#define PMU_PMU_RB_MPPT__MPPTPERIODCOUNT__WIDTH 9 +#define PMU_PMU_RB_MPPT__MPPTPERIODCOUNT__MASK 0x000001ffU +#define PMU_PMU_RB_MPPT__MPPTPERIODCOUNT__READ(src) \ + ((uint32_t)(src)\ + & 0x000001ffU) +#define PMU_PMU_RB_MPPT__MPPTPERIODCOUNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mpptEventCount */ +/** + * @defgroup pmu_top_regs_core_mpptEventCount_field mpptEventCount_field + * @brief macros for field mpptEventCount + * @details readback mpptEventCount value + * @{ + */ +#define PMU_PMU_RB_MPPT__MPPTEVENTCOUNT__SHIFT 9 +#define PMU_PMU_RB_MPPT__MPPTEVENTCOUNT__WIDTH 10 +#define PMU_PMU_RB_MPPT__MPPTEVENTCOUNT__MASK 0x0007fe00U +#define PMU_PMU_RB_MPPT__MPPTEVENTCOUNT__READ(src) \ + (((uint32_t)(src)\ + & 0x0007fe00U) >> 9) +#define PMU_PMU_RB_MPPT__MPPTEVENTCOUNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field vstoreTooHigh_latch */ +/** + * @defgroup pmu_top_regs_core_vstoreTooHigh_latch_field vstoreTooHigh_latch_field + * @brief macros for field vstoreTooHigh_latch + * @details readback vstoreToohigh latched value + * @{ + */ +#define PMU_PMU_RB_MPPT__VSTORETOOHIGH_LATCH__SHIFT 19 +#define PMU_PMU_RB_MPPT__VSTORETOOHIGH_LATCH__WIDTH 1 +#define PMU_PMU_RB_MPPT__VSTORETOOHIGH_LATCH__MASK 0x00080000U +#define PMU_PMU_RB_MPPT__VSTORETOOHIGH_LATCH__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define PMU_PMU_RB_MPPT__VSTORETOOHIGH_LATCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define PMU_PMU_RB_MPPT__VSTORETOOHIGH_LATCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define PMU_PMU_RB_MPPT__VSTORETOOHIGH_LATCH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ctr_mustharvfa */ +/** + * @defgroup pmu_top_regs_core_ctr_mustharvfa_field ctr_mustharvfa_field + * @brief macros for field ctr_mustharvfa + * @details readback vharv + * @{ + */ +#define PMU_PMU_RB_MPPT__CTR_MUSTHARVFA__SHIFT 20 +#define PMU_PMU_RB_MPPT__CTR_MUSTHARVFA__WIDTH 4 +#define PMU_PMU_RB_MPPT__CTR_MUSTHARVFA__MASK 0x00f00000U +#define PMU_PMU_RB_MPPT__CTR_MUSTHARVFA__READ(src) \ + (((uint32_t)(src)\ + & 0x00f00000U) >> 20) +#define PMU_PMU_RB_MPPT__CTR_MUSTHARVFA__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU_RB_MPPT__TYPE uint32_t +#define PMU_PMU_RB_MPPT__READ 0x00ffffffU +#define PMU_PMU_RB_MPPT__PRESERVED 0x00000000U +#define PMU_PMU_RB_MPPT__RESET_VALUE 0x00000000U + +#endif /* __PMU_PMU_RB_MPPT_MACRO__ */ + +/** @} end of pmu_rb_mppt */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu_rb3 */ +/** + * @defgroup pmu_top_regs_core_pmu_rb3 pmu_rb3 + * @brief internal OTP readback registers definitions. + * @{ + */ +#ifndef __PMU_PMU_RB3_MACRO__ +#define __PMU_PMU_RB3_MACRO__ + +/* macros for field otp_internal */ +/** + * @defgroup pmu_top_regs_core_otp_internal_field otp_internal_field + * @brief macros for field otp_internal + * @details {otp_internal_spare[3:0],otp_rect_ctune[2:0],otp_harv_disabled,otp_disable_chpu,otp_use_ldo,otp_nabg_trim[8:0]} + * @{ + */ +#define PMU_PMU_RB3__OTP_INTERNAL__SHIFT 0 +#define PMU_PMU_RB3__OTP_INTERNAL__WIDTH 19 +#define PMU_PMU_RB3__OTP_INTERNAL__MASK 0x0007ffffU +#define PMU_PMU_RB3__OTP_INTERNAL__READ(src) ((uint32_t)(src) & 0x0007ffffU) +#define PMU_PMU_RB3__OTP_INTERNAL__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU_RB3__TYPE uint32_t +#define PMU_PMU_RB3__READ 0x0007ffffU +#define PMU_PMU_RB3__PRESERVED 0x00000000U +#define PMU_PMU_RB3__RESET_VALUE 0x00000000U + +#endif /* __PMU_PMU_RB3_MACRO__ */ + +/** @} end of pmu_rb3 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu_rb4 */ +/** + * @defgroup pmu_top_regs_core_pmu_rb4 pmu_rb4 + * @brief external OTP readback registers definitions. + * @{ + */ +#ifndef __PMU_PMU_RB4_MACRO__ +#define __PMU_PMU_RB4_MACRO__ + +/* macros for field otp_disable_xtal32K */ +/** + * @defgroup pmu_top_regs_core_otp_disable_xtal32K_field otp_disable_xtal32K_field + * @brief macros for field otp_disable_xtal32K + * @{ + */ +#define PMU_PMU_RB4__OTP_DISABLE_XTAL32K__SHIFT 0 +#define PMU_PMU_RB4__OTP_DISABLE_XTAL32K__WIDTH 1 +#define PMU_PMU_RB4__OTP_DISABLE_XTAL32K__MASK 0x00000001U +#define PMU_PMU_RB4__OTP_DISABLE_XTAL32K__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define PMU_PMU_RB4__OTP_DISABLE_XTAL32K__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PMU_PMU_RB4__OTP_DISABLE_XTAL32K__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PMU_PMU_RB4__OTP_DISABLE_XTAL32K__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_supply_cfg */ +/** + * @defgroup pmu_top_regs_core_otp_supply_cfg_field otp_supply_cfg_field + * @brief macros for field otp_supply_cfg + * @details {otp_disable_5v,otp_disable_vddgen,otp_disable_vddIOgen,otp_noind} + * @{ + */ +#define PMU_PMU_RB4__OTP_SUPPLY_CFG__SHIFT 1 +#define PMU_PMU_RB4__OTP_SUPPLY_CFG__WIDTH 4 +#define PMU_PMU_RB4__OTP_SUPPLY_CFG__MASK 0x0000001eU +#define PMU_PMU_RB4__OTP_SUPPLY_CFG__READ(src) \ + (((uint32_t)(src)\ + & 0x0000001eU) >> 1) +#define PMU_PMU_RB4__OTP_SUPPLY_CFG__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_batt_cfg */ +/** + * @defgroup pmu_top_regs_core_otp_batt_cfg_field otp_batt_cfg_field + * @brief macros for field otp_batt_cfg + * @details {otp_vbatt_brownout[4:0],otp_vbatt_good[2:0],otp_batt_type[1:0],otp_vbatt_level} + * @{ + */ +#define PMU_PMU_RB4__OTP_BATT_CFG__SHIFT 5 +#define PMU_PMU_RB4__OTP_BATT_CFG__WIDTH 11 +#define PMU_PMU_RB4__OTP_BATT_CFG__MASK 0x0000ffe0U +#define PMU_PMU_RB4__OTP_BATT_CFG__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ffe0U) >> 5) +#define PMU_PMU_RB4__OTP_BATT_CFG__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_vddio_range */ +/** + * @defgroup pmu_top_regs_core_otp_vddio_range_field otp_vddio_range_field + * @brief macros for field otp_vddio_range + * @{ + */ +#define PMU_PMU_RB4__OTP_VDDIO_RANGE__SHIFT 16 +#define PMU_PMU_RB4__OTP_VDDIO_RANGE__WIDTH 1 +#define PMU_PMU_RB4__OTP_VDDIO_RANGE__MASK 0x00010000U +#define PMU_PMU_RB4__OTP_VDDIO_RANGE__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define PMU_PMU_RB4__OTP_VDDIO_RANGE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define PMU_PMU_RB4__OTP_VDDIO_RANGE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define PMU_PMU_RB4__OTP_VDDIO_RANGE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_reserved */ +/** + * @defgroup pmu_top_regs_core_otp_reserved_field otp_reserved_field + * @brief macros for field otp_reserved + * @{ + */ +#define PMU_PMU_RB4__OTP_RESERVED__SHIFT 17 +#define PMU_PMU_RB4__OTP_RESERVED__WIDTH 1 +#define PMU_PMU_RB4__OTP_RESERVED__MASK 0x00020000U +#define PMU_PMU_RB4__OTP_RESERVED__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define PMU_PMU_RB4__OTP_RESERVED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define PMU_PMU_RB4__OTP_RESERVED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define PMU_PMU_RB4__OTP_RESERVED__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_harv_cfg */ +/** + * @defgroup pmu_top_regs_core_otp_harv_cfg_field otp_harv_cfg_field + * @brief macros for field otp_harv_cfg + * @details {otp_vstore_max[2:0],otp_vstore_good[1:0],otp_vharv_start[1:0],otp_disable_rfharv,otp_mppt_type[1:0]} + * @{ + */ +#define PMU_PMU_RB4__OTP_HARV_CFG__SHIFT 18 +#define PMU_PMU_RB4__OTP_HARV_CFG__WIDTH 10 +#define PMU_PMU_RB4__OTP_HARV_CFG__MASK 0x0ffc0000U +#define PMU_PMU_RB4__OTP_HARV_CFG__READ(src) \ + (((uint32_t)(src)\ + & 0x0ffc0000U) >> 18) +#define PMU_PMU_RB4__OTP_HARV_CFG__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field otp_spare */ +/** + * @defgroup pmu_top_regs_core_otp_spare_field otp_spare_field + * @brief macros for field otp_spare + * @{ + */ +#define PMU_PMU_RB4__OTP_SPARE__SHIFT 28 +#define PMU_PMU_RB4__OTP_SPARE__WIDTH 1 +#define PMU_PMU_RB4__OTP_SPARE__MASK 0x10000000U +#define PMU_PMU_RB4__OTP_SPARE__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define PMU_PMU_RB4__OTP_SPARE__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define PMU_PMU_RB4__OTP_SPARE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define PMU_PMU_RB4__OTP_SPARE__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU_RB4__TYPE uint32_t +#define PMU_PMU_RB4__READ 0x1fffffffU +#define PMU_PMU_RB4__PRESERVED 0x00000000U +#define PMU_PMU_RB4__RESET_VALUE 0x00000000U + +#endif /* __PMU_PMU_RB4_MACRO__ */ + +/** @} end of pmu_rb4 */ + +/* macros for BlueprintGlobalNameSpace::PMU_pmu_rb5 */ +/** + * @defgroup pmu_top_regs_core_pmu_rb5 pmu_rb5 + * @brief external soc watchdog reset readback status register definitions. + * @{ + */ +#ifndef __PMU_PMU_RB5_MACRO__ +#define __PMU_PMU_RB5_MACRO__ + +/* macros for field soc_wdog_reset */ +/** + * @defgroup pmu_top_regs_core_soc_wdog_reset_field soc_wdog_reset_field + * @brief macros for field soc_wdog_reset + * @details HW writes sets status when soc wdog reset is asserted. SW writes clears status only. + * @{ + */ +#define PMU_PMU_RB5__SOC_WDOG_RESET__SHIFT 0 +#define PMU_PMU_RB5__SOC_WDOG_RESET__WIDTH 1 +#define PMU_PMU_RB5__SOC_WDOG_RESET__MASK 0x00000001U +#define PMU_PMU_RB5__SOC_WDOG_RESET__READ(src) ((uint32_t)(src) & 0x00000001U) +#define PMU_PMU_RB5__SOC_WDOG_RESET__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define PMU_PMU_RB5__SOC_WDOG_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define PMU_PMU_RB5__SOC_WDOG_RESET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define PMU_PMU_RB5__SOC_WDOG_RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define PMU_PMU_RB5__SOC_WDOG_RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define PMU_PMU_RB5__SOC_WDOG_RESET__RESET_VALUE 0x00000000U +/** @} */ +#define PMU_PMU_RB5__TYPE uint32_t +#define PMU_PMU_RB5__READ 0x00000001U +#define PMU_PMU_RB5__WRITE 0x00000001U +#define PMU_PMU_RB5__PRESERVED 0x00000000U +#define PMU_PMU_RB5__RESET_VALUE 0x00000000U + +#endif /* __PMU_PMU_RB5_MACRO__ */ + +/** @} end of pmu_rb5 */ + +/* macros for BlueprintGlobalNameSpace::PMU_core_id */ +/** + * @defgroup pmu_top_regs_core_core_id core_id + * @brief Core ID definitions. + * @{ + */ +#ifndef __PMU_CORE_ID_MACRO__ +#define __PMU_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup pmu_top_regs_core_id_field id_field + * @brief macros for field id + * @details PMU in ASCII + * @{ + */ +#define PMU_CORE_ID__ID__SHIFT 0 +#define PMU_CORE_ID__ID__WIDTH 32 +#define PMU_CORE_ID__ID__MASK 0xffffffffU +#define PMU_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define PMU_CORE_ID__ID__RESET_VALUE 0x504d5520U +/** @} */ +#define PMU_CORE_ID__TYPE uint32_t +#define PMU_CORE_ID__READ 0xffffffffU +#define PMU_CORE_ID__PRESERVED 0x00000000U +#define PMU_CORE_ID__RESET_VALUE 0x504d5520U + +#endif /* __PMU_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of PMU_TOP_REGS_CORE */ +#endif /* __REG_PMU_TOP_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/pmu_wurx_regs_core_macro.h b/ATM33xx-5/include/reg/pmu_wurx_regs_core_macro.h new file mode 100644 index 0000000..065c94c --- /dev/null +++ b/ATM33xx-5/include/reg/pmu_wurx_regs_core_macro.h @@ -0,0 +1,2165 @@ +/* */ +/* File: pmu_wurx_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic pmu_wurx_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_PMU_WURX_REGS_CORE_H__ +#define __REG_PMU_WURX_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup PMU_WURX_REGS_CORE pmu_wurx_regs_core + * @ingroup AT_REG + * @brief pmu_wurx_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::WURX_wurx_general */ +/** + * @defgroup pmu_wurx_regs_core_wurx_general wurx_general + * @brief Wake-up RX overrides and bias definitions. + * @{ + */ +#ifndef __WURX_WURX_GENERAL_MACRO__ +#define __WURX_WURX_GENERAL_MACRO__ + +/* macros for field wurx_select */ +/** + * @defgroup pmu_wurx_regs_core_wurx_select_field wurx_select_field + * @brief macros for field wurx_select + * @details which algorithm to use: 0: algorithm 0, 1: algorithm 1 + * @{ + */ +#define WURX_WURX_GENERAL__WURX_SELECT__SHIFT 0 +#define WURX_WURX_GENERAL__WURX_SELECT__WIDTH 1 +#define WURX_WURX_GENERAL__WURX_SELECT__MASK 0x00000001U +#define WURX_WURX_GENERAL__WURX_SELECT__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WURX_WURX_GENERAL__WURX_SELECT__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WURX_WURX_GENERAL__WURX_SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WURX_WURX_GENERAL__WURX_SELECT__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WURX_WURX_GENERAL__WURX_SELECT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WURX_WURX_GENERAL__WURX_SELECT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WURX_WURX_GENERAL__WURX_SELECT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wurx0_en_ovr */ +/** + * @defgroup pmu_wurx_regs_core_wurx0_en_ovr_field wurx0_en_ovr_field + * @brief macros for field wurx0_en_ovr + * @details override wurx0_en + * @{ + */ +#define WURX_WURX_GENERAL__WURX0_EN_OVR__SHIFT 1 +#define WURX_WURX_GENERAL__WURX0_EN_OVR__WIDTH 1 +#define WURX_WURX_GENERAL__WURX0_EN_OVR__MASK 0x00000002U +#define WURX_WURX_GENERAL__WURX0_EN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WURX_WURX_GENERAL__WURX0_EN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WURX_WURX_GENERAL__WURX0_EN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WURX_WURX_GENERAL__WURX0_EN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WURX_WURX_GENERAL__WURX0_EN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WURX_WURX_GENERAL__WURX0_EN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WURX_WURX_GENERAL__WURX0_EN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wurx0_en_val */ +/** + * @defgroup pmu_wurx_regs_core_wurx0_en_val_field wurx0_en_val_field + * @brief macros for field wurx0_en_val + * @details override value for wurx0_en + * @{ + */ +#define WURX_WURX_GENERAL__WURX0_EN_VAL__SHIFT 2 +#define WURX_WURX_GENERAL__WURX0_EN_VAL__WIDTH 1 +#define WURX_WURX_GENERAL__WURX0_EN_VAL__MASK 0x00000004U +#define WURX_WURX_GENERAL__WURX0_EN_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define WURX_WURX_GENERAL__WURX0_EN_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define WURX_WURX_GENERAL__WURX0_EN_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define WURX_WURX_GENERAL__WURX0_EN_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define WURX_WURX_GENERAL__WURX0_EN_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define WURX_WURX_GENERAL__WURX0_EN_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define WURX_WURX_GENERAL__WURX0_EN_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wurx1_en_ovr */ +/** + * @defgroup pmu_wurx_regs_core_wurx1_en_ovr_field wurx1_en_ovr_field + * @brief macros for field wurx1_en_ovr + * @details override wurx1_en + * @{ + */ +#define WURX_WURX_GENERAL__WURX1_EN_OVR__SHIFT 3 +#define WURX_WURX_GENERAL__WURX1_EN_OVR__WIDTH 1 +#define WURX_WURX_GENERAL__WURX1_EN_OVR__MASK 0x00000008U +#define WURX_WURX_GENERAL__WURX1_EN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define WURX_WURX_GENERAL__WURX1_EN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define WURX_WURX_GENERAL__WURX1_EN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define WURX_WURX_GENERAL__WURX1_EN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define WURX_WURX_GENERAL__WURX1_EN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define WURX_WURX_GENERAL__WURX1_EN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define WURX_WURX_GENERAL__WURX1_EN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wurx1_en_val */ +/** + * @defgroup pmu_wurx_regs_core_wurx1_en_val_field wurx1_en_val_field + * @brief macros for field wurx1_en_val + * @details override value for wurx1_en + * @{ + */ +#define WURX_WURX_GENERAL__WURX1_EN_VAL__SHIFT 4 +#define WURX_WURX_GENERAL__WURX1_EN_VAL__WIDTH 1 +#define WURX_WURX_GENERAL__WURX1_EN_VAL__MASK 0x00000010U +#define WURX_WURX_GENERAL__WURX1_EN_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define WURX_WURX_GENERAL__WURX1_EN_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define WURX_WURX_GENERAL__WURX1_EN_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define WURX_WURX_GENERAL__WURX1_EN_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define WURX_WURX_GENERAL__WURX1_EN_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define WURX_WURX_GENERAL__WURX1_EN_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define WURX_WURX_GENERAL__WURX1_EN_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wakeup0_ovr */ +/** + * @defgroup pmu_wurx_regs_core_wakeup0_ovr_field wakeup0_ovr_field + * @brief macros for field wakeup0_ovr + * @details wakeup0 override + * @{ + */ +#define WURX_WURX_GENERAL__WAKEUP0_OVR__SHIFT 5 +#define WURX_WURX_GENERAL__WAKEUP0_OVR__WIDTH 1 +#define WURX_WURX_GENERAL__WAKEUP0_OVR__MASK 0x00000020U +#define WURX_WURX_GENERAL__WAKEUP0_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define WURX_WURX_GENERAL__WAKEUP0_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define WURX_WURX_GENERAL__WAKEUP0_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define WURX_WURX_GENERAL__WAKEUP0_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define WURX_WURX_GENERAL__WAKEUP0_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define WURX_WURX_GENERAL__WAKEUP0_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define WURX_WURX_GENERAL__WAKEUP0_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wakeup0_ovr_val */ +/** + * @defgroup pmu_wurx_regs_core_wakeup0_ovr_val_field wakeup0_ovr_val_field + * @brief macros for field wakeup0_ovr_val + * @details wakeup0 override value + * @{ + */ +#define WURX_WURX_GENERAL__WAKEUP0_OVR_VAL__SHIFT 6 +#define WURX_WURX_GENERAL__WAKEUP0_OVR_VAL__WIDTH 1 +#define WURX_WURX_GENERAL__WAKEUP0_OVR_VAL__MASK 0x00000040U +#define WURX_WURX_GENERAL__WAKEUP0_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define WURX_WURX_GENERAL__WAKEUP0_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define WURX_WURX_GENERAL__WAKEUP0_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define WURX_WURX_GENERAL__WAKEUP0_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define WURX_WURX_GENERAL__WAKEUP0_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define WURX_WURX_GENERAL__WAKEUP0_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define WURX_WURX_GENERAL__WAKEUP0_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wakeup1_ovr */ +/** + * @defgroup pmu_wurx_regs_core_wakeup1_ovr_field wakeup1_ovr_field + * @brief macros for field wakeup1_ovr + * @details wakeup1 override + * @{ + */ +#define WURX_WURX_GENERAL__WAKEUP1_OVR__SHIFT 7 +#define WURX_WURX_GENERAL__WAKEUP1_OVR__WIDTH 1 +#define WURX_WURX_GENERAL__WAKEUP1_OVR__MASK 0x00000080U +#define WURX_WURX_GENERAL__WAKEUP1_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define WURX_WURX_GENERAL__WAKEUP1_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define WURX_WURX_GENERAL__WAKEUP1_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define WURX_WURX_GENERAL__WAKEUP1_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define WURX_WURX_GENERAL__WAKEUP1_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define WURX_WURX_GENERAL__WAKEUP1_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define WURX_WURX_GENERAL__WAKEUP1_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field wakeup1_ovr_val */ +/** + * @defgroup pmu_wurx_regs_core_wakeup1_ovr_val_field wakeup1_ovr_val_field + * @brief macros for field wakeup1_ovr_val + * @details wakeup1 override value + * @{ + */ +#define WURX_WURX_GENERAL__WAKEUP1_OVR_VAL__SHIFT 8 +#define WURX_WURX_GENERAL__WAKEUP1_OVR_VAL__WIDTH 1 +#define WURX_WURX_GENERAL__WAKEUP1_OVR_VAL__MASK 0x00000100U +#define WURX_WURX_GENERAL__WAKEUP1_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define WURX_WURX_GENERAL__WAKEUP1_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define WURX_WURX_GENERAL__WAKEUP1_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define WURX_WURX_GENERAL__WAKEUP1_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define WURX_WURX_GENERAL__WAKEUP1_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define WURX_WURX_GENERAL__WAKEUP1_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define WURX_WURX_GENERAL__WAKEUP1_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field init_cal_ovr */ +/** + * @defgroup pmu_wurx_regs_core_init_cal_ovr_field init_cal_ovr_field + * @brief macros for field init_cal_ovr + * @details ovrride for which cal to do + * @{ + */ +#define WURX_WURX_GENERAL__INIT_CAL_OVR__SHIFT 9 +#define WURX_WURX_GENERAL__INIT_CAL_OVR__WIDTH 1 +#define WURX_WURX_GENERAL__INIT_CAL_OVR__MASK 0x00000200U +#define WURX_WURX_GENERAL__INIT_CAL_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define WURX_WURX_GENERAL__INIT_CAL_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define WURX_WURX_GENERAL__INIT_CAL_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define WURX_WURX_GENERAL__INIT_CAL_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define WURX_WURX_GENERAL__INIT_CAL_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define WURX_WURX_GENERAL__INIT_CAL_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define WURX_WURX_GENERAL__INIT_CAL_OVR__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field init_cal_ovr_val */ +/** + * @defgroup pmu_wurx_regs_core_init_cal_ovr_val_field init_cal_ovr_val_field + * @brief macros for field init_cal_ovr_val + * @details override value for which cal to do + * @{ + */ +#define WURX_WURX_GENERAL__INIT_CAL_OVR_VAL__SHIFT 10 +#define WURX_WURX_GENERAL__INIT_CAL_OVR_VAL__WIDTH 1 +#define WURX_WURX_GENERAL__INIT_CAL_OVR_VAL__MASK 0x00000400U +#define WURX_WURX_GENERAL__INIT_CAL_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define WURX_WURX_GENERAL__INIT_CAL_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define WURX_WURX_GENERAL__INIT_CAL_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define WURX_WURX_GENERAL__INIT_CAL_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define WURX_WURX_GENERAL__INIT_CAL_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define WURX_WURX_GENERAL__INIT_CAL_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define WURX_WURX_GENERAL__INIT_CAL_OVR_VAL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field bias */ +/** + * @defgroup pmu_wurx_regs_core_bias_field bias_field + * @brief macros for field bias + * @details ??? + * @{ + */ +#define WURX_WURX_GENERAL__BIAS__SHIFT 11 +#define WURX_WURX_GENERAL__BIAS__WIDTH 4 +#define WURX_WURX_GENERAL__BIAS__MASK 0x00007800U +#define WURX_WURX_GENERAL__BIAS__READ(src) \ + (((uint32_t)(src)\ + & 0x00007800U) >> 11) +#define WURX_WURX_GENERAL__BIAS__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00007800U) +#define WURX_WURX_GENERAL__BIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007800U) | (((uint32_t)(src) <<\ + 11) & 0x00007800U) +#define WURX_WURX_GENERAL__BIAS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00007800U))) +#define WURX_WURX_GENERAL__BIAS__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field atbsel */ +/** + * @defgroup pmu_wurx_regs_core_atbsel_field atbsel_field + * @brief macros for field atbsel + * @details atb select + * @{ + */ +#define WURX_WURX_GENERAL__ATBSEL__SHIFT 15 +#define WURX_WURX_GENERAL__ATBSEL__WIDTH 4 +#define WURX_WURX_GENERAL__ATBSEL__MASK 0x00078000U +#define WURX_WURX_GENERAL__ATBSEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00078000U) >> 15) +#define WURX_WURX_GENERAL__ATBSEL__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00078000U) +#define WURX_WURX_GENERAL__ATBSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00078000U) | (((uint32_t)(src) <<\ + 15) & 0x00078000U) +#define WURX_WURX_GENERAL__ATBSEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00078000U))) +#define WURX_WURX_GENERAL__ATBSEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field attnIn_ovr */ +/** + * @defgroup pmu_wurx_regs_core_attnIn_ovr_field attnIn_ovr_field + * @brief macros for field attnIn_ovr + * @details attnIn ovr + * @{ + */ +#define WURX_WURX_GENERAL__ATTNIN_OVR__SHIFT 19 +#define WURX_WURX_GENERAL__ATTNIN_OVR__WIDTH 1 +#define WURX_WURX_GENERAL__ATTNIN_OVR__MASK 0x00080000U +#define WURX_WURX_GENERAL__ATTNIN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define WURX_WURX_GENERAL__ATTNIN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define WURX_WURX_GENERAL__ATTNIN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define WURX_WURX_GENERAL__ATTNIN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define WURX_WURX_GENERAL__ATTNIN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define WURX_WURX_GENERAL__ATTNIN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define WURX_WURX_GENERAL__ATTNIN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field attnIn_ovr_val */ +/** + * @defgroup pmu_wurx_regs_core_attnIn_ovr_val_field attnIn_ovr_val_field + * @brief macros for field attnIn_ovr_val + * @details ovrride val for attnIn + * @{ + */ +#define WURX_WURX_GENERAL__ATTNIN_OVR_VAL__SHIFT 20 +#define WURX_WURX_GENERAL__ATTNIN_OVR_VAL__WIDTH 1 +#define WURX_WURX_GENERAL__ATTNIN_OVR_VAL__MASK 0x00100000U +#define WURX_WURX_GENERAL__ATTNIN_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define WURX_WURX_GENERAL__ATTNIN_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define WURX_WURX_GENERAL__ATTNIN_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define WURX_WURX_GENERAL__ATTNIN_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define WURX_WURX_GENERAL__ATTNIN_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define WURX_WURX_GENERAL__ATTNIN_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define WURX_WURX_GENERAL__ATTNIN_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field thr_cal_en_reg */ +/** + * @defgroup pmu_wurx_regs_core_thr_cal_en_reg_field thr_cal_en_reg_field + * @brief macros for field thr_cal_en_reg + * @details if set to 0 disables calibration + * @{ + */ +#define WURX_WURX_GENERAL__THR_CAL_EN_REG__SHIFT 21 +#define WURX_WURX_GENERAL__THR_CAL_EN_REG__WIDTH 1 +#define WURX_WURX_GENERAL__THR_CAL_EN_REG__MASK 0x00200000U +#define WURX_WURX_GENERAL__THR_CAL_EN_REG__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define WURX_WURX_GENERAL__THR_CAL_EN_REG__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define WURX_WURX_GENERAL__THR_CAL_EN_REG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define WURX_WURX_GENERAL__THR_CAL_EN_REG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define WURX_WURX_GENERAL__THR_CAL_EN_REG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define WURX_WURX_GENERAL__THR_CAL_EN_REG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define WURX_WURX_GENERAL__THR_CAL_EN_REG__RESET_VALUE 0x00000001U +/** @} */ +#define WURX_WURX_GENERAL__TYPE uint32_t +#define WURX_WURX_GENERAL__READ 0x003fffffU +#define WURX_WURX_GENERAL__WRITE 0x003fffffU +#define WURX_WURX_GENERAL__PRESERVED 0x00000000U +#define WURX_WURX_GENERAL__RESET_VALUE 0x00202600U + +#endif /* __WURX_WURX_GENERAL_MACRO__ */ + +/** @} end of wurx_general */ + +/* macros for BlueprintGlobalNameSpace::WURX_wurx_general2 */ +/** + * @defgroup pmu_wurx_regs_core_wurx_general2 wurx_general2 + * @brief Wake-up RX general registers definitions. + * @{ + */ +#ifndef __WURX_WURX_GENERAL2_MACRO__ +#define __WURX_WURX_GENERAL2_MACRO__ + +/* macros for field load_ovr */ +/** + * @defgroup pmu_wurx_regs_core_load_ovr_field load_ovr_field + * @brief macros for field load_ovr + * @details ovrride load value + * @{ + */ +#define WURX_WURX_GENERAL2__LOAD_OVR__SHIFT 0 +#define WURX_WURX_GENERAL2__LOAD_OVR__WIDTH 1 +#define WURX_WURX_GENERAL2__LOAD_OVR__MASK 0x00000001U +#define WURX_WURX_GENERAL2__LOAD_OVR__READ(src) ((uint32_t)(src) & 0x00000001U) +#define WURX_WURX_GENERAL2__LOAD_OVR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WURX_WURX_GENERAL2__LOAD_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WURX_WURX_GENERAL2__LOAD_OVR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WURX_WURX_GENERAL2__LOAD_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WURX_WURX_GENERAL2__LOAD_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WURX_WURX_GENERAL2__LOAD_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field load_ovr_val */ +/** + * @defgroup pmu_wurx_regs_core_load_ovr_val_field load_ovr_val_field + * @brief macros for field load_ovr_val + * @details starting point for cal or override value + * @{ + */ +#define WURX_WURX_GENERAL2__LOAD_OVR_VAL__SHIFT 1 +#define WURX_WURX_GENERAL2__LOAD_OVR_VAL__WIDTH 9 +#define WURX_WURX_GENERAL2__LOAD_OVR_VAL__MASK 0x000003feU +#define WURX_WURX_GENERAL2__LOAD_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x000003feU) >> 1) +#define WURX_WURX_GENERAL2__LOAD_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000003feU) +#define WURX_WURX_GENERAL2__LOAD_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003feU) | (((uint32_t)(src) <<\ + 1) & 0x000003feU) +#define WURX_WURX_GENERAL2__LOAD_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000003feU))) +#define WURX_WURX_GENERAL2__LOAD_OVR_VAL__RESET_VALUE 0x00000064U +/** @} */ + +/* macros for field offset_ovr */ +/** + * @defgroup pmu_wurx_regs_core_offset_ovr_field offset_ovr_field + * @brief macros for field offset_ovr + * @details override offset value + * @{ + */ +#define WURX_WURX_GENERAL2__OFFSET_OVR__SHIFT 10 +#define WURX_WURX_GENERAL2__OFFSET_OVR__WIDTH 1 +#define WURX_WURX_GENERAL2__OFFSET_OVR__MASK 0x00000400U +#define WURX_WURX_GENERAL2__OFFSET_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define WURX_WURX_GENERAL2__OFFSET_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define WURX_WURX_GENERAL2__OFFSET_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define WURX_WURX_GENERAL2__OFFSET_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define WURX_WURX_GENERAL2__OFFSET_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define WURX_WURX_GENERAL2__OFFSET_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define WURX_WURX_GENERAL2__OFFSET_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field offset_ovr_val */ +/** + * @defgroup pmu_wurx_regs_core_offset_ovr_val_field offset_ovr_val_field + * @brief macros for field offset_ovr_val + * @details starting point for cal or override value + * @{ + */ +#define WURX_WURX_GENERAL2__OFFSET_OVR_VAL__SHIFT 11 +#define WURX_WURX_GENERAL2__OFFSET_OVR_VAL__WIDTH 8 +#define WURX_WURX_GENERAL2__OFFSET_OVR_VAL__MASK 0x0007f800U +#define WURX_WURX_GENERAL2__OFFSET_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x0007f800U) >> 11) +#define WURX_WURX_GENERAL2__OFFSET_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x0007f800U) +#define WURX_WURX_GENERAL2__OFFSET_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007f800U) | (((uint32_t)(src) <<\ + 11) & 0x0007f800U) +#define WURX_WURX_GENERAL2__OFFSET_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x0007f800U))) +#define WURX_WURX_GENERAL2__OFFSET_OVR_VAL__RESET_VALUE 0x00000064U +/** @} */ + +/* macros for field offsImbalance */ +/** + * @defgroup pmu_wurx_regs_core_offsImbalance_field offsImbalance_field + * @brief macros for field offsImbalance + * @details offset imbalance + * @{ + */ +#define WURX_WURX_GENERAL2__OFFSIMBALANCE__SHIFT 19 +#define WURX_WURX_GENERAL2__OFFSIMBALANCE__WIDTH 5 +#define WURX_WURX_GENERAL2__OFFSIMBALANCE__MASK 0x00f80000U +#define WURX_WURX_GENERAL2__OFFSIMBALANCE__READ(src) \ + (((uint32_t)(src)\ + & 0x00f80000U) >> 19) +#define WURX_WURX_GENERAL2__OFFSIMBALANCE__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00f80000U) +#define WURX_WURX_GENERAL2__OFFSIMBALANCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f80000U) | (((uint32_t)(src) <<\ + 19) & 0x00f80000U) +#define WURX_WURX_GENERAL2__OFFSIMBALANCE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00f80000U))) +#define WURX_WURX_GENERAL2__OFFSIMBALANCE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field offsRange */ +/** + * @defgroup pmu_wurx_regs_core_offsRange_field offsRange_field + * @brief macros for field offsRange + * @details range for offset + * @{ + */ +#define WURX_WURX_GENERAL2__OFFSRANGE__SHIFT 24 +#define WURX_WURX_GENERAL2__OFFSRANGE__WIDTH 3 +#define WURX_WURX_GENERAL2__OFFSRANGE__MASK 0x07000000U +#define WURX_WURX_GENERAL2__OFFSRANGE__READ(src) \ + (((uint32_t)(src)\ + & 0x07000000U) >> 24) +#define WURX_WURX_GENERAL2__OFFSRANGE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x07000000U) +#define WURX_WURX_GENERAL2__OFFSRANGE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((uint32_t)(src) <<\ + 24) & 0x07000000U) +#define WURX_WURX_GENERAL2__OFFSRANGE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x07000000U))) +#define WURX_WURX_GENERAL2__OFFSRANGE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field thr */ +/** + * @defgroup pmu_wurx_regs_core_thr_field thr_field + * @brief macros for field thr + * @details select output vs reference + * @{ + */ +#define WURX_WURX_GENERAL2__THR__SHIFT 27 +#define WURX_WURX_GENERAL2__THR__WIDTH 5 +#define WURX_WURX_GENERAL2__THR__MASK 0xf8000000U +#define WURX_WURX_GENERAL2__THR__READ(src) \ + (((uint32_t)(src)\ + & 0xf8000000U) >> 27) +#define WURX_WURX_GENERAL2__THR__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0xf8000000U) +#define WURX_WURX_GENERAL2__THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((uint32_t)(src) <<\ + 27) & 0xf8000000U) +#define WURX_WURX_GENERAL2__THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0xf8000000U))) +#define WURX_WURX_GENERAL2__THR__RESET_VALUE 0x00000000U +/** @} */ +#define WURX_WURX_GENERAL2__TYPE uint32_t +#define WURX_WURX_GENERAL2__READ 0xffffffffU +#define WURX_WURX_GENERAL2__WRITE 0xffffffffU +#define WURX_WURX_GENERAL2__PRESERVED 0x00000000U +#define WURX_WURX_GENERAL2__RESET_VALUE 0x000320c8U + +#endif /* __WURX_WURX_GENERAL2_MACRO__ */ + +/** @} end of wurx_general2 */ + +/* macros for BlueprintGlobalNameSpace::WURX_wurx0_0 */ +/** + * @defgroup pmu_wurx_regs_core_wurx0_0 wurx0_0 + * @brief Wake-up RX unique ID, algorithm 0 definitions. + * @{ + */ +#ifndef __WURX_WURX0_0_MACRO__ +#define __WURX_WURX0_0_MACRO__ + +/* macros for field uid */ +/** + * @defgroup pmu_wurx_regs_core_uid_field uid_field + * @brief macros for field uid + * @details User ID, upper 16 bits for group ID, lower 16 bits for user ID + * @{ + */ +#define WURX_WURX0_0__UID__SHIFT 0 +#define WURX_WURX0_0__UID__WIDTH 32 +#define WURX_WURX0_0__UID__MASK 0xffffffffU +#define WURX_WURX0_0__UID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define WURX_WURX0_0__UID__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define WURX_WURX0_0__UID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WURX_WURX0_0__UID__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define WURX_WURX0_0__UID__RESET_VALUE 0xaaaaaaaaU +/** @} */ +#define WURX_WURX0_0__TYPE uint32_t +#define WURX_WURX0_0__READ 0xffffffffU +#define WURX_WURX0_0__WRITE 0xffffffffU +#define WURX_WURX0_0__PRESERVED 0x00000000U +#define WURX_WURX0_0__RESET_VALUE 0xaaaaaaaaU + +#endif /* __WURX_WURX0_0_MACRO__ */ + +/** @} end of wurx0_0 */ + +/* macros for BlueprintGlobalNameSpace::WURX_wurx0_1 */ +/** + * @defgroup pmu_wurx_regs_core_wurx0_1 wurx0_1 + * @brief Wake-up RX global ID, algorithm 0 definitions. + * @{ + */ +#ifndef __WURX_WURX0_1_MACRO__ +#define __WURX_WURX0_1_MACRO__ + +/* macros for field gid */ +/** + * @defgroup pmu_wurx_regs_core_gid_field gid_field + * @brief macros for field gid + * @details Global ID + * @{ + */ +#define WURX_WURX0_1__GID__SHIFT 0 +#define WURX_WURX0_1__GID__WIDTH 32 +#define WURX_WURX0_1__GID__MASK 0xffffffffU +#define WURX_WURX0_1__GID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define WURX_WURX0_1__GID__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define WURX_WURX0_1__GID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WURX_WURX0_1__GID__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define WURX_WURX0_1__GID__RESET_VALUE 0xffffffffU +/** @} */ +#define WURX_WURX0_1__TYPE uint32_t +#define WURX_WURX0_1__READ 0xffffffffU +#define WURX_WURX0_1__WRITE 0xffffffffU +#define WURX_WURX0_1__PRESERVED 0x00000000U +#define WURX_WURX0_1__RESET_VALUE 0xffffffffU + +#endif /* __WURX_WURX0_1_MACRO__ */ + +/** @} end of wurx0_1 */ + +/* macros for BlueprintGlobalNameSpace::WURX_wurx0_2 */ +/** + * @defgroup pmu_wurx_regs_core_wurx0_2 wurx0_2 + * @brief Wake-up RX settings, algorithm 0 definitions. + * @{ + */ +#ifndef __WURX_WURX0_2_MACRO__ +#define __WURX_WURX0_2_MACRO__ + +/* macros for field err_threshold */ +/** + * @defgroup pmu_wurx_regs_core_err_threshold_field err_threshold_field + * @brief macros for field err_threshold + * @details number of bits of error between RX ID and detected ID + * @{ + */ +#define WURX_WURX0_2__ERR_THRESHOLD__SHIFT 0 +#define WURX_WURX0_2__ERR_THRESHOLD__WIDTH 6 +#define WURX_WURX0_2__ERR_THRESHOLD__MASK 0x0000003fU +#define WURX_WURX0_2__ERR_THRESHOLD__READ(src) ((uint32_t)(src) & 0x0000003fU) +#define WURX_WURX0_2__ERR_THRESHOLD__WRITE(src) ((uint32_t)(src) & 0x0000003fU) +#define WURX_WURX0_2__ERR_THRESHOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define WURX_WURX0_2__ERR_THRESHOLD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define WURX_WURX0_2__ERR_THRESHOLD__RESET_VALUE 0x0000001fU +/** @} */ + +/* macros for field too_lo1 */ +/** + * @defgroup pmu_wurx_regs_core_too_lo1_field too_lo1_field + * @brief macros for field too_lo1 + * @details number of samples that threshold is too low before linear increase in cal + * @{ + */ +#define WURX_WURX0_2__TOO_LO1__SHIFT 6 +#define WURX_WURX0_2__TOO_LO1__WIDTH 5 +#define WURX_WURX0_2__TOO_LO1__MASK 0x000007c0U +#define WURX_WURX0_2__TOO_LO1__READ(src) (((uint32_t)(src) & 0x000007c0U) >> 6) +#define WURX_WURX0_2__TOO_LO1__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000007c0U) +#define WURX_WURX0_2__TOO_LO1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007c0U) | (((uint32_t)(src) <<\ + 6) & 0x000007c0U) +#define WURX_WURX0_2__TOO_LO1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000007c0U))) +#define WURX_WURX0_2__TOO_LO1__RESET_VALUE 0x00000005U +/** @} */ + +/* macros for field too_lo2 */ +/** + * @defgroup pmu_wurx_regs_core_too_lo2_field too_lo2_field + * @brief macros for field too_lo2 + * @details number of samples that threshold is too low before binary cal + * @{ + */ +#define WURX_WURX0_2__TOO_LO2__SHIFT 11 +#define WURX_WURX0_2__TOO_LO2__WIDTH 5 +#define WURX_WURX0_2__TOO_LO2__MASK 0x0000f800U +#define WURX_WURX0_2__TOO_LO2__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f800U) >> 11) +#define WURX_WURX0_2__TOO_LO2__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x0000f800U) +#define WURX_WURX0_2__TOO_LO2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f800U) | (((uint32_t)(src) <<\ + 11) & 0x0000f800U) +#define WURX_WURX0_2__TOO_LO2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x0000f800U))) +#define WURX_WURX0_2__TOO_LO2__RESET_VALUE 0x0000000aU +/** @} */ + +/* macros for field too_hi */ +/** + * @defgroup pmu_wurx_regs_core_too_hi_field too_hi_field + * @brief macros for field too_hi + * @details number of samples that threshold is too high before binary cal + * @{ + */ +#define WURX_WURX0_2__TOO_HI__SHIFT 16 +#define WURX_WURX0_2__TOO_HI__WIDTH 5 +#define WURX_WURX0_2__TOO_HI__MASK 0x001f0000U +#define WURX_WURX0_2__TOO_HI__READ(src) (((uint32_t)(src) & 0x001f0000U) >> 16) +#define WURX_WURX0_2__TOO_HI__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x001f0000U) +#define WURX_WURX0_2__TOO_HI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((uint32_t)(src) <<\ + 16) & 0x001f0000U) +#define WURX_WURX0_2__TOO_HI__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x001f0000U))) +#define WURX_WURX0_2__TOO_HI__RESET_VALUE 0x0000000aU +/** @} */ + +/* macros for field corr_length */ +/** + * @defgroup pmu_wurx_regs_core_corr_length_field corr_length_field + * @brief macros for field corr_length + * @details number of symbols in one ID + * @{ + */ +#define WURX_WURX0_2__CORR_LENGTH__SHIFT 21 +#define WURX_WURX0_2__CORR_LENGTH__WIDTH 6 +#define WURX_WURX0_2__CORR_LENGTH__MASK 0x07e00000U +#define WURX_WURX0_2__CORR_LENGTH__READ(src) \ + (((uint32_t)(src)\ + & 0x07e00000U) >> 21) +#define WURX_WURX0_2__CORR_LENGTH__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x07e00000U) +#define WURX_WURX0_2__CORR_LENGTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07e00000U) | (((uint32_t)(src) <<\ + 21) & 0x07e00000U) +#define WURX_WURX0_2__CORR_LENGTH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x07e00000U))) +#define WURX_WURX0_2__CORR_LENGTH__RESET_VALUE 0x00000020U +/** @} */ + +/* macros for field thr_length */ +/** + * @defgroup pmu_wurx_regs_core_thr_length_field thr_length_field + * @brief macros for field thr_length + * @details how many sybmols to adjust threshold on, thr_length = 1: 2 symbols + * @{ + */ +#define WURX_WURX0_2__THR_LENGTH__SHIFT 27 +#define WURX_WURX0_2__THR_LENGTH__WIDTH 4 +#define WURX_WURX0_2__THR_LENGTH__MASK 0x78000000U +#define WURX_WURX0_2__THR_LENGTH__READ(src) \ + (((uint32_t)(src)\ + & 0x78000000U) >> 27) +#define WURX_WURX0_2__THR_LENGTH__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x78000000U) +#define WURX_WURX0_2__THR_LENGTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x78000000U) | (((uint32_t)(src) <<\ + 27) & 0x78000000U) +#define WURX_WURX0_2__THR_LENGTH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x78000000U))) +#define WURX_WURX0_2__THR_LENGTH__RESET_VALUE 0x00000001U +/** @} */ +#define WURX_WURX0_2__TYPE uint32_t +#define WURX_WURX0_2__READ 0x7fffffffU +#define WURX_WURX0_2__WRITE 0x7fffffffU +#define WURX_WURX0_2__PRESERVED 0x00000000U +#define WURX_WURX0_2__RESET_VALUE 0x0c0a515fU + +#endif /* __WURX_WURX0_2_MACRO__ */ + +/** @} end of wurx0_2 */ + +/* macros for BlueprintGlobalNameSpace::WURX_wurx0_3 */ +/** + * @defgroup pmu_wurx_regs_core_wurx0_3 wurx0_3 + * @brief Wake-up RX settings, algorithm 0 definitions. + * @{ + */ +#ifndef __WURX_WURX0_3_MACRO__ +#define __WURX_WURX0_3_MACRO__ + +/* macros for field energy_toolow */ +/** + * @defgroup pmu_wurx_regs_core_energy_toolow_field energy_toolow_field + * @brief macros for field energy_toolow + * @details received energy less than this --> decrease threshold + * @{ + */ +#define WURX_WURX0_3__ENERGY_TOOLOW__SHIFT 0 +#define WURX_WURX0_3__ENERGY_TOOLOW__WIDTH 9 +#define WURX_WURX0_3__ENERGY_TOOLOW__MASK 0x000001ffU +#define WURX_WURX0_3__ENERGY_TOOLOW__READ(src) ((uint32_t)(src) & 0x000001ffU) +#define WURX_WURX0_3__ENERGY_TOOLOW__WRITE(src) ((uint32_t)(src) & 0x000001ffU) +#define WURX_WURX0_3__ENERGY_TOOLOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((uint32_t)(src) &\ + 0x000001ffU) +#define WURX_WURX0_3__ENERGY_TOOLOW__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000001ffU))) +#define WURX_WURX0_3__ENERGY_TOOLOW__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field energy_toohigh */ +/** + * @defgroup pmu_wurx_regs_core_energy_toohigh_field energy_toohigh_field + * @brief macros for field energy_toohigh + * @details received energy more than this --> increase threshold + * @{ + */ +#define WURX_WURX0_3__ENERGY_TOOHIGH__SHIFT 9 +#define WURX_WURX0_3__ENERGY_TOOHIGH__WIDTH 10 +#define WURX_WURX0_3__ENERGY_TOOHIGH__MASK 0x0007fe00U +#define WURX_WURX0_3__ENERGY_TOOHIGH__READ(src) \ + (((uint32_t)(src)\ + & 0x0007fe00U) >> 9) +#define WURX_WURX0_3__ENERGY_TOOHIGH__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0007fe00U) +#define WURX_WURX0_3__ENERGY_TOOHIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0007fe00U) +#define WURX_WURX0_3__ENERGY_TOOHIGH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0007fe00U))) +#define WURX_WURX0_3__ENERGY_TOOHIGH__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field sym1_threshold */ +/** + * @defgroup pmu_wurx_regs_core_sym1_threshold_field sym1_threshold_field + * @brief macros for field sym1_threshold + * @details number of counts above this means symbol 1 is detected + * @{ + */ +#define WURX_WURX0_3__SYM1_THRESHOLD__SHIFT 19 +#define WURX_WURX0_3__SYM1_THRESHOLD__WIDTH 10 +#define WURX_WURX0_3__SYM1_THRESHOLD__MASK 0x1ff80000U +#define WURX_WURX0_3__SYM1_THRESHOLD__READ(src) \ + (((uint32_t)(src)\ + & 0x1ff80000U) >> 19) +#define WURX_WURX0_3__SYM1_THRESHOLD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x1ff80000U) +#define WURX_WURX0_3__SYM1_THRESHOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1ff80000U) | (((uint32_t)(src) <<\ + 19) & 0x1ff80000U) +#define WURX_WURX0_3__SYM1_THRESHOLD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x1ff80000U))) +#define WURX_WURX0_3__SYM1_THRESHOLD__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field clk_freq */ +/** + * @defgroup pmu_wurx_regs_core_clk_freq_field clk_freq_field + * @brief macros for field clk_freq + * @details 0 - 16KHz, 1- 32KHz + * @{ + */ +#define WURX_WURX0_3__CLK_FREQ__SHIFT 29 +#define WURX_WURX0_3__CLK_FREQ__WIDTH 1 +#define WURX_WURX0_3__CLK_FREQ__MASK 0x20000000U +#define WURX_WURX0_3__CLK_FREQ__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define WURX_WURX0_3__CLK_FREQ__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define WURX_WURX0_3__CLK_FREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define WURX_WURX0_3__CLK_FREQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define WURX_WURX0_3__CLK_FREQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define WURX_WURX0_3__CLK_FREQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define WURX_WURX0_3__CLK_FREQ__RESET_VALUE 0x00000001U +/** @} */ +#define WURX_WURX0_3__TYPE uint32_t +#define WURX_WURX0_3__READ 0x3fffffffU +#define WURX_WURX0_3__WRITE 0x3fffffffU +#define WURX_WURX0_3__PRESERVED 0x00000000U +#define WURX_WURX0_3__RESET_VALUE 0x20100c04U + +#endif /* __WURX_WURX0_3_MACRO__ */ + +/** @} end of wurx0_3 */ + +/* macros for BlueprintGlobalNameSpace::WURX_wurx0_4 */ +/** + * @defgroup pmu_wurx_regs_core_wurx0_4 wurx0_4 + * @brief Wake-up RX settings, algorithm 0 definitions. + * @{ + */ +#ifndef __WURX_WURX0_4_MACRO__ +#define __WURX_WURX0_4_MACRO__ + +/* macros for field timer_max */ +/** + * @defgroup pmu_wurx_regs_core_timer_max_field timer_max_field + * @brief macros for field timer_max + * @details number of cycles in one symbol period - 1 + * @{ + */ +#define WURX_WURX0_4__TIMER_MAX__SHIFT 0 +#define WURX_WURX0_4__TIMER_MAX__WIDTH 10 +#define WURX_WURX0_4__TIMER_MAX__MASK 0x000003ffU +#define WURX_WURX0_4__TIMER_MAX__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define WURX_WURX0_4__TIMER_MAX__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define WURX_WURX0_4__TIMER_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define WURX_WURX0_4__TIMER_MAX__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define WURX_WURX0_4__TIMER_MAX__RESET_VALUE 0x0000000fU +/** @} */ + +/* macros for field sym_silent_thr */ +/** + * @defgroup pmu_wurx_regs_core_sym_silent_thr_field sym_silent_thr_field + * @brief macros for field sym_silent_thr + * @details number of consecutive 0's considered as noise in a sym window + * @{ + */ +#define WURX_WURX0_4__SYM_SILENT_THR__SHIFT 10 +#define WURX_WURX0_4__SYM_SILENT_THR__WIDTH 5 +#define WURX_WURX0_4__SYM_SILENT_THR__MASK 0x00007c00U +#define WURX_WURX0_4__SYM_SILENT_THR__READ(src) \ + (((uint32_t)(src)\ + & 0x00007c00U) >> 10) +#define WURX_WURX0_4__SYM_SILENT_THR__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00007c00U) +#define WURX_WURX0_4__SYM_SILENT_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((uint32_t)(src) <<\ + 10) & 0x00007c00U) +#define WURX_WURX0_4__SYM_SILENT_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00007c00U))) +#define WURX_WURX0_4__SYM_SILENT_THR__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field init_cal_step */ +/** + * @defgroup pmu_wurx_regs_core_init_cal_step_field init_cal_step_field + * @brief macros for field init_cal_step + * @details initial cal step + * @{ + */ +#define WURX_WURX0_4__INIT_CAL_STEP__SHIFT 15 +#define WURX_WURX0_4__INIT_CAL_STEP__WIDTH 9 +#define WURX_WURX0_4__INIT_CAL_STEP__MASK 0x00ff8000U +#define WURX_WURX0_4__INIT_CAL_STEP__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff8000U) >> 15) +#define WURX_WURX0_4__INIT_CAL_STEP__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00ff8000U) +#define WURX_WURX0_4__INIT_CAL_STEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff8000U) | (((uint32_t)(src) <<\ + 15) & 0x00ff8000U) +#define WURX_WURX0_4__INIT_CAL_STEP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00ff8000U))) +#define WURX_WURX0_4__INIT_CAL_STEP__RESET_VALUE 0x00000100U +/** @} */ + +/* macros for field cal_silent_thr */ +/** + * @defgroup pmu_wurx_regs_core_cal_silent_thr_field cal_silent_thr_field + * @brief macros for field cal_silent_thr + * @details number of consecutive 0's considered as noise in a thr window + * @{ + */ +#define WURX_WURX0_4__CAL_SILENT_THR__SHIFT 24 +#define WURX_WURX0_4__CAL_SILENT_THR__WIDTH 7 +#define WURX_WURX0_4__CAL_SILENT_THR__MASK 0x7f000000U +#define WURX_WURX0_4__CAL_SILENT_THR__READ(src) \ + (((uint32_t)(src)\ + & 0x7f000000U) >> 24) +#define WURX_WURX0_4__CAL_SILENT_THR__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x7f000000U) +#define WURX_WURX0_4__CAL_SILENT_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((uint32_t)(src) <<\ + 24) & 0x7f000000U) +#define WURX_WURX0_4__CAL_SILENT_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x7f000000U))) +#define WURX_WURX0_4__CAL_SILENT_THR__RESET_VALUE 0x00000008U +/** @} */ +#define WURX_WURX0_4__TYPE uint32_t +#define WURX_WURX0_4__READ 0x7fffffffU +#define WURX_WURX0_4__WRITE 0x7fffffffU +#define WURX_WURX0_4__PRESERVED 0x00000000U +#define WURX_WURX0_4__RESET_VALUE 0x0880200fU + +#endif /* __WURX_WURX0_4_MACRO__ */ + +/** @} end of wurx0_4 */ + +/* macros for BlueprintGlobalNameSpace::WURX_wurx1_0 */ +/** + * @defgroup pmu_wurx_regs_core_wurx1_0 wurx1_0 + * @brief Wake-up RX unique ID, algorithm 0 definitions. + * @{ + */ +#ifndef __WURX_WURX1_0_MACRO__ +#define __WURX_WURX1_0_MACRO__ + +/* macros for field uid */ +/** + * @defgroup pmu_wurx_regs_core_uid_field uid_field + * @brief macros for field uid + * @details User ID, upper 16 bits for group ID, lower 16 bits for user ID + * @{ + */ +#define WURX_WURX1_0__UID__SHIFT 0 +#define WURX_WURX1_0__UID__WIDTH 32 +#define WURX_WURX1_0__UID__MASK 0xffffffffU +#define WURX_WURX1_0__UID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define WURX_WURX1_0__UID__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define WURX_WURX1_0__UID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WURX_WURX1_0__UID__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define WURX_WURX1_0__UID__RESET_VALUE 0xaaaaaaaaU +/** @} */ +#define WURX_WURX1_0__TYPE uint32_t +#define WURX_WURX1_0__READ 0xffffffffU +#define WURX_WURX1_0__WRITE 0xffffffffU +#define WURX_WURX1_0__PRESERVED 0x00000000U +#define WURX_WURX1_0__RESET_VALUE 0xaaaaaaaaU + +#endif /* __WURX_WURX1_0_MACRO__ */ + +/** @} end of wurx1_0 */ + +/* macros for BlueprintGlobalNameSpace::WURX_wurx1_1 */ +/** + * @defgroup pmu_wurx_regs_core_wurx1_1 wurx1_1 + * @brief Wake-up RX global ID, algorithm 0 definitions. + * @{ + */ +#ifndef __WURX_WURX1_1_MACRO__ +#define __WURX_WURX1_1_MACRO__ + +/* macros for field gid */ +/** + * @defgroup pmu_wurx_regs_core_gid_field gid_field + * @brief macros for field gid + * @details Global ID + * @{ + */ +#define WURX_WURX1_1__GID__SHIFT 0 +#define WURX_WURX1_1__GID__WIDTH 32 +#define WURX_WURX1_1__GID__MASK 0xffffffffU +#define WURX_WURX1_1__GID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define WURX_WURX1_1__GID__WRITE(src) ((uint32_t)(src) & 0xffffffffU) +#define WURX_WURX1_1__GID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((uint32_t)(src) &\ + 0xffffffffU) +#define WURX_WURX1_1__GID__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU))) +#define WURX_WURX1_1__GID__RESET_VALUE 0xffffffffU +/** @} */ +#define WURX_WURX1_1__TYPE uint32_t +#define WURX_WURX1_1__READ 0xffffffffU +#define WURX_WURX1_1__WRITE 0xffffffffU +#define WURX_WURX1_1__PRESERVED 0x00000000U +#define WURX_WURX1_1__RESET_VALUE 0xffffffffU + +#endif /* __WURX_WURX1_1_MACRO__ */ + +/** @} end of wurx1_1 */ + +/* macros for BlueprintGlobalNameSpace::WURX_wurx1_2 */ +/** + * @defgroup pmu_wurx_regs_core_wurx1_2 wurx1_2 + * @brief Wake-up RX settings, algorithm 0 definitions. + * @{ + */ +#ifndef __WURX_WURX1_2_MACRO__ +#define __WURX_WURX1_2_MACRO__ + +/* macros for field err_threshold */ +/** + * @defgroup pmu_wurx_regs_core_err_threshold_field err_threshold_field + * @brief macros for field err_threshold + * @details number of bits of error between RX ID and detected ID + * @{ + */ +#define WURX_WURX1_2__ERR_THRESHOLD__SHIFT 0 +#define WURX_WURX1_2__ERR_THRESHOLD__WIDTH 6 +#define WURX_WURX1_2__ERR_THRESHOLD__MASK 0x0000003fU +#define WURX_WURX1_2__ERR_THRESHOLD__READ(src) ((uint32_t)(src) & 0x0000003fU) +#define WURX_WURX1_2__ERR_THRESHOLD__WRITE(src) ((uint32_t)(src) & 0x0000003fU) +#define WURX_WURX1_2__ERR_THRESHOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define WURX_WURX1_2__ERR_THRESHOLD__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define WURX_WURX1_2__ERR_THRESHOLD__RESET_VALUE 0x0000001fU +/** @} */ + +/* macros for field too_lo1 */ +/** + * @defgroup pmu_wurx_regs_core_too_lo1_field too_lo1_field + * @brief macros for field too_lo1 + * @details number of samples that threshold is too low before linear increase in cal + * @{ + */ +#define WURX_WURX1_2__TOO_LO1__SHIFT 6 +#define WURX_WURX1_2__TOO_LO1__WIDTH 5 +#define WURX_WURX1_2__TOO_LO1__MASK 0x000007c0U +#define WURX_WURX1_2__TOO_LO1__READ(src) (((uint32_t)(src) & 0x000007c0U) >> 6) +#define WURX_WURX1_2__TOO_LO1__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000007c0U) +#define WURX_WURX1_2__TOO_LO1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007c0U) | (((uint32_t)(src) <<\ + 6) & 0x000007c0U) +#define WURX_WURX1_2__TOO_LO1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000007c0U))) +#define WURX_WURX1_2__TOO_LO1__RESET_VALUE 0x00000005U +/** @} */ + +/* macros for field too_lo2 */ +/** + * @defgroup pmu_wurx_regs_core_too_lo2_field too_lo2_field + * @brief macros for field too_lo2 + * @details number of samples that threshold is too low before binary cal + * @{ + */ +#define WURX_WURX1_2__TOO_LO2__SHIFT 11 +#define WURX_WURX1_2__TOO_LO2__WIDTH 5 +#define WURX_WURX1_2__TOO_LO2__MASK 0x0000f800U +#define WURX_WURX1_2__TOO_LO2__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f800U) >> 11) +#define WURX_WURX1_2__TOO_LO2__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x0000f800U) +#define WURX_WURX1_2__TOO_LO2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f800U) | (((uint32_t)(src) <<\ + 11) & 0x0000f800U) +#define WURX_WURX1_2__TOO_LO2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x0000f800U))) +#define WURX_WURX1_2__TOO_LO2__RESET_VALUE 0x0000000aU +/** @} */ + +/* macros for field too_hi */ +/** + * @defgroup pmu_wurx_regs_core_too_hi_field too_hi_field + * @brief macros for field too_hi + * @details number of samples that threshold is too high before binary cal + * @{ + */ +#define WURX_WURX1_2__TOO_HI__SHIFT 16 +#define WURX_WURX1_2__TOO_HI__WIDTH 5 +#define WURX_WURX1_2__TOO_HI__MASK 0x001f0000U +#define WURX_WURX1_2__TOO_HI__READ(src) (((uint32_t)(src) & 0x001f0000U) >> 16) +#define WURX_WURX1_2__TOO_HI__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x001f0000U) +#define WURX_WURX1_2__TOO_HI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((uint32_t)(src) <<\ + 16) & 0x001f0000U) +#define WURX_WURX1_2__TOO_HI__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x001f0000U))) +#define WURX_WURX1_2__TOO_HI__RESET_VALUE 0x0000000aU +/** @} */ + +/* macros for field corr_length */ +/** + * @defgroup pmu_wurx_regs_core_corr_length_field corr_length_field + * @brief macros for field corr_length + * @details number of symbols in one ID + * @{ + */ +#define WURX_WURX1_2__CORR_LENGTH__SHIFT 21 +#define WURX_WURX1_2__CORR_LENGTH__WIDTH 6 +#define WURX_WURX1_2__CORR_LENGTH__MASK 0x07e00000U +#define WURX_WURX1_2__CORR_LENGTH__READ(src) \ + (((uint32_t)(src)\ + & 0x07e00000U) >> 21) +#define WURX_WURX1_2__CORR_LENGTH__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x07e00000U) +#define WURX_WURX1_2__CORR_LENGTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07e00000U) | (((uint32_t)(src) <<\ + 21) & 0x07e00000U) +#define WURX_WURX1_2__CORR_LENGTH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x07e00000U))) +#define WURX_WURX1_2__CORR_LENGTH__RESET_VALUE 0x00000020U +/** @} */ + +/* macros for field thr_length */ +/** + * @defgroup pmu_wurx_regs_core_thr_length_field thr_length_field + * @brief macros for field thr_length + * @details how many sybmols to adjust threshold on, thr_length = 1: 2 symbols + * @{ + */ +#define WURX_WURX1_2__THR_LENGTH__SHIFT 27 +#define WURX_WURX1_2__THR_LENGTH__WIDTH 4 +#define WURX_WURX1_2__THR_LENGTH__MASK 0x78000000U +#define WURX_WURX1_2__THR_LENGTH__READ(src) \ + (((uint32_t)(src)\ + & 0x78000000U) >> 27) +#define WURX_WURX1_2__THR_LENGTH__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x78000000U) +#define WURX_WURX1_2__THR_LENGTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x78000000U) | (((uint32_t)(src) <<\ + 27) & 0x78000000U) +#define WURX_WURX1_2__THR_LENGTH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x78000000U))) +#define WURX_WURX1_2__THR_LENGTH__RESET_VALUE 0x00000001U +/** @} */ +#define WURX_WURX1_2__TYPE uint32_t +#define WURX_WURX1_2__READ 0x7fffffffU +#define WURX_WURX1_2__WRITE 0x7fffffffU +#define WURX_WURX1_2__PRESERVED 0x00000000U +#define WURX_WURX1_2__RESET_VALUE 0x0c0a515fU + +#endif /* __WURX_WURX1_2_MACRO__ */ + +/** @} end of wurx1_2 */ + +/* macros for BlueprintGlobalNameSpace::WURX_wurx1_3 */ +/** + * @defgroup pmu_wurx_regs_core_wurx1_3 wurx1_3 + * @brief Wake-up RX settings, algorithm 0 definitions. + * @{ + */ +#ifndef __WURX_WURX1_3_MACRO__ +#define __WURX_WURX1_3_MACRO__ + +/* macros for field energy_toolow */ +/** + * @defgroup pmu_wurx_regs_core_energy_toolow_field energy_toolow_field + * @brief macros for field energy_toolow + * @details received energy less than this --> decrease threshold + * @{ + */ +#define WURX_WURX1_3__ENERGY_TOOLOW__SHIFT 0 +#define WURX_WURX1_3__ENERGY_TOOLOW__WIDTH 9 +#define WURX_WURX1_3__ENERGY_TOOLOW__MASK 0x000001ffU +#define WURX_WURX1_3__ENERGY_TOOLOW__READ(src) ((uint32_t)(src) & 0x000001ffU) +#define WURX_WURX1_3__ENERGY_TOOLOW__WRITE(src) ((uint32_t)(src) & 0x000001ffU) +#define WURX_WURX1_3__ENERGY_TOOLOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((uint32_t)(src) &\ + 0x000001ffU) +#define WURX_WURX1_3__ENERGY_TOOLOW__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000001ffU))) +#define WURX_WURX1_3__ENERGY_TOOLOW__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field energy_toohigh */ +/** + * @defgroup pmu_wurx_regs_core_energy_toohigh_field energy_toohigh_field + * @brief macros for field energy_toohigh + * @details received energy more than this --> increase threshold + * @{ + */ +#define WURX_WURX1_3__ENERGY_TOOHIGH__SHIFT 9 +#define WURX_WURX1_3__ENERGY_TOOHIGH__WIDTH 10 +#define WURX_WURX1_3__ENERGY_TOOHIGH__MASK 0x0007fe00U +#define WURX_WURX1_3__ENERGY_TOOHIGH__READ(src) \ + (((uint32_t)(src)\ + & 0x0007fe00U) >> 9) +#define WURX_WURX1_3__ENERGY_TOOHIGH__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0007fe00U) +#define WURX_WURX1_3__ENERGY_TOOHIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0007fe00U) +#define WURX_WURX1_3__ENERGY_TOOHIGH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0007fe00U))) +#define WURX_WURX1_3__ENERGY_TOOHIGH__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field sym1_threshold */ +/** + * @defgroup pmu_wurx_regs_core_sym1_threshold_field sym1_threshold_field + * @brief macros for field sym1_threshold + * @details number of counts above this means symbol 1 is detected + * @{ + */ +#define WURX_WURX1_3__SYM1_THRESHOLD__SHIFT 19 +#define WURX_WURX1_3__SYM1_THRESHOLD__WIDTH 10 +#define WURX_WURX1_3__SYM1_THRESHOLD__MASK 0x1ff80000U +#define WURX_WURX1_3__SYM1_THRESHOLD__READ(src) \ + (((uint32_t)(src)\ + & 0x1ff80000U) >> 19) +#define WURX_WURX1_3__SYM1_THRESHOLD__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x1ff80000U) +#define WURX_WURX1_3__SYM1_THRESHOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1ff80000U) | (((uint32_t)(src) <<\ + 19) & 0x1ff80000U) +#define WURX_WURX1_3__SYM1_THRESHOLD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x1ff80000U))) +#define WURX_WURX1_3__SYM1_THRESHOLD__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field clk_freq */ +/** + * @defgroup pmu_wurx_regs_core_clk_freq_field clk_freq_field + * @brief macros for field clk_freq + * @details 0 - 16KHz, 1- 32KHz + * @{ + */ +#define WURX_WURX1_3__CLK_FREQ__SHIFT 29 +#define WURX_WURX1_3__CLK_FREQ__WIDTH 1 +#define WURX_WURX1_3__CLK_FREQ__MASK 0x20000000U +#define WURX_WURX1_3__CLK_FREQ__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define WURX_WURX1_3__CLK_FREQ__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define WURX_WURX1_3__CLK_FREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define WURX_WURX1_3__CLK_FREQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define WURX_WURX1_3__CLK_FREQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define WURX_WURX1_3__CLK_FREQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define WURX_WURX1_3__CLK_FREQ__RESET_VALUE 0x00000001U +/** @} */ +#define WURX_WURX1_3__TYPE uint32_t +#define WURX_WURX1_3__READ 0x3fffffffU +#define WURX_WURX1_3__WRITE 0x3fffffffU +#define WURX_WURX1_3__PRESERVED 0x00000000U +#define WURX_WURX1_3__RESET_VALUE 0x20100c04U + +#endif /* __WURX_WURX1_3_MACRO__ */ + +/** @} end of wurx1_3 */ + +/* macros for BlueprintGlobalNameSpace::WURX_wurx1_4 */ +/** + * @defgroup pmu_wurx_regs_core_wurx1_4 wurx1_4 + * @brief Wake-up RX settings, algorithm 0 definitions. + * @{ + */ +#ifndef __WURX_WURX1_4_MACRO__ +#define __WURX_WURX1_4_MACRO__ + +/* macros for field timer_max */ +/** + * @defgroup pmu_wurx_regs_core_timer_max_field timer_max_field + * @brief macros for field timer_max + * @details number of cycles in one symbol period - 1 + * @{ + */ +#define WURX_WURX1_4__TIMER_MAX__SHIFT 0 +#define WURX_WURX1_4__TIMER_MAX__WIDTH 10 +#define WURX_WURX1_4__TIMER_MAX__MASK 0x000003ffU +#define WURX_WURX1_4__TIMER_MAX__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define WURX_WURX1_4__TIMER_MAX__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define WURX_WURX1_4__TIMER_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define WURX_WURX1_4__TIMER_MAX__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define WURX_WURX1_4__TIMER_MAX__RESET_VALUE 0x0000000fU +/** @} */ + +/* macros for field sym_silent_thr */ +/** + * @defgroup pmu_wurx_regs_core_sym_silent_thr_field sym_silent_thr_field + * @brief macros for field sym_silent_thr + * @details number of consecutive 0's considered as noise in a sym window + * @{ + */ +#define WURX_WURX1_4__SYM_SILENT_THR__SHIFT 10 +#define WURX_WURX1_4__SYM_SILENT_THR__WIDTH 5 +#define WURX_WURX1_4__SYM_SILENT_THR__MASK 0x00007c00U +#define WURX_WURX1_4__SYM_SILENT_THR__READ(src) \ + (((uint32_t)(src)\ + & 0x00007c00U) >> 10) +#define WURX_WURX1_4__SYM_SILENT_THR__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00007c00U) +#define WURX_WURX1_4__SYM_SILENT_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((uint32_t)(src) <<\ + 10) & 0x00007c00U) +#define WURX_WURX1_4__SYM_SILENT_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00007c00U))) +#define WURX_WURX1_4__SYM_SILENT_THR__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field init_cal_step */ +/** + * @defgroup pmu_wurx_regs_core_init_cal_step_field init_cal_step_field + * @brief macros for field init_cal_step + * @details initial cal step + * @{ + */ +#define WURX_WURX1_4__INIT_CAL_STEP__SHIFT 15 +#define WURX_WURX1_4__INIT_CAL_STEP__WIDTH 9 +#define WURX_WURX1_4__INIT_CAL_STEP__MASK 0x00ff8000U +#define WURX_WURX1_4__INIT_CAL_STEP__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff8000U) >> 15) +#define WURX_WURX1_4__INIT_CAL_STEP__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00ff8000U) +#define WURX_WURX1_4__INIT_CAL_STEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff8000U) | (((uint32_t)(src) <<\ + 15) & 0x00ff8000U) +#define WURX_WURX1_4__INIT_CAL_STEP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00ff8000U))) +#define WURX_WURX1_4__INIT_CAL_STEP__RESET_VALUE 0x00000100U +/** @} */ + +/* macros for field cal_silent_thr */ +/** + * @defgroup pmu_wurx_regs_core_cal_silent_thr_field cal_silent_thr_field + * @brief macros for field cal_silent_thr + * @details number of consecutive 0's considered as noise in a thr window + * @{ + */ +#define WURX_WURX1_4__CAL_SILENT_THR__SHIFT 24 +#define WURX_WURX1_4__CAL_SILENT_THR__WIDTH 7 +#define WURX_WURX1_4__CAL_SILENT_THR__MASK 0x7f000000U +#define WURX_WURX1_4__CAL_SILENT_THR__READ(src) \ + (((uint32_t)(src)\ + & 0x7f000000U) >> 24) +#define WURX_WURX1_4__CAL_SILENT_THR__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x7f000000U) +#define WURX_WURX1_4__CAL_SILENT_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((uint32_t)(src) <<\ + 24) & 0x7f000000U) +#define WURX_WURX1_4__CAL_SILENT_THR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x7f000000U))) +#define WURX_WURX1_4__CAL_SILENT_THR__RESET_VALUE 0x00000008U +/** @} */ +#define WURX_WURX1_4__TYPE uint32_t +#define WURX_WURX1_4__READ 0x7fffffffU +#define WURX_WURX1_4__WRITE 0x7fffffffU +#define WURX_WURX1_4__PRESERVED 0x00000000U +#define WURX_WURX1_4__RESET_VALUE 0x0880200fU + +#endif /* __WURX_WURX1_4_MACRO__ */ + +/** @} end of wurx1_4 */ + +/* macros for BlueprintGlobalNameSpace::WURX_wurx_rb0 */ +/** + * @defgroup pmu_wurx_regs_core_wurx_rb0 wurx_rb0 + * @brief Wake-up RX read-out bits, algorithm 0 definitions. + * @{ + */ +#ifndef __WURX_WURX_RB0_MACRO__ +#define __WURX_WURX_RB0_MACRO__ + +/* macros for field state */ +/** + * @defgroup pmu_wurx_regs_core_state_field state_field + * @brief macros for field state + * @details FSM state + * @{ + */ +#define WURX_WURX_RB0__STATE__SHIFT 0 +#define WURX_WURX_RB0__STATE__WIDTH 2 +#define WURX_WURX_RB0__STATE__MASK 0x00000003U +#define WURX_WURX_RB0__STATE__READ(src) ((uint32_t)(src) & 0x00000003U) +#define WURX_WURX_RB0__STATE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field out_energy */ +/** + * @defgroup pmu_wurx_regs_core_out_energy_field out_energy_field + * @brief macros for field out_energy + * @details symbol energy + * @{ + */ +#define WURX_WURX_RB0__OUT_ENERGY__SHIFT 2 +#define WURX_WURX_RB0__OUT_ENERGY__WIDTH 10 +#define WURX_WURX_RB0__OUT_ENERGY__MASK 0x00000ffcU +#define WURX_WURX_RB0__OUT_ENERGY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000ffcU) >> 2) +#define WURX_WURX_RB0__OUT_ENERGY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cal_step */ +/** + * @defgroup pmu_wurx_regs_core_cal_step_field cal_step_field + * @brief macros for field cal_step + * @details FSM binary cal step + * @{ + */ +#define WURX_WURX_RB0__CAL_STEP__SHIFT 12 +#define WURX_WURX_RB0__CAL_STEP__WIDTH 8 +#define WURX_WURX_RB0__CAL_STEP__MASK 0x000ff000U +#define WURX_WURX_RB0__CAL_STEP__READ(src) \ + (((uint32_t)(src)\ + & 0x000ff000U) >> 12) +#define WURX_WURX_RB0__CAL_STEP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field monitor_2hi */ +/** + * @defgroup pmu_wurx_regs_core_monitor_2hi_field monitor_2hi_field + * @brief macros for field monitor_2hi + * @details number of consecutive symbols with too high energy + * @{ + */ +#define WURX_WURX_RB0__MONITOR_2HI__SHIFT 20 +#define WURX_WURX_RB0__MONITOR_2HI__WIDTH 5 +#define WURX_WURX_RB0__MONITOR_2HI__MASK 0x01f00000U +#define WURX_WURX_RB0__MONITOR_2HI__READ(src) \ + (((uint32_t)(src)\ + & 0x01f00000U) >> 20) +#define WURX_WURX_RB0__MONITOR_2HI__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field monitor_2lo */ +/** + * @defgroup pmu_wurx_regs_core_monitor_2lo_field monitor_2lo_field + * @brief macros for field monitor_2lo + * @details number of consecutive symbols with too low energy + * @{ + */ +#define WURX_WURX_RB0__MONITOR_2LO__SHIFT 25 +#define WURX_WURX_RB0__MONITOR_2LO__WIDTH 5 +#define WURX_WURX_RB0__MONITOR_2LO__MASK 0x3e000000U +#define WURX_WURX_RB0__MONITOR_2LO__READ(src) \ + (((uint32_t)(src)\ + & 0x3e000000U) >> 25) +#define WURX_WURX_RB0__MONITOR_2LO__RESET_VALUE 0x00000000U +/** @} */ +#define WURX_WURX_RB0__TYPE uint32_t +#define WURX_WURX_RB0__READ 0x3fffffffU +#define WURX_WURX_RB0__PRESERVED 0x00000000U +#define WURX_WURX_RB0__RESET_VALUE 0x00000000U + +#endif /* __WURX_WURX_RB0_MACRO__ */ + +/** @} end of wurx_rb0 */ + +/* macros for BlueprintGlobalNameSpace::WURX_wurx_rb1 */ +/** + * @defgroup pmu_wurx_regs_core_wurx_rb1 wurx_rb1 + * @brief Wake-up RX read-out bits, algorithm 0 definitions. + * @{ + */ +#ifndef __WURX_WURX_RB1_MACRO__ +#define __WURX_WURX_RB1_MACRO__ + +/* macros for field offset_cal */ +/** + * @defgroup pmu_wurx_regs_core_offset_cal_field offset_cal_field + * @brief macros for field offset_cal + * @details read back analog cal value --> make it common for both algorithms + * @{ + */ +#define WURX_WURX_RB1__OFFSET_CAL__SHIFT 0 +#define WURX_WURX_RB1__OFFSET_CAL__WIDTH 8 +#define WURX_WURX_RB1__OFFSET_CAL__MASK 0x000000ffU +#define WURX_WURX_RB1__OFFSET_CAL__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define WURX_WURX_RB1__OFFSET_CAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field analog_cal */ +/** + * @defgroup pmu_wurx_regs_core_analog_cal_field analog_cal_field + * @brief macros for field analog_cal + * @details readback + * @{ + */ +#define WURX_WURX_RB1__ANALOG_CAL__SHIFT 8 +#define WURX_WURX_RB1__ANALOG_CAL__WIDTH 9 +#define WURX_WURX_RB1__ANALOG_CAL__MASK 0x0001ff00U +#define WURX_WURX_RB1__ANALOG_CAL__READ(src) \ + (((uint32_t)(src)\ + & 0x0001ff00U) >> 8) +#define WURX_WURX_RB1__ANALOG_CAL__RESET_VALUE 0x00000000U +/** @} */ +#define WURX_WURX_RB1__TYPE uint32_t +#define WURX_WURX_RB1__READ 0x0001ffffU +#define WURX_WURX_RB1__PRESERVED 0x00000000U +#define WURX_WURX_RB1__RESET_VALUE 0x00000000U + +#endif /* __WURX_WURX_RB1_MACRO__ */ + +/** @} end of wurx_rb1 */ + +/* macros for BlueprintGlobalNameSpace::WURX_wurx_rb2 */ +/** + * @defgroup pmu_wurx_regs_core_wurx_rb2 wurx_rb2 + * @brief Wake-up RX read-out bits definitions. + * @{ + */ +#ifndef __WURX_WURX_RB2_MACRO__ +#define __WURX_WURX_RB2_MACRO__ + +/* macros for field cnt_det0 */ +/** + * @defgroup pmu_wurx_regs_core_cnt_det0_field cnt_det0_field + * @brief macros for field cnt_det0 + * @details number of wake_det[0] + * @{ + */ +#define WURX_WURX_RB2__CNT_DET0__SHIFT 0 +#define WURX_WURX_RB2__CNT_DET0__WIDTH 10 +#define WURX_WURX_RB2__CNT_DET0__MASK 0x000003ffU +#define WURX_WURX_RB2__CNT_DET0__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define WURX_WURX_RB2__CNT_DET0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cnt_det1 */ +/** + * @defgroup pmu_wurx_regs_core_cnt_det1_field cnt_det1_field + * @brief macros for field cnt_det1 + * @details number of wake_det[1] + * @{ + */ +#define WURX_WURX_RB2__CNT_DET1__SHIFT 10 +#define WURX_WURX_RB2__CNT_DET1__WIDTH 10 +#define WURX_WURX_RB2__CNT_DET1__MASK 0x000ffc00U +#define WURX_WURX_RB2__CNT_DET1__READ(src) \ + (((uint32_t)(src)\ + & 0x000ffc00U) >> 10) +#define WURX_WURX_RB2__CNT_DET1__RESET_VALUE 0x00000000U +/** @} */ +#define WURX_WURX_RB2__TYPE uint32_t +#define WURX_WURX_RB2__READ 0x000fffffU +#define WURX_WURX_RB2__PRESERVED 0x00000000U +#define WURX_WURX_RB2__RESET_VALUE 0x00000000U + +#endif /* __WURX_WURX_RB2_MACRO__ */ + +/** @} end of wurx_rb2 */ + +/* macros for BlueprintGlobalNameSpace::WURX_wurx_spare */ +/** + * @defgroup pmu_wurx_regs_core_wurx_spare wurx_spare + * @brief Wake-up RX spare bits definitions. + * @{ + */ +#ifndef __WURX_WURX_SPARE_MACRO__ +#define __WURX_WURX_SPARE_MACRO__ + +/* macros for field wurx_dig_in_sel */ +/** + * @defgroup pmu_wurx_regs_core_wurx_dig_in_sel_field wurx_dig_in_sel_field + * @brief macros for field wurx_dig_in_sel + * @details select between wurx analog and rectifier output + * @{ + */ +#define WURX_WURX_SPARE__WURX_DIG_IN_SEL__SHIFT 0 +#define WURX_WURX_SPARE__WURX_DIG_IN_SEL__WIDTH 1 +#define WURX_WURX_SPARE__WURX_DIG_IN_SEL__MASK 0x00000001U +#define WURX_WURX_SPARE__WURX_DIG_IN_SEL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WURX_WURX_SPARE__WURX_DIG_IN_SEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define WURX_WURX_SPARE__WURX_DIG_IN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define WURX_WURX_SPARE__WURX_DIG_IN_SEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define WURX_WURX_SPARE__WURX_DIG_IN_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define WURX_WURX_SPARE__WURX_DIG_IN_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define WURX_WURX_SPARE__WURX_DIG_IN_SEL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field longRst */ +/** + * @defgroup pmu_wurx_regs_core_longRst_field longRst_field + * @brief macros for field longRst + * @details resets the output while the clock is low (same as sydney) + * @{ + */ +#define WURX_WURX_SPARE__LONGRST__SHIFT 1 +#define WURX_WURX_SPARE__LONGRST__WIDTH 1 +#define WURX_WURX_SPARE__LONGRST__MASK 0x00000002U +#define WURX_WURX_SPARE__LONGRST__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define WURX_WURX_SPARE__LONGRST__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define WURX_WURX_SPARE__LONGRST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define WURX_WURX_SPARE__LONGRST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define WURX_WURX_SPARE__LONGRST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define WURX_WURX_SPARE__LONGRST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define WURX_WURX_SPARE__LONGRST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field delRst */ +/** + * @defgroup pmu_wurx_regs_core_delRst_field delRst_field + * @brief macros for field delRst + * @details adjusts output reset time + * @{ + */ +#define WURX_WURX_SPARE__DELRST__SHIFT 2 +#define WURX_WURX_SPARE__DELRST__WIDTH 2 +#define WURX_WURX_SPARE__DELRST__MASK 0x0000000cU +#define WURX_WURX_SPARE__DELRST__READ(src) \ + (((uint32_t)(src)\ + & 0x0000000cU) >> 2) +#define WURX_WURX_SPARE__DELRST__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000000cU) +#define WURX_WURX_SPARE__DELRST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((uint32_t)(src) <<\ + 2) & 0x0000000cU) +#define WURX_WURX_SPARE__DELRST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000000cU))) +#define WURX_WURX_SPARE__DELRST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bypassAmp */ +/** + * @defgroup pmu_wurx_regs_core_bypassAmp_field bypassAmp_field + * @brief macros for field bypassAmp + * @details do not use amp to bias source follower + * @{ + */ +#define WURX_WURX_SPARE__BYPASSAMP__SHIFT 4 +#define WURX_WURX_SPARE__BYPASSAMP__WIDTH 1 +#define WURX_WURX_SPARE__BYPASSAMP__MASK 0x00000010U +#define WURX_WURX_SPARE__BYPASSAMP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define WURX_WURX_SPARE__BYPASSAMP__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define WURX_WURX_SPARE__BYPASSAMP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define WURX_WURX_SPARE__BYPASSAMP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define WURX_WURX_SPARE__BYPASSAMP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define WURX_WURX_SPARE__BYPASSAMP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define WURX_WURX_SPARE__BYPASSAMP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field settle1_reg */ +/** + * @defgroup pmu_wurx_regs_core_settle1_reg_field settle1_reg_field + * @brief macros for field settle1_reg + * @details wait time after power on for bias at max load + * @{ + */ +#define WURX_WURX_SPARE__SETTLE1_REG__SHIFT 5 +#define WURX_WURX_SPARE__SETTLE1_REG__WIDTH 5 +#define WURX_WURX_SPARE__SETTLE1_REG__MASK 0x000003e0U +#define WURX_WURX_SPARE__SETTLE1_REG__READ(src) \ + (((uint32_t)(src)\ + & 0x000003e0U) >> 5) +#define WURX_WURX_SPARE__SETTLE1_REG__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x000003e0U) +#define WURX_WURX_SPARE__SETTLE1_REG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((uint32_t)(src) <<\ + 5) & 0x000003e0U) +#define WURX_WURX_SPARE__SETTLE1_REG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000003e0U))) +#define WURX_WURX_SPARE__SETTLE1_REG__RESET_VALUE 0x0000000dU +/** @} */ + +/* macros for field settle2_reg */ +/** + * @defgroup pmu_wurx_regs_core_settle2_reg_field settle2_reg_field + * @brief macros for field settle2_reg + * @details wait time after power on with load and bias set to default + * @{ + */ +#define WURX_WURX_SPARE__SETTLE2_REG__SHIFT 10 +#define WURX_WURX_SPARE__SETTLE2_REG__WIDTH 5 +#define WURX_WURX_SPARE__SETTLE2_REG__MASK 0x00007c00U +#define WURX_WURX_SPARE__SETTLE2_REG__READ(src) \ + (((uint32_t)(src)\ + & 0x00007c00U) >> 10) +#define WURX_WURX_SPARE__SETTLE2_REG__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00007c00U) +#define WURX_WURX_SPARE__SETTLE2_REG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((uint32_t)(src) <<\ + 10) & 0x00007c00U) +#define WURX_WURX_SPARE__SETTLE2_REG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00007c00U))) +#define WURX_WURX_SPARE__SETTLE2_REG__RESET_VALUE 0x00000011U +/** @} */ + +/* macros for field spares */ +/** + * @defgroup pmu_wurx_regs_core_spares_field spares_field + * @brief macros for field spares + * @details wurx local register spare bits + * @{ + */ +#define WURX_WURX_SPARE__SPARES__SHIFT 15 +#define WURX_WURX_SPARE__SPARES__WIDTH 17 +#define WURX_WURX_SPARE__SPARES__MASK 0xffff8000U +#define WURX_WURX_SPARE__SPARES__READ(src) \ + (((uint32_t)(src)\ + & 0xffff8000U) >> 15) +#define WURX_WURX_SPARE__SPARES__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0xffff8000U) +#define WURX_WURX_SPARE__SPARES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff8000U) | (((uint32_t)(src) <<\ + 15) & 0xffff8000U) +#define WURX_WURX_SPARE__SPARES__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0xffff8000U))) +#define WURX_WURX_SPARE__SPARES__RESET_VALUE 0x00000000U +/** @} */ +#define WURX_WURX_SPARE__TYPE uint32_t +#define WURX_WURX_SPARE__READ 0xffffffffU +#define WURX_WURX_SPARE__WRITE 0xffffffffU +#define WURX_WURX_SPARE__PRESERVED 0x00000000U +#define WURX_WURX_SPARE__RESET_VALUE 0x000045a1U + +#endif /* __WURX_WURX_SPARE_MACRO__ */ + +/** @} end of wurx_spare */ + +/* macros for BlueprintGlobalNameSpace::WURX_core_id */ +/** + * @defgroup pmu_wurx_regs_core_core_id core_id + * @brief Core ID definitions. + * @{ + */ +#ifndef __WURX_CORE_ID_MACRO__ +#define __WURX_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup pmu_wurx_regs_core_id_field id_field + * @brief macros for field id + * @details WURX in ASCII + * @{ + */ +#define WURX_CORE_ID__ID__SHIFT 0 +#define WURX_CORE_ID__ID__WIDTH 32 +#define WURX_CORE_ID__ID__MASK 0xffffffffU +#define WURX_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define WURX_CORE_ID__ID__RESET_VALUE 0x57555258U +/** @} */ +#define WURX_CORE_ID__TYPE uint32_t +#define WURX_CORE_ID__READ 0xffffffffU +#define WURX_CORE_ID__PRESERVED 0x00000000U +#define WURX_CORE_ID__RESET_VALUE 0x57555258U + +#endif /* __WURX_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of PMU_WURX_REGS_CORE */ +#endif /* __REG_PMU_WURX_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/pseq_states.h b/ATM33xx-5/include/reg/pseq_states.h new file mode 100644 index 0000000..7d2229a --- /dev/null +++ b/ATM33xx-5/include/reg/pseq_states.h @@ -0,0 +1,205 @@ +/** + ***************************************************************************** + * + * @file pseq_states.h + * + * @brief PSEQ State Machine definitions + * + * Copyright (C) Atmosic 2022-2024 + * + ***************************************************************************** + */ + +#pragma once + +#define PSEQ_STATE_START 0 +#define PSEQ_STATE_START_BRANCH 1 +#define PSEQ_STATE_START_2 2 +#define PSEQ_STATE_START_2_BRANCH 3 +#define PSEQ_STATE_START_3 4 +#define PSEQ_STATE_START_3_BRANCH 5 +#define PSEQ_STATE_START_4 6 +#define PSEQ_STATE_START_4_BRANCH 7 +#define PSEQ_STATE_CPU_ACT_START 8 +#define PSEQ_STATE_CPU_ACT_START_BRANCH 9 +#define PSEQ_STATE_CPU_ACT_2 10 +#define PSEQ_STATE_CPU_ACT_2_BRANCH 11 +#define PSEQ_STATE_CPU_ACT_3 12 +#define PSEQ_STATE_CPU_ACT_3_BRANCH 13 +#define PSEQ_STATE_CPU_ACT 14 +#define PSEQ_STATE_CPU_ACT_BRANCH 15 +#define PSEQ_STATE_BLE_BOOT_START 16 +#define PSEQ_STATE_BLE_BOOT_START_BRANCH 17 +#define PSEQ_STATE_BLE_BOOT_2 18 +#define PSEQ_STATE_BLE_BOOT_2_BRANCH 19 +#define PSEQ_STATE_BLE_BOOT_3 20 +#define PSEQ_STATE_BLE_BOOT_3_BRANCH 21 +#define PSEQ_STATE_BLE_BOOT_4 22 +#define PSEQ_STATE_BLE_BOOT_4_BRANCH 23 +#define PSEQ_STATE_BLE_BOOT 24 +#define PSEQ_STATE_BLE_BOOT_BRANCH 25 +#define PSEQ_STATE_ACT 26 +#define PSEQ_STATE_ACT_BRANCH 27 +#define PSEQ_STATE_HIB_START 28 +#define PSEQ_STATE_HIB_START_BRANCH 29 +#define PSEQ_STATE_HIB_1 30 +#define PSEQ_STATE_HIB_1_BRANCH 31 +#define PSEQ_STATE_HIB_2 32 +#define PSEQ_STATE_HIB_2_BRANCH 33 +#define PSEQ_STATE_HIB_3 34 +#define PSEQ_STATE_HIB_3_BRANCH 35 +#define PSEQ_STATE_HIB_4 36 +#define PSEQ_STATE_HIB_4_BRANCH 37 +#define PSEQ_STATE_HIB_5 38 +#define PSEQ_STATE_HIB_5_BRANCH 39 +#define PSEQ_STATE_HIB_6 40 +#define PSEQ_STATE_HIB_6_BRANCH 41 +#define PSEQ_STATE_HIB_7 42 +#define PSEQ_STATE_HIB_7_BRANCH 43 +#define PSEQ_STATE_HIB 44 +#define PSEQ_STATE_HIB_BRANCH 45 +#define PSEQ_STATE_HIB_SHUB_STOP 46 +#define PSEQ_STATE_HIB_SHUB_STOP_BRANCH 47 +#define PSEQ_STATE_HIB_UP_START 48 +#define PSEQ_STATE_HIB_UP_START_BRANCH 49 +#define PSEQ_STATE_HIB_UP_2 50 +#define PSEQ_STATE_HIB_UP_2_BRANCH 51 +#define PSEQ_STATE_HIB_UP_3A 52 +#define PSEQ_STATE_HIB_UP_3A_BRANCH 53 +#define PSEQ_STATE_HIB_UP_3B 54 +#define PSEQ_STATE_HIB_UP_3B_BRANCH 55 +#define PSEQ_STATE_HIB_UP_3C 56 +#define PSEQ_STATE_HIB_UP_3C_BRANCH 57 +#define PSEQ_STATE_HIB_UP_3D 58 +#define PSEQ_STATE_HIB_UP_3D_BRANCH 59 +#define PSEQ_STATE_HIB_UP_3E 60 +#define PSEQ_STATE_HIB_UP_3E_BRANCH 61 +#define PSEQ_STATE_HIB_UP_4 62 +#define PSEQ_STATE_HIB_UP_4_BRANCH 63 +#define PSEQ_STATE_HIB_UP_5 64 +#define PSEQ_STATE_HIB_UP_5_BRANCH 65 +#define PSEQ_STATE_HIB_UP_6 66 +#define PSEQ_STATE_HIB_UP_6_BRANCH 67 +#define PSEQ_STATE_HIB_UP_7 68 +#define PSEQ_STATE_HIB_UP_7_BRANCH 69 +#define PSEQ_STATE_HIB_UP_8 70 +#define PSEQ_STATE_HIB_UP_8_BRANCH 71 +#define PSEQ_STATE_HIB_UP_9 72 +#define PSEQ_STATE_HIB_UP_9_BRANCH 73 +#define PSEQ_STATE_HIB_UP_10 74 +#define PSEQ_STATE_HIB_UP_10_BRANCH 75 +#define PSEQ_STATE_HIB_BLE_START 76 +#define PSEQ_STATE_HIB_BLE_START_BRANCH 77 +#define PSEQ_STATE_HIB_BLE_1 78 +#define PSEQ_STATE_HIB_BLE_1_BRANCH 79 +#define PSEQ_STATE_HIB_BLE_2 80 +#define PSEQ_STATE_HIB_BLE_2_BRANCH 81 +#define PSEQ_STATE_HIB_BLE_3 82 +#define PSEQ_STATE_HIB_BLE_3_BRANCH 83 +#define PSEQ_STATE_HIB_BLE_4 84 +#define PSEQ_STATE_HIB_BLE_4_BRANCH 85 +#define PSEQ_STATE_HIB_BLE_5 86 +#define PSEQ_STATE_HIB_BLE_5_BRANCH 87 +#define PSEQ_STATE_HIB_BLE_6 88 +#define PSEQ_STATE_HIB_BLE_6_BRANCH 89 +#define PSEQ_STATE_HIB_BLE_7 90 +#define PSEQ_STATE_HIB_BLE_7_BRANCH 91 +#define PSEQ_STATE_HIB_BLE 92 +#define PSEQ_STATE_HIB_BLE_BRANCH 93 +#define PSEQ_STATE_SHUB_ADV_UP_START 94 +#define PSEQ_STATE_SHUB_ADV_UP_START_BRANCH 95 +#define PSEQ_STATE_SHUB_BLE_RET_UP_2 96 +#define PSEQ_STATE_SHUB_BLE_RET_UP_2_BRANCH 97 +#define PSEQ_STATE_SHUB_BLE_RET_UP_3 98 +#define PSEQ_STATE_SHUB_BLE_RET_UP_3_BRANCH 99 +#define PSEQ_STATE_SHUB_BLE_RET_UP_4 100 +#define PSEQ_STATE_SHUB_BLE_RET_UP_4_BRANCH 101 +#define PSEQ_STATE_SHUB_BLE_RET_UP 102 +#define PSEQ_STATE_SHUB_BLE_RET_UP_BRANCH 103 +#define PSEQ_STATE_SHUB_ADV 104 +#define PSEQ_STATE_SHUB_ADV_BRANCH 105 +#define PSEQ_STATE_RET_ALL_START 106 +#define PSEQ_STATE_RET_ALL_START_BRANCH 107 +#define PSEQ_STATE_RET_ALL_1 108 +#define PSEQ_STATE_RET_ALL_1_BRANCH 109 +#define PSEQ_STATE_RET_ALL_2 110 +#define PSEQ_STATE_RET_ALL_2_BRANCH 111 +#define PSEQ_STATE_RET_ALL_3 112 +#define PSEQ_STATE_RET_ALL_3_BRANCH 113 +#define PSEQ_STATE_RET_ALL_4 114 +#define PSEQ_STATE_RET_ALL_4_BRANCH 115 +#define PSEQ_STATE_RET_ALL_5 116 +#define PSEQ_STATE_RET_ALL_5_BRANCH 117 +#define PSEQ_STATE_RET_ALL_6 118 +#define PSEQ_STATE_RET_ALL_6_BRANCH 119 +#define PSEQ_STATE_RET_ALL_7 120 +#define PSEQ_STATE_RET_ALL_7_BRANCH 121 +#define PSEQ_STATE_RET_ALL_XTAL_1 122 +#define PSEQ_STATE_RET_ALL_XTAL_1_BRANCH 123 +#define PSEQ_STATE_RET_ALL_XTAL_2 124 +#define PSEQ_STATE_RET_ALL_XTAL_2_BRANCH 125 +#define PSEQ_STATE_RET_ALL_XTAL_3 126 +#define PSEQ_STATE_RET_ALL_XTAL_3_BRANCH 127 +#define PSEQ_STATE_RET_ALL_XTAL_4 128 +#define PSEQ_STATE_RET_ALL_XTAL_4_BRANCH 129 +#define PSEQ_STATE_RET_ALL_NOXTAL_1 130 +#define PSEQ_STATE_RET_ALL_NOXTAL_1_BRANCH 131 +#define PSEQ_STATE_RET_ALL_NOXTAL_2 132 +#define PSEQ_STATE_RET_ALL_NOXTAL_2_BRANCH 133 +#define PSEQ_STATE_RET_ALL_UP_3A 134 +#define PSEQ_STATE_RET_ALL_UP_3A_BRANCH 135 +#define PSEQ_STATE_RET_ALL_UP_3B 136 +#define PSEQ_STATE_RET_ALL_UP_3B_BRANCH 137 +#define PSEQ_STATE_RET_ALL_UP_3C 138 +#define PSEQ_STATE_RET_ALL_UP_3C_BRANCH 139 +#define PSEQ_STATE_RET_ALL_UP_3D 140 +#define PSEQ_STATE_RET_ALL_UP_3D_BRANCH 141 +#define PSEQ_STATE_RET_ALL_UP_4 142 +#define PSEQ_STATE_RET_ALL_UP_4_BRANCH 143 +#define PSEQ_STATE_RET_ALL_UP_5 144 +#define PSEQ_STATE_RET_ALL_UP_5_BRANCH 145 +#define PSEQ_STATE_RET_ALL_UP_6 146 +#define PSEQ_STATE_RET_ALL_UP_6_BRANCH 147 +#define PSEQ_STATE_RET_ALL_UP_7 148 +#define PSEQ_STATE_RET_ALL_UP_7_BRANCH 149 +#define PSEQ_STATE_RET_ALL_UP_8 150 +#define PSEQ_STATE_RET_ALL_UP_8_BRANCH 151 +#define PSEQ_STATE_RET_ALL_UP_9 152 +#define PSEQ_STATE_RET_ALL_UP_9_BRANCH 153 +#define PSEQ_STATE_BLE_ONLY_LP_START 154 +#define PSEQ_STATE_BLE_ONLY_LP_START_BRANCH 155 +#define PSEQ_STATE_BLE_ONLY_LP_1 156 +#define PSEQ_STATE_BLE_ONLY_LP_1_BRANCH 157 +#define PSEQ_STATE_BLE_ONLY_LP_2 158 +#define PSEQ_STATE_BLE_ONLY_LP_2_BRANCH 159 +#define PSEQ_STATE_BLE_ONLY_LP_3 160 +#define PSEQ_STATE_BLE_ONLY_LP_3_BRANCH 161 +#define PSEQ_STATE_BLE_ONLY_LP_4 162 +#define PSEQ_STATE_BLE_ONLY_LP_4_BRANCH 163 +#define PSEQ_STATE_BLE_ONLY_LP_5 164 +#define PSEQ_STATE_BLE_ONLY_LP_5_BRANCH 165 +#define PSEQ_STATE_BLE_ONLY_XTAL_1 166 +#define PSEQ_STATE_BLE_ONLY_XTAL_1_BRANCH 167 +#define PSEQ_STATE_BLE_ONLY_BOTTOM 168 +#define PSEQ_STATE_BLE_ONLY_BOTTOM_BRANCH 169 +#define PSEQ_STATE_BLE_ONLY_UP_1 170 +#define PSEQ_STATE_BLE_ONLY_UP_1_BRANCH 171 +#define PSEQ_STATE_BLE_ONLY_UP_2 172 +#define PSEQ_STATE_BLE_ONLY_UP_2_BRANCH 173 +#define PSEQ_STATE_BLE_ONLY_UP_3 174 +#define PSEQ_STATE_BLE_ONLY_UP_3_BRANCH 175 +#define PSEQ_STATE_BLE_ONLY_UP_4 176 +#define PSEQ_STATE_BLE_ONLY_UP_4_BRANCH 177 +#define PSEQ_STATE_BLE_ONLY_UP_5 178 +#define PSEQ_STATE_BLE_ONLY_UP_5_BRANCH 179 +#define PSEQ_STATE_BLE_ONLY_UP_6 180 +#define PSEQ_STATE_BLE_ONLY_UP_6_BRANCH 181 +#define PSEQ_STATE_BLE_ONLY_UP_7 182 +#define PSEQ_STATE_BLE_ONLY_UP_7_BRANCH 183 +#define PSEQ_STATE_BLE_ONLY_UP_8 184 +#define PSEQ_STATE_BLE_ONLY_UP_8_BRANCH 185 +#define PSEQ_STATE_BLE_ONLY_UP_9 186 +#define PSEQ_STATE_BLE_ONLY_UP_9_BRANCH 187 +#define PSEQ_STATE_BLE_ONLY_UP_10 188 +#define PSEQ_STATE_BLE_ONLY_UP_10_BRANCH 189 +#define PSEQ_STATE_BLE_ONLY_UP_11 190 diff --git a/ATM33xx-5/include/reg/radio_rx_regs_core_macro.h b/ATM33xx-5/include/reg/radio_rx_regs_core_macro.h new file mode 100644 index 0000000..53093d7 --- /dev/null +++ b/ATM33xx-5/include/reg/radio_rx_regs_core_macro.h @@ -0,0 +1,2973 @@ +/* */ +/* File: radio_rx_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic radio_rx_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_RADIO_RX_REGS_CORE_H__ +#define __REG_RADIO_RX_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup RADIO_RX_REGS_CORE radio_rx_regs_core + * @ingroup AT_REG + * @brief radio_rx_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::radio_rx_mode_ctrl */ +/** + * @defgroup radio_rx_regs_core_mode_ctrl mode_ctrl + * @brief Enable and mode overrides definitions. + * @{ + */ +#ifndef __RADIO_RX_MODE_CTRL_MACRO__ +#define __RADIO_RX_MODE_CTRL_MACRO__ + +/* macros for field lna_en_ovr */ +/** + * @defgroup radio_rx_regs_core_lna_en_ovr_field lna_en_ovr_field + * @brief macros for field lna_en_ovr + * @details LNA enable override + * @{ + */ +#define RADIO_RX_MODE_CTRL__LNA_EN_OVR__SHIFT 0 +#define RADIO_RX_MODE_CTRL__LNA_EN_OVR__WIDTH 2 +#define RADIO_RX_MODE_CTRL__LNA_EN_OVR__MASK 0x00000003U +#define RADIO_RX_MODE_CTRL__LNA_EN_OVR__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define RADIO_RX_MODE_CTRL__LNA_EN_OVR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define RADIO_RX_MODE_CTRL__LNA_EN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define RADIO_RX_MODE_CTRL__LNA_EN_OVR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define RADIO_RX_MODE_CTRL__LNA_EN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field lnapd_en_ovr */ +/** + * @defgroup radio_rx_regs_core_lnapd_en_ovr_field lnapd_en_ovr_field + * @brief macros for field lnapd_en_ovr + * @details LNA peak detector enable override + * @{ + */ +#define RADIO_RX_MODE_CTRL__LNAPD_EN_OVR__SHIFT 2 +#define RADIO_RX_MODE_CTRL__LNAPD_EN_OVR__WIDTH 2 +#define RADIO_RX_MODE_CTRL__LNAPD_EN_OVR__MASK 0x0000000cU +#define RADIO_RX_MODE_CTRL__LNAPD_EN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x0000000cU) >> 2) +#define RADIO_RX_MODE_CTRL__LNAPD_EN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000000cU) +#define RADIO_RX_MODE_CTRL__LNAPD_EN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((uint32_t)(src) <<\ + 2) & 0x0000000cU) +#define RADIO_RX_MODE_CTRL__LNAPD_EN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000000cU))) +#define RADIO_RX_MODE_CTRL__LNAPD_EN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mixer_en_ovr */ +/** + * @defgroup radio_rx_regs_core_mixer_en_ovr_field mixer_en_ovr_field + * @brief macros for field mixer_en_ovr + * @details Mixer enable override + * @{ + */ +#define RADIO_RX_MODE_CTRL__MIXER_EN_OVR__SHIFT 4 +#define RADIO_RX_MODE_CTRL__MIXER_EN_OVR__WIDTH 1 +#define RADIO_RX_MODE_CTRL__MIXER_EN_OVR__MASK 0x00000010U +#define RADIO_RX_MODE_CTRL__MIXER_EN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define RADIO_RX_MODE_CTRL__MIXER_EN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define RADIO_RX_MODE_CTRL__MIXER_EN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define RADIO_RX_MODE_CTRL__MIXER_EN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define RADIO_RX_MODE_CTRL__MIXER_EN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define RADIO_RX_MODE_CTRL__MIXER_EN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define RADIO_RX_MODE_CTRL__MIXER_EN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mixer_enIdual_ovr_val */ +/** + * @defgroup radio_rx_regs_core_mixer_enIdual_ovr_val_field mixer_enIdual_ovr_val_field + * @brief macros for field mixer_enIdual_ovr_val + * @details override value for enIdual + * @{ + */ +#define RADIO_RX_MODE_CTRL__MIXER_ENIDUAL_OVR_VAL__SHIFT 5 +#define RADIO_RX_MODE_CTRL__MIXER_ENIDUAL_OVR_VAL__WIDTH 1 +#define RADIO_RX_MODE_CTRL__MIXER_ENIDUAL_OVR_VAL__MASK 0x00000020U +#define RADIO_RX_MODE_CTRL__MIXER_ENIDUAL_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define RADIO_RX_MODE_CTRL__MIXER_ENIDUAL_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define RADIO_RX_MODE_CTRL__MIXER_ENIDUAL_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define RADIO_RX_MODE_CTRL__MIXER_ENIDUAL_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define RADIO_RX_MODE_CTRL__MIXER_ENIDUAL_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define RADIO_RX_MODE_CTRL__MIXER_ENIDUAL_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define RADIO_RX_MODE_CTRL__MIXER_ENIDUAL_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mixer_enQdual_ovr_val */ +/** + * @defgroup radio_rx_regs_core_mixer_enQdual_ovr_val_field mixer_enQdual_ovr_val_field + * @brief macros for field mixer_enQdual_ovr_val + * @details override value for enQdual + * @{ + */ +#define RADIO_RX_MODE_CTRL__MIXER_ENQDUAL_OVR_VAL__SHIFT 6 +#define RADIO_RX_MODE_CTRL__MIXER_ENQDUAL_OVR_VAL__WIDTH 1 +#define RADIO_RX_MODE_CTRL__MIXER_ENQDUAL_OVR_VAL__MASK 0x00000040U +#define RADIO_RX_MODE_CTRL__MIXER_ENQDUAL_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define RADIO_RX_MODE_CTRL__MIXER_ENQDUAL_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define RADIO_RX_MODE_CTRL__MIXER_ENQDUAL_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define RADIO_RX_MODE_CTRL__MIXER_ENQDUAL_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define RADIO_RX_MODE_CTRL__MIXER_ENQDUAL_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define RADIO_RX_MODE_CTRL__MIXER_ENQDUAL_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define RADIO_RX_MODE_CTRL__MIXER_ENQDUAL_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mixer_ensingle_ovr_val */ +/** + * @defgroup radio_rx_regs_core_mixer_ensingle_ovr_val_field mixer_ensingle_ovr_val_field + * @brief macros for field mixer_ensingle_ovr_val + * @details override value for ensingle + * @{ + */ +#define RADIO_RX_MODE_CTRL__MIXER_ENSINGLE_OVR_VAL__SHIFT 7 +#define RADIO_RX_MODE_CTRL__MIXER_ENSINGLE_OVR_VAL__WIDTH 1 +#define RADIO_RX_MODE_CTRL__MIXER_ENSINGLE_OVR_VAL__MASK 0x00000080U +#define RADIO_RX_MODE_CTRL__MIXER_ENSINGLE_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define RADIO_RX_MODE_CTRL__MIXER_ENSINGLE_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define RADIO_RX_MODE_CTRL__MIXER_ENSINGLE_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define RADIO_RX_MODE_CTRL__MIXER_ENSINGLE_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define RADIO_RX_MODE_CTRL__MIXER_ENSINGLE_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define RADIO_RX_MODE_CTRL__MIXER_ENSINGLE_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define RADIO_RX_MODE_CTRL__MIXER_ENSINGLE_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_tiaI_ovr */ +/** + * @defgroup radio_rx_regs_core_en_tiaI_ovr_field en_tiaI_ovr_field + * @brief macros for field en_tiaI_ovr + * @details Override for I-channel TIA enable + * @{ + */ +#define RADIO_RX_MODE_CTRL__EN_TIAI_OVR__SHIFT 8 +#define RADIO_RX_MODE_CTRL__EN_TIAI_OVR__WIDTH 2 +#define RADIO_RX_MODE_CTRL__EN_TIAI_OVR__MASK 0x00000300U +#define RADIO_RX_MODE_CTRL__EN_TIAI_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000300U) >> 8) +#define RADIO_RX_MODE_CTRL__EN_TIAI_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000300U) +#define RADIO_RX_MODE_CTRL__EN_TIAI_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((uint32_t)(src) <<\ + 8) & 0x00000300U) +#define RADIO_RX_MODE_CTRL__EN_TIAI_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000300U))) +#define RADIO_RX_MODE_CTRL__EN_TIAI_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_tiaQ_ovr */ +/** + * @defgroup radio_rx_regs_core_en_tiaQ_ovr_field en_tiaQ_ovr_field + * @brief macros for field en_tiaQ_ovr + * @details Override for Q-channel TIA enable + * @{ + */ +#define RADIO_RX_MODE_CTRL__EN_TIAQ_OVR__SHIFT 10 +#define RADIO_RX_MODE_CTRL__EN_TIAQ_OVR__WIDTH 2 +#define RADIO_RX_MODE_CTRL__EN_TIAQ_OVR__MASK 0x00000c00U +#define RADIO_RX_MODE_CTRL__EN_TIAQ_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000c00U) >> 10) +#define RADIO_RX_MODE_CTRL__EN_TIAQ_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000c00U) +#define RADIO_RX_MODE_CTRL__EN_TIAQ_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000c00U) | (((uint32_t)(src) <<\ + 10) & 0x00000c00U) +#define RADIO_RX_MODE_CTRL__EN_TIAQ_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000c00U))) +#define RADIO_RX_MODE_CTRL__EN_TIAQ_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tiapd_en_ovr */ +/** + * @defgroup radio_rx_regs_core_tiapd_en_ovr_field tiapd_en_ovr_field + * @brief macros for field tiapd_en_ovr + * @details TIA peak detector enable override + * @{ + */ +#define RADIO_RX_MODE_CTRL__TIAPD_EN_OVR__SHIFT 12 +#define RADIO_RX_MODE_CTRL__TIAPD_EN_OVR__WIDTH 2 +#define RADIO_RX_MODE_CTRL__TIAPD_EN_OVR__MASK 0x00003000U +#define RADIO_RX_MODE_CTRL__TIAPD_EN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00003000U) >> 12) +#define RADIO_RX_MODE_CTRL__TIAPD_EN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00003000U) +#define RADIO_RX_MODE_CTRL__TIAPD_EN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((uint32_t)(src) <<\ + 12) & 0x00003000U) +#define RADIO_RX_MODE_CTRL__TIAPD_EN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00003000U))) +#define RADIO_RX_MODE_CTRL__TIAPD_EN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_pgaI_ovr */ +/** + * @defgroup radio_rx_regs_core_en_pgaI_ovr_field en_pgaI_ovr_field + * @brief macros for field en_pgaI_ovr + * @details Override for I-channel PGA enable + * @{ + */ +#define RADIO_RX_MODE_CTRL__EN_PGAI_OVR__SHIFT 14 +#define RADIO_RX_MODE_CTRL__EN_PGAI_OVR__WIDTH 2 +#define RADIO_RX_MODE_CTRL__EN_PGAI_OVR__MASK 0x0000c000U +#define RADIO_RX_MODE_CTRL__EN_PGAI_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x0000c000U) >> 14) +#define RADIO_RX_MODE_CTRL__EN_PGAI_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0000c000U) +#define RADIO_RX_MODE_CTRL__EN_PGAI_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000c000U) | (((uint32_t)(src) <<\ + 14) & 0x0000c000U) +#define RADIO_RX_MODE_CTRL__EN_PGAI_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0000c000U))) +#define RADIO_RX_MODE_CTRL__EN_PGAI_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_pgaQ_ovr */ +/** + * @defgroup radio_rx_regs_core_en_pgaQ_ovr_field en_pgaQ_ovr_field + * @brief macros for field en_pgaQ_ovr + * @details Override for Q-channel PGA enable + * @{ + */ +#define RADIO_RX_MODE_CTRL__EN_PGAQ_OVR__SHIFT 16 +#define RADIO_RX_MODE_CTRL__EN_PGAQ_OVR__WIDTH 2 +#define RADIO_RX_MODE_CTRL__EN_PGAQ_OVR__MASK 0x00030000U +#define RADIO_RX_MODE_CTRL__EN_PGAQ_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00030000U) >> 16) +#define RADIO_RX_MODE_CTRL__EN_PGAQ_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00030000U) +#define RADIO_RX_MODE_CTRL__EN_PGAQ_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00030000U) | (((uint32_t)(src) <<\ + 16) & 0x00030000U) +#define RADIO_RX_MODE_CTRL__EN_PGAQ_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00030000U))) +#define RADIO_RX_MODE_CTRL__EN_PGAQ_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_osdacI_ovr */ +/** + * @defgroup radio_rx_regs_core_en_osdacI_ovr_field en_osdacI_ovr_field + * @brief macros for field en_osdacI_ovr + * @details Override for I-channel TIA and PGA offset DAC enables + * @{ + */ +#define RADIO_RX_MODE_CTRL__EN_OSDACI_OVR__SHIFT 18 +#define RADIO_RX_MODE_CTRL__EN_OSDACI_OVR__WIDTH 2 +#define RADIO_RX_MODE_CTRL__EN_OSDACI_OVR__MASK 0x000c0000U +#define RADIO_RX_MODE_CTRL__EN_OSDACI_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x000c0000U) >> 18) +#define RADIO_RX_MODE_CTRL__EN_OSDACI_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x000c0000U) +#define RADIO_RX_MODE_CTRL__EN_OSDACI_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000c0000U) | (((uint32_t)(src) <<\ + 18) & 0x000c0000U) +#define RADIO_RX_MODE_CTRL__EN_OSDACI_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x000c0000U))) +#define RADIO_RX_MODE_CTRL__EN_OSDACI_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_osdacQ_ovr */ +/** + * @defgroup radio_rx_regs_core_en_osdacQ_ovr_field en_osdacQ_ovr_field + * @brief macros for field en_osdacQ_ovr + * @details Override for Q-channel TIA and PGA offset DAC enables + * @{ + */ +#define RADIO_RX_MODE_CTRL__EN_OSDACQ_OVR__SHIFT 20 +#define RADIO_RX_MODE_CTRL__EN_OSDACQ_OVR__WIDTH 2 +#define RADIO_RX_MODE_CTRL__EN_OSDACQ_OVR__MASK 0x00300000U +#define RADIO_RX_MODE_CTRL__EN_OSDACQ_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00300000U) >> 20) +#define RADIO_RX_MODE_CTRL__EN_OSDACQ_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00300000U) +#define RADIO_RX_MODE_CTRL__EN_OSDACQ_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00300000U) | (((uint32_t)(src) <<\ + 20) & 0x00300000U) +#define RADIO_RX_MODE_CTRL__EN_OSDACQ_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00300000U))) +#define RADIO_RX_MODE_CTRL__EN_OSDACQ_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adci_en_ovr */ +/** + * @defgroup radio_rx_regs_core_adci_en_ovr_field adci_en_ovr_field + * @brief macros for field adci_en_ovr + * @details ADC I-channel enable override + * @{ + */ +#define RADIO_RX_MODE_CTRL__ADCI_EN_OVR__SHIFT 22 +#define RADIO_RX_MODE_CTRL__ADCI_EN_OVR__WIDTH 2 +#define RADIO_RX_MODE_CTRL__ADCI_EN_OVR__MASK 0x00c00000U +#define RADIO_RX_MODE_CTRL__ADCI_EN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00c00000U) >> 22) +#define RADIO_RX_MODE_CTRL__ADCI_EN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00c00000U) +#define RADIO_RX_MODE_CTRL__ADCI_EN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00c00000U) | (((uint32_t)(src) <<\ + 22) & 0x00c00000U) +#define RADIO_RX_MODE_CTRL__ADCI_EN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00c00000U))) +#define RADIO_RX_MODE_CTRL__ADCI_EN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adcq_en_ovr */ +/** + * @defgroup radio_rx_regs_core_adcq_en_ovr_field adcq_en_ovr_field + * @brief macros for field adcq_en_ovr + * @details ADC Q-channel enable override + * @{ + */ +#define RADIO_RX_MODE_CTRL__ADCQ_EN_OVR__SHIFT 24 +#define RADIO_RX_MODE_CTRL__ADCQ_EN_OVR__WIDTH 2 +#define RADIO_RX_MODE_CTRL__ADCQ_EN_OVR__MASK 0x03000000U +#define RADIO_RX_MODE_CTRL__ADCQ_EN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x03000000U) >> 24) +#define RADIO_RX_MODE_CTRL__ADCQ_EN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x03000000U) +#define RADIO_RX_MODE_CTRL__ADCQ_EN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((uint32_t)(src) <<\ + 24) & 0x03000000U) +#define RADIO_RX_MODE_CTRL__ADCQ_EN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x03000000U))) +#define RADIO_RX_MODE_CTRL__ADCQ_EN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adcref_en_ovr */ +/** + * @defgroup radio_rx_regs_core_adcref_en_ovr_field adcref_en_ovr_field + * @brief macros for field adcref_en_ovr + * @details ADC reference enable override + * @{ + */ +#define RADIO_RX_MODE_CTRL__ADCREF_EN_OVR__SHIFT 26 +#define RADIO_RX_MODE_CTRL__ADCREF_EN_OVR__WIDTH 2 +#define RADIO_RX_MODE_CTRL__ADCREF_EN_OVR__MASK 0x0c000000U +#define RADIO_RX_MODE_CTRL__ADCREF_EN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x0c000000U) >> 26) +#define RADIO_RX_MODE_CTRL__ADCREF_EN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x0c000000U) +#define RADIO_RX_MODE_CTRL__ADCREF_EN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((uint32_t)(src) <<\ + 26) & 0x0c000000U) +#define RADIO_RX_MODE_CTRL__ADCREF_EN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x0c000000U))) +#define RADIO_RX_MODE_CTRL__ADCREF_EN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adc_rstb_ovr */ +/** + * @defgroup radio_rx_regs_core_adc_rstb_ovr_field adc_rstb_ovr_field + * @brief macros for field adc_rstb_ovr + * @details ADC reset_b override + * @{ + */ +#define RADIO_RX_MODE_CTRL__ADC_RSTB_OVR__SHIFT 28 +#define RADIO_RX_MODE_CTRL__ADC_RSTB_OVR__WIDTH 2 +#define RADIO_RX_MODE_CTRL__ADC_RSTB_OVR__MASK 0x30000000U +#define RADIO_RX_MODE_CTRL__ADC_RSTB_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x30000000U) >> 28) +#define RADIO_RX_MODE_CTRL__ADC_RSTB_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x30000000U) +#define RADIO_RX_MODE_CTRL__ADC_RSTB_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x30000000U) | (((uint32_t)(src) <<\ + 28) & 0x30000000U) +#define RADIO_RX_MODE_CTRL__ADC_RSTB_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x30000000U))) +#define RADIO_RX_MODE_CTRL__ADC_RSTB_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rxbias_en_ovr */ +/** + * @defgroup radio_rx_regs_core_rxbias_en_ovr_field rxbias_en_ovr_field + * @brief macros for field rxbias_en_ovr + * @details RX bias enable override + * @{ + */ +#define RADIO_RX_MODE_CTRL__RXBIAS_EN_OVR__SHIFT 30 +#define RADIO_RX_MODE_CTRL__RXBIAS_EN_OVR__WIDTH 2 +#define RADIO_RX_MODE_CTRL__RXBIAS_EN_OVR__MASK 0xc0000000U +#define RADIO_RX_MODE_CTRL__RXBIAS_EN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define RADIO_RX_MODE_CTRL__RXBIAS_EN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define RADIO_RX_MODE_CTRL__RXBIAS_EN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define RADIO_RX_MODE_CTRL__RXBIAS_EN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define RADIO_RX_MODE_CTRL__RXBIAS_EN_OVR__RESET_VALUE 0x00000000U +/** @} */ +#define RADIO_RX_MODE_CTRL__TYPE uint32_t +#define RADIO_RX_MODE_CTRL__READ 0xffffffffU +#define RADIO_RX_MODE_CTRL__WRITE 0xffffffffU +#define RADIO_RX_MODE_CTRL__PRESERVED 0x00000000U +#define RADIO_RX_MODE_CTRL__RESET_VALUE 0x00000000U + +#endif /* __RADIO_RX_MODE_CTRL_MACRO__ */ + +/** @} end of mode_ctrl */ + +/* macros for BlueprintGlobalNameSpace::radio_rx_mode_ctrl2 */ +/** + * @defgroup radio_rx_regs_core_mode_ctrl2 mode_ctrl2 + * @brief Enable and mode overrides definitions. + * @{ + */ +#ifndef __RADIO_RX_MODE_CTRL2_MACRO__ +#define __RADIO_RX_MODE_CTRL2_MACRO__ + +/* macros for field mode1M_ovr */ +/** + * @defgroup radio_rx_regs_core_mode1M_ovr_field mode1M_ovr_field + * @brief macros for field mode1M_ovr + * @details mode 1M override + * @{ + */ +#define RADIO_RX_MODE_CTRL2__MODE1M_OVR__SHIFT 0 +#define RADIO_RX_MODE_CTRL2__MODE1M_OVR__WIDTH 2 +#define RADIO_RX_MODE_CTRL2__MODE1M_OVR__MASK 0x00000003U +#define RADIO_RX_MODE_CTRL2__MODE1M_OVR__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define RADIO_RX_MODE_CTRL2__MODE1M_OVR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define RADIO_RX_MODE_CTRL2__MODE1M_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define RADIO_RX_MODE_CTRL2__MODE1M_OVR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define RADIO_RX_MODE_CTRL2__MODE1M_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field swapIQ */ +/** + * @defgroup radio_rx_regs_core_swapIQ_field swapIQ_field + * @brief macros for field swapIQ + * @details mixer control bit to swap I and Q + * @{ + */ +#define RADIO_RX_MODE_CTRL2__SWAPIQ__SHIFT 2 +#define RADIO_RX_MODE_CTRL2__SWAPIQ__WIDTH 1 +#define RADIO_RX_MODE_CTRL2__SWAPIQ__MASK 0x00000004U +#define RADIO_RX_MODE_CTRL2__SWAPIQ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define RADIO_RX_MODE_CTRL2__SWAPIQ__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define RADIO_RX_MODE_CTRL2__SWAPIQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define RADIO_RX_MODE_CTRL2__SWAPIQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define RADIO_RX_MODE_CTRL2__SWAPIQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define RADIO_RX_MODE_CTRL2__SWAPIQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define RADIO_RX_MODE_CTRL2__SWAPIQ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field combineIQ */ +/** + * @defgroup radio_rx_regs_core_combineIQ_field combineIQ_field + * @brief macros for field combineIQ + * @details mixer control bit to combineIQ + * @{ + */ +#define RADIO_RX_MODE_CTRL2__COMBINEIQ__SHIFT 3 +#define RADIO_RX_MODE_CTRL2__COMBINEIQ__WIDTH 1 +#define RADIO_RX_MODE_CTRL2__COMBINEIQ__MASK 0x00000008U +#define RADIO_RX_MODE_CTRL2__COMBINEIQ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define RADIO_RX_MODE_CTRL2__COMBINEIQ__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define RADIO_RX_MODE_CTRL2__COMBINEIQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define RADIO_RX_MODE_CTRL2__COMBINEIQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define RADIO_RX_MODE_CTRL2__COMBINEIQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define RADIO_RX_MODE_CTRL2__COMBINEIQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define RADIO_RX_MODE_CTRL2__COMBINEIQ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mixer_ensinglelp_ovr_val */ +/** + * @defgroup radio_rx_regs_core_mixer_ensinglelp_ovr_val_field mixer_ensinglelp_ovr_val_field + * @brief macros for field mixer_ensinglelp_ovr_val + * @details override value for ensinglelp + * @{ + */ +#define RADIO_RX_MODE_CTRL2__MIXER_ENSINGLELP_OVR_VAL__SHIFT 4 +#define RADIO_RX_MODE_CTRL2__MIXER_ENSINGLELP_OVR_VAL__WIDTH 1 +#define RADIO_RX_MODE_CTRL2__MIXER_ENSINGLELP_OVR_VAL__MASK 0x00000010U +#define RADIO_RX_MODE_CTRL2__MIXER_ENSINGLELP_OVR_VAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define RADIO_RX_MODE_CTRL2__MIXER_ENSINGLELP_OVR_VAL__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define RADIO_RX_MODE_CTRL2__MIXER_ENSINGLELP_OVR_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define RADIO_RX_MODE_CTRL2__MIXER_ENSINGLELP_OVR_VAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define RADIO_RX_MODE_CTRL2__MIXER_ENSINGLELP_OVR_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define RADIO_RX_MODE_CTRL2__MIXER_ENSINGLELP_OVR_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define RADIO_RX_MODE_CTRL2__MIXER_ENSINGLELP_OVR_VAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field lna_offGain */ +/** + * @defgroup radio_rx_regs_core_lna_offGain_field lna_offGain_field + * @brief macros for field lna_offGain + * @details change the gain of lna + * @{ + */ +#define RADIO_RX_MODE_CTRL2__LNA_OFFGAIN__SHIFT 5 +#define RADIO_RX_MODE_CTRL2__LNA_OFFGAIN__WIDTH 1 +#define RADIO_RX_MODE_CTRL2__LNA_OFFGAIN__MASK 0x00000020U +#define RADIO_RX_MODE_CTRL2__LNA_OFFGAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define RADIO_RX_MODE_CTRL2__LNA_OFFGAIN__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define RADIO_RX_MODE_CTRL2__LNA_OFFGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define RADIO_RX_MODE_CTRL2__LNA_OFFGAIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define RADIO_RX_MODE_CTRL2__LNA_OFFGAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define RADIO_RX_MODE_CTRL2__LNA_OFFGAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define RADIO_RX_MODE_CTRL2__LNA_OFFGAIN__RESET_VALUE 0x00000000U +/** @} */ +#define RADIO_RX_MODE_CTRL2__TYPE uint32_t +#define RADIO_RX_MODE_CTRL2__READ 0x0000003fU +#define RADIO_RX_MODE_CTRL2__WRITE 0x0000003fU +#define RADIO_RX_MODE_CTRL2__PRESERVED 0x00000000U +#define RADIO_RX_MODE_CTRL2__RESET_VALUE 0x00000000U + +#endif /* __RADIO_RX_MODE_CTRL2_MACRO__ */ + +/** @} end of mode_ctrl2 */ + +/* macros for BlueprintGlobalNameSpace::radio_rx_cal_cfg */ +/** + * @defgroup radio_rx_regs_core_cal_cfg cal_cfg + * @brief Calibration configurations definitions. + * @{ + */ +#ifndef __RADIO_RX_CAL_CFG_MACRO__ +#define __RADIO_RX_CAL_CFG_MACRO__ + +/* macros for field caldc_lna_en */ +/** + * @defgroup radio_rx_regs_core_caldc_lna_en_field caldc_lna_en_field + * @brief macros for field caldc_lna_en + * @details LNA enable during DC offset calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALDC_LNA_EN__SHIFT 0 +#define RADIO_RX_CAL_CFG__CALDC_LNA_EN__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALDC_LNA_EN__MASK 0x00000001U +#define RADIO_RX_CAL_CFG__CALDC_LNA_EN__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RADIO_RX_CAL_CFG__CALDC_LNA_EN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RADIO_RX_CAL_CFG__CALDC_LNA_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define RADIO_RX_CAL_CFG__CALDC_LNA_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define RADIO_RX_CAL_CFG__CALDC_LNA_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define RADIO_RX_CAL_CFG__CALDC_LNA_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define RADIO_RX_CAL_CFG__CALDC_LNA_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field caldc_mix_en */ +/** + * @defgroup radio_rx_regs_core_caldc_mix_en_field caldc_mix_en_field + * @brief macros for field caldc_mix_en + * @details Mixer enable during DC offset calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALDC_MIX_EN__SHIFT 1 +#define RADIO_RX_CAL_CFG__CALDC_MIX_EN__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALDC_MIX_EN__MASK 0x00000002U +#define RADIO_RX_CAL_CFG__CALDC_MIX_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define RADIO_RX_CAL_CFG__CALDC_MIX_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define RADIO_RX_CAL_CFG__CALDC_MIX_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define RADIO_RX_CAL_CFG__CALDC_MIX_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define RADIO_RX_CAL_CFG__CALDC_MIX_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define RADIO_RX_CAL_CFG__CALDC_MIX_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define RADIO_RX_CAL_CFG__CALDC_MIX_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field caldc_tia_en */ +/** + * @defgroup radio_rx_regs_core_caldc_tia_en_field caldc_tia_en_field + * @brief macros for field caldc_tia_en + * @details TIA enable during DC offset calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALDC_TIA_EN__SHIFT 2 +#define RADIO_RX_CAL_CFG__CALDC_TIA_EN__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALDC_TIA_EN__MASK 0x00000004U +#define RADIO_RX_CAL_CFG__CALDC_TIA_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define RADIO_RX_CAL_CFG__CALDC_TIA_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define RADIO_RX_CAL_CFG__CALDC_TIA_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define RADIO_RX_CAL_CFG__CALDC_TIA_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define RADIO_RX_CAL_CFG__CALDC_TIA_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define RADIO_RX_CAL_CFG__CALDC_TIA_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define RADIO_RX_CAL_CFG__CALDC_TIA_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field caldc_tia_open_rcc */ +/** + * @defgroup radio_rx_regs_core_caldc_tia_open_rcc_field caldc_tia_open_rcc_field + * @brief macros for field caldc_tia_open_rcc + * @details Disconnect cross-coupling resistors around TIA during DC offset calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALDC_TIA_OPEN_RCC__SHIFT 3 +#define RADIO_RX_CAL_CFG__CALDC_TIA_OPEN_RCC__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALDC_TIA_OPEN_RCC__MASK 0x00000008U +#define RADIO_RX_CAL_CFG__CALDC_TIA_OPEN_RCC__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define RADIO_RX_CAL_CFG__CALDC_TIA_OPEN_RCC__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define RADIO_RX_CAL_CFG__CALDC_TIA_OPEN_RCC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define RADIO_RX_CAL_CFG__CALDC_TIA_OPEN_RCC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define RADIO_RX_CAL_CFG__CALDC_TIA_OPEN_RCC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define RADIO_RX_CAL_CFG__CALDC_TIA_OPEN_RCC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define RADIO_RX_CAL_CFG__CALDC_TIA_OPEN_RCC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field caldc_tia_open_rfb */ +/** + * @defgroup radio_rx_regs_core_caldc_tia_open_rfb_field caldc_tia_open_rfb_field + * @brief macros for field caldc_tia_open_rfb + * @details Disconnect feedback resistor around TIA during DC offset calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALDC_TIA_OPEN_RFB__SHIFT 4 +#define RADIO_RX_CAL_CFG__CALDC_TIA_OPEN_RFB__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALDC_TIA_OPEN_RFB__MASK 0x00000010U +#define RADIO_RX_CAL_CFG__CALDC_TIA_OPEN_RFB__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define RADIO_RX_CAL_CFG__CALDC_TIA_OPEN_RFB__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define RADIO_RX_CAL_CFG__CALDC_TIA_OPEN_RFB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define RADIO_RX_CAL_CFG__CALDC_TIA_OPEN_RFB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define RADIO_RX_CAL_CFG__CALDC_TIA_OPEN_RFB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define RADIO_RX_CAL_CFG__CALDC_TIA_OPEN_RFB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define RADIO_RX_CAL_CFG__CALDC_TIA_OPEN_RFB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field caldc_pga_en */ +/** + * @defgroup radio_rx_regs_core_caldc_pga_en_field caldc_pga_en_field + * @brief macros for field caldc_pga_en + * @details PGA enable during DC offset calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALDC_PGA_EN__SHIFT 5 +#define RADIO_RX_CAL_CFG__CALDC_PGA_EN__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALDC_PGA_EN__MASK 0x00000020U +#define RADIO_RX_CAL_CFG__CALDC_PGA_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define RADIO_RX_CAL_CFG__CALDC_PGA_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define RADIO_RX_CAL_CFG__CALDC_PGA_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define RADIO_RX_CAL_CFG__CALDC_PGA_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define RADIO_RX_CAL_CFG__CALDC_PGA_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define RADIO_RX_CAL_CFG__CALDC_PGA_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define RADIO_RX_CAL_CFG__CALDC_PGA_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field caldc_pga_open_rcc */ +/** + * @defgroup radio_rx_regs_core_caldc_pga_open_rcc_field caldc_pga_open_rcc_field + * @brief macros for field caldc_pga_open_rcc + * @details Disconnect cross-coupling resistors around PGA during DC offset calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALDC_PGA_OPEN_RCC__SHIFT 6 +#define RADIO_RX_CAL_CFG__CALDC_PGA_OPEN_RCC__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALDC_PGA_OPEN_RCC__MASK 0x00000040U +#define RADIO_RX_CAL_CFG__CALDC_PGA_OPEN_RCC__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define RADIO_RX_CAL_CFG__CALDC_PGA_OPEN_RCC__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define RADIO_RX_CAL_CFG__CALDC_PGA_OPEN_RCC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define RADIO_RX_CAL_CFG__CALDC_PGA_OPEN_RCC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define RADIO_RX_CAL_CFG__CALDC_PGA_OPEN_RCC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define RADIO_RX_CAL_CFG__CALDC_PGA_OPEN_RCC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define RADIO_RX_CAL_CFG__CALDC_PGA_OPEN_RCC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field caldc_pga_open_rfb */ +/** + * @defgroup radio_rx_regs_core_caldc_pga_open_rfb_field caldc_pga_open_rfb_field + * @brief macros for field caldc_pga_open_rfb + * @details Disconnect feedback resistor around PGA during DC offset calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALDC_PGA_OPEN_RFB__SHIFT 7 +#define RADIO_RX_CAL_CFG__CALDC_PGA_OPEN_RFB__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALDC_PGA_OPEN_RFB__MASK 0x00000080U +#define RADIO_RX_CAL_CFG__CALDC_PGA_OPEN_RFB__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define RADIO_RX_CAL_CFG__CALDC_PGA_OPEN_RFB__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define RADIO_RX_CAL_CFG__CALDC_PGA_OPEN_RFB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define RADIO_RX_CAL_CFG__CALDC_PGA_OPEN_RFB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define RADIO_RX_CAL_CFG__CALDC_PGA_OPEN_RFB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define RADIO_RX_CAL_CFG__CALDC_PGA_OPEN_RFB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define RADIO_RX_CAL_CFG__CALDC_PGA_OPEN_RFB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field caldc_adc_en */ +/** + * @defgroup radio_rx_regs_core_caldc_adc_en_field caldc_adc_en_field + * @brief macros for field caldc_adc_en + * @details ADC enable during DC offset calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALDC_ADC_EN__SHIFT 8 +#define RADIO_RX_CAL_CFG__CALDC_ADC_EN__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALDC_ADC_EN__MASK 0x00000100U +#define RADIO_RX_CAL_CFG__CALDC_ADC_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define RADIO_RX_CAL_CFG__CALDC_ADC_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define RADIO_RX_CAL_CFG__CALDC_ADC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define RADIO_RX_CAL_CFG__CALDC_ADC_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define RADIO_RX_CAL_CFG__CALDC_ADC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define RADIO_RX_CAL_CFG__CALDC_ADC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define RADIO_RX_CAL_CFG__CALDC_ADC_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pga_dcos_cal_ovr */ +/** + * @defgroup radio_rx_regs_core_pga_dcos_cal_ovr_field pga_dcos_cal_ovr_field + * @brief macros for field pga_dcos_cal_ovr + * @details Override to connect pga n and p inputs to each other + * @{ + */ +#define RADIO_RX_CAL_CFG__PGA_DCOS_CAL_OVR__SHIFT 9 +#define RADIO_RX_CAL_CFG__PGA_DCOS_CAL_OVR__WIDTH 2 +#define RADIO_RX_CAL_CFG__PGA_DCOS_CAL_OVR__MASK 0x00000600U +#define RADIO_RX_CAL_CFG__PGA_DCOS_CAL_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000600U) >> 9) +#define RADIO_RX_CAL_CFG__PGA_DCOS_CAL_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000600U) +#define RADIO_RX_CAL_CFG__PGA_DCOS_CAL_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000600U) | (((uint32_t)(src) <<\ + 9) & 0x00000600U) +#define RADIO_RX_CAL_CFG__PGA_DCOS_CAL_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000600U))) +#define RADIO_RX_CAL_CFG__PGA_DCOS_CAL_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field calfc_lna_en */ +/** + * @defgroup radio_rx_regs_core_calfc_lna_en_field calfc_lna_en_field + * @brief macros for field calfc_lna_en + * @details LNA enable during RXBB filter calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALFC_LNA_EN__SHIFT 11 +#define RADIO_RX_CAL_CFG__CALFC_LNA_EN__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALFC_LNA_EN__MASK 0x00000800U +#define RADIO_RX_CAL_CFG__CALFC_LNA_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define RADIO_RX_CAL_CFG__CALFC_LNA_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define RADIO_RX_CAL_CFG__CALFC_LNA_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define RADIO_RX_CAL_CFG__CALFC_LNA_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define RADIO_RX_CAL_CFG__CALFC_LNA_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define RADIO_RX_CAL_CFG__CALFC_LNA_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define RADIO_RX_CAL_CFG__CALFC_LNA_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field calfc_mix_en */ +/** + * @defgroup radio_rx_regs_core_calfc_mix_en_field calfc_mix_en_field + * @brief macros for field calfc_mix_en + * @details Mixer enable during RXBB filter calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALFC_MIX_EN__SHIFT 12 +#define RADIO_RX_CAL_CFG__CALFC_MIX_EN__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALFC_MIX_EN__MASK 0x00001000U +#define RADIO_RX_CAL_CFG__CALFC_MIX_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define RADIO_RX_CAL_CFG__CALFC_MIX_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define RADIO_RX_CAL_CFG__CALFC_MIX_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define RADIO_RX_CAL_CFG__CALFC_MIX_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define RADIO_RX_CAL_CFG__CALFC_MIX_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define RADIO_RX_CAL_CFG__CALFC_MIX_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define RADIO_RX_CAL_CFG__CALFC_MIX_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field calfc_tia_open_rcc */ +/** + * @defgroup radio_rx_regs_core_calfc_tia_open_rcc_field calfc_tia_open_rcc_field + * @brief macros for field calfc_tia_open_rcc + * @details Disconnect cross-coupling resistors around TIA during RXBB filter calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALFC_TIA_OPEN_RCC__SHIFT 13 +#define RADIO_RX_CAL_CFG__CALFC_TIA_OPEN_RCC__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALFC_TIA_OPEN_RCC__MASK 0x00002000U +#define RADIO_RX_CAL_CFG__CALFC_TIA_OPEN_RCC__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define RADIO_RX_CAL_CFG__CALFC_TIA_OPEN_RCC__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define RADIO_RX_CAL_CFG__CALFC_TIA_OPEN_RCC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define RADIO_RX_CAL_CFG__CALFC_TIA_OPEN_RCC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define RADIO_RX_CAL_CFG__CALFC_TIA_OPEN_RCC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define RADIO_RX_CAL_CFG__CALFC_TIA_OPEN_RCC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define RADIO_RX_CAL_CFG__CALFC_TIA_OPEN_RCC__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field calfc_tia_open_rfb */ +/** + * @defgroup radio_rx_regs_core_calfc_tia_open_rfb_field calfc_tia_open_rfb_field + * @brief macros for field calfc_tia_open_rfb + * @details Disconnect feedback resistors around TIA during RXBB filter calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALFC_TIA_OPEN_RFB__SHIFT 14 +#define RADIO_RX_CAL_CFG__CALFC_TIA_OPEN_RFB__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALFC_TIA_OPEN_RFB__MASK 0x00004000U +#define RADIO_RX_CAL_CFG__CALFC_TIA_OPEN_RFB__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define RADIO_RX_CAL_CFG__CALFC_TIA_OPEN_RFB__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define RADIO_RX_CAL_CFG__CALFC_TIA_OPEN_RFB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define RADIO_RX_CAL_CFG__CALFC_TIA_OPEN_RFB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define RADIO_RX_CAL_CFG__CALFC_TIA_OPEN_RFB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define RADIO_RX_CAL_CFG__CALFC_TIA_OPEN_RFB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define RADIO_RX_CAL_CFG__CALFC_TIA_OPEN_RFB__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field calfc_pga_open_rcc */ +/** + * @defgroup radio_rx_regs_core_calfc_pga_open_rcc_field calfc_pga_open_rcc_field + * @brief macros for field calfc_pga_open_rcc + * @details Disconnect cross-coupling resistors around PGA during RXBB filter calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALFC_PGA_OPEN_RCC__SHIFT 15 +#define RADIO_RX_CAL_CFG__CALFC_PGA_OPEN_RCC__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALFC_PGA_OPEN_RCC__MASK 0x00008000U +#define RADIO_RX_CAL_CFG__CALFC_PGA_OPEN_RCC__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define RADIO_RX_CAL_CFG__CALFC_PGA_OPEN_RCC__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define RADIO_RX_CAL_CFG__CALFC_PGA_OPEN_RCC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define RADIO_RX_CAL_CFG__CALFC_PGA_OPEN_RCC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define RADIO_RX_CAL_CFG__CALFC_PGA_OPEN_RCC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define RADIO_RX_CAL_CFG__CALFC_PGA_OPEN_RCC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define RADIO_RX_CAL_CFG__CALFC_PGA_OPEN_RCC__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field calfc_pga_open_rfb */ +/** + * @defgroup radio_rx_regs_core_calfc_pga_open_rfb_field calfc_pga_open_rfb_field + * @brief macros for field calfc_pga_open_rfb + * @details Disconnect feedback resistors around PGA during RXBB filter calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALFC_PGA_OPEN_RFB__SHIFT 16 +#define RADIO_RX_CAL_CFG__CALFC_PGA_OPEN_RFB__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALFC_PGA_OPEN_RFB__MASK 0x00010000U +#define RADIO_RX_CAL_CFG__CALFC_PGA_OPEN_RFB__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define RADIO_RX_CAL_CFG__CALFC_PGA_OPEN_RFB__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define RADIO_RX_CAL_CFG__CALFC_PGA_OPEN_RFB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define RADIO_RX_CAL_CFG__CALFC_PGA_OPEN_RFB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define RADIO_RX_CAL_CFG__CALFC_PGA_OPEN_RFB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define RADIO_RX_CAL_CFG__CALFC_PGA_OPEN_RFB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define RADIO_RX_CAL_CFG__CALFC_PGA_OPEN_RFB__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field calfc_pga_connectrcc2rfb */ +/** + * @defgroup radio_rx_regs_core_calfc_pga_connectrcc2rfb_field calfc_pga_connectrcc2rfb_field + * @brief macros for field calfc_pga_connectrcc2rfb + * @details PGA connect rcc to rfb during RXBB filter calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALFC_PGA_CONNECTRCC2RFB__SHIFT 17 +#define RADIO_RX_CAL_CFG__CALFC_PGA_CONNECTRCC2RFB__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALFC_PGA_CONNECTRCC2RFB__MASK 0x00020000U +#define RADIO_RX_CAL_CFG__CALFC_PGA_CONNECTRCC2RFB__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define RADIO_RX_CAL_CFG__CALFC_PGA_CONNECTRCC2RFB__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define RADIO_RX_CAL_CFG__CALFC_PGA_CONNECTRCC2RFB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define RADIO_RX_CAL_CFG__CALFC_PGA_CONNECTRCC2RFB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define RADIO_RX_CAL_CFG__CALFC_PGA_CONNECTRCC2RFB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define RADIO_RX_CAL_CFG__CALFC_PGA_CONNECTRCC2RFB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define RADIO_RX_CAL_CFG__CALFC_PGA_CONNECTRCC2RFB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field calfc_pga_op_cal */ +/** + * @defgroup radio_rx_regs_core_calfc_pga_op_cal_field calfc_pga_op_cal_field + * @brief macros for field calfc_pga_op_cal + * @details enable pga opamp calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALFC_PGA_OP_CAL__SHIFT 18 +#define RADIO_RX_CAL_CFG__CALFC_PGA_OP_CAL__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALFC_PGA_OP_CAL__MASK 0x00040000U +#define RADIO_RX_CAL_CFG__CALFC_PGA_OP_CAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define RADIO_RX_CAL_CFG__CALFC_PGA_OP_CAL__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define RADIO_RX_CAL_CFG__CALFC_PGA_OP_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define RADIO_RX_CAL_CFG__CALFC_PGA_OP_CAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define RADIO_RX_CAL_CFG__CALFC_PGA_OP_CAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define RADIO_RX_CAL_CFG__CALFC_PGA_OP_CAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define RADIO_RX_CAL_CFG__CALFC_PGA_OP_CAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field calfc_init_osc */ +/** + * @defgroup radio_rx_regs_core_calfc_init_osc_field calfc_init_osc_field + * @brief macros for field calfc_init_osc + * @details initialize loop nodes for osc during RXBB calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALFC_INIT_OSC__SHIFT 19 +#define RADIO_RX_CAL_CFG__CALFC_INIT_OSC__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALFC_INIT_OSC__MASK 0x00080000U +#define RADIO_RX_CAL_CFG__CALFC_INIT_OSC__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define RADIO_RX_CAL_CFG__CALFC_INIT_OSC__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define RADIO_RX_CAL_CFG__CALFC_INIT_OSC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define RADIO_RX_CAL_CFG__CALFC_INIT_OSC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define RADIO_RX_CAL_CFG__CALFC_INIT_OSC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define RADIO_RX_CAL_CFG__CALFC_INIT_OSC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define RADIO_RX_CAL_CFG__CALFC_INIT_OSC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field calfc_start_osc */ +/** + * @defgroup radio_rx_regs_core_calfc_start_osc_field calfc_start_osc_field + * @brief macros for field calfc_start_osc + * @details start osc during RXBB calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALFC_START_OSC__SHIFT 20 +#define RADIO_RX_CAL_CFG__CALFC_START_OSC__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALFC_START_OSC__MASK 0x00100000U +#define RADIO_RX_CAL_CFG__CALFC_START_OSC__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define RADIO_RX_CAL_CFG__CALFC_START_OSC__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define RADIO_RX_CAL_CFG__CALFC_START_OSC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define RADIO_RX_CAL_CFG__CALFC_START_OSC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define RADIO_RX_CAL_CFG__CALFC_START_OSC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define RADIO_RX_CAL_CFG__CALFC_START_OSC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define RADIO_RX_CAL_CFG__CALFC_START_OSC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field calfc_adc_en */ +/** + * @defgroup radio_rx_regs_core_calfc_adc_en_field calfc_adc_en_field + * @brief macros for field calfc_adc_en + * @details ADC enable during RXBB filter calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALFC_ADC_EN__SHIFT 21 +#define RADIO_RX_CAL_CFG__CALFC_ADC_EN__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALFC_ADC_EN__MASK 0x00200000U +#define RADIO_RX_CAL_CFG__CALFC_ADC_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define RADIO_RX_CAL_CFG__CALFC_ADC_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define RADIO_RX_CAL_CFG__CALFC_ADC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define RADIO_RX_CAL_CFG__CALFC_ADC_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define RADIO_RX_CAL_CFG__CALFC_ADC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define RADIO_RX_CAL_CFG__CALFC_ADC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define RADIO_RX_CAL_CFG__CALFC_ADC_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field calfc_notch_en */ +/** + * @defgroup radio_rx_regs_core_calfc_notch_en_field calfc_notch_en_field + * @brief macros for field calfc_notch_en + * @details enable notch calibration + * @{ + */ +#define RADIO_RX_CAL_CFG__CALFC_NOTCH_EN__SHIFT 22 +#define RADIO_RX_CAL_CFG__CALFC_NOTCH_EN__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALFC_NOTCH_EN__MASK 0x00400000U +#define RADIO_RX_CAL_CFG__CALFC_NOTCH_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define RADIO_RX_CAL_CFG__CALFC_NOTCH_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define RADIO_RX_CAL_CFG__CALFC_NOTCH_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define RADIO_RX_CAL_CFG__CALFC_NOTCH_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define RADIO_RX_CAL_CFG__CALFC_NOTCH_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define RADIO_RX_CAL_CFG__CALFC_NOTCH_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define RADIO_RX_CAL_CFG__CALFC_NOTCH_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field calrx_lna_en */ +/** + * @defgroup radio_rx_regs_core_calrx_lna_en_field calrx_lna_en_field + * @brief macros for field calrx_lna_en + * @details LNA enable during RX loopback calibration (reserved) + * @{ + */ +#define RADIO_RX_CAL_CFG__CALRX_LNA_EN__SHIFT 23 +#define RADIO_RX_CAL_CFG__CALRX_LNA_EN__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALRX_LNA_EN__MASK 0x00800000U +#define RADIO_RX_CAL_CFG__CALRX_LNA_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define RADIO_RX_CAL_CFG__CALRX_LNA_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define RADIO_RX_CAL_CFG__CALRX_LNA_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define RADIO_RX_CAL_CFG__CALRX_LNA_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define RADIO_RX_CAL_CFG__CALRX_LNA_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define RADIO_RX_CAL_CFG__CALRX_LNA_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define RADIO_RX_CAL_CFG__CALRX_LNA_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field calrx_mix_en */ +/** + * @defgroup radio_rx_regs_core_calrx_mix_en_field calrx_mix_en_field + * @brief macros for field calrx_mix_en + * @details Mixer enable during RX loopback calibration (reserved) + * @{ + */ +#define RADIO_RX_CAL_CFG__CALRX_MIX_EN__SHIFT 24 +#define RADIO_RX_CAL_CFG__CALRX_MIX_EN__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALRX_MIX_EN__MASK 0x01000000U +#define RADIO_RX_CAL_CFG__CALRX_MIX_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define RADIO_RX_CAL_CFG__CALRX_MIX_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define RADIO_RX_CAL_CFG__CALRX_MIX_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define RADIO_RX_CAL_CFG__CALRX_MIX_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define RADIO_RX_CAL_CFG__CALRX_MIX_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define RADIO_RX_CAL_CFG__CALRX_MIX_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define RADIO_RX_CAL_CFG__CALRX_MIX_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field calrx_tia_en */ +/** + * @defgroup radio_rx_regs_core_calrx_tia_en_field calrx_tia_en_field + * @brief macros for field calrx_tia_en + * @details TIA enable during RX loopback calibration (reserved) + * @{ + */ +#define RADIO_RX_CAL_CFG__CALRX_TIA_EN__SHIFT 25 +#define RADIO_RX_CAL_CFG__CALRX_TIA_EN__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALRX_TIA_EN__MASK 0x02000000U +#define RADIO_RX_CAL_CFG__CALRX_TIA_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define RADIO_RX_CAL_CFG__CALRX_TIA_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define RADIO_RX_CAL_CFG__CALRX_TIA_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define RADIO_RX_CAL_CFG__CALRX_TIA_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define RADIO_RX_CAL_CFG__CALRX_TIA_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define RADIO_RX_CAL_CFG__CALRX_TIA_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define RADIO_RX_CAL_CFG__CALRX_TIA_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field calrx_tia_open_rcc */ +/** + * @defgroup radio_rx_regs_core_calrx_tia_open_rcc_field calrx_tia_open_rcc_field + * @brief macros for field calrx_tia_open_rcc + * @details Disconnect cross-coupling resistors around TIA during RX loopback calibration (reserved) + * @{ + */ +#define RADIO_RX_CAL_CFG__CALRX_TIA_OPEN_RCC__SHIFT 26 +#define RADIO_RX_CAL_CFG__CALRX_TIA_OPEN_RCC__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALRX_TIA_OPEN_RCC__MASK 0x04000000U +#define RADIO_RX_CAL_CFG__CALRX_TIA_OPEN_RCC__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define RADIO_RX_CAL_CFG__CALRX_TIA_OPEN_RCC__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define RADIO_RX_CAL_CFG__CALRX_TIA_OPEN_RCC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define RADIO_RX_CAL_CFG__CALRX_TIA_OPEN_RCC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define RADIO_RX_CAL_CFG__CALRX_TIA_OPEN_RCC__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define RADIO_RX_CAL_CFG__CALRX_TIA_OPEN_RCC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define RADIO_RX_CAL_CFG__CALRX_TIA_OPEN_RCC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field calrx_tia_open_rfb */ +/** + * @defgroup radio_rx_regs_core_calrx_tia_open_rfb_field calrx_tia_open_rfb_field + * @brief macros for field calrx_tia_open_rfb + * @details Disconnect feedback resistors around TIA during RX loopback calibration (reserved) + * @{ + */ +#define RADIO_RX_CAL_CFG__CALRX_TIA_OPEN_RFB__SHIFT 27 +#define RADIO_RX_CAL_CFG__CALRX_TIA_OPEN_RFB__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALRX_TIA_OPEN_RFB__MASK 0x08000000U +#define RADIO_RX_CAL_CFG__CALRX_TIA_OPEN_RFB__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define RADIO_RX_CAL_CFG__CALRX_TIA_OPEN_RFB__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define RADIO_RX_CAL_CFG__CALRX_TIA_OPEN_RFB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define RADIO_RX_CAL_CFG__CALRX_TIA_OPEN_RFB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define RADIO_RX_CAL_CFG__CALRX_TIA_OPEN_RFB__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define RADIO_RX_CAL_CFG__CALRX_TIA_OPEN_RFB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define RADIO_RX_CAL_CFG__CALRX_TIA_OPEN_RFB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field calrx_pga_en */ +/** + * @defgroup radio_rx_regs_core_calrx_pga_en_field calrx_pga_en_field + * @brief macros for field calrx_pga_en + * @details PGA enable during RX loopback calibration (reserved) + * @{ + */ +#define RADIO_RX_CAL_CFG__CALRX_PGA_EN__SHIFT 28 +#define RADIO_RX_CAL_CFG__CALRX_PGA_EN__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALRX_PGA_EN__MASK 0x10000000U +#define RADIO_RX_CAL_CFG__CALRX_PGA_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define RADIO_RX_CAL_CFG__CALRX_PGA_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define RADIO_RX_CAL_CFG__CALRX_PGA_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define RADIO_RX_CAL_CFG__CALRX_PGA_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define RADIO_RX_CAL_CFG__CALRX_PGA_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define RADIO_RX_CAL_CFG__CALRX_PGA_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define RADIO_RX_CAL_CFG__CALRX_PGA_EN__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field calrx_pga_open_rcc */ +/** + * @defgroup radio_rx_regs_core_calrx_pga_open_rcc_field calrx_pga_open_rcc_field + * @brief macros for field calrx_pga_open_rcc + * @details Disconnect cross-coupling resistors around PGA during RX loopback calibration (reserved) + * @{ + */ +#define RADIO_RX_CAL_CFG__CALRX_PGA_OPEN_RCC__SHIFT 29 +#define RADIO_RX_CAL_CFG__CALRX_PGA_OPEN_RCC__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALRX_PGA_OPEN_RCC__MASK 0x20000000U +#define RADIO_RX_CAL_CFG__CALRX_PGA_OPEN_RCC__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define RADIO_RX_CAL_CFG__CALRX_PGA_OPEN_RCC__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define RADIO_RX_CAL_CFG__CALRX_PGA_OPEN_RCC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define RADIO_RX_CAL_CFG__CALRX_PGA_OPEN_RCC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define RADIO_RX_CAL_CFG__CALRX_PGA_OPEN_RCC__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define RADIO_RX_CAL_CFG__CALRX_PGA_OPEN_RCC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define RADIO_RX_CAL_CFG__CALRX_PGA_OPEN_RCC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field calrx_pga_open_rfb */ +/** + * @defgroup radio_rx_regs_core_calrx_pga_open_rfb_field calrx_pga_open_rfb_field + * @brief macros for field calrx_pga_open_rfb + * @details Disconnect feedback resistors around PGA during RX loopback calibration (reserved) + * @{ + */ +#define RADIO_RX_CAL_CFG__CALRX_PGA_OPEN_RFB__SHIFT 30 +#define RADIO_RX_CAL_CFG__CALRX_PGA_OPEN_RFB__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALRX_PGA_OPEN_RFB__MASK 0x40000000U +#define RADIO_RX_CAL_CFG__CALRX_PGA_OPEN_RFB__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define RADIO_RX_CAL_CFG__CALRX_PGA_OPEN_RFB__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define RADIO_RX_CAL_CFG__CALRX_PGA_OPEN_RFB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define RADIO_RX_CAL_CFG__CALRX_PGA_OPEN_RFB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define RADIO_RX_CAL_CFG__CALRX_PGA_OPEN_RFB__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define RADIO_RX_CAL_CFG__CALRX_PGA_OPEN_RFB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define RADIO_RX_CAL_CFG__CALRX_PGA_OPEN_RFB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field calrx_adc_en */ +/** + * @defgroup radio_rx_regs_core_calrx_adc_en_field calrx_adc_en_field + * @brief macros for field calrx_adc_en + * @details ADC enable during RX loopback calibration (reserved) + * @{ + */ +#define RADIO_RX_CAL_CFG__CALRX_ADC_EN__SHIFT 31 +#define RADIO_RX_CAL_CFG__CALRX_ADC_EN__WIDTH 1 +#define RADIO_RX_CAL_CFG__CALRX_ADC_EN__MASK 0x80000000U +#define RADIO_RX_CAL_CFG__CALRX_ADC_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO_RX_CAL_CFG__CALRX_ADC_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define RADIO_RX_CAL_CFG__CALRX_ADC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define RADIO_RX_CAL_CFG__CALRX_ADC_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADIO_RX_CAL_CFG__CALRX_ADC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define RADIO_RX_CAL_CFG__CALRX_ADC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define RADIO_RX_CAL_CFG__CALRX_ADC_EN__RESET_VALUE 0x00000001U +/** @} */ +#define RADIO_RX_CAL_CFG__TYPE uint32_t +#define RADIO_RX_CAL_CFG__READ 0xffffffffU +#define RADIO_RX_CAL_CFG__WRITE 0xffffffffU +#define RADIO_RX_CAL_CFG__PRESERVED 0x00000000U +#define RADIO_RX_CAL_CFG__RESET_VALUE 0x9321e126U + +#endif /* __RADIO_RX_CAL_CFG_MACRO__ */ + +/** @} end of cal_cfg */ + +/* macros for BlueprintGlobalNameSpace::radio_rx_gain_ctrl */ +/** + * @defgroup radio_rx_regs_core_gain_ctrl gain_ctrl + * @brief Gain control overrides definitions. + * @{ + */ +#ifndef __RADIO_RX_GAIN_CTRL_MACRO__ +#define __RADIO_RX_GAIN_CTRL_MACRO__ + +/* macros for field rfgain_ov_en */ +/** + * @defgroup radio_rx_regs_core_rfgain_ov_en_field rfgain_ov_en_field + * @brief macros for field rfgain_ov_en + * @details When set, take LNA gain from override registers, note DC offset won't be applied correctly + * @{ + */ +#define RADIO_RX_GAIN_CTRL__RFGAIN_OV_EN__SHIFT 0 +#define RADIO_RX_GAIN_CTRL__RFGAIN_OV_EN__WIDTH 1 +#define RADIO_RX_GAIN_CTRL__RFGAIN_OV_EN__MASK 0x00000001U +#define RADIO_RX_GAIN_CTRL__RFGAIN_OV_EN__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RADIO_RX_GAIN_CTRL__RFGAIN_OV_EN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RADIO_RX_GAIN_CTRL__RFGAIN_OV_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define RADIO_RX_GAIN_CTRL__RFGAIN_OV_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define RADIO_RX_GAIN_CTRL__RFGAIN_OV_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define RADIO_RX_GAIN_CTRL__RFGAIN_OV_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define RADIO_RX_GAIN_CTRL__RFGAIN_OV_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bbgain_ov_en */ +/** + * @defgroup radio_rx_regs_core_bbgain_ov_en_field bbgain_ov_en_field + * @brief macros for field bbgain_ov_en + * @details When set, take TIA and PGA gain from override registers + * @{ + */ +#define RADIO_RX_GAIN_CTRL__BBGAIN_OV_EN__SHIFT 1 +#define RADIO_RX_GAIN_CTRL__BBGAIN_OV_EN__WIDTH 1 +#define RADIO_RX_GAIN_CTRL__BBGAIN_OV_EN__MASK 0x00000002U +#define RADIO_RX_GAIN_CTRL__BBGAIN_OV_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define RADIO_RX_GAIN_CTRL__BBGAIN_OV_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define RADIO_RX_GAIN_CTRL__BBGAIN_OV_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define RADIO_RX_GAIN_CTRL__BBGAIN_OV_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define RADIO_RX_GAIN_CTRL__BBGAIN_OV_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define RADIO_RX_GAIN_CTRL__BBGAIN_OV_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define RADIO_RX_GAIN_CTRL__BBGAIN_OV_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field lnagain_ovr */ +/** + * @defgroup radio_rx_regs_core_lnagain_ovr_field lnagain_ovr_field + * @brief macros for field lnagain_ovr + * @details LNA gain override when rfgain_ov_en = 1 + * @{ + */ +#define RADIO_RX_GAIN_CTRL__LNAGAIN_OVR__SHIFT 2 +#define RADIO_RX_GAIN_CTRL__LNAGAIN_OVR__WIDTH 3 +#define RADIO_RX_GAIN_CTRL__LNAGAIN_OVR__MASK 0x0000001cU +#define RADIO_RX_GAIN_CTRL__LNAGAIN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x0000001cU) >> 2) +#define RADIO_RX_GAIN_CTRL__LNAGAIN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000001cU) +#define RADIO_RX_GAIN_CTRL__LNAGAIN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((uint32_t)(src) <<\ + 2) & 0x0000001cU) +#define RADIO_RX_GAIN_CTRL__LNAGAIN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000001cU))) +#define RADIO_RX_GAIN_CTRL__LNAGAIN_OVR__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field tia_gain_ovr */ +/** + * @defgroup radio_rx_regs_core_tia_gain_ovr_field tia_gain_ovr_field + * @brief macros for field tia_gain_ovr + * @details Override value for TIA gain + * @{ + */ +#define RADIO_RX_GAIN_CTRL__TIA_GAIN_OVR__SHIFT 5 +#define RADIO_RX_GAIN_CTRL__TIA_GAIN_OVR__WIDTH 2 +#define RADIO_RX_GAIN_CTRL__TIA_GAIN_OVR__MASK 0x00000060U +#define RADIO_RX_GAIN_CTRL__TIA_GAIN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000060U) >> 5) +#define RADIO_RX_GAIN_CTRL__TIA_GAIN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000060U) +#define RADIO_RX_GAIN_CTRL__TIA_GAIN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000060U) | (((uint32_t)(src) <<\ + 5) & 0x00000060U) +#define RADIO_RX_GAIN_CTRL__TIA_GAIN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000060U))) +#define RADIO_RX_GAIN_CTRL__TIA_GAIN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pga_gain_ovr */ +/** + * @defgroup radio_rx_regs_core_pga_gain_ovr_field pga_gain_ovr_field + * @brief macros for field pga_gain_ovr + * @details Override value for PGA gain + * @{ + */ +#define RADIO_RX_GAIN_CTRL__PGA_GAIN_OVR__SHIFT 7 +#define RADIO_RX_GAIN_CTRL__PGA_GAIN_OVR__WIDTH 5 +#define RADIO_RX_GAIN_CTRL__PGA_GAIN_OVR__MASK 0x00000f80U +#define RADIO_RX_GAIN_CTRL__PGA_GAIN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000f80U) >> 7) +#define RADIO_RX_GAIN_CTRL__PGA_GAIN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000f80U) +#define RADIO_RX_GAIN_CTRL__PGA_GAIN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f80U) | (((uint32_t)(src) <<\ + 7) & 0x00000f80U) +#define RADIO_RX_GAIN_CTRL__PGA_GAIN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000f80U))) +#define RADIO_RX_GAIN_CTRL__PGA_GAIN_OVR__RESET_VALUE 0x00000018U +/** @} */ +#define RADIO_RX_GAIN_CTRL__TYPE uint32_t +#define RADIO_RX_GAIN_CTRL__READ 0x00000fffU +#define RADIO_RX_GAIN_CTRL__WRITE 0x00000fffU +#define RADIO_RX_GAIN_CTRL__PRESERVED 0x00000000U +#define RADIO_RX_GAIN_CTRL__RESET_VALUE 0x00000c1cU + +#endif /* __RADIO_RX_GAIN_CTRL_MACRO__ */ + +/** @} end of gain_ctrl */ + +/* macros for BlueprintGlobalNameSpace::radio_rx_ana_ctrl */ +/** + * @defgroup radio_rx_regs_core_ana_ctrl ana_ctrl + * @brief Analog adjustments and test mode control definitions. + * @{ + */ +#ifndef __RADIO_RX_ANA_CTRL_MACRO__ +#define __RADIO_RX_ANA_CTRL_MACRO__ + +/* macros for field lna_shortSrc */ +/** + * @defgroup radio_rx_regs_core_lna_shortSrc_field lna_shortSrc_field + * @brief macros for field lna_shortSrc + * @details short source degen inductor + * @{ + */ +#define RADIO_RX_ANA_CTRL__LNA_SHORTSRC__SHIFT 0 +#define RADIO_RX_ANA_CTRL__LNA_SHORTSRC__WIDTH 1 +#define RADIO_RX_ANA_CTRL__LNA_SHORTSRC__MASK 0x00000001U +#define RADIO_RX_ANA_CTRL__LNA_SHORTSRC__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RADIO_RX_ANA_CTRL__LNA_SHORTSRC__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RADIO_RX_ANA_CTRL__LNA_SHORTSRC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define RADIO_RX_ANA_CTRL__LNA_SHORTSRC__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define RADIO_RX_ANA_CTRL__LNA_SHORTSRC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define RADIO_RX_ANA_CTRL__LNA_SHORTSRC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define RADIO_RX_ANA_CTRL__LNA_SHORTSRC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field lna_ctune */ +/** + * @defgroup radio_rx_regs_core_lna_ctune_field lna_ctune_field + * @brief macros for field lna_ctune + * @details find the best value + * @{ + */ +#define RADIO_RX_ANA_CTRL__LNA_CTUNE__SHIFT 1 +#define RADIO_RX_ANA_CTRL__LNA_CTUNE__WIDTH 3 +#define RADIO_RX_ANA_CTRL__LNA_CTUNE__MASK 0x0000000eU +#define RADIO_RX_ANA_CTRL__LNA_CTUNE__READ(src) \ + (((uint32_t)(src)\ + & 0x0000000eU) >> 1) +#define RADIO_RX_ANA_CTRL__LNA_CTUNE__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x0000000eU) +#define RADIO_RX_ANA_CTRL__LNA_CTUNE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((uint32_t)(src) <<\ + 1) & 0x0000000eU) +#define RADIO_RX_ANA_CTRL__LNA_CTUNE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x0000000eU))) +#define RADIO_RX_ANA_CTRL__LNA_CTUNE__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field tia_open_rcc */ +/** + * @defgroup radio_rx_regs_core_tia_open_rcc_field tia_open_rcc_field + * @brief macros for field tia_open_rcc + * @details when =1, disconnect cross-coupling resistor around TIA and revert to real filter + * @{ + */ +#define RADIO_RX_ANA_CTRL__TIA_OPEN_RCC__SHIFT 4 +#define RADIO_RX_ANA_CTRL__TIA_OPEN_RCC__WIDTH 1 +#define RADIO_RX_ANA_CTRL__TIA_OPEN_RCC__MASK 0x00000010U +#define RADIO_RX_ANA_CTRL__TIA_OPEN_RCC__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define RADIO_RX_ANA_CTRL__TIA_OPEN_RCC__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define RADIO_RX_ANA_CTRL__TIA_OPEN_RCC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define RADIO_RX_ANA_CTRL__TIA_OPEN_RCC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define RADIO_RX_ANA_CTRL__TIA_OPEN_RCC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define RADIO_RX_ANA_CTRL__TIA_OPEN_RCC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define RADIO_RX_ANA_CTRL__TIA_OPEN_RCC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tia_open_rfb */ +/** + * @defgroup radio_rx_regs_core_tia_open_rfb_field tia_open_rfb_field + * @brief macros for field tia_open_rfb + * @details may need for test + * @{ + */ +#define RADIO_RX_ANA_CTRL__TIA_OPEN_RFB__SHIFT 5 +#define RADIO_RX_ANA_CTRL__TIA_OPEN_RFB__WIDTH 1 +#define RADIO_RX_ANA_CTRL__TIA_OPEN_RFB__MASK 0x00000020U +#define RADIO_RX_ANA_CTRL__TIA_OPEN_RFB__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define RADIO_RX_ANA_CTRL__TIA_OPEN_RFB__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define RADIO_RX_ANA_CTRL__TIA_OPEN_RFB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define RADIO_RX_ANA_CTRL__TIA_OPEN_RFB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define RADIO_RX_ANA_CTRL__TIA_OPEN_RFB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define RADIO_RX_ANA_CTRL__TIA_OPEN_RFB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define RADIO_RX_ANA_CTRL__TIA_OPEN_RFB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pga_open_rcc */ +/** + * @defgroup radio_rx_regs_core_pga_open_rcc_field pga_open_rcc_field + * @brief macros for field pga_open_rcc + * @details when =1, disconnect cross-coupling resistor around TIA and revert to real filter + * @{ + */ +#define RADIO_RX_ANA_CTRL__PGA_OPEN_RCC__SHIFT 6 +#define RADIO_RX_ANA_CTRL__PGA_OPEN_RCC__WIDTH 1 +#define RADIO_RX_ANA_CTRL__PGA_OPEN_RCC__MASK 0x00000040U +#define RADIO_RX_ANA_CTRL__PGA_OPEN_RCC__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define RADIO_RX_ANA_CTRL__PGA_OPEN_RCC__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define RADIO_RX_ANA_CTRL__PGA_OPEN_RCC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define RADIO_RX_ANA_CTRL__PGA_OPEN_RCC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define RADIO_RX_ANA_CTRL__PGA_OPEN_RCC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define RADIO_RX_ANA_CTRL__PGA_OPEN_RCC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define RADIO_RX_ANA_CTRL__PGA_OPEN_RCC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pga_open_rfb */ +/** + * @defgroup radio_rx_regs_core_pga_open_rfb_field pga_open_rfb_field + * @brief macros for field pga_open_rfb + * @details may need for test + * @{ + */ +#define RADIO_RX_ANA_CTRL__PGA_OPEN_RFB__SHIFT 7 +#define RADIO_RX_ANA_CTRL__PGA_OPEN_RFB__WIDTH 1 +#define RADIO_RX_ANA_CTRL__PGA_OPEN_RFB__MASK 0x00000080U +#define RADIO_RX_ANA_CTRL__PGA_OPEN_RFB__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define RADIO_RX_ANA_CTRL__PGA_OPEN_RFB__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define RADIO_RX_ANA_CTRL__PGA_OPEN_RFB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define RADIO_RX_ANA_CTRL__PGA_OPEN_RFB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define RADIO_RX_ANA_CTRL__PGA_OPEN_RFB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define RADIO_RX_ANA_CTRL__PGA_OPEN_RFB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define RADIO_RX_ANA_CTRL__PGA_OPEN_RFB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tia_pkdet_ref_ctrl */ +/** + * @defgroup radio_rx_regs_core_tia_pkdet_ref_ctrl_field tia_pkdet_ref_ctrl_field + * @brief macros for field tia_pkdet_ref_ctrl + * @details adjusts tia peak detector level + * @{ + */ +#define RADIO_RX_ANA_CTRL__TIA_PKDET_REF_CTRL__SHIFT 8 +#define RADIO_RX_ANA_CTRL__TIA_PKDET_REF_CTRL__WIDTH 3 +#define RADIO_RX_ANA_CTRL__TIA_PKDET_REF_CTRL__MASK 0x00000700U +#define RADIO_RX_ANA_CTRL__TIA_PKDET_REF_CTRL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000700U) >> 8) +#define RADIO_RX_ANA_CTRL__TIA_PKDET_REF_CTRL__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000700U) +#define RADIO_RX_ANA_CTRL__TIA_PKDET_REF_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((uint32_t)(src) <<\ + 8) & 0x00000700U) +#define RADIO_RX_ANA_CTRL__TIA_PKDET_REF_CTRL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000700U))) +#define RADIO_RX_ANA_CTRL__TIA_PKDET_REF_CTRL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field testiq_ctrl */ +/** + * @defgroup radio_rx_regs_core_testiq_ctrl_field testiq_ctrl_field + * @brief macros for field testiq_ctrl + * @details connect RXBB test points to the testIQ bus (uses one-hot format); 0=hiZ, 1=TIA input, 2=TIA output, 4=PGA output, other values=invalid + * @{ + */ +#define RADIO_RX_ANA_CTRL__TESTIQ_CTRL__SHIFT 11 +#define RADIO_RX_ANA_CTRL__TESTIQ_CTRL__WIDTH 3 +#define RADIO_RX_ANA_CTRL__TESTIQ_CTRL__MASK 0x00003800U +#define RADIO_RX_ANA_CTRL__TESTIQ_CTRL__READ(src) \ + (((uint32_t)(src)\ + & 0x00003800U) >> 11) +#define RADIO_RX_ANA_CTRL__TESTIQ_CTRL__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00003800U) +#define RADIO_RX_ANA_CTRL__TESTIQ_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((uint32_t)(src) <<\ + 11) & 0x00003800U) +#define RADIO_RX_ANA_CTRL__TESTIQ_CTRL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00003800U))) +#define RADIO_RX_ANA_CTRL__TESTIQ_CTRL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_atbsel */ +/** + * @defgroup radio_rx_regs_core_rx_atbsel_field rx_atbsel_field + * @brief macros for field rx_atbsel + * @details RXFE and RXBB analog test bus selection, 0 = high-Z; 1 = LNA peakdet vref; 2 = LNA peakdet voltage; 3 = RXBB vref_lo_boost; 4 = RXBB common-mode voltage; 5 = spare ir1u current; 6 = spare ic1u current + * @{ + */ +#define RADIO_RX_ANA_CTRL__RX_ATBSEL__SHIFT 14 +#define RADIO_RX_ANA_CTRL__RX_ATBSEL__WIDTH 3 +#define RADIO_RX_ANA_CTRL__RX_ATBSEL__MASK 0x0001c000U +#define RADIO_RX_ANA_CTRL__RX_ATBSEL__READ(src) \ + (((uint32_t)(src)\ + & 0x0001c000U) >> 14) +#define RADIO_RX_ANA_CTRL__RX_ATBSEL__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0001c000U) +#define RADIO_RX_ANA_CTRL__RX_ATBSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((uint32_t)(src) <<\ + 14) & 0x0001c000U) +#define RADIO_RX_ANA_CTRL__RX_ATBSEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0001c000U))) +#define RADIO_RX_ANA_CTRL__RX_ATBSEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adc_atbsel */ +/** + * @defgroup radio_rx_regs_core_adc_atbsel_field adc_atbsel_field + * @brief macros for field adc_atbsel + * @details ADC analog test bus selection, 0 = high-Z; 1 = nbias; 2 = vref0p2; 3 = refnQ; 4 = refpQ; 5 = refnI; 6 = refpI; 7 = ic1u + * @{ + */ +#define RADIO_RX_ANA_CTRL__ADC_ATBSEL__SHIFT 17 +#define RADIO_RX_ANA_CTRL__ADC_ATBSEL__WIDTH 4 +#define RADIO_RX_ANA_CTRL__ADC_ATBSEL__MASK 0x001e0000U +#define RADIO_RX_ANA_CTRL__ADC_ATBSEL__READ(src) \ + (((uint32_t)(src)\ + & 0x001e0000U) >> 17) +#define RADIO_RX_ANA_CTRL__ADC_ATBSEL__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x001e0000U) +#define RADIO_RX_ANA_CTRL__ADC_ATBSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001e0000U) | (((uint32_t)(src) <<\ + 17) & 0x001e0000U) +#define RADIO_RX_ANA_CTRL__ADC_ATBSEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x001e0000U))) +#define RADIO_RX_ANA_CTRL__ADC_ATBSEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field lna_refLVlBiasCas */ +/** + * @defgroup radio_rx_regs_core_lna_refLVlBiasCas_field lna_refLVlBiasCas_field + * @brief macros for field lna_refLVlBiasCas + * @details lna cascode bias + * @{ + */ +#define RADIO_RX_ANA_CTRL__LNA_REFLVLBIASCAS__SHIFT 21 +#define RADIO_RX_ANA_CTRL__LNA_REFLVLBIASCAS__WIDTH 2 +#define RADIO_RX_ANA_CTRL__LNA_REFLVLBIASCAS__MASK 0x00600000U +#define RADIO_RX_ANA_CTRL__LNA_REFLVLBIASCAS__READ(src) \ + (((uint32_t)(src)\ + & 0x00600000U) >> 21) +#define RADIO_RX_ANA_CTRL__LNA_REFLVLBIASCAS__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00600000U) +#define RADIO_RX_ANA_CTRL__LNA_REFLVLBIASCAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((uint32_t)(src) <<\ + 21) & 0x00600000U) +#define RADIO_RX_ANA_CTRL__LNA_REFLVLBIASCAS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00600000U))) +#define RADIO_RX_ANA_CTRL__LNA_REFLVLBIASCAS__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field rx_spare */ +/** + * @defgroup radio_rx_regs_core_rx_spare_field rx_spare_field + * @brief macros for field rx_spare + * @details Spare bits + * @{ + */ +#define RADIO_RX_ANA_CTRL__RX_SPARE__SHIFT 23 +#define RADIO_RX_ANA_CTRL__RX_SPARE__WIDTH 9 +#define RADIO_RX_ANA_CTRL__RX_SPARE__MASK 0xff800000U +#define RADIO_RX_ANA_CTRL__RX_SPARE__READ(src) \ + (((uint32_t)(src)\ + & 0xff800000U) >> 23) +#define RADIO_RX_ANA_CTRL__RX_SPARE__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0xff800000U) +#define RADIO_RX_ANA_CTRL__RX_SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff800000U) | (((uint32_t)(src) <<\ + 23) & 0xff800000U) +#define RADIO_RX_ANA_CTRL__RX_SPARE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0xff800000U))) +#define RADIO_RX_ANA_CTRL__RX_SPARE__RESET_VALUE 0x00000000U +/** @} */ +#define RADIO_RX_ANA_CTRL__TYPE uint32_t +#define RADIO_RX_ANA_CTRL__READ 0xffffffffU +#define RADIO_RX_ANA_CTRL__WRITE 0xffffffffU +#define RADIO_RX_ANA_CTRL__PRESERVED 0x00000000U +#define RADIO_RX_ANA_CTRL__RESET_VALUE 0x00200008U + +#endif /* __RADIO_RX_ANA_CTRL_MACRO__ */ + +/** @} end of ana_ctrl */ + +/* macros for BlueprintGlobalNameSpace::radio_rx_lnagain0 */ +/** + * @defgroup radio_rx_regs_core_lnagain0 lnagain0 + * @brief LNA gain table for LNA, should fix definitions. + * @{ + */ +#ifndef __RADIO_RX_LNAGAIN0_MACRO__ +#define __RADIO_RX_LNAGAIN0_MACRO__ + +/* macros for field entry0 */ +/** + * @defgroup radio_rx_regs_core_entry0_field entry0_field + * @brief macros for field entry0 + * @details LNA gain index 0 + * @{ + */ +#define RADIO_RX_LNAGAIN0__ENTRY0__SHIFT 0 +#define RADIO_RX_LNAGAIN0__ENTRY0__WIDTH 5 +#define RADIO_RX_LNAGAIN0__ENTRY0__MASK 0x0000001fU +#define RADIO_RX_LNAGAIN0__ENTRY0__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define RADIO_RX_LNAGAIN0__ENTRY0__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define RADIO_RX_LNAGAIN0__ENTRY0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define RADIO_RX_LNAGAIN0__ENTRY0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define RADIO_RX_LNAGAIN0__ENTRY0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field entry1 */ +/** + * @defgroup radio_rx_regs_core_entry1_field entry1_field + * @brief macros for field entry1 + * @details LNA gain index 1 + * @{ + */ +#define RADIO_RX_LNAGAIN0__ENTRY1__SHIFT 5 +#define RADIO_RX_LNAGAIN0__ENTRY1__WIDTH 5 +#define RADIO_RX_LNAGAIN0__ENTRY1__MASK 0x000003e0U +#define RADIO_RX_LNAGAIN0__ENTRY1__READ(src) \ + (((uint32_t)(src)\ + & 0x000003e0U) >> 5) +#define RADIO_RX_LNAGAIN0__ENTRY1__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x000003e0U) +#define RADIO_RX_LNAGAIN0__ENTRY1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((uint32_t)(src) <<\ + 5) & 0x000003e0U) +#define RADIO_RX_LNAGAIN0__ENTRY1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000003e0U))) +#define RADIO_RX_LNAGAIN0__ENTRY1__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field entry2 */ +/** + * @defgroup radio_rx_regs_core_entry2_field entry2_field + * @brief macros for field entry2 + * @details LNA gain index 2 + * @{ + */ +#define RADIO_RX_LNAGAIN0__ENTRY2__SHIFT 10 +#define RADIO_RX_LNAGAIN0__ENTRY2__WIDTH 5 +#define RADIO_RX_LNAGAIN0__ENTRY2__MASK 0x00007c00U +#define RADIO_RX_LNAGAIN0__ENTRY2__READ(src) \ + (((uint32_t)(src)\ + & 0x00007c00U) >> 10) +#define RADIO_RX_LNAGAIN0__ENTRY2__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00007c00U) +#define RADIO_RX_LNAGAIN0__ENTRY2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((uint32_t)(src) <<\ + 10) & 0x00007c00U) +#define RADIO_RX_LNAGAIN0__ENTRY2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00007c00U))) +#define RADIO_RX_LNAGAIN0__ENTRY2__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field entry3 */ +/** + * @defgroup radio_rx_regs_core_entry3_field entry3_field + * @brief macros for field entry3 + * @details LNA gain index 3 + * @{ + */ +#define RADIO_RX_LNAGAIN0__ENTRY3__SHIFT 15 +#define RADIO_RX_LNAGAIN0__ENTRY3__WIDTH 5 +#define RADIO_RX_LNAGAIN0__ENTRY3__MASK 0x000f8000U +#define RADIO_RX_LNAGAIN0__ENTRY3__READ(src) \ + (((uint32_t)(src)\ + & 0x000f8000U) >> 15) +#define RADIO_RX_LNAGAIN0__ENTRY3__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x000f8000U) +#define RADIO_RX_LNAGAIN0__ENTRY3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((uint32_t)(src) <<\ + 15) & 0x000f8000U) +#define RADIO_RX_LNAGAIN0__ENTRY3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x000f8000U))) +#define RADIO_RX_LNAGAIN0__ENTRY3__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field entry4 */ +/** + * @defgroup radio_rx_regs_core_entry4_field entry4_field + * @brief macros for field entry4 + * @details LNA gain index 4 + * @{ + */ +#define RADIO_RX_LNAGAIN0__ENTRY4__SHIFT 20 +#define RADIO_RX_LNAGAIN0__ENTRY4__WIDTH 5 +#define RADIO_RX_LNAGAIN0__ENTRY4__MASK 0x01f00000U +#define RADIO_RX_LNAGAIN0__ENTRY4__READ(src) \ + (((uint32_t)(src)\ + & 0x01f00000U) >> 20) +#define RADIO_RX_LNAGAIN0__ENTRY4__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x01f00000U) +#define RADIO_RX_LNAGAIN0__ENTRY4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((uint32_t)(src) <<\ + 20) & 0x01f00000U) +#define RADIO_RX_LNAGAIN0__ENTRY4__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x01f00000U))) +#define RADIO_RX_LNAGAIN0__ENTRY4__RESET_VALUE 0x0000000fU +/** @} */ + +/* macros for field entry5 */ +/** + * @defgroup radio_rx_regs_core_entry5_field entry5_field + * @brief macros for field entry5 + * @details LNA gain index 5 + * @{ + */ +#define RADIO_RX_LNAGAIN0__ENTRY5__SHIFT 25 +#define RADIO_RX_LNAGAIN0__ENTRY5__WIDTH 5 +#define RADIO_RX_LNAGAIN0__ENTRY5__MASK 0x3e000000U +#define RADIO_RX_LNAGAIN0__ENTRY5__READ(src) \ + (((uint32_t)(src)\ + & 0x3e000000U) >> 25) +#define RADIO_RX_LNAGAIN0__ENTRY5__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x3e000000U) +#define RADIO_RX_LNAGAIN0__ENTRY5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((uint32_t)(src) <<\ + 25) & 0x3e000000U) +#define RADIO_RX_LNAGAIN0__ENTRY5__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x3e000000U))) +#define RADIO_RX_LNAGAIN0__ENTRY5__RESET_VALUE 0x0000001fU +/** @} */ +#define RADIO_RX_LNAGAIN0__TYPE uint32_t +#define RADIO_RX_LNAGAIN0__READ 0x3fffffffU +#define RADIO_RX_LNAGAIN0__WRITE 0x3fffffffU +#define RADIO_RX_LNAGAIN0__PRESERVED 0x00000000U +#define RADIO_RX_LNAGAIN0__RESET_VALUE 0x3ef38c20U + +#endif /* __RADIO_RX_LNAGAIN0_MACRO__ */ + +/** @} end of lnagain0 */ + +/* macros for BlueprintGlobalNameSpace::radio_rx_rxbias */ +/** + * @defgroup radio_rx_regs_core_rxbias rxbias + * @brief Bias current settings, 0.25uA to 2uA in 0.25uA steps definitions. + * @{ + */ +#ifndef __RADIO_RX_RXBIAS_MACRO__ +#define __RADIO_RX_RXBIAS_MACRO__ + +/* macros for field sel_irtiapkdet_ref */ +/** + * @defgroup radio_rx_regs_core_sel_irtiapkdet_ref_field sel_irtiapkdet_ref_field + * @brief macros for field sel_irtiapkdet_ref + * @details Mixer IC bias current, default 1uA + * @{ + */ +#define RADIO_RX_RXBIAS__SEL_IRTIAPKDET_REF__SHIFT 0 +#define RADIO_RX_RXBIAS__SEL_IRTIAPKDET_REF__WIDTH 3 +#define RADIO_RX_RXBIAS__SEL_IRTIAPKDET_REF__MASK 0x00000007U +#define RADIO_RX_RXBIAS__SEL_IRTIAPKDET_REF__READ(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define RADIO_RX_RXBIAS__SEL_IRTIAPKDET_REF__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define RADIO_RX_RXBIAS__SEL_IRTIAPKDET_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define RADIO_RX_RXBIAS__SEL_IRTIAPKDET_REF__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define RADIO_RX_RXBIAS__SEL_IRTIAPKDET_REF__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field sel_ictia */ +/** + * @defgroup radio_rx_regs_core_sel_ictia_field sel_ictia_field + * @brief macros for field sel_ictia + * @details TIA IC bias current for both I and Q channels, default 1uA + * @{ + */ +#define RADIO_RX_RXBIAS__SEL_ICTIA__SHIFT 3 +#define RADIO_RX_RXBIAS__SEL_ICTIA__WIDTH 3 +#define RADIO_RX_RXBIAS__SEL_ICTIA__MASK 0x00000038U +#define RADIO_RX_RXBIAS__SEL_ICTIA__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define RADIO_RX_RXBIAS__SEL_ICTIA__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define RADIO_RX_RXBIAS__SEL_ICTIA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define RADIO_RX_RXBIAS__SEL_ICTIA__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define RADIO_RX_RXBIAS__SEL_ICTIA__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field sel_ictiadcoc */ +/** + * @defgroup radio_rx_regs_core_sel_ictiadcoc_field sel_ictiadcoc_field + * @brief macros for field sel_ictiadcoc + * @details TIA offset DAC IC bias current for both I and Q channels, default 0.75uA + * @{ + */ +#define RADIO_RX_RXBIAS__SEL_ICTIADCOC__SHIFT 6 +#define RADIO_RX_RXBIAS__SEL_ICTIADCOC__WIDTH 3 +#define RADIO_RX_RXBIAS__SEL_ICTIADCOC__MASK 0x000001c0U +#define RADIO_RX_RXBIAS__SEL_ICTIADCOC__READ(src) \ + (((uint32_t)(src)\ + & 0x000001c0U) >> 6) +#define RADIO_RX_RXBIAS__SEL_ICTIADCOC__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000001c0U) +#define RADIO_RX_RXBIAS__SEL_ICTIADCOC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((uint32_t)(src) <<\ + 6) & 0x000001c0U) +#define RADIO_RX_RXBIAS__SEL_ICTIADCOC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000001c0U))) +#define RADIO_RX_RXBIAS__SEL_ICTIADCOC__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field sel_irpgadcoc */ +/** + * @defgroup radio_rx_regs_core_sel_irpgadcoc_field sel_irpgadcoc_field + * @brief macros for field sel_irpgadcoc + * @details PGA offset DAC IC bias current for both I and Q channels, default 1uA + * @{ + */ +#define RADIO_RX_RXBIAS__SEL_IRPGADCOC__SHIFT 9 +#define RADIO_RX_RXBIAS__SEL_IRPGADCOC__WIDTH 3 +#define RADIO_RX_RXBIAS__SEL_IRPGADCOC__MASK 0x00000e00U +#define RADIO_RX_RXBIAS__SEL_IRPGADCOC__READ(src) \ + (((uint32_t)(src)\ + & 0x00000e00U) >> 9) +#define RADIO_RX_RXBIAS__SEL_IRPGADCOC__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000e00U) +#define RADIO_RX_RXBIAS__SEL_IRPGADCOC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((uint32_t)(src) <<\ + 9) & 0x00000e00U) +#define RADIO_RX_RXBIAS__SEL_IRPGADCOC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000e00U))) +#define RADIO_RX_RXBIAS__SEL_IRPGADCOC__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field sel_icadc */ +/** + * @defgroup radio_rx_regs_core_sel_icadc_field sel_icadc_field + * @brief macros for field sel_icadc + * @details ADC IC bias current, default 1uA + * @{ + */ +#define RADIO_RX_RXBIAS__SEL_ICADC__SHIFT 12 +#define RADIO_RX_RXBIAS__SEL_ICADC__WIDTH 3 +#define RADIO_RX_RXBIAS__SEL_ICADC__MASK 0x00007000U +#define RADIO_RX_RXBIAS__SEL_ICADC__READ(src) \ + (((uint32_t)(src)\ + & 0x00007000U) >> 12) +#define RADIO_RX_RXBIAS__SEL_ICADC__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00007000U) +#define RADIO_RX_RXBIAS__SEL_ICADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((uint32_t)(src) <<\ + 12) & 0x00007000U) +#define RADIO_RX_RXBIAS__SEL_ICADC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00007000U))) +#define RADIO_RX_RXBIAS__SEL_ICADC__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field sel_icspare */ +/** + * @defgroup radio_rx_regs_core_sel_icspare_field sel_icspare_field + * @brief macros for field sel_icspare + * @details Spare IC bias currents, default 1uA + * @{ + */ +#define RADIO_RX_RXBIAS__SEL_ICSPARE__SHIFT 15 +#define RADIO_RX_RXBIAS__SEL_ICSPARE__WIDTH 3 +#define RADIO_RX_RXBIAS__SEL_ICSPARE__MASK 0x00038000U +#define RADIO_RX_RXBIAS__SEL_ICSPARE__READ(src) \ + (((uint32_t)(src)\ + & 0x00038000U) >> 15) +#define RADIO_RX_RXBIAS__SEL_ICSPARE__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00038000U) +#define RADIO_RX_RXBIAS__SEL_ICSPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((uint32_t)(src) <<\ + 15) & 0x00038000U) +#define RADIO_RX_RXBIAS__SEL_ICSPARE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00038000U))) +#define RADIO_RX_RXBIAS__SEL_ICSPARE__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field sel_irrxbb */ +/** + * @defgroup radio_rx_regs_core_sel_irrxbb_field sel_irrxbb_field + * @brief macros for field sel_irrxbb + * @details RXBB IR bias current, default 1uA + * @{ + */ +#define RADIO_RX_RXBIAS__SEL_IRRXBB__SHIFT 18 +#define RADIO_RX_RXBIAS__SEL_IRRXBB__WIDTH 3 +#define RADIO_RX_RXBIAS__SEL_IRRXBB__MASK 0x001c0000U +#define RADIO_RX_RXBIAS__SEL_IRRXBB__READ(src) \ + (((uint32_t)(src)\ + & 0x001c0000U) >> 18) +#define RADIO_RX_RXBIAS__SEL_IRRXBB__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x001c0000U) +#define RADIO_RX_RXBIAS__SEL_IRRXBB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((uint32_t)(src) <<\ + 18) & 0x001c0000U) +#define RADIO_RX_RXBIAS__SEL_IRRXBB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x001c0000U))) +#define RADIO_RX_RXBIAS__SEL_IRRXBB__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field sel_iradc */ +/** + * @defgroup radio_rx_regs_core_sel_iradc_field sel_iradc_field + * @brief macros for field sel_iradc + * @details ADC IR bias current, default 1uA + * @{ + */ +#define RADIO_RX_RXBIAS__SEL_IRADC__SHIFT 21 +#define RADIO_RX_RXBIAS__SEL_IRADC__WIDTH 3 +#define RADIO_RX_RXBIAS__SEL_IRADC__MASK 0x00e00000U +#define RADIO_RX_RXBIAS__SEL_IRADC__READ(src) \ + (((uint32_t)(src)\ + & 0x00e00000U) >> 21) +#define RADIO_RX_RXBIAS__SEL_IRADC__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00e00000U) +#define RADIO_RX_RXBIAS__SEL_IRADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((uint32_t)(src) <<\ + 21) & 0x00e00000U) +#define RADIO_RX_RXBIAS__SEL_IRADC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00e00000U))) +#define RADIO_RX_RXBIAS__SEL_IRADC__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field sel_irspare */ +/** + * @defgroup radio_rx_regs_core_sel_irspare_field sel_irspare_field + * @brief macros for field sel_irspare + * @details Spare IR bias currents, default 1uA + * @{ + */ +#define RADIO_RX_RXBIAS__SEL_IRSPARE__SHIFT 24 +#define RADIO_RX_RXBIAS__SEL_IRSPARE__WIDTH 3 +#define RADIO_RX_RXBIAS__SEL_IRSPARE__MASK 0x07000000U +#define RADIO_RX_RXBIAS__SEL_IRSPARE__READ(src) \ + (((uint32_t)(src)\ + & 0x07000000U) >> 24) +#define RADIO_RX_RXBIAS__SEL_IRSPARE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x07000000U) +#define RADIO_RX_RXBIAS__SEL_IRSPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((uint32_t)(src) <<\ + 24) & 0x07000000U) +#define RADIO_RX_RXBIAS__SEL_IRSPARE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x07000000U))) +#define RADIO_RX_RXBIAS__SEL_IRSPARE__RESET_VALUE 0x00000003U +/** @} */ +#define RADIO_RX_RXBIAS__TYPE uint32_t +#define RADIO_RX_RXBIAS__READ 0x07ffffffU +#define RADIO_RX_RXBIAS__WRITE 0x07ffffffU +#define RADIO_RX_RXBIAS__PRESERVED 0x00000000U +#define RADIO_RX_RXBIAS__RESET_VALUE 0x036db6fbU + +#endif /* __RADIO_RX_RXBIAS_MACRO__ */ + +/** @} end of rxbias */ + +/* macros for BlueprintGlobalNameSpace::radio_rx_status */ +/** + * @defgroup radio_rx_regs_core_status status + * @brief Applied enables, ctune, and LNA peak detector readback definitions. + * @{ + */ +#ifndef __RADIO_RX_STATUS_MACRO__ +#define __RADIO_RX_STATUS_MACRO__ + +/* macros for field tia_peakdet */ +/** + * @defgroup radio_rx_regs_core_tia_peakdet_field tia_peakdet_field + * @brief macros for field tia_peakdet + * @details tia peak detector status + * @{ + */ +#define RADIO_RX_STATUS__TIA_PEAKDET__SHIFT 0 +#define RADIO_RX_STATUS__TIA_PEAKDET__WIDTH 1 +#define RADIO_RX_STATUS__TIA_PEAKDET__MASK 0x00000001U +#define RADIO_RX_STATUS__TIA_PEAKDET__READ(src) ((uint32_t)(src) & 0x00000001U) +#define RADIO_RX_STATUS__TIA_PEAKDET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define RADIO_RX_STATUS__TIA_PEAKDET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define RADIO_RX_STATUS__TIA_PEAKDET__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field lna_en */ +/** + * @defgroup radio_rx_regs_core_lna_en_field lna_en_field + * @brief macros for field lna_en + * @details LNA enable status + * @{ + */ +#define RADIO_RX_STATUS__LNA_EN__SHIFT 1 +#define RADIO_RX_STATUS__LNA_EN__WIDTH 1 +#define RADIO_RX_STATUS__LNA_EN__MASK 0x00000002U +#define RADIO_RX_STATUS__LNA_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define RADIO_RX_STATUS__LNA_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define RADIO_RX_STATUS__LNA_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define RADIO_RX_STATUS__LNA_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field lna_peakdet */ +/** + * @defgroup radio_rx_regs_core_lna_peakdet_field lna_peakdet_field + * @brief macros for field lna_peakdet + * @details LNA peak detector comparator output status + * @{ + */ +#define RADIO_RX_STATUS__LNA_PEAKDET__SHIFT 2 +#define RADIO_RX_STATUS__LNA_PEAKDET__WIDTH 1 +#define RADIO_RX_STATUS__LNA_PEAKDET__MASK 0x00000004U +#define RADIO_RX_STATUS__LNA_PEAKDET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define RADIO_RX_STATUS__LNA_PEAKDET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define RADIO_RX_STATUS__LNA_PEAKDET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define RADIO_RX_STATUS__LNA_PEAKDET__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mix_en */ +/** + * @defgroup radio_rx_regs_core_mix_en_field mix_en_field + * @brief macros for field mix_en + * @details Mixer enable status + * @{ + */ +#define RADIO_RX_STATUS__MIX_EN__SHIFT 3 +#define RADIO_RX_STATUS__MIX_EN__WIDTH 1 +#define RADIO_RX_STATUS__MIX_EN__MASK 0x00000008U +#define RADIO_RX_STATUS__MIX_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define RADIO_RX_STATUS__MIX_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define RADIO_RX_STATUS__MIX_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define RADIO_RX_STATUS__MIX_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tiai_en */ +/** + * @defgroup radio_rx_regs_core_tiai_en_field tiai_en_field + * @brief macros for field tiai_en + * @details TIA I-channel enable status + * @{ + */ +#define RADIO_RX_STATUS__TIAI_EN__SHIFT 4 +#define RADIO_RX_STATUS__TIAI_EN__WIDTH 1 +#define RADIO_RX_STATUS__TIAI_EN__MASK 0x00000010U +#define RADIO_RX_STATUS__TIAI_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define RADIO_RX_STATUS__TIAI_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define RADIO_RX_STATUS__TIAI_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define RADIO_RX_STATUS__TIAI_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pgai_en */ +/** + * @defgroup radio_rx_regs_core_pgai_en_field pgai_en_field + * @brief macros for field pgai_en + * @details PGA I-channel enable status + * @{ + */ +#define RADIO_RX_STATUS__PGAI_EN__SHIFT 5 +#define RADIO_RX_STATUS__PGAI_EN__WIDTH 1 +#define RADIO_RX_STATUS__PGAI_EN__MASK 0x00000020U +#define RADIO_RX_STATUS__PGAI_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define RADIO_RX_STATUS__PGAI_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define RADIO_RX_STATUS__PGAI_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define RADIO_RX_STATUS__PGAI_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adci_en */ +/** + * @defgroup radio_rx_regs_core_adci_en_field adci_en_field + * @brief macros for field adci_en + * @details ADC I-channel enable status + * @{ + */ +#define RADIO_RX_STATUS__ADCI_EN__SHIFT 6 +#define RADIO_RX_STATUS__ADCI_EN__WIDTH 1 +#define RADIO_RX_STATUS__ADCI_EN__MASK 0x00000040U +#define RADIO_RX_STATUS__ADCI_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define RADIO_RX_STATUS__ADCI_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define RADIO_RX_STATUS__ADCI_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define RADIO_RX_STATUS__ADCI_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adcref_en */ +/** + * @defgroup radio_rx_regs_core_adcref_en_field adcref_en_field + * @brief macros for field adcref_en + * @details ADC reference enable status + * @{ + */ +#define RADIO_RX_STATUS__ADCREF_EN__SHIFT 7 +#define RADIO_RX_STATUS__ADCREF_EN__WIDTH 1 +#define RADIO_RX_STATUS__ADCREF_EN__MASK 0x00000080U +#define RADIO_RX_STATUS__ADCREF_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define RADIO_RX_STATUS__ADCREF_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define RADIO_RX_STATUS__ADCREF_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define RADIO_RX_STATUS__ADCREF_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adc_rstb */ +/** + * @defgroup radio_rx_regs_core_adc_rstb_field adc_rstb_field + * @brief macros for field adc_rstb + * @details ADC reset_b status + * @{ + */ +#define RADIO_RX_STATUS__ADC_RSTB__SHIFT 8 +#define RADIO_RX_STATUS__ADC_RSTB__WIDTH 1 +#define RADIO_RX_STATUS__ADC_RSTB__MASK 0x00000100U +#define RADIO_RX_STATUS__ADC_RSTB__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define RADIO_RX_STATUS__ADC_RSTB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define RADIO_RX_STATUS__ADC_RSTB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define RADIO_RX_STATUS__ADC_RSTB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rxbias_en */ +/** + * @defgroup radio_rx_regs_core_rxbias_en_field rxbias_en_field + * @brief macros for field rxbias_en + * @details RX bias enable status + * @{ + */ +#define RADIO_RX_STATUS__RXBIAS_EN__SHIFT 9 +#define RADIO_RX_STATUS__RXBIAS_EN__WIDTH 1 +#define RADIO_RX_STATUS__RXBIAS_EN__MASK 0x00000200U +#define RADIO_RX_STATUS__RXBIAS_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define RADIO_RX_STATUS__RXBIAS_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define RADIO_RX_STATUS__RXBIAS_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define RADIO_RX_STATUS__RXBIAS_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field lnagain */ +/** + * @defgroup radio_rx_regs_core_lnagain_field lnagain_field + * @brief macros for field lnagain + * @details LNA gain status + * @{ + */ +#define RADIO_RX_STATUS__LNAGAIN__SHIFT 10 +#define RADIO_RX_STATUS__LNAGAIN__WIDTH 3 +#define RADIO_RX_STATUS__LNAGAIN__MASK 0x00001c00U +#define RADIO_RX_STATUS__LNAGAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x00001c00U) >> 10) +#define RADIO_RX_STATUS__LNAGAIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tia_gain */ +/** + * @defgroup radio_rx_regs_core_tia_gain_field tia_gain_field + * @brief macros for field tia_gain + * @details TIA gain status + * @{ + */ +#define RADIO_RX_STATUS__TIA_GAIN__SHIFT 13 +#define RADIO_RX_STATUS__TIA_GAIN__WIDTH 2 +#define RADIO_RX_STATUS__TIA_GAIN__MASK 0x00006000U +#define RADIO_RX_STATUS__TIA_GAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x00006000U) >> 13) +#define RADIO_RX_STATUS__TIA_GAIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pga_gain */ +/** + * @defgroup radio_rx_regs_core_pga_gain_field pga_gain_field + * @brief macros for field pga_gain + * @details PGA gain status + * @{ + */ +#define RADIO_RX_STATUS__PGA_GAIN__SHIFT 15 +#define RADIO_RX_STATUS__PGA_GAIN__WIDTH 5 +#define RADIO_RX_STATUS__PGA_GAIN__MASK 0x000f8000U +#define RADIO_RX_STATUS__PGA_GAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x000f8000U) >> 15) +#define RADIO_RX_STATUS__PGA_GAIN__RESET_VALUE 0x00000000U +/** @} */ +#define RADIO_RX_STATUS__TYPE uint32_t +#define RADIO_RX_STATUS__READ 0x000fffffU +#define RADIO_RX_STATUS__PRESERVED 0x00000000U +#define RADIO_RX_STATUS__RESET_VALUE 0x00000000U + +#endif /* __RADIO_RX_STATUS_MACRO__ */ + +/** @} end of status */ + +/* macros for BlueprintGlobalNameSpace::radio_rx_core_id */ +/** + * @defgroup radio_rx_regs_core_core_id core_id + * @brief Core ID definitions. + * @{ + */ +#ifndef __RADIO_RX_CORE_ID_MACRO__ +#define __RADIO_RX_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup radio_rx_regs_core_id_field id_field + * @brief macros for field id + * @details RX in ASCII + * @{ + */ +#define RADIO_RX_CORE_ID__ID__SHIFT 0 +#define RADIO_RX_CORE_ID__ID__WIDTH 32 +#define RADIO_RX_CORE_ID__ID__MASK 0xffffffffU +#define RADIO_RX_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define RADIO_RX_CORE_ID__ID__RESET_VALUE 0x52582020U +/** @} */ +#define RADIO_RX_CORE_ID__TYPE uint32_t +#define RADIO_RX_CORE_ID__READ 0xffffffffU +#define RADIO_RX_CORE_ID__PRESERVED 0x00000000U +#define RADIO_RX_CORE_ID__RESET_VALUE 0x52582020U + +#endif /* __RADIO_RX_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of RADIO_RX_REGS_CORE */ +#endif /* __REG_RADIO_RX_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/radio_spi.h b/ATM33xx-5/include/reg/radio_spi.h new file mode 100644 index 0000000..45928b7 --- /dev/null +++ b/ATM33xx-5/include/reg/radio_spi.h @@ -0,0 +1,58 @@ +/** + ***************************************************************************** + * + * @file radio_spi.h + * + * @brief Radio SPI definitions + * + * Copyright (C) Atmosic 2022-2024 + * + ***************************************************************************** + */ + +#pragma once + +/** + * @defgroup at_radio_spi radio_spi + * @ingroup AT_REG + * @brief radio spi definitions. + * @{ + */ +#define RADIO_SPI__DUMMY_CYCLES 3 + +#define RADIO_RX__REG_BLADDR 0 +#define RADIO_RX__MODE_CTRL_REG_ADDR 0x0 +#define RADIO_RX__MODE_CTRL2_REG_ADDR 0x4 +#define RADIO_RX__CAL_CFG_REG_ADDR 0x8 +#define RADIO_RX__GAIN_CTRL_REG_ADDR 0xc +#define RADIO_RX__ANA_CTRL_REG_ADDR 0x10 +#define RADIO_RX__LNAGAIN0_REG_ADDR 0x14 +#define RADIO_RX__RXBIAS_REG_ADDR 0x18 +#define RADIO_RX__STATUS_REG_ADDR 0x1c +#define RADIO_RX__CORE_ID_REG_ADDR 0x20 + +#define RADIO_SYNTH__REG_BLADDR 1 +#define RADIO_SYNTH__SYNTH_CTRL_0_REG_ADDR 0x0 +#define RADIO_SYNTH__SYNTH_CTRL_1_REG_ADDR 0x4 +#define RADIO_SYNTH__SYNTH_CTRL_2_REG_ADDR 0x8 +#define RADIO_SYNTH__SYNTH_CTRL_3_REG_ADDR 0xc +#define RADIO_SYNTH__SYNTH_READOUT_REG_ADDR 0x10 +#define RADIO_SYNTH__CORE_ID_REG_ADDR 0x14 + +#define RADIO_TOP__REG_BLADDR 2 +#define RADIO_TOP__MODE_REG_ADDR 0x0 +#define RADIO_TOP__BIAS_REG_ADDR 0x4 +#define RADIO_TOP__TEST_REG_ADDR 0x8 +#define RADIO_TOP__STATUS_REG_ADDR 0xc +#define RADIO_TOP__VERSION_REG_ADDR 0x10 +#define RADIO_TOP__PROCMON_REG_ADDR 0x14 +#define RADIO_TOP__PROCMON_RESULT_REG_ADDR 0x18 +#define RADIO_TOP__CORE_ID_REG_ADDR 0x1c + +#define PLL__REG_BLADDR 3 +#define PLL__PLL_REG_ADDR 0x0 +#define PLL__TEST_REG_ADDR 0x4 +#define PLL__READOUT_REG_ADDR 0x8 +#define PLL__CORE_ID_REG_ADDR 0xc + +/** @} end of at_radio_spi */ diff --git a/ATM33xx-5/include/reg/radio_synth_regs_core_macro.h b/ATM33xx-5/include/reg/radio_synth_regs_core_macro.h new file mode 100644 index 0000000..8e32294 --- /dev/null +++ b/ATM33xx-5/include/reg/radio_synth_regs_core_macro.h @@ -0,0 +1,2185 @@ +/* */ +/* File: radio_synth_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic radio_synth_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_RADIO_SYNTH_REGS_CORE_H__ +#define __REG_RADIO_SYNTH_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup RADIO_SYNTH_REGS_CORE radio_synth_regs_core + * @ingroup AT_REG + * @brief radio_synth_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::radio_synth_synth_ctrl_0 */ +/** + * @defgroup radio_synth_regs_core_synth_ctrl_0 synth_ctrl_0 + * @brief Synth over-rides and analog adjustments definitions. + * @{ + */ +#ifndef __RADIO_SYNTH_SYNTH_CTRL_0_MACRO__ +#define __RADIO_SYNTH_SYNTH_CTRL_0_MACRO__ + +/* macros for field disableSynthAnalog */ +/** + * @defgroup radio_synth_regs_core_disableSynthAnalog_field disableSynthAnalog_field + * @brief macros for field disableSynthAnalog + * @details disables the analog part of the Synthesizer + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLESYNTHANALOG__SHIFT 0 +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLESYNTHANALOG__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLESYNTHANALOG__MASK 0x00000001U +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLESYNTHANALOG__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLESYNTHANALOG__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLESYNTHANALOG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLESYNTHANALOG__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLESYNTHANALOG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLESYNTHANALOG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLESYNTHANALOG__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field disableVco */ +/** + * @defgroup radio_synth_regs_core_disableVco_field disableVco_field + * @brief macros for field disableVco + * @details disables the VCO + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLEVCO__SHIFT 1 +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLEVCO__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLEVCO__MASK 0x00000002U +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLEVCO__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLEVCO__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLEVCO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLEVCO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLEVCO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLEVCO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLEVCO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field disableCp */ +/** + * @defgroup radio_synth_regs_core_disableCp_field disableCp_field + * @brief macros for field disableCp + * @details disables the Charge Pump + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLECP__SHIFT 2 +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLECP__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLECP__MASK 0x00000004U +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLECP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLECP__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLECP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLECP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLECP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLECP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLECP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field disableTxmodHF */ +/** + * @defgroup radio_synth_regs_core_disableTxmodHF_field disableTxmodHF_field + * @brief macros for field disableTxmodHF + * @details disables the High Frequency Tx Modulation + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLETXMODHF__SHIFT 3 +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLETXMODHF__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLETXMODHF__MASK 0x00000008U +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLETXMODHF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLETXMODHF__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLETXMODHF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLETXMODHF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLETXMODHF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLETXMODHF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLETXMODHF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field disableTxmodLF */ +/** + * @defgroup radio_synth_regs_core_disableTxmodLF_field disableTxmodLF_field + * @brief macros for field disableTxmodLF + * @details disables the Low Frequency Tx Modulation + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLETXMODLF__SHIFT 4 +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLETXMODLF__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLETXMODLF__MASK 0x00000010U +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLETXMODLF__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLETXMODLF__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLETXMODLF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLETXMODLF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLETXMODLF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLETXMODLF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLETXMODLF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field disableSDM */ +/** + * @defgroup radio_synth_regs_core_disableSDM_field disableSDM_field + * @brief macros for field disableSDM + * @details disables the Sigma-Delta Modulator + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLESDM__SHIFT 5 +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLESDM__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLESDM__MASK 0x00000020U +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLESDM__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLESDM__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLESDM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLESDM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLESDM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLESDM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define RADIO_SYNTH_SYNTH_CTRL_0__DISABLESDM__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field chanovr */ +/** + * @defgroup radio_synth_regs_core_chanovr_field chanovr_field + * @brief macros for field chanovr + * @details Enables channel override + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANOVR__SHIFT 6 +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANOVR__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANOVR__MASK 0x00000040U +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANOVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANOVR__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANOVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANOVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANOVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANOVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANOVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field chanint_8MHz */ +/** + * @defgroup radio_synth_regs_core_chanint_8MHz_field chanint_8MHz_field + * @brief macros for field chanint_8MHz + * @details Channel override integer part, for 8 MHz reference + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANINT_8MHZ__SHIFT 7 +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANINT_8MHZ__WIDTH 9 +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANINT_8MHZ__MASK 0x0000ff80U +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANINT_8MHZ__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff80U) >> 7) +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANINT_8MHZ__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x0000ff80U) +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANINT_8MHZ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff80U) | (((uint32_t)(src) <<\ + 7) & 0x0000ff80U) +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANINT_8MHZ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x0000ff80U))) +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANINT_8MHZ__RESET_VALUE 0x00000096U +/** @} */ + +/* macros for field chanfrac_8MHz */ +/** + * @defgroup radio_synth_regs_core_chanfrac_8MHz_field chanfrac_8MHz_field + * @brief macros for field chanfrac_8MHz + * @details Channel override fractional part, for 8 MHz reference + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANFRAC_8MHZ__SHIFT 16 +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANFRAC_8MHZ__WIDTH 15 +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANFRAC_8MHZ__MASK 0x7fff0000U +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANFRAC_8MHZ__READ(src) \ + (((uint32_t)(src)\ + & 0x7fff0000U) >> 16) +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANFRAC_8MHZ__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x7fff0000U) +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANFRAC_8MHZ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7fff0000U) | (((uint32_t)(src) <<\ + 16) & 0x7fff0000U) +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANFRAC_8MHZ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x7fff0000U))) +#define RADIO_SYNTH_SYNTH_CTRL_0__CHANFRAC_8MHZ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field alwaysShortR */ +/** + * @defgroup radio_synth_regs_core_alwaysShortR_field alwaysShortR_field + * @brief macros for field alwaysShortR + * @details always short large resistors + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_0__ALWAYSSHORTR__SHIFT 31 +#define RADIO_SYNTH_SYNTH_CTRL_0__ALWAYSSHORTR__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_0__ALWAYSSHORTR__MASK 0x80000000U +#define RADIO_SYNTH_SYNTH_CTRL_0__ALWAYSSHORTR__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO_SYNTH_SYNTH_CTRL_0__ALWAYSSHORTR__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define RADIO_SYNTH_SYNTH_CTRL_0__ALWAYSSHORTR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define RADIO_SYNTH_SYNTH_CTRL_0__ALWAYSSHORTR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADIO_SYNTH_SYNTH_CTRL_0__ALWAYSSHORTR__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define RADIO_SYNTH_SYNTH_CTRL_0__ALWAYSSHORTR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define RADIO_SYNTH_SYNTH_CTRL_0__ALWAYSSHORTR__RESET_VALUE 0x00000000U +/** @} */ +#define RADIO_SYNTH_SYNTH_CTRL_0__TYPE uint32_t +#define RADIO_SYNTH_SYNTH_CTRL_0__READ 0xffffffffU +#define RADIO_SYNTH_SYNTH_CTRL_0__WRITE 0xffffffffU +#define RADIO_SYNTH_SYNTH_CTRL_0__PRESERVED 0x00000000U +#define RADIO_SYNTH_SYNTH_CTRL_0__RESET_VALUE 0x00004b00U + +#endif /* __RADIO_SYNTH_SYNTH_CTRL_0_MACRO__ */ + +/** @} end of synth_ctrl_0 */ + +/* macros for BlueprintGlobalNameSpace::radio_synth_synth_ctrl_1 */ +/** + * @defgroup radio_synth_regs_core_synth_ctrl_1 synth_ctrl_1 + * @brief Synth monitor and override modes definitions. + * @{ + */ +#ifndef __RADIO_SYNTH_SYNTH_CTRL_1_MACRO__ +#define __RADIO_SYNTH_SYNTH_CTRL_1_MACRO__ + +/* macros for field atbsel */ +/** + * @defgroup radio_synth_regs_core_atbsel_field atbsel_field + * @brief macros for field atbsel + * @details analog test bus select. 0->Disconnect. 1->Control voltage. 2->VCO current source gate voltage, set by AGC. 3->VCO inductor center tap. 4->VCO core top (PMOS sources). 5->vdd_vco. 6->mod varactor gate bias. 7->mod RDAC top IR voltage. 8->mod voltage. 9-15->gnd + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_1__ATBSEL__SHIFT 0 +#define RADIO_SYNTH_SYNTH_CTRL_1__ATBSEL__WIDTH 4 +#define RADIO_SYNTH_SYNTH_CTRL_1__ATBSEL__MASK 0x0000000fU +#define RADIO_SYNTH_SYNTH_CTRL_1__ATBSEL__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define RADIO_SYNTH_SYNTH_CTRL_1__ATBSEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define RADIO_SYNTH_SYNTH_CTRL_1__ATBSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define RADIO_SYNTH_SYNTH_CTRL_1__ATBSEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define RADIO_SYNTH_SYNTH_CTRL_1__ATBSEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field monitorVc */ +/** + * @defgroup radio_synth_regs_core_monitorVc_field monitorVc_field + * @brief macros for field monitorVc + * @details modify the FSM to monitor the control voltage + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_1__MONITORVC__SHIFT 4 +#define RADIO_SYNTH_SYNTH_CTRL_1__MONITORVC__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_1__MONITORVC__MASK 0x00000010U +#define RADIO_SYNTH_SYNTH_CTRL_1__MONITORVC__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONITORVC__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONITORVC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONITORVC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONITORVC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONITORVC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONITORVC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field monAlarmCountMax */ +/** + * @defgroup radio_synth_regs_core_monAlarmCountMax_field monAlarmCountMax_field + * @brief macros for field monAlarmCountMax + * @details in FSM monitor Vc mode, max number of alarm events before it takes action + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_1__MONALARMCOUNTMAX__SHIFT 5 +#define RADIO_SYNTH_SYNTH_CTRL_1__MONALARMCOUNTMAX__WIDTH 2 +#define RADIO_SYNTH_SYNTH_CTRL_1__MONALARMCOUNTMAX__MASK 0x00000060U +#define RADIO_SYNTH_SYNTH_CTRL_1__MONALARMCOUNTMAX__READ(src) \ + (((uint32_t)(src)\ + & 0x00000060U) >> 5) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONALARMCOUNTMAX__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000060U) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONALARMCOUNTMAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000060U) | (((uint32_t)(src) <<\ + 5) & 0x00000060U) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONALARMCOUNTMAX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000060U))) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONALARMCOUNTMAX__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field monStateLength_SteadyState_x4u */ +/** + * @defgroup radio_synth_regs_core_monStateLength_SteadyState_x4u_field monStateLength_SteadyState_x4u_field + * @brief macros for field monStateLength_SteadyState_x4u + * @details in FSM monitor Vc mode, time interval between successive Vc checks + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_1__MONSTATELENGTH_STEADYSTATE_X4U__SHIFT 7 +#define RADIO_SYNTH_SYNTH_CTRL_1__MONSTATELENGTH_STEADYSTATE_X4U__WIDTH 3 +#define RADIO_SYNTH_SYNTH_CTRL_1__MONSTATELENGTH_STEADYSTATE_X4U__MASK \ + 0x00000380U +#define RADIO_SYNTH_SYNTH_CTRL_1__MONSTATELENGTH_STEADYSTATE_X4U__READ(src) \ + (((uint32_t)(src)\ + & 0x00000380U) >> 7) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONSTATELENGTH_STEADYSTATE_X4U__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000380U) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONSTATELENGTH_STEADYSTATE_X4U__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000380U) | (((uint32_t)(src) <<\ + 7) & 0x00000380U) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONSTATELENGTH_STEADYSTATE_X4U__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000380U))) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONSTATELENGTH_STEADYSTATE_X4U__RESET_VALUE \ + 0x00000004U +/** @} */ + +/* macros for field monVcrefHi */ +/** + * @defgroup radio_synth_regs_core_monVcrefHi_field monVcrefHi_field + * @brief macros for field monVcrefHi + * @details in FSM monitor Vc mode, adjusts the high threshold of the control voltage. 0 is the lowest threshold + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_1__MONVCREFHI__SHIFT 10 +#define RADIO_SYNTH_SYNTH_CTRL_1__MONVCREFHI__WIDTH 2 +#define RADIO_SYNTH_SYNTH_CTRL_1__MONVCREFHI__MASK 0x00000c00U +#define RADIO_SYNTH_SYNTH_CTRL_1__MONVCREFHI__READ(src) \ + (((uint32_t)(src)\ + & 0x00000c00U) >> 10) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONVCREFHI__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000c00U) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONVCREFHI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000c00U) | (((uint32_t)(src) <<\ + 10) & 0x00000c00U) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONVCREFHI__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000c00U))) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONVCREFHI__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field monVcrefLo */ +/** + * @defgroup radio_synth_regs_core_monVcrefLo_field monVcrefLo_field + * @brief macros for field monVcrefLo + * @details in FSM monitor Vc mode, adjusts the low threshold of the control voltage. 0 is the lowest threshold. 2 is the voltage in the inductor center tap. + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_1__MONVCREFLO__SHIFT 12 +#define RADIO_SYNTH_SYNTH_CTRL_1__MONVCREFLO__WIDTH 2 +#define RADIO_SYNTH_SYNTH_CTRL_1__MONVCREFLO__MASK 0x00003000U +#define RADIO_SYNTH_SYNTH_CTRL_1__MONVCREFLO__READ(src) \ + (((uint32_t)(src)\ + & 0x00003000U) >> 12) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONVCREFLO__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00003000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONVCREFLO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((uint32_t)(src) <<\ + 12) & 0x00003000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONVCREFLO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00003000U))) +#define RADIO_SYNTH_SYNTH_CTRL_1__MONVCREFLO__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field overrideFsm */ +/** + * @defgroup radio_synth_regs_core_overrideFsm_field overrideFsm_field + * @brief macros for field overrideFsm + * @details override the FSM + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_1__OVERRIDEFSM__SHIFT 14 +#define RADIO_SYNTH_SYNTH_CTRL_1__OVERRIDEFSM__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_1__OVERRIDEFSM__MASK 0x00004000U +#define RADIO_SYNTH_SYNTH_CTRL_1__OVERRIDEFSM__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define RADIO_SYNTH_SYNTH_CTRL_1__OVERRIDEFSM__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__OVERRIDEFSM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__OVERRIDEFSM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define RADIO_SYNTH_SYNTH_CTRL_1__OVERRIDEFSM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define RADIO_SYNTH_SYNTH_CTRL_1__OVERRIDEFSM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define RADIO_SYNTH_SYNTH_CTRL_1__OVERRIDEFSM__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field vcoCaps_ov */ +/** + * @defgroup radio_synth_regs_core_vcoCaps_ov_field vcoCaps_ov_field + * @brief macros for field vcoCaps_ov + * @details in override mode, the VCO capacitor setting + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_1__VCOCAPS_OV__SHIFT 15 +#define RADIO_SYNTH_SYNTH_CTRL_1__VCOCAPS_OV__WIDTH 7 +#define RADIO_SYNTH_SYNTH_CTRL_1__VCOCAPS_OV__MASK 0x003f8000U +#define RADIO_SYNTH_SYNTH_CTRL_1__VCOCAPS_OV__READ(src) \ + (((uint32_t)(src)\ + & 0x003f8000U) >> 15) +#define RADIO_SYNTH_SYNTH_CTRL_1__VCOCAPS_OV__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x003f8000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__VCOCAPS_OV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f8000U) | (((uint32_t)(src) <<\ + 15) & 0x003f8000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__VCOCAPS_OV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x003f8000U))) +#define RADIO_SYNTH_SYNTH_CTRL_1__VCOCAPS_OV__RESET_VALUE 0x00000040U +/** @} */ + +/* macros for field pinVc_ov */ +/** + * @defgroup radio_synth_regs_core_pinVc_ov_field pinVc_ov_field + * @brief macros for field pinVc_ov + * @details in override mode, pinVc + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_1__PINVC_OV__SHIFT 22 +#define RADIO_SYNTH_SYNTH_CTRL_1__PINVC_OV__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_1__PINVC_OV__MASK 0x00400000U +#define RADIO_SYNTH_SYNTH_CTRL_1__PINVC_OV__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define RADIO_SYNTH_SYNTH_CTRL_1__PINVC_OV__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__PINVC_OV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__PINVC_OV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define RADIO_SYNTH_SYNTH_CTRL_1__PINVC_OV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define RADIO_SYNTH_SYNTH_CTRL_1__PINVC_OV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define RADIO_SYNTH_SYNTH_CTRL_1__PINVC_OV__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field shortR_ov */ +/** + * @defgroup radio_synth_regs_core_shortR_ov_field shortR_ov_field + * @brief macros for field shortR_ov + * @details in override mode, short the large resistors + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_1__SHORTR_OV__SHIFT 23 +#define RADIO_SYNTH_SYNTH_CTRL_1__SHORTR_OV__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_1__SHORTR_OV__MASK 0x00800000U +#define RADIO_SYNTH_SYNTH_CTRL_1__SHORTR_OV__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define RADIO_SYNTH_SYNTH_CTRL_1__SHORTR_OV__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__SHORTR_OV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__SHORTR_OV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define RADIO_SYNTH_SYNTH_CTRL_1__SHORTR_OV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define RADIO_SYNTH_SYNTH_CTRL_1__SHORTR_OV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define RADIO_SYNTH_SYNTH_CTRL_1__SHORTR_OV__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field divRst_ov */ +/** + * @defgroup radio_synth_regs_core_divRst_ov_field divRst_ov_field + * @brief macros for field divRst_ov + * @details in override mode, divider Reset + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_1__DIVRST_OV__SHIFT 24 +#define RADIO_SYNTH_SYNTH_CTRL_1__DIVRST_OV__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_1__DIVRST_OV__MASK 0x01000000U +#define RADIO_SYNTH_SYNTH_CTRL_1__DIVRST_OV__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define RADIO_SYNTH_SYNTH_CTRL_1__DIVRST_OV__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__DIVRST_OV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__DIVRST_OV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define RADIO_SYNTH_SYNTH_CTRL_1__DIVRST_OV__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define RADIO_SYNTH_SYNTH_CTRL_1__DIVRST_OV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define RADIO_SYNTH_SYNTH_CTRL_1__DIVRST_OV__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pfdRst_ov */ +/** + * @defgroup radio_synth_regs_core_pfdRst_ov_field pfdRst_ov_field + * @brief macros for field pfdRst_ov + * @details in override mode, reset pfd + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_1__PFDRST_OV__SHIFT 25 +#define RADIO_SYNTH_SYNTH_CTRL_1__PFDRST_OV__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_1__PFDRST_OV__MASK 0x02000000U +#define RADIO_SYNTH_SYNTH_CTRL_1__PFDRST_OV__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define RADIO_SYNTH_SYNTH_CTRL_1__PFDRST_OV__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__PFDRST_OV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__PFDRST_OV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define RADIO_SYNTH_SYNTH_CTRL_1__PFDRST_OV__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define RADIO_SYNTH_SYNTH_CTRL_1__PFDRST_OV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define RADIO_SYNTH_SYNTH_CTRL_1__PFDRST_OV__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enSd_ov */ +/** + * @defgroup radio_synth_regs_core_enSd_ov_field enSd_ov_field + * @brief macros for field enSd_ov + * @details in override mode, enable Sigma-Delta Modulator + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_1__ENSD_OV__SHIFT 26 +#define RADIO_SYNTH_SYNTH_CTRL_1__ENSD_OV__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_1__ENSD_OV__MASK 0x04000000U +#define RADIO_SYNTH_SYNTH_CTRL_1__ENSD_OV__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define RADIO_SYNTH_SYNTH_CTRL_1__ENSD_OV__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__ENSD_OV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__ENSD_OV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define RADIO_SYNTH_SYNTH_CTRL_1__ENSD_OV__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define RADIO_SYNTH_SYNTH_CTRL_1__ENSD_OV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define RADIO_SYNTH_SYNTH_CTRL_1__ENSD_OV__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field divEnForce */ +/** + * @defgroup radio_synth_regs_core_divEnForce_field divEnForce_field + * @brief macros for field divEnForce + * @details Forces the divider to be always enabled + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_1__DIVENFORCE__SHIFT 27 +#define RADIO_SYNTH_SYNTH_CTRL_1__DIVENFORCE__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_1__DIVENFORCE__MASK 0x08000000U +#define RADIO_SYNTH_SYNTH_CTRL_1__DIVENFORCE__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define RADIO_SYNTH_SYNTH_CTRL_1__DIVENFORCE__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__DIVENFORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__DIVENFORCE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define RADIO_SYNTH_SYNTH_CTRL_1__DIVENFORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define RADIO_SYNTH_SYNTH_CTRL_1__DIVENFORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define RADIO_SYNTH_SYNTH_CTRL_1__DIVENFORCE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field synthonForce */ +/** + * @defgroup radio_synth_regs_core_synthonForce_field synthonForce_field + * @brief macros for field synthonForce + * @details Forces synthon high. Used for testing + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_1__SYNTHONFORCE__SHIFT 28 +#define RADIO_SYNTH_SYNTH_CTRL_1__SYNTHONFORCE__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_1__SYNTHONFORCE__MASK 0x10000000U +#define RADIO_SYNTH_SYNTH_CTRL_1__SYNTHONFORCE__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define RADIO_SYNTH_SYNTH_CTRL_1__SYNTHONFORCE__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__SYNTHONFORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__SYNTHONFORCE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define RADIO_SYNTH_SYNTH_CTRL_1__SYNTHONFORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define RADIO_SYNTH_SYNTH_CTRL_1__SYNTHONFORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define RADIO_SYNTH_SYNTH_CTRL_1__SYNTHONFORCE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field openLoopSS */ +/** + * @defgroup radio_synth_regs_core_openLoopSS_field openLoopSS_field + * @brief macros for field openLoopSS + * @details open loop in steady state after locking during TX, primarily intended for testing HF modulation path + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_1__OPENLOOPSS__SHIFT 29 +#define RADIO_SYNTH_SYNTH_CTRL_1__OPENLOOPSS__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_1__OPENLOOPSS__MASK 0x20000000U +#define RADIO_SYNTH_SYNTH_CTRL_1__OPENLOOPSS__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define RADIO_SYNTH_SYNTH_CTRL_1__OPENLOOPSS__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__OPENLOOPSS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__OPENLOOPSS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define RADIO_SYNTH_SYNTH_CTRL_1__OPENLOOPSS__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define RADIO_SYNTH_SYNTH_CTRL_1__OPENLOOPSS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define RADIO_SYNTH_SYNTH_CTRL_1__OPENLOOPSS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field spareExt */ +/** + * @defgroup radio_synth_regs_core_spareExt_field spareExt_field + * @brief macros for field spareExt + * @details synth local register internal spare bits taken out as pins to synthDigital + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_1__SPAREEXT__SHIFT 30 +#define RADIO_SYNTH_SYNTH_CTRL_1__SPAREEXT__WIDTH 2 +#define RADIO_SYNTH_SYNTH_CTRL_1__SPAREEXT__MASK 0xc0000000U +#define RADIO_SYNTH_SYNTH_CTRL_1__SPAREEXT__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define RADIO_SYNTH_SYNTH_CTRL_1__SPAREEXT__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__SPAREEXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define RADIO_SYNTH_SYNTH_CTRL_1__SPAREEXT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define RADIO_SYNTH_SYNTH_CTRL_1__SPAREEXT__RESET_VALUE 0x00000000U +/** @} */ +#define RADIO_SYNTH_SYNTH_CTRL_1__TYPE uint32_t +#define RADIO_SYNTH_SYNTH_CTRL_1__READ 0xffffffffU +#define RADIO_SYNTH_SYNTH_CTRL_1__WRITE 0xffffffffU +#define RADIO_SYNTH_SYNTH_CTRL_1__PRESERVED 0x00000000U +#define RADIO_SYNTH_SYNTH_CTRL_1__RESET_VALUE 0x00202a40U + +#endif /* __RADIO_SYNTH_SYNTH_CTRL_1_MACRO__ */ + +/** @} end of synth_ctrl_1 */ + +/* macros for BlueprintGlobalNameSpace::radio_synth_synth_ctrl_2 */ +/** + * @defgroup radio_synth_regs_core_synth_ctrl_2 synth_ctrl_2 + * @brief Synth txmod data override, RX LOGen, PA and PA LDO enable controls and overrides, TX cal options definitions. + * @{ + */ +#ifndef __RADIO_SYNTH_SYNTH_CTRL_2_MACRO__ +#define __RADIO_SYNTH_SYNTH_CTRL_2_MACRO__ + +/* macros for field txmodDataOvr */ +/** + * @defgroup radio_synth_regs_core_txmodDataOvr_field txmodDataOvr_field + * @brief macros for field txmodDataOvr + * @details set to override the txmodData used in the HF modulation path (VCO) + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__TXMODDATAOVR__SHIFT 0 +#define RADIO_SYNTH_SYNTH_CTRL_2__TXMODDATAOVR__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_2__TXMODDATAOVR__MASK 0x00000001U +#define RADIO_SYNTH_SYNTH_CTRL_2__TXMODDATAOVR__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RADIO_SYNTH_SYNTH_CTRL_2__TXMODDATAOVR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RADIO_SYNTH_SYNTH_CTRL_2__TXMODDATAOVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define RADIO_SYNTH_SYNTH_CTRL_2__TXMODDATAOVR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define RADIO_SYNTH_SYNTH_CTRL_2__TXMODDATAOVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define RADIO_SYNTH_SYNTH_CTRL_2__TXMODDATAOVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define RADIO_SYNTH_SYNTH_CTRL_2__TXMODDATAOVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field txmodData */ +/** + * @defgroup radio_synth_regs_core_txmodData_field txmodData_field + * @brief macros for field txmodData + * @details txmodData static bits, effective in the HF modulatin path when txmodDataOvr=1 + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__TXMODDATA__SHIFT 1 +#define RADIO_SYNTH_SYNTH_CTRL_2__TXMODDATA__WIDTH 7 +#define RADIO_SYNTH_SYNTH_CTRL_2__TXMODDATA__MASK 0x000000feU +#define RADIO_SYNTH_SYNTH_CTRL_2__TXMODDATA__READ(src) \ + (((uint32_t)(src)\ + & 0x000000feU) >> 1) +#define RADIO_SYNTH_SYNTH_CTRL_2__TXMODDATA__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x000000feU) +#define RADIO_SYNTH_SYNTH_CTRL_2__TXMODDATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000feU) | (((uint32_t)(src) <<\ + 1) & 0x000000feU) +#define RADIO_SYNTH_SYNTH_CTRL_2__TXMODDATA__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000000feU))) +#define RADIO_SYNTH_SYNTH_CTRL_2__TXMODDATA__RESET_VALUE 0x00000020U +/** @} */ + +/* macros for field lockTestEn */ +/** + * @defgroup radio_synth_regs_core_lockTestEn_field lockTestEn_field + * @brief macros for field lockTestEn + * @details enables the lock detector + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__LOCKTESTEN__SHIFT 8 +#define RADIO_SYNTH_SYNTH_CTRL_2__LOCKTESTEN__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_2__LOCKTESTEN__MASK 0x00000100U +#define RADIO_SYNTH_SYNTH_CTRL_2__LOCKTESTEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define RADIO_SYNTH_SYNTH_CTRL_2__LOCKTESTEN__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define RADIO_SYNTH_SYNTH_CTRL_2__LOCKTESTEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define RADIO_SYNTH_SYNTH_CTRL_2__LOCKTESTEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define RADIO_SYNTH_SYNTH_CTRL_2__LOCKTESTEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define RADIO_SYNTH_SYNTH_CTRL_2__LOCKTESTEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define RADIO_SYNTH_SYNTH_CTRL_2__LOCKTESTEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field disableVcoModClk */ +/** + * @defgroup radio_synth_regs_core_disableVcoModClk_field disableVcoModClk_field + * @brief macros for field disableVcoModClk + * @details disables the VCO modulation clock, which retimes the data in the HF modulation path + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__DISABLEVCOMODCLK__SHIFT 9 +#define RADIO_SYNTH_SYNTH_CTRL_2__DISABLEVCOMODCLK__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_2__DISABLEVCOMODCLK__MASK 0x00000200U +#define RADIO_SYNTH_SYNTH_CTRL_2__DISABLEVCOMODCLK__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define RADIO_SYNTH_SYNTH_CTRL_2__DISABLEVCOMODCLK__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define RADIO_SYNTH_SYNTH_CTRL_2__DISABLEVCOMODCLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define RADIO_SYNTH_SYNTH_CTRL_2__DISABLEVCOMODCLK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define RADIO_SYNTH_SYNTH_CTRL_2__DISABLEVCOMODCLK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define RADIO_SYNTH_SYNTH_CTRL_2__DISABLEVCOMODCLK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define RADIO_SYNTH_SYNTH_CTRL_2__DISABLEVCOMODCLK__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rxlo_combineIQ */ +/** + * @defgroup radio_synth_regs_core_rxlo_combineIQ_field rxlo_combineIQ_field + * @brief macros for field rxlo_combineIQ + * @details if =1, when in low-power dual-conversion mode, keeps both I & Q paths enabled in RXLO + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_COMBINEIQ__SHIFT 10 +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_COMBINEIQ__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_COMBINEIQ__MASK 0x00000400U +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_COMBINEIQ__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_COMBINEIQ__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_COMBINEIQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_COMBINEIQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_COMBINEIQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_COMBINEIQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_COMBINEIQ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field overrideRxLOgen */ +/** + * @defgroup radio_synth_regs_core_overrideRxLOgen_field overrideRxLOgen_field + * @brief macros for field overrideRxLOgen + * @details if set, overrides the enable control bits of RXLOgen + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__OVERRIDERXLOGEN__SHIFT 11 +#define RADIO_SYNTH_SYNTH_CTRL_2__OVERRIDERXLOGEN__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_2__OVERRIDERXLOGEN__MASK 0x00000800U +#define RADIO_SYNTH_SYNTH_CTRL_2__OVERRIDERXLOGEN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define RADIO_SYNTH_SYNTH_CTRL_2__OVERRIDERXLOGEN__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define RADIO_SYNTH_SYNTH_CTRL_2__OVERRIDERXLOGEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define RADIO_SYNTH_SYNTH_CTRL_2__OVERRIDERXLOGEN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define RADIO_SYNTH_SYNTH_CTRL_2__OVERRIDERXLOGEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define RADIO_SYNTH_SYNTH_CTRL_2__OVERRIDERXLOGEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define RADIO_SYNTH_SYNTH_CTRL_2__OVERRIDERXLOGEN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rxlo_enIdual_ov */ +/** + * @defgroup radio_synth_regs_core_rxlo_enIdual_ov_field rxlo_enIdual_ov_field + * @brief macros for field rxlo_enIdual_ov + * @details in RXLOgen override mode, the setting for enIdual + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENIDUAL_OV__SHIFT 12 +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENIDUAL_OV__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENIDUAL_OV__MASK 0x00001000U +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENIDUAL_OV__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENIDUAL_OV__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENIDUAL_OV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENIDUAL_OV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENIDUAL_OV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENIDUAL_OV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENIDUAL_OV__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rxlo_enQdual_ov */ +/** + * @defgroup radio_synth_regs_core_rxlo_enQdual_ov_field rxlo_enQdual_ov_field + * @brief macros for field rxlo_enQdual_ov + * @details in RXLOgen override mode, the setting for enQdual + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENQDUAL_OV__SHIFT 13 +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENQDUAL_OV__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENQDUAL_OV__MASK 0x00002000U +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENQDUAL_OV__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENQDUAL_OV__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENQDUAL_OV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENQDUAL_OV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENQDUAL_OV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENQDUAL_OV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENQDUAL_OV__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rxlo_ensinglelp_ov */ +/** + * @defgroup radio_synth_regs_core_rxlo_ensinglelp_ov_field rxlo_ensinglelp_ov_field + * @brief macros for field rxlo_ensinglelp_ov + * @details in RXLOgen override mode, the setting for ensinglelp + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENSINGLELP_OV__SHIFT 14 +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENSINGLELP_OV__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENSINGLELP_OV__MASK 0x00004000U +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENSINGLELP_OV__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENSINGLELP_OV__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENSINGLELP_OV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENSINGLELP_OV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENSINGLELP_OV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENSINGLELP_OV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENSINGLELP_OV__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rxlo_ensingle_ov */ +/** + * @defgroup radio_synth_regs_core_rxlo_ensingle_ov_field rxlo_ensingle_ov_field + * @brief macros for field rxlo_ensingle_ov + * @details in RXLOgen override mode, the setting for ensingle + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENSINGLE_OV__SHIFT 15 +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENSINGLE_OV__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENSINGLE_OV__MASK 0x00008000U +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENSINGLE_OV__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENSINGLE_OV__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENSINGLE_OV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENSINGLE_OV__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENSINGLE_OV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENSINGLE_OV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define RADIO_SYNTH_SYNTH_CTRL_2__RXLO_ENSINGLE_OV__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field disableRxLOBuf */ +/** + * @defgroup radio_synth_regs_core_disableRxLOBuf_field disableRxLOBuf_field + * @brief macros for field disableRxLOBuf + * @details Disables RX LO buffer + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__DISABLERXLOBUF__SHIFT 16 +#define RADIO_SYNTH_SYNTH_CTRL_2__DISABLERXLOBUF__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_2__DISABLERXLOBUF__MASK 0x00010000U +#define RADIO_SYNTH_SYNTH_CTRL_2__DISABLERXLOBUF__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define RADIO_SYNTH_SYNTH_CTRL_2__DISABLERXLOBUF__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__DISABLERXLOBUF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__DISABLERXLOBUF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define RADIO_SYNTH_SYNTH_CTRL_2__DISABLERXLOBUF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define RADIO_SYNTH_SYNTH_CTRL_2__DISABLERXLOBUF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define RADIO_SYNTH_SYNTH_CTRL_2__DISABLERXLOBUF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pa_bypassDuty */ +/** + * @defgroup radio_synth_regs_core_pa_bypassDuty_field pa_bypassDuty_field + * @brief macros for field pa_bypassDuty + * @details if set, bypasses the duty cycle control in PA + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__PA_BYPASSDUTY__SHIFT 17 +#define RADIO_SYNTH_SYNTH_CTRL_2__PA_BYPASSDUTY__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_2__PA_BYPASSDUTY__MASK 0x00020000U +#define RADIO_SYNTH_SYNTH_CTRL_2__PA_BYPASSDUTY__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define RADIO_SYNTH_SYNTH_CTRL_2__PA_BYPASSDUTY__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__PA_BYPASSDUTY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__PA_BYPASSDUTY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define RADIO_SYNTH_SYNTH_CTRL_2__PA_BYPASSDUTY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define RADIO_SYNTH_SYNTH_CTRL_2__PA_BYPASSDUTY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define RADIO_SYNTH_SYNTH_CTRL_2__PA_BYPASSDUTY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enPAdriverOvrValue */ +/** + * @defgroup radio_synth_regs_core_enPAdriverOvrValue_field enPAdriverOvrValue_field + * @brief macros for field enPAdriverOvrValue + * @details Enable PA driver override value when enPAdriver_sel = 3 + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPADRIVEROVRVALUE__SHIFT 18 +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPADRIVEROVRVALUE__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPADRIVEROVRVALUE__MASK 0x00040000U +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPADRIVEROVRVALUE__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPADRIVEROVRVALUE__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPADRIVEROVRVALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPADRIVEROVRVALUE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPADRIVEROVRVALUE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPADRIVEROVRVALUE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPADRIVEROVRVALUE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enPAdriver_sel */ +/** + * @defgroup radio_synth_regs_core_enPAdriver_sel_field enPAdriver_sel_field + * @brief macros for field enPAdriver_sel + * @details Select how PA driver is controlled, 0 - txon, 1 - synthon, 2 - paon, 3 - use enPAdriverOvrValue + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPADRIVER_SEL__SHIFT 19 +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPADRIVER_SEL__WIDTH 2 +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPADRIVER_SEL__MASK 0x00180000U +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPADRIVER_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00180000U) >> 19) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPADRIVER_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00180000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPADRIVER_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((uint32_t)(src) <<\ + 19) & 0x00180000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPADRIVER_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00180000U))) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPADRIVER_SEL__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field enPAOvrValue */ +/** + * @defgroup radio_synth_regs_core_enPAOvrValue_field enPAOvrValue_field + * @brief macros for field enPAOvrValue + * @details Enable PA output stage override value when enPA_sel = 3 + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPAOVRVALUE__SHIFT 21 +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPAOVRVALUE__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPAOVRVALUE__MASK 0x00200000U +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPAOVRVALUE__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPAOVRVALUE__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPAOVRVALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPAOVRVALUE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPAOVRVALUE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPAOVRVALUE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPAOVRVALUE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enPA_sel */ +/** + * @defgroup radio_synth_regs_core_enPA_sel_field enPA_sel_field + * @brief macros for field enPA_sel + * @details Select how PA output stage is controlled, 0 - txon, 1 - synthon, 2 - paon, 3 - use enPAOvrValue + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPA_SEL__SHIFT 22 +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPA_SEL__WIDTH 2 +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPA_SEL__MASK 0x00c00000U +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPA_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00c00000U) >> 22) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPA_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00c00000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPA_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00c00000U) | (((uint32_t)(src) <<\ + 22) & 0x00c00000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPA_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00c00000U))) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPA_SEL__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field enPAldoOvrValue */ +/** + * @defgroup radio_synth_regs_core_enPAldoOvrValue_field enPAldoOvrValue_field + * @brief macros for field enPAldoOvrValue + * @details Enable PA output stage LDO override value when enPAldo_sel = 3 + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPALDOOVRVALUE__SHIFT 24 +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPALDOOVRVALUE__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPALDOOVRVALUE__MASK 0x01000000U +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPALDOOVRVALUE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPALDOOVRVALUE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPALDOOVRVALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPALDOOVRVALUE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPALDOOVRVALUE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPALDOOVRVALUE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPALDOOVRVALUE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enPAldo_sel */ +/** + * @defgroup radio_synth_regs_core_enPAldo_sel_field enPAldo_sel_field + * @brief macros for field enPAldo_sel + * @details Select how PA output stage LDO is controlled, 0 - txon, 1 - synthon, 2 - paon, 3 - use enPAldoValue + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPALDO_SEL__SHIFT 25 +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPALDO_SEL__WIDTH 2 +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPALDO_SEL__MASK 0x06000000U +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPALDO_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x06000000U) >> 25) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPALDO_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x06000000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPALDO_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x06000000U) | (((uint32_t)(src) <<\ + 25) & 0x06000000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPALDO_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x06000000U))) +#define RADIO_SYNTH_SYNTH_CTRL_2__ENPALDO_SEL__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field vcoTuneMargin_x16M */ +/** + * @defgroup radio_synth_regs_core_vcoTuneMargin_x16M_field vcoTuneMargin_x16M_field + * @brief macros for field vcoTuneMargin_x16M + * @details Set target frequency for coarse bank search to (2480 + 16x) for TX and (2835 + 16x) for RX, where x is the value of this register + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__VCOTUNEMARGIN_X16M__SHIFT 27 +#define RADIO_SYNTH_SYNTH_CTRL_2__VCOTUNEMARGIN_X16M__WIDTH 3 +#define RADIO_SYNTH_SYNTH_CTRL_2__VCOTUNEMARGIN_X16M__MASK 0x38000000U +#define RADIO_SYNTH_SYNTH_CTRL_2__VCOTUNEMARGIN_X16M__READ(src) \ + (((uint32_t)(src)\ + & 0x38000000U) >> 27) +#define RADIO_SYNTH_SYNTH_CTRL_2__VCOTUNEMARGIN_X16M__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x38000000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__VCOTUNEMARGIN_X16M__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x38000000U) | (((uint32_t)(src) <<\ + 27) & 0x38000000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__VCOTUNEMARGIN_X16M__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x38000000U))) +#define RADIO_SYNTH_SYNTH_CTRL_2__VCOTUNEMARGIN_X16M__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field dontRoundUp_modGainCal */ +/** + * @defgroup radio_synth_regs_core_dontRoundUp_modGainCal_field dontRoundUp_modGainCal_field + * @brief macros for field dontRoundUp_modGainCal + * @details if set, state machine will not round-up when making final calculation of modGain_cal_result + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__DONTROUNDUP_MODGAINCAL__SHIFT 30 +#define RADIO_SYNTH_SYNTH_CTRL_2__DONTROUNDUP_MODGAINCAL__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_2__DONTROUNDUP_MODGAINCAL__MASK 0x40000000U +#define RADIO_SYNTH_SYNTH_CTRL_2__DONTROUNDUP_MODGAINCAL__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define RADIO_SYNTH_SYNTH_CTRL_2__DONTROUNDUP_MODGAINCAL__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__DONTROUNDUP_MODGAINCAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__DONTROUNDUP_MODGAINCAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define RADIO_SYNTH_SYNTH_CTRL_2__DONTROUNDUP_MODGAINCAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define RADIO_SYNTH_SYNTH_CTRL_2__DONTROUNDUP_MODGAINCAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define RADIO_SYNTH_SYNTH_CTRL_2__DONTROUNDUP_MODGAINCAL__RESET_VALUE \ + 0x00000000U +/** @} */ + +/* macros for field dontRoundUp_vcoCapsCal */ +/** + * @defgroup radio_synth_regs_core_dontRoundUp_vcoCapsCal_field dontRoundUp_vcoCapsCal_field + * @brief macros for field dontRoundUp_vcoCapsCal + * @details if set, state machine will not round-up when making final calculation of Bx and Cx values during VCO cap calibration + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_2__DONTROUNDUP_VCOCAPSCAL__SHIFT 31 +#define RADIO_SYNTH_SYNTH_CTRL_2__DONTROUNDUP_VCOCAPSCAL__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_2__DONTROUNDUP_VCOCAPSCAL__MASK 0x80000000U +#define RADIO_SYNTH_SYNTH_CTRL_2__DONTROUNDUP_VCOCAPSCAL__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO_SYNTH_SYNTH_CTRL_2__DONTROUNDUP_VCOCAPSCAL__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__DONTROUNDUP_VCOCAPSCAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define RADIO_SYNTH_SYNTH_CTRL_2__DONTROUNDUP_VCOCAPSCAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADIO_SYNTH_SYNTH_CTRL_2__DONTROUNDUP_VCOCAPSCAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define RADIO_SYNTH_SYNTH_CTRL_2__DONTROUNDUP_VCOCAPSCAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define RADIO_SYNTH_SYNTH_CTRL_2__DONTROUNDUP_VCOCAPSCAL__RESET_VALUE \ + 0x00000001U +/** @} */ +#define RADIO_SYNTH_SYNTH_CTRL_2__TYPE uint32_t +#define RADIO_SYNTH_SYNTH_CTRL_2__READ 0xffffffffU +#define RADIO_SYNTH_SYNTH_CTRL_2__WRITE 0xffffffffU +#define RADIO_SYNTH_SYNTH_CTRL_2__PRESERVED 0x00000000U +#define RADIO_SYNTH_SYNTH_CTRL_2__RESET_VALUE 0xa4900040U + +#endif /* __RADIO_SYNTH_SYNTH_CTRL_2_MACRO__ */ + +/** @} end of synth_ctrl_2 */ + +/* macros for BlueprintGlobalNameSpace::radio_synth_synth_ctrl_3 */ +/** + * @defgroup radio_synth_regs_core_synth_ctrl_3 synth_ctrl_3 + * @brief Synth txmod static bits definitions. + * @{ + */ +#ifndef __RADIO_SYNTH_SYNTH_CTRL_3_MACRO__ +#define __RADIO_SYNTH_SYNTH_CTRL_3_MACRO__ + +/* macros for field modVarSize_cal */ +/** + * @defgroup radio_synth_regs_core_modVarSize_cal_field modVarSize_cal_field + * @brief macros for field modVarSize_cal + * @details modulation varactor size to be used during modGain calibration + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARSIZE_CAL__SHIFT 0 +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARSIZE_CAL__WIDTH 4 +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARSIZE_CAL__MASK 0x0000000fU +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARSIZE_CAL__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARSIZE_CAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARSIZE_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARSIZE_CAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARSIZE_CAL__RESET_VALUE 0x0000000fU +/** @} */ + +/* macros for field modVarBias_1M */ +/** + * @defgroup radio_synth_regs_core_modVarBias_1M_field modVarBias_1M_field + * @brief macros for field modVarBias_1M + * @details modulation varactor gate bias voltage for 1Mbps rate + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARBIAS_1M__SHIFT 4 +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARBIAS_1M__WIDTH 4 +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARBIAS_1M__MASK 0x000000f0U +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARBIAS_1M__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARBIAS_1M__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x000000f0U) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARBIAS_1M__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARBIAS_1M__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARBIAS_1M__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field modBucketSize_1M */ +/** + * @defgroup radio_synth_regs_core_modBucketSize_1M_field modBucketSize_1M_field + * @brief macros for field modBucketSize_1M + * @details frequency bin size in 4MHz steps for modgain adjustment for 1Mbps rate + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_3__MODBUCKETSIZE_1M__SHIFT 8 +#define RADIO_SYNTH_SYNTH_CTRL_3__MODBUCKETSIZE_1M__WIDTH 5 +#define RADIO_SYNTH_SYNTH_CTRL_3__MODBUCKETSIZE_1M__MASK 0x00001f00U +#define RADIO_SYNTH_SYNTH_CTRL_3__MODBUCKETSIZE_1M__READ(src) \ + (((uint32_t)(src)\ + & 0x00001f00U) >> 8) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODBUCKETSIZE_1M__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00001f00U) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODBUCKETSIZE_1M__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((uint32_t)(src) <<\ + 8) & 0x00001f00U) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODBUCKETSIZE_1M__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00001f00U))) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODBUCKETSIZE_1M__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field modDelayHF_1M */ +/** + * @defgroup radio_synth_regs_core_modDelayHF_1M_field modDelayHF_1M_field + * @brief macros for field modDelayHF_1M + * @details if set, the data to the HF modulation path is delayed, otherwise the data to the LF modulation path is delayed + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_3__MODDELAYHF_1M__SHIFT 13 +#define RADIO_SYNTH_SYNTH_CTRL_3__MODDELAYHF_1M__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_3__MODDELAYHF_1M__MASK 0x00002000U +#define RADIO_SYNTH_SYNTH_CTRL_3__MODDELAYHF_1M__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODDELAYHF_1M__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODDELAYHF_1M__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODDELAYHF_1M__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODDELAYHF_1M__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODDELAYHF_1M__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODDELAYHF_1M__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field modRelPathDelay_1M */ +/** + * @defgroup radio_synth_regs_core_modRelPathDelay_1M_field modRelPathDelay_1M_field + * @brief macros for field modRelPathDelay_1M + * @details relative delay in cycles of the 16M clock, in the path determined by modDelayHF_1M + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_3__MODRELPATHDELAY_1M__SHIFT 14 +#define RADIO_SYNTH_SYNTH_CTRL_3__MODRELPATHDELAY_1M__WIDTH 3 +#define RADIO_SYNTH_SYNTH_CTRL_3__MODRELPATHDELAY_1M__MASK 0x0001c000U +#define RADIO_SYNTH_SYNTH_CTRL_3__MODRELPATHDELAY_1M__READ(src) \ + (((uint32_t)(src)\ + & 0x0001c000U) >> 14) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODRELPATHDELAY_1M__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0001c000U) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODRELPATHDELAY_1M__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((uint32_t)(src) <<\ + 14) & 0x0001c000U) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODRELPATHDELAY_1M__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0001c000U))) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODRELPATHDELAY_1M__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field modVarBias_2M */ +/** + * @defgroup radio_synth_regs_core_modVarBias_2M_field modVarBias_2M_field + * @brief macros for field modVarBias_2M + * @details modulation varactor gate bias voltage for 2Mbps rate + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARBIAS_2M__SHIFT 17 +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARBIAS_2M__WIDTH 4 +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARBIAS_2M__MASK 0x001e0000U +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARBIAS_2M__READ(src) \ + (((uint32_t)(src)\ + & 0x001e0000U) >> 17) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARBIAS_2M__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x001e0000U) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARBIAS_2M__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001e0000U) | (((uint32_t)(src) <<\ + 17) & 0x001e0000U) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARBIAS_2M__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x001e0000U))) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODVARBIAS_2M__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field modBucketSize_2M */ +/** + * @defgroup radio_synth_regs_core_modBucketSize_2M_field modBucketSize_2M_field + * @brief macros for field modBucketSize_2M + * @details frequency bin size in 4MHz steps for modgain adjustment for 2Mbps rate + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_3__MODBUCKETSIZE_2M__SHIFT 21 +#define RADIO_SYNTH_SYNTH_CTRL_3__MODBUCKETSIZE_2M__WIDTH 5 +#define RADIO_SYNTH_SYNTH_CTRL_3__MODBUCKETSIZE_2M__MASK 0x03e00000U +#define RADIO_SYNTH_SYNTH_CTRL_3__MODBUCKETSIZE_2M__READ(src) \ + (((uint32_t)(src)\ + & 0x03e00000U) >> 21) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODBUCKETSIZE_2M__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x03e00000U) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODBUCKETSIZE_2M__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03e00000U) | (((uint32_t)(src) <<\ + 21) & 0x03e00000U) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODBUCKETSIZE_2M__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x03e00000U))) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODBUCKETSIZE_2M__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field modDelayHF_2M */ +/** + * @defgroup radio_synth_regs_core_modDelayHF_2M_field modDelayHF_2M_field + * @brief macros for field modDelayHF_2M + * @details if set, the data to the HF modulation path is delayed, otherwise the data to the LF modulation path is delayed + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_3__MODDELAYHF_2M__SHIFT 26 +#define RADIO_SYNTH_SYNTH_CTRL_3__MODDELAYHF_2M__WIDTH 1 +#define RADIO_SYNTH_SYNTH_CTRL_3__MODDELAYHF_2M__MASK 0x04000000U +#define RADIO_SYNTH_SYNTH_CTRL_3__MODDELAYHF_2M__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODDELAYHF_2M__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODDELAYHF_2M__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODDELAYHF_2M__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODDELAYHF_2M__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODDELAYHF_2M__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODDELAYHF_2M__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field modRelPathDelay_2M */ +/** + * @defgroup radio_synth_regs_core_modRelPathDelay_2M_field modRelPathDelay_2M_field + * @brief macros for field modRelPathDelay_2M + * @details relative delay in cycles of the 16M clock, in the path determined by modDelayHF_2M + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_3__MODRELPATHDELAY_2M__SHIFT 27 +#define RADIO_SYNTH_SYNTH_CTRL_3__MODRELPATHDELAY_2M__WIDTH 3 +#define RADIO_SYNTH_SYNTH_CTRL_3__MODRELPATHDELAY_2M__MASK 0x38000000U +#define RADIO_SYNTH_SYNTH_CTRL_3__MODRELPATHDELAY_2M__READ(src) \ + (((uint32_t)(src)\ + & 0x38000000U) >> 27) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODRELPATHDELAY_2M__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x38000000U) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODRELPATHDELAY_2M__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x38000000U) | (((uint32_t)(src) <<\ + 27) & 0x38000000U) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODRELPATHDELAY_2M__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x38000000U))) +#define RADIO_SYNTH_SYNTH_CTRL_3__MODRELPATHDELAY_2M__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field txRate_hadm */ +/** + * @defgroup radio_synth_regs_core_txRate_hadm_field txRate_hadm_field + * @brief macros for field txRate_hadm + * @details value of txRate when in HADM mode; default is 2M rate + * @{ + */ +#define RADIO_SYNTH_SYNTH_CTRL_3__TXRATE_HADM__SHIFT 30 +#define RADIO_SYNTH_SYNTH_CTRL_3__TXRATE_HADM__WIDTH 2 +#define RADIO_SYNTH_SYNTH_CTRL_3__TXRATE_HADM__MASK 0xc0000000U +#define RADIO_SYNTH_SYNTH_CTRL_3__TXRATE_HADM__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define RADIO_SYNTH_SYNTH_CTRL_3__TXRATE_HADM__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define RADIO_SYNTH_SYNTH_CTRL_3__TXRATE_HADM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define RADIO_SYNTH_SYNTH_CTRL_3__TXRATE_HADM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define RADIO_SYNTH_SYNTH_CTRL_3__TXRATE_HADM__RESET_VALUE 0x00000001U +/** @} */ +#define RADIO_SYNTH_SYNTH_CTRL_3__TYPE uint32_t +#define RADIO_SYNTH_SYNTH_CTRL_3__READ 0xffffffffU +#define RADIO_SYNTH_SYNTH_CTRL_3__WRITE 0xffffffffU +#define RADIO_SYNTH_SYNTH_CTRL_3__PRESERVED 0x00000000U +#define RADIO_SYNTH_SYNTH_CTRL_3__RESET_VALUE 0x40f0078fU + +#endif /* __RADIO_SYNTH_SYNTH_CTRL_3_MACRO__ */ + +/** @} end of synth_ctrl_3 */ + +/* macros for BlueprintGlobalNameSpace::radio_synth_synth_readout */ +/** + * @defgroup radio_synth_regs_core_synth_readout synth_readout + * @brief Synth read-out bits definitions. + * @{ + */ +#ifndef __RADIO_SYNTH_SYNTH_READOUT_MACRO__ +#define __RADIO_SYNTH_SYNTH_READOUT_MACRO__ + +/* macros for field fsm_state */ +/** + * @defgroup radio_synth_regs_core_fsm_state_field fsm_state_field + * @brief macros for field fsm_state + * @details FSM output, the state + * @{ + */ +#define RADIO_SYNTH_SYNTH_READOUT__FSM_STATE__SHIFT 0 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_STATE__WIDTH 5 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_STATE__MASK 0x0000001fU +#define RADIO_SYNTH_SYNTH_READOUT__FSM_STATE__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_STATE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fsm_vcoCaps */ +/** + * @defgroup radio_synth_regs_core_fsm_vcoCaps_field fsm_vcoCaps_field + * @brief macros for field fsm_vcoCaps + * @details FSM output, the VCO cap setting + * @{ + */ +#define RADIO_SYNTH_SYNTH_READOUT__FSM_VCOCAPS__SHIFT 5 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_VCOCAPS__WIDTH 7 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_VCOCAPS__MASK 0x00000fe0U +#define RADIO_SYNTH_SYNTH_READOUT__FSM_VCOCAPS__READ(src) \ + (((uint32_t)(src)\ + & 0x00000fe0U) >> 5) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_VCOCAPS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fsm_divCapSearch */ +/** + * @defgroup radio_synth_regs_core_fsm_divCapSearch_field fsm_divCapSearch_field + * @brief macros for field fsm_divCapSearch + * @details FSM output, the divCapSearch signal + * @{ + */ +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVCAPSEARCH__SHIFT 12 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVCAPSEARCH__WIDTH 1 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVCAPSEARCH__MASK 0x00001000U +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVCAPSEARCH__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVCAPSEARCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVCAPSEARCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVCAPSEARCH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fsm_enSynthAnalog */ +/** + * @defgroup radio_synth_regs_core_fsm_enSynthAnalog_field fsm_enSynthAnalog_field + * @brief macros for field fsm_enSynthAnalog + * @details FSM output, enSynthAnalog signal + * @{ + */ +#define RADIO_SYNTH_SYNTH_READOUT__FSM_ENSYNTHANALOG__SHIFT 13 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_ENSYNTHANALOG__WIDTH 1 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_ENSYNTHANALOG__MASK 0x00002000U +#define RADIO_SYNTH_SYNTH_READOUT__FSM_ENSYNTHANALOG__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_ENSYNTHANALOG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_ENSYNTHANALOG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_ENSYNTHANALOG__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fsm_pinVc */ +/** + * @defgroup radio_synth_regs_core_fsm_pinVc_field fsm_pinVc_field + * @brief macros for field fsm_pinVc + * @details FSM output, pinVc signal + * @{ + */ +#define RADIO_SYNTH_SYNTH_READOUT__FSM_PINVC__SHIFT 14 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_PINVC__WIDTH 1 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_PINVC__MASK 0x00004000U +#define RADIO_SYNTH_SYNTH_READOUT__FSM_PINVC__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_PINVC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_PINVC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_PINVC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fsm_shortR */ +/** + * @defgroup radio_synth_regs_core_fsm_shortR_field fsm_shortR_field + * @brief macros for field fsm_shortR + * @details FSM output, shortR signal + * @{ + */ +#define RADIO_SYNTH_SYNTH_READOUT__FSM_SHORTR__SHIFT 15 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_SHORTR__WIDTH 1 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_SHORTR__MASK 0x00008000U +#define RADIO_SYNTH_SYNTH_READOUT__FSM_SHORTR__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_SHORTR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_SHORTR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_SHORTR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fsm_divRst */ +/** + * @defgroup radio_synth_regs_core_fsm_divRst_field fsm_divRst_field + * @brief macros for field fsm_divRst + * @details FSM output, divRst signal + * @{ + */ +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVRST__SHIFT 16 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVRST__WIDTH 1 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVRST__MASK 0x00010000U +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVRST__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVRST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVRST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVRST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fsm_divEnToggle */ +/** + * @defgroup radio_synth_regs_core_fsm_divEnToggle_field fsm_divEnToggle_field + * @brief macros for field fsm_divEnToggle + * @details FSM output, divEnToggle signal + * @{ + */ +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVENTOGGLE__SHIFT 17 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVENTOGGLE__WIDTH 1 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVENTOGGLE__MASK 0x00020000U +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVENTOGGLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVENTOGGLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVENTOGGLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_DIVENTOGGLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fsm_pfdRst */ +/** + * @defgroup radio_synth_regs_core_fsm_pfdRst_field fsm_pfdRst_field + * @brief macros for field fsm_pfdRst + * @details FSM output, pfdRst signal + * @{ + */ +#define RADIO_SYNTH_SYNTH_READOUT__FSM_PFDRST__SHIFT 18 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_PFDRST__WIDTH 1 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_PFDRST__MASK 0x00040000U +#define RADIO_SYNTH_SYNTH_READOUT__FSM_PFDRST__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_PFDRST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_PFDRST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_PFDRST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fsm_enSd */ +/** + * @defgroup radio_synth_regs_core_fsm_enSd_field fsm_enSd_field + * @brief macros for field fsm_enSd + * @details FSM output, enSd signal + * @{ + */ +#define RADIO_SYNTH_SYNTH_READOUT__FSM_ENSD__SHIFT 19 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_ENSD__WIDTH 1 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_ENSD__MASK 0x00080000U +#define RADIO_SYNTH_SYNTH_READOUT__FSM_ENSD__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_ENSD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_ENSD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_ENSD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fsm_vc2hi_Sync */ +/** + * @defgroup radio_synth_regs_core_fsm_vc2hi_Sync_field fsm_vc2hi_Sync_field + * @brief macros for field fsm_vc2hi_Sync + * @details FSM output, vc2hi_Sync signal + * @{ + */ +#define RADIO_SYNTH_SYNTH_READOUT__FSM_VC2HI_SYNC__SHIFT 20 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_VC2HI_SYNC__WIDTH 1 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_VC2HI_SYNC__MASK 0x00100000U +#define RADIO_SYNTH_SYNTH_READOUT__FSM_VC2HI_SYNC__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_VC2HI_SYNC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_VC2HI_SYNC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_VC2HI_SYNC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fsm_vc2lo_Sync */ +/** + * @defgroup radio_synth_regs_core_fsm_vc2lo_Sync_field fsm_vc2lo_Sync_field + * @brief macros for field fsm_vc2lo_Sync + * @details FSM output, vc2lo_Sync signal + * @{ + */ +#define RADIO_SYNTH_SYNTH_READOUT__FSM_VC2LO_SYNC__SHIFT 21 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_VC2LO_SYNC__WIDTH 1 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_VC2LO_SYNC__MASK 0x00200000U +#define RADIO_SYNTH_SYNTH_READOUT__FSM_VC2LO_SYNC__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_VC2LO_SYNC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_VC2LO_SYNC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_VC2LO_SYNC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fsm_nolock_Sync */ +/** + * @defgroup radio_synth_regs_core_fsm_nolock_Sync_field fsm_nolock_Sync_field + * @brief macros for field fsm_nolock_Sync + * @details FSM output, nolock_Sync signal + * @{ + */ +#define RADIO_SYNTH_SYNTH_READOUT__FSM_NOLOCK_SYNC__SHIFT 22 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_NOLOCK_SYNC__WIDTH 1 +#define RADIO_SYNTH_SYNTH_READOUT__FSM_NOLOCK_SYNC__MASK 0x00400000U +#define RADIO_SYNTH_SYNTH_READOUT__FSM_NOLOCK_SYNC__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_NOLOCK_SYNC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_NOLOCK_SYNC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define RADIO_SYNTH_SYNTH_READOUT__FSM_NOLOCK_SYNC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field txmodGain */ +/** + * @defgroup radio_synth_regs_core_txmodGain_field txmodGain_field + * @brief macros for field txmodGain + * @details calculated modGain output based on rate and channel + * @{ + */ +#define RADIO_SYNTH_SYNTH_READOUT__TXMODGAIN__SHIFT 23 +#define RADIO_SYNTH_SYNTH_READOUT__TXMODGAIN__WIDTH 5 +#define RADIO_SYNTH_SYNTH_READOUT__TXMODGAIN__MASK 0x0f800000U +#define RADIO_SYNTH_SYNTH_READOUT__TXMODGAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x0f800000U) >> 23) +#define RADIO_SYNTH_SYNTH_READOUT__TXMODGAIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field vcoCapsCoarse */ +/** + * @defgroup radio_synth_regs_core_vcoCapsCoarse_field vcoCapsCoarse_field + * @brief macros for field vcoCapsCoarse + * @details VCO coarse bank setting + * @{ + */ +#define RADIO_SYNTH_SYNTH_READOUT__VCOCAPSCOARSE__SHIFT 28 +#define RADIO_SYNTH_SYNTH_READOUT__VCOCAPSCOARSE__WIDTH 3 +#define RADIO_SYNTH_SYNTH_READOUT__VCOCAPSCOARSE__MASK 0x70000000U +#define RADIO_SYNTH_SYNTH_READOUT__VCOCAPSCOARSE__READ(src) \ + (((uint32_t)(src)\ + & 0x70000000U) >> 28) +#define RADIO_SYNTH_SYNTH_READOUT__VCOCAPSCOARSE__RESET_VALUE 0x00000000U +/** @} */ +#define RADIO_SYNTH_SYNTH_READOUT__TYPE uint32_t +#define RADIO_SYNTH_SYNTH_READOUT__READ 0x7fffffffU +#define RADIO_SYNTH_SYNTH_READOUT__PRESERVED 0x00000000U +#define RADIO_SYNTH_SYNTH_READOUT__RESET_VALUE 0x00000000U + +#endif /* __RADIO_SYNTH_SYNTH_READOUT_MACRO__ */ + +/** @} end of synth_readout */ + +/* macros for BlueprintGlobalNameSpace::radio_synth_core_id */ +/** + * @defgroup radio_synth_regs_core_core_id core_id + * @brief Core ID definitions. + * @{ + */ +#ifndef __RADIO_SYNTH_CORE_ID_MACRO__ +#define __RADIO_SYNTH_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup radio_synth_regs_core_id_field id_field + * @brief macros for field id + * @details SYNT in ASCII + * @{ + */ +#define RADIO_SYNTH_CORE_ID__ID__SHIFT 0 +#define RADIO_SYNTH_CORE_ID__ID__WIDTH 32 +#define RADIO_SYNTH_CORE_ID__ID__MASK 0xffffffffU +#define RADIO_SYNTH_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define RADIO_SYNTH_CORE_ID__ID__RESET_VALUE 0x53594e54U +/** @} */ +#define RADIO_SYNTH_CORE_ID__TYPE uint32_t +#define RADIO_SYNTH_CORE_ID__READ 0xffffffffU +#define RADIO_SYNTH_CORE_ID__PRESERVED 0x00000000U +#define RADIO_SYNTH_CORE_ID__RESET_VALUE 0x53594e54U + +#endif /* __RADIO_SYNTH_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of RADIO_SYNTH_REGS_CORE */ +#endif /* __REG_RADIO_SYNTH_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/radio_top_regs_core_macro.h b/ATM33xx-5/include/reg/radio_top_regs_core_macro.h new file mode 100644 index 0000000..20dcf27 --- /dev/null +++ b/ATM33xx-5/include/reg/radio_top_regs_core_macro.h @@ -0,0 +1,1599 @@ +/* */ +/* File: radio_top_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic radio_top_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_RADIO_TOP_REGS_CORE_H__ +#define __REG_RADIO_TOP_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup RADIO_TOP_REGS_CORE radio_top_regs_core + * @ingroup AT_REG + * @brief radio_top_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::radio_top_mode */ +/** + * @defgroup radio_top_regs_core_mode mode + * @brief Mode control overrides (mostly from RIF) definitions. + * @{ + */ +#ifndef __RADIO_TOP_MODE_MACRO__ +#define __RADIO_TOP_MODE_MACRO__ + +/* macros for field synthon_ovr */ +/** + * @defgroup radio_top_regs_core_synthon_ovr_field synthon_ovr_field + * @brief macros for field synthon_ovr + * @details synthon override + * @{ + */ +#define RADIO_TOP_MODE__SYNTHON_OVR__SHIFT 0 +#define RADIO_TOP_MODE__SYNTHON_OVR__WIDTH 2 +#define RADIO_TOP_MODE__SYNTHON_OVR__MASK 0x00000003U +#define RADIO_TOP_MODE__SYNTHON_OVR__READ(src) ((uint32_t)(src) & 0x00000003U) +#define RADIO_TOP_MODE__SYNTHON_OVR__WRITE(src) ((uint32_t)(src) & 0x00000003U) +#define RADIO_TOP_MODE__SYNTHON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define RADIO_TOP_MODE__SYNTHON_OVR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define RADIO_TOP_MODE__SYNTHON_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field txon_ovr */ +/** + * @defgroup radio_top_regs_core_txon_ovr_field txon_ovr_field + * @brief macros for field txon_ovr + * @details txon override + * @{ + */ +#define RADIO_TOP_MODE__TXON_OVR__SHIFT 2 +#define RADIO_TOP_MODE__TXON_OVR__WIDTH 2 +#define RADIO_TOP_MODE__TXON_OVR__MASK 0x0000000cU +#define RADIO_TOP_MODE__TXON_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x0000000cU) >> 2) +#define RADIO_TOP_MODE__TXON_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000000cU) +#define RADIO_TOP_MODE__TXON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((uint32_t)(src) <<\ + 2) & 0x0000000cU) +#define RADIO_TOP_MODE__TXON_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000000cU))) +#define RADIO_TOP_MODE__TXON_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field paon_ovr */ +/** + * @defgroup radio_top_regs_core_paon_ovr_field paon_ovr_field + * @brief macros for field paon_ovr + * @details paon override + * @{ + */ +#define RADIO_TOP_MODE__PAON_OVR__SHIFT 4 +#define RADIO_TOP_MODE__PAON_OVR__WIDTH 2 +#define RADIO_TOP_MODE__PAON_OVR__MASK 0x00000030U +#define RADIO_TOP_MODE__PAON_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000030U) >> 4) +#define RADIO_TOP_MODE__PAON_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000030U) +#define RADIO_TOP_MODE__PAON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((uint32_t)(src) <<\ + 4) & 0x00000030U) +#define RADIO_TOP_MODE__PAON_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000030U))) +#define RADIO_TOP_MODE__PAON_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rxon_ovr */ +/** + * @defgroup radio_top_regs_core_rxon_ovr_field rxon_ovr_field + * @brief macros for field rxon_ovr + * @details rxon override + * @{ + */ +#define RADIO_TOP_MODE__RXON_OVR__SHIFT 6 +#define RADIO_TOP_MODE__RXON_OVR__WIDTH 2 +#define RADIO_TOP_MODE__RXON_OVR__MASK 0x000000c0U +#define RADIO_TOP_MODE__RXON_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x000000c0U) >> 6) +#define RADIO_TOP_MODE__RXON_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000000c0U) +#define RADIO_TOP_MODE__RXON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((uint32_t)(src) <<\ + 6) & 0x000000c0U) +#define RADIO_TOP_MODE__RXON_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000000c0U))) +#define RADIO_TOP_MODE__RXON_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adcon_ovr */ +/** + * @defgroup radio_top_regs_core_adcon_ovr_field adcon_ovr_field + * @brief macros for field adcon_ovr + * @details adcon override + * @{ + */ +#define RADIO_TOP_MODE__ADCON_OVR__SHIFT 8 +#define RADIO_TOP_MODE__ADCON_OVR__WIDTH 2 +#define RADIO_TOP_MODE__ADCON_OVR__MASK 0x00000300U +#define RADIO_TOP_MODE__ADCON_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000300U) >> 8) +#define RADIO_TOP_MODE__ADCON_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000300U) +#define RADIO_TOP_MODE__ADCON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((uint32_t)(src) <<\ + 8) & 0x00000300U) +#define RADIO_TOP_MODE__ADCON_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000300U))) +#define RADIO_TOP_MODE__ADCON_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adcon_early_ovr */ +/** + * @defgroup radio_top_regs_core_adcon_early_ovr_field adcon_early_ovr_field + * @brief macros for field adcon_early_ovr + * @details adcon_early override + * @{ + */ +#define RADIO_TOP_MODE__ADCON_EARLY_OVR__SHIFT 10 +#define RADIO_TOP_MODE__ADCON_EARLY_OVR__WIDTH 2 +#define RADIO_TOP_MODE__ADCON_EARLY_OVR__MASK 0x00000c00U +#define RADIO_TOP_MODE__ADCON_EARLY_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000c00U) >> 10) +#define RADIO_TOP_MODE__ADCON_EARLY_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000c00U) +#define RADIO_TOP_MODE__ADCON_EARLY_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000c00U) | (((uint32_t)(src) <<\ + 10) & 0x00000c00U) +#define RADIO_TOP_MODE__ADCON_EARLY_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000c00U))) +#define RADIO_TOP_MODE__ADCON_EARLY_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clkrf_en_ovr */ +/** + * @defgroup radio_top_regs_core_clkrf_en_ovr_field clkrf_en_ovr_field + * @brief macros for field clkrf_en_ovr + * @details Synth XTAL clock buffer enable override + * @{ + */ +#define RADIO_TOP_MODE__CLKRF_EN_OVR__SHIFT 12 +#define RADIO_TOP_MODE__CLKRF_EN_OVR__WIDTH 2 +#define RADIO_TOP_MODE__CLKRF_EN_OVR__MASK 0x00003000U +#define RADIO_TOP_MODE__CLKRF_EN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00003000U) >> 12) +#define RADIO_TOP_MODE__CLKRF_EN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00003000U) +#define RADIO_TOP_MODE__CLKRF_EN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((uint32_t)(src) <<\ + 12) & 0x00003000U) +#define RADIO_TOP_MODE__CLKRF_EN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00003000U))) +#define RADIO_TOP_MODE__CLKRF_EN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clkadc_en_ovr */ +/** + * @defgroup radio_top_regs_core_clkadc_en_ovr_field clkadc_en_ovr_field + * @brief macros for field clkadc_en_ovr + * @details ADC XTAL clock buffer enable override + * @{ + */ +#define RADIO_TOP_MODE__CLKADC_EN_OVR__SHIFT 14 +#define RADIO_TOP_MODE__CLKADC_EN_OVR__WIDTH 2 +#define RADIO_TOP_MODE__CLKADC_EN_OVR__MASK 0x0000c000U +#define RADIO_TOP_MODE__CLKADC_EN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x0000c000U) >> 14) +#define RADIO_TOP_MODE__CLKADC_EN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0000c000U) +#define RADIO_TOP_MODE__CLKADC_EN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000c000U) | (((uint32_t)(src) <<\ + 14) & 0x0000c000U) +#define RADIO_TOP_MODE__CLKADC_EN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0000c000U))) +#define RADIO_TOP_MODE__CLKADC_EN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sel_clkadc */ +/** + * @defgroup radio_top_regs_core_sel_clkadc_field sel_clkadc_field + * @brief macros for field sel_clkadc + * @details ADC clock frequency selection, 2'b00 = xtal, 2'b01 = xtal*2, 2'b10 = xtal/2 + * @{ + */ +#define RADIO_TOP_MODE__SEL_CLKADC__SHIFT 16 +#define RADIO_TOP_MODE__SEL_CLKADC__WIDTH 2 +#define RADIO_TOP_MODE__SEL_CLKADC__MASK 0x00030000U +#define RADIO_TOP_MODE__SEL_CLKADC__READ(src) \ + (((uint32_t)(src)\ + & 0x00030000U) >> 16) +#define RADIO_TOP_MODE__SEL_CLKADC__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00030000U) +#define RADIO_TOP_MODE__SEL_CLKADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00030000U) | (((uint32_t)(src) <<\ + 16) & 0x00030000U) +#define RADIO_TOP_MODE__SEL_CLKADC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00030000U))) +#define RADIO_TOP_MODE__SEL_CLKADC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clkpm_en */ +/** + * @defgroup radio_top_regs_core_clkpm_en_field clkpm_en_field + * @brief macros for field clkpm_en + * @details Process monitor clock buffer enable + * @{ + */ +#define RADIO_TOP_MODE__CLKPM_EN__SHIFT 18 +#define RADIO_TOP_MODE__CLKPM_EN__WIDTH 1 +#define RADIO_TOP_MODE__CLKPM_EN__MASK 0x00040000U +#define RADIO_TOP_MODE__CLKPM_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define RADIO_TOP_MODE__CLKPM_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define RADIO_TOP_MODE__CLKPM_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define RADIO_TOP_MODE__CLKPM_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define RADIO_TOP_MODE__CLKPM_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define RADIO_TOP_MODE__CLKPM_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define RADIO_TOP_MODE__CLKPM_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sparebits */ +/** + * @defgroup radio_top_regs_core_sparebits_field sparebits_field + * @brief macros for field sparebits + * @details spares + * @{ + */ +#define RADIO_TOP_MODE__SPAREBITS__SHIFT 19 +#define RADIO_TOP_MODE__SPAREBITS__WIDTH 5 +#define RADIO_TOP_MODE__SPAREBITS__MASK 0x00f80000U +#define RADIO_TOP_MODE__SPAREBITS__READ(src) \ + (((uint32_t)(src)\ + & 0x00f80000U) >> 19) +#define RADIO_TOP_MODE__SPAREBITS__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00f80000U) +#define RADIO_TOP_MODE__SPAREBITS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f80000U) | (((uint32_t)(src) <<\ + 19) & 0x00f80000U) +#define RADIO_TOP_MODE__SPAREBITS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00f80000U))) +#define RADIO_TOP_MODE__SPAREBITS__RESET_VALUE 0x00000000U +/** @} */ +#define RADIO_TOP_MODE__TYPE uint32_t +#define RADIO_TOP_MODE__READ 0x00ffffffU +#define RADIO_TOP_MODE__WRITE 0x00ffffffU +#define RADIO_TOP_MODE__PRESERVED 0x00000000U +#define RADIO_TOP_MODE__RESET_VALUE 0x00000000U + +#endif /* __RADIO_TOP_MODE_MACRO__ */ + +/** @} end of mode */ + +/* macros for BlueprintGlobalNameSpace::radio_top_bias */ +/** + * @defgroup radio_top_regs_core_bias bias + * @brief Bandgap and LDO settings definitions. + * @{ + */ +#ifndef __RADIO_TOP_BIAS_MACRO__ +#define __RADIO_TOP_BIAS_MACRO__ + +/* macros for field bgtrim */ +/** + * @defgroup radio_top_regs_core_bgtrim_field bgtrim_field + * @brief macros for field bgtrim + * @details Bandgap tempco trim + * @{ + */ +#define RADIO_TOP_BIAS__BGTRIM__SHIFT 0 +#define RADIO_TOP_BIAS__BGTRIM__WIDTH 4 +#define RADIO_TOP_BIAS__BGTRIM__MASK 0x0000000fU +#define RADIO_TOP_BIAS__BGTRIM__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define RADIO_TOP_BIAS__BGTRIM__WRITE(src) ((uint32_t)(src) & 0x0000000fU) +#define RADIO_TOP_BIAS__BGTRIM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define RADIO_TOP_BIAS__BGTRIM__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define RADIO_TOP_BIAS__BGTRIM__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field irtrim */ +/** + * @defgroup radio_top_regs_core_irtrim_field irtrim_field + * @brief macros for field irtrim + * @details IR resistor trim, ie. global IR resistor adjustment + * @{ + */ +#define RADIO_TOP_BIAS__IRTRIM__SHIFT 4 +#define RADIO_TOP_BIAS__IRTRIM__WIDTH 6 +#define RADIO_TOP_BIAS__IRTRIM__MASK 0x000003f0U +#define RADIO_TOP_BIAS__IRTRIM__READ(src) \ + (((uint32_t)(src)\ + & 0x000003f0U) >> 4) +#define RADIO_TOP_BIAS__IRTRIM__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x000003f0U) +#define RADIO_TOP_BIAS__IRTRIM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003f0U) | (((uint32_t)(src) <<\ + 4) & 0x000003f0U) +#define RADIO_TOP_BIAS__IRTRIM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000003f0U))) +#define RADIO_TOP_BIAS__IRTRIM__RESET_VALUE 0x00000020U +/** @} */ + +/* macros for field bg_shrb_ovr */ +/** + * @defgroup radio_top_regs_core_bg_shrb_ovr_field bg_shrb_ovr_field + * @brief macros for field bg_shrb_ovr + * @details Force shorting of filter resistor in bandgap + * @{ + */ +#define RADIO_TOP_BIAS__BG_SHRB_OVR__SHIFT 10 +#define RADIO_TOP_BIAS__BG_SHRB_OVR__WIDTH 1 +#define RADIO_TOP_BIAS__BG_SHRB_OVR__MASK 0x00000400U +#define RADIO_TOP_BIAS__BG_SHRB_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define RADIO_TOP_BIAS__BG_SHRB_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define RADIO_TOP_BIAS__BG_SHRB_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define RADIO_TOP_BIAS__BG_SHRB_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define RADIO_TOP_BIAS__BG_SHRB_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define RADIO_TOP_BIAS__BG_SHRB_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define RADIO_TOP_BIAS__BG_SHRB_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_ldo_top_ovr */ +/** + * @defgroup radio_top_regs_core_en_ldo_top_ovr_field en_ldo_top_ovr_field + * @brief macros for field en_ldo_top_ovr + * @details Top LDO enable override, MSB enables override, LSB is override value + * @{ + */ +#define RADIO_TOP_BIAS__EN_LDO_TOP_OVR__SHIFT 11 +#define RADIO_TOP_BIAS__EN_LDO_TOP_OVR__WIDTH 2 +#define RADIO_TOP_BIAS__EN_LDO_TOP_OVR__MASK 0x00001800U +#define RADIO_TOP_BIAS__EN_LDO_TOP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00001800U) >> 11) +#define RADIO_TOP_BIAS__EN_LDO_TOP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00001800U) +#define RADIO_TOP_BIAS__EN_LDO_TOP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001800U) | (((uint32_t)(src) <<\ + 11) & 0x00001800U) +#define RADIO_TOP_BIAS__EN_LDO_TOP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00001800U))) +#define RADIO_TOP_BIAS__EN_LDO_TOP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_ldo_ovr */ +/** + * @defgroup radio_top_regs_core_en_ldo_ovr_field en_ldo_ovr_field + * @brief macros for field en_ldo_ovr + * @details Block LDO enable override, MSB enables override, LSB {RXFE, synthA, synthB, RXBB} is override value + * @{ + */ +#define RADIO_TOP_BIAS__EN_LDO_OVR__SHIFT 13 +#define RADIO_TOP_BIAS__EN_LDO_OVR__WIDTH 5 +#define RADIO_TOP_BIAS__EN_LDO_OVR__MASK 0x0003e000U +#define RADIO_TOP_BIAS__EN_LDO_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x0003e000U) >> 13) +#define RADIO_TOP_BIAS__EN_LDO_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0003e000U) +#define RADIO_TOP_BIAS__EN_LDO_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003e000U) | (((uint32_t)(src) <<\ + 13) & 0x0003e000U) +#define RADIO_TOP_BIAS__EN_LDO_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0003e000U))) +#define RADIO_TOP_BIAS__EN_LDO_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ldo_bypass_top_ovr */ +/** + * @defgroup radio_top_regs_core_ldo_bypass_top_ovr_field ldo_bypass_top_ovr_field + * @brief macros for field ldo_bypass_top_ovr + * @details Top LDO bypass override, MSB enables override, LSB is the override value + * @{ + */ +#define RADIO_TOP_BIAS__LDO_BYPASS_TOP_OVR__SHIFT 18 +#define RADIO_TOP_BIAS__LDO_BYPASS_TOP_OVR__WIDTH 2 +#define RADIO_TOP_BIAS__LDO_BYPASS_TOP_OVR__MASK 0x000c0000U +#define RADIO_TOP_BIAS__LDO_BYPASS_TOP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x000c0000U) >> 18) +#define RADIO_TOP_BIAS__LDO_BYPASS_TOP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x000c0000U) +#define RADIO_TOP_BIAS__LDO_BYPASS_TOP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000c0000U) | (((uint32_t)(src) <<\ + 18) & 0x000c0000U) +#define RADIO_TOP_BIAS__LDO_BYPASS_TOP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x000c0000U))) +#define RADIO_TOP_BIAS__LDO_BYPASS_TOP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ldo_bypass_ovr */ +/** + * @defgroup radio_top_regs_core_ldo_bypass_ovr_field ldo_bypass_ovr_field + * @brief macros for field ldo_bypass_ovr + * @details Block LDO bypass override, MSB enables override, LSB is override value, overrides all LDOs, bits [4:1] unused + * @{ + */ +#define RADIO_TOP_BIAS__LDO_BYPASS_OVR__SHIFT 20 +#define RADIO_TOP_BIAS__LDO_BYPASS_OVR__WIDTH 5 +#define RADIO_TOP_BIAS__LDO_BYPASS_OVR__MASK 0x01f00000U +#define RADIO_TOP_BIAS__LDO_BYPASS_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x01f00000U) >> 20) +#define RADIO_TOP_BIAS__LDO_BYPASS_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x01f00000U) +#define RADIO_TOP_BIAS__LDO_BYPASS_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((uint32_t)(src) <<\ + 20) & 0x01f00000U) +#define RADIO_TOP_BIAS__LDO_BYPASS_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x01f00000U))) +#define RADIO_TOP_BIAS__LDO_BYPASS_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ldo_shrb_top_ovr */ +/** + * @defgroup radio_top_regs_core_ldo_shrb_top_ovr_field ldo_shrb_top_ovr_field + * @brief macros for field ldo_shrb_top_ovr + * @details Force shorting of vref filter resistor for top LDO + * @{ + */ +#define RADIO_TOP_BIAS__LDO_SHRB_TOP_OVR__SHIFT 25 +#define RADIO_TOP_BIAS__LDO_SHRB_TOP_OVR__WIDTH 1 +#define RADIO_TOP_BIAS__LDO_SHRB_TOP_OVR__MASK 0x02000000U +#define RADIO_TOP_BIAS__LDO_SHRB_TOP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define RADIO_TOP_BIAS__LDO_SHRB_TOP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define RADIO_TOP_BIAS__LDO_SHRB_TOP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define RADIO_TOP_BIAS__LDO_SHRB_TOP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define RADIO_TOP_BIAS__LDO_SHRB_TOP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define RADIO_TOP_BIAS__LDO_SHRB_TOP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define RADIO_TOP_BIAS__LDO_SHRB_TOP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ldo_shrb_ovr */ +/** + * @defgroup radio_top_regs_core_ldo_shrb_ovr_field ldo_shrb_ovr_field + * @brief macros for field ldo_shrb_ovr + * @details Force shorting of vref filter resistor for block LDOs + * @{ + */ +#define RADIO_TOP_BIAS__LDO_SHRB_OVR__SHIFT 26 +#define RADIO_TOP_BIAS__LDO_SHRB_OVR__WIDTH 1 +#define RADIO_TOP_BIAS__LDO_SHRB_OVR__MASK 0x04000000U +#define RADIO_TOP_BIAS__LDO_SHRB_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define RADIO_TOP_BIAS__LDO_SHRB_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define RADIO_TOP_BIAS__LDO_SHRB_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define RADIO_TOP_BIAS__LDO_SHRB_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define RADIO_TOP_BIAS__LDO_SHRB_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define RADIO_TOP_BIAS__LDO_SHRB_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define RADIO_TOP_BIAS__LDO_SHRB_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field cnt_shortres_b */ +/** + * @defgroup radio_top_regs_core_cnt_shortres_b_field cnt_shortres_b_field + * @brief macros for field cnt_shortres_b + * @details Time after radio reset deassertion to unshort bandgap and LDO filter resistors, 9us to 40us in 1us step, default 25us + * @{ + */ +#define RADIO_TOP_BIAS__CNT_SHORTRES_B__SHIFT 27 +#define RADIO_TOP_BIAS__CNT_SHORTRES_B__WIDTH 5 +#define RADIO_TOP_BIAS__CNT_SHORTRES_B__MASK 0xf8000000U +#define RADIO_TOP_BIAS__CNT_SHORTRES_B__READ(src) \ + (((uint32_t)(src)\ + & 0xf8000000U) >> 27) +#define RADIO_TOP_BIAS__CNT_SHORTRES_B__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0xf8000000U) +#define RADIO_TOP_BIAS__CNT_SHORTRES_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((uint32_t)(src) <<\ + 27) & 0xf8000000U) +#define RADIO_TOP_BIAS__CNT_SHORTRES_B__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0xf8000000U))) +#define RADIO_TOP_BIAS__CNT_SHORTRES_B__RESET_VALUE 0x00000010U +/** @} */ +#define RADIO_TOP_BIAS__TYPE uint32_t +#define RADIO_TOP_BIAS__READ 0xffffffffU +#define RADIO_TOP_BIAS__WRITE 0xffffffffU +#define RADIO_TOP_BIAS__PRESERVED 0x00000000U +#define RADIO_TOP_BIAS__RESET_VALUE 0x80000208U + +#endif /* __RADIO_TOP_BIAS_MACRO__ */ + +/** @} end of bias */ + +/* macros for BlueprintGlobalNameSpace::radio_top_test */ +/** + * @defgroup radio_top_regs_core_test test + * @brief Test controls definitions. + * @{ + */ +#ifndef __RADIO_TOP_TEST_MACRO__ +#define __RADIO_TOP_TEST_MACRO__ + +/* macros for field testiq_buf_en */ +/** + * @defgroup radio_top_regs_core_testiq_buf_en_field testiq_buf_en_field + * @brief macros for field testiq_buf_en + * @details Enable test I/Q buffers + * @{ + */ +#define RADIO_TOP_TEST__TESTIQ_BUF_EN__SHIFT 0 +#define RADIO_TOP_TEST__TESTIQ_BUF_EN__WIDTH 1 +#define RADIO_TOP_TEST__TESTIQ_BUF_EN__MASK 0x00000001U +#define RADIO_TOP_TEST__TESTIQ_BUF_EN__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RADIO_TOP_TEST__TESTIQ_BUF_EN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RADIO_TOP_TEST__TESTIQ_BUF_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define RADIO_TOP_TEST__TESTIQ_BUF_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define RADIO_TOP_TEST__TESTIQ_BUF_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define RADIO_TOP_TEST__TESTIQ_BUF_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define RADIO_TOP_TEST__TESTIQ_BUF_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field testiq_buf_bypass */ +/** + * @defgroup radio_top_regs_core_testiq_buf_bypass_field testiq_buf_bypass_field + * @brief macros for field testiq_buf_bypass + * @details Bypass test I/Q buffers so analog test signals can be driven in + * @{ + */ +#define RADIO_TOP_TEST__TESTIQ_BUF_BYPASS__SHIFT 1 +#define RADIO_TOP_TEST__TESTIQ_BUF_BYPASS__WIDTH 1 +#define RADIO_TOP_TEST__TESTIQ_BUF_BYPASS__MASK 0x00000002U +#define RADIO_TOP_TEST__TESTIQ_BUF_BYPASS__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define RADIO_TOP_TEST__TESTIQ_BUF_BYPASS__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define RADIO_TOP_TEST__TESTIQ_BUF_BYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define RADIO_TOP_TEST__TESTIQ_BUF_BYPASS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define RADIO_TOP_TEST__TESTIQ_BUF_BYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define RADIO_TOP_TEST__TESTIQ_BUF_BYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define RADIO_TOP_TEST__TESTIQ_BUF_BYPASS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field testiq_pad_en */ +/** + * @defgroup radio_top_regs_core_testiq_pad_en_field testiq_pad_en_field + * @brief macros for field testiq_pad_en + * @details Disable digital pad input and output and enable test I/Q path to pad + * @{ + */ +#define RADIO_TOP_TEST__TESTIQ_PAD_EN__SHIFT 2 +#define RADIO_TOP_TEST__TESTIQ_PAD_EN__WIDTH 1 +#define RADIO_TOP_TEST__TESTIQ_PAD_EN__MASK 0x00000004U +#define RADIO_TOP_TEST__TESTIQ_PAD_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define RADIO_TOP_TEST__TESTIQ_PAD_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define RADIO_TOP_TEST__TESTIQ_PAD_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define RADIO_TOP_TEST__TESTIQ_PAD_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define RADIO_TOP_TEST__TESTIQ_PAD_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define RADIO_TOP_TEST__TESTIQ_PAD_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define RADIO_TOP_TEST__TESTIQ_PAD_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field atb_pad_en */ +/** + * @defgroup radio_top_regs_core_atb_pad_en_field atb_pad_en_field + * @brief macros for field atb_pad_en + * @details Disable digital pad input and output and enable ATB path to pad + * @{ + */ +#define RADIO_TOP_TEST__ATB_PAD_EN__SHIFT 3 +#define RADIO_TOP_TEST__ATB_PAD_EN__WIDTH 1 +#define RADIO_TOP_TEST__ATB_PAD_EN__MASK 0x00000008U +#define RADIO_TOP_TEST__ATB_PAD_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define RADIO_TOP_TEST__ATB_PAD_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define RADIO_TOP_TEST__ATB_PAD_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define RADIO_TOP_TEST__ATB_PAD_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define RADIO_TOP_TEST__ATB_PAD_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define RADIO_TOP_TEST__ATB_PAD_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define RADIO_TOP_TEST__ATB_PAD_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field atb_sel */ +/** + * @defgroup radio_top_regs_core_atb_sel_field atb_sel_field + * @brief macros for field atb_sel + * @details Top-level ATB mux select, 0 = high-Z, 1 = bias, 2 = synth/TX, 3 = RX, 4 = LDO, 5 = PLL, 6 = WuRX, 7 = reserved + * @{ + */ +#define RADIO_TOP_TEST__ATB_SEL__SHIFT 4 +#define RADIO_TOP_TEST__ATB_SEL__WIDTH 3 +#define RADIO_TOP_TEST__ATB_SEL__MASK 0x00000070U +#define RADIO_TOP_TEST__ATB_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000070U) >> 4) +#define RADIO_TOP_TEST__ATB_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000070U) +#define RADIO_TOP_TEST__ATB_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((uint32_t)(src) <<\ + 4) & 0x00000070U) +#define RADIO_TOP_TEST__ATB_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000070U))) +#define RADIO_TOP_TEST__ATB_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dig_sel */ +/** + * @defgroup radio_top_regs_core_dig_sel_field dig_sel_field + * @brief macros for field dig_sel + * @details Select digital signals to put onto dig_test_out, 0 = tielo, 1 = xtal_stable, 2 = lna_peakdet, 3 = pm_osc_out, 4-7 TBD + * @{ + */ +#define RADIO_TOP_TEST__DIG_SEL__SHIFT 7 +#define RADIO_TOP_TEST__DIG_SEL__WIDTH 3 +#define RADIO_TOP_TEST__DIG_SEL__MASK 0x00000380U +#define RADIO_TOP_TEST__DIG_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000380U) >> 7) +#define RADIO_TOP_TEST__DIG_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000380U) +#define RADIO_TOP_TEST__DIG_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000380U) | (((uint32_t)(src) <<\ + 7) & 0x00000380U) +#define RADIO_TOP_TEST__DIG_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000380U))) +#define RADIO_TOP_TEST__DIG_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bias_atb_sel */ +/** + * @defgroup radio_top_regs_core_bias_atb_sel_field bias_atb_sel_field + * @brief macros for field bias_atb_sel + * @details Bias block ATB, 0 = high-Z, 1 = pcas, 2 = vc, 3 = vr, 4 = pcur, 5 = gnd, 6 = ir3_1uA, 7 = ic2_4uA + * @{ + */ +#define RADIO_TOP_TEST__BIAS_ATB_SEL__SHIFT 10 +#define RADIO_TOP_TEST__BIAS_ATB_SEL__WIDTH 3 +#define RADIO_TOP_TEST__BIAS_ATB_SEL__MASK 0x00001c00U +#define RADIO_TOP_TEST__BIAS_ATB_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00001c00U) >> 10) +#define RADIO_TOP_TEST__BIAS_ATB_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00001c00U) +#define RADIO_TOP_TEST__BIAS_ATB_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001c00U) | (((uint32_t)(src) <<\ + 10) & 0x00001c00U) +#define RADIO_TOP_TEST__BIAS_ATB_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00001c00U))) +#define RADIO_TOP_TEST__BIAS_ATB_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ldo_atb_sel */ +/** + * @defgroup radio_top_regs_core_ldo_atb_sel_field ldo_atb_sel_field + * @brief macros for field ldo_atb_sel + * @details LDO ATB, 0 = high-Z, 1 = synthB vout/2, 2 = RXBB vout/2, 3 = top vout/2, 4 = block vref800mV, 5 = top vref800mV, 6 = block ir2u, 7 = top ir2u + * @{ + */ +#define RADIO_TOP_TEST__LDO_ATB_SEL__SHIFT 13 +#define RADIO_TOP_TEST__LDO_ATB_SEL__WIDTH 3 +#define RADIO_TOP_TEST__LDO_ATB_SEL__MASK 0x0000e000U +#define RADIO_TOP_TEST__LDO_ATB_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x0000e000U) >> 13) +#define RADIO_TOP_TEST__LDO_ATB_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0000e000U) +#define RADIO_TOP_TEST__LDO_ATB_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((uint32_t)(src) <<\ + 13) & 0x0000e000U) +#define RADIO_TOP_TEST__LDO_ATB_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0000e000U))) +#define RADIO_TOP_TEST__LDO_ATB_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_rload_top */ +/** + * @defgroup radio_top_regs_core_en_rload_top_field en_rload_top_field + * @brief macros for field en_rload_top + * @details Enable load resistor divider and vout/2 voltage for top LDO + * @{ + */ +#define RADIO_TOP_TEST__EN_RLOAD_TOP__SHIFT 16 +#define RADIO_TOP_TEST__EN_RLOAD_TOP__WIDTH 1 +#define RADIO_TOP_TEST__EN_RLOAD_TOP__MASK 0x00010000U +#define RADIO_TOP_TEST__EN_RLOAD_TOP__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define RADIO_TOP_TEST__EN_RLOAD_TOP__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define RADIO_TOP_TEST__EN_RLOAD_TOP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define RADIO_TOP_TEST__EN_RLOAD_TOP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define RADIO_TOP_TEST__EN_RLOAD_TOP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define RADIO_TOP_TEST__EN_RLOAD_TOP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define RADIO_TOP_TEST__EN_RLOAD_TOP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field en_rload */ +/** + * @defgroup radio_top_regs_core_en_rload_field en_rload_field + * @brief macros for field en_rload + * @details Enable load resistor divider and vout/2 voltages for block LDOs, {RXFE, synthA, synthB, RXBB} + * @{ + */ +#define RADIO_TOP_TEST__EN_RLOAD__SHIFT 17 +#define RADIO_TOP_TEST__EN_RLOAD__WIDTH 4 +#define RADIO_TOP_TEST__EN_RLOAD__MASK 0x001e0000U +#define RADIO_TOP_TEST__EN_RLOAD__READ(src) \ + (((uint32_t)(src)\ + & 0x001e0000U) >> 17) +#define RADIO_TOP_TEST__EN_RLOAD__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x001e0000U) +#define RADIO_TOP_TEST__EN_RLOAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001e0000U) | (((uint32_t)(src) <<\ + 17) & 0x001e0000U) +#define RADIO_TOP_TEST__EN_RLOAD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x001e0000U))) +#define RADIO_TOP_TEST__EN_RLOAD__RESET_VALUE 0x00000000U +/** @} */ +#define RADIO_TOP_TEST__TYPE uint32_t +#define RADIO_TOP_TEST__READ 0x001fffffU +#define RADIO_TOP_TEST__WRITE 0x001fffffU +#define RADIO_TOP_TEST__PRESERVED 0x00000000U +#define RADIO_TOP_TEST__RESET_VALUE 0x00000000U + +#endif /* __RADIO_TOP_TEST_MACRO__ */ + +/** @} end of test */ + +/* macros for BlueprintGlobalNameSpace::radio_top_status */ +/** + * @defgroup radio_top_regs_core_status status + * @brief Applied mode controls and dig_test_in readback definitions. + * @{ + */ +#ifndef __RADIO_TOP_STATUS_MACRO__ +#define __RADIO_TOP_STATUS_MACRO__ + +/* macros for field synthon */ +/** + * @defgroup radio_top_regs_core_synthon_field synthon_field + * @brief macros for field synthon + * @details synthon status + * @{ + */ +#define RADIO_TOP_STATUS__SYNTHON__SHIFT 0 +#define RADIO_TOP_STATUS__SYNTHON__WIDTH 1 +#define RADIO_TOP_STATUS__SYNTHON__MASK 0x00000001U +#define RADIO_TOP_STATUS__SYNTHON__READ(src) ((uint32_t)(src) & 0x00000001U) +#define RADIO_TOP_STATUS__SYNTHON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define RADIO_TOP_STATUS__SYNTHON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define RADIO_TOP_STATUS__SYNTHON__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field txon */ +/** + * @defgroup radio_top_regs_core_txon_field txon_field + * @brief macros for field txon + * @details txon status + * @{ + */ +#define RADIO_TOP_STATUS__TXON__SHIFT 1 +#define RADIO_TOP_STATUS__TXON__WIDTH 1 +#define RADIO_TOP_STATUS__TXON__MASK 0x00000002U +#define RADIO_TOP_STATUS__TXON__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define RADIO_TOP_STATUS__TXON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define RADIO_TOP_STATUS__TXON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define RADIO_TOP_STATUS__TXON__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field paon */ +/** + * @defgroup radio_top_regs_core_paon_field paon_field + * @brief macros for field paon + * @details paon status + * @{ + */ +#define RADIO_TOP_STATUS__PAON__SHIFT 2 +#define RADIO_TOP_STATUS__PAON__WIDTH 1 +#define RADIO_TOP_STATUS__PAON__MASK 0x00000004U +#define RADIO_TOP_STATUS__PAON__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define RADIO_TOP_STATUS__PAON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define RADIO_TOP_STATUS__PAON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define RADIO_TOP_STATUS__PAON__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rxon */ +/** + * @defgroup radio_top_regs_core_rxon_field rxon_field + * @brief macros for field rxon + * @details rxon status + * @{ + */ +#define RADIO_TOP_STATUS__RXON__SHIFT 3 +#define RADIO_TOP_STATUS__RXON__WIDTH 1 +#define RADIO_TOP_STATUS__RXON__MASK 0x00000008U +#define RADIO_TOP_STATUS__RXON__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define RADIO_TOP_STATUS__RXON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define RADIO_TOP_STATUS__RXON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define RADIO_TOP_STATUS__RXON__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adcon */ +/** + * @defgroup radio_top_regs_core_adcon_field adcon_field + * @brief macros for field adcon + * @details adcon status + * @{ + */ +#define RADIO_TOP_STATUS__ADCON__SHIFT 4 +#define RADIO_TOP_STATUS__ADCON__WIDTH 1 +#define RADIO_TOP_STATUS__ADCON__MASK 0x00000010U +#define RADIO_TOP_STATUS__ADCON__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define RADIO_TOP_STATUS__ADCON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define RADIO_TOP_STATUS__ADCON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define RADIO_TOP_STATUS__ADCON__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adcon_early */ +/** + * @defgroup radio_top_regs_core_adcon_early_field adcon_early_field + * @brief macros for field adcon_early + * @details adcon_early status + * @{ + */ +#define RADIO_TOP_STATUS__ADCON_EARLY__SHIFT 5 +#define RADIO_TOP_STATUS__ADCON_EARLY__WIDTH 1 +#define RADIO_TOP_STATUS__ADCON_EARLY__MASK 0x00000020U +#define RADIO_TOP_STATUS__ADCON_EARLY__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define RADIO_TOP_STATUS__ADCON_EARLY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define RADIO_TOP_STATUS__ADCON_EARLY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define RADIO_TOP_STATUS__ADCON_EARLY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dig_test_in_xtal_stable */ +/** + * @defgroup radio_top_regs_core_dig_test_in_xtal_stable_field dig_test_in_xtal_stable_field + * @brief macros for field dig_test_in_xtal_stable + * @details digital test inputs, bit 0 = xtal_stable, bit 1 = tia_peakdet, bit 2 = lna_peakdet, bits 3-6 TBD + * @{ + */ +#define RADIO_TOP_STATUS__DIG_TEST_IN_XTAL_STABLE__SHIFT 6 +#define RADIO_TOP_STATUS__DIG_TEST_IN_XTAL_STABLE__WIDTH 1 +#define RADIO_TOP_STATUS__DIG_TEST_IN_XTAL_STABLE__MASK 0x00000040U +#define RADIO_TOP_STATUS__DIG_TEST_IN_XTAL_STABLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define RADIO_TOP_STATUS__DIG_TEST_IN_XTAL_STABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define RADIO_TOP_STATUS__DIG_TEST_IN_XTAL_STABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define RADIO_TOP_STATUS__DIG_TEST_IN_XTAL_STABLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dig_test_in_tia_peakdet */ +/** + * @defgroup radio_top_regs_core_dig_test_in_tia_peakdet_field dig_test_in_tia_peakdet_field + * @brief macros for field dig_test_in_tia_peakdet + * @details digital test inputs, bit 0 = xtal_stable, bit 1 = tia_peakdet, bit 2 = lna_peakdet, bits 3-6 TBD + * @{ + */ +#define RADIO_TOP_STATUS__DIG_TEST_IN_TIA_PEAKDET__SHIFT 7 +#define RADIO_TOP_STATUS__DIG_TEST_IN_TIA_PEAKDET__WIDTH 1 +#define RADIO_TOP_STATUS__DIG_TEST_IN_TIA_PEAKDET__MASK 0x00000080U +#define RADIO_TOP_STATUS__DIG_TEST_IN_TIA_PEAKDET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define RADIO_TOP_STATUS__DIG_TEST_IN_TIA_PEAKDET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define RADIO_TOP_STATUS__DIG_TEST_IN_TIA_PEAKDET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define RADIO_TOP_STATUS__DIG_TEST_IN_TIA_PEAKDET__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dig_test_in_lna_peakdet */ +/** + * @defgroup radio_top_regs_core_dig_test_in_lna_peakdet_field dig_test_in_lna_peakdet_field + * @brief macros for field dig_test_in_lna_peakdet + * @details digital test inputs, bit 0 = xtal_stable, bit 1 = tia_peakdet, bit 2 = lna_peakdet, bits 3-6 TBD + * @{ + */ +#define RADIO_TOP_STATUS__DIG_TEST_IN_LNA_PEAKDET__SHIFT 8 +#define RADIO_TOP_STATUS__DIG_TEST_IN_LNA_PEAKDET__WIDTH 1 +#define RADIO_TOP_STATUS__DIG_TEST_IN_LNA_PEAKDET__MASK 0x00000100U +#define RADIO_TOP_STATUS__DIG_TEST_IN_LNA_PEAKDET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define RADIO_TOP_STATUS__DIG_TEST_IN_LNA_PEAKDET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define RADIO_TOP_STATUS__DIG_TEST_IN_LNA_PEAKDET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define RADIO_TOP_STATUS__DIG_TEST_IN_LNA_PEAKDET__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field dig_test_in_TBD */ +/** + * @defgroup radio_top_regs_core_dig_test_in_TBD_field dig_test_in_TBD_field + * @brief macros for field dig_test_in_TBD + * @details digital test inputs, bit 0 = xtal_stable, bit 1 = tia_peakdet, bit 2 = lna_peakdet, bits 3-6 TBD + * @{ + */ +#define RADIO_TOP_STATUS__DIG_TEST_IN_TBD__SHIFT 9 +#define RADIO_TOP_STATUS__DIG_TEST_IN_TBD__WIDTH 4 +#define RADIO_TOP_STATUS__DIG_TEST_IN_TBD__MASK 0x00001e00U +#define RADIO_TOP_STATUS__DIG_TEST_IN_TBD__READ(src) \ + (((uint32_t)(src)\ + & 0x00001e00U) >> 9) +#define RADIO_TOP_STATUS__DIG_TEST_IN_TBD__RESET_VALUE 0x00000000U +/** @} */ +#define RADIO_TOP_STATUS__TYPE uint32_t +#define RADIO_TOP_STATUS__READ 0x00001fffU +#define RADIO_TOP_STATUS__PRESERVED 0x00000000U +#define RADIO_TOP_STATUS__RESET_VALUE 0x00000000U + +#endif /* __RADIO_TOP_STATUS_MACRO__ */ + +/** @} end of status */ + +/* macros for BlueprintGlobalNameSpace::radio_top_version */ +/** + * @defgroup radio_top_regs_core_version version + * @brief Radio version definitions. + * @{ + */ +#ifndef __RADIO_TOP_VERSION_MACRO__ +#define __RADIO_TOP_VERSION_MACRO__ + +/* macros for field rev_id */ +/** + * @defgroup radio_top_regs_core_rev_id_field rev_id_field + * @brief macros for field rev_id + * @details revision ID, upper 4-bits major version, lower 4-bits minor version + * @{ + */ +#define RADIO_TOP_VERSION__REV_ID__SHIFT 0 +#define RADIO_TOP_VERSION__REV_ID__WIDTH 8 +#define RADIO_TOP_VERSION__REV_ID__MASK 0x000000ffU +#define RADIO_TOP_VERSION__REV_ID__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define RADIO_TOP_VERSION__REV_ID__RESET_VALUE 0x00000021U +/** @} */ + +/* macros for field prod_id */ +/** + * @defgroup radio_top_regs_core_prod_id_field prod_id_field + * @brief macros for field prod_id + * @details product ID, 2 = paris + * @{ + */ +#define RADIO_TOP_VERSION__PROD_ID__SHIFT 8 +#define RADIO_TOP_VERSION__PROD_ID__WIDTH 8 +#define RADIO_TOP_VERSION__PROD_ID__MASK 0x0000ff00U +#define RADIO_TOP_VERSION__PROD_ID__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define RADIO_TOP_VERSION__PROD_ID__RESET_VALUE 0x00000002U +/** @} */ +#define RADIO_TOP_VERSION__TYPE uint32_t +#define RADIO_TOP_VERSION__READ 0x0000ffffU +#define RADIO_TOP_VERSION__PRESERVED 0x00000000U +#define RADIO_TOP_VERSION__RESET_VALUE 0x00000221U + +#endif /* __RADIO_TOP_VERSION_MACRO__ */ + +/** @} end of version */ + +/* macros for BlueprintGlobalNameSpace::radio_top_procmon */ +/** + * @defgroup radio_top_regs_core_procmon procmon + * @brief Process monitor control and settings definitions. + * @{ + */ +#ifndef __RADIO_TOP_PROCMON_MACRO__ +#define __RADIO_TOP_PROCMON_MACRO__ + +/* macros for field ro_cnt_en */ +/** + * @defgroup radio_top_regs_core_ro_cnt_en_field ro_cnt_en_field + * @brief macros for field ro_cnt_en + * @details Enable ring oscillator counter + * @{ + */ +#define RADIO_TOP_PROCMON__RO_CNT_EN__SHIFT 0 +#define RADIO_TOP_PROCMON__RO_CNT_EN__WIDTH 1 +#define RADIO_TOP_PROCMON__RO_CNT_EN__MASK 0x00000001U +#define RADIO_TOP_PROCMON__RO_CNT_EN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define RADIO_TOP_PROCMON__RO_CNT_EN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RADIO_TOP_PROCMON__RO_CNT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define RADIO_TOP_PROCMON__RO_CNT_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define RADIO_TOP_PROCMON__RO_CNT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define RADIO_TOP_PROCMON__RO_CNT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define RADIO_TOP_PROCMON__RO_CNT_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ro_cnt_rst */ +/** + * @defgroup radio_top_regs_core_ro_cnt_rst_field ro_cnt_rst_field + * @brief macros for field ro_cnt_rst + * @details Reset ring oscillator counter + * @{ + */ +#define RADIO_TOP_PROCMON__RO_CNT_RST__SHIFT 1 +#define RADIO_TOP_PROCMON__RO_CNT_RST__WIDTH 1 +#define RADIO_TOP_PROCMON__RO_CNT_RST__MASK 0x00000002U +#define RADIO_TOP_PROCMON__RO_CNT_RST__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define RADIO_TOP_PROCMON__RO_CNT_RST__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define RADIO_TOP_PROCMON__RO_CNT_RST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define RADIO_TOP_PROCMON__RO_CNT_RST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define RADIO_TOP_PROCMON__RO_CNT_RST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define RADIO_TOP_PROCMON__RO_CNT_RST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define RADIO_TOP_PROCMON__RO_CNT_RST__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field ro_sel */ +/** + * @defgroup radio_top_regs_core_ro_sel_field ro_sel_field + * @brief macros for field ro_sel + * @details Ring oscillator type select, one-hot, 0: all off, 1: HVT, 2: SVT, 4: LVT, 8: ELVT + * @{ + */ +#define RADIO_TOP_PROCMON__RO_SEL__SHIFT 2 +#define RADIO_TOP_PROCMON__RO_SEL__WIDTH 4 +#define RADIO_TOP_PROCMON__RO_SEL__MASK 0x0000003cU +#define RADIO_TOP_PROCMON__RO_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x0000003cU) >> 2) +#define RADIO_TOP_PROCMON__RO_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000003cU) +#define RADIO_TOP_PROCMON__RO_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003cU) | (((uint32_t)(src) <<\ + 2) & 0x0000003cU) +#define RADIO_TOP_PROCMON__RO_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000003cU))) +#define RADIO_TOP_PROCMON__RO_SEL__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field N_refclk */ +/** + * @defgroup radio_top_regs_core_N_refclk_field N_refclk_field + * @brief macros for field N_refclk + * @details Number of refclk cycles to run ring oscillator counter + * @{ + */ +#define RADIO_TOP_PROCMON__N_REFCLK__SHIFT 6 +#define RADIO_TOP_PROCMON__N_REFCLK__WIDTH 4 +#define RADIO_TOP_PROCMON__N_REFCLK__MASK 0x000003c0U +#define RADIO_TOP_PROCMON__N_REFCLK__READ(src) \ + (((uint32_t)(src)\ + & 0x000003c0U) >> 6) +#define RADIO_TOP_PROCMON__N_REFCLK__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000003c0U) +#define RADIO_TOP_PROCMON__N_REFCLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003c0U) | (((uint32_t)(src) <<\ + 6) & 0x000003c0U) +#define RADIO_TOP_PROCMON__N_REFCLK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000003c0U))) +#define RADIO_TOP_PROCMON__N_REFCLK__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field cosc_en */ +/** + * @defgroup radio_top_regs_core_cosc_en_field cosc_en_field + * @brief macros for field cosc_en + * @details Enable C-based oscillator + * @{ + */ +#define RADIO_TOP_PROCMON__COSC_EN__SHIFT 10 +#define RADIO_TOP_PROCMON__COSC_EN__WIDTH 1 +#define RADIO_TOP_PROCMON__COSC_EN__MASK 0x00000400U +#define RADIO_TOP_PROCMON__COSC_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define RADIO_TOP_PROCMON__COSC_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define RADIO_TOP_PROCMON__COSC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define RADIO_TOP_PROCMON__COSC_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define RADIO_TOP_PROCMON__COSC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define RADIO_TOP_PROCMON__COSC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define RADIO_TOP_PROCMON__COSC_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rcosc_en */ +/** + * @defgroup radio_top_regs_core_rcosc_en_field rcosc_en_field + * @brief macros for field rcosc_en + * @details Enable RC-based oscillator + * @{ + */ +#define RADIO_TOP_PROCMON__RCOSC_EN__SHIFT 11 +#define RADIO_TOP_PROCMON__RCOSC_EN__WIDTH 1 +#define RADIO_TOP_PROCMON__RCOSC_EN__MASK 0x00000800U +#define RADIO_TOP_PROCMON__RCOSC_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define RADIO_TOP_PROCMON__RCOSC_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define RADIO_TOP_PROCMON__RCOSC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define RADIO_TOP_PROCMON__RCOSC_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define RADIO_TOP_PROCMON__RCOSC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define RADIO_TOP_PROCMON__RCOSC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define RADIO_TOP_PROCMON__RCOSC_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sel_icchg */ +/** + * @defgroup radio_top_regs_core_sel_icchg_field sel_icchg_field + * @brief macros for field sel_icchg + * @details C-based oscillator charging current + * @{ + */ +#define RADIO_TOP_PROCMON__SEL_ICCHG__SHIFT 12 +#define RADIO_TOP_PROCMON__SEL_ICCHG__WIDTH 3 +#define RADIO_TOP_PROCMON__SEL_ICCHG__MASK 0x00007000U +#define RADIO_TOP_PROCMON__SEL_ICCHG__READ(src) \ + (((uint32_t)(src)\ + & 0x00007000U) >> 12) +#define RADIO_TOP_PROCMON__SEL_ICCHG__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00007000U) +#define RADIO_TOP_PROCMON__SEL_ICCHG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((uint32_t)(src) <<\ + 12) & 0x00007000U) +#define RADIO_TOP_PROCMON__SEL_ICCHG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00007000U))) +#define RADIO_TOP_PROCMON__SEL_ICCHG__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field sel_icdisch */ +/** + * @defgroup radio_top_regs_core_sel_icdisch_field sel_icdisch_field + * @brief macros for field sel_icdisch + * @details C-based oscillator discharge current + * @{ + */ +#define RADIO_TOP_PROCMON__SEL_ICDISCH__SHIFT 15 +#define RADIO_TOP_PROCMON__SEL_ICDISCH__WIDTH 3 +#define RADIO_TOP_PROCMON__SEL_ICDISCH__MASK 0x00038000U +#define RADIO_TOP_PROCMON__SEL_ICDISCH__READ(src) \ + (((uint32_t)(src)\ + & 0x00038000U) >> 15) +#define RADIO_TOP_PROCMON__SEL_ICDISCH__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00038000U) +#define RADIO_TOP_PROCMON__SEL_ICDISCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((uint32_t)(src) <<\ + 15) & 0x00038000U) +#define RADIO_TOP_PROCMON__SEL_ICDISCH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00038000U))) +#define RADIO_TOP_PROCMON__SEL_ICDISCH__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field sel_iccomp */ +/** + * @defgroup radio_top_regs_core_sel_iccomp_field sel_iccomp_field + * @brief macros for field sel_iccomp + * @details C-based oscillator comparator bias current + * @{ + */ +#define RADIO_TOP_PROCMON__SEL_ICCOMP__SHIFT 18 +#define RADIO_TOP_PROCMON__SEL_ICCOMP__WIDTH 3 +#define RADIO_TOP_PROCMON__SEL_ICCOMP__MASK 0x001c0000U +#define RADIO_TOP_PROCMON__SEL_ICCOMP__READ(src) \ + (((uint32_t)(src)\ + & 0x001c0000U) >> 18) +#define RADIO_TOP_PROCMON__SEL_ICCOMP__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x001c0000U) +#define RADIO_TOP_PROCMON__SEL_ICCOMP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((uint32_t)(src) <<\ + 18) & 0x001c0000U) +#define RADIO_TOP_PROCMON__SEL_ICCOMP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x001c0000U))) +#define RADIO_TOP_PROCMON__SEL_ICCOMP__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field pm_spare */ +/** + * @defgroup radio_top_regs_core_pm_spare_field pm_spare_field + * @brief macros for field pm_spare + * @details spares + * @{ + */ +#define RADIO_TOP_PROCMON__PM_SPARE__SHIFT 21 +#define RADIO_TOP_PROCMON__PM_SPARE__WIDTH 3 +#define RADIO_TOP_PROCMON__PM_SPARE__MASK 0x00e00000U +#define RADIO_TOP_PROCMON__PM_SPARE__READ(src) \ + (((uint32_t)(src)\ + & 0x00e00000U) >> 21) +#define RADIO_TOP_PROCMON__PM_SPARE__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00e00000U) +#define RADIO_TOP_PROCMON__PM_SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((uint32_t)(src) <<\ + 21) & 0x00e00000U) +#define RADIO_TOP_PROCMON__PM_SPARE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00e00000U))) +#define RADIO_TOP_PROCMON__PM_SPARE__RESET_VALUE 0x00000000U +/** @} */ +#define RADIO_TOP_PROCMON__TYPE uint32_t +#define RADIO_TOP_PROCMON__READ 0x00ffffffU +#define RADIO_TOP_PROCMON__WRITE 0x00ffffffU +#define RADIO_TOP_PROCMON__PRESERVED 0x00000000U +#define RADIO_TOP_PROCMON__RESET_VALUE 0x000db206U + +#endif /* __RADIO_TOP_PROCMON_MACRO__ */ + +/** @} end of procmon */ + +/* macros for BlueprintGlobalNameSpace::radio_top_procmon_result */ +/** + * @defgroup radio_top_regs_core_procmon_result procmon_result + * @brief Process monitor results definitions. + * @{ + */ +#ifndef __RADIO_TOP_PROCMON_RESULT_MACRO__ +#define __RADIO_TOP_PROCMON_RESULT_MACRO__ + +/* macros for field ro_count */ +/** + * @defgroup radio_top_regs_core_ro_count_field ro_count_field + * @brief macros for field ro_count + * @details Ring oscillator counter value + * @{ + */ +#define RADIO_TOP_PROCMON_RESULT__RO_COUNT__SHIFT 0 +#define RADIO_TOP_PROCMON_RESULT__RO_COUNT__WIDTH 16 +#define RADIO_TOP_PROCMON_RESULT__RO_COUNT__MASK 0x0000ffffU +#define RADIO_TOP_PROCMON_RESULT__RO_COUNT__READ(src) \ + ((uint32_t)(src)\ + & 0x0000ffffU) +#define RADIO_TOP_PROCMON_RESULT__RO_COUNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ro_count_done */ +/** + * @defgroup radio_top_regs_core_ro_count_done_field ro_count_done_field + * @brief macros for field ro_count_done + * @details Indicates ring osc counter is finished + * @{ + */ +#define RADIO_TOP_PROCMON_RESULT__RO_COUNT_DONE__SHIFT 16 +#define RADIO_TOP_PROCMON_RESULT__RO_COUNT_DONE__WIDTH 1 +#define RADIO_TOP_PROCMON_RESULT__RO_COUNT_DONE__MASK 0x00010000U +#define RADIO_TOP_PROCMON_RESULT__RO_COUNT_DONE__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define RADIO_TOP_PROCMON_RESULT__RO_COUNT_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define RADIO_TOP_PROCMON_RESULT__RO_COUNT_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define RADIO_TOP_PROCMON_RESULT__RO_COUNT_DONE__RESET_VALUE 0x00000000U +/** @} */ +#define RADIO_TOP_PROCMON_RESULT__TYPE uint32_t +#define RADIO_TOP_PROCMON_RESULT__READ 0x0001ffffU +#define RADIO_TOP_PROCMON_RESULT__PRESERVED 0x00000000U +#define RADIO_TOP_PROCMON_RESULT__RESET_VALUE 0x00000000U + +#endif /* __RADIO_TOP_PROCMON_RESULT_MACRO__ */ + +/** @} end of procmon_result */ + +/* macros for BlueprintGlobalNameSpace::radio_top_core_id */ +/** + * @defgroup radio_top_regs_core_core_id core_id + * @brief Core ID definitions. + * @{ + */ +#ifndef __RADIO_TOP_CORE_ID_MACRO__ +#define __RADIO_TOP_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup radio_top_regs_core_id_field id_field + * @brief macros for field id + * @details RTOP in ASCII + * @{ + */ +#define RADIO_TOP_CORE_ID__ID__SHIFT 0 +#define RADIO_TOP_CORE_ID__ID__WIDTH 32 +#define RADIO_TOP_CORE_ID__ID__MASK 0xffffffffU +#define RADIO_TOP_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define RADIO_TOP_CORE_ID__ID__RESET_VALUE 0x52544f50U +/** @} */ +#define RADIO_TOP_CORE_ID__TYPE uint32_t +#define RADIO_TOP_CORE_ID__READ 0xffffffffU +#define RADIO_TOP_CORE_ID__PRESERVED 0x00000000U +#define RADIO_TOP_CORE_ID__RESET_VALUE 0x52544f50U + +#endif /* __RADIO_TOP_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of RADIO_TOP_REGS_CORE */ +#endif /* __REG_RADIO_TOP_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/rif_regs_core_macro.h b/ATM33xx-5/include/reg/rif_regs_core_macro.h new file mode 100644 index 0000000..cca9dd4 --- /dev/null +++ b/ATM33xx-5/include/reg/rif_regs_core_macro.h @@ -0,0 +1,8632 @@ +/* */ +/* File: rif_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic rif_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_RIF_REGS_CORE_H__ +#define __REG_RIF_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup RIF_REGS_CORE rif_regs_core + * @ingroup AT_REG + * @brief rif_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::RIF_bias */ +/** + * @defgroup rif_regs_core_bias bias + * @brief Bias settings definitions. + * @{ + */ +#ifndef __RIF_BIAS_MACRO__ +#define __RIF_BIAS_MACRO__ + +/* macros for field rbias */ +/** + * @defgroup rif_regs_core_rbias_field rbias_field + * @brief macros for field rbias + * @details RBIAS reference resistor trim + * @{ + */ +#define RIF_BIAS__RBIAS__SHIFT 0 +#define RIF_BIAS__RBIAS__WIDTH 6 +#define RIF_BIAS__RBIAS__MASK 0x0000003fU +#define RIF_BIAS__RBIAS__READ(src) ((uint32_t)(src) & 0x0000003fU) +#define RIF_BIAS__RBIAS__WRITE(src) ((uint32_t)(src) & 0x0000003fU) +#define RIF_BIAS__RBIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define RIF_BIAS__RBIAS__VERIFY(src) (!(((uint32_t)(src) & ~0x0000003fU))) +#define RIF_BIAS__RBIAS__RESET_VALUE 0x00000020U +/** @} */ + +/* macros for field ldo_top_trim */ +/** + * @defgroup rif_regs_core_ldo_top_trim_field ldo_top_trim_field + * @brief macros for field ldo_top_trim + * @details Output voltage trim for radio top LDO + * @{ + */ +#define RIF_BIAS__LDO_TOP_TRIM__SHIFT 6 +#define RIF_BIAS__LDO_TOP_TRIM__WIDTH 4 +#define RIF_BIAS__LDO_TOP_TRIM__MASK 0x000003c0U +#define RIF_BIAS__LDO_TOP_TRIM__READ(src) \ + (((uint32_t)(src)\ + & 0x000003c0U) >> 6) +#define RIF_BIAS__LDO_TOP_TRIM__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000003c0U) +#define RIF_BIAS__LDO_TOP_TRIM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003c0U) | (((uint32_t)(src) <<\ + 6) & 0x000003c0U) +#define RIF_BIAS__LDO_TOP_TRIM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000003c0U))) +#define RIF_BIAS__LDO_TOP_TRIM__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field ldo_trim */ +/** + * @defgroup rif_regs_core_ldo_trim_field ldo_trim_field + * @brief macros for field ldo_trim + * @details Output voltage trim for radio block LDOs + * @{ + */ +#define RIF_BIAS__LDO_TRIM__SHIFT 10 +#define RIF_BIAS__LDO_TRIM__WIDTH 4 +#define RIF_BIAS__LDO_TRIM__MASK 0x00003c00U +#define RIF_BIAS__LDO_TRIM__READ(src) (((uint32_t)(src) & 0x00003c00U) >> 10) +#define RIF_BIAS__LDO_TRIM__WRITE(src) (((uint32_t)(src) << 10) & 0x00003c00U) +#define RIF_BIAS__LDO_TRIM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003c00U) | (((uint32_t)(src) <<\ + 10) & 0x00003c00U) +#define RIF_BIAS__LDO_TRIM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00003c00U))) +#define RIF_BIAS__LDO_TRIM__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field disable_sel_vddldo */ +/** + * @defgroup rif_regs_core_disable_sel_vddldo_field disable_sel_vddldo_field + * @brief macros for field disable_sel_vddldo + * @details Disable switching bandgap supply to LDO output + * @{ + */ +#define RIF_BIAS__DISABLE_SEL_VDDLDO__SHIFT 14 +#define RIF_BIAS__DISABLE_SEL_VDDLDO__WIDTH 1 +#define RIF_BIAS__DISABLE_SEL_VDDLDO__MASK 0x00004000U +#define RIF_BIAS__DISABLE_SEL_VDDLDO__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define RIF_BIAS__DISABLE_SEL_VDDLDO__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define RIF_BIAS__DISABLE_SEL_VDDLDO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define RIF_BIAS__DISABLE_SEL_VDDLDO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define RIF_BIAS__DISABLE_SEL_VDDLDO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define RIF_BIAS__DISABLE_SEL_VDDLDO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define RIF_BIAS__DISABLE_SEL_VDDLDO__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_BIAS__TYPE uint32_t +#define RIF_BIAS__READ 0x00007fffU +#define RIF_BIAS__WRITE 0x00007fffU +#define RIF_BIAS__PRESERVED 0x00000000U +#define RIF_BIAS__RESET_VALUE 0x00001de0U + +#endif /* __RIF_BIAS_MACRO__ */ + +/** @} end of bias */ + +/* macros for BlueprintGlobalNameSpace::RIF_rxbbf */ +/** + * @defgroup rif_regs_core_rxbbf rxbbf + * @brief RXBB filter bandwidth-independent settings definitions. + * @{ + */ +#ifndef __RIF_RXBBF_MACRO__ +#define __RIF_RXBBF_MACRO__ + +/* macros for field tia_rtrim */ +/** + * @defgroup rif_regs_core_tia_rtrim_field tia_rtrim_field + * @brief macros for field tia_rtrim + * @details Resistor trim for TIA feedback, sets absolute TIA gain in 1M mode + * @{ + */ +#define RIF_RXBBF__TIA_RTRIM__SHIFT 0 +#define RIF_RXBBF__TIA_RTRIM__WIDTH 4 +#define RIF_RXBBF__TIA_RTRIM__MASK 0x0000000fU +#define RIF_RXBBF__TIA_RTRIM__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define RIF_RXBBF__TIA_RTRIM__WRITE(src) ((uint32_t)(src) & 0x0000000fU) +#define RIF_RXBBF__TIA_RTRIM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define RIF_RXBBF__TIA_RTRIM__VERIFY(src) (!(((uint32_t)(src) & ~0x0000000fU))) +#define RIF_RXBBF__TIA_RTRIM__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field notch_ctune */ +/** + * @defgroup rif_regs_core_notch_ctune_field notch_ctune_field + * @brief macros for field notch_ctune + * @details Cap setting for twin-T notch when notch_ctune_ovr = 1, now driven from modem cal + * @{ + */ +#define RIF_RXBBF__NOTCH_CTUNE__SHIFT 4 +#define RIF_RXBBF__NOTCH_CTUNE__WIDTH 6 +#define RIF_RXBBF__NOTCH_CTUNE__MASK 0x000003f0U +#define RIF_RXBBF__NOTCH_CTUNE__READ(src) \ + (((uint32_t)(src)\ + & 0x000003f0U) >> 4) +#define RIF_RXBBF__NOTCH_CTUNE__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x000003f0U) +#define RIF_RXBBF__NOTCH_CTUNE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003f0U) | (((uint32_t)(src) <<\ + 4) & 0x000003f0U) +#define RIF_RXBBF__NOTCH_CTUNE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000003f0U))) +#define RIF_RXBBF__NOTCH_CTUNE__RESET_VALUE 0x0000001dU +/** @} */ + +/* macros for field notch_ctune_ovr */ +/** + * @defgroup rif_regs_core_notch_ctune_ovr_field notch_ctune_ovr_field + * @brief macros for field notch_ctune_ovr + * @details Override notch_ctune value from modem + * @{ + */ +#define RIF_RXBBF__NOTCH_CTUNE_OVR__SHIFT 10 +#define RIF_RXBBF__NOTCH_CTUNE_OVR__WIDTH 1 +#define RIF_RXBBF__NOTCH_CTUNE_OVR__MASK 0x00000400U +#define RIF_RXBBF__NOTCH_CTUNE_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define RIF_RXBBF__NOTCH_CTUNE_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define RIF_RXBBF__NOTCH_CTUNE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define RIF_RXBBF__NOTCH_CTUNE_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define RIF_RXBBF__NOTCH_CTUNE_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define RIF_RXBBF__NOTCH_CTUNE_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define RIF_RXBBF__NOTCH_CTUNE_OVR__RESET_VALUE 0x00000001U +/** @} */ +#define RIF_RXBBF__TYPE uint32_t +#define RIF_RXBBF__READ 0x000007ffU +#define RIF_RXBBF__WRITE 0x000007ffU +#define RIF_RXBBF__PRESERVED 0x00000000U +#define RIF_RXBBF__RESET_VALUE 0x000005d8U + +#endif /* __RIF_RXBBF_MACRO__ */ + +/** @} end of rxbbf */ + +/* macros for BlueprintGlobalNameSpace::RIF_rxbbf_1M */ +/** + * @defgroup rif_regs_core_rxbbf_1M rxbbf_1M + * @brief RXBB filter settings for 1M definitions. + * @{ + */ +#ifndef __RIF_RXBBF_1M_MACRO__ +#define __RIF_RXBBF_1M_MACRO__ + +/* macros for field pga_ctune */ +/** + * @defgroup rif_regs_core_pga_ctune_field pga_ctune_field + * @brief macros for field pga_ctune + * @details Cap setting for PGA feedback in 1M mode + * @{ + */ +#define RIF_RXBBF_1M__PGA_CTUNE__SHIFT 0 +#define RIF_RXBBF_1M__PGA_CTUNE__WIDTH 6 +#define RIF_RXBBF_1M__PGA_CTUNE__MASK 0x0000003fU +#define RIF_RXBBF_1M__PGA_CTUNE__READ(src) ((uint32_t)(src) & 0x0000003fU) +#define RIF_RXBBF_1M__PGA_CTUNE__WRITE(src) ((uint32_t)(src) & 0x0000003fU) +#define RIF_RXBBF_1M__PGA_CTUNE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define RIF_RXBBF_1M__PGA_CTUNE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define RIF_RXBBF_1M__PGA_CTUNE__RESET_VALUE 0x0000001fU +/** @} */ + +/* macros for field pga_ctune_lp */ +/** + * @defgroup rif_regs_core_pga_ctune_lp_field pga_ctune_lp_field + * @brief macros for field pga_ctune_lp + * @details Cap setting for PGA feedback in 1M low-power modes + * @{ + */ +#define RIF_RXBBF_1M__PGA_CTUNE_LP__SHIFT 6 +#define RIF_RXBBF_1M__PGA_CTUNE_LP__WIDTH 6 +#define RIF_RXBBF_1M__PGA_CTUNE_LP__MASK 0x00000fc0U +#define RIF_RXBBF_1M__PGA_CTUNE_LP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000fc0U) >> 6) +#define RIF_RXBBF_1M__PGA_CTUNE_LP__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000fc0U) +#define RIF_RXBBF_1M__PGA_CTUNE_LP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((uint32_t)(src) <<\ + 6) & 0x00000fc0U) +#define RIF_RXBBF_1M__PGA_CTUNE_LP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000fc0U))) +#define RIF_RXBBF_1M__PGA_CTUNE_LP__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field rcc_rtrim */ +/** + * @defgroup rif_regs_core_rcc_rtrim_field rcc_rtrim_field + * @brief macros for field rcc_rtrim + * @details Resistor trim for cross-coupling, sets low-IF frequency in 1M mode + * @{ + */ +#define RIF_RXBBF_1M__RCC_RTRIM__SHIFT 12 +#define RIF_RXBBF_1M__RCC_RTRIM__WIDTH 4 +#define RIF_RXBBF_1M__RCC_RTRIM__MASK 0x0000f000U +#define RIF_RXBBF_1M__RCC_RTRIM__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f000U) >> 12) +#define RIF_RXBBF_1M__RCC_RTRIM__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0000f000U) +#define RIF_RXBBF_1M__RCC_RTRIM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((uint32_t)(src) <<\ + 12) & 0x0000f000U) +#define RIF_RXBBF_1M__RCC_RTRIM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0000f000U))) +#define RIF_RXBBF_1M__RCC_RTRIM__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field tia_ctune */ +/** + * @defgroup rif_regs_core_tia_ctune_field tia_ctune_field + * @brief macros for field tia_ctune + * @details Cap setting for TIA feedback in 1M mode + * @{ + */ +#define RIF_RXBBF_1M__TIA_CTUNE__SHIFT 16 +#define RIF_RXBBF_1M__TIA_CTUNE__WIDTH 7 +#define RIF_RXBBF_1M__TIA_CTUNE__MASK 0x007f0000U +#define RIF_RXBBF_1M__TIA_CTUNE__READ(src) \ + (((uint32_t)(src)\ + & 0x007f0000U) >> 16) +#define RIF_RXBBF_1M__TIA_CTUNE__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x007f0000U) +#define RIF_RXBBF_1M__TIA_CTUNE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007f0000U) | (((uint32_t)(src) <<\ + 16) & 0x007f0000U) +#define RIF_RXBBF_1M__TIA_CTUNE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x007f0000U))) +#define RIF_RXBBF_1M__TIA_CTUNE__RESET_VALUE 0x0000002aU +/** @} */ + +/* macros for field tia_ctune_lp */ +/** + * @defgroup rif_regs_core_tia_ctune_lp_field tia_ctune_lp_field + * @brief macros for field tia_ctune_lp + * @details Cap setting for TIA feedback in 1M low-power modes + * @{ + */ +#define RIF_RXBBF_1M__TIA_CTUNE_LP__SHIFT 23 +#define RIF_RXBBF_1M__TIA_CTUNE_LP__WIDTH 7 +#define RIF_RXBBF_1M__TIA_CTUNE_LP__MASK 0x3f800000U +#define RIF_RXBBF_1M__TIA_CTUNE_LP__READ(src) \ + (((uint32_t)(src)\ + & 0x3f800000U) >> 23) +#define RIF_RXBBF_1M__TIA_CTUNE_LP__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x3f800000U) +#define RIF_RXBBF_1M__TIA_CTUNE_LP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f800000U) | (((uint32_t)(src) <<\ + 23) & 0x3f800000U) +#define RIF_RXBBF_1M__TIA_CTUNE_LP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x3f800000U))) +#define RIF_RXBBF_1M__TIA_CTUNE_LP__RESET_VALUE 0x00000004U +/** @} */ +#define RIF_RXBBF_1M__TYPE uint32_t +#define RIF_RXBBF_1M__READ 0x3fffffffU +#define RIF_RXBBF_1M__WRITE 0x3fffffffU +#define RIF_RXBBF_1M__PRESERVED 0x00000000U +#define RIF_RXBBF_1M__RESET_VALUE 0x022a809fU + +#endif /* __RIF_RXBBF_1M_MACRO__ */ + +/** @} end of rxbbf_1M */ + +/* macros for BlueprintGlobalNameSpace::RIF_rxbbf_2M */ +/** + * @defgroup rif_regs_core_rxbbf_2M rxbbf_2M + * @brief RXBB filter settings for 2M definitions. + * @{ + */ +#ifndef __RIF_RXBBF_2M_MACRO__ +#define __RIF_RXBBF_2M_MACRO__ + +/* macros for field pga_ctune */ +/** + * @defgroup rif_regs_core_pga_ctune_field pga_ctune_field + * @brief macros for field pga_ctune + * @details Cap setting for PGA feedback in 2M mode + * @{ + */ +#define RIF_RXBBF_2M__PGA_CTUNE__SHIFT 0 +#define RIF_RXBBF_2M__PGA_CTUNE__WIDTH 6 +#define RIF_RXBBF_2M__PGA_CTUNE__MASK 0x0000003fU +#define RIF_RXBBF_2M__PGA_CTUNE__READ(src) ((uint32_t)(src) & 0x0000003fU) +#define RIF_RXBBF_2M__PGA_CTUNE__WRITE(src) ((uint32_t)(src) & 0x0000003fU) +#define RIF_RXBBF_2M__PGA_CTUNE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define RIF_RXBBF_2M__PGA_CTUNE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define RIF_RXBBF_2M__PGA_CTUNE__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field pga_ctune_lp */ +/** + * @defgroup rif_regs_core_pga_ctune_lp_field pga_ctune_lp_field + * @brief macros for field pga_ctune_lp + * @details Cap setting for PGA feedback in 2M mode low-power modes + * @{ + */ +#define RIF_RXBBF_2M__PGA_CTUNE_LP__SHIFT 6 +#define RIF_RXBBF_2M__PGA_CTUNE_LP__WIDTH 6 +#define RIF_RXBBF_2M__PGA_CTUNE_LP__MASK 0x00000fc0U +#define RIF_RXBBF_2M__PGA_CTUNE_LP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000fc0U) >> 6) +#define RIF_RXBBF_2M__PGA_CTUNE_LP__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000fc0U) +#define RIF_RXBBF_2M__PGA_CTUNE_LP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((uint32_t)(src) <<\ + 6) & 0x00000fc0U) +#define RIF_RXBBF_2M__PGA_CTUNE_LP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000fc0U))) +#define RIF_RXBBF_2M__PGA_CTUNE_LP__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field rcc_rtrim */ +/** + * @defgroup rif_regs_core_rcc_rtrim_field rcc_rtrim_field + * @brief macros for field rcc_rtrim + * @details Resistor trim for cross-coupling, sets low-IF frequency in 2M mode + * @{ + */ +#define RIF_RXBBF_2M__RCC_RTRIM__SHIFT 12 +#define RIF_RXBBF_2M__RCC_RTRIM__WIDTH 4 +#define RIF_RXBBF_2M__RCC_RTRIM__MASK 0x0000f000U +#define RIF_RXBBF_2M__RCC_RTRIM__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f000U) >> 12) +#define RIF_RXBBF_2M__RCC_RTRIM__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0000f000U) +#define RIF_RXBBF_2M__RCC_RTRIM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((uint32_t)(src) <<\ + 12) & 0x0000f000U) +#define RIF_RXBBF_2M__RCC_RTRIM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0000f000U))) +#define RIF_RXBBF_2M__RCC_RTRIM__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field tia_ctune */ +/** + * @defgroup rif_regs_core_tia_ctune_field tia_ctune_field + * @brief macros for field tia_ctune + * @details Cap setting for TIA feedback in 2M mode + * @{ + */ +#define RIF_RXBBF_2M__TIA_CTUNE__SHIFT 16 +#define RIF_RXBBF_2M__TIA_CTUNE__WIDTH 7 +#define RIF_RXBBF_2M__TIA_CTUNE__MASK 0x007f0000U +#define RIF_RXBBF_2M__TIA_CTUNE__READ(src) \ + (((uint32_t)(src)\ + & 0x007f0000U) >> 16) +#define RIF_RXBBF_2M__TIA_CTUNE__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x007f0000U) +#define RIF_RXBBF_2M__TIA_CTUNE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007f0000U) | (((uint32_t)(src) <<\ + 16) & 0x007f0000U) +#define RIF_RXBBF_2M__TIA_CTUNE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x007f0000U))) +#define RIF_RXBBF_2M__TIA_CTUNE__RESET_VALUE 0x00000015U +/** @} */ + +/* macros for field tia_ctune_lp */ +/** + * @defgroup rif_regs_core_tia_ctune_lp_field tia_ctune_lp_field + * @brief macros for field tia_ctune_lp + * @details Cap setting for TIA feedback in 2M low-power modes + * @{ + */ +#define RIF_RXBBF_2M__TIA_CTUNE_LP__SHIFT 23 +#define RIF_RXBBF_2M__TIA_CTUNE_LP__WIDTH 7 +#define RIF_RXBBF_2M__TIA_CTUNE_LP__MASK 0x3f800000U +#define RIF_RXBBF_2M__TIA_CTUNE_LP__READ(src) \ + (((uint32_t)(src)\ + & 0x3f800000U) >> 23) +#define RIF_RXBBF_2M__TIA_CTUNE_LP__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x3f800000U) +#define RIF_RXBBF_2M__TIA_CTUNE_LP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f800000U) | (((uint32_t)(src) <<\ + 23) & 0x3f800000U) +#define RIF_RXBBF_2M__TIA_CTUNE_LP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x3f800000U))) +#define RIF_RXBBF_2M__TIA_CTUNE_LP__RESET_VALUE 0x00000002U +/** @} */ +#define RIF_RXBBF_2M__TYPE uint32_t +#define RIF_RXBBF_2M__READ 0x3fffffffU +#define RIF_RXBBF_2M__WRITE 0x3fffffffU +#define RIF_RXBBF_2M__PRESERVED 0x00000000U +#define RIF_RXBBF_2M__RESET_VALUE 0x01158050U + +#endif /* __RIF_RXBBF_2M_MACRO__ */ + +/** @} end of rxbbf_2M */ + +/* macros for BlueprintGlobalNameSpace::RIF_syntx_modgain */ +/** + * @defgroup rif_regs_core_syntx_modgain syntx_modgain + * @brief Synth TX modgain calibration values definitions. + * @{ + */ +#ifndef __RIF_SYNTX_MODGAIN_MACRO__ +#define __RIF_SYNTX_MODGAIN_MACRO__ + +/* macros for field txmodGain */ +/** + * @defgroup rif_regs_core_txmodGain_field txmodGain_field + * @brief macros for field txmodGain + * @details Sets full-scale gain of the high frequency modulation path in 1Mbps mode + * @{ + */ +#define RIF_SYNTX_MODGAIN__TXMODGAIN__SHIFT 0 +#define RIF_SYNTX_MODGAIN__TXMODGAIN__WIDTH 5 +#define RIF_SYNTX_MODGAIN__TXMODGAIN__MASK 0x0000001fU +#define RIF_SYNTX_MODGAIN__TXMODGAIN__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define RIF_SYNTX_MODGAIN__TXMODGAIN__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define RIF_SYNTX_MODGAIN__TXMODGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define RIF_SYNTX_MODGAIN__TXMODGAIN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define RIF_SYNTX_MODGAIN__TXMODGAIN__RESET_VALUE 0x0000000fU +/** @} */ +#define RIF_SYNTX_MODGAIN__TYPE uint32_t +#define RIF_SYNTX_MODGAIN__READ 0x0000001fU +#define RIF_SYNTX_MODGAIN__WRITE 0x0000001fU +#define RIF_SYNTX_MODGAIN__PRESERVED 0x00000000U +#define RIF_SYNTX_MODGAIN__RESET_VALUE 0x0000000fU + +#endif /* __RIF_SYNTX_MODGAIN_MACRO__ */ + +/** @} end of syntx_modgain */ + +/* macros for BlueprintGlobalNameSpace::RIF_syntx_vcocap */ +/** + * @defgroup rif_regs_core_syntx_vcocap syntx_vcocap + * @brief Synth vcocap calibration values definitions. + * @{ + */ +#ifndef __RIF_SYNTX_VCOCAP_MACRO__ +#define __RIF_SYNTX_VCOCAP_MACRO__ + +/* macros for field vcoCapsCoarse_tx */ +/** + * @defgroup rif_regs_core_vcoCapsCoarse_tx_field vcoCapsCoarse_tx_field + * @brief macros for field vcoCapsCoarse_tx + * @details VCO coarse cap setting that covers at least 2480MHz in TX mode + * @{ + */ +#define RIF_SYNTX_VCOCAP__VCOCAPSCOARSE_TX__SHIFT 0 +#define RIF_SYNTX_VCOCAP__VCOCAPSCOARSE_TX__WIDTH 3 +#define RIF_SYNTX_VCOCAP__VCOCAPSCOARSE_TX__MASK 0x00000007U +#define RIF_SYNTX_VCOCAP__VCOCAPSCOARSE_TX__READ(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define RIF_SYNTX_VCOCAP__VCOCAPSCOARSE_TX__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define RIF_SYNTX_VCOCAP__VCOCAPSCOARSE_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define RIF_SYNTX_VCOCAP__VCOCAPSCOARSE_TX__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define RIF_SYNTX_VCOCAP__VCOCAPSCOARSE_TX__RESET_VALUE 0x00000005U +/** @} */ + +/* macros for field vcoCapsCoarse_rx */ +/** + * @defgroup rif_regs_core_vcoCapsCoarse_rx_field vcoCapsCoarse_rx_field + * @brief macros for field vcoCapsCoarse_rx + * @details VCO coarse cap setting that covers at least 2835MHz (2480MHz RF) in RX mode + * @{ + */ +#define RIF_SYNTX_VCOCAP__VCOCAPSCOARSE_RX__SHIFT 3 +#define RIF_SYNTX_VCOCAP__VCOCAPSCOARSE_RX__WIDTH 3 +#define RIF_SYNTX_VCOCAP__VCOCAPSCOARSE_RX__MASK 0x00000038U +#define RIF_SYNTX_VCOCAP__VCOCAPSCOARSE_RX__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define RIF_SYNTX_VCOCAP__VCOCAPSCOARSE_RX__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define RIF_SYNTX_VCOCAP__VCOCAPSCOARSE_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define RIF_SYNTX_VCOCAP__VCOCAPSCOARSE_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define RIF_SYNTX_VCOCAP__VCOCAPSCOARSE_RX__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field vcoCapsB1_tx */ +/** + * @defgroup rif_regs_core_vcoCapsB1_tx_field vcoCapsB1_tx_field + * @brief macros for field vcoCapsB1_tx + * @details MSBs of vcocap setting that covers high end 2480MHz in TX mode + * @{ + */ +#define RIF_SYNTX_VCOCAP__VCOCAPSB1_TX__SHIFT 6 +#define RIF_SYNTX_VCOCAP__VCOCAPSB1_TX__WIDTH 4 +#define RIF_SYNTX_VCOCAP__VCOCAPSB1_TX__MASK 0x000003c0U +#define RIF_SYNTX_VCOCAP__VCOCAPSB1_TX__READ(src) \ + (((uint32_t)(src)\ + & 0x000003c0U) >> 6) +#define RIF_SYNTX_VCOCAP__VCOCAPSB1_TX__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000003c0U) +#define RIF_SYNTX_VCOCAP__VCOCAPSB1_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003c0U) | (((uint32_t)(src) <<\ + 6) & 0x000003c0U) +#define RIF_SYNTX_VCOCAP__VCOCAPSB1_TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000003c0U))) +#define RIF_SYNTX_VCOCAP__VCOCAPSB1_TX__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field vcoCapsB1_rx */ +/** + * @defgroup rif_regs_core_vcoCapsB1_rx_field vcoCapsB1_rx_field + * @brief macros for field vcoCapsB1_rx + * @details MSBs of vcocap setting that covers high end 2835MHz (2480MHz RF) in RX mode + * @{ + */ +#define RIF_SYNTX_VCOCAP__VCOCAPSB1_RX__SHIFT 10 +#define RIF_SYNTX_VCOCAP__VCOCAPSB1_RX__WIDTH 4 +#define RIF_SYNTX_VCOCAP__VCOCAPSB1_RX__MASK 0x00003c00U +#define RIF_SYNTX_VCOCAP__VCOCAPSB1_RX__READ(src) \ + (((uint32_t)(src)\ + & 0x00003c00U) >> 10) +#define RIF_SYNTX_VCOCAP__VCOCAPSB1_RX__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00003c00U) +#define RIF_SYNTX_VCOCAP__VCOCAPSB1_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003c00U) | (((uint32_t)(src) <<\ + 10) & 0x00003c00U) +#define RIF_SYNTX_VCOCAP__VCOCAPSB1_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00003c00U))) +#define RIF_SYNTX_VCOCAP__VCOCAPSB1_RX__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field vcoCapsB0_tx */ +/** + * @defgroup rif_regs_core_vcoCapsB0_tx_field vcoCapsB0_tx_field + * @brief macros for field vcoCapsB0_tx + * @details MSBs of vcocap setting that covers low end 2400MHz in TX mode + * @{ + */ +#define RIF_SYNTX_VCOCAP__VCOCAPSB0_TX__SHIFT 14 +#define RIF_SYNTX_VCOCAP__VCOCAPSB0_TX__WIDTH 4 +#define RIF_SYNTX_VCOCAP__VCOCAPSB0_TX__MASK 0x0003c000U +#define RIF_SYNTX_VCOCAP__VCOCAPSB0_TX__READ(src) \ + (((uint32_t)(src)\ + & 0x0003c000U) >> 14) +#define RIF_SYNTX_VCOCAP__VCOCAPSB0_TX__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0003c000U) +#define RIF_SYNTX_VCOCAP__VCOCAPSB0_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003c000U) | (((uint32_t)(src) <<\ + 14) & 0x0003c000U) +#define RIF_SYNTX_VCOCAP__VCOCAPSB0_TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0003c000U))) +#define RIF_SYNTX_VCOCAP__VCOCAPSB0_TX__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field vcoCapsB0_rx */ +/** + * @defgroup rif_regs_core_vcoCapsB0_rx_field vcoCapsB0_rx_field + * @brief macros for field vcoCapsB0_rx + * @details MSBs of vcocap setting that covers low end 2742MHz (2400MHz RF) in RX mode + * @{ + */ +#define RIF_SYNTX_VCOCAP__VCOCAPSB0_RX__SHIFT 18 +#define RIF_SYNTX_VCOCAP__VCOCAPSB0_RX__WIDTH 4 +#define RIF_SYNTX_VCOCAP__VCOCAPSB0_RX__MASK 0x003c0000U +#define RIF_SYNTX_VCOCAP__VCOCAPSB0_RX__READ(src) \ + (((uint32_t)(src)\ + & 0x003c0000U) >> 18) +#define RIF_SYNTX_VCOCAP__VCOCAPSB0_RX__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x003c0000U) +#define RIF_SYNTX_VCOCAP__VCOCAPSB0_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003c0000U) | (((uint32_t)(src) <<\ + 18) & 0x003c0000U) +#define RIF_SYNTX_VCOCAP__VCOCAPSB0_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x003c0000U))) +#define RIF_SYNTX_VCOCAP__VCOCAPSB0_RX__RESET_VALUE 0x00000008U +/** @} */ +#define RIF_SYNTX_VCOCAP__TYPE uint32_t +#define RIF_SYNTX_VCOCAP__READ 0x003fffffU +#define RIF_SYNTX_VCOCAP__WRITE 0x003fffffU +#define RIF_SYNTX_VCOCAP__PRESERVED 0x00000000U +#define RIF_SYNTX_VCOCAP__RESET_VALUE 0x00220ccdU + +#endif /* __RIF_SYNTX_VCOCAP_MACRO__ */ + +/** @} end of syntx_vcocap */ + +/* macros for BlueprintGlobalNameSpace::RIF_lna */ +/** + * @defgroup rif_regs_core_lna lna + * @brief LNA step size from ATE cal definitions. + * @{ + */ +#ifndef __RIF_LNA_MACRO__ +#define __RIF_LNA_MACRO__ + +/* macros for field step1 */ +/** + * @defgroup rif_regs_core_step1_field step1_field + * @brief macros for field step1 + * @details Step size in dB from lnagain = 0 to minimum lnagain setting used other than 0 or 1 + * @{ + */ +#define RIF_LNA__STEP1__SHIFT 0 +#define RIF_LNA__STEP1__WIDTH 7 +#define RIF_LNA__STEP1__MASK 0x0000007fU +#define RIF_LNA__STEP1__READ(src) ((uint32_t)(src) & 0x0000007fU) +#define RIF_LNA__STEP1__WRITE(src) ((uint32_t)(src) & 0x0000007fU) +#define RIF_LNA__STEP1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define RIF_LNA__STEP1__VERIFY(src) (!(((uint32_t)(src) & ~0x0000007fU))) +#define RIF_LNA__STEP1__RESET_VALUE 0x00000016U +/** @} */ + +/* macros for field step2 */ +/** + * @defgroup rif_regs_core_step2_field step2_field + * @brief macros for field step2 + * @details Step size in dB from lnagain = 1 to minimum lnagain setting used other than 0 or 1 + * @{ + */ +#define RIF_LNA__STEP2__SHIFT 7 +#define RIF_LNA__STEP2__WIDTH 7 +#define RIF_LNA__STEP2__MASK 0x00003f80U +#define RIF_LNA__STEP2__READ(src) (((uint32_t)(src) & 0x00003f80U) >> 7) +#define RIF_LNA__STEP2__WRITE(src) (((uint32_t)(src) << 7) & 0x00003f80U) +#define RIF_LNA__STEP2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((uint32_t)(src) <<\ + 7) & 0x00003f80U) +#define RIF_LNA__STEP2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00003f80U))) +#define RIF_LNA__STEP2__RESET_VALUE 0x00000011U +/** @} */ +#define RIF_LNA__TYPE uint32_t +#define RIF_LNA__READ 0x00003fffU +#define RIF_LNA__WRITE 0x00003fffU +#define RIF_LNA__PRESERVED 0x00000000U +#define RIF_LNA__RESET_VALUE 0x00000896U + +#endif /* __RIF_LNA_MACRO__ */ + +/** @} end of lna */ + +/* macros for BlueprintGlobalNameSpace::RIF_rgt */ +/** + * @defgroup rif_regs_core_rgt rgt + * @brief Reduced Gain Table control definitions. + * @{ + */ +#ifndef __RIF_RGT_MACRO__ +#define __RIF_RGT_MACRO__ + +/* macros for field use_lna_reduced_gain_table */ +/** + * @defgroup rif_regs_core_use_lna_reduced_gain_table_field use_lna_reduced_gain_table_field + * @brief macros for field use_lna_reduced_gain_table + * @{ + */ +#define RIF_RGT__USE_LNA_REDUCED_GAIN_TABLE__SHIFT 0 +#define RIF_RGT__USE_LNA_REDUCED_GAIN_TABLE__WIDTH 1 +#define RIF_RGT__USE_LNA_REDUCED_GAIN_TABLE__MASK 0x00000001U +#define RIF_RGT__USE_LNA_REDUCED_GAIN_TABLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RIF_RGT__USE_LNA_REDUCED_GAIN_TABLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define RIF_RGT__USE_LNA_REDUCED_GAIN_TABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define RIF_RGT__USE_LNA_REDUCED_GAIN_TABLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define RIF_RGT__USE_LNA_REDUCED_GAIN_TABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define RIF_RGT__USE_LNA_REDUCED_GAIN_TABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define RIF_RGT__USE_LNA_REDUCED_GAIN_TABLE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field lna0_thresh */ +/** + * @defgroup rif_regs_core_lna0_thresh_field lna0_thresh_field + * @brief macros for field lna0_thresh + * @details RX gain index to switch between lnagain=0 and lnagain=1 + * @{ + */ +#define RIF_RGT__LNA0_THRESH__SHIFT 1 +#define RIF_RGT__LNA0_THRESH__WIDTH 7 +#define RIF_RGT__LNA0_THRESH__MASK 0x000000feU +#define RIF_RGT__LNA0_THRESH__READ(src) (((uint32_t)(src) & 0x000000feU) >> 1) +#define RIF_RGT__LNA0_THRESH__WRITE(src) (((uint32_t)(src) << 1) & 0x000000feU) +#define RIF_RGT__LNA0_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000feU) | (((uint32_t)(src) <<\ + 1) & 0x000000feU) +#define RIF_RGT__LNA0_THRESH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x000000feU))) +#define RIF_RGT__LNA0_THRESH__RESET_VALUE 0x0000000aU +/** @} */ + +/* macros for field lna1_thresh */ +/** + * @defgroup rif_regs_core_lna1_thresh_field lna1_thresh_field + * @brief macros for field lna1_thresh + * @details RX gain index to switch between lnagain=1 and which ever is chosen as the next highest lnagain setting + * @{ + */ +#define RIF_RGT__LNA1_THRESH__SHIFT 8 +#define RIF_RGT__LNA1_THRESH__WIDTH 7 +#define RIF_RGT__LNA1_THRESH__MASK 0x00007f00U +#define RIF_RGT__LNA1_THRESH__READ(src) (((uint32_t)(src) & 0x00007f00U) >> 8) +#define RIF_RGT__LNA1_THRESH__WRITE(src) (((uint32_t)(src) << 8) & 0x00007f00U) +#define RIF_RGT__LNA1_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007f00U) | (((uint32_t)(src) <<\ + 8) & 0x00007f00U) +#define RIF_RGT__LNA1_THRESH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00007f00U))) +#define RIF_RGT__LNA1_THRESH__RESET_VALUE 0x00000014U +/** @} */ + +/* macros for field lna_step_offset */ +/** + * @defgroup rif_regs_core_lna_step_offset_field lna_step_offset_field + * @brief macros for field lna_step_offset + * @details Signed. Offset to apply to lna_step1/2 (which come from ATE) depending on minimum lnagain setting used that is not 0 or 1 + * @{ + */ +#define RIF_RGT__LNA_STEP_OFFSET__SHIFT 15 +#define RIF_RGT__LNA_STEP_OFFSET__WIDTH 7 +#define RIF_RGT__LNA_STEP_OFFSET__MASK 0x003f8000U +#define RIF_RGT__LNA_STEP_OFFSET__READ(src) \ + (((uint32_t)(src)\ + & 0x003f8000U) >> 15) +#define RIF_RGT__LNA_STEP_OFFSET__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x003f8000U) +#define RIF_RGT__LNA_STEP_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f8000U) | (((uint32_t)(src) <<\ + 15) & 0x003f8000U) +#define RIF_RGT__LNA_STEP_OFFSET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x003f8000U))) +#define RIF_RGT__LNA_STEP_OFFSET__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field xlna_step */ +/** + * @defgroup rif_regs_core_xlna_step_field xlna_step_field + * @brief macros for field xlna_step + * @details Change in signal size between XLNA on and off, in dB + * @{ + */ +#define RIF_RGT__XLNA_STEP__SHIFT 22 +#define RIF_RGT__XLNA_STEP__WIDTH 6 +#define RIF_RGT__XLNA_STEP__MASK 0x0fc00000U +#define RIF_RGT__XLNA_STEP__READ(src) (((uint32_t)(src) & 0x0fc00000U) >> 22) +#define RIF_RGT__XLNA_STEP__WRITE(src) (((uint32_t)(src) << 22) & 0x0fc00000U) +#define RIF_RGT__XLNA_STEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fc00000U) | (((uint32_t)(src) <<\ + 22) & 0x0fc00000U) +#define RIF_RGT__XLNA_STEP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x0fc00000U))) +#define RIF_RGT__XLNA_STEP__RESET_VALUE 0x00000014U +/** @} */ +#define RIF_RGT__TYPE uint32_t +#define RIF_RGT__READ 0x0fffffffU +#define RIF_RGT__WRITE 0x0fffffffU +#define RIF_RGT__PRESERVED 0x00000000U +#define RIF_RGT__RESET_VALUE 0x05001415U + +#endif /* __RIF_RGT_MACRO__ */ + +/** @} end of rgt */ + +/* macros for BlueprintGlobalNameSpace::RIF_rgthw */ +/** + * @defgroup rif_regs_core_rgthw rgthw + * @brief Reduced Gain Table HW-only registers for register management definitions. + * @{ + */ +#ifndef __RIF_RGTHW_MACRO__ +#define __RIF_RGTHW_MACRO__ + +/* macros for field bb_table_offset */ +/** + * @defgroup rif_regs_core_bb_table_offset_field bb_table_offset_field + * @brief macros for field bb_table_offset + * @details RX gain index offset of bb-only table with respect to variable-LNA setting table. + * @{ + */ +#define RIF_RGTHW__BB_TABLE_OFFSET__SHIFT 0 +#define RIF_RGTHW__BB_TABLE_OFFSET__WIDTH 7 +#define RIF_RGTHW__BB_TABLE_OFFSET__MASK 0x0000007fU +#define RIF_RGTHW__BB_TABLE_OFFSET__READ(src) ((uint32_t)(src) & 0x0000007fU) +#define RIF_RGTHW__BB_TABLE_OFFSET__WRITE(src) ((uint32_t)(src) & 0x0000007fU) +#define RIF_RGTHW__BB_TABLE_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define RIF_RGTHW__BB_TABLE_OFFSET__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000007fU))) +#define RIF_RGTHW__BB_TABLE_OFFSET__RESET_VALUE 0x0000003cU +/** @} */ + +/* macros for field max_bb_index */ +/** + * @defgroup rif_regs_core_max_bb_index_field max_bb_index_field + * @brief macros for field max_bb_index + * @details Maximum allowed index for bb-only table, relative to its base + * @{ + */ +#define RIF_RGTHW__MAX_BB_INDEX__SHIFT 7 +#define RIF_RGTHW__MAX_BB_INDEX__WIDTH 7 +#define RIF_RGTHW__MAX_BB_INDEX__MASK 0x00003f80U +#define RIF_RGTHW__MAX_BB_INDEX__READ(src) \ + (((uint32_t)(src)\ + & 0x00003f80U) >> 7) +#define RIF_RGTHW__MAX_BB_INDEX__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00003f80U) +#define RIF_RGTHW__MAX_BB_INDEX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((uint32_t)(src) <<\ + 7) & 0x00003f80U) +#define RIF_RGTHW__MAX_BB_INDEX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00003f80U))) +#define RIF_RGTHW__MAX_BB_INDEX__RESET_VALUE 0x0000001eU +/** @} */ + +/* macros for field max_rgt_index */ +/** + * @defgroup rif_regs_core_max_rgt_index_field max_rgt_index_field + * @brief macros for field max_rgt_index + * @details Maximum allowed index for reduced gain table, for portion that includes LNA + * @{ + */ +#define RIF_RGTHW__MAX_RGT_INDEX__SHIFT 14 +#define RIF_RGTHW__MAX_RGT_INDEX__WIDTH 7 +#define RIF_RGTHW__MAX_RGT_INDEX__MASK 0x001fc000U +#define RIF_RGTHW__MAX_RGT_INDEX__READ(src) \ + (((uint32_t)(src)\ + & 0x001fc000U) >> 14) +#define RIF_RGTHW__MAX_RGT_INDEX__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x001fc000U) +#define RIF_RGTHW__MAX_RGT_INDEX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001fc000U) | (((uint32_t)(src) <<\ + 14) & 0x001fc000U) +#define RIF_RGTHW__MAX_RGT_INDEX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x001fc000U))) +#define RIF_RGTHW__MAX_RGT_INDEX__RESET_VALUE 0x00000036U +/** @} */ +#define RIF_RGTHW__TYPE uint32_t +#define RIF_RGTHW__READ 0x001fffffU +#define RIF_RGTHW__WRITE 0x001fffffU +#define RIF_RGTHW__PRESERVED 0x00000000U +#define RIF_RGTHW__RESET_VALUE 0x000d8f3cU + +#endif /* __RIF_RGTHW_MACRO__ */ + +/** @} end of rgthw */ + +/* macros for BlueprintGlobalNameSpace::RIF_txgain0 */ +/** + * @defgroup rif_regs_core_txgain0 txgain0 + * @brief TX power table entries 0 to 2, maps to pa_stages[2:0], pa_ref[5:0] definitions. + * @{ + */ +#ifndef __RIF_TXGAIN0_MACRO__ +#define __RIF_TXGAIN0_MACRO__ + +/* macros for field entry0 */ +/** + * @defgroup rif_regs_core_entry0_field entry0_field + * @brief macros for field entry0 + * @details TX power level entry 0, -20dBm + * @{ + */ +#define RIF_TXGAIN0__ENTRY0__SHIFT 0 +#define RIF_TXGAIN0__ENTRY0__WIDTH 9 +#define RIF_TXGAIN0__ENTRY0__MASK 0x000001ffU +#define RIF_TXGAIN0__ENTRY0__READ(src) ((uint32_t)(src) & 0x000001ffU) +#define RIF_TXGAIN0__ENTRY0__WRITE(src) ((uint32_t)(src) & 0x000001ffU) +#define RIF_TXGAIN0__ENTRY0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((uint32_t)(src) &\ + 0x000001ffU) +#define RIF_TXGAIN0__ENTRY0__VERIFY(src) (!(((uint32_t)(src) & ~0x000001ffU))) +#define RIF_TXGAIN0__ENTRY0__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field entry1 */ +/** + * @defgroup rif_regs_core_entry1_field entry1_field + * @brief macros for field entry1 + * @details TX power level entry 1, -10dBm + * @{ + */ +#define RIF_TXGAIN0__ENTRY1__SHIFT 9 +#define RIF_TXGAIN0__ENTRY1__WIDTH 9 +#define RIF_TXGAIN0__ENTRY1__MASK 0x0003fe00U +#define RIF_TXGAIN0__ENTRY1__READ(src) (((uint32_t)(src) & 0x0003fe00U) >> 9) +#define RIF_TXGAIN0__ENTRY1__WRITE(src) (((uint32_t)(src) << 9) & 0x0003fe00U) +#define RIF_TXGAIN0__ENTRY1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0003fe00U) +#define RIF_TXGAIN0__ENTRY1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0003fe00U))) +#define RIF_TXGAIN0__ENTRY1__RESET_VALUE 0x00000027U +/** @} */ + +/* macros for field entry2 */ +/** + * @defgroup rif_regs_core_entry2_field entry2_field + * @brief macros for field entry2 + * @details TX power level entry 2, -8dBm + * @{ + */ +#define RIF_TXGAIN0__ENTRY2__SHIFT 18 +#define RIF_TXGAIN0__ENTRY2__WIDTH 9 +#define RIF_TXGAIN0__ENTRY2__MASK 0x07fc0000U +#define RIF_TXGAIN0__ENTRY2__READ(src) (((uint32_t)(src) & 0x07fc0000U) >> 18) +#define RIF_TXGAIN0__ENTRY2__WRITE(src) (((uint32_t)(src) << 18) & 0x07fc0000U) +#define RIF_TXGAIN0__ENTRY2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07fc0000U) | (((uint32_t)(src) <<\ + 18) & 0x07fc0000U) +#define RIF_TXGAIN0__ENTRY2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x07fc0000U))) +#define RIF_TXGAIN0__ENTRY2__RESET_VALUE 0x00000030U +/** @} */ + +/* macros for field pa_supconf0 */ +/** + * @defgroup rif_regs_core_pa_supconf0_field pa_supconf0_field + * @brief macros for field pa_supconf0 + * @details PA input supply configuration, 00: VDDPA passthrough with NMOS1 and PMOS, 01: AVDD with NMOS0, 10: VDDPA with NMOS1, 11: VDDPA with PMOS + * @{ + */ +#define RIF_TXGAIN0__PA_SUPCONF0__SHIFT 27 +#define RIF_TXGAIN0__PA_SUPCONF0__WIDTH 2 +#define RIF_TXGAIN0__PA_SUPCONF0__MASK 0x18000000U +#define RIF_TXGAIN0__PA_SUPCONF0__READ(src) \ + (((uint32_t)(src)\ + & 0x18000000U) >> 27) +#define RIF_TXGAIN0__PA_SUPCONF0__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x18000000U) +#define RIF_TXGAIN0__PA_SUPCONF0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x18000000U) | (((uint32_t)(src) <<\ + 27) & 0x18000000U) +#define RIF_TXGAIN0__PA_SUPCONF0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x18000000U))) +#define RIF_TXGAIN0__PA_SUPCONF0__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pa_refconf0 */ +/** + * @defgroup rif_regs_core_pa_refconf0_field pa_refconf0_field + * @brief macros for field pa_refconf0 + * @details PA LDO reference configuration max voltage, 00: AVDD, 01: VDDPA, 10: IR 1.0V, 11: IR 1.8V + * @{ + */ +#define RIF_TXGAIN0__PA_REFCONF0__SHIFT 29 +#define RIF_TXGAIN0__PA_REFCONF0__WIDTH 2 +#define RIF_TXGAIN0__PA_REFCONF0__MASK 0x60000000U +#define RIF_TXGAIN0__PA_REFCONF0__READ(src) \ + (((uint32_t)(src)\ + & 0x60000000U) >> 29) +#define RIF_TXGAIN0__PA_REFCONF0__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x60000000U) +#define RIF_TXGAIN0__PA_REFCONF0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x60000000U) | (((uint32_t)(src) <<\ + 29) & 0x60000000U) +#define RIF_TXGAIN0__PA_REFCONF0__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x60000000U))) +#define RIF_TXGAIN0__PA_REFCONF0__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_TXGAIN0__TYPE uint32_t +#define RIF_TXGAIN0__READ 0x7fffffffU +#define RIF_TXGAIN0__WRITE 0x7fffffffU +#define RIF_TXGAIN0__PRESERVED 0x00000000U +#define RIF_TXGAIN0__RESET_VALUE 0x08c04e10U + +#endif /* __RIF_TXGAIN0_MACRO__ */ + +/** @} end of txgain0 */ + +/* macros for BlueprintGlobalNameSpace::RIF_txgain1 */ +/** + * @defgroup rif_regs_core_txgain1 txgain1 + * @brief TX power table entries 3 to 5, maps to pa_stages[2:0], pa_ref[5:0] definitions. + * @{ + */ +#ifndef __RIF_TXGAIN1_MACRO__ +#define __RIF_TXGAIN1_MACRO__ + +/* macros for field entry3 */ +/** + * @defgroup rif_regs_core_entry3_field entry3_field + * @brief macros for field entry3 + * @details TX power level entry 3, -6dBm + * @{ + */ +#define RIF_TXGAIN1__ENTRY3__SHIFT 0 +#define RIF_TXGAIN1__ENTRY3__WIDTH 9 +#define RIF_TXGAIN1__ENTRY3__MASK 0x000001ffU +#define RIF_TXGAIN1__ENTRY3__READ(src) ((uint32_t)(src) & 0x000001ffU) +#define RIF_TXGAIN1__ENTRY3__WRITE(src) ((uint32_t)(src) & 0x000001ffU) +#define RIF_TXGAIN1__ENTRY3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((uint32_t)(src) &\ + 0x000001ffU) +#define RIF_TXGAIN1__ENTRY3__VERIFY(src) (!(((uint32_t)(src) & ~0x000001ffU))) +#define RIF_TXGAIN1__ENTRY3__RESET_VALUE 0x00000067U +/** @} */ + +/* macros for field entry4 */ +/** + * @defgroup rif_regs_core_entry4_field entry4_field + * @brief macros for field entry4 + * @details TX power level entry 4, -4dBm + * @{ + */ +#define RIF_TXGAIN1__ENTRY4__SHIFT 9 +#define RIF_TXGAIN1__ENTRY4__WIDTH 9 +#define RIF_TXGAIN1__ENTRY4__MASK 0x0003fe00U +#define RIF_TXGAIN1__ENTRY4__READ(src) (((uint32_t)(src) & 0x0003fe00U) >> 9) +#define RIF_TXGAIN1__ENTRY4__WRITE(src) (((uint32_t)(src) << 9) & 0x0003fe00U) +#define RIF_TXGAIN1__ENTRY4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0003fe00U) +#define RIF_TXGAIN1__ENTRY4__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0003fe00U))) +#define RIF_TXGAIN1__ENTRY4__RESET_VALUE 0x0000006eU +/** @} */ + +/* macros for field entry5 */ +/** + * @defgroup rif_regs_core_entry5_field entry5_field + * @brief macros for field entry5 + * @details TX power level entry 5, -2dBm + * @{ + */ +#define RIF_TXGAIN1__ENTRY5__SHIFT 18 +#define RIF_TXGAIN1__ENTRY5__WIDTH 9 +#define RIF_TXGAIN1__ENTRY5__MASK 0x07fc0000U +#define RIF_TXGAIN1__ENTRY5__READ(src) (((uint32_t)(src) & 0x07fc0000U) >> 18) +#define RIF_TXGAIN1__ENTRY5__WRITE(src) (((uint32_t)(src) << 18) & 0x07fc0000U) +#define RIF_TXGAIN1__ENTRY5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07fc0000U) | (((uint32_t)(src) <<\ + 18) & 0x07fc0000U) +#define RIF_TXGAIN1__ENTRY5__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x07fc0000U))) +#define RIF_TXGAIN1__ENTRY5__RESET_VALUE 0x00000079U +/** @} */ + +/* macros for field pa_supconf1 */ +/** + * @defgroup rif_regs_core_pa_supconf1_field pa_supconf1_field + * @brief macros for field pa_supconf1 + * @details PA input supply configuration, 00: VDDPA passthrough with NMOS1 and PMOS, 01: AVDD with NMOS0, 10: VDDPA with NMOS1, 11: VDDPA with PMOS + * @{ + */ +#define RIF_TXGAIN1__PA_SUPCONF1__SHIFT 27 +#define RIF_TXGAIN1__PA_SUPCONF1__WIDTH 2 +#define RIF_TXGAIN1__PA_SUPCONF1__MASK 0x18000000U +#define RIF_TXGAIN1__PA_SUPCONF1__READ(src) \ + (((uint32_t)(src)\ + & 0x18000000U) >> 27) +#define RIF_TXGAIN1__PA_SUPCONF1__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x18000000U) +#define RIF_TXGAIN1__PA_SUPCONF1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x18000000U) | (((uint32_t)(src) <<\ + 27) & 0x18000000U) +#define RIF_TXGAIN1__PA_SUPCONF1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x18000000U))) +#define RIF_TXGAIN1__PA_SUPCONF1__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pa_refconf1 */ +/** + * @defgroup rif_regs_core_pa_refconf1_field pa_refconf1_field + * @brief macros for field pa_refconf1 + * @details PA LDO reference configuration max voltage, 00: AVDD, 01: VDDPA, 10: IR 1.0V, 11: IR 1.8V + * @{ + */ +#define RIF_TXGAIN1__PA_REFCONF1__SHIFT 29 +#define RIF_TXGAIN1__PA_REFCONF1__WIDTH 2 +#define RIF_TXGAIN1__PA_REFCONF1__MASK 0x60000000U +#define RIF_TXGAIN1__PA_REFCONF1__READ(src) \ + (((uint32_t)(src)\ + & 0x60000000U) >> 29) +#define RIF_TXGAIN1__PA_REFCONF1__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x60000000U) +#define RIF_TXGAIN1__PA_REFCONF1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x60000000U) | (((uint32_t)(src) <<\ + 29) & 0x60000000U) +#define RIF_TXGAIN1__PA_REFCONF1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x60000000U))) +#define RIF_TXGAIN1__PA_REFCONF1__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_TXGAIN1__TYPE uint32_t +#define RIF_TXGAIN1__READ 0x7fffffffU +#define RIF_TXGAIN1__WRITE 0x7fffffffU +#define RIF_TXGAIN1__PRESERVED 0x00000000U +#define RIF_TXGAIN1__RESET_VALUE 0x09e4dc67U + +#endif /* __RIF_TXGAIN1_MACRO__ */ + +/** @} end of txgain1 */ + +/* macros for BlueprintGlobalNameSpace::RIF_txgain2 */ +/** + * @defgroup rif_regs_core_txgain2 txgain2 + * @brief TX power table entries 6 to 8, maps to pa_stages[2:0], pa_ref[5:0] definitions. + * @{ + */ +#ifndef __RIF_TXGAIN2_MACRO__ +#define __RIF_TXGAIN2_MACRO__ + +/* macros for field entry6 */ +/** + * @defgroup rif_regs_core_entry6_field entry6_field + * @brief macros for field entry6 + * @details TX power level entry 6, 0dBm + * @{ + */ +#define RIF_TXGAIN2__ENTRY6__SHIFT 0 +#define RIF_TXGAIN2__ENTRY6__WIDTH 9 +#define RIF_TXGAIN2__ENTRY6__MASK 0x000001ffU +#define RIF_TXGAIN2__ENTRY6__READ(src) ((uint32_t)(src) & 0x000001ffU) +#define RIF_TXGAIN2__ENTRY6__WRITE(src) ((uint32_t)(src) & 0x000001ffU) +#define RIF_TXGAIN2__ENTRY6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((uint32_t)(src) &\ + 0x000001ffU) +#define RIF_TXGAIN2__ENTRY6__VERIFY(src) (!(((uint32_t)(src) & ~0x000001ffU))) +#define RIF_TXGAIN2__ENTRY6__RESET_VALUE 0x000000b9U +/** @} */ + +/* macros for field entry7 */ +/** + * @defgroup rif_regs_core_entry7_field entry7_field + * @brief macros for field entry7 + * @details TX power level entry 7, 2dBm + * @{ + */ +#define RIF_TXGAIN2__ENTRY7__SHIFT 9 +#define RIF_TXGAIN2__ENTRY7__WIDTH 9 +#define RIF_TXGAIN2__ENTRY7__MASK 0x0003fe00U +#define RIF_TXGAIN2__ENTRY7__READ(src) (((uint32_t)(src) & 0x0003fe00U) >> 9) +#define RIF_TXGAIN2__ENTRY7__WRITE(src) (((uint32_t)(src) << 9) & 0x0003fe00U) +#define RIF_TXGAIN2__ENTRY7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0003fe00U) +#define RIF_TXGAIN2__ENTRY7__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0003fe00U))) +#define RIF_TXGAIN2__ENTRY7__RESET_VALUE 0x000000f8U +/** @} */ + +/* macros for field entry8 */ +/** + * @defgroup rif_regs_core_entry8_field entry8_field + * @brief macros for field entry8 + * @details TX power level entry 8, 4dBm + * @{ + */ +#define RIF_TXGAIN2__ENTRY8__SHIFT 18 +#define RIF_TXGAIN2__ENTRY8__WIDTH 9 +#define RIF_TXGAIN2__ENTRY8__MASK 0x07fc0000U +#define RIF_TXGAIN2__ENTRY8__READ(src) (((uint32_t)(src) & 0x07fc0000U) >> 18) +#define RIF_TXGAIN2__ENTRY8__WRITE(src) (((uint32_t)(src) << 18) & 0x07fc0000U) +#define RIF_TXGAIN2__ENTRY8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07fc0000U) | (((uint32_t)(src) <<\ + 18) & 0x07fc0000U) +#define RIF_TXGAIN2__ENTRY8__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x07fc0000U))) +#define RIF_TXGAIN2__ENTRY8__RESET_VALUE 0x0000013fU +/** @} */ + +/* macros for field pa_supconf2 */ +/** + * @defgroup rif_regs_core_pa_supconf2_field pa_supconf2_field + * @brief macros for field pa_supconf2 + * @details PA input supply configuration, 00: VDDPA passthrough with NMOS1 and PMOS, 01: AVDD with NMOS0, 10: VDDPA with NMOS1, 11: VDDPA with PMOS + * @{ + */ +#define RIF_TXGAIN2__PA_SUPCONF2__SHIFT 27 +#define RIF_TXGAIN2__PA_SUPCONF2__WIDTH 2 +#define RIF_TXGAIN2__PA_SUPCONF2__MASK 0x18000000U +#define RIF_TXGAIN2__PA_SUPCONF2__READ(src) \ + (((uint32_t)(src)\ + & 0x18000000U) >> 27) +#define RIF_TXGAIN2__PA_SUPCONF2__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x18000000U) +#define RIF_TXGAIN2__PA_SUPCONF2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x18000000U) | (((uint32_t)(src) <<\ + 27) & 0x18000000U) +#define RIF_TXGAIN2__PA_SUPCONF2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x18000000U))) +#define RIF_TXGAIN2__PA_SUPCONF2__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pa_refconf2 */ +/** + * @defgroup rif_regs_core_pa_refconf2_field pa_refconf2_field + * @brief macros for field pa_refconf2 + * @details PA LDO reference configuration max voltage, 00: AVDD, 01: VDDPA, 10: IR 1.0V, 11: IR 1.8V + * @{ + */ +#define RIF_TXGAIN2__PA_REFCONF2__SHIFT 29 +#define RIF_TXGAIN2__PA_REFCONF2__WIDTH 2 +#define RIF_TXGAIN2__PA_REFCONF2__MASK 0x60000000U +#define RIF_TXGAIN2__PA_REFCONF2__READ(src) \ + (((uint32_t)(src)\ + & 0x60000000U) >> 29) +#define RIF_TXGAIN2__PA_REFCONF2__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x60000000U) +#define RIF_TXGAIN2__PA_REFCONF2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x60000000U) | (((uint32_t)(src) <<\ + 29) & 0x60000000U) +#define RIF_TXGAIN2__PA_REFCONF2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x60000000U))) +#define RIF_TXGAIN2__PA_REFCONF2__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_TXGAIN2__TYPE uint32_t +#define RIF_TXGAIN2__READ 0x7fffffffU +#define RIF_TXGAIN2__WRITE 0x7fffffffU +#define RIF_TXGAIN2__PRESERVED 0x00000000U +#define RIF_TXGAIN2__RESET_VALUE 0x0cfdf0b9U + +#endif /* __RIF_TXGAIN2_MACRO__ */ + +/** @} end of txgain2 */ + +/* macros for BlueprintGlobalNameSpace::RIF_txgain3 */ +/** + * @defgroup rif_regs_core_txgain3 txgain3 + * @brief TX power table entries 9 to 11, maps to pa_stages[2:0], pa_ref[5:0] definitions. + * @{ + */ +#ifndef __RIF_TXGAIN3_MACRO__ +#define __RIF_TXGAIN3_MACRO__ + +/* macros for field entry9 */ +/** + * @defgroup rif_regs_core_entry9_field entry9_field + * @brief macros for field entry9 + * @details TX power level entry 9, 6dBm + * @{ + */ +#define RIF_TXGAIN3__ENTRY9__SHIFT 0 +#define RIF_TXGAIN3__ENTRY9__WIDTH 9 +#define RIF_TXGAIN3__ENTRY9__MASK 0x000001ffU +#define RIF_TXGAIN3__ENTRY9__READ(src) ((uint32_t)(src) & 0x000001ffU) +#define RIF_TXGAIN3__ENTRY9__WRITE(src) ((uint32_t)(src) & 0x000001ffU) +#define RIF_TXGAIN3__ENTRY9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((uint32_t)(src) &\ + 0x000001ffU) +#define RIF_TXGAIN3__ENTRY9__VERIFY(src) (!(((uint32_t)(src) & ~0x000001ffU))) +#define RIF_TXGAIN3__ENTRY9__RESET_VALUE 0x000001aeU +/** @} */ + +/* macros for field entry10 */ +/** + * @defgroup rif_regs_core_entry10_field entry10_field + * @brief macros for field entry10 + * @details TX power level entry 10, 8dBm + * @{ + */ +#define RIF_TXGAIN3__ENTRY10__SHIFT 9 +#define RIF_TXGAIN3__ENTRY10__WIDTH 9 +#define RIF_TXGAIN3__ENTRY10__MASK 0x0003fe00U +#define RIF_TXGAIN3__ENTRY10__READ(src) (((uint32_t)(src) & 0x0003fe00U) >> 9) +#define RIF_TXGAIN3__ENTRY10__WRITE(src) (((uint32_t)(src) << 9) & 0x0003fe00U) +#define RIF_TXGAIN3__ENTRY10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0003fe00U) +#define RIF_TXGAIN3__ENTRY10__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0003fe00U))) +#define RIF_TXGAIN3__ENTRY10__RESET_VALUE 0x000001b4U +/** @} */ + +/* macros for field entry11 */ +/** + * @defgroup rif_regs_core_entry11_field entry11_field + * @brief macros for field entry11 + * @details TX power level entry 11, extra + * @{ + */ +#define RIF_TXGAIN3__ENTRY11__SHIFT 18 +#define RIF_TXGAIN3__ENTRY11__WIDTH 9 +#define RIF_TXGAIN3__ENTRY11__MASK 0x07fc0000U +#define RIF_TXGAIN3__ENTRY11__READ(src) (((uint32_t)(src) & 0x07fc0000U) >> 18) +#define RIF_TXGAIN3__ENTRY11__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x07fc0000U) +#define RIF_TXGAIN3__ENTRY11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07fc0000U) | (((uint32_t)(src) <<\ + 18) & 0x07fc0000U) +#define RIF_TXGAIN3__ENTRY11__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x07fc0000U))) +#define RIF_TXGAIN3__ENTRY11__RESET_VALUE 0x000001ffU +/** @} */ + +/* macros for field pa_supconf3 */ +/** + * @defgroup rif_regs_core_pa_supconf3_field pa_supconf3_field + * @brief macros for field pa_supconf3 + * @details PA input supply configuration, 00: VDDPA passthrough with NMOS1 and PMOS, 01: AVDD with NMOS0, 10: VDDPA with NMOS1, 11: VDDPA with PMOS + * @{ + */ +#define RIF_TXGAIN3__PA_SUPCONF3__SHIFT 27 +#define RIF_TXGAIN3__PA_SUPCONF3__WIDTH 2 +#define RIF_TXGAIN3__PA_SUPCONF3__MASK 0x18000000U +#define RIF_TXGAIN3__PA_SUPCONF3__READ(src) \ + (((uint32_t)(src)\ + & 0x18000000U) >> 27) +#define RIF_TXGAIN3__PA_SUPCONF3__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x18000000U) +#define RIF_TXGAIN3__PA_SUPCONF3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x18000000U) | (((uint32_t)(src) <<\ + 27) & 0x18000000U) +#define RIF_TXGAIN3__PA_SUPCONF3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x18000000U))) +#define RIF_TXGAIN3__PA_SUPCONF3__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field pa_refconf3 */ +/** + * @defgroup rif_regs_core_pa_refconf3_field pa_refconf3_field + * @brief macros for field pa_refconf3 + * @details PA LDO reference configuration max voltage, 00: AVDD, 01: VDDPA, 10: IR 1.0V, 11: IR 1.8V + * @{ + */ +#define RIF_TXGAIN3__PA_REFCONF3__SHIFT 29 +#define RIF_TXGAIN3__PA_REFCONF3__WIDTH 2 +#define RIF_TXGAIN3__PA_REFCONF3__MASK 0x60000000U +#define RIF_TXGAIN3__PA_REFCONF3__READ(src) \ + (((uint32_t)(src)\ + & 0x60000000U) >> 29) +#define RIF_TXGAIN3__PA_REFCONF3__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x60000000U) +#define RIF_TXGAIN3__PA_REFCONF3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x60000000U) | (((uint32_t)(src) <<\ + 29) & 0x60000000U) +#define RIF_TXGAIN3__PA_REFCONF3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x60000000U))) +#define RIF_TXGAIN3__PA_REFCONF3__RESET_VALUE 0x00000001U +/** @} */ +#define RIF_TXGAIN3__TYPE uint32_t +#define RIF_TXGAIN3__READ 0x7fffffffU +#define RIF_TXGAIN3__WRITE 0x7fffffffU +#define RIF_TXGAIN3__PRESERVED 0x00000000U +#define RIF_TXGAIN3__RESET_VALUE 0x3fff69aeU + +#endif /* __RIF_TXGAIN3_MACRO__ */ + +/** @} end of txgain3 */ + +/* macros for BlueprintGlobalNameSpace::RIF_rxgain0 */ +/** + * @defgroup rif_regs_core_rxgain0 rxgain0 + * @brief RX gain table, entries ordered lnagain[2:0], bb1gain[1:0], bb2gain[4:0] definitions. + * @{ + */ +#ifndef __RIF_RXGAIN0_MACRO__ +#define __RIF_RXGAIN0_MACRO__ + +/* macros for field entry0 */ +/** + * @defgroup rif_regs_core_entry0_field entry0_field + * @brief macros for field entry0 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN0__ENTRY0__SHIFT 0 +#define RIF_RXGAIN0__ENTRY0__WIDTH 10 +#define RIF_RXGAIN0__ENTRY0__MASK 0x000003ffU +#define RIF_RXGAIN0__ENTRY0__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN0__ENTRY0__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN0__ENTRY0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_RXGAIN0__ENTRY0__VERIFY(src) (!(((uint32_t)(src) & ~0x000003ffU))) +#define RIF_RXGAIN0__ENTRY0__RESET_VALUE 0x00000100U +/** @} */ + +/* macros for field entry1 */ +/** + * @defgroup rif_regs_core_entry1_field entry1_field + * @brief macros for field entry1 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN0__ENTRY1__SHIFT 10 +#define RIF_RXGAIN0__ENTRY1__WIDTH 10 +#define RIF_RXGAIN0__ENTRY1__MASK 0x000ffc00U +#define RIF_RXGAIN0__ENTRY1__READ(src) (((uint32_t)(src) & 0x000ffc00U) >> 10) +#define RIF_RXGAIN0__ENTRY1__WRITE(src) (((uint32_t)(src) << 10) & 0x000ffc00U) +#define RIF_RXGAIN0__ENTRY1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define RIF_RXGAIN0__ENTRY1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define RIF_RXGAIN0__ENTRY1__RESET_VALUE 0x00000102U +/** @} */ + +/* macros for field entry2 */ +/** + * @defgroup rif_regs_core_entry2_field entry2_field + * @brief macros for field entry2 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN0__ENTRY2__SHIFT 20 +#define RIF_RXGAIN0__ENTRY2__WIDTH 10 +#define RIF_RXGAIN0__ENTRY2__MASK 0x3ff00000U +#define RIF_RXGAIN0__ENTRY2__READ(src) (((uint32_t)(src) & 0x3ff00000U) >> 20) +#define RIF_RXGAIN0__ENTRY2__WRITE(src) (((uint32_t)(src) << 20) & 0x3ff00000U) +#define RIF_RXGAIN0__ENTRY2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define RIF_RXGAIN0__ENTRY2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define RIF_RXGAIN0__ENTRY2__RESET_VALUE 0x00000104U +/** @} */ +#define RIF_RXGAIN0__TYPE uint32_t +#define RIF_RXGAIN0__READ 0x3fffffffU +#define RIF_RXGAIN0__WRITE 0x3fffffffU +#define RIF_RXGAIN0__PRESERVED 0x00000000U +#define RIF_RXGAIN0__RESET_VALUE 0x10440900U + +#endif /* __RIF_RXGAIN0_MACRO__ */ + +/** @} end of rxgain0 */ + +/* macros for BlueprintGlobalNameSpace::RIF_rxgain1 */ +/** + * @defgroup rif_regs_core_rxgain1 rxgain1 + * @brief RX gain table, entries ordered lnagain[2:0], bb1gain[1:0], bb2gain[4:0] definitions. + * @{ + */ +#ifndef __RIF_RXGAIN1_MACRO__ +#define __RIF_RXGAIN1_MACRO__ + +/* macros for field entry3 */ +/** + * @defgroup rif_regs_core_entry3_field entry3_field + * @brief macros for field entry3 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN1__ENTRY3__SHIFT 0 +#define RIF_RXGAIN1__ENTRY3__WIDTH 10 +#define RIF_RXGAIN1__ENTRY3__MASK 0x000003ffU +#define RIF_RXGAIN1__ENTRY3__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN1__ENTRY3__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN1__ENTRY3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_RXGAIN1__ENTRY3__VERIFY(src) (!(((uint32_t)(src) & ~0x000003ffU))) +#define RIF_RXGAIN1__ENTRY3__RESET_VALUE 0x00000120U +/** @} */ + +/* macros for field entry4 */ +/** + * @defgroup rif_regs_core_entry4_field entry4_field + * @brief macros for field entry4 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN1__ENTRY4__SHIFT 10 +#define RIF_RXGAIN1__ENTRY4__WIDTH 10 +#define RIF_RXGAIN1__ENTRY4__MASK 0x000ffc00U +#define RIF_RXGAIN1__ENTRY4__READ(src) (((uint32_t)(src) & 0x000ffc00U) >> 10) +#define RIF_RXGAIN1__ENTRY4__WRITE(src) (((uint32_t)(src) << 10) & 0x000ffc00U) +#define RIF_RXGAIN1__ENTRY4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define RIF_RXGAIN1__ENTRY4__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define RIF_RXGAIN1__ENTRY4__RESET_VALUE 0x00000122U +/** @} */ + +/* macros for field entry5 */ +/** + * @defgroup rif_regs_core_entry5_field entry5_field + * @brief macros for field entry5 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN1__ENTRY5__SHIFT 20 +#define RIF_RXGAIN1__ENTRY5__WIDTH 10 +#define RIF_RXGAIN1__ENTRY5__MASK 0x3ff00000U +#define RIF_RXGAIN1__ENTRY5__READ(src) (((uint32_t)(src) & 0x3ff00000U) >> 20) +#define RIF_RXGAIN1__ENTRY5__WRITE(src) (((uint32_t)(src) << 20) & 0x3ff00000U) +#define RIF_RXGAIN1__ENTRY5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define RIF_RXGAIN1__ENTRY5__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define RIF_RXGAIN1__ENTRY5__RESET_VALUE 0x00000124U +/** @} */ +#define RIF_RXGAIN1__TYPE uint32_t +#define RIF_RXGAIN1__READ 0x3fffffffU +#define RIF_RXGAIN1__WRITE 0x3fffffffU +#define RIF_RXGAIN1__PRESERVED 0x00000000U +#define RIF_RXGAIN1__RESET_VALUE 0x12448920U + +#endif /* __RIF_RXGAIN1_MACRO__ */ + +/** @} end of rxgain1 */ + +/* macros for BlueprintGlobalNameSpace::RIF_rxgain2 */ +/** + * @defgroup rif_regs_core_rxgain2 rxgain2 + * @brief RX gain table, entries ordered lnagain[2:0], bb1gain[1:0], bb2gain[4:0] definitions. + * @{ + */ +#ifndef __RIF_RXGAIN2_MACRO__ +#define __RIF_RXGAIN2_MACRO__ + +/* macros for field entry6 */ +/** + * @defgroup rif_regs_core_entry6_field entry6_field + * @brief macros for field entry6 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN2__ENTRY6__SHIFT 0 +#define RIF_RXGAIN2__ENTRY6__WIDTH 10 +#define RIF_RXGAIN2__ENTRY6__MASK 0x000003ffU +#define RIF_RXGAIN2__ENTRY6__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN2__ENTRY6__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN2__ENTRY6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_RXGAIN2__ENTRY6__VERIFY(src) (!(((uint32_t)(src) & ~0x000003ffU))) +#define RIF_RXGAIN2__ENTRY6__RESET_VALUE 0x00000126U +/** @} */ + +/* macros for field entry7 */ +/** + * @defgroup rif_regs_core_entry7_field entry7_field + * @brief macros for field entry7 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN2__ENTRY7__SHIFT 10 +#define RIF_RXGAIN2__ENTRY7__WIDTH 10 +#define RIF_RXGAIN2__ENTRY7__MASK 0x000ffc00U +#define RIF_RXGAIN2__ENTRY7__READ(src) (((uint32_t)(src) & 0x000ffc00U) >> 10) +#define RIF_RXGAIN2__ENTRY7__WRITE(src) (((uint32_t)(src) << 10) & 0x000ffc00U) +#define RIF_RXGAIN2__ENTRY7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define RIF_RXGAIN2__ENTRY7__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define RIF_RXGAIN2__ENTRY7__RESET_VALUE 0x00000128U +/** @} */ + +/* macros for field entry8 */ +/** + * @defgroup rif_regs_core_entry8_field entry8_field + * @brief macros for field entry8 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN2__ENTRY8__SHIFT 20 +#define RIF_RXGAIN2__ENTRY8__WIDTH 10 +#define RIF_RXGAIN2__ENTRY8__MASK 0x3ff00000U +#define RIF_RXGAIN2__ENTRY8__READ(src) (((uint32_t)(src) & 0x3ff00000U) >> 20) +#define RIF_RXGAIN2__ENTRY8__WRITE(src) (((uint32_t)(src) << 20) & 0x3ff00000U) +#define RIF_RXGAIN2__ENTRY8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define RIF_RXGAIN2__ENTRY8__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define RIF_RXGAIN2__ENTRY8__RESET_VALUE 0x0000012aU +/** @} */ +#define RIF_RXGAIN2__TYPE uint32_t +#define RIF_RXGAIN2__READ 0x3fffffffU +#define RIF_RXGAIN2__WRITE 0x3fffffffU +#define RIF_RXGAIN2__PRESERVED 0x00000000U +#define RIF_RXGAIN2__RESET_VALUE 0x12a4a126U + +#endif /* __RIF_RXGAIN2_MACRO__ */ + +/** @} end of rxgain2 */ + +/* macros for BlueprintGlobalNameSpace::RIF_rxgain3 */ +/** + * @defgroup rif_regs_core_rxgain3 rxgain3 + * @brief RX gain table, entries ordered lnagain[2:0], bb1gain[1:0], bb2gain[4:0] definitions. + * @{ + */ +#ifndef __RIF_RXGAIN3_MACRO__ +#define __RIF_RXGAIN3_MACRO__ + +/* macros for field entry9 */ +/** + * @defgroup rif_regs_core_entry9_field entry9_field + * @brief macros for field entry9 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN3__ENTRY9__SHIFT 0 +#define RIF_RXGAIN3__ENTRY9__WIDTH 10 +#define RIF_RXGAIN3__ENTRY9__MASK 0x000003ffU +#define RIF_RXGAIN3__ENTRY9__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN3__ENTRY9__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN3__ENTRY9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_RXGAIN3__ENTRY9__VERIFY(src) (!(((uint32_t)(src) & ~0x000003ffU))) +#define RIF_RXGAIN3__ENTRY9__RESET_VALUE 0x0000012cU +/** @} */ + +/* macros for field entry10 */ +/** + * @defgroup rif_regs_core_entry10_field entry10_field + * @brief macros for field entry10 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN3__ENTRY10__SHIFT 10 +#define RIF_RXGAIN3__ENTRY10__WIDTH 10 +#define RIF_RXGAIN3__ENTRY10__MASK 0x000ffc00U +#define RIF_RXGAIN3__ENTRY10__READ(src) (((uint32_t)(src) & 0x000ffc00U) >> 10) +#define RIF_RXGAIN3__ENTRY10__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x000ffc00U) +#define RIF_RXGAIN3__ENTRY10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define RIF_RXGAIN3__ENTRY10__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define RIF_RXGAIN3__ENTRY10__RESET_VALUE 0x0000012eU +/** @} */ + +/* macros for field entry11 */ +/** + * @defgroup rif_regs_core_entry11_field entry11_field + * @brief macros for field entry11 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN3__ENTRY11__SHIFT 20 +#define RIF_RXGAIN3__ENTRY11__WIDTH 10 +#define RIF_RXGAIN3__ENTRY11__MASK 0x3ff00000U +#define RIF_RXGAIN3__ENTRY11__READ(src) (((uint32_t)(src) & 0x3ff00000U) >> 20) +#define RIF_RXGAIN3__ENTRY11__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x3ff00000U) +#define RIF_RXGAIN3__ENTRY11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define RIF_RXGAIN3__ENTRY11__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define RIF_RXGAIN3__ENTRY11__RESET_VALUE 0x00000130U +/** @} */ +#define RIF_RXGAIN3__TYPE uint32_t +#define RIF_RXGAIN3__READ 0x3fffffffU +#define RIF_RXGAIN3__WRITE 0x3fffffffU +#define RIF_RXGAIN3__PRESERVED 0x00000000U +#define RIF_RXGAIN3__RESET_VALUE 0x1304b92cU + +#endif /* __RIF_RXGAIN3_MACRO__ */ + +/** @} end of rxgain3 */ + +/* macros for BlueprintGlobalNameSpace::RIF_rxgain4 */ +/** + * @defgroup rif_regs_core_rxgain4 rxgain4 + * @brief RX gain table, entries ordered lnagain[2:0], bb1gain[1:0], bb2gain[4:0] definitions. + * @{ + */ +#ifndef __RIF_RXGAIN4_MACRO__ +#define __RIF_RXGAIN4_MACRO__ + +/* macros for field entry12 */ +/** + * @defgroup rif_regs_core_entry12_field entry12_field + * @brief macros for field entry12 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN4__ENTRY12__SHIFT 0 +#define RIF_RXGAIN4__ENTRY12__WIDTH 10 +#define RIF_RXGAIN4__ENTRY12__MASK 0x000003ffU +#define RIF_RXGAIN4__ENTRY12__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN4__ENTRY12__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN4__ENTRY12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_RXGAIN4__ENTRY12__VERIFY(src) (!(((uint32_t)(src) & ~0x000003ffU))) +#define RIF_RXGAIN4__ENTRY12__RESET_VALUE 0x00000132U +/** @} */ + +/* macros for field entry13 */ +/** + * @defgroup rif_regs_core_entry13_field entry13_field + * @brief macros for field entry13 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN4__ENTRY13__SHIFT 10 +#define RIF_RXGAIN4__ENTRY13__WIDTH 10 +#define RIF_RXGAIN4__ENTRY13__MASK 0x000ffc00U +#define RIF_RXGAIN4__ENTRY13__READ(src) (((uint32_t)(src) & 0x000ffc00U) >> 10) +#define RIF_RXGAIN4__ENTRY13__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x000ffc00U) +#define RIF_RXGAIN4__ENTRY13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define RIF_RXGAIN4__ENTRY13__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define RIF_RXGAIN4__ENTRY13__RESET_VALUE 0x00000134U +/** @} */ + +/* macros for field entry14 */ +/** + * @defgroup rif_regs_core_entry14_field entry14_field + * @brief macros for field entry14 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN4__ENTRY14__SHIFT 20 +#define RIF_RXGAIN4__ENTRY14__WIDTH 10 +#define RIF_RXGAIN4__ENTRY14__MASK 0x3ff00000U +#define RIF_RXGAIN4__ENTRY14__READ(src) (((uint32_t)(src) & 0x3ff00000U) >> 20) +#define RIF_RXGAIN4__ENTRY14__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x3ff00000U) +#define RIF_RXGAIN4__ENTRY14__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define RIF_RXGAIN4__ENTRY14__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define RIF_RXGAIN4__ENTRY14__RESET_VALUE 0x000001b1U +/** @} */ +#define RIF_RXGAIN4__TYPE uint32_t +#define RIF_RXGAIN4__READ 0x3fffffffU +#define RIF_RXGAIN4__WRITE 0x3fffffffU +#define RIF_RXGAIN4__PRESERVED 0x00000000U +#define RIF_RXGAIN4__RESET_VALUE 0x1b14d132U + +#endif /* __RIF_RXGAIN4_MACRO__ */ + +/** @} end of rxgain4 */ + +/* macros for BlueprintGlobalNameSpace::RIF_rxgain5 */ +/** + * @defgroup rif_regs_core_rxgain5 rxgain5 + * @brief RX gain table, entries ordered lnagain[2:0], bb1gain[1:0], bb2gain[4:0] definitions. + * @{ + */ +#ifndef __RIF_RXGAIN5_MACRO__ +#define __RIF_RXGAIN5_MACRO__ + +/* macros for field entry15 */ +/** + * @defgroup rif_regs_core_entry15_field entry15_field + * @brief macros for field entry15 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN5__ENTRY15__SHIFT 0 +#define RIF_RXGAIN5__ENTRY15__WIDTH 10 +#define RIF_RXGAIN5__ENTRY15__MASK 0x000003ffU +#define RIF_RXGAIN5__ENTRY15__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN5__ENTRY15__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN5__ENTRY15__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_RXGAIN5__ENTRY15__VERIFY(src) (!(((uint32_t)(src) & ~0x000003ffU))) +#define RIF_RXGAIN5__ENTRY15__RESET_VALUE 0x000001b3U +/** @} */ + +/* macros for field entry16 */ +/** + * @defgroup rif_regs_core_entry16_field entry16_field + * @brief macros for field entry16 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN5__ENTRY16__SHIFT 10 +#define RIF_RXGAIN5__ENTRY16__WIDTH 10 +#define RIF_RXGAIN5__ENTRY16__MASK 0x000ffc00U +#define RIF_RXGAIN5__ENTRY16__READ(src) (((uint32_t)(src) & 0x000ffc00U) >> 10) +#define RIF_RXGAIN5__ENTRY16__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x000ffc00U) +#define RIF_RXGAIN5__ENTRY16__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define RIF_RXGAIN5__ENTRY16__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define RIF_RXGAIN5__ENTRY16__RESET_VALUE 0x00000230U +/** @} */ + +/* macros for field entry17 */ +/** + * @defgroup rif_regs_core_entry17_field entry17_field + * @brief macros for field entry17 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN5__ENTRY17__SHIFT 20 +#define RIF_RXGAIN5__ENTRY17__WIDTH 10 +#define RIF_RXGAIN5__ENTRY17__MASK 0x3ff00000U +#define RIF_RXGAIN5__ENTRY17__READ(src) (((uint32_t)(src) & 0x3ff00000U) >> 20) +#define RIF_RXGAIN5__ENTRY17__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x3ff00000U) +#define RIF_RXGAIN5__ENTRY17__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define RIF_RXGAIN5__ENTRY17__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define RIF_RXGAIN5__ENTRY17__RESET_VALUE 0x00000232U +/** @} */ +#define RIF_RXGAIN5__TYPE uint32_t +#define RIF_RXGAIN5__READ 0x3fffffffU +#define RIF_RXGAIN5__WRITE 0x3fffffffU +#define RIF_RXGAIN5__PRESERVED 0x00000000U +#define RIF_RXGAIN5__RESET_VALUE 0x2328c1b3U + +#endif /* __RIF_RXGAIN5_MACRO__ */ + +/** @} end of rxgain5 */ + +/* macros for BlueprintGlobalNameSpace::RIF_rxgain6 */ +/** + * @defgroup rif_regs_core_rxgain6 rxgain6 + * @brief RX gain table, entries ordered lnagain[2:0], bb1gain[1:0], bb2gain[4:0] definitions. + * @{ + */ +#ifndef __RIF_RXGAIN6_MACRO__ +#define __RIF_RXGAIN6_MACRO__ + +/* macros for field entry18 */ +/** + * @defgroup rif_regs_core_entry18_field entry18_field + * @brief macros for field entry18 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN6__ENTRY18__SHIFT 0 +#define RIF_RXGAIN6__ENTRY18__WIDTH 10 +#define RIF_RXGAIN6__ENTRY18__MASK 0x000003ffU +#define RIF_RXGAIN6__ENTRY18__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN6__ENTRY18__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN6__ENTRY18__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_RXGAIN6__ENTRY18__VERIFY(src) (!(((uint32_t)(src) & ~0x000003ffU))) +#define RIF_RXGAIN6__ENTRY18__RESET_VALUE 0x00000234U +/** @} */ + +/* macros for field entry19 */ +/** + * @defgroup rif_regs_core_entry19_field entry19_field + * @brief macros for field entry19 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN6__ENTRY19__SHIFT 10 +#define RIF_RXGAIN6__ENTRY19__WIDTH 10 +#define RIF_RXGAIN6__ENTRY19__MASK 0x000ffc00U +#define RIF_RXGAIN6__ENTRY19__READ(src) (((uint32_t)(src) & 0x000ffc00U) >> 10) +#define RIF_RXGAIN6__ENTRY19__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x000ffc00U) +#define RIF_RXGAIN6__ENTRY19__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define RIF_RXGAIN6__ENTRY19__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define RIF_RXGAIN6__ENTRY19__RESET_VALUE 0x000002b1U +/** @} */ + +/* macros for field entry20 */ +/** + * @defgroup rif_regs_core_entry20_field entry20_field + * @brief macros for field entry20 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN6__ENTRY20__SHIFT 20 +#define RIF_RXGAIN6__ENTRY20__WIDTH 10 +#define RIF_RXGAIN6__ENTRY20__MASK 0x3ff00000U +#define RIF_RXGAIN6__ENTRY20__READ(src) (((uint32_t)(src) & 0x3ff00000U) >> 20) +#define RIF_RXGAIN6__ENTRY20__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x3ff00000U) +#define RIF_RXGAIN6__ENTRY20__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define RIF_RXGAIN6__ENTRY20__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define RIF_RXGAIN6__ENTRY20__RESET_VALUE 0x000002b3U +/** @} */ +#define RIF_RXGAIN6__TYPE uint32_t +#define RIF_RXGAIN6__READ 0x3fffffffU +#define RIF_RXGAIN6__WRITE 0x3fffffffU +#define RIF_RXGAIN6__PRESERVED 0x00000000U +#define RIF_RXGAIN6__RESET_VALUE 0x2b3ac634U + +#endif /* __RIF_RXGAIN6_MACRO__ */ + +/** @} end of rxgain6 */ + +/* macros for BlueprintGlobalNameSpace::RIF_rxgain7 */ +/** + * @defgroup rif_regs_core_rxgain7 rxgain7 + * @brief RX gain table, entries ordered lnagain[2:0], bb1gain[1:0], bb2gain[4:0] definitions. + * @{ + */ +#ifndef __RIF_RXGAIN7_MACRO__ +#define __RIF_RXGAIN7_MACRO__ + +/* macros for field entry21 */ +/** + * @defgroup rif_regs_core_entry21_field entry21_field + * @brief macros for field entry21 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN7__ENTRY21__SHIFT 0 +#define RIF_RXGAIN7__ENTRY21__WIDTH 10 +#define RIF_RXGAIN7__ENTRY21__MASK 0x000003ffU +#define RIF_RXGAIN7__ENTRY21__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN7__ENTRY21__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN7__ENTRY21__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_RXGAIN7__ENTRY21__VERIFY(src) (!(((uint32_t)(src) & ~0x000003ffU))) +#define RIF_RXGAIN7__ENTRY21__RESET_VALUE 0x000002b5U +/** @} */ + +/* macros for field entry22 */ +/** + * @defgroup rif_regs_core_entry22_field entry22_field + * @brief macros for field entry22 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN7__ENTRY22__SHIFT 10 +#define RIF_RXGAIN7__ENTRY22__WIDTH 10 +#define RIF_RXGAIN7__ENTRY22__MASK 0x000ffc00U +#define RIF_RXGAIN7__ENTRY22__READ(src) (((uint32_t)(src) & 0x000ffc00U) >> 10) +#define RIF_RXGAIN7__ENTRY22__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x000ffc00U) +#define RIF_RXGAIN7__ENTRY22__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define RIF_RXGAIN7__ENTRY22__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define RIF_RXGAIN7__ENTRY22__RESET_VALUE 0x00000332U +/** @} */ + +/* macros for field entry23 */ +/** + * @defgroup rif_regs_core_entry23_field entry23_field + * @brief macros for field entry23 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN7__ENTRY23__SHIFT 20 +#define RIF_RXGAIN7__ENTRY23__WIDTH 10 +#define RIF_RXGAIN7__ENTRY23__MASK 0x3ff00000U +#define RIF_RXGAIN7__ENTRY23__READ(src) (((uint32_t)(src) & 0x3ff00000U) >> 20) +#define RIF_RXGAIN7__ENTRY23__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x3ff00000U) +#define RIF_RXGAIN7__ENTRY23__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define RIF_RXGAIN7__ENTRY23__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define RIF_RXGAIN7__ENTRY23__RESET_VALUE 0x00000334U +/** @} */ +#define RIF_RXGAIN7__TYPE uint32_t +#define RIF_RXGAIN7__READ 0x3fffffffU +#define RIF_RXGAIN7__WRITE 0x3fffffffU +#define RIF_RXGAIN7__PRESERVED 0x00000000U +#define RIF_RXGAIN7__RESET_VALUE 0x334ccab5U + +#endif /* __RIF_RXGAIN7_MACRO__ */ + +/** @} end of rxgain7 */ + +/* macros for BlueprintGlobalNameSpace::RIF_rxgain8 */ +/** + * @defgroup rif_regs_core_rxgain8 rxgain8 + * @brief RX gain table, entries ordered lnagain[2:0], bb1gain[1:0], bb2gain[4:0] definitions. + * @{ + */ +#ifndef __RIF_RXGAIN8_MACRO__ +#define __RIF_RXGAIN8_MACRO__ + +/* macros for field entry24 */ +/** + * @defgroup rif_regs_core_entry24_field entry24_field + * @brief macros for field entry24 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN8__ENTRY24__SHIFT 0 +#define RIF_RXGAIN8__ENTRY24__WIDTH 10 +#define RIF_RXGAIN8__ENTRY24__MASK 0x000003ffU +#define RIF_RXGAIN8__ENTRY24__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN8__ENTRY24__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN8__ENTRY24__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_RXGAIN8__ENTRY24__VERIFY(src) (!(((uint32_t)(src) & ~0x000003ffU))) +#define RIF_RXGAIN8__ENTRY24__RESET_VALUE 0x00000336U +/** @} */ + +/* macros for field entry25 */ +/** + * @defgroup rif_regs_core_entry25_field entry25_field + * @brief macros for field entry25 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN8__ENTRY25__SHIFT 10 +#define RIF_RXGAIN8__ENTRY25__WIDTH 10 +#define RIF_RXGAIN8__ENTRY25__MASK 0x000ffc00U +#define RIF_RXGAIN8__ENTRY25__READ(src) (((uint32_t)(src) & 0x000ffc00U) >> 10) +#define RIF_RXGAIN8__ENTRY25__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x000ffc00U) +#define RIF_RXGAIN8__ENTRY25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define RIF_RXGAIN8__ENTRY25__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define RIF_RXGAIN8__ENTRY25__RESET_VALUE 0x000003b4U +/** @} */ + +/* macros for field entry26 */ +/** + * @defgroup rif_regs_core_entry26_field entry26_field + * @brief macros for field entry26 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN8__ENTRY26__SHIFT 20 +#define RIF_RXGAIN8__ENTRY26__WIDTH 10 +#define RIF_RXGAIN8__ENTRY26__MASK 0x3ff00000U +#define RIF_RXGAIN8__ENTRY26__READ(src) (((uint32_t)(src) & 0x3ff00000U) >> 20) +#define RIF_RXGAIN8__ENTRY26__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x3ff00000U) +#define RIF_RXGAIN8__ENTRY26__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define RIF_RXGAIN8__ENTRY26__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define RIF_RXGAIN8__ENTRY26__RESET_VALUE 0x000003b6U +/** @} */ +#define RIF_RXGAIN8__TYPE uint32_t +#define RIF_RXGAIN8__READ 0x3fffffffU +#define RIF_RXGAIN8__WRITE 0x3fffffffU +#define RIF_RXGAIN8__PRESERVED 0x00000000U +#define RIF_RXGAIN8__RESET_VALUE 0x3b6ed336U + +#endif /* __RIF_RXGAIN8_MACRO__ */ + +/** @} end of rxgain8 */ + +/* macros for BlueprintGlobalNameSpace::RIF_rxgain9 */ +/** + * @defgroup rif_regs_core_rxgain9 rxgain9 + * @brief RX gain table, entries ordered lnagain[2:0], bb1gain[1:0], bb2gain[4:0] definitions. + * @{ + */ +#ifndef __RIF_RXGAIN9_MACRO__ +#define __RIF_RXGAIN9_MACRO__ + +/* macros for field entry27 */ +/** + * @defgroup rif_regs_core_entry27_field entry27_field + * @brief macros for field entry27 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN9__ENTRY27__SHIFT 0 +#define RIF_RXGAIN9__ENTRY27__WIDTH 10 +#define RIF_RXGAIN9__ENTRY27__MASK 0x000003ffU +#define RIF_RXGAIN9__ENTRY27__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN9__ENTRY27__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN9__ENTRY27__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_RXGAIN9__ENTRY27__VERIFY(src) (!(((uint32_t)(src) & ~0x000003ffU))) +#define RIF_RXGAIN9__ENTRY27__RESET_VALUE 0x000003b8U +/** @} */ + +/* macros for field entry28 */ +/** + * @defgroup rif_regs_core_entry28_field entry28_field + * @brief macros for field entry28 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN9__ENTRY28__SHIFT 10 +#define RIF_RXGAIN9__ENTRY28__WIDTH 10 +#define RIF_RXGAIN9__ENTRY28__MASK 0x000ffc00U +#define RIF_RXGAIN9__ENTRY28__READ(src) (((uint32_t)(src) & 0x000ffc00U) >> 10) +#define RIF_RXGAIN9__ENTRY28__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x000ffc00U) +#define RIF_RXGAIN9__ENTRY28__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define RIF_RXGAIN9__ENTRY28__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define RIF_RXGAIN9__ENTRY28__RESET_VALUE 0x000003b8U +/** @} */ + +/* macros for field entry29 */ +/** + * @defgroup rif_regs_core_entry29_field entry29_field + * @brief macros for field entry29 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN9__ENTRY29__SHIFT 20 +#define RIF_RXGAIN9__ENTRY29__WIDTH 10 +#define RIF_RXGAIN9__ENTRY29__MASK 0x3ff00000U +#define RIF_RXGAIN9__ENTRY29__READ(src) (((uint32_t)(src) & 0x3ff00000U) >> 20) +#define RIF_RXGAIN9__ENTRY29__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x3ff00000U) +#define RIF_RXGAIN9__ENTRY29__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define RIF_RXGAIN9__ENTRY29__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define RIF_RXGAIN9__ENTRY29__RESET_VALUE 0x000003b8U +/** @} */ +#define RIF_RXGAIN9__TYPE uint32_t +#define RIF_RXGAIN9__READ 0x3fffffffU +#define RIF_RXGAIN9__WRITE 0x3fffffffU +#define RIF_RXGAIN9__PRESERVED 0x00000000U +#define RIF_RXGAIN9__RESET_VALUE 0x3b8ee3b8U + +#endif /* __RIF_RXGAIN9_MACRO__ */ + +/** @} end of rxgain9 */ + +/* macros for BlueprintGlobalNameSpace::RIF_rxgain10 */ +/** + * @defgroup rif_regs_core_rxgain10 rxgain10 + * @brief RX gain table, entries ordered lnagain[2:0], bb1gain[1:0], bb2gain[4:0] definitions. + * @{ + */ +#ifndef __RIF_RXGAIN10_MACRO__ +#define __RIF_RXGAIN10_MACRO__ + +/* macros for field entry30 */ +/** + * @defgroup rif_regs_core_entry30_field entry30_field + * @brief macros for field entry30 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN10__ENTRY30__SHIFT 0 +#define RIF_RXGAIN10__ENTRY30__WIDTH 10 +#define RIF_RXGAIN10__ENTRY30__MASK 0x000003ffU +#define RIF_RXGAIN10__ENTRY30__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN10__ENTRY30__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN10__ENTRY30__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_RXGAIN10__ENTRY30__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define RIF_RXGAIN10__ENTRY30__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field entry31 */ +/** + * @defgroup rif_regs_core_entry31_field entry31_field + * @brief macros for field entry31 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN10__ENTRY31__SHIFT 10 +#define RIF_RXGAIN10__ENTRY31__WIDTH 10 +#define RIF_RXGAIN10__ENTRY31__MASK 0x000ffc00U +#define RIF_RXGAIN10__ENTRY31__READ(src) \ + (((uint32_t)(src)\ + & 0x000ffc00U) >> 10) +#define RIF_RXGAIN10__ENTRY31__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x000ffc00U) +#define RIF_RXGAIN10__ENTRY31__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define RIF_RXGAIN10__ENTRY31__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define RIF_RXGAIN10__ENTRY31__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field entry32 */ +/** + * @defgroup rif_regs_core_entry32_field entry32_field + * @brief macros for field entry32 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN10__ENTRY32__SHIFT 20 +#define RIF_RXGAIN10__ENTRY32__WIDTH 10 +#define RIF_RXGAIN10__ENTRY32__MASK 0x3ff00000U +#define RIF_RXGAIN10__ENTRY32__READ(src) \ + (((uint32_t)(src)\ + & 0x3ff00000U) >> 20) +#define RIF_RXGAIN10__ENTRY32__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x3ff00000U) +#define RIF_RXGAIN10__ENTRY32__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define RIF_RXGAIN10__ENTRY32__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define RIF_RXGAIN10__ENTRY32__RESET_VALUE 0x00000004U +/** @} */ +#define RIF_RXGAIN10__TYPE uint32_t +#define RIF_RXGAIN10__READ 0x3fffffffU +#define RIF_RXGAIN10__WRITE 0x3fffffffU +#define RIF_RXGAIN10__PRESERVED 0x00000000U +#define RIF_RXGAIN10__RESET_VALUE 0x00400800U + +#endif /* __RIF_RXGAIN10_MACRO__ */ + +/** @} end of rxgain10 */ + +/* macros for BlueprintGlobalNameSpace::RIF_rxgain11 */ +/** + * @defgroup rif_regs_core_rxgain11 rxgain11 + * @brief RX gain table, entries ordered lnagain[2:0], bb1gain[1:0], bb2gain[4:0] definitions. + * @{ + */ +#ifndef __RIF_RXGAIN11_MACRO__ +#define __RIF_RXGAIN11_MACRO__ + +/* macros for field entry33 */ +/** + * @defgroup rif_regs_core_entry33_field entry33_field + * @brief macros for field entry33 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN11__ENTRY33__SHIFT 0 +#define RIF_RXGAIN11__ENTRY33__WIDTH 10 +#define RIF_RXGAIN11__ENTRY33__MASK 0x000003ffU +#define RIF_RXGAIN11__ENTRY33__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN11__ENTRY33__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN11__ENTRY33__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_RXGAIN11__ENTRY33__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define RIF_RXGAIN11__ENTRY33__RESET_VALUE 0x00000020U +/** @} */ + +/* macros for field entry34 */ +/** + * @defgroup rif_regs_core_entry34_field entry34_field + * @brief macros for field entry34 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN11__ENTRY34__SHIFT 10 +#define RIF_RXGAIN11__ENTRY34__WIDTH 10 +#define RIF_RXGAIN11__ENTRY34__MASK 0x000ffc00U +#define RIF_RXGAIN11__ENTRY34__READ(src) \ + (((uint32_t)(src)\ + & 0x000ffc00U) >> 10) +#define RIF_RXGAIN11__ENTRY34__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x000ffc00U) +#define RIF_RXGAIN11__ENTRY34__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define RIF_RXGAIN11__ENTRY34__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define RIF_RXGAIN11__ENTRY34__RESET_VALUE 0x00000022U +/** @} */ + +/* macros for field entry35 */ +/** + * @defgroup rif_regs_core_entry35_field entry35_field + * @brief macros for field entry35 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN11__ENTRY35__SHIFT 20 +#define RIF_RXGAIN11__ENTRY35__WIDTH 10 +#define RIF_RXGAIN11__ENTRY35__MASK 0x3ff00000U +#define RIF_RXGAIN11__ENTRY35__READ(src) \ + (((uint32_t)(src)\ + & 0x3ff00000U) >> 20) +#define RIF_RXGAIN11__ENTRY35__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x3ff00000U) +#define RIF_RXGAIN11__ENTRY35__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define RIF_RXGAIN11__ENTRY35__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define RIF_RXGAIN11__ENTRY35__RESET_VALUE 0x00000024U +/** @} */ +#define RIF_RXGAIN11__TYPE uint32_t +#define RIF_RXGAIN11__READ 0x3fffffffU +#define RIF_RXGAIN11__WRITE 0x3fffffffU +#define RIF_RXGAIN11__PRESERVED 0x00000000U +#define RIF_RXGAIN11__RESET_VALUE 0x02408820U + +#endif /* __RIF_RXGAIN11_MACRO__ */ + +/** @} end of rxgain11 */ + +/* macros for BlueprintGlobalNameSpace::RIF_rxgain12 */ +/** + * @defgroup rif_regs_core_rxgain12 rxgain12 + * @brief RX gain table, entries ordered lnagain[2:0], bb1gain[1:0], bb2gain[4:0] definitions. + * @{ + */ +#ifndef __RIF_RXGAIN12_MACRO__ +#define __RIF_RXGAIN12_MACRO__ + +/* macros for field entry36 */ +/** + * @defgroup rif_regs_core_entry36_field entry36_field + * @brief macros for field entry36 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN12__ENTRY36__SHIFT 0 +#define RIF_RXGAIN12__ENTRY36__WIDTH 10 +#define RIF_RXGAIN12__ENTRY36__MASK 0x000003ffU +#define RIF_RXGAIN12__ENTRY36__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN12__ENTRY36__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN12__ENTRY36__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_RXGAIN12__ENTRY36__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define RIF_RXGAIN12__ENTRY36__RESET_VALUE 0x00000026U +/** @} */ + +/* macros for field entry37 */ +/** + * @defgroup rif_regs_core_entry37_field entry37_field + * @brief macros for field entry37 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN12__ENTRY37__SHIFT 10 +#define RIF_RXGAIN12__ENTRY37__WIDTH 10 +#define RIF_RXGAIN12__ENTRY37__MASK 0x000ffc00U +#define RIF_RXGAIN12__ENTRY37__READ(src) \ + (((uint32_t)(src)\ + & 0x000ffc00U) >> 10) +#define RIF_RXGAIN12__ENTRY37__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x000ffc00U) +#define RIF_RXGAIN12__ENTRY37__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define RIF_RXGAIN12__ENTRY37__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define RIF_RXGAIN12__ENTRY37__RESET_VALUE 0x00000028U +/** @} */ + +/* macros for field entry38 */ +/** + * @defgroup rif_regs_core_entry38_field entry38_field + * @brief macros for field entry38 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN12__ENTRY38__SHIFT 20 +#define RIF_RXGAIN12__ENTRY38__WIDTH 10 +#define RIF_RXGAIN12__ENTRY38__MASK 0x3ff00000U +#define RIF_RXGAIN12__ENTRY38__READ(src) \ + (((uint32_t)(src)\ + & 0x3ff00000U) >> 20) +#define RIF_RXGAIN12__ENTRY38__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x3ff00000U) +#define RIF_RXGAIN12__ENTRY38__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define RIF_RXGAIN12__ENTRY38__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define RIF_RXGAIN12__ENTRY38__RESET_VALUE 0x0000002aU +/** @} */ +#define RIF_RXGAIN12__TYPE uint32_t +#define RIF_RXGAIN12__READ 0x3fffffffU +#define RIF_RXGAIN12__WRITE 0x3fffffffU +#define RIF_RXGAIN12__PRESERVED 0x00000000U +#define RIF_RXGAIN12__RESET_VALUE 0x02a0a026U + +#endif /* __RIF_RXGAIN12_MACRO__ */ + +/** @} end of rxgain12 */ + +/* macros for BlueprintGlobalNameSpace::RIF_rxgain13 */ +/** + * @defgroup rif_regs_core_rxgain13 rxgain13 + * @brief RX gain table, entries ordered lnagain[2:0], bb1gain[1:0], bb2gain[4:0] definitions. + * @{ + */ +#ifndef __RIF_RXGAIN13_MACRO__ +#define __RIF_RXGAIN13_MACRO__ + +/* macros for field entry39 */ +/** + * @defgroup rif_regs_core_entry39_field entry39_field + * @brief macros for field entry39 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN13__ENTRY39__SHIFT 0 +#define RIF_RXGAIN13__ENTRY39__WIDTH 10 +#define RIF_RXGAIN13__ENTRY39__MASK 0x000003ffU +#define RIF_RXGAIN13__ENTRY39__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN13__ENTRY39__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN13__ENTRY39__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_RXGAIN13__ENTRY39__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define RIF_RXGAIN13__ENTRY39__RESET_VALUE 0x0000002cU +/** @} */ + +/* macros for field entry40 */ +/** + * @defgroup rif_regs_core_entry40_field entry40_field + * @brief macros for field entry40 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN13__ENTRY40__SHIFT 10 +#define RIF_RXGAIN13__ENTRY40__WIDTH 10 +#define RIF_RXGAIN13__ENTRY40__MASK 0x000ffc00U +#define RIF_RXGAIN13__ENTRY40__READ(src) \ + (((uint32_t)(src)\ + & 0x000ffc00U) >> 10) +#define RIF_RXGAIN13__ENTRY40__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x000ffc00U) +#define RIF_RXGAIN13__ENTRY40__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define RIF_RXGAIN13__ENTRY40__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define RIF_RXGAIN13__ENTRY40__RESET_VALUE 0x0000002eU +/** @} */ + +/* macros for field entry41 */ +/** + * @defgroup rif_regs_core_entry41_field entry41_field + * @brief macros for field entry41 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN13__ENTRY41__SHIFT 20 +#define RIF_RXGAIN13__ENTRY41__WIDTH 10 +#define RIF_RXGAIN13__ENTRY41__MASK 0x3ff00000U +#define RIF_RXGAIN13__ENTRY41__READ(src) \ + (((uint32_t)(src)\ + & 0x3ff00000U) >> 20) +#define RIF_RXGAIN13__ENTRY41__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x3ff00000U) +#define RIF_RXGAIN13__ENTRY41__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define RIF_RXGAIN13__ENTRY41__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define RIF_RXGAIN13__ENTRY41__RESET_VALUE 0x00000030U +/** @} */ +#define RIF_RXGAIN13__TYPE uint32_t +#define RIF_RXGAIN13__READ 0x3fffffffU +#define RIF_RXGAIN13__WRITE 0x3fffffffU +#define RIF_RXGAIN13__PRESERVED 0x00000000U +#define RIF_RXGAIN13__RESET_VALUE 0x0300b82cU + +#endif /* __RIF_RXGAIN13_MACRO__ */ + +/** @} end of rxgain13 */ + +/* macros for BlueprintGlobalNameSpace::RIF_rxgain14 */ +/** + * @defgroup rif_regs_core_rxgain14 rxgain14 + * @brief RX gain table, entries ordered lnagain[2:0], bb1gain[1:0], bb2gain[4:0] definitions. + * @{ + */ +#ifndef __RIF_RXGAIN14_MACRO__ +#define __RIF_RXGAIN14_MACRO__ + +/* macros for field entry42 */ +/** + * @defgroup rif_regs_core_entry42_field entry42_field + * @brief macros for field entry42 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN14__ENTRY42__SHIFT 0 +#define RIF_RXGAIN14__ENTRY42__WIDTH 10 +#define RIF_RXGAIN14__ENTRY42__MASK 0x000003ffU +#define RIF_RXGAIN14__ENTRY42__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN14__ENTRY42__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN14__ENTRY42__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_RXGAIN14__ENTRY42__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define RIF_RXGAIN14__ENTRY42__RESET_VALUE 0x00000032U +/** @} */ + +/* macros for field entry43 */ +/** + * @defgroup rif_regs_core_entry43_field entry43_field + * @brief macros for field entry43 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN14__ENTRY43__SHIFT 10 +#define RIF_RXGAIN14__ENTRY43__WIDTH 10 +#define RIF_RXGAIN14__ENTRY43__MASK 0x000ffc00U +#define RIF_RXGAIN14__ENTRY43__READ(src) \ + (((uint32_t)(src)\ + & 0x000ffc00U) >> 10) +#define RIF_RXGAIN14__ENTRY43__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x000ffc00U) +#define RIF_RXGAIN14__ENTRY43__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define RIF_RXGAIN14__ENTRY43__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define RIF_RXGAIN14__ENTRY43__RESET_VALUE 0x00000034U +/** @} */ + +/* macros for field entry44 */ +/** + * @defgroup rif_regs_core_entry44_field entry44_field + * @brief macros for field entry44 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN14__ENTRY44__SHIFT 20 +#define RIF_RXGAIN14__ENTRY44__WIDTH 10 +#define RIF_RXGAIN14__ENTRY44__MASK 0x3ff00000U +#define RIF_RXGAIN14__ENTRY44__READ(src) \ + (((uint32_t)(src)\ + & 0x3ff00000U) >> 20) +#define RIF_RXGAIN14__ENTRY44__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x3ff00000U) +#define RIF_RXGAIN14__ENTRY44__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define RIF_RXGAIN14__ENTRY44__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define RIF_RXGAIN14__ENTRY44__RESET_VALUE 0x00000036U +/** @} */ +#define RIF_RXGAIN14__TYPE uint32_t +#define RIF_RXGAIN14__READ 0x3fffffffU +#define RIF_RXGAIN14__WRITE 0x3fffffffU +#define RIF_RXGAIN14__PRESERVED 0x00000000U +#define RIF_RXGAIN14__RESET_VALUE 0x0360d032U + +#endif /* __RIF_RXGAIN14_MACRO__ */ + +/** @} end of rxgain14 */ + +/* macros for BlueprintGlobalNameSpace::RIF_rxgain15 */ +/** + * @defgroup rif_regs_core_rxgain15 rxgain15 + * @brief RX gain table, entries ordered lnagain[2:0], bb1gain[1:0], bb2gain[4:0] definitions. + * @{ + */ +#ifndef __RIF_RXGAIN15_MACRO__ +#define __RIF_RXGAIN15_MACRO__ + +/* macros for field entry45 */ +/** + * @defgroup rif_regs_core_entry45_field entry45_field + * @brief macros for field entry45 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN15__ENTRY45__SHIFT 0 +#define RIF_RXGAIN15__ENTRY45__WIDTH 10 +#define RIF_RXGAIN15__ENTRY45__MASK 0x000003ffU +#define RIF_RXGAIN15__ENTRY45__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN15__ENTRY45__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_RXGAIN15__ENTRY45__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_RXGAIN15__ENTRY45__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define RIF_RXGAIN15__ENTRY45__RESET_VALUE 0x00000038U +/** @} */ + +/* macros for field entry46 */ +/** + * @defgroup rif_regs_core_entry46_field entry46_field + * @brief macros for field entry46 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN15__ENTRY46__SHIFT 10 +#define RIF_RXGAIN15__ENTRY46__WIDTH 10 +#define RIF_RXGAIN15__ENTRY46__MASK 0x000ffc00U +#define RIF_RXGAIN15__ENTRY46__READ(src) \ + (((uint32_t)(src)\ + & 0x000ffc00U) >> 10) +#define RIF_RXGAIN15__ENTRY46__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x000ffc00U) +#define RIF_RXGAIN15__ENTRY46__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define RIF_RXGAIN15__ENTRY46__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define RIF_RXGAIN15__ENTRY46__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field entry47 */ +/** + * @defgroup rif_regs_core_entry47_field entry47_field + * @brief macros for field entry47 + * @details RX gain table entry + * @{ + */ +#define RIF_RXGAIN15__ENTRY47__SHIFT 20 +#define RIF_RXGAIN15__ENTRY47__WIDTH 10 +#define RIF_RXGAIN15__ENTRY47__MASK 0x3ff00000U +#define RIF_RXGAIN15__ENTRY47__READ(src) \ + (((uint32_t)(src)\ + & 0x3ff00000U) >> 20) +#define RIF_RXGAIN15__ENTRY47__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x3ff00000U) +#define RIF_RXGAIN15__ENTRY47__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x3ff00000U) +#define RIF_RXGAIN15__ENTRY47__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define RIF_RXGAIN15__ENTRY47__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_RXGAIN15__TYPE uint32_t +#define RIF_RXGAIN15__READ 0x3fffffffU +#define RIF_RXGAIN15__WRITE 0x3fffffffU +#define RIF_RXGAIN15__PRESERVED 0x00000000U +#define RIF_RXGAIN15__RESET_VALUE 0x00000038U + +#endif /* __RIF_RXGAIN15_MACRO__ */ + +/** @} end of rxgain15 */ + +/* macros for BlueprintGlobalNameSpace::RIF_syntx_cal */ +/** + * @defgroup rif_regs_core_syntx_cal syntx_cal + * @brief Synth TX calibration settings definitions. + * @{ + */ +#ifndef __RIF_SYNTX_CAL_MACRO__ +#define __RIF_SYNTX_CAL_MACRO__ + +/* macros for field txmodGain2M_delta */ +/** + * @defgroup rif_regs_core_txmodGain2M_delta_field txmodGain2M_delta_field + * @brief macros for field txmodGain2M_delta + * @details Signed delta offset from txmodGain value to set full-scale gain of the high frequency modulation path in 2Mbps mode + * @{ + */ +#define RIF_SYNTX_CAL__TXMODGAIN2M_DELTA__SHIFT 0 +#define RIF_SYNTX_CAL__TXMODGAIN2M_DELTA__WIDTH 5 +#define RIF_SYNTX_CAL__TXMODGAIN2M_DELTA__MASK 0x0000001fU +#define RIF_SYNTX_CAL__TXMODGAIN2M_DELTA__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define RIF_SYNTX_CAL__TXMODGAIN2M_DELTA__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define RIF_SYNTX_CAL__TXMODGAIN2M_DELTA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define RIF_SYNTX_CAL__TXMODGAIN2M_DELTA__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define RIF_SYNTX_CAL__TXMODGAIN2M_DELTA__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field deltaF_target */ +/** + * @defgroup rif_regs_core_deltaF_target_field deltaF_target_field + * @brief macros for field deltaF_target + * @details During modgain cal, normalized target freq deviation = 390.625KHz + (15.625KHz * deltaF_target) for 1Mbps + * @{ + */ +#define RIF_SYNTX_CAL__DELTAF_TARGET__SHIFT 5 +#define RIF_SYNTX_CAL__DELTAF_TARGET__WIDTH 4 +#define RIF_SYNTX_CAL__DELTAF_TARGET__MASK 0x000001e0U +#define RIF_SYNTX_CAL__DELTAF_TARGET__READ(src) \ + (((uint32_t)(src)\ + & 0x000001e0U) >> 5) +#define RIF_SYNTX_CAL__DELTAF_TARGET__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x000001e0U) +#define RIF_SYNTX_CAL__DELTAF_TARGET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001e0U) | (((uint32_t)(src) <<\ + 5) & 0x000001e0U) +#define RIF_SYNTX_CAL__DELTAF_TARGET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000001e0U))) +#define RIF_SYNTX_CAL__DELTAF_TARGET__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field modVarSize_1M */ +/** + * @defgroup rif_regs_core_modVarSize_1M_field modVarSize_1M_field + * @brief macros for field modVarSize_1M + * @details modulation varactor size for 1Mbps rate + * @{ + */ +#define RIF_SYNTX_CAL__MODVARSIZE_1M__SHIFT 9 +#define RIF_SYNTX_CAL__MODVARSIZE_1M__WIDTH 4 +#define RIF_SYNTX_CAL__MODVARSIZE_1M__MASK 0x00001e00U +#define RIF_SYNTX_CAL__MODVARSIZE_1M__READ(src) \ + (((uint32_t)(src)\ + & 0x00001e00U) >> 9) +#define RIF_SYNTX_CAL__MODVARSIZE_1M__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00001e00U) +#define RIF_SYNTX_CAL__MODVARSIZE_1M__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001e00U) | (((uint32_t)(src) <<\ + 9) & 0x00001e00U) +#define RIF_SYNTX_CAL__MODVARSIZE_1M__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00001e00U))) +#define RIF_SYNTX_CAL__MODVARSIZE_1M__RESET_VALUE 0x00000003U +/** @} */ +#define RIF_SYNTX_CAL__TYPE uint32_t +#define RIF_SYNTX_CAL__READ 0x00001fffU +#define RIF_SYNTX_CAL__WRITE 0x00001fffU +#define RIF_SYNTX_CAL__PRESERVED 0x00000000U +#define RIF_SYNTX_CAL__RESET_VALUE 0x000006e0U + +#endif /* __RIF_SYNTX_CAL_MACRO__ */ + +/** @} end of syntx_cal */ + +/* macros for BlueprintGlobalNameSpace::RIF_syntx0 */ +/** + * @defgroup rif_regs_core_syntx0 syntx0 + * @brief Synth state machine, misc settings, and VCO cap search algorithm definitions. + * @{ + */ +#ifndef __RIF_SYNTX0_MACRO__ +#define __RIF_SYNTX0_MACRO__ + +/* macros for field stateLength_PowerOnWait_x4u */ +/** + * @defgroup rif_regs_core_stateLength_PowerOnWait_x4u_field stateLength_PowerOnWait_x4u_field + * @brief macros for field stateLength_PowerOnWait_x4u + * @details Length of POWER_ON_WAIT state is (stateLength_PowerOnWait_x4u+1)*4us + * @{ + */ +#define RIF_SYNTX0__STATELENGTH_POWERONWAIT_X4U__SHIFT 0 +#define RIF_SYNTX0__STATELENGTH_POWERONWAIT_X4U__WIDTH 3 +#define RIF_SYNTX0__STATELENGTH_POWERONWAIT_X4U__MASK 0x00000007U +#define RIF_SYNTX0__STATELENGTH_POWERONWAIT_X4U__READ(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define RIF_SYNTX0__STATELENGTH_POWERONWAIT_X4U__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define RIF_SYNTX0__STATELENGTH_POWERONWAIT_X4U__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define RIF_SYNTX0__STATELENGTH_POWERONWAIT_X4U__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define RIF_SYNTX0__STATELENGTH_POWERONWAIT_X4U__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field stateLength_CapSearchGetReady_x250n */ +/** + * @defgroup rif_regs_core_stateLength_CapSearchGetReady_x250n_field stateLength_CapSearchGetReady_x250n_field + * @brief macros for field stateLength_CapSearchGetReady_x250n + * @details Length of CAPSEARCH_GETREADY state is (stateLength_CapSearchGetReady_x250n+1)*250n + * @{ + */ +#define RIF_SYNTX0__STATELENGTH_CAPSEARCHGETREADY_X250N__SHIFT 3 +#define RIF_SYNTX0__STATELENGTH_CAPSEARCHGETREADY_X250N__WIDTH 3 +#define RIF_SYNTX0__STATELENGTH_CAPSEARCHGETREADY_X250N__MASK 0x00000038U +#define RIF_SYNTX0__STATELENGTH_CAPSEARCHGETREADY_X250N__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define RIF_SYNTX0__STATELENGTH_CAPSEARCHGETREADY_X250N__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define RIF_SYNTX0__STATELENGTH_CAPSEARCHGETREADY_X250N__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define RIF_SYNTX0__STATELENGTH_CAPSEARCHGETREADY_X250N__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define RIF_SYNTX0__STATELENGTH_CAPSEARCHGETREADY_X250N__RESET_VALUE \ + 0x00000003U +/** @} */ + +/* macros for field stateLength_CapSearchCount_x1u */ +/** + * @defgroup rif_regs_core_stateLength_CapSearchCount_x1u_field stateLength_CapSearchCount_x1u_field + * @brief macros for field stateLength_CapSearchCount_x1u + * @details Length of CAPSEARCH_COUNT state is (stateLength_CapSearchCount_x1u+1)*1u + * @{ + */ +#define RIF_SYNTX0__STATELENGTH_CAPSEARCHCOUNT_X1U__SHIFT 6 +#define RIF_SYNTX0__STATELENGTH_CAPSEARCHCOUNT_X1U__WIDTH 3 +#define RIF_SYNTX0__STATELENGTH_CAPSEARCHCOUNT_X1U__MASK 0x000001c0U +#define RIF_SYNTX0__STATELENGTH_CAPSEARCHCOUNT_X1U__READ(src) \ + (((uint32_t)(src)\ + & 0x000001c0U) >> 6) +#define RIF_SYNTX0__STATELENGTH_CAPSEARCHCOUNT_X1U__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000001c0U) +#define RIF_SYNTX0__STATELENGTH_CAPSEARCHCOUNT_X1U__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((uint32_t)(src) <<\ + 6) & 0x000001c0U) +#define RIF_SYNTX0__STATELENGTH_CAPSEARCHCOUNT_X1U__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000001c0U))) +#define RIF_SYNTX0__STATELENGTH_CAPSEARCHCOUNT_X1U__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field stateLength_CloseLoop_x2u */ +/** + * @defgroup rif_regs_core_stateLength_CloseLoop_x2u_field stateLength_CloseLoop_x2u_field + * @brief macros for field stateLength_CloseLoop_x2u + * @details Length of CLOSE_LOOP state is (stateLength_CloseLoop_x2u+1)*2u + * @{ + */ +#define RIF_SYNTX0__STATELENGTH_CLOSELOOP_X2U__SHIFT 9 +#define RIF_SYNTX0__STATELENGTH_CLOSELOOP_X2U__WIDTH 3 +#define RIF_SYNTX0__STATELENGTH_CLOSELOOP_X2U__MASK 0x00000e00U +#define RIF_SYNTX0__STATELENGTH_CLOSELOOP_X2U__READ(src) \ + (((uint32_t)(src)\ + & 0x00000e00U) >> 9) +#define RIF_SYNTX0__STATELENGTH_CLOSELOOP_X2U__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000e00U) +#define RIF_SYNTX0__STATELENGTH_CLOSELOOP_X2U__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((uint32_t)(src) <<\ + 9) & 0x00000e00U) +#define RIF_SYNTX0__STATELENGTH_CLOSELOOP_X2U__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000e00U))) +#define RIF_SYNTX0__STATELENGTH_CLOSELOOP_X2U__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field stateLength_modGainCal_x64u */ +/** + * @defgroup rif_regs_core_stateLength_modGainCal_x64u_field stateLength_modGainCal_x64u_field + * @brief macros for field stateLength_modGainCal_x64u + * @details Length of STATE_MODCAL_COUNT* state is (stateLength_modGainCal_x64u+1)*64u + * @{ + */ +#define RIF_SYNTX0__STATELENGTH_MODGAINCAL_X64U__SHIFT 12 +#define RIF_SYNTX0__STATELENGTH_MODGAINCAL_X64U__WIDTH 4 +#define RIF_SYNTX0__STATELENGTH_MODGAINCAL_X64U__MASK 0x0000f000U +#define RIF_SYNTX0__STATELENGTH_MODGAINCAL_X64U__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f000U) >> 12) +#define RIF_SYNTX0__STATELENGTH_MODGAINCAL_X64U__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0000f000U) +#define RIF_SYNTX0__STATELENGTH_MODGAINCAL_X64U__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((uint32_t)(src) <<\ + 12) & 0x0000f000U) +#define RIF_SYNTX0__STATELENGTH_MODGAINCAL_X64U__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0000f000U))) +#define RIF_SYNTX0__STATELENGTH_MODGAINCAL_X64U__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field vcrefMi */ +/** + * @defgroup rif_regs_core_vcrefMi_field vcrefMi_field + * @brief macros for field vcrefMi + * @details Adjusts the voltage to which the control voltage is pinned during capacitor search. 0 is the lowest value + * @{ + */ +#define RIF_SYNTX0__VCREFMI__SHIFT 16 +#define RIF_SYNTX0__VCREFMI__WIDTH 2 +#define RIF_SYNTX0__VCREFMI__MASK 0x00030000U +#define RIF_SYNTX0__VCREFMI__READ(src) (((uint32_t)(src) & 0x00030000U) >> 16) +#define RIF_SYNTX0__VCREFMI__WRITE(src) (((uint32_t)(src) << 16) & 0x00030000U) +#define RIF_SYNTX0__VCREFMI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00030000U) | (((uint32_t)(src) <<\ + 16) & 0x00030000U) +#define RIF_SYNTX0__VCREFMI__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00030000U))) +#define RIF_SYNTX0__VCREFMI__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field cpLkIntLow */ +/** + * @defgroup rif_regs_core_cpLkIntLow_field cpLkIntLow_field + * @brief macros for field cpLkIntLow + * @details If set, the charge pump leakage current is reduced in integer channels to reduce noise and spurs + * @{ + */ +#define RIF_SYNTX0__CPLKINTLOW__SHIFT 18 +#define RIF_SYNTX0__CPLKINTLOW__WIDTH 1 +#define RIF_SYNTX0__CPLKINTLOW__MASK 0x00040000U +#define RIF_SYNTX0__CPLKINTLOW__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define RIF_SYNTX0__CPLKINTLOW__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define RIF_SYNTX0__CPLKINTLOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define RIF_SYNTX0__CPLKINTLOW__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define RIF_SYNTX0__CPLKINTLOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define RIF_SYNTX0__CPLKINTLOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define RIF_SYNTX0__CPLKINTLOW__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field alwaysCpHiBias */ +/** + * @defgroup rif_regs_core_alwaysCpHiBias_field alwaysCpHiBias_field + * @brief macros for field alwaysCpHiBias + * @details If set, the charge pump bias is forced to always be in high current mode + * @{ + */ +#define RIF_SYNTX0__ALWAYSCPHIBIAS__SHIFT 19 +#define RIF_SYNTX0__ALWAYSCPHIBIAS__WIDTH 1 +#define RIF_SYNTX0__ALWAYSCPHIBIAS__MASK 0x00080000U +#define RIF_SYNTX0__ALWAYSCPHIBIAS__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define RIF_SYNTX0__ALWAYSCPHIBIAS__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define RIF_SYNTX0__ALWAYSCPHIBIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define RIF_SYNTX0__ALWAYSCPHIBIAS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define RIF_SYNTX0__ALWAYSCPHIBIAS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define RIF_SYNTX0__ALWAYSCPHIBIAS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define RIF_SYNTX0__ALWAYSCPHIBIAS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enRXLObufEarly */ +/** + * @defgroup rif_regs_core_enRXLObufEarly_field enRXLObufEarly_field + * @brief macros for field enRXLObufEarly + * @details If set, RXLO buffers are enabled when (enSynthAnalog & ~txon), which is earlier than rxon + * @{ + */ +#define RIF_SYNTX0__ENRXLOBUFEARLY__SHIFT 20 +#define RIF_SYNTX0__ENRXLOBUFEARLY__WIDTH 1 +#define RIF_SYNTX0__ENRXLOBUFEARLY__MASK 0x00100000U +#define RIF_SYNTX0__ENRXLOBUFEARLY__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define RIF_SYNTX0__ENRXLOBUFEARLY__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define RIF_SYNTX0__ENRXLOBUFEARLY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define RIF_SYNTX0__ENRXLOBUFEARLY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define RIF_SYNTX0__ENRXLOBUFEARLY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define RIF_SYNTX0__ENRXLOBUFEARLY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define RIF_SYNTX0__ENRXLOBUFEARLY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rxloSingleStartupAlwaysOn */ +/** + * @defgroup rif_regs_core_rxloSingleStartupAlwaysOn_field rxloSingleStartupAlwaysOn_field + * @brief macros for field rxloSingleStartupAlwaysOn + * @details if =1, forces enSingleStartup to always be high + * @{ + */ +#define RIF_SYNTX0__RXLOSINGLESTARTUPALWAYSON__SHIFT 21 +#define RIF_SYNTX0__RXLOSINGLESTARTUPALWAYSON__WIDTH 1 +#define RIF_SYNTX0__RXLOSINGLESTARTUPALWAYSON__MASK 0x00200000U +#define RIF_SYNTX0__RXLOSINGLESTARTUPALWAYSON__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define RIF_SYNTX0__RXLOSINGLESTARTUPALWAYSON__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define RIF_SYNTX0__RXLOSINGLESTARTUPALWAYSON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define RIF_SYNTX0__RXLOSINGLESTARTUPALWAYSON__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define RIF_SYNTX0__RXLOSINGLESTARTUPALWAYSON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define RIF_SYNTX0__RXLOSINGLESTARTUPALWAYSON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define RIF_SYNTX0__RXLOSINGLESTARTUPALWAYSON__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field useFullBinaryCapSearch_tx */ +/** + * @defgroup rif_regs_core_useFullBinaryCapSearch_tx_field useFullBinaryCapSearch_tx_field + * @brief macros for field useFullBinaryCapSearch_tx + * @details if =1, VCO cap search algorithm reverts to a full binary search at every channel change for TX mode + * @{ + */ +#define RIF_SYNTX0__USEFULLBINARYCAPSEARCH_TX__SHIFT 22 +#define RIF_SYNTX0__USEFULLBINARYCAPSEARCH_TX__WIDTH 1 +#define RIF_SYNTX0__USEFULLBINARYCAPSEARCH_TX__MASK 0x00400000U +#define RIF_SYNTX0__USEFULLBINARYCAPSEARCH_TX__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define RIF_SYNTX0__USEFULLBINARYCAPSEARCH_TX__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define RIF_SYNTX0__USEFULLBINARYCAPSEARCH_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define RIF_SYNTX0__USEFULLBINARYCAPSEARCH_TX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define RIF_SYNTX0__USEFULLBINARYCAPSEARCH_TX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define RIF_SYNTX0__USEFULLBINARYCAPSEARCH_TX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define RIF_SYNTX0__USEFULLBINARYCAPSEARCH_TX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field useFullBinaryCapSearch_rx */ +/** + * @defgroup rif_regs_core_useFullBinaryCapSearch_rx_field useFullBinaryCapSearch_rx_field + * @brief macros for field useFullBinaryCapSearch_rx + * @details if =1, VCO cap search algorithm reverts to a full binary search at every channel change for RX mode + * @{ + */ +#define RIF_SYNTX0__USEFULLBINARYCAPSEARCH_RX__SHIFT 23 +#define RIF_SYNTX0__USEFULLBINARYCAPSEARCH_RX__WIDTH 1 +#define RIF_SYNTX0__USEFULLBINARYCAPSEARCH_RX__MASK 0x00800000U +#define RIF_SYNTX0__USEFULLBINARYCAPSEARCH_RX__READ(src) \ + (((uint32_t)(src)\ + & 0x00800000U) >> 23) +#define RIF_SYNTX0__USEFULLBINARYCAPSEARCH_RX__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define RIF_SYNTX0__USEFULLBINARYCAPSEARCH_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define RIF_SYNTX0__USEFULLBINARYCAPSEARCH_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define RIF_SYNTX0__USEFULLBINARYCAPSEARCH_RX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define RIF_SYNTX0__USEFULLBINARYCAPSEARCH_RX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define RIF_SYNTX0__USEFULLBINARYCAPSEARCH_RX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field synth_spare */ +/** + * @defgroup rif_regs_core_synth_spare_field synth_spare_field + * @brief macros for field synth_spare + * @details spare bits + * @{ + */ +#define RIF_SYNTX0__SYNTH_SPARE__SHIFT 24 +#define RIF_SYNTX0__SYNTH_SPARE__WIDTH 5 +#define RIF_SYNTX0__SYNTH_SPARE__MASK 0x1f000000U +#define RIF_SYNTX0__SYNTH_SPARE__READ(src) \ + (((uint32_t)(src)\ + & 0x1f000000U) >> 24) +#define RIF_SYNTX0__SYNTH_SPARE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x1f000000U) +#define RIF_SYNTX0__SYNTH_SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1f000000U) | (((uint32_t)(src) <<\ + 24) & 0x1f000000U) +#define RIF_SYNTX0__SYNTH_SPARE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x1f000000U))) +#define RIF_SYNTX0__SYNTH_SPARE__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_SYNTX0__TYPE uint32_t +#define RIF_SYNTX0__READ 0x1fffffffU +#define RIF_SYNTX0__WRITE 0x1fffffffU +#define RIF_SYNTX0__PRESERVED 0x00000000U +#define RIF_SYNTX0__RESET_VALUE 0x00061899U + +#endif /* __RIF_SYNTX0_MACRO__ */ + +/** @} end of syntx0 */ + +/* macros for BlueprintGlobalNameSpace::RIF_syntx1 */ +/** + * @defgroup rif_regs_core_syntx1 syntx1 + * @brief Synth loop parameters for TX 1M mode definitions. + * @{ + */ +#ifndef __RIF_SYNTX1_MACRO__ +#define __RIF_SYNTX1_MACRO__ + +/* macros for field loopReferenceFrequency_tx1 */ +/** + * @defgroup rif_regs_core_loopReferenceFrequency_tx1_field loopReferenceFrequency_tx1_field + * @brief macros for field loopReferenceFrequency_tx1 + * @details Loop reference frequency, 0 -> 8MHz (only with 8MHz crystal), 1 -> 16MHz, 2 -> 32MHz (only with 16 MHz crystal), 3 -> unused + * @{ + */ +#define RIF_SYNTX1__LOOPREFERENCEFREQUENCY_TX1__SHIFT 0 +#define RIF_SYNTX1__LOOPREFERENCEFREQUENCY_TX1__WIDTH 2 +#define RIF_SYNTX1__LOOPREFERENCEFREQUENCY_TX1__MASK 0x00000003U +#define RIF_SYNTX1__LOOPREFERENCEFREQUENCY_TX1__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define RIF_SYNTX1__LOOPREFERENCEFREQUENCY_TX1__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define RIF_SYNTX1__LOOPREFERENCEFREQUENCY_TX1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define RIF_SYNTX1__LOOPREFERENCEFREQUENCY_TX1__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define RIF_SYNTX1__LOOPREFERENCEFREQUENCY_TX1__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field vcoAgcEn_tx1 */ +/** + * @defgroup rif_regs_core_vcoAgcEn_tx1_field vcoAgcEn_tx1_field + * @brief macros for field vcoAgcEn_tx1 + * @details enables the vco AGC + * @{ + */ +#define RIF_SYNTX1__VCOAGCEN_TX1__SHIFT 2 +#define RIF_SYNTX1__VCOAGCEN_TX1__WIDTH 1 +#define RIF_SYNTX1__VCOAGCEN_TX1__MASK 0x00000004U +#define RIF_SYNTX1__VCOAGCEN_TX1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define RIF_SYNTX1__VCOAGCEN_TX1__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define RIF_SYNTX1__VCOAGCEN_TX1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define RIF_SYNTX1__VCOAGCEN_TX1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define RIF_SYNTX1__VCOAGCEN_TX1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define RIF_SYNTX1__VCOAGCEN_TX1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define RIF_SYNTX1__VCOAGCEN_TX1__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field vcoAgcEnGain_tx1 */ +/** + * @defgroup rif_regs_core_vcoAgcEnGain_tx1_field vcoAgcEnGain_tx1_field + * @brief macros for field vcoAgcEnGain_tx1 + * @details vco AGC gain + * @{ + */ +#define RIF_SYNTX1__VCOAGCENGAIN_TX1__SHIFT 3 +#define RIF_SYNTX1__VCOAGCENGAIN_TX1__WIDTH 3 +#define RIF_SYNTX1__VCOAGCENGAIN_TX1__MASK 0x00000038U +#define RIF_SYNTX1__VCOAGCENGAIN_TX1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define RIF_SYNTX1__VCOAGCENGAIN_TX1__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define RIF_SYNTX1__VCOAGCENGAIN_TX1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define RIF_SYNTX1__VCOAGCENGAIN_TX1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define RIF_SYNTX1__VCOAGCENGAIN_TX1__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field vcoBias_tx1 */ +/** + * @defgroup rif_regs_core_vcoBias_tx1_field vcoBias_tx1_field + * @brief macros for field vcoBias_tx1 + * @details vco bias, also the target value for the vco AGC when it is enabled + * @{ + */ +#define RIF_SYNTX1__VCOBIAS_TX1__SHIFT 6 +#define RIF_SYNTX1__VCOBIAS_TX1__WIDTH 4 +#define RIF_SYNTX1__VCOBIAS_TX1__MASK 0x000003c0U +#define RIF_SYNTX1__VCOBIAS_TX1__READ(src) \ + (((uint32_t)(src)\ + & 0x000003c0U) >> 6) +#define RIF_SYNTX1__VCOBIAS_TX1__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000003c0U) +#define RIF_SYNTX1__VCOBIAS_TX1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003c0U) | (((uint32_t)(src) <<\ + 6) & 0x000003c0U) +#define RIF_SYNTX1__VCOBIAS_TX1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000003c0U))) +#define RIF_SYNTX1__VCOBIAS_TX1__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field cpBias_tx1 */ +/** + * @defgroup rif_regs_core_cpBias_tx1_field cpBias_tx1_field + * @brief macros for field cpBias_tx1 + * @details charge pump bias current + * @{ + */ +#define RIF_SYNTX1__CPBIAS_TX1__SHIFT 10 +#define RIF_SYNTX1__CPBIAS_TX1__WIDTH 4 +#define RIF_SYNTX1__CPBIAS_TX1__MASK 0x00003c00U +#define RIF_SYNTX1__CPBIAS_TX1__READ(src) \ + (((uint32_t)(src)\ + & 0x00003c00U) >> 10) +#define RIF_SYNTX1__CPBIAS_TX1__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00003c00U) +#define RIF_SYNTX1__CPBIAS_TX1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003c00U) | (((uint32_t)(src) <<\ + 10) & 0x00003c00U) +#define RIF_SYNTX1__CPBIAS_TX1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00003c00U))) +#define RIF_SYNTX1__CPBIAS_TX1__RESET_VALUE 0x00000009U +/** @} */ + +/* macros for field cpCur_tx1 */ +/** + * @defgroup rif_regs_core_cpCur_tx1_field cpCur_tx1_field + * @brief macros for field cpCur_tx1 + * @details charge pump current (Icp = (1+cpBias<3:0>) * (1+cpCur<3:0>) * 1.5uA = (1+cpCur<3:0>) * 24uA (for cbBias<3:0>=0xf) = (1+cpBias<3:0>) * 24uA (for cpCur<3:0>=0xf) = 384uA max) + * @{ + */ +#define RIF_SYNTX1__CPCUR_TX1__SHIFT 14 +#define RIF_SYNTX1__CPCUR_TX1__WIDTH 4 +#define RIF_SYNTX1__CPCUR_TX1__MASK 0x0003c000U +#define RIF_SYNTX1__CPCUR_TX1__READ(src) \ + (((uint32_t)(src)\ + & 0x0003c000U) >> 14) +#define RIF_SYNTX1__CPCUR_TX1__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0003c000U) +#define RIF_SYNTX1__CPCUR_TX1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003c000U) | (((uint32_t)(src) <<\ + 14) & 0x0003c000U) +#define RIF_SYNTX1__CPCUR_TX1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0003c000U))) +#define RIF_SYNTX1__CPCUR_TX1__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field cpLk_tx1 */ +/** + * @defgroup rif_regs_core_cpLk_tx1_field cpLk_tx1_field + * @brief macros for field cpLk_tx1 + * @details charge pump leakage current (Iup = 125nA * (1 + lk<3:0>) = 2uA max, DC = Iup/Idn*100% =(1 + lk<3:0>) * 0.52% = 8.32% max) + * @{ + */ +#define RIF_SYNTX1__CPLK_TX1__SHIFT 18 +#define RIF_SYNTX1__CPLK_TX1__WIDTH 4 +#define RIF_SYNTX1__CPLK_TX1__MASK 0x003c0000U +#define RIF_SYNTX1__CPLK_TX1__READ(src) (((uint32_t)(src) & 0x003c0000U) >> 18) +#define RIF_SYNTX1__CPLK_TX1__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x003c0000U) +#define RIF_SYNTX1__CPLK_TX1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003c0000U) | (((uint32_t)(src) <<\ + 18) & 0x003c0000U) +#define RIF_SYNTX1__CPLK_TX1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x003c0000U))) +#define RIF_SYNTX1__CPLK_TX1__RESET_VALUE 0x0000000cU +/** @} */ + +/* macros for field filtC_tx1 */ +/** + * @defgroup rif_regs_core_filtC_tx1_field filtC_tx1_field + * @brief macros for field filtC_tx1 + * @details Loop filter capacitor setting Cs = 100p*(0.5 + 0.5/3*filtC<1:0>) Cp = 2.28p(inside 3rd order filter) + 3.42p + 5.64p/3*filtC<1:0> + * @{ + */ +#define RIF_SYNTX1__FILTC_TX1__SHIFT 22 +#define RIF_SYNTX1__FILTC_TX1__WIDTH 2 +#define RIF_SYNTX1__FILTC_TX1__MASK 0x00c00000U +#define RIF_SYNTX1__FILTC_TX1__READ(src) \ + (((uint32_t)(src)\ + & 0x00c00000U) >> 22) +#define RIF_SYNTX1__FILTC_TX1__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00c00000U) +#define RIF_SYNTX1__FILTC_TX1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00c00000U) | (((uint32_t)(src) <<\ + 22) & 0x00c00000U) +#define RIF_SYNTX1__FILTC_TX1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00c00000U))) +#define RIF_SYNTX1__FILTC_TX1__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field filtRs_tx1 */ +/** + * @defgroup rif_regs_core_filtRs_tx1_field filtRs_tx1_field + * @brief macros for field filtRs_tx1 + * @details Loop filter Rs setting (0..15) -> Rs=(13, 17, 21, 27, 33, 41, 49, 61, 73, 89, 109, 133, 161, 197, 241, 301)KOhms + * @{ + */ +#define RIF_SYNTX1__FILTRS_TX1__SHIFT 24 +#define RIF_SYNTX1__FILTRS_TX1__WIDTH 4 +#define RIF_SYNTX1__FILTRS_TX1__MASK 0x0f000000U +#define RIF_SYNTX1__FILTRS_TX1__READ(src) \ + (((uint32_t)(src)\ + & 0x0f000000U) >> 24) +#define RIF_SYNTX1__FILTRS_TX1__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x0f000000U) +#define RIF_SYNTX1__FILTRS_TX1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f000000U) | (((uint32_t)(src) <<\ + 24) & 0x0f000000U) +#define RIF_SYNTX1__FILTRS_TX1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x0f000000U))) +#define RIF_SYNTX1__FILTRS_TX1__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field filtR3_tx1 */ +/** + * @defgroup rif_regs_core_filtR3_tx1_field filtR3_tx1_field + * @brief macros for field filtR3_tx1 + * @details Loop filter resistor for 3rd pole (0..15) -> Rs=(13, 17, 21, 27, 33, 41, 49, 61, 73, 89, 109, 133, 161, 197, 241, 301)KOhms. (0..15) -> p3=(5.37, 4.11, 3.32, 2.58, 2.12, 1.70, 1.42, 1.14, 0.95, 0.78, 0.64, 0.52, 0.43, 0.35, 0.29, 0.23)MHz + * @{ + */ +#define RIF_SYNTX1__FILTR3_TX1__SHIFT 28 +#define RIF_SYNTX1__FILTR3_TX1__WIDTH 4 +#define RIF_SYNTX1__FILTR3_TX1__MASK 0xf0000000U +#define RIF_SYNTX1__FILTR3_TX1__READ(src) \ + (((uint32_t)(src)\ + & 0xf0000000U) >> 28) +#define RIF_SYNTX1__FILTR3_TX1__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0xf0000000U) +#define RIF_SYNTX1__FILTR3_TX1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf0000000U) | (((uint32_t)(src) <<\ + 28) & 0xf0000000U) +#define RIF_SYNTX1__FILTR3_TX1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0xf0000000U))) +#define RIF_SYNTX1__FILTR3_TX1__RESET_VALUE 0x00000007U +/** @} */ +#define RIF_SYNTX1__TYPE uint32_t +#define RIF_SYNTX1__READ 0xffffffffU +#define RIF_SYNTX1__WRITE 0xffffffffU +#define RIF_SYNTX1__PRESERVED 0x00000000U +#define RIF_SYNTX1__RESET_VALUE 0x74f0663eU + +#endif /* __RIF_SYNTX1_MACRO__ */ + +/** @} end of syntx1 */ + +/* macros for BlueprintGlobalNameSpace::RIF_syntx2 */ +/** + * @defgroup rif_regs_core_syntx2 syntx2 + * @brief Synth loop parameters for TX 2M mode 2Mbps definitions. + * @{ + */ +#ifndef __RIF_SYNTX2_MACRO__ +#define __RIF_SYNTX2_MACRO__ + +/* macros for field loopReferenceFrequency_tx2 */ +/** + * @defgroup rif_regs_core_loopReferenceFrequency_tx2_field loopReferenceFrequency_tx2_field + * @brief macros for field loopReferenceFrequency_tx2 + * @details Loop reference frequency, 0 -> 8MHz, 1 -> 16MHz, 2 = 32MHz + * @{ + */ +#define RIF_SYNTX2__LOOPREFERENCEFREQUENCY_TX2__SHIFT 0 +#define RIF_SYNTX2__LOOPREFERENCEFREQUENCY_TX2__WIDTH 2 +#define RIF_SYNTX2__LOOPREFERENCEFREQUENCY_TX2__MASK 0x00000003U +#define RIF_SYNTX2__LOOPREFERENCEFREQUENCY_TX2__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define RIF_SYNTX2__LOOPREFERENCEFREQUENCY_TX2__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define RIF_SYNTX2__LOOPREFERENCEFREQUENCY_TX2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define RIF_SYNTX2__LOOPREFERENCEFREQUENCY_TX2__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define RIF_SYNTX2__LOOPREFERENCEFREQUENCY_TX2__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field vcoAgcEn_tx2 */ +/** + * @defgroup rif_regs_core_vcoAgcEn_tx2_field vcoAgcEn_tx2_field + * @brief macros for field vcoAgcEn_tx2 + * @details Enable VCO AGC + * @{ + */ +#define RIF_SYNTX2__VCOAGCEN_TX2__SHIFT 2 +#define RIF_SYNTX2__VCOAGCEN_TX2__WIDTH 1 +#define RIF_SYNTX2__VCOAGCEN_TX2__MASK 0x00000004U +#define RIF_SYNTX2__VCOAGCEN_TX2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define RIF_SYNTX2__VCOAGCEN_TX2__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define RIF_SYNTX2__VCOAGCEN_TX2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define RIF_SYNTX2__VCOAGCEN_TX2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define RIF_SYNTX2__VCOAGCEN_TX2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define RIF_SYNTX2__VCOAGCEN_TX2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define RIF_SYNTX2__VCOAGCEN_TX2__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field vcoAgcEnGain_tx2 */ +/** + * @defgroup rif_regs_core_vcoAgcEnGain_tx2_field vcoAgcEnGain_tx2_field + * @brief macros for field vcoAgcEnGain_tx2 + * @details VCO AGC gain setting + * @{ + */ +#define RIF_SYNTX2__VCOAGCENGAIN_TX2__SHIFT 3 +#define RIF_SYNTX2__VCOAGCENGAIN_TX2__WIDTH 3 +#define RIF_SYNTX2__VCOAGCENGAIN_TX2__MASK 0x00000038U +#define RIF_SYNTX2__VCOAGCENGAIN_TX2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define RIF_SYNTX2__VCOAGCENGAIN_TX2__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define RIF_SYNTX2__VCOAGCENGAIN_TX2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define RIF_SYNTX2__VCOAGCENGAIN_TX2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define RIF_SYNTX2__VCOAGCENGAIN_TX2__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field vcoBias_tx2 */ +/** + * @defgroup rif_regs_core_vcoBias_tx2_field vcoBias_tx2_field + * @brief macros for field vcoBias_tx2 + * @details VCO bias setting + * @{ + */ +#define RIF_SYNTX2__VCOBIAS_TX2__SHIFT 6 +#define RIF_SYNTX2__VCOBIAS_TX2__WIDTH 4 +#define RIF_SYNTX2__VCOBIAS_TX2__MASK 0x000003c0U +#define RIF_SYNTX2__VCOBIAS_TX2__READ(src) \ + (((uint32_t)(src)\ + & 0x000003c0U) >> 6) +#define RIF_SYNTX2__VCOBIAS_TX2__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000003c0U) +#define RIF_SYNTX2__VCOBIAS_TX2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003c0U) | (((uint32_t)(src) <<\ + 6) & 0x000003c0U) +#define RIF_SYNTX2__VCOBIAS_TX2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000003c0U))) +#define RIF_SYNTX2__VCOBIAS_TX2__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field cpBias_tx2 */ +/** + * @defgroup rif_regs_core_cpBias_tx2_field cpBias_tx2_field + * @brief macros for field cpBias_tx2 + * @details CP bias setting + * @{ + */ +#define RIF_SYNTX2__CPBIAS_TX2__SHIFT 10 +#define RIF_SYNTX2__CPBIAS_TX2__WIDTH 4 +#define RIF_SYNTX2__CPBIAS_TX2__MASK 0x00003c00U +#define RIF_SYNTX2__CPBIAS_TX2__READ(src) \ + (((uint32_t)(src)\ + & 0x00003c00U) >> 10) +#define RIF_SYNTX2__CPBIAS_TX2__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00003c00U) +#define RIF_SYNTX2__CPBIAS_TX2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003c00U) | (((uint32_t)(src) <<\ + 10) & 0x00003c00U) +#define RIF_SYNTX2__CPBIAS_TX2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00003c00U))) +#define RIF_SYNTX2__CPBIAS_TX2__RESET_VALUE 0x0000000eU +/** @} */ + +/* macros for field cpCur_tx2 */ +/** + * @defgroup rif_regs_core_cpCur_tx2_field cpCur_tx2_field + * @brief macros for field cpCur_tx2 + * @details CP current setting + * @{ + */ +#define RIF_SYNTX2__CPCUR_TX2__SHIFT 14 +#define RIF_SYNTX2__CPCUR_TX2__WIDTH 4 +#define RIF_SYNTX2__CPCUR_TX2__MASK 0x0003c000U +#define RIF_SYNTX2__CPCUR_TX2__READ(src) \ + (((uint32_t)(src)\ + & 0x0003c000U) >> 14) +#define RIF_SYNTX2__CPCUR_TX2__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0003c000U) +#define RIF_SYNTX2__CPCUR_TX2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003c000U) | (((uint32_t)(src) <<\ + 14) & 0x0003c000U) +#define RIF_SYNTX2__CPCUR_TX2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0003c000U))) +#define RIF_SYNTX2__CPCUR_TX2__RESET_VALUE 0x00000005U +/** @} */ + +/* macros for field cpLk_tx2 */ +/** + * @defgroup rif_regs_core_cpLk_tx2_field cpLk_tx2_field + * @brief macros for field cpLk_tx2 + * @details CP leakage setting + * @{ + */ +#define RIF_SYNTX2__CPLK_TX2__SHIFT 18 +#define RIF_SYNTX2__CPLK_TX2__WIDTH 4 +#define RIF_SYNTX2__CPLK_TX2__MASK 0x003c0000U +#define RIF_SYNTX2__CPLK_TX2__READ(src) (((uint32_t)(src) & 0x003c0000U) >> 18) +#define RIF_SYNTX2__CPLK_TX2__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x003c0000U) +#define RIF_SYNTX2__CPLK_TX2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003c0000U) | (((uint32_t)(src) <<\ + 18) & 0x003c0000U) +#define RIF_SYNTX2__CPLK_TX2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x003c0000U))) +#define RIF_SYNTX2__CPLK_TX2__RESET_VALUE 0x0000000cU +/** @} */ + +/* macros for field filtC_tx2 */ +/** + * @defgroup rif_regs_core_filtC_tx2_field filtC_tx2_field + * @brief macros for field filtC_tx2 + * @details Loop filter series big C setting + * @{ + */ +#define RIF_SYNTX2__FILTC_TX2__SHIFT 22 +#define RIF_SYNTX2__FILTC_TX2__WIDTH 2 +#define RIF_SYNTX2__FILTC_TX2__MASK 0x00c00000U +#define RIF_SYNTX2__FILTC_TX2__READ(src) \ + (((uint32_t)(src)\ + & 0x00c00000U) >> 22) +#define RIF_SYNTX2__FILTC_TX2__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00c00000U) +#define RIF_SYNTX2__FILTC_TX2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00c00000U) | (((uint32_t)(src) <<\ + 22) & 0x00c00000U) +#define RIF_SYNTX2__FILTC_TX2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00c00000U))) +#define RIF_SYNTX2__FILTC_TX2__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field filtRs_tx2 */ +/** + * @defgroup rif_regs_core_filtRs_tx2_field filtRs_tx2_field + * @brief macros for field filtRs_tx2 + * @details Loop filter series R setting + * @{ + */ +#define RIF_SYNTX2__FILTRS_TX2__SHIFT 24 +#define RIF_SYNTX2__FILTRS_TX2__WIDTH 4 +#define RIF_SYNTX2__FILTRS_TX2__MASK 0x0f000000U +#define RIF_SYNTX2__FILTRS_TX2__READ(src) \ + (((uint32_t)(src)\ + & 0x0f000000U) >> 24) +#define RIF_SYNTX2__FILTRS_TX2__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x0f000000U) +#define RIF_SYNTX2__FILTRS_TX2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f000000U) | (((uint32_t)(src) <<\ + 24) & 0x0f000000U) +#define RIF_SYNTX2__FILTRS_TX2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x0f000000U))) +#define RIF_SYNTX2__FILTRS_TX2__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field filtR3_tx2 */ +/** + * @defgroup rif_regs_core_filtR3_tx2_field filtR3_tx2_field + * @brief macros for field filtR3_tx2 + * @details Loop filter 3rd order R setting + * @{ + */ +#define RIF_SYNTX2__FILTR3_TX2__SHIFT 28 +#define RIF_SYNTX2__FILTR3_TX2__WIDTH 4 +#define RIF_SYNTX2__FILTR3_TX2__MASK 0xf0000000U +#define RIF_SYNTX2__FILTR3_TX2__READ(src) \ + (((uint32_t)(src)\ + & 0xf0000000U) >> 28) +#define RIF_SYNTX2__FILTR3_TX2__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0xf0000000U) +#define RIF_SYNTX2__FILTR3_TX2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf0000000U) | (((uint32_t)(src) <<\ + 28) & 0xf0000000U) +#define RIF_SYNTX2__FILTR3_TX2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0xf0000000U))) +#define RIF_SYNTX2__FILTR3_TX2__RESET_VALUE 0x00000004U +/** @} */ +#define RIF_SYNTX2__TYPE uint32_t +#define RIF_SYNTX2__READ 0xffffffffU +#define RIF_SYNTX2__WRITE 0xffffffffU +#define RIF_SYNTX2__PRESERVED 0x00000000U +#define RIF_SYNTX2__RESET_VALUE 0x41f17a3eU + +#endif /* __RIF_SYNTX2_MACRO__ */ + +/** @} end of syntx2 */ + +/* macros for BlueprintGlobalNameSpace::RIF_syntx3 */ +/** + * @defgroup rif_regs_core_syntx3 syntx3 + * @brief Synth loop parameters for RX mode definitions. + * @{ + */ +#ifndef __RIF_SYNTX3_MACRO__ +#define __RIF_SYNTX3_MACRO__ + +/* macros for field loopReferenceFrequency_rx */ +/** + * @defgroup rif_regs_core_loopReferenceFrequency_rx_field loopReferenceFrequency_rx_field + * @brief macros for field loopReferenceFrequency_rx + * @details Loop reference frequency, 0 -> 8MHz, 1 -> 16MHz, 2 = 32MHz + * @{ + */ +#define RIF_SYNTX3__LOOPREFERENCEFREQUENCY_RX__SHIFT 0 +#define RIF_SYNTX3__LOOPREFERENCEFREQUENCY_RX__WIDTH 2 +#define RIF_SYNTX3__LOOPREFERENCEFREQUENCY_RX__MASK 0x00000003U +#define RIF_SYNTX3__LOOPREFERENCEFREQUENCY_RX__READ(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define RIF_SYNTX3__LOOPREFERENCEFREQUENCY_RX__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000003U) +#define RIF_SYNTX3__LOOPREFERENCEFREQUENCY_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define RIF_SYNTX3__LOOPREFERENCEFREQUENCY_RX__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define RIF_SYNTX3__LOOPREFERENCEFREQUENCY_RX__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field vcoAgcEn_rx */ +/** + * @defgroup rif_regs_core_vcoAgcEn_rx_field vcoAgcEn_rx_field + * @brief macros for field vcoAgcEn_rx + * @details Enable VCO AGC + * @{ + */ +#define RIF_SYNTX3__VCOAGCEN_RX__SHIFT 2 +#define RIF_SYNTX3__VCOAGCEN_RX__WIDTH 1 +#define RIF_SYNTX3__VCOAGCEN_RX__MASK 0x00000004U +#define RIF_SYNTX3__VCOAGCEN_RX__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define RIF_SYNTX3__VCOAGCEN_RX__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define RIF_SYNTX3__VCOAGCEN_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define RIF_SYNTX3__VCOAGCEN_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define RIF_SYNTX3__VCOAGCEN_RX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define RIF_SYNTX3__VCOAGCEN_RX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define RIF_SYNTX3__VCOAGCEN_RX__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field vcoAgcEnGain_rx */ +/** + * @defgroup rif_regs_core_vcoAgcEnGain_rx_field vcoAgcEnGain_rx_field + * @brief macros for field vcoAgcEnGain_rx + * @details VCO AGC gain setting + * @{ + */ +#define RIF_SYNTX3__VCOAGCENGAIN_RX__SHIFT 3 +#define RIF_SYNTX3__VCOAGCENGAIN_RX__WIDTH 3 +#define RIF_SYNTX3__VCOAGCENGAIN_RX__MASK 0x00000038U +#define RIF_SYNTX3__VCOAGCENGAIN_RX__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define RIF_SYNTX3__VCOAGCENGAIN_RX__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define RIF_SYNTX3__VCOAGCENGAIN_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define RIF_SYNTX3__VCOAGCENGAIN_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define RIF_SYNTX3__VCOAGCENGAIN_RX__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field vcoBias_rx */ +/** + * @defgroup rif_regs_core_vcoBias_rx_field vcoBias_rx_field + * @brief macros for field vcoBias_rx + * @details VCO bias setting + * @{ + */ +#define RIF_SYNTX3__VCOBIAS_RX__SHIFT 6 +#define RIF_SYNTX3__VCOBIAS_RX__WIDTH 4 +#define RIF_SYNTX3__VCOBIAS_RX__MASK 0x000003c0U +#define RIF_SYNTX3__VCOBIAS_RX__READ(src) \ + (((uint32_t)(src)\ + & 0x000003c0U) >> 6) +#define RIF_SYNTX3__VCOBIAS_RX__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000003c0U) +#define RIF_SYNTX3__VCOBIAS_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003c0U) | (((uint32_t)(src) <<\ + 6) & 0x000003c0U) +#define RIF_SYNTX3__VCOBIAS_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000003c0U))) +#define RIF_SYNTX3__VCOBIAS_RX__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field cpBias_rx */ +/** + * @defgroup rif_regs_core_cpBias_rx_field cpBias_rx_field + * @brief macros for field cpBias_rx + * @details CP bias setting + * @{ + */ +#define RIF_SYNTX3__CPBIAS_RX__SHIFT 10 +#define RIF_SYNTX3__CPBIAS_RX__WIDTH 4 +#define RIF_SYNTX3__CPBIAS_RX__MASK 0x00003c00U +#define RIF_SYNTX3__CPBIAS_RX__READ(src) \ + (((uint32_t)(src)\ + & 0x00003c00U) >> 10) +#define RIF_SYNTX3__CPBIAS_RX__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00003c00U) +#define RIF_SYNTX3__CPBIAS_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003c00U) | (((uint32_t)(src) <<\ + 10) & 0x00003c00U) +#define RIF_SYNTX3__CPBIAS_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00003c00U))) +#define RIF_SYNTX3__CPBIAS_RX__RESET_VALUE 0x0000000bU +/** @} */ + +/* macros for field cpCur_rx */ +/** + * @defgroup rif_regs_core_cpCur_rx_field cpCur_rx_field + * @brief macros for field cpCur_rx + * @details CP current setting + * @{ + */ +#define RIF_SYNTX3__CPCUR_RX__SHIFT 14 +#define RIF_SYNTX3__CPCUR_RX__WIDTH 4 +#define RIF_SYNTX3__CPCUR_RX__MASK 0x0003c000U +#define RIF_SYNTX3__CPCUR_RX__READ(src) (((uint32_t)(src) & 0x0003c000U) >> 14) +#define RIF_SYNTX3__CPCUR_RX__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0003c000U) +#define RIF_SYNTX3__CPCUR_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003c000U) | (((uint32_t)(src) <<\ + 14) & 0x0003c000U) +#define RIF_SYNTX3__CPCUR_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0003c000U))) +#define RIF_SYNTX3__CPCUR_RX__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field cpLk_rx */ +/** + * @defgroup rif_regs_core_cpLk_rx_field cpLk_rx_field + * @brief macros for field cpLk_rx + * @details CP leakage setting + * @{ + */ +#define RIF_SYNTX3__CPLK_RX__SHIFT 18 +#define RIF_SYNTX3__CPLK_RX__WIDTH 4 +#define RIF_SYNTX3__CPLK_RX__MASK 0x003c0000U +#define RIF_SYNTX3__CPLK_RX__READ(src) (((uint32_t)(src) & 0x003c0000U) >> 18) +#define RIF_SYNTX3__CPLK_RX__WRITE(src) (((uint32_t)(src) << 18) & 0x003c0000U) +#define RIF_SYNTX3__CPLK_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003c0000U) | (((uint32_t)(src) <<\ + 18) & 0x003c0000U) +#define RIF_SYNTX3__CPLK_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x003c0000U))) +#define RIF_SYNTX3__CPLK_RX__RESET_VALUE 0x0000000bU +/** @} */ + +/* macros for field filtC_rx */ +/** + * @defgroup rif_regs_core_filtC_rx_field filtC_rx_field + * @brief macros for field filtC_rx + * @details Loop filter series big C setting + * @{ + */ +#define RIF_SYNTX3__FILTC_RX__SHIFT 22 +#define RIF_SYNTX3__FILTC_RX__WIDTH 2 +#define RIF_SYNTX3__FILTC_RX__MASK 0x00c00000U +#define RIF_SYNTX3__FILTC_RX__READ(src) (((uint32_t)(src) & 0x00c00000U) >> 22) +#define RIF_SYNTX3__FILTC_RX__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00c00000U) +#define RIF_SYNTX3__FILTC_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00c00000U) | (((uint32_t)(src) <<\ + 22) & 0x00c00000U) +#define RIF_SYNTX3__FILTC_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00c00000U))) +#define RIF_SYNTX3__FILTC_RX__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field filtRs_rx */ +/** + * @defgroup rif_regs_core_filtRs_rx_field filtRs_rx_field + * @brief macros for field filtRs_rx + * @details Loop filter series R setting + * @{ + */ +#define RIF_SYNTX3__FILTRS_RX__SHIFT 24 +#define RIF_SYNTX3__FILTRS_RX__WIDTH 4 +#define RIF_SYNTX3__FILTRS_RX__MASK 0x0f000000U +#define RIF_SYNTX3__FILTRS_RX__READ(src) \ + (((uint32_t)(src)\ + & 0x0f000000U) >> 24) +#define RIF_SYNTX3__FILTRS_RX__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x0f000000U) +#define RIF_SYNTX3__FILTRS_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f000000U) | (((uint32_t)(src) <<\ + 24) & 0x0f000000U) +#define RIF_SYNTX3__FILTRS_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x0f000000U))) +#define RIF_SYNTX3__FILTRS_RX__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field filtR3_rx */ +/** + * @defgroup rif_regs_core_filtR3_rx_field filtR3_rx_field + * @brief macros for field filtR3_rx + * @details Loop filter 3rd order R setting + * @{ + */ +#define RIF_SYNTX3__FILTR3_RX__SHIFT 28 +#define RIF_SYNTX3__FILTR3_RX__WIDTH 4 +#define RIF_SYNTX3__FILTR3_RX__MASK 0xf0000000U +#define RIF_SYNTX3__FILTR3_RX__READ(src) \ + (((uint32_t)(src)\ + & 0xf0000000U) >> 28) +#define RIF_SYNTX3__FILTR3_RX__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0xf0000000U) +#define RIF_SYNTX3__FILTR3_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf0000000U) | (((uint32_t)(src) <<\ + 28) & 0xf0000000U) +#define RIF_SYNTX3__FILTR3_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0xf0000000U))) +#define RIF_SYNTX3__FILTR3_RX__RESET_VALUE 0x00000007U +/** @} */ +#define RIF_SYNTX3__TYPE uint32_t +#define RIF_SYNTX3__READ 0xffffffffU +#define RIF_SYNTX3__WRITE 0xffffffffU +#define RIF_SYNTX3__PRESERVED 0x00000000U +#define RIF_SYNTX3__RESET_VALUE 0x74ec6e3eU + +#endif /* __RIF_SYNTX3_MACRO__ */ + +/** @} end of syntx3 */ + +/* macros for BlueprintGlobalNameSpace::RIF_syntx4 */ +/** + * @defgroup rif_regs_core_syntx4 syntx4 + * @brief Extra synth vcoGain loop parameter, modulation index and ramp controls definitions. + * @{ + */ +#ifndef __RIF_SYNTX4_MACRO__ +#define __RIF_SYNTX4_MACRO__ + +/* macros for field vcoGain_tx1 */ +/** + * @defgroup rif_regs_core_vcoGain_tx1_field vcoGain_tx1_field + * @brief macros for field vcoGain_tx1 + * @details VCO gain in 1Mbps TX mode. Kvco = (vcoGain<2:0> + 1)*13.9MHz/V, Kvcomax=111MHz/v + * @{ + */ +#define RIF_SYNTX4__VCOGAIN_TX1__SHIFT 0 +#define RIF_SYNTX4__VCOGAIN_TX1__WIDTH 3 +#define RIF_SYNTX4__VCOGAIN_TX1__MASK 0x00000007U +#define RIF_SYNTX4__VCOGAIN_TX1__READ(src) ((uint32_t)(src) & 0x00000007U) +#define RIF_SYNTX4__VCOGAIN_TX1__WRITE(src) ((uint32_t)(src) & 0x00000007U) +#define RIF_SYNTX4__VCOGAIN_TX1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define RIF_SYNTX4__VCOGAIN_TX1__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define RIF_SYNTX4__VCOGAIN_TX1__RESET_VALUE 0x00000005U +/** @} */ + +/* macros for field vcoGain_tx2 */ +/** + * @defgroup rif_regs_core_vcoGain_tx2_field vcoGain_tx2_field + * @brief macros for field vcoGain_tx2 + * @details VCO gain in 2Mbps TX mode + * @{ + */ +#define RIF_SYNTX4__VCOGAIN_TX2__SHIFT 3 +#define RIF_SYNTX4__VCOGAIN_TX2__WIDTH 3 +#define RIF_SYNTX4__VCOGAIN_TX2__MASK 0x00000038U +#define RIF_SYNTX4__VCOGAIN_TX2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define RIF_SYNTX4__VCOGAIN_TX2__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define RIF_SYNTX4__VCOGAIN_TX2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define RIF_SYNTX4__VCOGAIN_TX2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define RIF_SYNTX4__VCOGAIN_TX2__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field vcoGain_rx */ +/** + * @defgroup rif_regs_core_vcoGain_rx_field vcoGain_rx_field + * @brief macros for field vcoGain_rx + * @details VCO gain in RX mode. Kvco = (vcoGain<2:0> + 1)*20.8MHz/V, Kvcomax=166MHz/v + * @{ + */ +#define RIF_SYNTX4__VCOGAIN_RX__SHIFT 6 +#define RIF_SYNTX4__VCOGAIN_RX__WIDTH 3 +#define RIF_SYNTX4__VCOGAIN_RX__MASK 0x000001c0U +#define RIF_SYNTX4__VCOGAIN_RX__READ(src) \ + (((uint32_t)(src)\ + & 0x000001c0U) >> 6) +#define RIF_SYNTX4__VCOGAIN_RX__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000001c0U) +#define RIF_SYNTX4__VCOGAIN_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((uint32_t)(src) <<\ + 6) & 0x000001c0U) +#define RIF_SYNTX4__VCOGAIN_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000001c0U))) +#define RIF_SYNTX4__VCOGAIN_RX__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field disableVcoGainInMinSS */ +/** + * @defgroup rif_regs_core_disableVcoGainInMinSS_field disableVcoGainInMinSS_field + * @brief macros for field disableVcoGainInMinSS + * @{ + */ +#define RIF_SYNTX4__DISABLEVCOGAININMINSS__SHIFT 9 +#define RIF_SYNTX4__DISABLEVCOGAININMINSS__WIDTH 1 +#define RIF_SYNTX4__DISABLEVCOGAININMINSS__MASK 0x00000200U +#define RIF_SYNTX4__DISABLEVCOGAININMINSS__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define RIF_SYNTX4__DISABLEVCOGAININMINSS__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define RIF_SYNTX4__DISABLEVCOGAININMINSS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define RIF_SYNTX4__DISABLEVCOGAININMINSS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define RIF_SYNTX4__DISABLEVCOGAININMINSS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define RIF_SYNTX4__DISABLEVCOGAININMINSS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define RIF_SYNTX4__DISABLEVCOGAININMINSS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mod_idx */ +/** + * @defgroup rif_regs_core_mod_idx_field mod_idx_field + * @brief macros for field mod_idx + * @details MAX VALUE = 251, not 255 + * @{ + */ +#define RIF_SYNTX4__MOD_IDX__SHIFT 10 +#define RIF_SYNTX4__MOD_IDX__WIDTH 8 +#define RIF_SYNTX4__MOD_IDX__MASK 0x0003fc00U +#define RIF_SYNTX4__MOD_IDX__READ(src) (((uint32_t)(src) & 0x0003fc00U) >> 10) +#define RIF_SYNTX4__MOD_IDX__WRITE(src) (((uint32_t)(src) << 10) & 0x0003fc00U) +#define RIF_SYNTX4__MOD_IDX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fc00U) | (((uint32_t)(src) <<\ + 10) & 0x0003fc00U) +#define RIF_SYNTX4__MOD_IDX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x0003fc00U))) +#define RIF_SYNTX4__MOD_IDX__RESET_VALUE 0x00000080U +/** @} */ + +/* macros for field fast_mod_ramp_down */ +/** + * @defgroup rif_regs_core_fast_mod_ramp_down_field fast_mod_ramp_down_field + * @brief macros for field fast_mod_ramp_down + * @details If set, instant frequency deviation step from last symbol back to carrier rather than smooth transition + * @{ + */ +#define RIF_SYNTX4__FAST_MOD_RAMP_DOWN__SHIFT 18 +#define RIF_SYNTX4__FAST_MOD_RAMP_DOWN__WIDTH 1 +#define RIF_SYNTX4__FAST_MOD_RAMP_DOWN__MASK 0x00040000U +#define RIF_SYNTX4__FAST_MOD_RAMP_DOWN__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define RIF_SYNTX4__FAST_MOD_RAMP_DOWN__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define RIF_SYNTX4__FAST_MOD_RAMP_DOWN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define RIF_SYNTX4__FAST_MOD_RAMP_DOWN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define RIF_SYNTX4__FAST_MOD_RAMP_DOWN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define RIF_SYNTX4__FAST_MOD_RAMP_DOWN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define RIF_SYNTX4__FAST_MOD_RAMP_DOWN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fast_mod_ramp_up */ +/** + * @defgroup rif_regs_core_fast_mod_ramp_up_field fast_mod_ramp_up_field + * @brief macros for field fast_mod_ramp_up + * @details If set, instant frequency deviation step from carrier to first symbol rather than smooth transition + * @{ + */ +#define RIF_SYNTX4__FAST_MOD_RAMP_UP__SHIFT 19 +#define RIF_SYNTX4__FAST_MOD_RAMP_UP__WIDTH 1 +#define RIF_SYNTX4__FAST_MOD_RAMP_UP__MASK 0x00080000U +#define RIF_SYNTX4__FAST_MOD_RAMP_UP__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define RIF_SYNTX4__FAST_MOD_RAMP_UP__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define RIF_SYNTX4__FAST_MOD_RAMP_UP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define RIF_SYNTX4__FAST_MOD_RAMP_UP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define RIF_SYNTX4__FAST_MOD_RAMP_UP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define RIF_SYNTX4__FAST_MOD_RAMP_UP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define RIF_SYNTX4__FAST_MOD_RAMP_UP__RESET_VALUE 0x00000001U +/** @} */ +#define RIF_SYNTX4__TYPE uint32_t +#define RIF_SYNTX4__READ 0x000fffffU +#define RIF_SYNTX4__WRITE 0x000fffffU +#define RIF_SYNTX4__PRESERVED 0x00000000U +#define RIF_SYNTX4__RESET_VALUE 0x000a00e5U + +#endif /* __RIF_SYNTX4_MACRO__ */ + +/** @} end of syntx4 */ + +/* macros for BlueprintGlobalNameSpace::RIF_syntx5 */ +/** + * @defgroup rif_regs_core_syntx5 syntx5 + * @brief PA settings and more spares definitions. + * @{ + */ +#ifndef __RIF_SYNTX5_MACRO__ +#define __RIF_SYNTX5_MACRO__ + +/* macros for field pa_cas */ +/** + * @defgroup rif_regs_core_pa_cas_field pa_cas_field + * @brief macros for field pa_cas + * @details PA cascode bias voltage + * @{ + */ +#define RIF_SYNTX5__PA_CAS__SHIFT 5 +#define RIF_SYNTX5__PA_CAS__WIDTH 3 +#define RIF_SYNTX5__PA_CAS__MASK 0x000000e0U +#define RIF_SYNTX5__PA_CAS__READ(src) (((uint32_t)(src) & 0x000000e0U) >> 5) +#define RIF_SYNTX5__PA_CAS__WRITE(src) (((uint32_t)(src) << 5) & 0x000000e0U) +#define RIF_SYNTX5__PA_CAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((uint32_t)(src) <<\ + 5) & 0x000000e0U) +#define RIF_SYNTX5__PA_CAS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000000e0U))) +#define RIF_SYNTX5__PA_CAS__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field pa_ctx */ +/** + * @defgroup rif_regs_core_pa_ctx_field pa_ctx_field + * @brief macros for field pa_ctx + * @details 0 = ground cascode gates of unused PA devices during TX, could cause extra stress but improve efficiency, 1 = all devices stay biased at cascode voltage + * @{ + */ +#define RIF_SYNTX5__PA_CTX__SHIFT 8 +#define RIF_SYNTX5__PA_CTX__WIDTH 1 +#define RIF_SYNTX5__PA_CTX__MASK 0x00000100U +#define RIF_SYNTX5__PA_CTX__READ(src) (((uint32_t)(src) & 0x00000100U) >> 8) +#define RIF_SYNTX5__PA_CTX__WRITE(src) (((uint32_t)(src) << 8) & 0x00000100U) +#define RIF_SYNTX5__PA_CTX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define RIF_SYNTX5__PA_CTX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define RIF_SYNTX5__PA_CTX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define RIF_SYNTX5__PA_CTX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define RIF_SYNTX5__PA_CTX__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pa_ctune_rx */ +/** + * @defgroup rif_regs_core_pa_ctune_rx_field pa_ctune_rx_field + * @brief macros for field pa_ctune_rx + * @details Controls number of PA stages whose cascode gate is tied high to get programmable matching cap in RX + * @{ + */ +#define RIF_SYNTX5__PA_CTUNE_RX__SHIFT 9 +#define RIF_SYNTX5__PA_CTUNE_RX__WIDTH 4 +#define RIF_SYNTX5__PA_CTUNE_RX__MASK 0x00001e00U +#define RIF_SYNTX5__PA_CTUNE_RX__READ(src) \ + (((uint32_t)(src)\ + & 0x00001e00U) >> 9) +#define RIF_SYNTX5__PA_CTUNE_RX__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00001e00U) +#define RIF_SYNTX5__PA_CTUNE_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001e00U) | (((uint32_t)(src) <<\ + 9) & 0x00001e00U) +#define RIF_SYNTX5__PA_CTUNE_RX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00001e00U))) +#define RIF_SYNTX5__PA_CTUNE_RX__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_SYNTX5__TYPE uint32_t +#define RIF_SYNTX5__READ 0x00001fe0U +#define RIF_SYNTX5__WRITE 0x00001fe0U +#define RIF_SYNTX5__PRESERVED 0x00000000U +#define RIF_SYNTX5__RESET_VALUE 0x00000180U + +#endif /* __RIF_SYNTX5_MACRO__ */ + +/** @} end of syntx5 */ + +/* macros for BlueprintGlobalNameSpace::RIF_duty_cycle */ +/** + * @defgroup rif_regs_core_duty_cycle duty_cycle + * @brief PA duty cycle definitions. + * @{ + */ +#ifndef __RIF_DUTY_CYCLE_MACRO__ +#define __RIF_DUTY_CYCLE_MACRO__ + +/* macros for field tx_index0_to_6 */ +/** + * @defgroup rif_regs_core_tx_index0_to_6_field tx_index0_to_6_field + * @brief macros for field tx_index0_to_6 + * @details duty cycle to use when tx_index is between 0 and 6, inclusive + * @{ + */ +#define RIF_DUTY_CYCLE__TX_INDEX0_TO_6__SHIFT 0 +#define RIF_DUTY_CYCLE__TX_INDEX0_TO_6__WIDTH 4 +#define RIF_DUTY_CYCLE__TX_INDEX0_TO_6__MASK 0x0000000fU +#define RIF_DUTY_CYCLE__TX_INDEX0_TO_6__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define RIF_DUTY_CYCLE__TX_INDEX0_TO_6__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define RIF_DUTY_CYCLE__TX_INDEX0_TO_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define RIF_DUTY_CYCLE__TX_INDEX0_TO_6__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define RIF_DUTY_CYCLE__TX_INDEX0_TO_6__RESET_VALUE 0x0000000fU +/** @} */ + +/* macros for field tx_index7 */ +/** + * @defgroup rif_regs_core_tx_index7_field tx_index7_field + * @brief macros for field tx_index7 + * @details duty cycle to use when tx_index is 7 + * @{ + */ +#define RIF_DUTY_CYCLE__TX_INDEX7__SHIFT 4 +#define RIF_DUTY_CYCLE__TX_INDEX7__WIDTH 4 +#define RIF_DUTY_CYCLE__TX_INDEX7__MASK 0x000000f0U +#define RIF_DUTY_CYCLE__TX_INDEX7__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define RIF_DUTY_CYCLE__TX_INDEX7__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x000000f0U) +#define RIF_DUTY_CYCLE__TX_INDEX7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define RIF_DUTY_CYCLE__TX_INDEX7__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define RIF_DUTY_CYCLE__TX_INDEX7__RESET_VALUE 0x0000000bU +/** @} */ + +/* macros for field tx_index8 */ +/** + * @defgroup rif_regs_core_tx_index8_field tx_index8_field + * @brief macros for field tx_index8 + * @details duty cycle to use when tx_index is 8 + * @{ + */ +#define RIF_DUTY_CYCLE__TX_INDEX8__SHIFT 8 +#define RIF_DUTY_CYCLE__TX_INDEX8__WIDTH 4 +#define RIF_DUTY_CYCLE__TX_INDEX8__MASK 0x00000f00U +#define RIF_DUTY_CYCLE__TX_INDEX8__READ(src) \ + (((uint32_t)(src)\ + & 0x00000f00U) >> 8) +#define RIF_DUTY_CYCLE__TX_INDEX8__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000f00U) +#define RIF_DUTY_CYCLE__TX_INDEX8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((uint32_t)(src) <<\ + 8) & 0x00000f00U) +#define RIF_DUTY_CYCLE__TX_INDEX8__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000f00U))) +#define RIF_DUTY_CYCLE__TX_INDEX8__RESET_VALUE 0x0000000cU +/** @} */ + +/* macros for field tx_index9 */ +/** + * @defgroup rif_regs_core_tx_index9_field tx_index9_field + * @brief macros for field tx_index9 + * @details duty cycle to use when tx_index is 9 + * @{ + */ +#define RIF_DUTY_CYCLE__TX_INDEX9__SHIFT 12 +#define RIF_DUTY_CYCLE__TX_INDEX9__WIDTH 4 +#define RIF_DUTY_CYCLE__TX_INDEX9__MASK 0x0000f000U +#define RIF_DUTY_CYCLE__TX_INDEX9__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f000U) >> 12) +#define RIF_DUTY_CYCLE__TX_INDEX9__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0000f000U) +#define RIF_DUTY_CYCLE__TX_INDEX9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((uint32_t)(src) <<\ + 12) & 0x0000f000U) +#define RIF_DUTY_CYCLE__TX_INDEX9__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0000f000U))) +#define RIF_DUTY_CYCLE__TX_INDEX9__RESET_VALUE 0x00000009U +/** @} */ + +/* macros for field tx_index10 */ +/** + * @defgroup rif_regs_core_tx_index10_field tx_index10_field + * @brief macros for field tx_index10 + * @details duty cycle to use when tx_index is 10 + * @{ + */ +#define RIF_DUTY_CYCLE__TX_INDEX10__SHIFT 16 +#define RIF_DUTY_CYCLE__TX_INDEX10__WIDTH 4 +#define RIF_DUTY_CYCLE__TX_INDEX10__MASK 0x000f0000U +#define RIF_DUTY_CYCLE__TX_INDEX10__READ(src) \ + (((uint32_t)(src)\ + & 0x000f0000U) >> 16) +#define RIF_DUTY_CYCLE__TX_INDEX10__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x000f0000U) +#define RIF_DUTY_CYCLE__TX_INDEX10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((uint32_t)(src) <<\ + 16) & 0x000f0000U) +#define RIF_DUTY_CYCLE__TX_INDEX10__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x000f0000U))) +#define RIF_DUTY_CYCLE__TX_INDEX10__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field tx_index11 */ +/** + * @defgroup rif_regs_core_tx_index11_field tx_index11_field + * @brief macros for field tx_index11 + * @details duty cycle to use when tx_index is 11 + * @{ + */ +#define RIF_DUTY_CYCLE__TX_INDEX11__SHIFT 20 +#define RIF_DUTY_CYCLE__TX_INDEX11__WIDTH 4 +#define RIF_DUTY_CYCLE__TX_INDEX11__MASK 0x00f00000U +#define RIF_DUTY_CYCLE__TX_INDEX11__READ(src) \ + (((uint32_t)(src)\ + & 0x00f00000U) >> 20) +#define RIF_DUTY_CYCLE__TX_INDEX11__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00f00000U) +#define RIF_DUTY_CYCLE__TX_INDEX11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f00000U) | (((uint32_t)(src) <<\ + 20) & 0x00f00000U) +#define RIF_DUTY_CYCLE__TX_INDEX11__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00f00000U))) +#define RIF_DUTY_CYCLE__TX_INDEX11__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field override_value */ +/** + * @defgroup rif_regs_core_override_value_field override_value_field + * @brief macros for field override_value + * @details if ovr is set, then use override_value and ignore tx_index from LC + * @{ + */ +#define RIF_DUTY_CYCLE__OVERRIDE_VALUE__SHIFT 24 +#define RIF_DUTY_CYCLE__OVERRIDE_VALUE__WIDTH 4 +#define RIF_DUTY_CYCLE__OVERRIDE_VALUE__MASK 0x0f000000U +#define RIF_DUTY_CYCLE__OVERRIDE_VALUE__READ(src) \ + (((uint32_t)(src)\ + & 0x0f000000U) >> 24) +#define RIF_DUTY_CYCLE__OVERRIDE_VALUE__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x0f000000U) +#define RIF_DUTY_CYCLE__OVERRIDE_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f000000U) | (((uint32_t)(src) <<\ + 24) & 0x0f000000U) +#define RIF_DUTY_CYCLE__OVERRIDE_VALUE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x0f000000U))) +#define RIF_DUTY_CYCLE__OVERRIDE_VALUE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ovr */ +/** + * @defgroup rif_regs_core_ovr_field ovr_field + * @brief macros for field ovr + * @details if ovr is set, then use override_value and ignore tx_index from LC + * @{ + */ +#define RIF_DUTY_CYCLE__OVR__SHIFT 28 +#define RIF_DUTY_CYCLE__OVR__WIDTH 1 +#define RIF_DUTY_CYCLE__OVR__MASK 0x10000000U +#define RIF_DUTY_CYCLE__OVR__READ(src) (((uint32_t)(src) & 0x10000000U) >> 28) +#define RIF_DUTY_CYCLE__OVR__WRITE(src) (((uint32_t)(src) << 28) & 0x10000000U) +#define RIF_DUTY_CYCLE__OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define RIF_DUTY_CYCLE__OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define RIF_DUTY_CYCLE__OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define RIF_DUTY_CYCLE__OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define RIF_DUTY_CYCLE__OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pa_invert */ +/** + * @defgroup rif_regs_core_pa_invert_field pa_invert_field + * @brief macros for field pa_invert + * @details Invert PA to get duty cycles <50% + * @{ + */ +#define RIF_DUTY_CYCLE__PA_INVERT__SHIFT 29 +#define RIF_DUTY_CYCLE__PA_INVERT__WIDTH 1 +#define RIF_DUTY_CYCLE__PA_INVERT__MASK 0x20000000U +#define RIF_DUTY_CYCLE__PA_INVERT__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define RIF_DUTY_CYCLE__PA_INVERT__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define RIF_DUTY_CYCLE__PA_INVERT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define RIF_DUTY_CYCLE__PA_INVERT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define RIF_DUTY_CYCLE__PA_INVERT__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define RIF_DUTY_CYCLE__PA_INVERT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define RIF_DUTY_CYCLE__PA_INVERT__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_DUTY_CYCLE__TYPE uint32_t +#define RIF_DUTY_CYCLE__READ 0x3fffffffU +#define RIF_DUTY_CYCLE__WRITE 0x3fffffffU +#define RIF_DUTY_CYCLE__PRESERVED 0x00000000U +#define RIF_DUTY_CYCLE__RESET_VALUE 0x00079cbfU + +#endif /* __RIF_DUTY_CYCLE_MACRO__ */ + +/** @} end of duty_cycle */ + +/* macros for BlueprintGlobalNameSpace::RIF_txgain0_pmu */ +/** + * @defgroup rif_regs_core_txgain0_pmu txgain0_pmu + * @brief TX power table for pmu using VSTORE as PA supply, entries 0 to 4, paRef[5:0] definitions. + * @{ + */ +#ifndef __RIF_TXGAIN0_PMU_MACRO__ +#define __RIF_TXGAIN0_PMU_MACRO__ + +/* macros for field entry0 */ +/** + * @defgroup rif_regs_core_entry0_field entry0_field + * @brief macros for field entry0 + * @details TX power level entry 0, -20dBm + * @{ + */ +#define RIF_TXGAIN0_PMU__ENTRY0__SHIFT 0 +#define RIF_TXGAIN0_PMU__ENTRY0__WIDTH 6 +#define RIF_TXGAIN0_PMU__ENTRY0__MASK 0x0000003fU +#define RIF_TXGAIN0_PMU__ENTRY0__READ(src) ((uint32_t)(src) & 0x0000003fU) +#define RIF_TXGAIN0_PMU__ENTRY0__WRITE(src) ((uint32_t)(src) & 0x0000003fU) +#define RIF_TXGAIN0_PMU__ENTRY0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define RIF_TXGAIN0_PMU__ENTRY0__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define RIF_TXGAIN0_PMU__ENTRY0__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field entry1 */ +/** + * @defgroup rif_regs_core_entry1_field entry1_field + * @brief macros for field entry1 + * @details TX power level entry 1, -10dBm + * @{ + */ +#define RIF_TXGAIN0_PMU__ENTRY1__SHIFT 6 +#define RIF_TXGAIN0_PMU__ENTRY1__WIDTH 6 +#define RIF_TXGAIN0_PMU__ENTRY1__MASK 0x00000fc0U +#define RIF_TXGAIN0_PMU__ENTRY1__READ(src) \ + (((uint32_t)(src)\ + & 0x00000fc0U) >> 6) +#define RIF_TXGAIN0_PMU__ENTRY1__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000fc0U) +#define RIF_TXGAIN0_PMU__ENTRY1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((uint32_t)(src) <<\ + 6) & 0x00000fc0U) +#define RIF_TXGAIN0_PMU__ENTRY1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000fc0U))) +#define RIF_TXGAIN0_PMU__ENTRY1__RESET_VALUE 0x0000000cU +/** @} */ + +/* macros for field entry2 */ +/** + * @defgroup rif_regs_core_entry2_field entry2_field + * @brief macros for field entry2 + * @details TX power level entry 2, -8dBm + * @{ + */ +#define RIF_TXGAIN0_PMU__ENTRY2__SHIFT 12 +#define RIF_TXGAIN0_PMU__ENTRY2__WIDTH 6 +#define RIF_TXGAIN0_PMU__ENTRY2__MASK 0x0003f000U +#define RIF_TXGAIN0_PMU__ENTRY2__READ(src) \ + (((uint32_t)(src)\ + & 0x0003f000U) >> 12) +#define RIF_TXGAIN0_PMU__ENTRY2__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0003f000U) +#define RIF_TXGAIN0_PMU__ENTRY2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((uint32_t)(src) <<\ + 12) & 0x0003f000U) +#define RIF_TXGAIN0_PMU__ENTRY2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0003f000U))) +#define RIF_TXGAIN0_PMU__ENTRY2__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field entry3 */ +/** + * @defgroup rif_regs_core_entry3_field entry3_field + * @brief macros for field entry3 + * @details TX power level entry 3, -6dBm + * @{ + */ +#define RIF_TXGAIN0_PMU__ENTRY3__SHIFT 18 +#define RIF_TXGAIN0_PMU__ENTRY3__WIDTH 6 +#define RIF_TXGAIN0_PMU__ENTRY3__MASK 0x00fc0000U +#define RIF_TXGAIN0_PMU__ENTRY3__READ(src) \ + (((uint32_t)(src)\ + & 0x00fc0000U) >> 18) +#define RIF_TXGAIN0_PMU__ENTRY3__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00fc0000U) +#define RIF_TXGAIN0_PMU__ENTRY3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((uint32_t)(src) <<\ + 18) & 0x00fc0000U) +#define RIF_TXGAIN0_PMU__ENTRY3__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00fc0000U))) +#define RIF_TXGAIN0_PMU__ENTRY3__RESET_VALUE 0x00000013U +/** @} */ + +/* macros for field entry4 */ +/** + * @defgroup rif_regs_core_entry4_field entry4_field + * @brief macros for field entry4 + * @details TX power level entry 4, -4dBm + * @{ + */ +#define RIF_TXGAIN0_PMU__ENTRY4__SHIFT 24 +#define RIF_TXGAIN0_PMU__ENTRY4__WIDTH 6 +#define RIF_TXGAIN0_PMU__ENTRY4__MASK 0x3f000000U +#define RIF_TXGAIN0_PMU__ENTRY4__READ(src) \ + (((uint32_t)(src)\ + & 0x3f000000U) >> 24) +#define RIF_TXGAIN0_PMU__ENTRY4__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x3f000000U) +#define RIF_TXGAIN0_PMU__ENTRY4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((uint32_t)(src) <<\ + 24) & 0x3f000000U) +#define RIF_TXGAIN0_PMU__ENTRY4__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x3f000000U))) +#define RIF_TXGAIN0_PMU__ENTRY4__RESET_VALUE 0x00000017U +/** @} */ +#define RIF_TXGAIN0_PMU__TYPE uint32_t +#define RIF_TXGAIN0_PMU__READ 0x3fffffffU +#define RIF_TXGAIN0_PMU__WRITE 0x3fffffffU +#define RIF_TXGAIN0_PMU__PRESERVED 0x00000000U +#define RIF_TXGAIN0_PMU__RESET_VALUE 0x174d0300U + +#endif /* __RIF_TXGAIN0_PMU_MACRO__ */ + +/** @} end of txgain0_pmu */ + +/* macros for BlueprintGlobalNameSpace::RIF_txgain1_pmu */ +/** + * @defgroup rif_regs_core_txgain1_pmu txgain1_pmu + * @brief TX power table for pmu using VSTORE as PA supply, entries 5 to 9, paRef[5:0] definitions. + * @{ + */ +#ifndef __RIF_TXGAIN1_PMU_MACRO__ +#define __RIF_TXGAIN1_PMU_MACRO__ + +/* macros for field entry5 */ +/** + * @defgroup rif_regs_core_entry5_field entry5_field + * @brief macros for field entry5 + * @details TX power level entry 5, -2dBm + * @{ + */ +#define RIF_TXGAIN1_PMU__ENTRY5__SHIFT 0 +#define RIF_TXGAIN1_PMU__ENTRY5__WIDTH 6 +#define RIF_TXGAIN1_PMU__ENTRY5__MASK 0x0000003fU +#define RIF_TXGAIN1_PMU__ENTRY5__READ(src) ((uint32_t)(src) & 0x0000003fU) +#define RIF_TXGAIN1_PMU__ENTRY5__WRITE(src) ((uint32_t)(src) & 0x0000003fU) +#define RIF_TXGAIN1_PMU__ENTRY5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define RIF_TXGAIN1_PMU__ENTRY5__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define RIF_TXGAIN1_PMU__ENTRY5__RESET_VALUE 0x0000001bU +/** @} */ + +/* macros for field entry6 */ +/** + * @defgroup rif_regs_core_entry6_field entry6_field + * @brief macros for field entry6 + * @details TX power level entry 6, 0dBm + * @{ + */ +#define RIF_TXGAIN1_PMU__ENTRY6__SHIFT 6 +#define RIF_TXGAIN1_PMU__ENTRY6__WIDTH 6 +#define RIF_TXGAIN1_PMU__ENTRY6__MASK 0x00000fc0U +#define RIF_TXGAIN1_PMU__ENTRY6__READ(src) \ + (((uint32_t)(src)\ + & 0x00000fc0U) >> 6) +#define RIF_TXGAIN1_PMU__ENTRY6__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000fc0U) +#define RIF_TXGAIN1_PMU__ENTRY6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((uint32_t)(src) <<\ + 6) & 0x00000fc0U) +#define RIF_TXGAIN1_PMU__ENTRY6__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000fc0U))) +#define RIF_TXGAIN1_PMU__ENTRY6__RESET_VALUE 0x00000020U +/** @} */ + +/* macros for field entry7 */ +/** + * @defgroup rif_regs_core_entry7_field entry7_field + * @brief macros for field entry7 + * @details TX power level entry 7, 2dBm + * @{ + */ +#define RIF_TXGAIN1_PMU__ENTRY7__SHIFT 12 +#define RIF_TXGAIN1_PMU__ENTRY7__WIDTH 6 +#define RIF_TXGAIN1_PMU__ENTRY7__MASK 0x0003f000U +#define RIF_TXGAIN1_PMU__ENTRY7__READ(src) \ + (((uint32_t)(src)\ + & 0x0003f000U) >> 12) +#define RIF_TXGAIN1_PMU__ENTRY7__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0003f000U) +#define RIF_TXGAIN1_PMU__ENTRY7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((uint32_t)(src) <<\ + 12) & 0x0003f000U) +#define RIF_TXGAIN1_PMU__ENTRY7__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0003f000U))) +#define RIF_TXGAIN1_PMU__ENTRY7__RESET_VALUE 0x00000024U +/** @} */ + +/* macros for field entry8 */ +/** + * @defgroup rif_regs_core_entry8_field entry8_field + * @brief macros for field entry8 + * @details TX power level entry 8, 4dBm + * @{ + */ +#define RIF_TXGAIN1_PMU__ENTRY8__SHIFT 18 +#define RIF_TXGAIN1_PMU__ENTRY8__WIDTH 6 +#define RIF_TXGAIN1_PMU__ENTRY8__MASK 0x00fc0000U +#define RIF_TXGAIN1_PMU__ENTRY8__READ(src) \ + (((uint32_t)(src)\ + & 0x00fc0000U) >> 18) +#define RIF_TXGAIN1_PMU__ENTRY8__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00fc0000U) +#define RIF_TXGAIN1_PMU__ENTRY8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((uint32_t)(src) <<\ + 18) & 0x00fc0000U) +#define RIF_TXGAIN1_PMU__ENTRY8__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00fc0000U))) +#define RIF_TXGAIN1_PMU__ENTRY8__RESET_VALUE 0x0000002aU +/** @} */ + +/* macros for field entry9 */ +/** + * @defgroup rif_regs_core_entry9_field entry9_field + * @brief macros for field entry9 + * @details TX power level entry 9, 6dBm + * @{ + */ +#define RIF_TXGAIN1_PMU__ENTRY9__SHIFT 24 +#define RIF_TXGAIN1_PMU__ENTRY9__WIDTH 6 +#define RIF_TXGAIN1_PMU__ENTRY9__MASK 0x3f000000U +#define RIF_TXGAIN1_PMU__ENTRY9__READ(src) \ + (((uint32_t)(src)\ + & 0x3f000000U) >> 24) +#define RIF_TXGAIN1_PMU__ENTRY9__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x3f000000U) +#define RIF_TXGAIN1_PMU__ENTRY9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((uint32_t)(src) <<\ + 24) & 0x3f000000U) +#define RIF_TXGAIN1_PMU__ENTRY9__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x3f000000U))) +#define RIF_TXGAIN1_PMU__ENTRY9__RESET_VALUE 0x00000030U +/** @} */ +#define RIF_TXGAIN1_PMU__TYPE uint32_t +#define RIF_TXGAIN1_PMU__READ 0x3fffffffU +#define RIF_TXGAIN1_PMU__WRITE 0x3fffffffU +#define RIF_TXGAIN1_PMU__PRESERVED 0x00000000U +#define RIF_TXGAIN1_PMU__RESET_VALUE 0x30aa481bU + +#endif /* __RIF_TXGAIN1_PMU_MACRO__ */ + +/** @} end of txgain1_pmu */ + +/* macros for BlueprintGlobalNameSpace::RIF_txgain2_pmu */ +/** + * @defgroup rif_regs_core_txgain2_pmu txgain2_pmu + * @brief TX power table for pmu using VSTORE as PA supply, entries 10 to 11, paRef[5:0] definitions. + * @{ + */ +#ifndef __RIF_TXGAIN2_PMU_MACRO__ +#define __RIF_TXGAIN2_PMU_MACRO__ + +/* macros for field entry10 */ +/** + * @defgroup rif_regs_core_entry10_field entry10_field + * @brief macros for field entry10 + * @details TX power level entry 10, 8dBm + * @{ + */ +#define RIF_TXGAIN2_PMU__ENTRY10__SHIFT 0 +#define RIF_TXGAIN2_PMU__ENTRY10__WIDTH 6 +#define RIF_TXGAIN2_PMU__ENTRY10__MASK 0x0000003fU +#define RIF_TXGAIN2_PMU__ENTRY10__READ(src) ((uint32_t)(src) & 0x0000003fU) +#define RIF_TXGAIN2_PMU__ENTRY10__WRITE(src) ((uint32_t)(src) & 0x0000003fU) +#define RIF_TXGAIN2_PMU__ENTRY10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define RIF_TXGAIN2_PMU__ENTRY10__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define RIF_TXGAIN2_PMU__ENTRY10__RESET_VALUE 0x00000037U +/** @} */ + +/* macros for field entry11 */ +/** + * @defgroup rif_regs_core_entry11_field entry11_field + * @brief macros for field entry11 + * @details TX power level entry 11, extra + * @{ + */ +#define RIF_TXGAIN2_PMU__ENTRY11__SHIFT 6 +#define RIF_TXGAIN2_PMU__ENTRY11__WIDTH 6 +#define RIF_TXGAIN2_PMU__ENTRY11__MASK 0x00000fc0U +#define RIF_TXGAIN2_PMU__ENTRY11__READ(src) \ + (((uint32_t)(src)\ + & 0x00000fc0U) >> 6) +#define RIF_TXGAIN2_PMU__ENTRY11__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000fc0U) +#define RIF_TXGAIN2_PMU__ENTRY11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((uint32_t)(src) <<\ + 6) & 0x00000fc0U) +#define RIF_TXGAIN2_PMU__ENTRY11__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000fc0U))) +#define RIF_TXGAIN2_PMU__ENTRY11__RESET_VALUE 0x0000003fU +/** @} */ + +/* macros for field paRefLoDvdd */ +/** + * @defgroup rif_regs_core_paRefLoDvdd_field paRefLoDvdd_field + * @brief macros for field paRefLoDvdd + * @details Reference level from AVDD or DVDD + * @{ + */ +#define RIF_TXGAIN2_PMU__PAREFLODVDD__SHIFT 18 +#define RIF_TXGAIN2_PMU__PAREFLODVDD__WIDTH 1 +#define RIF_TXGAIN2_PMU__PAREFLODVDD__MASK 0x00040000U +#define RIF_TXGAIN2_PMU__PAREFLODVDD__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define RIF_TXGAIN2_PMU__PAREFLODVDD__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define RIF_TXGAIN2_PMU__PAREFLODVDD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define RIF_TXGAIN2_PMU__PAREFLODVDD__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define RIF_TXGAIN2_PMU__PAREFLODVDD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define RIF_TXGAIN2_PMU__PAREFLODVDD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define RIF_TXGAIN2_PMU__PAREFLODVDD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field paRefHi */ +/** + * @defgroup rif_regs_core_paRefHi_field paRefHi_field + * @brief macros for field paRefHi + * @details Reference level from VDDIO + * @{ + */ +#define RIF_TXGAIN2_PMU__PAREFHI__SHIFT 19 +#define RIF_TXGAIN2_PMU__PAREFHI__WIDTH 1 +#define RIF_TXGAIN2_PMU__PAREFHI__MASK 0x00080000U +#define RIF_TXGAIN2_PMU__PAREFHI__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define RIF_TXGAIN2_PMU__PAREFHI__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define RIF_TXGAIN2_PMU__PAREFHI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define RIF_TXGAIN2_PMU__PAREFHI__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define RIF_TXGAIN2_PMU__PAREFHI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define RIF_TXGAIN2_PMU__PAREFHI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define RIF_TXGAIN2_PMU__PAREFHI__RESET_VALUE 0x00000001U +/** @} */ +#define RIF_TXGAIN2_PMU__TYPE uint32_t +#define RIF_TXGAIN2_PMU__READ 0x000c0fffU +#define RIF_TXGAIN2_PMU__WRITE 0x000c0fffU +#define RIF_TXGAIN2_PMU__PRESERVED 0x00000000U +#define RIF_TXGAIN2_PMU__RESET_VALUE 0x00080ff7U + +#endif /* __RIF_TXGAIN2_PMU_MACRO__ */ + +/** @} end of txgain2_pmu */ + +/* macros for BlueprintGlobalNameSpace::RIF_rx0 */ +/** + * @defgroup rif_regs_core_rx0 rx0 + * @brief Contains register fields associated with rx0. definitions. + * @{ + */ +#ifndef __RIF_RX0_MACRO__ +#define __RIF_RX0_MACRO__ + +/* macros for field lna_bias */ +/** + * @defgroup rif_regs_core_lna_bias_field lna_bias_field + * @brief macros for field lna_bias + * @details LNA bias current + * @{ + */ +#define RIF_RX0__LNA_BIAS__SHIFT 0 +#define RIF_RX0__LNA_BIAS__WIDTH 5 +#define RIF_RX0__LNA_BIAS__MASK 0x0000001fU +#define RIF_RX0__LNA_BIAS__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define RIF_RX0__LNA_BIAS__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define RIF_RX0__LNA_BIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define RIF_RX0__LNA_BIAS__VERIFY(src) (!(((uint32_t)(src) & ~0x0000001fU))) +#define RIF_RX0__LNA_BIAS__RESET_VALUE 0x0000000fU +/** @} */ + +/* macros for field lnapd_gain */ +/** + * @defgroup rif_regs_core_lnapd_gain_field lnapd_gain_field + * @brief macros for field lnapd_gain + * @details LNA peak detector gain + * @{ + */ +#define RIF_RX0__LNAPD_GAIN__SHIFT 5 +#define RIF_RX0__LNAPD_GAIN__WIDTH 2 +#define RIF_RX0__LNAPD_GAIN__MASK 0x00000060U +#define RIF_RX0__LNAPD_GAIN__READ(src) (((uint32_t)(src) & 0x00000060U) >> 5) +#define RIF_RX0__LNAPD_GAIN__WRITE(src) (((uint32_t)(src) << 5) & 0x00000060U) +#define RIF_RX0__LNAPD_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000060U) | (((uint32_t)(src) <<\ + 5) & 0x00000060U) +#define RIF_RX0__LNAPD_GAIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000060U))) +#define RIF_RX0__LNAPD_GAIN__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field lnapd_reflvl */ +/** + * @defgroup rif_regs_core_lnapd_reflvl_field lnapd_reflvl_field + * @brief macros for field lnapd_reflvl + * @details LNA peak detector reference level + * @{ + */ +#define RIF_RX0__LNAPD_REFLVL__SHIFT 7 +#define RIF_RX0__LNAPD_REFLVL__WIDTH 4 +#define RIF_RX0__LNAPD_REFLVL__MASK 0x00000780U +#define RIF_RX0__LNAPD_REFLVL__READ(src) (((uint32_t)(src) & 0x00000780U) >> 7) +#define RIF_RX0__LNAPD_REFLVL__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000780U) +#define RIF_RX0__LNAPD_REFLVL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000780U) | (((uint32_t)(src) <<\ + 7) & 0x00000780U) +#define RIF_RX0__LNAPD_REFLVL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000780U))) +#define RIF_RX0__LNAPD_REFLVL__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field lna_off_attn_in */ +/** + * @defgroup rif_regs_core_lna_off_attn_in_field lna_off_attn_in_field + * @brief macros for field lna_off_attn_in + * @details LNA off input attenuation setting + * @{ + */ +#define RIF_RX0__LNA_OFF_ATTN_IN__SHIFT 11 +#define RIF_RX0__LNA_OFF_ATTN_IN__WIDTH 2 +#define RIF_RX0__LNA_OFF_ATTN_IN__MASK 0x00001800U +#define RIF_RX0__LNA_OFF_ATTN_IN__READ(src) \ + (((uint32_t)(src)\ + & 0x00001800U) >> 11) +#define RIF_RX0__LNA_OFF_ATTN_IN__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00001800U) +#define RIF_RX0__LNA_OFF_ATTN_IN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001800U) | (((uint32_t)(src) <<\ + 11) & 0x00001800U) +#define RIF_RX0__LNA_OFF_ATTN_IN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00001800U))) +#define RIF_RX0__LNA_OFF_ATTN_IN__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field lna_off_attn_out */ +/** + * @defgroup rif_regs_core_lna_off_attn_out_field lna_off_attn_out_field + * @brief macros for field lna_off_attn_out + * @details LNA off output attenuation setting + * @{ + */ +#define RIF_RX0__LNA_OFF_ATTN_OUT__SHIFT 13 +#define RIF_RX0__LNA_OFF_ATTN_OUT__WIDTH 1 +#define RIF_RX0__LNA_OFF_ATTN_OUT__MASK 0x00002000U +#define RIF_RX0__LNA_OFF_ATTN_OUT__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define RIF_RX0__LNA_OFF_ATTN_OUT__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define RIF_RX0__LNA_OFF_ATTN_OUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define RIF_RX0__LNA_OFF_ATTN_OUT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define RIF_RX0__LNA_OFF_ATTN_OUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define RIF_RX0__LNA_OFF_ATTN_OUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define RIF_RX0__LNA_OFF_ATTN_OUT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field lna_on_attn_in */ +/** + * @defgroup rif_regs_core_lna_on_attn_in_field lna_on_attn_in_field + * @brief macros for field lna_on_attn_in + * @details LNA on min gain input attenuation setting + * @{ + */ +#define RIF_RX0__LNA_ON_ATTN_IN__SHIFT 14 +#define RIF_RX0__LNA_ON_ATTN_IN__WIDTH 2 +#define RIF_RX0__LNA_ON_ATTN_IN__MASK 0x0000c000U +#define RIF_RX0__LNA_ON_ATTN_IN__READ(src) \ + (((uint32_t)(src)\ + & 0x0000c000U) >> 14) +#define RIF_RX0__LNA_ON_ATTN_IN__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0000c000U) +#define RIF_RX0__LNA_ON_ATTN_IN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000c000U) | (((uint32_t)(src) <<\ + 14) & 0x0000c000U) +#define RIF_RX0__LNA_ON_ATTN_IN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0000c000U))) +#define RIF_RX0__LNA_ON_ATTN_IN__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field sel_icpga */ +/** + * @defgroup rif_regs_core_sel_icpga_field sel_icpga_field + * @brief macros for field sel_icpga + * @details PGA bias current + * @{ + */ +#define RIF_RX0__SEL_ICPGA__SHIFT 16 +#define RIF_RX0__SEL_ICPGA__WIDTH 4 +#define RIF_RX0__SEL_ICPGA__MASK 0x000f0000U +#define RIF_RX0__SEL_ICPGA__READ(src) (((uint32_t)(src) & 0x000f0000U) >> 16) +#define RIF_RX0__SEL_ICPGA__WRITE(src) (((uint32_t)(src) << 16) & 0x000f0000U) +#define RIF_RX0__SEL_ICPGA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((uint32_t)(src) <<\ + 16) & 0x000f0000U) +#define RIF_RX0__SEL_ICPGA__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x000f0000U))) +#define RIF_RX0__SEL_ICPGA__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field vcm_ctrl */ +/** + * @defgroup rif_regs_core_vcm_ctrl_field vcm_ctrl_field + * @brief macros for field vcm_ctrl + * @details Adjusts the common-mode reference voltage to TIA and PGA op-amps, 0=510mV, 1=550mV, 2=590mV, 3=630mV, 4=650mV, 5=670mV, 6=690mV, 7=710mV + * @{ + */ +#define RIF_RX0__VCM_CTRL__SHIFT 20 +#define RIF_RX0__VCM_CTRL__WIDTH 3 +#define RIF_RX0__VCM_CTRL__MASK 0x00700000U +#define RIF_RX0__VCM_CTRL__READ(src) (((uint32_t)(src) & 0x00700000U) >> 20) +#define RIF_RX0__VCM_CTRL__WRITE(src) (((uint32_t)(src) << 20) & 0x00700000U) +#define RIF_RX0__VCM_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((uint32_t)(src) <<\ + 20) & 0x00700000U) +#define RIF_RX0__VCM_CTRL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00700000U))) +#define RIF_RX0__VCM_CTRL__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field bb1_dcoc_extra_en */ +/** + * @defgroup rif_regs_core_bb1_dcoc_extra_en_field bb1_dcoc_extra_en_field + * @brief macros for field bb1_dcoc_extra_en + * @details Enable extra TIA DC offset DAC MSBs, [0] = enable bit 6, [1] = enable bit 7 + * @{ + */ +#define RIF_RX0__BB1_DCOC_EXTRA_EN__SHIFT 23 +#define RIF_RX0__BB1_DCOC_EXTRA_EN__WIDTH 2 +#define RIF_RX0__BB1_DCOC_EXTRA_EN__MASK 0x01800000U +#define RIF_RX0__BB1_DCOC_EXTRA_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x01800000U) >> 23) +#define RIF_RX0__BB1_DCOC_EXTRA_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x01800000U) +#define RIF_RX0__BB1_DCOC_EXTRA_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01800000U) | (((uint32_t)(src) <<\ + 23) & 0x01800000U) +#define RIF_RX0__BB1_DCOC_EXTRA_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x01800000U))) +#define RIF_RX0__BB1_DCOC_EXTRA_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hadm_lp */ +/** + * @defgroup rif_regs_core_hadm_lp_field hadm_lp_field + * @brief macros for field hadm_lp + * @details Selects RXLO mode for HADM, 0=PMODE_SINGLE, 1=PMODE_LP_SINGLE + * @{ + */ +#define RIF_RX0__HADM_LP__SHIFT 25 +#define RIF_RX0__HADM_LP__WIDTH 1 +#define RIF_RX0__HADM_LP__MASK 0x02000000U +#define RIF_RX0__HADM_LP__READ(src) (((uint32_t)(src) & 0x02000000U) >> 25) +#define RIF_RX0__HADM_LP__WRITE(src) (((uint32_t)(src) << 25) & 0x02000000U) +#define RIF_RX0__HADM_LP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define RIF_RX0__HADM_LP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define RIF_RX0__HADM_LP__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define RIF_RX0__HADM_LP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define RIF_RX0__HADM_LP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_sparebits */ +/** + * @defgroup rif_regs_core_rx_sparebits_field rx_sparebits_field + * @brief macros for field rx_sparebits + * @details spare bits + * @{ + */ +#define RIF_RX0__RX_SPAREBITS__SHIFT 26 +#define RIF_RX0__RX_SPAREBITS__WIDTH 4 +#define RIF_RX0__RX_SPAREBITS__MASK 0x3c000000U +#define RIF_RX0__RX_SPAREBITS__READ(src) \ + (((uint32_t)(src)\ + & 0x3c000000U) >> 26) +#define RIF_RX0__RX_SPAREBITS__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x3c000000U) +#define RIF_RX0__RX_SPAREBITS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3c000000U) | (((uint32_t)(src) <<\ + 26) & 0x3c000000U) +#define RIF_RX0__RX_SPAREBITS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x3c000000U))) +#define RIF_RX0__RX_SPAREBITS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field lna_protect_ovr */ +/** + * @defgroup rif_regs_core_lna_protect_ovr_field lna_protect_ovr_field + * @brief macros for field lna_protect_ovr + * @details Force override of lna_protect signal, MSB is override control, LSB is override value + * @{ + */ +#define RIF_RX0__LNA_PROTECT_OVR__SHIFT 30 +#define RIF_RX0__LNA_PROTECT_OVR__WIDTH 2 +#define RIF_RX0__LNA_PROTECT_OVR__MASK 0xc0000000U +#define RIF_RX0__LNA_PROTECT_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define RIF_RX0__LNA_PROTECT_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define RIF_RX0__LNA_PROTECT_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define RIF_RX0__LNA_PROTECT_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define RIF_RX0__LNA_PROTECT_OVR__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_RX0__TYPE uint32_t +#define RIF_RX0__READ 0xffffffffU +#define RIF_RX0__WRITE 0xffffffffU +#define RIF_RX0__PRESERVED 0x00000000U +#define RIF_RX0__RESET_VALUE 0x0043d44fU + +#endif /* __RIF_RX0_MACRO__ */ + +/** @} end of rx0 */ + +/* macros for BlueprintGlobalNameSpace::RIF_timer0 */ +/** + * @defgroup rif_regs_core_timer0 timer0 + * @brief All timers in units of 8 MHz clocks definitions. + * @{ + */ +#ifndef __RIF_TIMER0_MACRO__ +#define __RIF_TIMER0_MACRO__ + +/* macros for field synthon_time */ +/** + * @defgroup rif_regs_core_synthon_time_field synthon_time_field + * @brief macros for field synthon_time + * @details Triggered by rising tx_en or rx_en + * @{ + */ +#define RIF_TIMER0__SYNTHON_TIME__SHIFT 0 +#define RIF_TIMER0__SYNTHON_TIME__WIDTH 10 +#define RIF_TIMER0__SYNTHON_TIME__MASK 0x000003ffU +#define RIF_TIMER0__SYNTHON_TIME__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_TIMER0__SYNTHON_TIME__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_TIMER0__SYNTHON_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_TIMER0__SYNTHON_TIME__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define RIF_TIMER0__SYNTHON_TIME__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field synthoff_time */ +/** + * @defgroup rif_regs_core_synthoff_time_field synthoff_time_field + * @brief macros for field synthoff_time + * @details Triggered by falling tx_en or rx_en + * @{ + */ +#define RIF_TIMER0__SYNTHOFF_TIME__SHIFT 10 +#define RIF_TIMER0__SYNTHOFF_TIME__WIDTH 6 +#define RIF_TIMER0__SYNTHOFF_TIME__MASK 0x0000fc00U +#define RIF_TIMER0__SYNTHOFF_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0x0000fc00U) >> 10) +#define RIF_TIMER0__SYNTHOFF_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x0000fc00U) +#define RIF_TIMER0__SYNTHOFF_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fc00U) | (((uint32_t)(src) <<\ + 10) & 0x0000fc00U) +#define RIF_TIMER0__SYNTHOFF_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x0000fc00U))) +#define RIF_TIMER0__SYNTHOFF_TIME__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field txon_time */ +/** + * @defgroup rif_regs_core_txon_time_field txon_time_field + * @brief macros for field txon_time + * @details Triggered by rising tx_en + * @{ + */ +#define RIF_TIMER0__TXON_TIME__SHIFT 16 +#define RIF_TIMER0__TXON_TIME__WIDTH 10 +#define RIF_TIMER0__TXON_TIME__MASK 0x03ff0000U +#define RIF_TIMER0__TXON_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0x03ff0000U) >> 16) +#define RIF_TIMER0__TXON_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x03ff0000U) +#define RIF_TIMER0__TXON_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x03ff0000U) +#define RIF_TIMER0__TXON_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x03ff0000U))) +#define RIF_TIMER0__TXON_TIME__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field txoff_time */ +/** + * @defgroup rif_regs_core_txoff_time_field txoff_time_field + * @brief macros for field txoff_time + * @details Triggered by falling tx_en + * @{ + */ +#define RIF_TIMER0__TXOFF_TIME__SHIFT 26 +#define RIF_TIMER0__TXOFF_TIME__WIDTH 6 +#define RIF_TIMER0__TXOFF_TIME__MASK 0xfc000000U +#define RIF_TIMER0__TXOFF_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0xfc000000U) >> 26) +#define RIF_TIMER0__TXOFF_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0xfc000000U) +#define RIF_TIMER0__TXOFF_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfc000000U) | (((uint32_t)(src) <<\ + 26) & 0xfc000000U) +#define RIF_TIMER0__TXOFF_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0xfc000000U))) +#define RIF_TIMER0__TXOFF_TIME__RESET_VALUE 0x00000002U +/** @} */ +#define RIF_TIMER0__TYPE uint32_t +#define RIF_TIMER0__READ 0xffffffffU +#define RIF_TIMER0__WRITE 0xffffffffU +#define RIF_TIMER0__PRESERVED 0x00000000U +#define RIF_TIMER0__RESET_VALUE 0x08000401U + +#endif /* __RIF_TIMER0_MACRO__ */ + +/** @} end of timer0 */ + +/* macros for BlueprintGlobalNameSpace::RIF_timer1 */ +/** + * @defgroup rif_regs_core_timer1 timer1 + * @brief All timers in units of 8 MHz clocks definitions. + * @{ + */ +#ifndef __RIF_TIMER1_MACRO__ +#define __RIF_TIMER1_MACRO__ + +/* macros for field paon_time */ +/** + * @defgroup rif_regs_core_paon_time_field paon_time_field + * @brief macros for field paon_time + * @details Triggered by rising tx_en + * @{ + */ +#define RIF_TIMER1__PAON_TIME__SHIFT 0 +#define RIF_TIMER1__PAON_TIME__WIDTH 10 +#define RIF_TIMER1__PAON_TIME__MASK 0x000003ffU +#define RIF_TIMER1__PAON_TIME__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_TIMER1__PAON_TIME__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_TIMER1__PAON_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_TIMER1__PAON_TIME__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define RIF_TIMER1__PAON_TIME__RESET_VALUE 0x00000168U +/** @} */ + +/* macros for field paoff_time */ +/** + * @defgroup rif_regs_core_paoff_time_field paoff_time_field + * @brief macros for field paoff_time + * @details Triggered by falling tx_en + * @{ + */ +#define RIF_TIMER1__PAOFF_TIME__SHIFT 10 +#define RIF_TIMER1__PAOFF_TIME__WIDTH 6 +#define RIF_TIMER1__PAOFF_TIME__MASK 0x0000fc00U +#define RIF_TIMER1__PAOFF_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0x0000fc00U) >> 10) +#define RIF_TIMER1__PAOFF_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x0000fc00U) +#define RIF_TIMER1__PAOFF_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fc00U) | (((uint32_t)(src) <<\ + 10) & 0x0000fc00U) +#define RIF_TIMER1__PAOFF_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x0000fc00U))) +#define RIF_TIMER1__PAOFF_TIME__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rxon_time */ +/** + * @defgroup rif_regs_core_rxon_time_field rxon_time_field + * @brief macros for field rxon_time + * @details Triggered by rising rx_en + * @{ + */ +#define RIF_TIMER1__RXON_TIME__SHIFT 16 +#define RIF_TIMER1__RXON_TIME__WIDTH 10 +#define RIF_TIMER1__RXON_TIME__MASK 0x03ff0000U +#define RIF_TIMER1__RXON_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0x03ff0000U) >> 16) +#define RIF_TIMER1__RXON_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x03ff0000U) +#define RIF_TIMER1__RXON_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x03ff0000U) +#define RIF_TIMER1__RXON_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x03ff0000U))) +#define RIF_TIMER1__RXON_TIME__RESET_VALUE 0x00000190U +/** @} */ + +/* macros for field rxoff_time */ +/** + * @defgroup rif_regs_core_rxoff_time_field rxoff_time_field + * @brief macros for field rxoff_time + * @details Triggered by falling rx_en + * @{ + */ +#define RIF_TIMER1__RXOFF_TIME__SHIFT 26 +#define RIF_TIMER1__RXOFF_TIME__WIDTH 6 +#define RIF_TIMER1__RXOFF_TIME__MASK 0xfc000000U +#define RIF_TIMER1__RXOFF_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0xfc000000U) >> 26) +#define RIF_TIMER1__RXOFF_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0xfc000000U) +#define RIF_TIMER1__RXOFF_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfc000000U) | (((uint32_t)(src) <<\ + 26) & 0xfc000000U) +#define RIF_TIMER1__RXOFF_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0xfc000000U))) +#define RIF_TIMER1__RXOFF_TIME__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_TIMER1__TYPE uint32_t +#define RIF_TIMER1__READ 0xffffffffU +#define RIF_TIMER1__WRITE 0xffffffffU +#define RIF_TIMER1__PRESERVED 0x00000000U +#define RIF_TIMER1__RESET_VALUE 0x01900168U + +#endif /* __RIF_TIMER1_MACRO__ */ + +/** @} end of timer1 */ + +/* macros for BlueprintGlobalNameSpace::RIF_timer2 */ +/** + * @defgroup rif_regs_core_timer2 timer2 + * @brief All timers in units of 8 MHz clocks definitions. + * @{ + */ +#ifndef __RIF_TIMER2_MACRO__ +#define __RIF_TIMER2_MACRO__ + +/* macros for field adcon_time */ +/** + * @defgroup rif_regs_core_adcon_time_field adcon_time_field + * @brief macros for field adcon_time + * @details Triggered by rising rx_en + * @{ + */ +#define RIF_TIMER2__ADCON_TIME__SHIFT 0 +#define RIF_TIMER2__ADCON_TIME__WIDTH 10 +#define RIF_TIMER2__ADCON_TIME__MASK 0x000003ffU +#define RIF_TIMER2__ADCON_TIME__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_TIMER2__ADCON_TIME__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_TIMER2__ADCON_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_TIMER2__ADCON_TIME__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define RIF_TIMER2__ADCON_TIME__RESET_VALUE 0x0000017cU +/** @} */ + +/* macros for field adcoff_time */ +/** + * @defgroup rif_regs_core_adcoff_time_field adcoff_time_field + * @brief macros for field adcoff_time + * @details Triggered by falling rx_en + * @{ + */ +#define RIF_TIMER2__ADCOFF_TIME__SHIFT 10 +#define RIF_TIMER2__ADCOFF_TIME__WIDTH 6 +#define RIF_TIMER2__ADCOFF_TIME__MASK 0x0000fc00U +#define RIF_TIMER2__ADCOFF_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0x0000fc00U) >> 10) +#define RIF_TIMER2__ADCOFF_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x0000fc00U) +#define RIF_TIMER2__ADCOFF_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fc00U) | (((uint32_t)(src) <<\ + 10) & 0x0000fc00U) +#define RIF_TIMER2__ADCOFF_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x0000fc00U))) +#define RIF_TIMER2__ADCOFF_TIME__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adcearlyon_time */ +/** + * @defgroup rif_regs_core_adcearlyon_time_field adcearlyon_time_field + * @brief macros for field adcearlyon_time + * @details Triggered by rising rx_en + * @{ + */ +#define RIF_TIMER2__ADCEARLYON_TIME__SHIFT 16 +#define RIF_TIMER2__ADCEARLYON_TIME__WIDTH 10 +#define RIF_TIMER2__ADCEARLYON_TIME__MASK 0x03ff0000U +#define RIF_TIMER2__ADCEARLYON_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0x03ff0000U) >> 16) +#define RIF_TIMER2__ADCEARLYON_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x03ff0000U) +#define RIF_TIMER2__ADCEARLYON_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x03ff0000U) +#define RIF_TIMER2__ADCEARLYON_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x03ff0000U))) +#define RIF_TIMER2__ADCEARLYON_TIME__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adcearlyoff_time */ +/** + * @defgroup rif_regs_core_adcearlyoff_time_field adcearlyoff_time_field + * @brief macros for field adcearlyoff_time + * @details Triggered by falling rx_en + * @{ + */ +#define RIF_TIMER2__ADCEARLYOFF_TIME__SHIFT 26 +#define RIF_TIMER2__ADCEARLYOFF_TIME__WIDTH 6 +#define RIF_TIMER2__ADCEARLYOFF_TIME__MASK 0xfc000000U +#define RIF_TIMER2__ADCEARLYOFF_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0xfc000000U) >> 26) +#define RIF_TIMER2__ADCEARLYOFF_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0xfc000000U) +#define RIF_TIMER2__ADCEARLYOFF_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfc000000U) | (((uint32_t)(src) <<\ + 26) & 0xfc000000U) +#define RIF_TIMER2__ADCEARLYOFF_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0xfc000000U))) +#define RIF_TIMER2__ADCEARLYOFF_TIME__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_TIMER2__TYPE uint32_t +#define RIF_TIMER2__READ 0xffffffffU +#define RIF_TIMER2__WRITE 0xffffffffU +#define RIF_TIMER2__PRESERVED 0x00000000U +#define RIF_TIMER2__RESET_VALUE 0x0000017cU + +#endif /* __RIF_TIMER2_MACRO__ */ + +/** @} end of timer2 */ + +/* macros for BlueprintGlobalNameSpace::RIF_timer3 */ +/** + * @defgroup rif_regs_core_timer3 timer3 + * @brief All timers in units of 8 MHz clocks definitions. + * @{ + */ +#ifndef __RIF_TIMER3_MACRO__ +#define __RIF_TIMER3_MACRO__ + +/* macros for field xpaon_time */ +/** + * @defgroup rif_regs_core_xpaon_time_field xpaon_time_field + * @brief macros for field xpaon_time + * @details Triggered by rising tx_en + * @{ + */ +#define RIF_TIMER3__XPAON_TIME__SHIFT 0 +#define RIF_TIMER3__XPAON_TIME__WIDTH 10 +#define RIF_TIMER3__XPAON_TIME__MASK 0x000003ffU +#define RIF_TIMER3__XPAON_TIME__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_TIMER3__XPAON_TIME__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_TIMER3__XPAON_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_TIMER3__XPAON_TIME__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define RIF_TIMER3__XPAON_TIME__RESET_VALUE 0x00000168U +/** @} */ + +/* macros for field xpaoff_time */ +/** + * @defgroup rif_regs_core_xpaoff_time_field xpaoff_time_field + * @brief macros for field xpaoff_time + * @details Triggered by falling tx_en + * @{ + */ +#define RIF_TIMER3__XPAOFF_TIME__SHIFT 10 +#define RIF_TIMER3__XPAOFF_TIME__WIDTH 6 +#define RIF_TIMER3__XPAOFF_TIME__MASK 0x0000fc00U +#define RIF_TIMER3__XPAOFF_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0x0000fc00U) >> 10) +#define RIF_TIMER3__XPAOFF_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x0000fc00U) +#define RIF_TIMER3__XPAOFF_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fc00U) | (((uint32_t)(src) <<\ + 10) & 0x0000fc00U) +#define RIF_TIMER3__XPAOFF_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x0000fc00U))) +#define RIF_TIMER3__XPAOFF_TIME__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field xlnaon_time */ +/** + * @defgroup rif_regs_core_xlnaon_time_field xlnaon_time_field + * @brief macros for field xlnaon_time + * @details Triggered by rising rx_en + * @{ + */ +#define RIF_TIMER3__XLNAON_TIME__SHIFT 16 +#define RIF_TIMER3__XLNAON_TIME__WIDTH 10 +#define RIF_TIMER3__XLNAON_TIME__MASK 0x03ff0000U +#define RIF_TIMER3__XLNAON_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0x03ff0000U) >> 16) +#define RIF_TIMER3__XLNAON_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x03ff0000U) +#define RIF_TIMER3__XLNAON_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x03ff0000U) +#define RIF_TIMER3__XLNAON_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x03ff0000U))) +#define RIF_TIMER3__XLNAON_TIME__RESET_VALUE 0x00000190U +/** @} */ + +/* macros for field xlnaoff_time */ +/** + * @defgroup rif_regs_core_xlnaoff_time_field xlnaoff_time_field + * @brief macros for field xlnaoff_time + * @details Triggered by falling rx_en + * @{ + */ +#define RIF_TIMER3__XLNAOFF_TIME__SHIFT 26 +#define RIF_TIMER3__XLNAOFF_TIME__WIDTH 6 +#define RIF_TIMER3__XLNAOFF_TIME__MASK 0xfc000000U +#define RIF_TIMER3__XLNAOFF_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0xfc000000U) >> 26) +#define RIF_TIMER3__XLNAOFF_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0xfc000000U) +#define RIF_TIMER3__XLNAOFF_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfc000000U) | (((uint32_t)(src) <<\ + 26) & 0xfc000000U) +#define RIF_TIMER3__XLNAOFF_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0xfc000000U))) +#define RIF_TIMER3__XLNAOFF_TIME__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_TIMER3__TYPE uint32_t +#define RIF_TIMER3__READ 0xffffffffU +#define RIF_TIMER3__WRITE 0xffffffffU +#define RIF_TIMER3__PRESERVED 0x00000000U +#define RIF_TIMER3__RESET_VALUE 0x01900168U + +#endif /* __RIF_TIMER3_MACRO__ */ + +/** @} end of timer3 */ + +/* macros for BlueprintGlobalNameSpace::RIF_hadm_timer0 */ +/** + * @defgroup rif_regs_core_hadm_timer0 hadm_timer0 + * @brief All timers in units of 8 MHz clocks definitions. + * @{ + */ +#ifndef __RIF_HADM_TIMER0_MACRO__ +#define __RIF_HADM_TIMER0_MACRO__ + +/* macros for field synthon_time */ +/** + * @defgroup rif_regs_core_synthon_time_field synthon_time_field + * @brief macros for field synthon_time + * @details Triggered by rising tx_en or rx_en + * @{ + */ +#define RIF_HADM_TIMER0__SYNTHON_TIME__SHIFT 0 +#define RIF_HADM_TIMER0__SYNTHON_TIME__WIDTH 10 +#define RIF_HADM_TIMER0__SYNTHON_TIME__MASK 0x000003ffU +#define RIF_HADM_TIMER0__SYNTHON_TIME__READ(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define RIF_HADM_TIMER0__SYNTHON_TIME__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000003ffU) +#define RIF_HADM_TIMER0__SYNTHON_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_HADM_TIMER0__SYNTHON_TIME__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define RIF_HADM_TIMER0__SYNTHON_TIME__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field synthoff_time */ +/** + * @defgroup rif_regs_core_synthoff_time_field synthoff_time_field + * @brief macros for field synthoff_time + * @details Triggered by falling tx_en or rx_en + * @{ + */ +#define RIF_HADM_TIMER0__SYNTHOFF_TIME__SHIFT 10 +#define RIF_HADM_TIMER0__SYNTHOFF_TIME__WIDTH 6 +#define RIF_HADM_TIMER0__SYNTHOFF_TIME__MASK 0x0000fc00U +#define RIF_HADM_TIMER0__SYNTHOFF_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0x0000fc00U) >> 10) +#define RIF_HADM_TIMER0__SYNTHOFF_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x0000fc00U) +#define RIF_HADM_TIMER0__SYNTHOFF_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fc00U) | (((uint32_t)(src) <<\ + 10) & 0x0000fc00U) +#define RIF_HADM_TIMER0__SYNTHOFF_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x0000fc00U))) +#define RIF_HADM_TIMER0__SYNTHOFF_TIME__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field txon_time */ +/** + * @defgroup rif_regs_core_txon_time_field txon_time_field + * @brief macros for field txon_time + * @details Triggered by rising tx_en + * @{ + */ +#define RIF_HADM_TIMER0__TXON_TIME__SHIFT 16 +#define RIF_HADM_TIMER0__TXON_TIME__WIDTH 10 +#define RIF_HADM_TIMER0__TXON_TIME__MASK 0x03ff0000U +#define RIF_HADM_TIMER0__TXON_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0x03ff0000U) >> 16) +#define RIF_HADM_TIMER0__TXON_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x03ff0000U) +#define RIF_HADM_TIMER0__TXON_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x03ff0000U) +#define RIF_HADM_TIMER0__TXON_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x03ff0000U))) +#define RIF_HADM_TIMER0__TXON_TIME__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field txoff_time */ +/** + * @defgroup rif_regs_core_txoff_time_field txoff_time_field + * @brief macros for field txoff_time + * @details Triggered by falling tx_en + * @{ + */ +#define RIF_HADM_TIMER0__TXOFF_TIME__SHIFT 26 +#define RIF_HADM_TIMER0__TXOFF_TIME__WIDTH 6 +#define RIF_HADM_TIMER0__TXOFF_TIME__MASK 0xfc000000U +#define RIF_HADM_TIMER0__TXOFF_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0xfc000000U) >> 26) +#define RIF_HADM_TIMER0__TXOFF_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0xfc000000U) +#define RIF_HADM_TIMER0__TXOFF_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfc000000U) | (((uint32_t)(src) <<\ + 26) & 0xfc000000U) +#define RIF_HADM_TIMER0__TXOFF_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0xfc000000U))) +#define RIF_HADM_TIMER0__TXOFF_TIME__RESET_VALUE 0x00000002U +/** @} */ +#define RIF_HADM_TIMER0__TYPE uint32_t +#define RIF_HADM_TIMER0__READ 0xffffffffU +#define RIF_HADM_TIMER0__WRITE 0xffffffffU +#define RIF_HADM_TIMER0__PRESERVED 0x00000000U +#define RIF_HADM_TIMER0__RESET_VALUE 0x08000401U + +#endif /* __RIF_HADM_TIMER0_MACRO__ */ + +/** @} end of hadm_timer0 */ + +/* macros for BlueprintGlobalNameSpace::RIF_hadm_timer1 */ +/** + * @defgroup rif_regs_core_hadm_timer1 hadm_timer1 + * @brief All timers in units of 8 MHz clocks definitions. + * @{ + */ +#ifndef __RIF_HADM_TIMER1_MACRO__ +#define __RIF_HADM_TIMER1_MACRO__ + +/* macros for field paon_time */ +/** + * @defgroup rif_regs_core_paon_time_field paon_time_field + * @brief macros for field paon_time + * @details Triggered by rising tx_en + * @{ + */ +#define RIF_HADM_TIMER1__PAON_TIME__SHIFT 0 +#define RIF_HADM_TIMER1__PAON_TIME__WIDTH 10 +#define RIF_HADM_TIMER1__PAON_TIME__MASK 0x000003ffU +#define RIF_HADM_TIMER1__PAON_TIME__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_HADM_TIMER1__PAON_TIME__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_HADM_TIMER1__PAON_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_HADM_TIMER1__PAON_TIME__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define RIF_HADM_TIMER1__PAON_TIME__RESET_VALUE 0x00000168U +/** @} */ + +/* macros for field paoff_time */ +/** + * @defgroup rif_regs_core_paoff_time_field paoff_time_field + * @brief macros for field paoff_time + * @details Triggered by falling tx_en + * @{ + */ +#define RIF_HADM_TIMER1__PAOFF_TIME__SHIFT 10 +#define RIF_HADM_TIMER1__PAOFF_TIME__WIDTH 6 +#define RIF_HADM_TIMER1__PAOFF_TIME__MASK 0x0000fc00U +#define RIF_HADM_TIMER1__PAOFF_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0x0000fc00U) >> 10) +#define RIF_HADM_TIMER1__PAOFF_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x0000fc00U) +#define RIF_HADM_TIMER1__PAOFF_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fc00U) | (((uint32_t)(src) <<\ + 10) & 0x0000fc00U) +#define RIF_HADM_TIMER1__PAOFF_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x0000fc00U))) +#define RIF_HADM_TIMER1__PAOFF_TIME__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rxon_time */ +/** + * @defgroup rif_regs_core_rxon_time_field rxon_time_field + * @brief macros for field rxon_time + * @details Triggered by rising rx_en + * @{ + */ +#define RIF_HADM_TIMER1__RXON_TIME__SHIFT 16 +#define RIF_HADM_TIMER1__RXON_TIME__WIDTH 10 +#define RIF_HADM_TIMER1__RXON_TIME__MASK 0x03ff0000U +#define RIF_HADM_TIMER1__RXON_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0x03ff0000U) >> 16) +#define RIF_HADM_TIMER1__RXON_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x03ff0000U) +#define RIF_HADM_TIMER1__RXON_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x03ff0000U) +#define RIF_HADM_TIMER1__RXON_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x03ff0000U))) +#define RIF_HADM_TIMER1__RXON_TIME__RESET_VALUE 0x00000190U +/** @} */ + +/* macros for field rxoff_time */ +/** + * @defgroup rif_regs_core_rxoff_time_field rxoff_time_field + * @brief macros for field rxoff_time + * @details Triggered by falling rx_en + * @{ + */ +#define RIF_HADM_TIMER1__RXOFF_TIME__SHIFT 26 +#define RIF_HADM_TIMER1__RXOFF_TIME__WIDTH 6 +#define RIF_HADM_TIMER1__RXOFF_TIME__MASK 0xfc000000U +#define RIF_HADM_TIMER1__RXOFF_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0xfc000000U) >> 26) +#define RIF_HADM_TIMER1__RXOFF_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0xfc000000U) +#define RIF_HADM_TIMER1__RXOFF_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfc000000U) | (((uint32_t)(src) <<\ + 26) & 0xfc000000U) +#define RIF_HADM_TIMER1__RXOFF_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0xfc000000U))) +#define RIF_HADM_TIMER1__RXOFF_TIME__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_HADM_TIMER1__TYPE uint32_t +#define RIF_HADM_TIMER1__READ 0xffffffffU +#define RIF_HADM_TIMER1__WRITE 0xffffffffU +#define RIF_HADM_TIMER1__PRESERVED 0x00000000U +#define RIF_HADM_TIMER1__RESET_VALUE 0x01900168U + +#endif /* __RIF_HADM_TIMER1_MACRO__ */ + +/** @} end of hadm_timer1 */ + +/* macros for BlueprintGlobalNameSpace::RIF_hadm_timer2 */ +/** + * @defgroup rif_regs_core_hadm_timer2 hadm_timer2 + * @brief All timers in units of 8 MHz clocks definitions. + * @{ + */ +#ifndef __RIF_HADM_TIMER2_MACRO__ +#define __RIF_HADM_TIMER2_MACRO__ + +/* macros for field adcon_time */ +/** + * @defgroup rif_regs_core_adcon_time_field adcon_time_field + * @brief macros for field adcon_time + * @details Triggered by rising rx_en + * @{ + */ +#define RIF_HADM_TIMER2__ADCON_TIME__SHIFT 0 +#define RIF_HADM_TIMER2__ADCON_TIME__WIDTH 10 +#define RIF_HADM_TIMER2__ADCON_TIME__MASK 0x000003ffU +#define RIF_HADM_TIMER2__ADCON_TIME__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_HADM_TIMER2__ADCON_TIME__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_HADM_TIMER2__ADCON_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_HADM_TIMER2__ADCON_TIME__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define RIF_HADM_TIMER2__ADCON_TIME__RESET_VALUE 0x0000017cU +/** @} */ + +/* macros for field adcoff_time */ +/** + * @defgroup rif_regs_core_adcoff_time_field adcoff_time_field + * @brief macros for field adcoff_time + * @details Triggered by falling rx_en + * @{ + */ +#define RIF_HADM_TIMER2__ADCOFF_TIME__SHIFT 10 +#define RIF_HADM_TIMER2__ADCOFF_TIME__WIDTH 6 +#define RIF_HADM_TIMER2__ADCOFF_TIME__MASK 0x0000fc00U +#define RIF_HADM_TIMER2__ADCOFF_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0x0000fc00U) >> 10) +#define RIF_HADM_TIMER2__ADCOFF_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x0000fc00U) +#define RIF_HADM_TIMER2__ADCOFF_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fc00U) | (((uint32_t)(src) <<\ + 10) & 0x0000fc00U) +#define RIF_HADM_TIMER2__ADCOFF_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x0000fc00U))) +#define RIF_HADM_TIMER2__ADCOFF_TIME__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adcearlyon_time */ +/** + * @defgroup rif_regs_core_adcearlyon_time_field adcearlyon_time_field + * @brief macros for field adcearlyon_time + * @details Triggered by rising rx_en + * @{ + */ +#define RIF_HADM_TIMER2__ADCEARLYON_TIME__SHIFT 16 +#define RIF_HADM_TIMER2__ADCEARLYON_TIME__WIDTH 10 +#define RIF_HADM_TIMER2__ADCEARLYON_TIME__MASK 0x03ff0000U +#define RIF_HADM_TIMER2__ADCEARLYON_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0x03ff0000U) >> 16) +#define RIF_HADM_TIMER2__ADCEARLYON_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x03ff0000U) +#define RIF_HADM_TIMER2__ADCEARLYON_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x03ff0000U) +#define RIF_HADM_TIMER2__ADCEARLYON_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x03ff0000U))) +#define RIF_HADM_TIMER2__ADCEARLYON_TIME__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adcearlyoff_time */ +/** + * @defgroup rif_regs_core_adcearlyoff_time_field adcearlyoff_time_field + * @brief macros for field adcearlyoff_time + * @details Triggered by falling rx_en + * @{ + */ +#define RIF_HADM_TIMER2__ADCEARLYOFF_TIME__SHIFT 26 +#define RIF_HADM_TIMER2__ADCEARLYOFF_TIME__WIDTH 6 +#define RIF_HADM_TIMER2__ADCEARLYOFF_TIME__MASK 0xfc000000U +#define RIF_HADM_TIMER2__ADCEARLYOFF_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0xfc000000U) >> 26) +#define RIF_HADM_TIMER2__ADCEARLYOFF_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0xfc000000U) +#define RIF_HADM_TIMER2__ADCEARLYOFF_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfc000000U) | (((uint32_t)(src) <<\ + 26) & 0xfc000000U) +#define RIF_HADM_TIMER2__ADCEARLYOFF_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0xfc000000U))) +#define RIF_HADM_TIMER2__ADCEARLYOFF_TIME__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_HADM_TIMER2__TYPE uint32_t +#define RIF_HADM_TIMER2__READ 0xffffffffU +#define RIF_HADM_TIMER2__WRITE 0xffffffffU +#define RIF_HADM_TIMER2__PRESERVED 0x00000000U +#define RIF_HADM_TIMER2__RESET_VALUE 0x0000017cU + +#endif /* __RIF_HADM_TIMER2_MACRO__ */ + +/** @} end of hadm_timer2 */ + +/* macros for BlueprintGlobalNameSpace::RIF_hadm_timer3 */ +/** + * @defgroup rif_regs_core_hadm_timer3 hadm_timer3 + * @brief All timers in units of 8 MHz clocks definitions. + * @{ + */ +#ifndef __RIF_HADM_TIMER3_MACRO__ +#define __RIF_HADM_TIMER3_MACRO__ + +/* macros for field xpaon_time */ +/** + * @defgroup rif_regs_core_xpaon_time_field xpaon_time_field + * @brief macros for field xpaon_time + * @details Triggered by rising tx_en + * @{ + */ +#define RIF_HADM_TIMER3__XPAON_TIME__SHIFT 0 +#define RIF_HADM_TIMER3__XPAON_TIME__WIDTH 10 +#define RIF_HADM_TIMER3__XPAON_TIME__MASK 0x000003ffU +#define RIF_HADM_TIMER3__XPAON_TIME__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_HADM_TIMER3__XPAON_TIME__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define RIF_HADM_TIMER3__XPAON_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define RIF_HADM_TIMER3__XPAON_TIME__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define RIF_HADM_TIMER3__XPAON_TIME__RESET_VALUE 0x00000168U +/** @} */ + +/* macros for field xpaoff_time */ +/** + * @defgroup rif_regs_core_xpaoff_time_field xpaoff_time_field + * @brief macros for field xpaoff_time + * @details Triggered by falling tx_en + * @{ + */ +#define RIF_HADM_TIMER3__XPAOFF_TIME__SHIFT 10 +#define RIF_HADM_TIMER3__XPAOFF_TIME__WIDTH 6 +#define RIF_HADM_TIMER3__XPAOFF_TIME__MASK 0x0000fc00U +#define RIF_HADM_TIMER3__XPAOFF_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0x0000fc00U) >> 10) +#define RIF_HADM_TIMER3__XPAOFF_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x0000fc00U) +#define RIF_HADM_TIMER3__XPAOFF_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fc00U) | (((uint32_t)(src) <<\ + 10) & 0x0000fc00U) +#define RIF_HADM_TIMER3__XPAOFF_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x0000fc00U))) +#define RIF_HADM_TIMER3__XPAOFF_TIME__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field xlnaon_time */ +/** + * @defgroup rif_regs_core_xlnaon_time_field xlnaon_time_field + * @brief macros for field xlnaon_time + * @details Triggered by rising rx_en + * @{ + */ +#define RIF_HADM_TIMER3__XLNAON_TIME__SHIFT 16 +#define RIF_HADM_TIMER3__XLNAON_TIME__WIDTH 10 +#define RIF_HADM_TIMER3__XLNAON_TIME__MASK 0x03ff0000U +#define RIF_HADM_TIMER3__XLNAON_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0x03ff0000U) >> 16) +#define RIF_HADM_TIMER3__XLNAON_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x03ff0000U) +#define RIF_HADM_TIMER3__XLNAON_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03ff0000U) | (((uint32_t)(src) <<\ + 16) & 0x03ff0000U) +#define RIF_HADM_TIMER3__XLNAON_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x03ff0000U))) +#define RIF_HADM_TIMER3__XLNAON_TIME__RESET_VALUE 0x00000190U +/** @} */ + +/* macros for field xlnaoff_time */ +/** + * @defgroup rif_regs_core_xlnaoff_time_field xlnaoff_time_field + * @brief macros for field xlnaoff_time + * @details Triggered by falling rx_en + * @{ + */ +#define RIF_HADM_TIMER3__XLNAOFF_TIME__SHIFT 26 +#define RIF_HADM_TIMER3__XLNAOFF_TIME__WIDTH 6 +#define RIF_HADM_TIMER3__XLNAOFF_TIME__MASK 0xfc000000U +#define RIF_HADM_TIMER3__XLNAOFF_TIME__READ(src) \ + (((uint32_t)(src)\ + & 0xfc000000U) >> 26) +#define RIF_HADM_TIMER3__XLNAOFF_TIME__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0xfc000000U) +#define RIF_HADM_TIMER3__XLNAOFF_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfc000000U) | (((uint32_t)(src) <<\ + 26) & 0xfc000000U) +#define RIF_HADM_TIMER3__XLNAOFF_TIME__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0xfc000000U))) +#define RIF_HADM_TIMER3__XLNAOFF_TIME__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_HADM_TIMER3__TYPE uint32_t +#define RIF_HADM_TIMER3__READ 0xffffffffU +#define RIF_HADM_TIMER3__WRITE 0xffffffffU +#define RIF_HADM_TIMER3__PRESERVED 0x00000000U +#define RIF_HADM_TIMER3__RESET_VALUE 0x01900168U + +#endif /* __RIF_HADM_TIMER3_MACRO__ */ + +/** @} end of hadm_timer3 */ + +/* macros for BlueprintGlobalNameSpace::RIF_rxdc7 */ +/** + * @defgroup rif_regs_core_rxdc7 rxdc7 + * @brief RX DC offset for manual override for TIA and PGA definitions. + * @{ + */ +#ifndef __RIF_RXDC7_MACRO__ +#define __RIF_RXDC7_MACRO__ + +/* macros for field bb1q_dcoc */ +/** + * @defgroup rif_regs_core_bb1q_dcoc_field bb1q_dcoc_field + * @brief macros for field bb1q_dcoc + * @details value of TIA Q offset DAC when bb1_dcoc_ovr = 1 + * @{ + */ +#define RIF_RXDC7__BB1Q_DCOC__SHIFT 0 +#define RIF_RXDC7__BB1Q_DCOC__WIDTH 8 +#define RIF_RXDC7__BB1Q_DCOC__MASK 0x000000ffU +#define RIF_RXDC7__BB1Q_DCOC__READ(src) ((uint32_t)(src) & 0x000000ffU) +#define RIF_RXDC7__BB1Q_DCOC__WRITE(src) ((uint32_t)(src) & 0x000000ffU) +#define RIF_RXDC7__BB1Q_DCOC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define RIF_RXDC7__BB1Q_DCOC__VERIFY(src) (!(((uint32_t)(src) & ~0x000000ffU))) +#define RIF_RXDC7__BB1Q_DCOC__RESET_VALUE 0x00000020U +/** @} */ + +/* macros for field bb1i_dcoc */ +/** + * @defgroup rif_regs_core_bb1i_dcoc_field bb1i_dcoc_field + * @brief macros for field bb1i_dcoc + * @details value of TIA I offset DAC when bb1_dcoc_ovr = 1 + * @{ + */ +#define RIF_RXDC7__BB1I_DCOC__SHIFT 8 +#define RIF_RXDC7__BB1I_DCOC__WIDTH 8 +#define RIF_RXDC7__BB1I_DCOC__MASK 0x0000ff00U +#define RIF_RXDC7__BB1I_DCOC__READ(src) (((uint32_t)(src) & 0x0000ff00U) >> 8) +#define RIF_RXDC7__BB1I_DCOC__WRITE(src) (((uint32_t)(src) << 8) & 0x0000ff00U) +#define RIF_RXDC7__BB1I_DCOC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define RIF_RXDC7__BB1I_DCOC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define RIF_RXDC7__BB1I_DCOC__RESET_VALUE 0x00000020U +/** @} */ + +/* macros for field bb1_dcoc_ovr */ +/** + * @defgroup rif_regs_core_bb1_dcoc_ovr_field bb1_dcoc_ovr_field + * @brief macros for field bb1_dcoc_ovr + * @details override TIA offset DAC values from modem + * @{ + */ +#define RIF_RXDC7__BB1_DCOC_OVR__SHIFT 16 +#define RIF_RXDC7__BB1_DCOC_OVR__WIDTH 1 +#define RIF_RXDC7__BB1_DCOC_OVR__MASK 0x00010000U +#define RIF_RXDC7__BB1_DCOC_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define RIF_RXDC7__BB1_DCOC_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define RIF_RXDC7__BB1_DCOC_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define RIF_RXDC7__BB1_DCOC_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define RIF_RXDC7__BB1_DCOC_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define RIF_RXDC7__BB1_DCOC_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define RIF_RXDC7__BB1_DCOC_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field bb2q_dcoc */ +/** + * @defgroup rif_regs_core_bb2q_dcoc_field bb2q_dcoc_field + * @brief macros for field bb2q_dcoc + * @details value of PGA Q offset DAC when bb2_dcoc_ovr = 1 + * @{ + */ +#define RIF_RXDC7__BB2Q_DCOC__SHIFT 17 +#define RIF_RXDC7__BB2Q_DCOC__WIDTH 5 +#define RIF_RXDC7__BB2Q_DCOC__MASK 0x003e0000U +#define RIF_RXDC7__BB2Q_DCOC__READ(src) (((uint32_t)(src) & 0x003e0000U) >> 17) +#define RIF_RXDC7__BB2Q_DCOC__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x003e0000U) +#define RIF_RXDC7__BB2Q_DCOC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((uint32_t)(src) <<\ + 17) & 0x003e0000U) +#define RIF_RXDC7__BB2Q_DCOC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x003e0000U))) +#define RIF_RXDC7__BB2Q_DCOC__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field bb2i_dcoc */ +/** + * @defgroup rif_regs_core_bb2i_dcoc_field bb2i_dcoc_field + * @brief macros for field bb2i_dcoc + * @details value of PGA I offset DAC when bb2_dcoc_ovr = 1 + * @{ + */ +#define RIF_RXDC7__BB2I_DCOC__SHIFT 22 +#define RIF_RXDC7__BB2I_DCOC__WIDTH 5 +#define RIF_RXDC7__BB2I_DCOC__MASK 0x07c00000U +#define RIF_RXDC7__BB2I_DCOC__READ(src) (((uint32_t)(src) & 0x07c00000U) >> 22) +#define RIF_RXDC7__BB2I_DCOC__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x07c00000U) +#define RIF_RXDC7__BB2I_DCOC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((uint32_t)(src) <<\ + 22) & 0x07c00000U) +#define RIF_RXDC7__BB2I_DCOC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x07c00000U))) +#define RIF_RXDC7__BB2I_DCOC__RESET_VALUE 0x00000010U +/** @} */ + +/* macros for field bb2_dcoc_ovr */ +/** + * @defgroup rif_regs_core_bb2_dcoc_ovr_field bb2_dcoc_ovr_field + * @brief macros for field bb2_dcoc_ovr + * @details override PGA offset DAC values from modem + * @{ + */ +#define RIF_RXDC7__BB2_DCOC_OVR__SHIFT 27 +#define RIF_RXDC7__BB2_DCOC_OVR__WIDTH 1 +#define RIF_RXDC7__BB2_DCOC_OVR__MASK 0x08000000U +#define RIF_RXDC7__BB2_DCOC_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define RIF_RXDC7__BB2_DCOC_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define RIF_RXDC7__BB2_DCOC_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define RIF_RXDC7__BB2_DCOC_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define RIF_RXDC7__BB2_DCOC_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define RIF_RXDC7__BB2_DCOC_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define RIF_RXDC7__BB2_DCOC_OVR__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_RXDC7__TYPE uint32_t +#define RIF_RXDC7__READ 0x0fffffffU +#define RIF_RXDC7__WRITE 0x0fffffffU +#define RIF_RXDC7__PRESERVED 0x00000000U +#define RIF_RXDC7__RESET_VALUE 0x04202020U + +#endif /* __RIF_RXDC7_MACRO__ */ + +/** @} end of rxdc7 */ + +/* macros for BlueprintGlobalNameSpace::RIF_synth_chan0 */ +/** + * @defgroup rif_regs_core_synth_chan0 synth_chan0 + * @brief Synth channel programming definitions. + * @{ + */ +#ifndef __RIF_SYNTH_CHAN0_MACRO__ +#define __RIF_SYNTH_CHAN0_MACRO__ + +/* macros for field chan_frac_rx_base */ +/** + * @defgroup rif_regs_core_chan_frac_rx_base_field chan_frac_rx_base_field + * @brief macros for field chan_frac_rx_base + * @details Fractional part divide ratio for RX at 2402MHz with 8MHz Fref, = (2402*sif_ratio/Fref - chan_int_rx_base)*2^15 + * @{ + */ +#define RIF_SYNTH_CHAN0__CHAN_FRAC_RX_BASE__SHIFT 0 +#define RIF_SYNTH_CHAN0__CHAN_FRAC_RX_BASE__WIDTH 15 +#define RIF_SYNTH_CHAN0__CHAN_FRAC_RX_BASE__MASK 0x00007fffU +#define RIF_SYNTH_CHAN0__CHAN_FRAC_RX_BASE__READ(src) \ + ((uint32_t)(src)\ + & 0x00007fffU) +#define RIF_SYNTH_CHAN0__CHAN_FRAC_RX_BASE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00007fffU) +#define RIF_SYNTH_CHAN0__CHAN_FRAC_RX_BASE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007fffU) | ((uint32_t)(src) &\ + 0x00007fffU) +#define RIF_SYNTH_CHAN0__CHAN_FRAC_RX_BASE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00007fffU))) +#define RIF_SYNTH_CHAN0__CHAN_FRAC_RX_BASE__RESET_VALUE 0x00001249U +/** @} */ + +/* macros for field chan_int_rx_base */ +/** + * @defgroup rif_regs_core_chan_int_rx_base_field chan_int_rx_base_field + * @brief macros for field chan_int_rx_base + * @details Integer part divide ratio for RX at 2402MHz with 8MHz Fref, = int(2402*sif_ratio/Fref) + * @{ + */ +#define RIF_SYNTH_CHAN0__CHAN_INT_RX_BASE__SHIFT 15 +#define RIF_SYNTH_CHAN0__CHAN_INT_RX_BASE__WIDTH 9 +#define RIF_SYNTH_CHAN0__CHAN_INT_RX_BASE__MASK 0x00ff8000U +#define RIF_SYNTH_CHAN0__CHAN_INT_RX_BASE__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff8000U) >> 15) +#define RIF_SYNTH_CHAN0__CHAN_INT_RX_BASE__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00ff8000U) +#define RIF_SYNTH_CHAN0__CHAN_INT_RX_BASE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff8000U) | (((uint32_t)(src) <<\ + 15) & 0x00ff8000U) +#define RIF_SYNTH_CHAN0__CHAN_INT_RX_BASE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00ff8000U))) +#define RIF_SYNTH_CHAN0__CHAN_INT_RX_BASE__RESET_VALUE 0x00000157U +/** @} */ +#define RIF_SYNTH_CHAN0__TYPE uint32_t +#define RIF_SYNTH_CHAN0__READ 0x00ffffffU +#define RIF_SYNTH_CHAN0__WRITE 0x00ffffffU +#define RIF_SYNTH_CHAN0__PRESERVED 0x00000000U +#define RIF_SYNTH_CHAN0__RESET_VALUE 0x00ab9249U + +#endif /* __RIF_SYNTH_CHAN0_MACRO__ */ + +/** @} end of synth_chan0 */ + +/* macros for BlueprintGlobalNameSpace::RIF_synth_chan1 */ +/** + * @defgroup rif_regs_core_synth_chan1 synth_chan1 + * @brief Synth channel programming definitions. + * @{ + */ +#ifndef __RIF_SYNTH_CHAN1_MACRO__ +#define __RIF_SYNTH_CHAN1_MACRO__ + +/* macros for field chan_frac_sif */ +/** + * @defgroup rif_regs_core_chan_frac_sif_field chan_frac_sif_field + * @brief macros for field chan_frac_sif + * @details Sliding-IF channel spacing in MHz in extended chan_frac units, = sif_ratio/Fref*2^21 + * @{ + */ +#define RIF_SYNTH_CHAN1__CHAN_FRAC_SIF__SHIFT 0 +#define RIF_SYNTH_CHAN1__CHAN_FRAC_SIF__WIDTH 21 +#define RIF_SYNTH_CHAN1__CHAN_FRAC_SIF__MASK 0x001fffffU +#define RIF_SYNTH_CHAN1__CHAN_FRAC_SIF__READ(src) \ + ((uint32_t)(src)\ + & 0x001fffffU) +#define RIF_SYNTH_CHAN1__CHAN_FRAC_SIF__WRITE(src) \ + ((uint32_t)(src)\ + & 0x001fffffU) +#define RIF_SYNTH_CHAN1__CHAN_FRAC_SIF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001fffffU) | ((uint32_t)(src) &\ + 0x001fffffU) +#define RIF_SYNTH_CHAN1__CHAN_FRAC_SIF__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x001fffffU))) +#define RIF_SYNTH_CHAN1__CHAN_FRAC_SIF__RESET_VALUE 0x00049249U +/** @} */ +#define RIF_SYNTH_CHAN1__TYPE uint32_t +#define RIF_SYNTH_CHAN1__READ 0x001fffffU +#define RIF_SYNTH_CHAN1__WRITE 0x001fffffU +#define RIF_SYNTH_CHAN1__PRESERVED 0x00000000U +#define RIF_SYNTH_CHAN1__RESET_VALUE 0x00049249U + +#endif /* __RIF_SYNTH_CHAN1_MACRO__ */ + +/** @} end of synth_chan1 */ + +/* macros for BlueprintGlobalNameSpace::RIF_synth_chan2 */ +/** + * @defgroup rif_regs_core_synth_chan2 synth_chan2 + * @brief Synth channel programming definitions. + * @{ + */ +#ifndef __RIF_SYNTH_CHAN2_MACRO__ +#define __RIF_SYNTH_CHAN2_MACRO__ + +/* macros for field chan_frac_lif1 */ +/** + * @defgroup rif_regs_core_chan_frac_lif1_field chan_frac_lif1_field + * @brief macros for field chan_frac_lif1 + * @details Low-IF offset in MHz for 1Mbps rate in extended chan_frac units, = lif_1M*sif_ratio/Fref*2^21, default 0.8MHz + * @{ + */ +#define RIF_SYNTH_CHAN2__CHAN_FRAC_LIF1__SHIFT 0 +#define RIF_SYNTH_CHAN2__CHAN_FRAC_LIF1__WIDTH 21 +#define RIF_SYNTH_CHAN2__CHAN_FRAC_LIF1__MASK 0x001fffffU +#define RIF_SYNTH_CHAN2__CHAN_FRAC_LIF1__READ(src) \ + ((uint32_t)(src)\ + & 0x001fffffU) +#define RIF_SYNTH_CHAN2__CHAN_FRAC_LIF1__WRITE(src) \ + ((uint32_t)(src)\ + & 0x001fffffU) +#define RIF_SYNTH_CHAN2__CHAN_FRAC_LIF1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001fffffU) | ((uint32_t)(src) &\ + 0x001fffffU) +#define RIF_SYNTH_CHAN2__CHAN_FRAC_LIF1__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x001fffffU))) +#define RIF_SYNTH_CHAN2__CHAN_FRAC_LIF1__RESET_VALUE 0x0003a83aU +/** @} */ +#define RIF_SYNTH_CHAN2__TYPE uint32_t +#define RIF_SYNTH_CHAN2__READ 0x001fffffU +#define RIF_SYNTH_CHAN2__WRITE 0x001fffffU +#define RIF_SYNTH_CHAN2__PRESERVED 0x00000000U +#define RIF_SYNTH_CHAN2__RESET_VALUE 0x0003a83aU + +#endif /* __RIF_SYNTH_CHAN2_MACRO__ */ + +/** @} end of synth_chan2 */ + +/* macros for BlueprintGlobalNameSpace::RIF_synth_chan3 */ +/** + * @defgroup rif_regs_core_synth_chan3 synth_chan3 + * @brief Synth channel programming definitions. + * @{ + */ +#ifndef __RIF_SYNTH_CHAN3_MACRO__ +#define __RIF_SYNTH_CHAN3_MACRO__ + +/* macros for field chan_frac_lif2 */ +/** + * @defgroup rif_regs_core_chan_frac_lif2_field chan_frac_lif2_field + * @brief macros for field chan_frac_lif2 + * @details Low-IF offset in MHz for 2Mbps rate in extended chan_frac units, = lif_2M*sif_ratio/Fref*2^21, default 1.6MHz + * @{ + */ +#define RIF_SYNTH_CHAN3__CHAN_FRAC_LIF2__SHIFT 0 +#define RIF_SYNTH_CHAN3__CHAN_FRAC_LIF2__WIDTH 21 +#define RIF_SYNTH_CHAN3__CHAN_FRAC_LIF2__MASK 0x001fffffU +#define RIF_SYNTH_CHAN3__CHAN_FRAC_LIF2__READ(src) \ + ((uint32_t)(src)\ + & 0x001fffffU) +#define RIF_SYNTH_CHAN3__CHAN_FRAC_LIF2__WRITE(src) \ + ((uint32_t)(src)\ + & 0x001fffffU) +#define RIF_SYNTH_CHAN3__CHAN_FRAC_LIF2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001fffffU) | ((uint32_t)(src) &\ + 0x001fffffU) +#define RIF_SYNTH_CHAN3__CHAN_FRAC_LIF2__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x001fffffU))) +#define RIF_SYNTH_CHAN3__CHAN_FRAC_LIF2__RESET_VALUE 0x00075074U +/** @} */ +#define RIF_SYNTH_CHAN3__TYPE uint32_t +#define RIF_SYNTH_CHAN3__READ 0x001fffffU +#define RIF_SYNTH_CHAN3__WRITE 0x001fffffU +#define RIF_SYNTH_CHAN3__PRESERVED 0x00000000U +#define RIF_SYNTH_CHAN3__RESET_VALUE 0x00075074U + +#endif /* __RIF_SYNTH_CHAN3_MACRO__ */ + +/** @} end of synth_chan3 */ + +/* macros for BlueprintGlobalNameSpace::RIF_synth_chan4 */ +/** + * @defgroup rif_regs_core_synth_chan4 synth_chan4 + * @brief Synth channel programming definitions. + * @{ + */ +#ifndef __RIF_SYNTH_CHAN4_MACRO__ +#define __RIF_SYNTH_CHAN4_MACRO__ + +/* macros for field chan_frac_cfo */ +/** + * @defgroup rif_regs_core_chan_frac_cfo_field chan_frac_cfo_field + * @brief macros for field chan_frac_cfo + * @details RX carrier frequency offset in MHz in extended chan_frac units, = cfo*sif_ratio/Fref*2^21. Signed from -0.5MHz to 0.5MHz + * @{ + */ +#define RIF_SYNTH_CHAN4__CHAN_FRAC_CFO__SHIFT 0 +#define RIF_SYNTH_CHAN4__CHAN_FRAC_CFO__WIDTH 21 +#define RIF_SYNTH_CHAN4__CHAN_FRAC_CFO__MASK 0x001fffffU +#define RIF_SYNTH_CHAN4__CHAN_FRAC_CFO__READ(src) \ + ((uint32_t)(src)\ + & 0x001fffffU) +#define RIF_SYNTH_CHAN4__CHAN_FRAC_CFO__WRITE(src) \ + ((uint32_t)(src)\ + & 0x001fffffU) +#define RIF_SYNTH_CHAN4__CHAN_FRAC_CFO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001fffffU) | ((uint32_t)(src) &\ + 0x001fffffU) +#define RIF_SYNTH_CHAN4__CHAN_FRAC_CFO__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x001fffffU))) +#define RIF_SYNTH_CHAN4__CHAN_FRAC_CFO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field chan_frac_tx_lsb */ +/** + * @defgroup rif_regs_core_chan_frac_tx_lsb_field chan_frac_tx_lsb_field + * @brief macros for field chan_frac_tx_lsb + * @details LSB shift to avoid fractional spurs in TX + * @{ + */ +#define RIF_SYNTH_CHAN4__CHAN_FRAC_TX_LSB__SHIFT 21 +#define RIF_SYNTH_CHAN4__CHAN_FRAC_TX_LSB__WIDTH 4 +#define RIF_SYNTH_CHAN4__CHAN_FRAC_TX_LSB__MASK 0x01e00000U +#define RIF_SYNTH_CHAN4__CHAN_FRAC_TX_LSB__READ(src) \ + (((uint32_t)(src)\ + & 0x01e00000U) >> 21) +#define RIF_SYNTH_CHAN4__CHAN_FRAC_TX_LSB__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x01e00000U) +#define RIF_SYNTH_CHAN4__CHAN_FRAC_TX_LSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01e00000U) | (((uint32_t)(src) <<\ + 21) & 0x01e00000U) +#define RIF_SYNTH_CHAN4__CHAN_FRAC_TX_LSB__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x01e00000U))) +#define RIF_SYNTH_CHAN4__CHAN_FRAC_TX_LSB__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field sif_num */ +/** + * @defgroup rif_regs_core_sif_num_field sif_num_field + * @brief macros for field sif_num + * @details sif_num+1 is power of sliding-IF ratio numerator, ie. for 8/7, sif_num = 2 + * @{ + */ +#define RIF_SYNTH_CHAN4__SIF_NUM__SHIFT 25 +#define RIF_SYNTH_CHAN4__SIF_NUM__WIDTH 2 +#define RIF_SYNTH_CHAN4__SIF_NUM__MASK 0x06000000U +#define RIF_SYNTH_CHAN4__SIF_NUM__READ(src) \ + (((uint32_t)(src)\ + & 0x06000000U) >> 25) +#define RIF_SYNTH_CHAN4__SIF_NUM__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x06000000U) +#define RIF_SYNTH_CHAN4__SIF_NUM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x06000000U) | (((uint32_t)(src) <<\ + 25) & 0x06000000U) +#define RIF_SYNTH_CHAN4__SIF_NUM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x06000000U))) +#define RIF_SYNTH_CHAN4__SIF_NUM__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field high_side_lo */ +/** + * @defgroup rif_regs_core_high_side_lo_field high_side_lo_field + * @brief macros for field high_side_lo + * @details Low-IF LO frequency side, 1 = LO is placed above desired signal, 0 = LO placed below desired signal + * @{ + */ +#define RIF_SYNTH_CHAN4__HIGH_SIDE_LO__SHIFT 27 +#define RIF_SYNTH_CHAN4__HIGH_SIDE_LO__WIDTH 1 +#define RIF_SYNTH_CHAN4__HIGH_SIDE_LO__MASK 0x08000000U +#define RIF_SYNTH_CHAN4__HIGH_SIDE_LO__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define RIF_SYNTH_CHAN4__HIGH_SIDE_LO__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define RIF_SYNTH_CHAN4__HIGH_SIDE_LO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define RIF_SYNTH_CHAN4__HIGH_SIDE_LO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define RIF_SYNTH_CHAN4__HIGH_SIDE_LO__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define RIF_SYNTH_CHAN4__HIGH_SIDE_LO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define RIF_SYNTH_CHAN4__HIGH_SIDE_LO__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_SYNTH_CHAN4__TYPE uint32_t +#define RIF_SYNTH_CHAN4__READ 0x0fffffffU +#define RIF_SYNTH_CHAN4__WRITE 0x0fffffffU +#define RIF_SYNTH_CHAN4__PRESERVED 0x00000000U +#define RIF_SYNTH_CHAN4__RESET_VALUE 0x04000000U + +#endif /* __RIF_SYNTH_CHAN4_MACRO__ */ + +/** @} end of synth_chan4 */ + +/* macros for BlueprintGlobalNameSpace::RIF_synth_chan5 */ +/** + * @defgroup rif_regs_core_synth_chan5 synth_chan5 + * @brief Synth channel programming for HADM definitions. + * @{ + */ +#ifndef __RIF_SYNTH_CHAN5_MACRO__ +#define __RIF_SYNTH_CHAN5_MACRO__ + +/* macros for field hadm_chan_frac_hlif */ +/** + * @defgroup rif_regs_core_hadm_chan_frac_hlif_field hadm_chan_frac_hlif_field + * @brief macros for field hadm_chan_frac_hlif + * @details Half low-IF offset in MHz in HADM mode in extended chan_frac units, = hadm_hlif/Fref*2^21, default 0.4MHz + * @{ + */ +#define RIF_SYNTH_CHAN5__HADM_CHAN_FRAC_HLIF__SHIFT 0 +#define RIF_SYNTH_CHAN5__HADM_CHAN_FRAC_HLIF__WIDTH 21 +#define RIF_SYNTH_CHAN5__HADM_CHAN_FRAC_HLIF__MASK 0x001fffffU +#define RIF_SYNTH_CHAN5__HADM_CHAN_FRAC_HLIF__READ(src) \ + ((uint32_t)(src)\ + & 0x001fffffU) +#define RIF_SYNTH_CHAN5__HADM_CHAN_FRAC_HLIF__WRITE(src) \ + ((uint32_t)(src)\ + & 0x001fffffU) +#define RIF_SYNTH_CHAN5__HADM_CHAN_FRAC_HLIF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001fffffU) | ((uint32_t)(src) &\ + 0x001fffffU) +#define RIF_SYNTH_CHAN5__HADM_CHAN_FRAC_HLIF__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x001fffffU))) +#define RIF_SYNTH_CHAN5__HADM_CHAN_FRAC_HLIF__RESET_VALUE 0x00019999U +/** @} */ + +/* macros for field hadm_high_side_lo */ +/** + * @defgroup rif_regs_core_hadm_high_side_lo_field hadm_high_side_lo_field + * @brief macros for field hadm_high_side_lo + * @details Low-IF LO frequency side in HADM mode, 1 = LO is placed above desired signal, 0 = LO placed below desired signal + * @{ + */ +#define RIF_SYNTH_CHAN5__HADM_HIGH_SIDE_LO__SHIFT 21 +#define RIF_SYNTH_CHAN5__HADM_HIGH_SIDE_LO__WIDTH 1 +#define RIF_SYNTH_CHAN5__HADM_HIGH_SIDE_LO__MASK 0x00200000U +#define RIF_SYNTH_CHAN5__HADM_HIGH_SIDE_LO__READ(src) \ + (((uint32_t)(src)\ + & 0x00200000U) >> 21) +#define RIF_SYNTH_CHAN5__HADM_HIGH_SIDE_LO__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define RIF_SYNTH_CHAN5__HADM_HIGH_SIDE_LO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define RIF_SYNTH_CHAN5__HADM_HIGH_SIDE_LO__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define RIF_SYNTH_CHAN5__HADM_HIGH_SIDE_LO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define RIF_SYNTH_CHAN5__HADM_HIGH_SIDE_LO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define RIF_SYNTH_CHAN5__HADM_HIGH_SIDE_LO__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_SYNTH_CHAN5__TYPE uint32_t +#define RIF_SYNTH_CHAN5__READ 0x003fffffU +#define RIF_SYNTH_CHAN5__WRITE 0x003fffffU +#define RIF_SYNTH_CHAN5__PRESERVED 0x00000000U +#define RIF_SYNTH_CHAN5__RESET_VALUE 0x00019999U + +#endif /* __RIF_SYNTH_CHAN5_MACRO__ */ + +/** @} end of synth_chan5 */ + +/* macros for BlueprintGlobalNameSpace::RIF_adc_cntl */ +/** + * @defgroup rif_regs_core_adc_cntl adc_cntl + * @brief ADC controls definitions. + * @{ + */ +#ifndef __RIF_ADC_CNTL_MACRO__ +#define __RIF_ADC_CNTL_MACRO__ + +/* macros for field invert_msb */ +/** + * @defgroup rif_regs_core_invert_msb_field invert_msb_field + * @brief macros for field invert_msb + * @details To convert from unsigned to signed + * @{ + */ +#define RIF_ADC_CNTL__INVERT_MSB__SHIFT 0 +#define RIF_ADC_CNTL__INVERT_MSB__WIDTH 1 +#define RIF_ADC_CNTL__INVERT_MSB__MASK 0x00000001U +#define RIF_ADC_CNTL__INVERT_MSB__READ(src) ((uint32_t)(src) & 0x00000001U) +#define RIF_ADC_CNTL__INVERT_MSB__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define RIF_ADC_CNTL__INVERT_MSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define RIF_ADC_CNTL__INVERT_MSB__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define RIF_ADC_CNTL__INVERT_MSB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define RIF_ADC_CNTL__INVERT_MSB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define RIF_ADC_CNTL__INVERT_MSB__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field swap_iq */ +/** + * @defgroup rif_regs_core_swap_iq_field swap_iq_field + * @brief macros for field swap_iq + * @details Swap I and Q channels after ADC outputs + * @{ + */ +#define RIF_ADC_CNTL__SWAP_IQ__SHIFT 1 +#define RIF_ADC_CNTL__SWAP_IQ__WIDTH 1 +#define RIF_ADC_CNTL__SWAP_IQ__MASK 0x00000002U +#define RIF_ADC_CNTL__SWAP_IQ__READ(src) (((uint32_t)(src) & 0x00000002U) >> 1) +#define RIF_ADC_CNTL__SWAP_IQ__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define RIF_ADC_CNTL__SWAP_IQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define RIF_ADC_CNTL__SWAP_IQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define RIF_ADC_CNTL__SWAP_IQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define RIF_ADC_CNTL__SWAP_IQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define RIF_ADC_CNTL__SWAP_IQ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field invert_i */ +/** + * @defgroup rif_regs_core_invert_i_field invert_i_field + * @brief macros for field invert_i + * @details Invert I *before* possible iq swap + * @{ + */ +#define RIF_ADC_CNTL__INVERT_I__SHIFT 2 +#define RIF_ADC_CNTL__INVERT_I__WIDTH 1 +#define RIF_ADC_CNTL__INVERT_I__MASK 0x00000004U +#define RIF_ADC_CNTL__INVERT_I__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define RIF_ADC_CNTL__INVERT_I__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define RIF_ADC_CNTL__INVERT_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define RIF_ADC_CNTL__INVERT_I__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define RIF_ADC_CNTL__INVERT_I__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define RIF_ADC_CNTL__INVERT_I__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define RIF_ADC_CNTL__INVERT_I__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field invert_q */ +/** + * @defgroup rif_regs_core_invert_q_field invert_q_field + * @brief macros for field invert_q + * @details Invert Q *before* possible iq swap + * @{ + */ +#define RIF_ADC_CNTL__INVERT_Q__SHIFT 3 +#define RIF_ADC_CNTL__INVERT_Q__WIDTH 1 +#define RIF_ADC_CNTL__INVERT_Q__MASK 0x00000008U +#define RIF_ADC_CNTL__INVERT_Q__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define RIF_ADC_CNTL__INVERT_Q__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define RIF_ADC_CNTL__INVERT_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define RIF_ADC_CNTL__INVERT_Q__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define RIF_ADC_CNTL__INVERT_Q__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define RIF_ADC_CNTL__INVERT_Q__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define RIF_ADC_CNTL__INVERT_Q__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field edge_sel */ +/** + * @defgroup rif_regs_core_edge_sel_field edge_sel_field + * @brief macros for field edge_sel + * @details 0 = launch ADC data on falling edge out of radio, 1 = launch ADC data on rising edge out of radio + * @{ + */ +#define RIF_ADC_CNTL__EDGE_SEL__SHIFT 4 +#define RIF_ADC_CNTL__EDGE_SEL__WIDTH 1 +#define RIF_ADC_CNTL__EDGE_SEL__MASK 0x00000010U +#define RIF_ADC_CNTL__EDGE_SEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define RIF_ADC_CNTL__EDGE_SEL__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define RIF_ADC_CNTL__EDGE_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define RIF_ADC_CNTL__EDGE_SEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define RIF_ADC_CNTL__EDGE_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define RIF_ADC_CNTL__EDGE_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define RIF_ADC_CNTL__EDGE_SEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field delay_ctrl */ +/** + * @defgroup rif_regs_core_delay_ctrl_field delay_ctrl_field + * @brief macros for field delay_ctrl + * @details SAR logic delay control, delay decreases as control increases + * @{ + */ +#define RIF_ADC_CNTL__DELAY_CTRL__SHIFT 5 +#define RIF_ADC_CNTL__DELAY_CTRL__WIDTH 3 +#define RIF_ADC_CNTL__DELAY_CTRL__MASK 0x000000e0U +#define RIF_ADC_CNTL__DELAY_CTRL__READ(src) \ + (((uint32_t)(src)\ + & 0x000000e0U) >> 5) +#define RIF_ADC_CNTL__DELAY_CTRL__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x000000e0U) +#define RIF_ADC_CNTL__DELAY_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((uint32_t)(src) <<\ + 5) & 0x000000e0U) +#define RIF_ADC_CNTL__DELAY_CTRL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000000e0U))) +#define RIF_ADC_CNTL__DELAY_CTRL__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field ref_ctrl */ +/** + * @defgroup rif_regs_core_ref_ctrl_field ref_ctrl_field + * @brief macros for field ref_ctrl + * @details ADC reference voltage level = 0.8 + 0.1*(ref_ctrl[2:0] - 4) + * @{ + */ +#define RIF_ADC_CNTL__REF_CTRL__SHIFT 8 +#define RIF_ADC_CNTL__REF_CTRL__WIDTH 3 +#define RIF_ADC_CNTL__REF_CTRL__MASK 0x00000700U +#define RIF_ADC_CNTL__REF_CTRL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000700U) >> 8) +#define RIF_ADC_CNTL__REF_CTRL__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000700U) +#define RIF_ADC_CNTL__REF_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((uint32_t)(src) <<\ + 8) & 0x00000700U) +#define RIF_ADC_CNTL__REF_CTRL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000700U))) +#define RIF_ADC_CNTL__REF_CTRL__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field clksample_ext */ +/** + * @defgroup rif_regs_core_clksample_ext_field clksample_ext_field + * @brief macros for field clksample_ext + * @details Borrow time from sampling phase + * @{ + */ +#define RIF_ADC_CNTL__CLKSAMPLE_EXT__SHIFT 11 +#define RIF_ADC_CNTL__CLKSAMPLE_EXT__WIDTH 1 +#define RIF_ADC_CNTL__CLKSAMPLE_EXT__MASK 0x00000800U +#define RIF_ADC_CNTL__CLKSAMPLE_EXT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define RIF_ADC_CNTL__CLKSAMPLE_EXT__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define RIF_ADC_CNTL__CLKSAMPLE_EXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define RIF_ADC_CNTL__CLKSAMPLE_EXT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define RIF_ADC_CNTL__CLKSAMPLE_EXT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define RIF_ADC_CNTL__CLKSAMPLE_EXT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define RIF_ADC_CNTL__CLKSAMPLE_EXT__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field vcm_ctrl */ +/** + * @defgroup rif_regs_core_vcm_ctrl_field vcm_ctrl_field + * @brief macros for field vcm_ctrl + * @details ADC common-mode voltage level = 0.5 + 0.125*(vcm_ctrl[1:0] - 2) + * @{ + */ +#define RIF_ADC_CNTL__VCM_CTRL__SHIFT 12 +#define RIF_ADC_CNTL__VCM_CTRL__WIDTH 2 +#define RIF_ADC_CNTL__VCM_CTRL__MASK 0x00003000U +#define RIF_ADC_CNTL__VCM_CTRL__READ(src) \ + (((uint32_t)(src)\ + & 0x00003000U) >> 12) +#define RIF_ADC_CNTL__VCM_CTRL__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00003000U) +#define RIF_ADC_CNTL__VCM_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((uint32_t)(src) <<\ + 12) & 0x00003000U) +#define RIF_ADC_CNTL__VCM_CTRL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00003000U))) +#define RIF_ADC_CNTL__VCM_CTRL__RESET_VALUE 0x00000002U +/** @} */ +#define RIF_ADC_CNTL__TYPE uint32_t +#define RIF_ADC_CNTL__READ 0x00003fffU +#define RIF_ADC_CNTL__WRITE 0x00003fffU +#define RIF_ADC_CNTL__PRESERVED 0x00000000U +#define RIF_ADC_CNTL__RESET_VALUE 0x00002c81U + +#endif /* __RIF_ADC_CNTL_MACRO__ */ + +/** @} end of adc_cntl */ + +/* macros for BlueprintGlobalNameSpace::RIF_mode_cntl */ +/** + * @defgroup rif_regs_core_mode_cntl mode_cntl + * @brief Radio mode controls definitions. + * @{ + */ +#ifndef __RIF_MODE_CNTL_MACRO__ +#define __RIF_MODE_CNTL_MACRO__ + +/* macros for field tx_power */ +/** + * @defgroup rif_regs_core_tx_power_field tx_power_field + * @brief macros for field tx_power + * @details value in emulation mode or when tx_power_ovr = 1, this is the TX gain table index + * @{ + */ +#define RIF_MODE_CNTL__TX_POWER__SHIFT 0 +#define RIF_MODE_CNTL__TX_POWER__WIDTH 4 +#define RIF_MODE_CNTL__TX_POWER__MASK 0x0000000fU +#define RIF_MODE_CNTL__TX_POWER__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define RIF_MODE_CNTL__TX_POWER__WRITE(src) ((uint32_t)(src) & 0x0000000fU) +#define RIF_MODE_CNTL__TX_POWER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define RIF_MODE_CNTL__TX_POWER__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define RIF_MODE_CNTL__TX_POWER__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tx_power_ovr */ +/** + * @defgroup rif_regs_core_tx_power_ovr_field tx_power_ovr_field + * @brief macros for field tx_power_ovr + * @details override tx_power index value from LC + * @{ + */ +#define RIF_MODE_CNTL__TX_POWER_OVR__SHIFT 4 +#define RIF_MODE_CNTL__TX_POWER_OVR__WIDTH 1 +#define RIF_MODE_CNTL__TX_POWER_OVR__MASK 0x00000010U +#define RIF_MODE_CNTL__TX_POWER_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define RIF_MODE_CNTL__TX_POWER_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define RIF_MODE_CNTL__TX_POWER_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define RIF_MODE_CNTL__TX_POWER_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define RIF_MODE_CNTL__TX_POWER_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define RIF_MODE_CNTL__TX_POWER_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define RIF_MODE_CNTL__TX_POWER_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rxgain */ +/** + * @defgroup rif_regs_core_rxgain_field rxgain_field + * @brief macros for field rxgain + * @details value when rxgain_ovr = 1, this is the RX gain table index + * @{ + */ +#define RIF_MODE_CNTL__RXGAIN__SHIFT 5 +#define RIF_MODE_CNTL__RXGAIN__WIDTH 7 +#define RIF_MODE_CNTL__RXGAIN__MASK 0x00000fe0U +#define RIF_MODE_CNTL__RXGAIN__READ(src) (((uint32_t)(src) & 0x00000fe0U) >> 5) +#define RIF_MODE_CNTL__RXGAIN__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000fe0U) +#define RIF_MODE_CNTL__RXGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fe0U) | (((uint32_t)(src) <<\ + 5) & 0x00000fe0U) +#define RIF_MODE_CNTL__RXGAIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000fe0U))) +#define RIF_MODE_CNTL__RXGAIN__RESET_VALUE 0x0000007fU +/** @} */ + +/* macros for field rxgain_ovr */ +/** + * @defgroup rif_regs_core_rxgain_ovr_field rxgain_ovr_field + * @brief macros for field rxgain_ovr + * @details override rxgain index value from modem + * @{ + */ +#define RIF_MODE_CNTL__RXGAIN_OVR__SHIFT 12 +#define RIF_MODE_CNTL__RXGAIN_OVR__WIDTH 1 +#define RIF_MODE_CNTL__RXGAIN_OVR__MASK 0x00001000U +#define RIF_MODE_CNTL__RXGAIN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define RIF_MODE_CNTL__RXGAIN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define RIF_MODE_CNTL__RXGAIN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define RIF_MODE_CNTL__RXGAIN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define RIF_MODE_CNTL__RXGAIN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define RIF_MODE_CNTL__RXGAIN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define RIF_MODE_CNTL__RXGAIN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field chan_idx */ +/** + * @defgroup rif_regs_core_chan_idx_field chan_idx_field + * @brief macros for field chan_idx + * @details value in emulation mode, TRNG, or when chan_idx_ovr = 1 + * @{ + */ +#define RIF_MODE_CNTL__CHAN_IDX__SHIFT 13 +#define RIF_MODE_CNTL__CHAN_IDX__WIDTH 7 +#define RIF_MODE_CNTL__CHAN_IDX__MASK 0x000fe000U +#define RIF_MODE_CNTL__CHAN_IDX__READ(src) \ + (((uint32_t)(src)\ + & 0x000fe000U) >> 13) +#define RIF_MODE_CNTL__CHAN_IDX__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x000fe000U) +#define RIF_MODE_CNTL__CHAN_IDX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fe000U) | (((uint32_t)(src) <<\ + 13) & 0x000fe000U) +#define RIF_MODE_CNTL__CHAN_IDX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x000fe000U))) +#define RIF_MODE_CNTL__CHAN_IDX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field chan_idx_ovr */ +/** + * @defgroup rif_regs_core_chan_idx_ovr_field chan_idx_ovr_field + * @brief macros for field chan_idx_ovr + * @details override chan_idx value from LC + * @{ + */ +#define RIF_MODE_CNTL__CHAN_IDX_OVR__SHIFT 20 +#define RIF_MODE_CNTL__CHAN_IDX_OVR__WIDTH 1 +#define RIF_MODE_CNTL__CHAN_IDX_OVR__MASK 0x00100000U +#define RIF_MODE_CNTL__CHAN_IDX_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define RIF_MODE_CNTL__CHAN_IDX_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define RIF_MODE_CNTL__CHAN_IDX_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define RIF_MODE_CNTL__CHAN_IDX_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define RIF_MODE_CNTL__CHAN_IDX_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define RIF_MODE_CNTL__CHAN_IDX_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define RIF_MODE_CNTL__CHAN_IDX_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tx_en */ +/** + * @defgroup rif_regs_core_tx_en_field tx_en_field + * @brief macros for field tx_en + * @details value when tx_en_ovr = 1 + * @{ + */ +#define RIF_MODE_CNTL__TX_EN__SHIFT 21 +#define RIF_MODE_CNTL__TX_EN__WIDTH 1 +#define RIF_MODE_CNTL__TX_EN__MASK 0x00200000U +#define RIF_MODE_CNTL__TX_EN__READ(src) (((uint32_t)(src) & 0x00200000U) >> 21) +#define RIF_MODE_CNTL__TX_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x00200000U) +#define RIF_MODE_CNTL__TX_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((uint32_t)(src) <<\ + 21) & 0x00200000U) +#define RIF_MODE_CNTL__TX_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x00200000U))) +#define RIF_MODE_CNTL__TX_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(1) << 21) +#define RIF_MODE_CNTL__TX_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((uint32_t)(0) << 21) +#define RIF_MODE_CNTL__TX_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tx_en_ovr */ +/** + * @defgroup rif_regs_core_tx_en_ovr_field tx_en_ovr_field + * @brief macros for field tx_en_ovr + * @details override tx_en value from LC + * @{ + */ +#define RIF_MODE_CNTL__TX_EN_OVR__SHIFT 22 +#define RIF_MODE_CNTL__TX_EN_OVR__WIDTH 1 +#define RIF_MODE_CNTL__TX_EN_OVR__MASK 0x00400000U +#define RIF_MODE_CNTL__TX_EN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define RIF_MODE_CNTL__TX_EN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define RIF_MODE_CNTL__TX_EN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define RIF_MODE_CNTL__TX_EN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define RIF_MODE_CNTL__TX_EN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define RIF_MODE_CNTL__TX_EN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define RIF_MODE_CNTL__TX_EN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_en */ +/** + * @defgroup rif_regs_core_rx_en_field rx_en_field + * @brief macros for field rx_en + * @details value when rx_en_ovr = 1 + * @{ + */ +#define RIF_MODE_CNTL__RX_EN__SHIFT 23 +#define RIF_MODE_CNTL__RX_EN__WIDTH 1 +#define RIF_MODE_CNTL__RX_EN__MASK 0x00800000U +#define RIF_MODE_CNTL__RX_EN__READ(src) (((uint32_t)(src) & 0x00800000U) >> 23) +#define RIF_MODE_CNTL__RX_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0x00800000U) +#define RIF_MODE_CNTL__RX_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((uint32_t)(src) <<\ + 23) & 0x00800000U) +#define RIF_MODE_CNTL__RX_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0x00800000U))) +#define RIF_MODE_CNTL__RX_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(1) << 23) +#define RIF_MODE_CNTL__RX_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((uint32_t)(0) << 23) +#define RIF_MODE_CNTL__RX_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_en_ovr */ +/** + * @defgroup rif_regs_core_rx_en_ovr_field rx_en_ovr_field + * @brief macros for field rx_en_ovr + * @details override rx_en value from LC + * @{ + */ +#define RIF_MODE_CNTL__RX_EN_OVR__SHIFT 24 +#define RIF_MODE_CNTL__RX_EN_OVR__WIDTH 1 +#define RIF_MODE_CNTL__RX_EN_OVR__MASK 0x01000000U +#define RIF_MODE_CNTL__RX_EN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define RIF_MODE_CNTL__RX_EN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x01000000U) +#define RIF_MODE_CNTL__RX_EN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((uint32_t)(src) <<\ + 24) & 0x01000000U) +#define RIF_MODE_CNTL__RX_EN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x01000000U))) +#define RIF_MODE_CNTL__RX_EN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define RIF_MODE_CNTL__RX_EN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define RIF_MODE_CNTL__RX_EN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field radio_en */ +/** + * @defgroup rif_regs_core_radio_en_field radio_en_field + * @brief macros for field radio_en + * @details value when radio_en_ovr = 1 + * @{ + */ +#define RIF_MODE_CNTL__RADIO_EN__SHIFT 25 +#define RIF_MODE_CNTL__RADIO_EN__WIDTH 1 +#define RIF_MODE_CNTL__RADIO_EN__MASK 0x02000000U +#define RIF_MODE_CNTL__RADIO_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x02000000U) >> 25) +#define RIF_MODE_CNTL__RADIO_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x02000000U) +#define RIF_MODE_CNTL__RADIO_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((uint32_t)(src) <<\ + 25) & 0x02000000U) +#define RIF_MODE_CNTL__RADIO_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x02000000U))) +#define RIF_MODE_CNTL__RADIO_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(1) << 25) +#define RIF_MODE_CNTL__RADIO_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((uint32_t)(0) << 25) +#define RIF_MODE_CNTL__RADIO_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field radio_en_ovr */ +/** + * @defgroup rif_regs_core_radio_en_ovr_field radio_en_ovr_field + * @brief macros for field radio_en_ovr + * @details override radio_en value from LC + * @{ + */ +#define RIF_MODE_CNTL__RADIO_EN_OVR__SHIFT 26 +#define RIF_MODE_CNTL__RADIO_EN_OVR__WIDTH 1 +#define RIF_MODE_CNTL__RADIO_EN_OVR__MASK 0x04000000U +#define RIF_MODE_CNTL__RADIO_EN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x04000000U) >> 26) +#define RIF_MODE_CNTL__RADIO_EN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x04000000U) +#define RIF_MODE_CNTL__RADIO_EN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((uint32_t)(src) <<\ + 26) & 0x04000000U) +#define RIF_MODE_CNTL__RADIO_EN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x04000000U))) +#define RIF_MODE_CNTL__RADIO_EN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(1) << 26) +#define RIF_MODE_CNTL__RADIO_EN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((uint32_t)(0) << 26) +#define RIF_MODE_CNTL__RADIO_EN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field select_ext */ +/** + * @defgroup rif_regs_core_select_ext_field select_ext_field + * @brief macros for field select_ext + * @details Enable external interface for radio emulation/dtop_bypass mode + * @{ + */ +#define RIF_MODE_CNTL__SELECT_EXT__SHIFT 27 +#define RIF_MODE_CNTL__SELECT_EXT__WIDTH 1 +#define RIF_MODE_CNTL__SELECT_EXT__MASK 0x08000000U +#define RIF_MODE_CNTL__SELECT_EXT__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define RIF_MODE_CNTL__SELECT_EXT__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define RIF_MODE_CNTL__SELECT_EXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define RIF_MODE_CNTL__SELECT_EXT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define RIF_MODE_CNTL__SELECT_EXT__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define RIF_MODE_CNTL__SELECT_EXT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define RIF_MODE_CNTL__SELECT_EXT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field interleave_adc_iq */ +/** + * @defgroup rif_regs_core_interleave_adc_iq_field interleave_adc_iq_field + * @brief macros for field interleave_adc_iq + * @details Enable interleaving of ADC I/Q output bits for testing + * @{ + */ +#define RIF_MODE_CNTL__INTERLEAVE_ADC_IQ__SHIFT 28 +#define RIF_MODE_CNTL__INTERLEAVE_ADC_IQ__WIDTH 1 +#define RIF_MODE_CNTL__INTERLEAVE_ADC_IQ__MASK 0x10000000U +#define RIF_MODE_CNTL__INTERLEAVE_ADC_IQ__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define RIF_MODE_CNTL__INTERLEAVE_ADC_IQ__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define RIF_MODE_CNTL__INTERLEAVE_ADC_IQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define RIF_MODE_CNTL__INTERLEAVE_ADC_IQ__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define RIF_MODE_CNTL__INTERLEAVE_ADC_IQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define RIF_MODE_CNTL__INTERLEAVE_ADC_IQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define RIF_MODE_CNTL__INTERLEAVE_ADC_IQ__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adcon */ +/** + * @defgroup rif_regs_core_adcon_field adcon_field + * @brief macros for field adcon + * @details value when adcon_ovr = 1 + * @{ + */ +#define RIF_MODE_CNTL__ADCON__SHIFT 29 +#define RIF_MODE_CNTL__ADCON__WIDTH 1 +#define RIF_MODE_CNTL__ADCON__MASK 0x20000000U +#define RIF_MODE_CNTL__ADCON__READ(src) (((uint32_t)(src) & 0x20000000U) >> 29) +#define RIF_MODE_CNTL__ADCON__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define RIF_MODE_CNTL__ADCON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define RIF_MODE_CNTL__ADCON__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define RIF_MODE_CNTL__ADCON__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define RIF_MODE_CNTL__ADCON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define RIF_MODE_CNTL__ADCON__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field adcon_ovr */ +/** + * @defgroup rif_regs_core_adcon_ovr_field adcon_ovr_field + * @brief macros for field adcon_ovr + * @details override adcon value so ADC bits can be clocked out of RIF, also overrides adcon_early + * @{ + */ +#define RIF_MODE_CNTL__ADCON_OVR__SHIFT 30 +#define RIF_MODE_CNTL__ADCON_OVR__WIDTH 1 +#define RIF_MODE_CNTL__ADCON_OVR__MASK 0x40000000U +#define RIF_MODE_CNTL__ADCON_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define RIF_MODE_CNTL__ADCON_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define RIF_MODE_CNTL__ADCON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define RIF_MODE_CNTL__ADCON_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define RIF_MODE_CNTL__ADCON_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define RIF_MODE_CNTL__ADCON_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define RIF_MODE_CNTL__ADCON_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field flash_suppresses_paon */ +/** + * @defgroup rif_regs_core_flash_suppresses_paon_field flash_suppresses_paon_field + * @brief macros for field flash_suppresses_paon + * @details Should a flash write or erase block paon? + * @{ + */ +#define RIF_MODE_CNTL__FLASH_SUPPRESSES_PAON__SHIFT 31 +#define RIF_MODE_CNTL__FLASH_SUPPRESSES_PAON__WIDTH 1 +#define RIF_MODE_CNTL__FLASH_SUPPRESSES_PAON__MASK 0x80000000U +#define RIF_MODE_CNTL__FLASH_SUPPRESSES_PAON__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define RIF_MODE_CNTL__FLASH_SUPPRESSES_PAON__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define RIF_MODE_CNTL__FLASH_SUPPRESSES_PAON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define RIF_MODE_CNTL__FLASH_SUPPRESSES_PAON__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define RIF_MODE_CNTL__FLASH_SUPPRESSES_PAON__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define RIF_MODE_CNTL__FLASH_SUPPRESSES_PAON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define RIF_MODE_CNTL__FLASH_SUPPRESSES_PAON__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_MODE_CNTL__TYPE uint32_t +#define RIF_MODE_CNTL__READ 0xffffffffU +#define RIF_MODE_CNTL__WRITE 0xffffffffU +#define RIF_MODE_CNTL__PRESERVED 0x00000000U +#define RIF_MODE_CNTL__RESET_VALUE 0x00000fe0U + +#endif /* __RIF_MODE_CNTL_MACRO__ */ + +/** @} end of mode_cntl */ + +/* macros for BlueprintGlobalNameSpace::RIF_mode_cntl2 */ +/** + * @defgroup rif_regs_core_mode_cntl2 mode_cntl2 + * @brief Radio mode controls definitions. + * @{ + */ +#ifndef __RIF_MODE_CNTL2_MACRO__ +#define __RIF_MODE_CNTL2_MACRO__ + +/* macros for field hadm_en */ +/** + * @defgroup rif_regs_core_hadm_en_field hadm_en_field + * @brief macros for field hadm_en + * @details 0: Normal BLE mode. 1: HADM mode + * @{ + */ +#define RIF_MODE_CNTL2__HADM_EN__SHIFT 0 +#define RIF_MODE_CNTL2__HADM_EN__WIDTH 1 +#define RIF_MODE_CNTL2__HADM_EN__MASK 0x00000001U +#define RIF_MODE_CNTL2__HADM_EN__READ(src) ((uint32_t)(src) & 0x00000001U) +#define RIF_MODE_CNTL2__HADM_EN__WRITE(src) ((uint32_t)(src) & 0x00000001U) +#define RIF_MODE_CNTL2__HADM_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define RIF_MODE_CNTL2__HADM_EN__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define RIF_MODE_CNTL2__HADM_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define RIF_MODE_CNTL2__HADM_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define RIF_MODE_CNTL2__HADM_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field full_packet_peakdet */ +/** + * @defgroup rif_regs_core_full_packet_peakdet_field full_packet_peakdet_field + * @brief macros for field full_packet_peakdet + * @details 0: Turn off peakdet after access_address_found, to save power 1: Keep peakdet on for full packet (in case of any phase disturbance if turning off mid-packet) + * @{ + */ +#define RIF_MODE_CNTL2__FULL_PACKET_PEAKDET__SHIFT 1 +#define RIF_MODE_CNTL2__FULL_PACKET_PEAKDET__WIDTH 1 +#define RIF_MODE_CNTL2__FULL_PACKET_PEAKDET__MASK 0x00000002U +#define RIF_MODE_CNTL2__FULL_PACKET_PEAKDET__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define RIF_MODE_CNTL2__FULL_PACKET_PEAKDET__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define RIF_MODE_CNTL2__FULL_PACKET_PEAKDET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define RIF_MODE_CNTL2__FULL_PACKET_PEAKDET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define RIF_MODE_CNTL2__FULL_PACKET_PEAKDET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define RIF_MODE_CNTL2__FULL_PACKET_PEAKDET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define RIF_MODE_CNTL2__FULL_PACKET_PEAKDET__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field force_txon_when_hadm_en */ +/** + * @defgroup rif_regs_core_force_txon_when_hadm_en_field force_txon_when_hadm_en_field + * @brief macros for field force_txon_when_hadm_en + * @details If bit is set, force txon high whenever hadm_en is set + * @{ + */ +#define RIF_MODE_CNTL2__FORCE_TXON_WHEN_HADM_EN__SHIFT 2 +#define RIF_MODE_CNTL2__FORCE_TXON_WHEN_HADM_EN__WIDTH 1 +#define RIF_MODE_CNTL2__FORCE_TXON_WHEN_HADM_EN__MASK 0x00000004U +#define RIF_MODE_CNTL2__FORCE_TXON_WHEN_HADM_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define RIF_MODE_CNTL2__FORCE_TXON_WHEN_HADM_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define RIF_MODE_CNTL2__FORCE_TXON_WHEN_HADM_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define RIF_MODE_CNTL2__FORCE_TXON_WHEN_HADM_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define RIF_MODE_CNTL2__FORCE_TXON_WHEN_HADM_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define RIF_MODE_CNTL2__FORCE_TXON_WHEN_HADM_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define RIF_MODE_CNTL2__FORCE_TXON_WHEN_HADM_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field force_synthon_when_hadm_en */ +/** + * @defgroup rif_regs_core_force_synthon_when_hadm_en_field force_synthon_when_hadm_en_field + * @brief macros for field force_synthon_when_hadm_en + * @details If bit is set, force synthon high whenever hadm_en is set + * @{ + */ +#define RIF_MODE_CNTL2__FORCE_SYNTHON_WHEN_HADM_EN__SHIFT 3 +#define RIF_MODE_CNTL2__FORCE_SYNTHON_WHEN_HADM_EN__WIDTH 1 +#define RIF_MODE_CNTL2__FORCE_SYNTHON_WHEN_HADM_EN__MASK 0x00000008U +#define RIF_MODE_CNTL2__FORCE_SYNTHON_WHEN_HADM_EN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define RIF_MODE_CNTL2__FORCE_SYNTHON_WHEN_HADM_EN__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define RIF_MODE_CNTL2__FORCE_SYNTHON_WHEN_HADM_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define RIF_MODE_CNTL2__FORCE_SYNTHON_WHEN_HADM_EN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define RIF_MODE_CNTL2__FORCE_SYNTHON_WHEN_HADM_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define RIF_MODE_CNTL2__FORCE_SYNTHON_WHEN_HADM_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define RIF_MODE_CNTL2__FORCE_SYNTHON_WHEN_HADM_EN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hadm_synth_bw2 */ +/** + * @defgroup rif_regs_core_hadm_synth_bw2_field hadm_synth_bw2_field + * @brief macros for field hadm_synth_bw2 + * @details In HADM mode, 0 = use 1M synth loop bandwidth, 1 = use 2M synth loop bandwidth, same for TX and RX + * @{ + */ +#define RIF_MODE_CNTL2__HADM_SYNTH_BW2__SHIFT 4 +#define RIF_MODE_CNTL2__HADM_SYNTH_BW2__WIDTH 1 +#define RIF_MODE_CNTL2__HADM_SYNTH_BW2__MASK 0x00000010U +#define RIF_MODE_CNTL2__HADM_SYNTH_BW2__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define RIF_MODE_CNTL2__HADM_SYNTH_BW2__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define RIF_MODE_CNTL2__HADM_SYNTH_BW2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define RIF_MODE_CNTL2__HADM_SYNTH_BW2__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define RIF_MODE_CNTL2__HADM_SYNTH_BW2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define RIF_MODE_CNTL2__HADM_SYNTH_BW2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define RIF_MODE_CNTL2__HADM_SYNTH_BW2__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field pmode */ +/** + * @defgroup rif_regs_core_pmode_field pmode_field + * @brief macros for field pmode + * @details value when pmode_ovr = 1 + * @{ + */ +#define RIF_MODE_CNTL2__PMODE__SHIFT 5 +#define RIF_MODE_CNTL2__PMODE__WIDTH 2 +#define RIF_MODE_CNTL2__PMODE__MASK 0x00000060U +#define RIF_MODE_CNTL2__PMODE__READ(src) (((uint32_t)(src) & 0x00000060U) >> 5) +#define RIF_MODE_CNTL2__PMODE__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000060U) +#define RIF_MODE_CNTL2__PMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000060U) | (((uint32_t)(src) <<\ + 5) & 0x00000060U) +#define RIF_MODE_CNTL2__PMODE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000060U))) +#define RIF_MODE_CNTL2__PMODE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pmode_ovr */ +/** + * @defgroup rif_regs_core_pmode_ovr_field pmode_ovr_field + * @brief macros for field pmode_ovr + * @details ovrride pmode value from modem + * @{ + */ +#define RIF_MODE_CNTL2__PMODE_OVR__SHIFT 7 +#define RIF_MODE_CNTL2__PMODE_OVR__WIDTH 1 +#define RIF_MODE_CNTL2__PMODE_OVR__MASK 0x00000080U +#define RIF_MODE_CNTL2__PMODE_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define RIF_MODE_CNTL2__PMODE_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define RIF_MODE_CNTL2__PMODE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define RIF_MODE_CNTL2__PMODE_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define RIF_MODE_CNTL2__PMODE_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define RIF_MODE_CNTL2__PMODE_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define RIF_MODE_CNTL2__PMODE_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field xpa_thresh */ +/** + * @defgroup rif_regs_core_xpa_thresh_field xpa_thresh_field + * @brief macros for field xpa_thresh + * @details Enable XPA if tx_power from LC is >= xpa_thresh + * @{ + */ +#define RIF_MODE_CNTL2__XPA_THRESH__SHIFT 8 +#define RIF_MODE_CNTL2__XPA_THRESH__WIDTH 4 +#define RIF_MODE_CNTL2__XPA_THRESH__MASK 0x00000f00U +#define RIF_MODE_CNTL2__XPA_THRESH__READ(src) \ + (((uint32_t)(src)\ + & 0x00000f00U) >> 8) +#define RIF_MODE_CNTL2__XPA_THRESH__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000f00U) +#define RIF_MODE_CNTL2__XPA_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((uint32_t)(src) <<\ + 8) & 0x00000f00U) +#define RIF_MODE_CNTL2__XPA_THRESH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000f00U))) +#define RIF_MODE_CNTL2__XPA_THRESH__RESET_VALUE 0x0000000fU +/** @} */ + +/* macros for field dbg_select */ +/** + * @defgroup rif_regs_core_dbg_select_field dbg_select_field + * @brief macros for field dbg_select + * @details 0 = {r_ext_mdm_xlnaon, r_ext_rxgain[6:0]} 1 = {r_ext_tx_data_valid, r_ext_tx_data[6:0]} + * @{ + */ +#define RIF_MODE_CNTL2__DBG_SELECT__SHIFT 12 +#define RIF_MODE_CNTL2__DBG_SELECT__WIDTH 1 +#define RIF_MODE_CNTL2__DBG_SELECT__MASK 0x00001000U +#define RIF_MODE_CNTL2__DBG_SELECT__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define RIF_MODE_CNTL2__DBG_SELECT__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define RIF_MODE_CNTL2__DBG_SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define RIF_MODE_CNTL2__DBG_SELECT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define RIF_MODE_CNTL2__DBG_SELECT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define RIF_MODE_CNTL2__DBG_SELECT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define RIF_MODE_CNTL2__DBG_SELECT__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_MODE_CNTL2__TYPE uint32_t +#define RIF_MODE_CNTL2__READ 0x00001fffU +#define RIF_MODE_CNTL2__WRITE 0x00001fffU +#define RIF_MODE_CNTL2__PRESERVED 0x00000000U +#define RIF_MODE_CNTL2__RESET_VALUE 0x00000f10U + +#endif /* __RIF_MODE_CNTL2_MACRO__ */ + +/** @} end of mode_cntl2 */ + +/* macros for BlueprintGlobalNameSpace::RIF_xlna_xpa_cntl */ +/** + * @defgroup rif_regs_core_xlna_xpa_cntl xlna_xpa_cntl + * @brief External LNA/PA control definitions. + * @{ + */ +#ifndef __RIF_XLNA_XPA_CNTL_MACRO__ +#define __RIF_XLNA_XPA_CNTL_MACRO__ + +/* macros for field idle */ +/** + * @defgroup rif_regs_core_idle_field idle_field + * @brief macros for field idle + * @details No active transmit or receive + * @{ + */ +#define RIF_XLNA_XPA_CNTL__IDLE__SHIFT 0 +#define RIF_XLNA_XPA_CNTL__IDLE__WIDTH 5 +#define RIF_XLNA_XPA_CNTL__IDLE__MASK 0x0000001fU +#define RIF_XLNA_XPA_CNTL__IDLE__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define RIF_XLNA_XPA_CNTL__IDLE__WRITE(src) ((uint32_t)(src) & 0x0000001fU) +#define RIF_XLNA_XPA_CNTL__IDLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define RIF_XLNA_XPA_CNTL__IDLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define RIF_XLNA_XPA_CNTL__IDLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tx_xpa_off */ +/** + * @defgroup rif_regs_core_tx_xpa_off_field tx_xpa_off_field + * @brief macros for field tx_xpa_off + * @details Transmit with XPA off + * @{ + */ +#define RIF_XLNA_XPA_CNTL__TX_XPA_OFF__SHIFT 5 +#define RIF_XLNA_XPA_CNTL__TX_XPA_OFF__WIDTH 5 +#define RIF_XLNA_XPA_CNTL__TX_XPA_OFF__MASK 0x000003e0U +#define RIF_XLNA_XPA_CNTL__TX_XPA_OFF__READ(src) \ + (((uint32_t)(src)\ + & 0x000003e0U) >> 5) +#define RIF_XLNA_XPA_CNTL__TX_XPA_OFF__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x000003e0U) +#define RIF_XLNA_XPA_CNTL__TX_XPA_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((uint32_t)(src) <<\ + 5) & 0x000003e0U) +#define RIF_XLNA_XPA_CNTL__TX_XPA_OFF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000003e0U))) +#define RIF_XLNA_XPA_CNTL__TX_XPA_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tx_xpa_on */ +/** + * @defgroup rif_regs_core_tx_xpa_on_field tx_xpa_on_field + * @brief macros for field tx_xpa_on + * @details Transmit with XPA on + * @{ + */ +#define RIF_XLNA_XPA_CNTL__TX_XPA_ON__SHIFT 10 +#define RIF_XLNA_XPA_CNTL__TX_XPA_ON__WIDTH 5 +#define RIF_XLNA_XPA_CNTL__TX_XPA_ON__MASK 0x00007c00U +#define RIF_XLNA_XPA_CNTL__TX_XPA_ON__READ(src) \ + (((uint32_t)(src)\ + & 0x00007c00U) >> 10) +#define RIF_XLNA_XPA_CNTL__TX_XPA_ON__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00007c00U) +#define RIF_XLNA_XPA_CNTL__TX_XPA_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((uint32_t)(src) <<\ + 10) & 0x00007c00U) +#define RIF_XLNA_XPA_CNTL__TX_XPA_ON__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00007c00U))) +#define RIF_XLNA_XPA_CNTL__TX_XPA_ON__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_xlna_off */ +/** + * @defgroup rif_regs_core_rx_xlna_off_field rx_xlna_off_field + * @brief macros for field rx_xlna_off + * @details Receive with XLNA off + * @{ + */ +#define RIF_XLNA_XPA_CNTL__RX_XLNA_OFF__SHIFT 15 +#define RIF_XLNA_XPA_CNTL__RX_XLNA_OFF__WIDTH 5 +#define RIF_XLNA_XPA_CNTL__RX_XLNA_OFF__MASK 0x000f8000U +#define RIF_XLNA_XPA_CNTL__RX_XLNA_OFF__READ(src) \ + (((uint32_t)(src)\ + & 0x000f8000U) >> 15) +#define RIF_XLNA_XPA_CNTL__RX_XLNA_OFF__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x000f8000U) +#define RIF_XLNA_XPA_CNTL__RX_XLNA_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((uint32_t)(src) <<\ + 15) & 0x000f8000U) +#define RIF_XLNA_XPA_CNTL__RX_XLNA_OFF__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x000f8000U))) +#define RIF_XLNA_XPA_CNTL__RX_XLNA_OFF__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_xlna_on */ +/** + * @defgroup rif_regs_core_rx_xlna_on_field rx_xlna_on_field + * @brief macros for field rx_xlna_on + * @details Receive with XLNA on + * @{ + */ +#define RIF_XLNA_XPA_CNTL__RX_XLNA_ON__SHIFT 20 +#define RIF_XLNA_XPA_CNTL__RX_XLNA_ON__WIDTH 5 +#define RIF_XLNA_XPA_CNTL__RX_XLNA_ON__MASK 0x01f00000U +#define RIF_XLNA_XPA_CNTL__RX_XLNA_ON__READ(src) \ + (((uint32_t)(src)\ + & 0x01f00000U) >> 20) +#define RIF_XLNA_XPA_CNTL__RX_XLNA_ON__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x01f00000U) +#define RIF_XLNA_XPA_CNTL__RX_XLNA_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((uint32_t)(src) <<\ + 20) & 0x01f00000U) +#define RIF_XLNA_XPA_CNTL__RX_XLNA_ON__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x01f00000U))) +#define RIF_XLNA_XPA_CNTL__RX_XLNA_ON__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rx_cal */ +/** + * @defgroup rif_regs_core_rx_cal_field rx_cal_field + * @brief macros for field rx_cal + * @details Receiver calibration. Expect to program the same as rx_xlna_off + * @{ + */ +#define RIF_XLNA_XPA_CNTL__RX_CAL__SHIFT 25 +#define RIF_XLNA_XPA_CNTL__RX_CAL__WIDTH 5 +#define RIF_XLNA_XPA_CNTL__RX_CAL__MASK 0x3e000000U +#define RIF_XLNA_XPA_CNTL__RX_CAL__READ(src) \ + (((uint32_t)(src)\ + & 0x3e000000U) >> 25) +#define RIF_XLNA_XPA_CNTL__RX_CAL__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x3e000000U) +#define RIF_XLNA_XPA_CNTL__RX_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((uint32_t)(src) <<\ + 25) & 0x3e000000U) +#define RIF_XLNA_XPA_CNTL__RX_CAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x3e000000U))) +#define RIF_XLNA_XPA_CNTL__RX_CAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field register_outputs */ +/** + * @defgroup rif_regs_core_register_outputs_field register_outputs_field + * @brief macros for field register_outputs + * @details To prevent possible glitching (for example XPA control during RX) register outputs before driving to pins + * @{ + */ +#define RIF_XLNA_XPA_CNTL__REGISTER_OUTPUTS__SHIFT 30 +#define RIF_XLNA_XPA_CNTL__REGISTER_OUTPUTS__WIDTH 1 +#define RIF_XLNA_XPA_CNTL__REGISTER_OUTPUTS__MASK 0x40000000U +#define RIF_XLNA_XPA_CNTL__REGISTER_OUTPUTS__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define RIF_XLNA_XPA_CNTL__REGISTER_OUTPUTS__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define RIF_XLNA_XPA_CNTL__REGISTER_OUTPUTS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define RIF_XLNA_XPA_CNTL__REGISTER_OUTPUTS__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define RIF_XLNA_XPA_CNTL__REGISTER_OUTPUTS__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define RIF_XLNA_XPA_CNTL__REGISTER_OUTPUTS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define RIF_XLNA_XPA_CNTL__REGISTER_OUTPUTS__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_XLNA_XPA_CNTL__TYPE uint32_t +#define RIF_XLNA_XPA_CNTL__READ 0x7fffffffU +#define RIF_XLNA_XPA_CNTL__WRITE 0x7fffffffU +#define RIF_XLNA_XPA_CNTL__PRESERVED 0x00000000U +#define RIF_XLNA_XPA_CNTL__RESET_VALUE 0x00000000U + +#endif /* __RIF_XLNA_XPA_CNTL_MACRO__ */ + +/** @} end of xlna_xpa_cntl */ + +/* macros for BlueprintGlobalNameSpace::RIF_cal_cntl */ +/** + * @defgroup rif_regs_core_cal_cntl cal_cntl + * @brief Radio calibration signals definitions. + * @{ + */ +#ifndef __RIF_CAL_CNTL_MACRO__ +#define __RIF_CAL_CNTL_MACRO__ + +/* macros for field caltx */ +/** + * @defgroup rif_regs_core_caltx_field caltx_field + * @brief macros for field caltx + * @details Set to 1 to configure radio for synth cals, MSB is modgain, LSB is vcocap + * @{ + */ +#define RIF_CAL_CNTL__CALTX__SHIFT 0 +#define RIF_CAL_CNTL__CALTX__WIDTH 2 +#define RIF_CAL_CNTL__CALTX__MASK 0x00000003U +#define RIF_CAL_CNTL__CALTX__READ(src) ((uint32_t)(src) & 0x00000003U) +#define RIF_CAL_CNTL__CALTX__WRITE(src) ((uint32_t)(src) & 0x00000003U) +#define RIF_CAL_CNTL__CALTX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define RIF_CAL_CNTL__CALTX__VERIFY(src) (!(((uint32_t)(src) & ~0x00000003U))) +#define RIF_CAL_CNTL__CALTX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field calrx */ +/** + * @defgroup rif_regs_core_calrx_field calrx_field + * @brief macros for field calrx + * @details Reserved for any other RX calibration modes (also used for TRNG) + * @{ + */ +#define RIF_CAL_CNTL__CALRX__SHIFT 2 +#define RIF_CAL_CNTL__CALRX__WIDTH 1 +#define RIF_CAL_CNTL__CALRX__MASK 0x00000004U +#define RIF_CAL_CNTL__CALRX__READ(src) (((uint32_t)(src) & 0x00000004U) >> 2) +#define RIF_CAL_CNTL__CALRX__WRITE(src) (((uint32_t)(src) << 2) & 0x00000004U) +#define RIF_CAL_CNTL__CALRX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define RIF_CAL_CNTL__CALRX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define RIF_CAL_CNTL__CALRX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define RIF_CAL_CNTL__CALRX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define RIF_CAL_CNTL__CALRX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field caldc */ +/** + * @defgroup rif_regs_core_caldc_field caldc_field + * @brief macros for field caldc + * @details Set to 1 to configure radio for RX DC offset cal, MSB is TIA, LSB is PGA + * @{ + */ +#define RIF_CAL_CNTL__CALDC__SHIFT 3 +#define RIF_CAL_CNTL__CALDC__WIDTH 2 +#define RIF_CAL_CNTL__CALDC__MASK 0x00000018U +#define RIF_CAL_CNTL__CALDC__READ(src) (((uint32_t)(src) & 0x00000018U) >> 3) +#define RIF_CAL_CNTL__CALDC__WRITE(src) (((uint32_t)(src) << 3) & 0x00000018U) +#define RIF_CAL_CNTL__CALDC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000018U) | (((uint32_t)(src) <<\ + 3) & 0x00000018U) +#define RIF_CAL_CNTL__CALDC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000018U))) +#define RIF_CAL_CNTL__CALDC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field calfc */ +/** + * @defgroup rif_regs_core_calfc_field calfc_field + * @brief macros for field calfc + * @details Set to 1 to configure radio for RXBB filter BW cal, MSB is TIA, LSB is PGA + * @{ + */ +#define RIF_CAL_CNTL__CALFC__SHIFT 5 +#define RIF_CAL_CNTL__CALFC__WIDTH 2 +#define RIF_CAL_CNTL__CALFC__MASK 0x00000060U +#define RIF_CAL_CNTL__CALFC__READ(src) (((uint32_t)(src) & 0x00000060U) >> 5) +#define RIF_CAL_CNTL__CALFC__WRITE(src) (((uint32_t)(src) << 5) & 0x00000060U) +#define RIF_CAL_CNTL__CALFC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000060U) | (((uint32_t)(src) <<\ + 5) & 0x00000060U) +#define RIF_CAL_CNTL__CALFC__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000060U))) +#define RIF_CAL_CNTL__CALFC__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field caltx_chan_idx */ +/** + * @defgroup rif_regs_core_caltx_chan_idx_field caltx_chan_idx_field + * @brief macros for field caltx_chan_idx + * @details chan_idx value during modgain cal + * @{ + */ +#define RIF_CAL_CNTL__CALTX_CHAN_IDX__SHIFT 7 +#define RIF_CAL_CNTL__CALTX_CHAN_IDX__WIDTH 7 +#define RIF_CAL_CNTL__CALTX_CHAN_IDX__MASK 0x00003f80U +#define RIF_CAL_CNTL__CALTX_CHAN_IDX__READ(src) \ + (((uint32_t)(src)\ + & 0x00003f80U) >> 7) +#define RIF_CAL_CNTL__CALTX_CHAN_IDX__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00003f80U) +#define RIF_CAL_CNTL__CALTX_CHAN_IDX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((uint32_t)(src) <<\ + 7) & 0x00003f80U) +#define RIF_CAL_CNTL__CALTX_CHAN_IDX__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00003f80U))) +#define RIF_CAL_CNTL__CALTX_CHAN_IDX__RESET_VALUE 0x00000026U +/** @} */ +#define RIF_CAL_CNTL__TYPE uint32_t +#define RIF_CAL_CNTL__READ 0x00003fffU +#define RIF_CAL_CNTL__WRITE 0x00003fffU +#define RIF_CAL_CNTL__PRESERVED 0x00000000U +#define RIF_CAL_CNTL__RESET_VALUE 0x00001300U + +#endif /* __RIF_CAL_CNTL_MACRO__ */ + +/** @} end of cal_cntl */ + +/* macros for BlueprintGlobalNameSpace::RIF_cal_done */ +/** + * @defgroup rif_regs_core_cal_done cal_done + * @brief Synth/TX calibration done indicator definitions. + * @{ + */ +#ifndef __RIF_CAL_DONE_MACRO__ +#define __RIF_CAL_DONE_MACRO__ + +/* macros for field caltx_done */ +/** + * @defgroup rif_regs_core_caltx_done_field caltx_done_field + * @brief macros for field caltx_done + * @details Indicates calibration is finished, MSB is modgain, LSB is vcocap + * @{ + */ +#define RIF_CAL_DONE__CALTX_DONE__SHIFT 0 +#define RIF_CAL_DONE__CALTX_DONE__WIDTH 2 +#define RIF_CAL_DONE__CALTX_DONE__MASK 0x00000003U +#define RIF_CAL_DONE__CALTX_DONE__READ(src) ((uint32_t)(src) & 0x00000003U) +#define RIF_CAL_DONE__CALTX_DONE__RESET_VALUE 0x00000000U +/** @} */ +#define RIF_CAL_DONE__TYPE uint32_t +#define RIF_CAL_DONE__READ 0x00000003U +#define RIF_CAL_DONE__PRESERVED 0x00000000U +#define RIF_CAL_DONE__RESET_VALUE 0x00000000U + +#endif /* __RIF_CAL_DONE_MACRO__ */ + +/** @} end of cal_done */ + +/* macros for BlueprintGlobalNameSpace::RIF_id */ +/** + * @defgroup rif_regs_core_id id + * @brief Core ID definitions. + * @{ + */ +#ifndef __RIF_ID_MACRO__ +#define __RIF_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup rif_regs_core_id_field id_field + * @brief macros for field id + * @details RIF+space in ASCII + * @{ + */ +#define RIF_ID__ID__SHIFT 0 +#define RIF_ID__ID__WIDTH 32 +#define RIF_ID__ID__MASK 0xffffffffU +#define RIF_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define RIF_ID__ID__RESET_VALUE 0x52494620U +/** @} */ +#define RIF_ID__TYPE uint32_t +#define RIF_ID__READ 0xffffffffU +#define RIF_ID__PRESERVED 0x00000000U +#define RIF_ID__RESET_VALUE 0x52494620U + +#endif /* __RIF_ID_MACRO__ */ + +/** @} end of id */ + +/** @} end of RIF_REGS_CORE */ +#endif /* __REG_RIF_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/rram.h b/ATM33xx-5/include/reg/rram.h new file mode 100644 index 0000000..5f614bf --- /dev/null +++ b/ATM33xx-5/include/reg/rram.h @@ -0,0 +1,130 @@ +/** + ****************************************************************************** + * + * @file rram.h + * + * @brief RRAM register access + * + * Copyright (C) Atmosic 2020-2023 + * + ****************************************************************************** + */ + +#pragma once + +#include +#include +#include "at_ahb_prrf_regs_core_macro.h" +#include "at_apb_wrpr_pins_regs_core_macro.h" + +typedef enum { + RRAM_R_TEST = 0x00, + RRAM_R_CLK_INFO = 0x16, + RRAM_R_WRITE_ADJ = 0x18, + RRAM_R_CMD2YE = 0x1c, +} RRAM_R_Enum; + +#define RRAM_R_BASE_ADDR 0x00090000U + +#define RRAM_R_TEST__TEST_MODE__SHIFT 0 +#define RRAM_R_TEST__TEST_MODE__MASK 0x0000000001ULL + +#define RRAM_R_CLK_INFO__LVEN_READ_CYC__SHIFT 26 +#define RRAM_R_CLK_INFO__LVEN_READ_CYC__MASK 0x003c000000ULL +#define RRAM_R_CLK_INFO__MARGIN_READ_CYC__SHIFT 18 +#define RRAM_R_CLK_INFO__MARGIN_READ_CYC__MASK 0x0003fc0000ULL +#define RRAM_R_CLK_INFO__READ_CYC__SHIFT 14 +#define RRAM_R_CLK_INFO__READ_CYC__MASK 0x000003c000ULL +#define RRAM_R_CLK_INFO__US_UNIT__SHIFT 0 +#define RRAM_R_CLK_INFO__US_UNIT__MASK 0x00000003ffULL +#define RRAM_R_CLK_INFO__NS100_UNIT__SHIFT 10 +#define RRAM_R_CLK_INFO__NS100_UNIT__MASK 0x0000003c00ULL + +#define RRAM_R_WRITE_ADJ__SU_AD_YE__SHIFT 0 +#define RRAM_R_WRITE_ADJ__SU_AD_YE__MASK 0x000000007FULL + +#define RRAM_READ_NS 58 +#define RRAM_LVEN_READ_NS 63 +#define RRAM_SU_CMD_YE 5000 + +#ifndef __RRAM_STATIC_INLINE +#define __RRAM_STATIC_INLINE __STATIC_INLINE +#endif + +__RRAM_STATIC_INLINE uint64_t +rram_reg_read(RRAM_R_Enum reg) +{ + *(volatile uint32_t *)(RRAM_R_BASE_ADDR + (reg << 1)); + uint32_t lo = CMSDK_AT_PRRF_NONSECURE->RRAM_READ_CONFIG_LO; + uint32_t hi = CMSDK_AT_PRRF_NONSECURE->RRAM_READ_CONFIG_HI; + return ((((uint64_t)hi) << 32) | lo); +} + +__RRAM_STATIC_INLINE void +rram_reg_write(RRAM_R_Enum reg, uint64_t val) +{ + CMSDK_AT_PRRF_NONSECURE->RRAM_WRT_CONFIG_LO = val & 0xffffffff; + CMSDK_AT_PRRF_NONSECURE->RRAM_WRT_CONFIG_HI = val >> 32; + *(volatile uint32_t *)(RRAM_R_BASE_ADDR + (reg << 1)) = 0; +} + +__RRAM_STATIC_INLINE uint32_t +rram_calc_cmd2ye(uint16_t us_unit) +{ + uint32_t r_write_adj = rram_reg_read(RRAM_R_WRITE_ADJ) & + RRAM_R_WRITE_ADJ__SU_AD_YE__MASK; + return ((RRAM_SU_CMD_YE * us_unit) / 1000) - (3 + r_write_adj) + 1; +} + +__RRAM_STATIC_INLINE void +rram_adjust_timing(uint16_t us_unit) +{ + // Adjust RRAM timing + uint8_t ns100_unit = ((us_unit - 1) / 10) + 1; + if (ns100_unit < 2) { + ns100_unit = 2; + } + uint8_t read_cyc = ((us_unit * RRAM_READ_NS) - 1) / 1000; + uint8_t lven_cyc = ((us_unit * RRAM_LVEN_READ_NS) - 1) / 1000; + uint8_t margin_cyc = (lven_cyc < 4) ? 4 : lven_cyc; + uint32_t r_cmd2ye = rram_calc_cmd2ye(us_unit); + + uint64_t r_clk_info = rram_reg_read(RRAM_R_CLK_INFO); + r_clk_info = (r_clk_info & + ~(RRAM_R_CLK_INFO__LVEN_READ_CYC__MASK | + RRAM_R_CLK_INFO__MARGIN_READ_CYC__MASK | + RRAM_R_CLK_INFO__READ_CYC__MASK | + RRAM_R_CLK_INFO__NS100_UNIT__MASK | RRAM_R_CLK_INFO__US_UNIT__MASK)) + | (((uint64_t)lven_cyc) << RRAM_R_CLK_INFO__LVEN_READ_CYC__SHIFT) + | (((uint64_t)margin_cyc) << RRAM_R_CLK_INFO__MARGIN_READ_CYC__SHIFT) + | (((uint64_t)read_cyc) << RRAM_R_CLK_INFO__READ_CYC__SHIFT) + | (((uint64_t)ns100_unit) << RRAM_R_CLK_INFO__NS100_UNIT__SHIFT) + | (((uint64_t)us_unit) << RRAM_R_CLK_INFO__US_UNIT__SHIFT); + + // Unlock test mode registers + rram_reg_write(RRAM_R_TEST, RRAM_R_TEST__TEST_MODE__MASK); + { + rram_reg_write(RRAM_R_CLK_INFO, r_clk_info); + rram_reg_write(RRAM_R_CMD2YE, r_cmd2ye); + } + // Lock test mode registers + rram_reg_write(RRAM_R_TEST, 0); +} + +__RRAM_STATIC_INLINE void +rram_enable_cache(void) +{ + CMSDK_AT_PRRF_NONSECURE->RRAM_CACHE_CONFIG = + AT_PRRF_RRAM_CACHE_CONFIG__INVALIDATE_CACHE__MASK; + CMSDK_AT_PRRF_NONSECURE->RRAM_CACHE_CONFIG = + AT_PRRF_RRAM_CACHE_CONFIG__ENABLE_CACHE__MASK | + AT_PRRF_RRAM_CACHE_CONFIG__CACHE_MODE__MASK; +} + +__RRAM_STATIC_INLINE void +rram_disable_cache(void) +{ + CMSDK_AT_PRRF_NONSECURE->RRAM_CACHE_CONFIG = + AT_PRRF_RRAM_CACHE_CONFIG__CACHE_MODE__MASK; + // don't worry about invalidate; that's done by rram_enale_cache +} diff --git a/ATM33xx-5/include/reg/swreg_aon_regs_core_macro.h b/ATM33xx-5/include/reg/swreg_aon_regs_core_macro.h new file mode 100644 index 0000000..69ee55a --- /dev/null +++ b/ATM33xx-5/include/reg/swreg_aon_regs_core_macro.h @@ -0,0 +1,2175 @@ +/* */ +/* File: swreg_aon_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic swreg_aon_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_SWREG_AON_REGS_CORE_H__ +#define __REG_SWREG_AON_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup SWREG_AON_REGS_CORE swreg_aon_regs_core + * @ingroup AT_REG + * @brief swreg_aon_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::SWREG_AON_aon0 */ +/** + * @defgroup swreg_aon_regs_core_aon0 aon0 + * @brief swreg aon regs For fields that refer to the FSMs the order is: 3: None 2: Main 1: Simple 0: Tiny For fields that refer to the sources the order is: 2: Battery 1: Store 0: Harvester For fields that refer to the destinations the order is: 4: Store 3: AVDD 2: VDDIO 1: VDDAUX 0: DVDD For fields that refer to the supplies the order is: 4: Store 3: AVDD 2: VDDIO 1: VDDAUX 0: DVDD definitions. + * @{ + */ +#ifndef __SWREG_AON_AON0_MACRO__ +#define __SWREG_AON_AON0_MACRO__ + +/* macros for field clkFixedMain_SH */ +/** + * @defgroup swreg_aon_regs_core_clkFixedMain_SH_field clkFixedMain_SH_field + * @brief macros for field clkFixedMain_SH + * @details fixed time for the clock of the main FSM (shadowed in main) + * @{ + */ +#define SWREG_AON_AON0__CLKFIXEDMAIN_SH__SHIFT 0 +#define SWREG_AON_AON0__CLKFIXEDMAIN_SH__WIDTH 4 +#define SWREG_AON_AON0__CLKFIXEDMAIN_SH__MASK 0x0000000fU +#define SWREG_AON_AON0__CLKFIXEDMAIN_SH__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define SWREG_AON_AON0__CLKFIXEDMAIN_SH__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define SWREG_AON_AON0__CLKFIXEDMAIN_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define SWREG_AON_AON0__CLKFIXEDMAIN_SH__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define SWREG_AON_AON0__CLKFIXEDMAIN_SH__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field clkFixedSimple_SH */ +/** + * @defgroup swreg_aon_regs_core_clkFixedSimple_SH_field clkFixedSimple_SH_field + * @brief macros for field clkFixedSimple_SH + * @details fixed time for the clock of the simple FSM (shadowed in simple) + * @{ + */ +#define SWREG_AON_AON0__CLKFIXEDSIMPLE_SH__SHIFT 4 +#define SWREG_AON_AON0__CLKFIXEDSIMPLE_SH__WIDTH 4 +#define SWREG_AON_AON0__CLKFIXEDSIMPLE_SH__MASK 0x000000f0U +#define SWREG_AON_AON0__CLKFIXEDSIMPLE_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define SWREG_AON_AON0__CLKFIXEDSIMPLE_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x000000f0U) +#define SWREG_AON_AON0__CLKFIXEDSIMPLE_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define SWREG_AON_AON0__CLKFIXEDSIMPLE_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define SWREG_AON_AON0__CLKFIXEDSIMPLE_SH__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field clkFixedTiny_SH */ +/** + * @defgroup swreg_aon_regs_core_clkFixedTiny_SH_field clkFixedTiny_SH_field + * @brief macros for field clkFixedTiny_SH + * @details fixed time for the clock of the tiny FSM (shadowed in aon) + * @{ + */ +#define SWREG_AON_AON0__CLKFIXEDTINY_SH__SHIFT 8 +#define SWREG_AON_AON0__CLKFIXEDTINY_SH__WIDTH 4 +#define SWREG_AON_AON0__CLKFIXEDTINY_SH__MASK 0x00000f00U +#define SWREG_AON_AON0__CLKFIXEDTINY_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00000f00U) >> 8) +#define SWREG_AON_AON0__CLKFIXEDTINY_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000f00U) +#define SWREG_AON_AON0__CLKFIXEDTINY_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((uint32_t)(src) <<\ + 8) & 0x00000f00U) +#define SWREG_AON_AON0__CLKFIXEDTINY_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000f00U))) +#define SWREG_AON_AON0__CLKFIXEDTINY_SH__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field skipSample_SH */ +/** + * @defgroup swreg_aon_regs_core_skipSample_SH_field skipSample_SH_field + * @brief macros for field skipSample_SH + * @details skip the sample state after dump. A sample state allows more time for the request comparators to respond. (shadowed in simple and main) + * @{ + */ +#define SWREG_AON_AON0__SKIPSAMPLE_SH__SHIFT 12 +#define SWREG_AON_AON0__SKIPSAMPLE_SH__WIDTH 1 +#define SWREG_AON_AON0__SKIPSAMPLE_SH__MASK 0x00001000U +#define SWREG_AON_AON0__SKIPSAMPLE_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define SWREG_AON_AON0__SKIPSAMPLE_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define SWREG_AON_AON0__SKIPSAMPLE_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define SWREG_AON_AON0__SKIPSAMPLE_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define SWREG_AON_AON0__SKIPSAMPLE_SH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define SWREG_AON_AON0__SKIPSAMPLE_SH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define SWREG_AON_AON0__SKIPSAMPLE_SH__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field timeStepSettleTarget_SH */ +/** + * @defgroup swreg_aon_regs_core_timeStepSettleTarget_SH_field timeStepSettleTarget_SH_field + * @brief macros for field timeStepSettleTarget_SH + * @details step size used for the settling targets (0 is step of 1) (shadowed in simple and main) + * @{ + */ +#define SWREG_AON_AON0__TIMESTEPSETTLETARGET_SH__SHIFT 13 +#define SWREG_AON_AON0__TIMESTEPSETTLETARGET_SH__WIDTH 3 +#define SWREG_AON_AON0__TIMESTEPSETTLETARGET_SH__MASK 0x0000e000U +#define SWREG_AON_AON0__TIMESTEPSETTLETARGET_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x0000e000U) >> 13) +#define SWREG_AON_AON0__TIMESTEPSETTLETARGET_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0000e000U) +#define SWREG_AON_AON0__TIMESTEPSETTLETARGET_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((uint32_t)(src) <<\ + 13) & 0x0000e000U) +#define SWREG_AON_AON0__TIMESTEPSETTLETARGET_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0000e000U))) +#define SWREG_AON_AON0__TIMESTEPSETTLETARGET_SH__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field timeStepStepUp_SH */ +/** + * @defgroup swreg_aon_regs_core_timeStepStepUp_SH_field timeStepStepUp_SH_field + * @brief macros for field timeStepStepUp_SH + * @details step with which the timestep increases when the ZCD result is repeatedly negative (the supply discharges). 0 corresponds to step of 1 (shadowed in simple and main) + * @{ + */ +#define SWREG_AON_AON0__TIMESTEPSTEPUP_SH__SHIFT 16 +#define SWREG_AON_AON0__TIMESTEPSTEPUP_SH__WIDTH 3 +#define SWREG_AON_AON0__TIMESTEPSTEPUP_SH__MASK 0x00070000U +#define SWREG_AON_AON0__TIMESTEPSTEPUP_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00070000U) >> 16) +#define SWREG_AON_AON0__TIMESTEPSTEPUP_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00070000U) +#define SWREG_AON_AON0__TIMESTEPSTEPUP_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((uint32_t)(src) <<\ + 16) & 0x00070000U) +#define SWREG_AON_AON0__TIMESTEPSTEPUP_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00070000U))) +#define SWREG_AON_AON0__TIMESTEPSTEPUP_SH__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field timeStepStepDn_SH */ +/** + * @defgroup swreg_aon_regs_core_timeStepStepDn_SH_field timeStepStepDn_SH_field + * @brief macros for field timeStepStepDn_SH + * @details step with which the timestep decreases, or increases when ZCD result is repeatedly positive. 0 corresponds to step of 1 (shadowed in simple and main) + * @{ + */ +#define SWREG_AON_AON0__TIMESTEPSTEPDN_SH__SHIFT 19 +#define SWREG_AON_AON0__TIMESTEPSTEPDN_SH__WIDTH 3 +#define SWREG_AON_AON0__TIMESTEPSTEPDN_SH__MASK 0x00380000U +#define SWREG_AON_AON0__TIMESTEPSTEPDN_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00380000U) >> 19) +#define SWREG_AON_AON0__TIMESTEPSTEPDN_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00380000U) +#define SWREG_AON_AON0__TIMESTEPSTEPDN_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00380000U) | (((uint32_t)(src) <<\ + 19) & 0x00380000U) +#define SWREG_AON_AON0__TIMESTEPSTEPDN_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00380000U))) +#define SWREG_AON_AON0__TIMESTEPSTEPDN_SH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field timeAfterDump_SH */ +/** + * @defgroup swreg_aon_regs_core_timeAfterDump_SH_field timeAfterDump_SH_field + * @brief macros for field timeAfterDump_SH + * @details length of state after dump. The remaining inductor current is dissipated during this state (x4+3) (shadowed in simple and main and used directly in tiny) + * @{ + */ +#define SWREG_AON_AON0__TIMEAFTERDUMP_SH__SHIFT 22 +#define SWREG_AON_AON0__TIMEAFTERDUMP_SH__WIDTH 4 +#define SWREG_AON_AON0__TIMEAFTERDUMP_SH__MASK 0x03c00000U +#define SWREG_AON_AON0__TIMEAFTERDUMP_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x03c00000U) >> 22) +#define SWREG_AON_AON0__TIMEAFTERDUMP_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x03c00000U) +#define SWREG_AON_AON0__TIMEAFTERDUMP_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03c00000U) | (((uint32_t)(src) <<\ + 22) & 0x03c00000U) +#define SWREG_AON_AON0__TIMEAFTERDUMP_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x03c00000U))) +#define SWREG_AON_AON0__TIMEAFTERDUMP_SH__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field indCurrentHistoryLength_SH */ +/** + * @defgroup swreg_aon_regs_core_indCurrentHistoryLength_SH_field indCurrentHistoryLength_SH_field + * @brief macros for field indCurrentHistoryLength_SH + * @details length of inductor current history, max is 2 (n means acting after the inductor current sign is the same n+2 times) (shadowed in simple and main) + * @{ + */ +#define SWREG_AON_AON0__INDCURRENTHISTORYLENGTH_SH__SHIFT 26 +#define SWREG_AON_AON0__INDCURRENTHISTORYLENGTH_SH__WIDTH 2 +#define SWREG_AON_AON0__INDCURRENTHISTORYLENGTH_SH__MASK 0x0c000000U +#define SWREG_AON_AON0__INDCURRENTHISTORYLENGTH_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x0c000000U) >> 26) +#define SWREG_AON_AON0__INDCURRENTHISTORYLENGTH_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x0c000000U) +#define SWREG_AON_AON0__INDCURRENTHISTORYLENGTH_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((uint32_t)(src) <<\ + 26) & 0x0c000000U) +#define SWREG_AON_AON0__INDCURRENTHISTORYLENGTH_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x0c000000U))) +#define SWREG_AON_AON0__INDCURRENTHISTORYLENGTH_SH__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field enableHarv2SupFirst_SH */ +/** + * @defgroup swreg_aon_regs_core_enableHarv2SupFirst_SH_field enableHarv2SupFirst_SH_field + * @brief macros for field enableHarv2SupFirst_SH + * @details enables the use of the harvester as a source before the battery and the store. If set to zero but enableHarv2Sup=1 the harvest is used as a source if the battery and store are not available. must be set for mppt if enableHarv2Sup=1(shadowed in simple and main) + * @{ + */ +#define SWREG_AON_AON0__ENABLEHARV2SUPFIRST_SH__SHIFT 28 +#define SWREG_AON_AON0__ENABLEHARV2SUPFIRST_SH__WIDTH 1 +#define SWREG_AON_AON0__ENABLEHARV2SUPFIRST_SH__MASK 0x10000000U +#define SWREG_AON_AON0__ENABLEHARV2SUPFIRST_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define SWREG_AON_AON0__ENABLEHARV2SUPFIRST_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define SWREG_AON_AON0__ENABLEHARV2SUPFIRST_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define SWREG_AON_AON0__ENABLEHARV2SUPFIRST_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define SWREG_AON_AON0__ENABLEHARV2SUPFIRST_SH__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define SWREG_AON_AON0__ENABLEHARV2SUPFIRST_SH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define SWREG_AON_AON0__ENABLEHARV2SUPFIRST_SH__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field mpptFullSettling_SH */ +/** + * @defgroup swreg_aon_regs_core_mpptFullSettling_SH_field mpptFullSettling_SH_field + * @brief macros for field mpptFullSettling_SH + * @details wait for full dump time settling, before starting counting switching events for mppt. Normally this should not be necessary (shadowed in simple and main) + * @{ + */ +#define SWREG_AON_AON0__MPPTFULLSETTLING_SH__SHIFT 29 +#define SWREG_AON_AON0__MPPTFULLSETTLING_SH__WIDTH 1 +#define SWREG_AON_AON0__MPPTFULLSETTLING_SH__MASK 0x20000000U +#define SWREG_AON_AON0__MPPTFULLSETTLING_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define SWREG_AON_AON0__MPPTFULLSETTLING_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define SWREG_AON_AON0__MPPTFULLSETTLING_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define SWREG_AON_AON0__MPPTFULLSETTLING_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define SWREG_AON_AON0__MPPTFULLSETTLING_SH__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define SWREG_AON_AON0__MPPTFULLSETTLING_SH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define SWREG_AON_AON0__MPPTFULLSETTLING_SH__RESET_VALUE 0x00000000U +/** @} */ +#define SWREG_AON_AON0__TYPE uint32_t +#define SWREG_AON_AON0__READ 0x3fffffffU +#define SWREG_AON_AON0__WRITE 0x3fffffffU +#define SWREG_AON_AON0__PRESERVED 0x00000000U +#define SWREG_AON_AON0__RESET_VALUE 0x18433663U + +#endif /* __SWREG_AON_AON0_MACRO__ */ + +/** @} end of aon0 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_AON_aon1 */ +/** + * @defgroup swreg_aon_regs_core_aon1 aon1 + * @brief swreg aon regs definitions. + * @{ + */ +#ifndef __SWREG_AON_AON1_MACRO__ +#define __SWREG_AON_AON1_MACRO__ + +/* macros for field mpptSettlingTimeoutCoef_SH */ +/** + * @defgroup swreg_aon_regs_core_mpptSettlingTimeoutCoef_SH_field mpptSettlingTimeoutCoef_SH_field + * @brief macros for field mpptSettlingTimeoutCoef_SH + * @details the mppt settling time timeout is mpptPeriodsTarget*(1+mpptSettlingTimeoutCoef) (shadowed in simple and main) + * @{ + */ +#define SWREG_AON_AON1__MPPTSETTLINGTIMEOUTCOEF_SH__SHIFT 0 +#define SWREG_AON_AON1__MPPTSETTLINGTIMEOUTCOEF_SH__WIDTH 5 +#define SWREG_AON_AON1__MPPTSETTLINGTIMEOUTCOEF_SH__MASK 0x0000001fU +#define SWREG_AON_AON1__MPPTSETTLINGTIMEOUTCOEF_SH__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SWREG_AON_AON1__MPPTSETTLINGTIMEOUTCOEF_SH__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SWREG_AON_AON1__MPPTSETTLINGTIMEOUTCOEF_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define SWREG_AON_AON1__MPPTSETTLINGTIMEOUTCOEF_SH__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define SWREG_AON_AON1__MPPTSETTLINGTIMEOUTCOEF_SH__RESET_VALUE 0x0000000fU +/** @} */ + +/* macros for field timeDumpTarget_dvdd_SH */ +/** + * @defgroup swreg_aon_regs_core_timeDumpTarget_dvdd_SH_field timeDumpTarget_dvdd_SH_field + * @brief macros for field timeDumpTarget_dvdd_SH + * @details target dump time for dvdd (shadowed in simple and main) + * @{ + */ +#define SWREG_AON_AON1__TIMEDUMPTARGET_DVDD_SH__SHIFT 5 +#define SWREG_AON_AON1__TIMEDUMPTARGET_DVDD_SH__WIDTH 7 +#define SWREG_AON_AON1__TIMEDUMPTARGET_DVDD_SH__MASK 0x00000fe0U +#define SWREG_AON_AON1__TIMEDUMPTARGET_DVDD_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00000fe0U) >> 5) +#define SWREG_AON_AON1__TIMEDUMPTARGET_DVDD_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000fe0U) +#define SWREG_AON_AON1__TIMEDUMPTARGET_DVDD_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fe0U) | (((uint32_t)(src) <<\ + 5) & 0x00000fe0U) +#define SWREG_AON_AON1__TIMEDUMPTARGET_DVDD_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000fe0U))) +#define SWREG_AON_AON1__TIMEDUMPTARGET_DVDD_SH__RESET_VALUE 0x00000032U +/** @} */ + +/* macros for field timeDumpTarget_vaux_SH */ +/** + * @defgroup swreg_aon_regs_core_timeDumpTarget_vaux_SH_field timeDumpTarget_vaux_SH_field + * @brief macros for field timeDumpTarget_vaux_SH + * @details target dump time for vaux (shadowed in simple and main) + * @{ + */ +#define SWREG_AON_AON1__TIMEDUMPTARGET_VAUX_SH__SHIFT 12 +#define SWREG_AON_AON1__TIMEDUMPTARGET_VAUX_SH__WIDTH 7 +#define SWREG_AON_AON1__TIMEDUMPTARGET_VAUX_SH__MASK 0x0007f000U +#define SWREG_AON_AON1__TIMEDUMPTARGET_VAUX_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x0007f000U) >> 12) +#define SWREG_AON_AON1__TIMEDUMPTARGET_VAUX_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0007f000U) +#define SWREG_AON_AON1__TIMEDUMPTARGET_VAUX_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007f000U) | (((uint32_t)(src) <<\ + 12) & 0x0007f000U) +#define SWREG_AON_AON1__TIMEDUMPTARGET_VAUX_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0007f000U))) +#define SWREG_AON_AON1__TIMEDUMPTARGET_VAUX_SH__RESET_VALUE 0x0000000aU +/** @} */ + +/* macros for field timeDumpTarget_vddio_SH */ +/** + * @defgroup swreg_aon_regs_core_timeDumpTarget_vddio_SH_field timeDumpTarget_vddio_SH_field + * @brief macros for field timeDumpTarget_vddio_SH + * @details target dump time for vddio (shadowed in simple and main) + * @{ + */ +#define SWREG_AON_AON1__TIMEDUMPTARGET_VDDIO_SH__SHIFT 19 +#define SWREG_AON_AON1__TIMEDUMPTARGET_VDDIO_SH__WIDTH 7 +#define SWREG_AON_AON1__TIMEDUMPTARGET_VDDIO_SH__MASK 0x03f80000U +#define SWREG_AON_AON1__TIMEDUMPTARGET_VDDIO_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x03f80000U) >> 19) +#define SWREG_AON_AON1__TIMEDUMPTARGET_VDDIO_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x03f80000U) +#define SWREG_AON_AON1__TIMEDUMPTARGET_VDDIO_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03f80000U) | (((uint32_t)(src) <<\ + 19) & 0x03f80000U) +#define SWREG_AON_AON1__TIMEDUMPTARGET_VDDIO_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x03f80000U))) +#define SWREG_AON_AON1__TIMEDUMPTARGET_VDDIO_SH__RESET_VALUE 0x00000015U +/** @} */ +#define SWREG_AON_AON1__TYPE uint32_t +#define SWREG_AON_AON1__READ 0x03ffffffU +#define SWREG_AON_AON1__WRITE 0x03ffffffU +#define SWREG_AON_AON1__PRESERVED 0x00000000U +#define SWREG_AON_AON1__RESET_VALUE 0x00a8a64fU + +#endif /* __SWREG_AON_AON1_MACRO__ */ + +/** @} end of aon1 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_AON_aon2 */ +/** + * @defgroup swreg_aon_regs_core_aon2 aon2 + * @brief swreg aon regs definitions. + * @{ + */ +#ifndef __SWREG_AON_AON2_MACRO__ +#define __SWREG_AON_AON2_MACRO__ + +/* macros for field timeDumpTarget_avdd_SH */ +/** + * @defgroup swreg_aon_regs_core_timeDumpTarget_avdd_SH_field timeDumpTarget_avdd_SH_field + * @brief macros for field timeDumpTarget_avdd_SH + * @details target dump time for avdd (shadowed in simple and main) + * @{ + */ +#define SWREG_AON_AON2__TIMEDUMPTARGET_AVDD_SH__SHIFT 0 +#define SWREG_AON_AON2__TIMEDUMPTARGET_AVDD_SH__WIDTH 7 +#define SWREG_AON_AON2__TIMEDUMPTARGET_AVDD_SH__MASK 0x0000007fU +#define SWREG_AON_AON2__TIMEDUMPTARGET_AVDD_SH__READ(src) \ + ((uint32_t)(src)\ + & 0x0000007fU) +#define SWREG_AON_AON2__TIMEDUMPTARGET_AVDD_SH__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000007fU) +#define SWREG_AON_AON2__TIMEDUMPTARGET_AVDD_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define SWREG_AON_AON2__TIMEDUMPTARGET_AVDD_SH__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000007fU))) +#define SWREG_AON_AON2__TIMEDUMPTARGET_AVDD_SH__RESET_VALUE 0x00000032U +/** @} */ + +/* macros for field timeTargetHarv2Store_SH */ +/** + * @defgroup swreg_aon_regs_core_timeTargetHarv2Store_SH_field timeTargetHarv2Store_SH_field + * @brief macros for field timeTargetHarv2Store_SH + * @details target time for the harvest to store mode, also target dump time for vddpa (shadowed in simple and main) + * @{ + */ +#define SWREG_AON_AON2__TIMETARGETHARV2STORE_SH__SHIFT 7 +#define SWREG_AON_AON2__TIMETARGETHARV2STORE_SH__WIDTH 7 +#define SWREG_AON_AON2__TIMETARGETHARV2STORE_SH__MASK 0x00003f80U +#define SWREG_AON_AON2__TIMETARGETHARV2STORE_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00003f80U) >> 7) +#define SWREG_AON_AON2__TIMETARGETHARV2STORE_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00003f80U) +#define SWREG_AON_AON2__TIMETARGETHARV2STORE_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((uint32_t)(src) <<\ + 7) & 0x00003f80U) +#define SWREG_AON_AON2__TIMETARGETHARV2STORE_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00003f80U))) +#define SWREG_AON_AON2__TIMETARGETHARV2STORE_SH__RESET_VALUE 0x0000001eU +/** @} */ + +/* macros for field targetIsDumpHarv2Store_SH */ +/** + * @defgroup swreg_aon_regs_core_targetIsDumpHarv2Store_SH_field targetIsDumpHarv2Store_SH_field + * @brief macros for field targetIsDumpHarv2Store_SH + * @details if 1 the target for the harvest to store mode is the dump time, otherwise it is the energize time (shadowed in simple and main) + * @{ + */ +#define SWREG_AON_AON2__TARGETISDUMPHARV2STORE_SH__SHIFT 14 +#define SWREG_AON_AON2__TARGETISDUMPHARV2STORE_SH__WIDTH 1 +#define SWREG_AON_AON2__TARGETISDUMPHARV2STORE_SH__MASK 0x00004000U +#define SWREG_AON_AON2__TARGETISDUMPHARV2STORE_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00004000U) >> 14) +#define SWREG_AON_AON2__TARGETISDUMPHARV2STORE_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x00004000U) +#define SWREG_AON_AON2__TARGETISDUMPHARV2STORE_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((uint32_t)(src) <<\ + 14) & 0x00004000U) +#define SWREG_AON_AON2__TARGETISDUMPHARV2STORE_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x00004000U))) +#define SWREG_AON_AON2__TARGETISDUMPHARV2STORE_SH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(1) << 14) +#define SWREG_AON_AON2__TARGETISDUMPHARV2STORE_SH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((uint32_t)(0) << 14) +#define SWREG_AON_AON2__TARGETISDUMPHARV2STORE_SH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field chargeStartingReady_SH */ +/** + * @defgroup swreg_aon_regs_core_chargeStartingReady_SH_field chargeStartingReady_SH_field + * @brief macros for field chargeStartingReady_SH + * @details It affects charging STORE from VHARV and BATT, and charging VBATT from STORE. In these modes when the target time is dump we startwith constant energize time until the destination is ready (vstoreGood or vbattGood becomes 1). When the target time is energize we are always in constant energize mode. In this case, if chargeStartingReady_SH=0 before the supply is ready we are in startup mode, in which the energize time is constant regargless of if the dump time is maximized. If chargeStartingReady_SH=1 the supply is always ready and we start charging in steady state mode in which while energize is set, if the dump time is maximized, the energize time is reduced to satisfy ZCD (shadowed in simple and main) + * @{ + */ +#define SWREG_AON_AON2__CHARGESTARTINGREADY_SH__SHIFT 15 +#define SWREG_AON_AON2__CHARGESTARTINGREADY_SH__WIDTH 1 +#define SWREG_AON_AON2__CHARGESTARTINGREADY_SH__MASK 0x00008000U +#define SWREG_AON_AON2__CHARGESTARTINGREADY_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00008000U) >> 15) +#define SWREG_AON_AON2__CHARGESTARTINGREADY_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x00008000U) +#define SWREG_AON_AON2__CHARGESTARTINGREADY_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((uint32_t)(src) <<\ + 15) & 0x00008000U) +#define SWREG_AON_AON2__CHARGESTARTINGREADY_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x00008000U))) +#define SWREG_AON_AON2__CHARGESTARTINGREADY_SH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(1) << 15) +#define SWREG_AON_AON2__CHARGESTARTINGREADY_SH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((uint32_t)(0) << 15) +#define SWREG_AON_AON2__CHARGESTARTINGREADY_SH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field timeEnergStart_battery */ +/** + * @defgroup swreg_aon_regs_core_timeEnergStart_battery_field timeEnergStart_battery_field + * @brief macros for field timeEnergStart_battery + * @details target energize time for battery, used before the supply is ready (used in simple and main) + * @{ + */ +#define SWREG_AON_AON2__TIMEENERGSTART_BATTERY__SHIFT 16 +#define SWREG_AON_AON2__TIMEENERGSTART_BATTERY__WIDTH 5 +#define SWREG_AON_AON2__TIMEENERGSTART_BATTERY__MASK 0x001f0000U +#define SWREG_AON_AON2__TIMEENERGSTART_BATTERY__READ(src) \ + (((uint32_t)(src)\ + & 0x001f0000U) >> 16) +#define SWREG_AON_AON2__TIMEENERGSTART_BATTERY__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x001f0000U) +#define SWREG_AON_AON2__TIMEENERGSTART_BATTERY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((uint32_t)(src) <<\ + 16) & 0x001f0000U) +#define SWREG_AON_AON2__TIMEENERGSTART_BATTERY__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x001f0000U))) +#define SWREG_AON_AON2__TIMEENERGSTART_BATTERY__RESET_VALUE 0x00000008U +/** @} */ + +/* macros for field timeEnergStart_store */ +/** + * @defgroup swreg_aon_regs_core_timeEnergStart_store_field timeEnergStart_store_field + * @brief macros for field timeEnergStart_store + * @details target energize time for store, used before the supply is ready (used in simple and main) timeEnergStart_harvest was removed and timeTargetHarv2Store_SH is used instead. Better to keep targetIsDumpHarv2Store_SH 0, because if targetIsDumpHarv2Store_SH=1, timeTargetHarv2Store_SH is energize time for harv->supplies and harv->store at startup and dump time for harv->store after store is ready. + * @{ + */ +#define SWREG_AON_AON2__TIMEENERGSTART_STORE__SHIFT 21 +#define SWREG_AON_AON2__TIMEENERGSTART_STORE__WIDTH 5 +#define SWREG_AON_AON2__TIMEENERGSTART_STORE__MASK 0x03e00000U +#define SWREG_AON_AON2__TIMEENERGSTART_STORE__READ(src) \ + (((uint32_t)(src)\ + & 0x03e00000U) >> 21) +#define SWREG_AON_AON2__TIMEENERGSTART_STORE__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x03e00000U) +#define SWREG_AON_AON2__TIMEENERGSTART_STORE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03e00000U) | (((uint32_t)(src) <<\ + 21) & 0x03e00000U) +#define SWREG_AON_AON2__TIMEENERGSTART_STORE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x03e00000U))) +#define SWREG_AON_AON2__TIMEENERGSTART_STORE__RESET_VALUE 0x0000000cU +/** @} */ + +/* macros for field timeAfterDump_Start */ +/** + * @defgroup swreg_aon_regs_core_timeAfterDump_Start_field timeAfterDump_Start_field + * @brief macros for field timeAfterDump_Start + * @details length of state after dump at startup (normally plan state), during supply rampup and also before Vaux is ready. The higher the value the lower the startup current. Setting greater than zero is safer for timing, although should be OK. (x8 + 7)(used in simple and main) + * @{ + */ +#define SWREG_AON_AON2__TIMEAFTERDUMP_START__SHIFT 26 +#define SWREG_AON_AON2__TIMEAFTERDUMP_START__WIDTH 4 +#define SWREG_AON_AON2__TIMEAFTERDUMP_START__MASK 0x3c000000U +#define SWREG_AON_AON2__TIMEAFTERDUMP_START__READ(src) \ + (((uint32_t)(src)\ + & 0x3c000000U) >> 26) +#define SWREG_AON_AON2__TIMEAFTERDUMP_START__WRITE(src) \ + (((uint32_t)(src)\ + << 26) & 0x3c000000U) +#define SWREG_AON_AON2__TIMEAFTERDUMP_START__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3c000000U) | (((uint32_t)(src) <<\ + 26) & 0x3c000000U) +#define SWREG_AON_AON2__TIMEAFTERDUMP_START__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 26) & ~0x3c000000U))) +#define SWREG_AON_AON2__TIMEAFTERDUMP_START__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field loadRegAon */ +/** + * @defgroup swreg_aon_regs_core_loadRegAon_field loadRegAon_field + * @brief macros for field loadRegAon + * @details load the Aon shadow register + * @{ + */ +#define SWREG_AON_AON2__LOADREGAON__SHIFT 30 +#define SWREG_AON_AON2__LOADREGAON__WIDTH 1 +#define SWREG_AON_AON2__LOADREGAON__MASK 0x40000000U +#define SWREG_AON_AON2__LOADREGAON__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define SWREG_AON_AON2__LOADREGAON__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define SWREG_AON_AON2__LOADREGAON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define SWREG_AON_AON2__LOADREGAON__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define SWREG_AON_AON2__LOADREGAON__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define SWREG_AON_AON2__LOADREGAON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define SWREG_AON_AON2__LOADREGAON__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field changeFsm_ovr */ +/** + * @defgroup swreg_aon_regs_core_changeFsm_ovr_field changeFsm_ovr_field + * @brief macros for field changeFsm_ovr + * @details override changeFsm and fsmToUse + * @{ + */ +#define SWREG_AON_AON2__CHANGEFSM_OVR__SHIFT 31 +#define SWREG_AON_AON2__CHANGEFSM_OVR__WIDTH 1 +#define SWREG_AON_AON2__CHANGEFSM_OVR__MASK 0x80000000U +#define SWREG_AON_AON2__CHANGEFSM_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define SWREG_AON_AON2__CHANGEFSM_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define SWREG_AON_AON2__CHANGEFSM_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define SWREG_AON_AON2__CHANGEFSM_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define SWREG_AON_AON2__CHANGEFSM_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define SWREG_AON_AON2__CHANGEFSM_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define SWREG_AON_AON2__CHANGEFSM_OVR__RESET_VALUE 0x00000000U +/** @} */ +#define SWREG_AON_AON2__TYPE uint32_t +#define SWREG_AON_AON2__READ 0xffffffffU +#define SWREG_AON_AON2__WRITE 0xffffffffU +#define SWREG_AON_AON2__PRESERVED 0x00000000U +#define SWREG_AON_AON2__RESET_VALUE 0x1d880f32U + +#endif /* __SWREG_AON_AON2_MACRO__ */ + +/** @} end of aon2 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_AON_aon3 */ +/** + * @defgroup swreg_aon_regs_core_aon3 aon3 + * @brief swreg aon regs definitions. + * @{ + */ +#ifndef __SWREG_AON_AON3_MACRO__ +#define __SWREG_AON_AON3_MACRO__ + +/* macros for field changeFsm_ovrVal */ +/** + * @defgroup swreg_aon_regs_core_changeFsm_ovrVal_field changeFsm_ovrVal_field + * @brief macros for field changeFsm_ovrVal + * @details override value of changeFsm + * @{ + */ +#define SWREG_AON_AON3__CHANGEFSM_OVRVAL__SHIFT 0 +#define SWREG_AON_AON3__CHANGEFSM_OVRVAL__WIDTH 1 +#define SWREG_AON_AON3__CHANGEFSM_OVRVAL__MASK 0x00000001U +#define SWREG_AON_AON3__CHANGEFSM_OVRVAL__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWREG_AON_AON3__CHANGEFSM_OVRVAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWREG_AON_AON3__CHANGEFSM_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SWREG_AON_AON3__CHANGEFSM_OVRVAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SWREG_AON_AON3__CHANGEFSM_OVRVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SWREG_AON_AON3__CHANGEFSM_OVRVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SWREG_AON_AON3__CHANGEFSM_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fsmToUse_ovrVal */ +/** + * @defgroup swreg_aon_regs_core_fsmToUse_ovrVal_field fsmToUse_ovrVal_field + * @brief macros for field fsmToUse_ovrVal + * @details override value of fsmToUse. Must be set before changeFsm_ovrVal posedge + * @{ + */ +#define SWREG_AON_AON3__FSMTOUSE_OVRVAL__SHIFT 1 +#define SWREG_AON_AON3__FSMTOUSE_OVRVAL__WIDTH 2 +#define SWREG_AON_AON3__FSMTOUSE_OVRVAL__MASK 0x00000006U +#define SWREG_AON_AON3__FSMTOUSE_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000006U) >> 1) +#define SWREG_AON_AON3__FSMTOUSE_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000006U) +#define SWREG_AON_AON3__FSMTOUSE_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000006U) | (((uint32_t)(src) <<\ + 1) & 0x00000006U) +#define SWREG_AON_AON3__FSMTOUSE_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000006U))) +#define SWREG_AON_AON3__FSMTOUSE_OVRVAL__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field rstStoreUnavailable */ +/** + * @defgroup swreg_aon_regs_core_rstStoreUnavailable_field rstStoreUnavailable_field + * @brief macros for field rstStoreUnavailable + * @details reset the energize and dump time of all the modes whose source is store, when store becomes unavailable as a source (vstoreGood=0) + * @{ + */ +#define SWREG_AON_AON3__RSTSTOREUNAVAILABLE__SHIFT 3 +#define SWREG_AON_AON3__RSTSTOREUNAVAILABLE__WIDTH 1 +#define SWREG_AON_AON3__RSTSTOREUNAVAILABLE__MASK 0x00000008U +#define SWREG_AON_AON3__RSTSTOREUNAVAILABLE__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define SWREG_AON_AON3__RSTSTOREUNAVAILABLE__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define SWREG_AON_AON3__RSTSTOREUNAVAILABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define SWREG_AON_AON3__RSTSTOREUNAVAILABLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define SWREG_AON_AON3__RSTSTOREUNAVAILABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define SWREG_AON_AON3__RSTSTOREUNAVAILABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define SWREG_AON_AON3__RSTSTOREUNAVAILABLE__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field useHotStart */ +/** + * @defgroup swreg_aon_regs_core_useHotStart_field useHotStart_field + * @brief macros for field useHotStart + * @details use hot start to assume enabled supplies are ready when switching to a new fsm (destReady is immediately asserted) + * @{ + */ +#define SWREG_AON_AON3__USEHOTSTART__SHIFT 4 +#define SWREG_AON_AON3__USEHOTSTART__WIDTH 1 +#define SWREG_AON_AON3__USEHOTSTART__MASK 0x00000010U +#define SWREG_AON_AON3__USEHOTSTART__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define SWREG_AON_AON3__USEHOTSTART__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define SWREG_AON_AON3__USEHOTSTART__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define SWREG_AON_AON3__USEHOTSTART__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define SWREG_AON_AON3__USEHOTSTART__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define SWREG_AON_AON3__USEHOTSTART__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define SWREG_AON_AON3__USEHOTSTART__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field clkUnitDelTop */ +/** + * @defgroup swreg_aon_regs_core_clkUnitDelTop_field clkUnitDelTop_field + * @brief macros for field clkUnitDelTop + * @details unit delay for the clock of the top FSM. + * @{ + */ +#define SWREG_AON_AON3__CLKUNITDELTOP__SHIFT 5 +#define SWREG_AON_AON3__CLKUNITDELTOP__WIDTH 3 +#define SWREG_AON_AON3__CLKUNITDELTOP__MASK 0x000000e0U +#define SWREG_AON_AON3__CLKUNITDELTOP__READ(src) \ + (((uint32_t)(src)\ + & 0x000000e0U) >> 5) +#define SWREG_AON_AON3__CLKUNITDELTOP__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x000000e0U) +#define SWREG_AON_AON3__CLKUNITDELTOP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((uint32_t)(src) <<\ + 5) & 0x000000e0U) +#define SWREG_AON_AON3__CLKUNITDELTOP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000000e0U))) +#define SWREG_AON_AON3__CLKUNITDELTOP__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field clkFixedTop */ +/** + * @defgroup swreg_aon_regs_core_clkFixedTop_field clkFixedTop_field + * @brief macros for field clkFixedTop + * @details fixed time for the clock of the top FSM. clkFixedTop=3 and clkUnitDelTop=4 provides a ~6.4 MHz clock in typical corner. + * @{ + */ +#define SWREG_AON_AON3__CLKFIXEDTOP__SHIFT 8 +#define SWREG_AON_AON3__CLKFIXEDTOP__WIDTH 3 +#define SWREG_AON_AON3__CLKFIXEDTOP__MASK 0x00000700U +#define SWREG_AON_AON3__CLKFIXEDTOP__READ(src) \ + (((uint32_t)(src)\ + & 0x00000700U) >> 8) +#define SWREG_AON_AON3__CLKFIXEDTOP__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000700U) +#define SWREG_AON_AON3__CLKFIXEDTOP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((uint32_t)(src) <<\ + 8) & 0x00000700U) +#define SWREG_AON_AON3__CLKFIXEDTOP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000700U))) +#define SWREG_AON_AON3__CLKFIXEDTOP__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field enableSource_ovr */ +/** + * @defgroup swreg_aon_regs_core_enableSource_ovr_field enableSource_ovr_field + * @brief macros for field enableSource_ovr + * @details override enables for the 3 sources + * @{ + */ +#define SWREG_AON_AON3__ENABLESOURCE_OVR__SHIFT 11 +#define SWREG_AON_AON3__ENABLESOURCE_OVR__WIDTH 3 +#define SWREG_AON_AON3__ENABLESOURCE_OVR__MASK 0x00003800U +#define SWREG_AON_AON3__ENABLESOURCE_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00003800U) >> 11) +#define SWREG_AON_AON3__ENABLESOURCE_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00003800U) +#define SWREG_AON_AON3__ENABLESOURCE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((uint32_t)(src) <<\ + 11) & 0x00003800U) +#define SWREG_AON_AON3__ENABLESOURCE_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00003800U))) +#define SWREG_AON_AON3__ENABLESOURCE_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enableSource_ovrVal */ +/** + * @defgroup swreg_aon_regs_core_enableSource_ovrVal_field enableSource_ovrVal_field + * @brief macros for field enableSource_ovrVal + * @details override values of the enables for the 3 sources + * @{ + */ +#define SWREG_AON_AON3__ENABLESOURCE_OVRVAL__SHIFT 14 +#define SWREG_AON_AON3__ENABLESOURCE_OVRVAL__WIDTH 3 +#define SWREG_AON_AON3__ENABLESOURCE_OVRVAL__MASK 0x0001c000U +#define SWREG_AON_AON3__ENABLESOURCE_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x0001c000U) >> 14) +#define SWREG_AON_AON3__ENABLESOURCE_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0001c000U) +#define SWREG_AON_AON3__ENABLESOURCE_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((uint32_t)(src) <<\ + 14) & 0x0001c000U) +#define SWREG_AON_AON3__ENABLESOURCE_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0001c000U))) +#define SWREG_AON_AON3__ENABLESOURCE_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enableDest_ovr */ +/** + * @defgroup swreg_aon_regs_core_enableDest_ovr_field enableDest_ovr_field + * @brief macros for field enableDest_ovr + * @details override enables for the 5 destinations + * @{ + */ +#define SWREG_AON_AON3__ENABLEDEST_OVR__SHIFT 17 +#define SWREG_AON_AON3__ENABLEDEST_OVR__WIDTH 5 +#define SWREG_AON_AON3__ENABLEDEST_OVR__MASK 0x003e0000U +#define SWREG_AON_AON3__ENABLEDEST_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x003e0000U) >> 17) +#define SWREG_AON_AON3__ENABLEDEST_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x003e0000U) +#define SWREG_AON_AON3__ENABLEDEST_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((uint32_t)(src) <<\ + 17) & 0x003e0000U) +#define SWREG_AON_AON3__ENABLEDEST_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x003e0000U))) +#define SWREG_AON_AON3__ENABLEDEST_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enableDest_ovrVal */ +/** + * @defgroup swreg_aon_regs_core_enableDest_ovrVal_field enableDest_ovrVal_field + * @brief macros for field enableDest_ovrVal + * @details override values of the enables for the 5 destinations + * @{ + */ +#define SWREG_AON_AON3__ENABLEDEST_OVRVAL__SHIFT 22 +#define SWREG_AON_AON3__ENABLEDEST_OVRVAL__WIDTH 5 +#define SWREG_AON_AON3__ENABLEDEST_OVRVAL__MASK 0x07c00000U +#define SWREG_AON_AON3__ENABLEDEST_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x07c00000U) >> 22) +#define SWREG_AON_AON3__ENABLEDEST_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x07c00000U) +#define SWREG_AON_AON3__ENABLEDEST_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((uint32_t)(src) <<\ + 22) & 0x07c00000U) +#define SWREG_AON_AON3__ENABLEDEST_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x07c00000U))) +#define SWREG_AON_AON3__ENABLEDEST_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field poweronSimple */ +/** + * @defgroup swreg_aon_regs_core_poweronSimple_field poweronSimple_field + * @brief macros for field poweronSimple + * @details force power on the simple FSM + * @{ + */ +#define SWREG_AON_AON3__POWERONSIMPLE__SHIFT 27 +#define SWREG_AON_AON3__POWERONSIMPLE__WIDTH 1 +#define SWREG_AON_AON3__POWERONSIMPLE__MASK 0x08000000U +#define SWREG_AON_AON3__POWERONSIMPLE__READ(src) \ + (((uint32_t)(src)\ + & 0x08000000U) >> 27) +#define SWREG_AON_AON3__POWERONSIMPLE__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x08000000U) +#define SWREG_AON_AON3__POWERONSIMPLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((uint32_t)(src) <<\ + 27) & 0x08000000U) +#define SWREG_AON_AON3__POWERONSIMPLE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x08000000U))) +#define SWREG_AON_AON3__POWERONSIMPLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(1) << 27) +#define SWREG_AON_AON3__POWERONSIMPLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((uint32_t)(0) << 27) +#define SWREG_AON_AON3__POWERONSIMPLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field poweronMain */ +/** + * @defgroup swreg_aon_regs_core_poweronMain_field poweronMain_field + * @brief macros for field poweronMain + * @details force power on the main FSM + * @{ + */ +#define SWREG_AON_AON3__POWERONMAIN__SHIFT 28 +#define SWREG_AON_AON3__POWERONMAIN__WIDTH 1 +#define SWREG_AON_AON3__POWERONMAIN__MASK 0x10000000U +#define SWREG_AON_AON3__POWERONMAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define SWREG_AON_AON3__POWERONMAIN__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define SWREG_AON_AON3__POWERONMAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define SWREG_AON_AON3__POWERONMAIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define SWREG_AON_AON3__POWERONMAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define SWREG_AON_AON3__POWERONMAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define SWREG_AON_AON3__POWERONMAIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field resetPreviousFsm */ +/** + * @defgroup swreg_aon_regs_core_resetPreviousFsm_field resetPreviousFsm_field + * @brief macros for field resetPreviousFsm + * @details reset the previous FSM, even if its power domain remains established. By default the previous FSM maintains its state if its supply does not collapse. + * @{ + */ +#define SWREG_AON_AON3__RESETPREVIOUSFSM__SHIFT 29 +#define SWREG_AON_AON3__RESETPREVIOUSFSM__WIDTH 1 +#define SWREG_AON_AON3__RESETPREVIOUSFSM__MASK 0x20000000U +#define SWREG_AON_AON3__RESETPREVIOUSFSM__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define SWREG_AON_AON3__RESETPREVIOUSFSM__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define SWREG_AON_AON3__RESETPREVIOUSFSM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define SWREG_AON_AON3__RESETPREVIOUSFSM__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define SWREG_AON_AON3__RESETPREVIOUSFSM__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define SWREG_AON_AON3__RESETPREVIOUSFSM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define SWREG_AON_AON3__RESETPREVIOUSFSM__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hsTiny_ovr */ +/** + * @defgroup swreg_aon_regs_core_hsTiny_ovr_field hsTiny_ovr_field + * @brief macros for field hsTiny_ovr + * @details override of the vdd_tiny head switch control, bypassing fsmTop + * @{ + */ +#define SWREG_AON_AON3__HSTINY_OVR__SHIFT 30 +#define SWREG_AON_AON3__HSTINY_OVR__WIDTH 1 +#define SWREG_AON_AON3__HSTINY_OVR__MASK 0x40000000U +#define SWREG_AON_AON3__HSTINY_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define SWREG_AON_AON3__HSTINY_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define SWREG_AON_AON3__HSTINY_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define SWREG_AON_AON3__HSTINY_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define SWREG_AON_AON3__HSTINY_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define SWREG_AON_AON3__HSTINY_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define SWREG_AON_AON3__HSTINY_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hsTiny_ovrVal */ +/** + * @defgroup swreg_aon_regs_core_hsTiny_ovrVal_field hsTiny_ovrVal_field + * @brief macros for field hsTiny_ovrVal + * @details override value of the vdd_tiny head switch control, bypassing fsmTop + * @{ + */ +#define SWREG_AON_AON3__HSTINY_OVRVAL__SHIFT 31 +#define SWREG_AON_AON3__HSTINY_OVRVAL__WIDTH 1 +#define SWREG_AON_AON3__HSTINY_OVRVAL__MASK 0x80000000U +#define SWREG_AON_AON3__HSTINY_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define SWREG_AON_AON3__HSTINY_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define SWREG_AON_AON3__HSTINY_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define SWREG_AON_AON3__HSTINY_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define SWREG_AON_AON3__HSTINY_OVRVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define SWREG_AON_AON3__HSTINY_OVRVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define SWREG_AON_AON3__HSTINY_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ +#define SWREG_AON_AON3__TYPE uint32_t +#define SWREG_AON_AON3__READ 0xffffffffU +#define SWREG_AON_AON3__WRITE 0xffffffffU +#define SWREG_AON_AON3__PRESERVED 0x00000000U +#define SWREG_AON_AON3__RESET_VALUE 0x0000039eU + +#endif /* __SWREG_AON_AON3_MACRO__ */ + +/** @} end of aon3 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_AON_aon4 */ +/** + * @defgroup swreg_aon_regs_core_aon4 aon4 + * @brief swreg aon regs definitions. + * @{ + */ +#ifndef __SWREG_AON_AON4_MACRO__ +#define __SWREG_AON_AON4_MACRO__ + +/* macros for field hsSimple_ovr */ +/** + * @defgroup swreg_aon_regs_core_hsSimple_ovr_field hsSimple_ovr_field + * @brief macros for field hsSimple_ovr + * @details override of the vdd_simple head switch control, bypassing fsmTop + * @{ + */ +#define SWREG_AON_AON4__HSSIMPLE_OVR__SHIFT 0 +#define SWREG_AON_AON4__HSSIMPLE_OVR__WIDTH 1 +#define SWREG_AON_AON4__HSSIMPLE_OVR__MASK 0x00000001U +#define SWREG_AON_AON4__HSSIMPLE_OVR__READ(src) ((uint32_t)(src) & 0x00000001U) +#define SWREG_AON_AON4__HSSIMPLE_OVR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWREG_AON_AON4__HSSIMPLE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SWREG_AON_AON4__HSSIMPLE_OVR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SWREG_AON_AON4__HSSIMPLE_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SWREG_AON_AON4__HSSIMPLE_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SWREG_AON_AON4__HSSIMPLE_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hsSimple_ovrVal */ +/** + * @defgroup swreg_aon_regs_core_hsSimple_ovrVal_field hsSimple_ovrVal_field + * @brief macros for field hsSimple_ovrVal + * @details override value of the vdd_simple head switch control, bypassing fsmTop + * @{ + */ +#define SWREG_AON_AON4__HSSIMPLE_OVRVAL__SHIFT 1 +#define SWREG_AON_AON4__HSSIMPLE_OVRVAL__WIDTH 1 +#define SWREG_AON_AON4__HSSIMPLE_OVRVAL__MASK 0x00000002U +#define SWREG_AON_AON4__HSSIMPLE_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define SWREG_AON_AON4__HSSIMPLE_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define SWREG_AON_AON4__HSSIMPLE_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define SWREG_AON_AON4__HSSIMPLE_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define SWREG_AON_AON4__HSSIMPLE_OVRVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SWREG_AON_AON4__HSSIMPLE_OVRVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SWREG_AON_AON4__HSSIMPLE_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hsMain_ovr */ +/** + * @defgroup swreg_aon_regs_core_hsMain_ovr_field hsMain_ovr_field + * @brief macros for field hsMain_ovr + * @details override of the vdd_main head switch control, bypassing fsmTop + * @{ + */ +#define SWREG_AON_AON4__HSMAIN_OVR__SHIFT 2 +#define SWREG_AON_AON4__HSMAIN_OVR__WIDTH 1 +#define SWREG_AON_AON4__HSMAIN_OVR__MASK 0x00000004U +#define SWREG_AON_AON4__HSMAIN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define SWREG_AON_AON4__HSMAIN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define SWREG_AON_AON4__HSMAIN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define SWREG_AON_AON4__HSMAIN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define SWREG_AON_AON4__HSMAIN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define SWREG_AON_AON4__HSMAIN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define SWREG_AON_AON4__HSMAIN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hsMain_ovrVal */ +/** + * @defgroup swreg_aon_regs_core_hsMain_ovrVal_field hsMain_ovrVal_field + * @brief macros for field hsMain_ovrVal + * @details override value of the vdd_main head switch control, bypassing fsmTop + * @{ + */ +#define SWREG_AON_AON4__HSMAIN_OVRVAL__SHIFT 3 +#define SWREG_AON_AON4__HSMAIN_OVRVAL__WIDTH 1 +#define SWREG_AON_AON4__HSMAIN_OVRVAL__MASK 0x00000008U +#define SWREG_AON_AON4__HSMAIN_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define SWREG_AON_AON4__HSMAIN_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define SWREG_AON_AON4__HSMAIN_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define SWREG_AON_AON4__HSMAIN_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define SWREG_AON_AON4__HSMAIN_OVRVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define SWREG_AON_AON4__HSMAIN_OVRVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define SWREG_AON_AON4__HSMAIN_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field loadShadowAon_ovr */ +/** + * @defgroup swreg_aon_regs_core_loadShadowAon_ovr_field loadShadowAon_ovr_field + * @brief macros for field loadShadowAon_ovr + * @details override of the load for the shadowAon register, bypassing fsmTop + * @{ + */ +#define SWREG_AON_AON4__LOADSHADOWAON_OVR__SHIFT 4 +#define SWREG_AON_AON4__LOADSHADOWAON_OVR__WIDTH 1 +#define SWREG_AON_AON4__LOADSHADOWAON_OVR__MASK 0x00000010U +#define SWREG_AON_AON4__LOADSHADOWAON_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define SWREG_AON_AON4__LOADSHADOWAON_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define SWREG_AON_AON4__LOADSHADOWAON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define SWREG_AON_AON4__LOADSHADOWAON_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define SWREG_AON_AON4__LOADSHADOWAON_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define SWREG_AON_AON4__LOADSHADOWAON_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define SWREG_AON_AON4__LOADSHADOWAON_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field loadShadowAon_ovrVal */ +/** + * @defgroup swreg_aon_regs_core_loadShadowAon_ovrVal_field loadShadowAon_ovrVal_field + * @brief macros for field loadShadowAon_ovrVal + * @details override value of the load for the shadowAon register, bypassing fsmTop + * @{ + */ +#define SWREG_AON_AON4__LOADSHADOWAON_OVRVAL__SHIFT 5 +#define SWREG_AON_AON4__LOADSHADOWAON_OVRVAL__WIDTH 1 +#define SWREG_AON_AON4__LOADSHADOWAON_OVRVAL__MASK 0x00000020U +#define SWREG_AON_AON4__LOADSHADOWAON_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define SWREG_AON_AON4__LOADSHADOWAON_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define SWREG_AON_AON4__LOADSHADOWAON_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define SWREG_AON_AON4__LOADSHADOWAON_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define SWREG_AON_AON4__LOADSHADOWAON_OVRVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define SWREG_AON_AON4__LOADSHADOWAON_OVRVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define SWREG_AON_AON4__LOADSHADOWAON_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field loadShadowSimple_ovr */ +/** + * @defgroup swreg_aon_regs_core_loadShadowSimple_ovr_field loadShadowSimple_ovr_field + * @brief macros for field loadShadowSimple_ovr + * @details override of the load for the shadowSimple register, bypassing fsmTop + * @{ + */ +#define SWREG_AON_AON4__LOADSHADOWSIMPLE_OVR__SHIFT 6 +#define SWREG_AON_AON4__LOADSHADOWSIMPLE_OVR__WIDTH 1 +#define SWREG_AON_AON4__LOADSHADOWSIMPLE_OVR__MASK 0x00000040U +#define SWREG_AON_AON4__LOADSHADOWSIMPLE_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define SWREG_AON_AON4__LOADSHADOWSIMPLE_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define SWREG_AON_AON4__LOADSHADOWSIMPLE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define SWREG_AON_AON4__LOADSHADOWSIMPLE_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define SWREG_AON_AON4__LOADSHADOWSIMPLE_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define SWREG_AON_AON4__LOADSHADOWSIMPLE_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define SWREG_AON_AON4__LOADSHADOWSIMPLE_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field loadShadowSimple_ovrVal */ +/** + * @defgroup swreg_aon_regs_core_loadShadowSimple_ovrVal_field loadShadowSimple_ovrVal_field + * @brief macros for field loadShadowSimple_ovrVal + * @details override value of the load for the shadowSimple register, bypassing fsmTop + * @{ + */ +#define SWREG_AON_AON4__LOADSHADOWSIMPLE_OVRVAL__SHIFT 7 +#define SWREG_AON_AON4__LOADSHADOWSIMPLE_OVRVAL__WIDTH 1 +#define SWREG_AON_AON4__LOADSHADOWSIMPLE_OVRVAL__MASK 0x00000080U +#define SWREG_AON_AON4__LOADSHADOWSIMPLE_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define SWREG_AON_AON4__LOADSHADOWSIMPLE_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define SWREG_AON_AON4__LOADSHADOWSIMPLE_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define SWREG_AON_AON4__LOADSHADOWSIMPLE_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define SWREG_AON_AON4__LOADSHADOWSIMPLE_OVRVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define SWREG_AON_AON4__LOADSHADOWSIMPLE_OVRVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define SWREG_AON_AON4__LOADSHADOWSIMPLE_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field loadShadowMain_ovr */ +/** + * @defgroup swreg_aon_regs_core_loadShadowMain_ovr_field loadShadowMain_ovr_field + * @brief macros for field loadShadowMain_ovr + * @details override of the load for the shadowMain register, bypassing fsmTop + * @{ + */ +#define SWREG_AON_AON4__LOADSHADOWMAIN_OVR__SHIFT 8 +#define SWREG_AON_AON4__LOADSHADOWMAIN_OVR__WIDTH 1 +#define SWREG_AON_AON4__LOADSHADOWMAIN_OVR__MASK 0x00000100U +#define SWREG_AON_AON4__LOADSHADOWMAIN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define SWREG_AON_AON4__LOADSHADOWMAIN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define SWREG_AON_AON4__LOADSHADOWMAIN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define SWREG_AON_AON4__LOADSHADOWMAIN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define SWREG_AON_AON4__LOADSHADOWMAIN_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define SWREG_AON_AON4__LOADSHADOWMAIN_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define SWREG_AON_AON4__LOADSHADOWMAIN_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field loadShadowMain_ovrVal */ +/** + * @defgroup swreg_aon_regs_core_loadShadowMain_ovrVal_field loadShadowMain_ovrVal_field + * @brief macros for field loadShadowMain_ovrVal + * @details override value of the load for the shadowMain register, bypassing fsmTop + * @{ + */ +#define SWREG_AON_AON4__LOADSHADOWMAIN_OVRVAL__SHIFT 9 +#define SWREG_AON_AON4__LOADSHADOWMAIN_OVRVAL__WIDTH 1 +#define SWREG_AON_AON4__LOADSHADOWMAIN_OVRVAL__MASK 0x00000200U +#define SWREG_AON_AON4__LOADSHADOWMAIN_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define SWREG_AON_AON4__LOADSHADOWMAIN_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define SWREG_AON_AON4__LOADSHADOWMAIN_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define SWREG_AON_AON4__LOADSHADOWMAIN_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define SWREG_AON_AON4__LOADSHADOWMAIN_OVRVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define SWREG_AON_AON4__LOADSHADOWMAIN_OVRVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define SWREG_AON_AON4__LOADSHADOWMAIN_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field loadShadowUnitDel_ovr */ +/** + * @defgroup swreg_aon_regs_core_loadShadowUnitDel_ovr_field loadShadowUnitDel_ovr_field + * @brief macros for field loadShadowUnitDel_ovr + * @details override of the load for shadowUnitDel, bypassing fsmTop + * @{ + */ +#define SWREG_AON_AON4__LOADSHADOWUNITDEL_OVR__SHIFT 10 +#define SWREG_AON_AON4__LOADSHADOWUNITDEL_OVR__WIDTH 1 +#define SWREG_AON_AON4__LOADSHADOWUNITDEL_OVR__MASK 0x00000400U +#define SWREG_AON_AON4__LOADSHADOWUNITDEL_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000400U) >> 10) +#define SWREG_AON_AON4__LOADSHADOWUNITDEL_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x00000400U) +#define SWREG_AON_AON4__LOADSHADOWUNITDEL_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((uint32_t)(src) <<\ + 10) & 0x00000400U) +#define SWREG_AON_AON4__LOADSHADOWUNITDEL_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x00000400U))) +#define SWREG_AON_AON4__LOADSHADOWUNITDEL_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(1) << 10) +#define SWREG_AON_AON4__LOADSHADOWUNITDEL_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((uint32_t)(0) << 10) +#define SWREG_AON_AON4__LOADSHADOWUNITDEL_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field loadShadowUnitDel_ovrVal */ +/** + * @defgroup swreg_aon_regs_core_loadShadowUnitDel_ovrVal_field loadShadowUnitDel_ovrVal_field + * @brief macros for field loadShadowUnitDel_ovrVal + * @details override value of the load for shadowUnitDel, bypassing fsmTop + * @{ + */ +#define SWREG_AON_AON4__LOADSHADOWUNITDEL_OVRVAL__SHIFT 11 +#define SWREG_AON_AON4__LOADSHADOWUNITDEL_OVRVAL__WIDTH 1 +#define SWREG_AON_AON4__LOADSHADOWUNITDEL_OVRVAL__MASK 0x00000800U +#define SWREG_AON_AON4__LOADSHADOWUNITDEL_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000800U) >> 11) +#define SWREG_AON_AON4__LOADSHADOWUNITDEL_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 11) & 0x00000800U) +#define SWREG_AON_AON4__LOADSHADOWUNITDEL_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((uint32_t)(src) <<\ + 11) & 0x00000800U) +#define SWREG_AON_AON4__LOADSHADOWUNITDEL_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 11) & ~0x00000800U))) +#define SWREG_AON_AON4__LOADSHADOWUNITDEL_OVRVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(1) << 11) +#define SWREG_AON_AON4__LOADSHADOWUNITDEL_OVRVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((uint32_t)(0) << 11) +#define SWREG_AON_AON4__LOADSHADOWUNITDEL_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field updateUnitDel_ovr */ +/** + * @defgroup swreg_aon_regs_core_updateUnitDel_ovr_field updateUnitDel_ovr_field + * @brief macros for field updateUnitDel_ovr + * @details override updateUnitDel + * @{ + */ +#define SWREG_AON_AON4__UPDATEUNITDEL_OVR__SHIFT 12 +#define SWREG_AON_AON4__UPDATEUNITDEL_OVR__WIDTH 1 +#define SWREG_AON_AON4__UPDATEUNITDEL_OVR__MASK 0x00001000U +#define SWREG_AON_AON4__UPDATEUNITDEL_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define SWREG_AON_AON4__UPDATEUNITDEL_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define SWREG_AON_AON4__UPDATEUNITDEL_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define SWREG_AON_AON4__UPDATEUNITDEL_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define SWREG_AON_AON4__UPDATEUNITDEL_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define SWREG_AON_AON4__UPDATEUNITDEL_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define SWREG_AON_AON4__UPDATEUNITDEL_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field updateUnitDel_ovrVal */ +/** + * @defgroup swreg_aon_regs_core_updateUnitDel_ovrVal_field updateUnitDel_ovrVal_field + * @brief macros for field updateUnitDel_ovrVal + * @details override value of updateUnitDel At the posedge it updates the unit delay for the clock used by the active FSM (tiny, simple or active)If the main FSM is used (or powered) and skipClkCal=1'b0, it performs a clock cal. Otherwise it loads clkUnitDelReg + * @{ + */ +#define SWREG_AON_AON4__UPDATEUNITDEL_OVRVAL__SHIFT 13 +#define SWREG_AON_AON4__UPDATEUNITDEL_OVRVAL__WIDTH 1 +#define SWREG_AON_AON4__UPDATEUNITDEL_OVRVAL__MASK 0x00002000U +#define SWREG_AON_AON4__UPDATEUNITDEL_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define SWREG_AON_AON4__UPDATEUNITDEL_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define SWREG_AON_AON4__UPDATEUNITDEL_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define SWREG_AON_AON4__UPDATEUNITDEL_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define SWREG_AON_AON4__UPDATEUNITDEL_OVRVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define SWREG_AON_AON4__UPDATEUNITDEL_OVRVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define SWREG_AON_AON4__UPDATEUNITDEL_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clkUnitDelReg */ +/** + * @defgroup swreg_aon_regs_core_clkUnitDelReg_field clkUnitDelReg_field + * @brief macros for field clkUnitDelReg + * @details unit delay for the active clock, to be used at the posedge of updateUnitDel if the main Fsm is powered down or skipClkCal=1'b1. Also the value coming out of reset. + * @{ + */ +#define SWREG_AON_AON4__CLKUNITDELREG__SHIFT 14 +#define SWREG_AON_AON4__CLKUNITDELREG__WIDTH 5 +#define SWREG_AON_AON4__CLKUNITDELREG__MASK 0x0007c000U +#define SWREG_AON_AON4__CLKUNITDELREG__READ(src) \ + (((uint32_t)(src)\ + & 0x0007c000U) >> 14) +#define SWREG_AON_AON4__CLKUNITDELREG__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0007c000U) +#define SWREG_AON_AON4__CLKUNITDELREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007c000U) | (((uint32_t)(src) <<\ + 14) & 0x0007c000U) +#define SWREG_AON_AON4__CLKUNITDELREG__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0007c000U))) +#define SWREG_AON_AON4__CLKUNITDELREG__RESET_VALUE 0x00000009U +/** @} */ + +/* macros for field tinySourceStore_ovr */ +/** + * @defgroup swreg_aon_regs_core_tinySourceStore_ovr_field tinySourceStore_ovr_field + * @brief macros for field tinySourceStore_ovr + * @details override tinySourceStore + * @{ + */ +#define SWREG_AON_AON4__TINYSOURCESTORE_OVR__SHIFT 19 +#define SWREG_AON_AON4__TINYSOURCESTORE_OVR__WIDTH 1 +#define SWREG_AON_AON4__TINYSOURCESTORE_OVR__MASK 0x00080000U +#define SWREG_AON_AON4__TINYSOURCESTORE_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define SWREG_AON_AON4__TINYSOURCESTORE_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define SWREG_AON_AON4__TINYSOURCESTORE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define SWREG_AON_AON4__TINYSOURCESTORE_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define SWREG_AON_AON4__TINYSOURCESTORE_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define SWREG_AON_AON4__TINYSOURCESTORE_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define SWREG_AON_AON4__TINYSOURCESTORE_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field tinySourceStore_ovrVal */ +/** + * @defgroup swreg_aon_regs_core_tinySourceStore_ovrVal_field tinySourceStore_ovrVal_field + * @brief macros for field tinySourceStore_ovrVal + * @details override value of tinySourceStore. If 1, the source during the tiny FSM will be the STORE, otherwise it will be the BATT + * @{ + */ +#define SWREG_AON_AON4__TINYSOURCESTORE_OVRVAL__SHIFT 20 +#define SWREG_AON_AON4__TINYSOURCESTORE_OVRVAL__WIDTH 1 +#define SWREG_AON_AON4__TINYSOURCESTORE_OVRVAL__MASK 0x00100000U +#define SWREG_AON_AON4__TINYSOURCESTORE_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00100000U) >> 20) +#define SWREG_AON_AON4__TINYSOURCESTORE_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00100000U) +#define SWREG_AON_AON4__TINYSOURCESTORE_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((uint32_t)(src) <<\ + 20) & 0x00100000U) +#define SWREG_AON_AON4__TINYSOURCESTORE_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00100000U))) +#define SWREG_AON_AON4__TINYSOURCESTORE_OVRVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(1) << 20) +#define SWREG_AON_AON4__TINYSOURCESTORE_OVRVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((uint32_t)(0) << 20) +#define SWREG_AON_AON4__TINYSOURCESTORE_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field pn_ovr */ +/** + * @defgroup swreg_aon_regs_core_pn_ovr_field pn_ovr_field + * @brief macros for field pn_ovr + * @details override enables for the N and P parts of the switches. Switch order:battP, battN, storeSrcP, storeSrcN, harvP, harvN, storeDstP, storeDstN, avddP, dvddP + * @{ + */ +#define SWREG_AON_AON4__PN_OVR__SHIFT 21 +#define SWREG_AON_AON4__PN_OVR__WIDTH 10 +#define SWREG_AON_AON4__PN_OVR__MASK 0x7fe00000U +#define SWREG_AON_AON4__PN_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x7fe00000U) >> 21) +#define SWREG_AON_AON4__PN_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x7fe00000U) +#define SWREG_AON_AON4__PN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7fe00000U) | (((uint32_t)(src) <<\ + 21) & 0x7fe00000U) +#define SWREG_AON_AON4__PN_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x7fe00000U))) +#define SWREG_AON_AON4__PN_OVR__RESET_VALUE 0x00000000U +/** @} */ +#define SWREG_AON_AON4__TYPE uint32_t +#define SWREG_AON_AON4__READ 0x7fffffffU +#define SWREG_AON_AON4__WRITE 0x7fffffffU +#define SWREG_AON_AON4__PRESERVED 0x00000000U +#define SWREG_AON_AON4__RESET_VALUE 0x00024000U + +#endif /* __SWREG_AON_AON4_MACRO__ */ + +/** @} end of aon4 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_AON_aon5 */ +/** + * @defgroup swreg_aon_regs_core_aon5 aon5 + * @brief swreg aon regs definitions. + * @{ + */ +#ifndef __SWREG_AON_AON5_MACRO__ +#define __SWREG_AON_AON5_MACRO__ + +/* macros for field pn_ovrVal */ +/** + * @defgroup swreg_aon_regs_core_pn_ovrVal_field pn_ovrVal_field + * @brief macros for field pn_ovrVal + * @details override values of the enables for the N and P parts of the switches + * @{ + */ +#define SWREG_AON_AON5__PN_OVRVAL__SHIFT 0 +#define SWREG_AON_AON5__PN_OVRVAL__WIDTH 10 +#define SWREG_AON_AON5__PN_OVRVAL__MASK 0x000003ffU +#define SWREG_AON_AON5__PN_OVRVAL__READ(src) ((uint32_t)(src) & 0x000003ffU) +#define SWREG_AON_AON5__PN_OVRVAL__WRITE(src) ((uint32_t)(src) & 0x000003ffU) +#define SWREG_AON_AON5__PN_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((uint32_t)(src) &\ + 0x000003ffU) +#define SWREG_AON_AON5__PN_OVRVAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000003ffU))) +#define SWREG_AON_AON5__PN_OVRVAL__RESET_VALUE 0x000003ffU +/** @} */ + +/* macros for field size */ +/** + * @defgroup swreg_aon_regs_core_size_field size_field + * @brief macros for field size + * @details switch size, with the following order:[19:18] battery [17:16] store, source side [15:14] harvest [13:12] ground, source side [11:10] store, destination side [9:8] avdd [7:6] vddio [5:4] vaux [3:2] dvdd [1:0] ground, destination side + * @{ + */ +#define SWREG_AON_AON5__SIZE__SHIFT 10 +#define SWREG_AON_AON5__SIZE__WIDTH 20 +#define SWREG_AON_AON5__SIZE__MASK 0x3ffffc00U +#define SWREG_AON_AON5__SIZE__READ(src) (((uint32_t)(src) & 0x3ffffc00U) >> 10) +#define SWREG_AON_AON5__SIZE__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x3ffffc00U) +#define SWREG_AON_AON5__SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ffffc00U) | (((uint32_t)(src) <<\ + 10) & 0x3ffffc00U) +#define SWREG_AON_AON5__SIZE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x3ffffc00U))) +#define SWREG_AON_AON5__SIZE__RESET_VALUE 0x000fffffU +/** @} */ + +/* macros for field delZCD1 */ +/** + * @defgroup swreg_aon_regs_core_delZCD1_field delZCD1_field + * @brief macros for field delZCD1 + * @details delay1 for ZCD + * @{ + */ +#define SWREG_AON_AON5__DELZCD1__SHIFT 30 +#define SWREG_AON_AON5__DELZCD1__WIDTH 2 +#define SWREG_AON_AON5__DELZCD1__MASK 0xc0000000U +#define SWREG_AON_AON5__DELZCD1__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define SWREG_AON_AON5__DELZCD1__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define SWREG_AON_AON5__DELZCD1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define SWREG_AON_AON5__DELZCD1__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define SWREG_AON_AON5__DELZCD1__RESET_VALUE 0x00000001U +/** @} */ +#define SWREG_AON_AON5__TYPE uint32_t +#define SWREG_AON_AON5__READ 0xffffffffU +#define SWREG_AON_AON5__WRITE 0xffffffffU +#define SWREG_AON_AON5__PRESERVED 0x00000000U +#define SWREG_AON_AON5__RESET_VALUE 0x7fffffffU + +#endif /* __SWREG_AON_AON5_MACRO__ */ + +/** @} end of aon5 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_AON_aon6 */ +/** + * @defgroup swreg_aon_regs_core_aon6 aon6 + * @brief swreg aon regs definitions. + * @{ + */ +#ifndef __SWREG_AON_AON6_MACRO__ +#define __SWREG_AON_AON6_MACRO__ + +/* macros for field delZCD2 */ +/** + * @defgroup swreg_aon_regs_core_delZCD2_field delZCD2_field + * @brief macros for field delZCD2 + * @details delay2 for ZCD + * @{ + */ +#define SWREG_AON_AON6__DELZCD2__SHIFT 0 +#define SWREG_AON_AON6__DELZCD2__WIDTH 2 +#define SWREG_AON_AON6__DELZCD2__MASK 0x00000003U +#define SWREG_AON_AON6__DELZCD2__READ(src) ((uint32_t)(src) & 0x00000003U) +#define SWREG_AON_AON6__DELZCD2__WRITE(src) ((uint32_t)(src) & 0x00000003U) +#define SWREG_AON_AON6__DELZCD2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((uint32_t)(src) &\ + 0x00000003U) +#define SWREG_AON_AON6__DELZCD2__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000003U))) +#define SWREG_AON_AON6__DELZCD2__RESET_VALUE 0x00000001U +/** @} */ + +/* macros for field delEnergDump */ +/** + * @defgroup swreg_aon_regs_core_delEnergDump_field delEnergDump_field + * @brief macros for field delEnergDump + * @details delay to avoid overlap between energize and dump + * @{ + */ +#define SWREG_AON_AON6__DELENERGDUMP__SHIFT 2 +#define SWREG_AON_AON6__DELENERGDUMP__WIDTH 4 +#define SWREG_AON_AON6__DELENERGDUMP__MASK 0x0000003cU +#define SWREG_AON_AON6__DELENERGDUMP__READ(src) \ + (((uint32_t)(src)\ + & 0x0000003cU) >> 2) +#define SWREG_AON_AON6__DELENERGDUMP__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x0000003cU) +#define SWREG_AON_AON6__DELENERGDUMP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003cU) | (((uint32_t)(src) <<\ + 2) & 0x0000003cU) +#define SWREG_AON_AON6__DELENERGDUMP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x0000003cU))) +#define SWREG_AON_AON6__DELENERGDUMP__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field ateTest */ +/** + * @defgroup swreg_aon_regs_core_ateTest_field ateTest_field + * @brief macros for field ateTest + * @details turn on ATE test mode + * @{ + */ +#define SWREG_AON_AON6__ATETEST__SHIFT 6 +#define SWREG_AON_AON6__ATETEST__WIDTH 1 +#define SWREG_AON_AON6__ATETEST__MASK 0x00000040U +#define SWREG_AON_AON6__ATETEST__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define SWREG_AON_AON6__ATETEST__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define SWREG_AON_AON6__ATETEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define SWREG_AON_AON6__ATETEST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define SWREG_AON_AON6__ATETEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define SWREG_AON_AON6__ATETEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define SWREG_AON_AON6__ATETEST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field digTestSel */ +/** + * @defgroup swreg_aon_regs_core_digTestSel_field digTestSel_field + * @brief macros for field digTestSel + * @details digital bus select signal, as follows:31-26: NC25: indCurrentSign24-20: request19: canHarvest18: mustHarvest17: vstoreGood16: vbattGood15-11: supReady10: suppliesReady9: harvesting8: swDump7: swSampleIndCurrent6: mode: Battery -> VSUP0, BuckBoost 5: mode: Battery -> VSUP0, Buck 4: mode: Store -> VSUP0, Buck 3: 2nd active clock generator 2: 1st active clock generator 1: top clock generator 0: NC + * @{ + */ +#define SWREG_AON_AON6__DIGTESTSEL__SHIFT 7 +#define SWREG_AON_AON6__DIGTESTSEL__WIDTH 5 +#define SWREG_AON_AON6__DIGTESTSEL__MASK 0x00000f80U +#define SWREG_AON_AON6__DIGTESTSEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000f80U) >> 7) +#define SWREG_AON_AON6__DIGTESTSEL__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000f80U) +#define SWREG_AON_AON6__DIGTESTSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f80U) | (((uint32_t)(src) <<\ + 7) & 0x00000f80U) +#define SWREG_AON_AON6__DIGTESTSEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000f80U))) +#define SWREG_AON_AON6__DIGTESTSEL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field spare */ +/** + * @defgroup swreg_aon_regs_core_spare_field spare_field + * @brief macros for field spare + * @details spare + * @{ + */ +#define SWREG_AON_AON6__SPARE__SHIFT 12 +#define SWREG_AON_AON6__SPARE__WIDTH 4 +#define SWREG_AON_AON6__SPARE__MASK 0x0000f000U +#define SWREG_AON_AON6__SPARE__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f000U) >> 12) +#define SWREG_AON_AON6__SPARE__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0000f000U) +#define SWREG_AON_AON6__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((uint32_t)(src) <<\ + 12) & 0x0000f000U) +#define SWREG_AON_AON6__SPARE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0000f000U))) +#define SWREG_AON_AON6__SPARE__RESET_VALUE 0x00000003U +/** @} */ +#define SWREG_AON_AON6__TYPE uint32_t +#define SWREG_AON_AON6__READ 0x0000ffffU +#define SWREG_AON_AON6__WRITE 0x0000ffffU +#define SWREG_AON_AON6__PRESERVED 0x00000000U +#define SWREG_AON_AON6__RESET_VALUE 0x0000300dU + +#endif /* __SWREG_AON_AON6_MACRO__ */ + +/** @} end of aon6 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_AON_readout */ +/** + * @defgroup swreg_aon_regs_core_readout readout + * @brief aon readout bits definitions. + * @{ + */ +#ifndef __SWREG_AON_READOUT_MACRO__ +#define __SWREG_AON_READOUT_MACRO__ + +/* macros for field stateTop */ +/** + * @defgroup swreg_aon_regs_core_stateTop_field stateTop_field + * @brief macros for field stateTop + * @details the fsmTop state + * @{ + */ +#define SWREG_AON_READOUT__STATETOP__SHIFT 0 +#define SWREG_AON_READOUT__STATETOP__WIDTH 4 +#define SWREG_AON_READOUT__STATETOP__MASK 0x0000000fU +#define SWREG_AON_READOUT__STATETOP__READ(src) ((uint32_t)(src) & 0x0000000fU) +#define SWREG_AON_READOUT__STATETOP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fsmCurrent */ +/** + * @defgroup swreg_aon_regs_core_fsmCurrent_field fsmCurrent_field + * @brief macros for field fsmCurrent + * @details the currently used fsm + * @{ + */ +#define SWREG_AON_READOUT__FSMCURRENT__SHIFT 4 +#define SWREG_AON_READOUT__FSMCURRENT__WIDTH 2 +#define SWREG_AON_READOUT__FSMCURRENT__MASK 0x00000030U +#define SWREG_AON_READOUT__FSMCURRENT__READ(src) \ + (((uint32_t)(src)\ + & 0x00000030U) >> 4) +#define SWREG_AON_READOUT__FSMCURRENT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fsmPrevious */ +/** + * @defgroup swreg_aon_regs_core_fsmPrevious_field fsmPrevious_field + * @brief macros for field fsmPrevious + * @details the previously used fsm + * @{ + */ +#define SWREG_AON_READOUT__FSMPREVIOUS__SHIFT 6 +#define SWREG_AON_READOUT__FSMPREVIOUS__WIDTH 2 +#define SWREG_AON_READOUT__FSMPREVIOUS__MASK 0x000000c0U +#define SWREG_AON_READOUT__FSMPREVIOUS__READ(src) \ + (((uint32_t)(src)\ + & 0x000000c0U) >> 6) +#define SWREG_AON_READOUT__FSMPREVIOUS__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field supReady */ +/** + * @defgroup swreg_aon_regs_core_supReady_field supReady_field + * @brief macros for field supReady + * @details the 5 supply ready signals + * @{ + */ +#define SWREG_AON_READOUT__SUPREADY__SHIFT 8 +#define SWREG_AON_READOUT__SUPREADY__WIDTH 5 +#define SWREG_AON_READOUT__SUPREADY__MASK 0x00001f00U +#define SWREG_AON_READOUT__SUPREADY__READ(src) \ + (((uint32_t)(src)\ + & 0x00001f00U) >> 8) +#define SWREG_AON_READOUT__SUPREADY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field suppliesReady */ +/** + * @defgroup swreg_aon_regs_core_suppliesReady_field suppliesReady_field + * @brief macros for field suppliesReady + * @details suppliesReady signal + * @{ + */ +#define SWREG_AON_READOUT__SUPPLIESREADY__SHIFT 13 +#define SWREG_AON_READOUT__SUPPLIESREADY__WIDTH 1 +#define SWREG_AON_READOUT__SUPPLIESREADY__MASK 0x00002000U +#define SWREG_AON_READOUT__SUPPLIESREADY__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define SWREG_AON_READOUT__SUPPLIESREADY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define SWREG_AON_READOUT__SUPPLIESREADY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define SWREG_AON_READOUT__SUPPLIESREADY__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clkUnitDelActive */ +/** + * @defgroup swreg_aon_regs_core_clkUnitDelActive_field clkUnitDelActive_field + * @brief macros for field clkUnitDelActive + * @details the unit delay of the active clock, possibly the result of the clock cal + * @{ + */ +#define SWREG_AON_READOUT__CLKUNITDELACTIVE__SHIFT 14 +#define SWREG_AON_READOUT__CLKUNITDELACTIVE__WIDTH 5 +#define SWREG_AON_READOUT__CLKUNITDELACTIVE__MASK 0x0007c000U +#define SWREG_AON_READOUT__CLKUNITDELACTIVE__READ(src) \ + (((uint32_t)(src)\ + & 0x0007c000U) >> 14) +#define SWREG_AON_READOUT__CLKUNITDELACTIVE__RESET_VALUE 0x00000000U +/** @} */ +#define SWREG_AON_READOUT__TYPE uint32_t +#define SWREG_AON_READOUT__READ 0x0007ffffU +#define SWREG_AON_READOUT__PRESERVED 0x00000000U +#define SWREG_AON_READOUT__RESET_VALUE 0x00000000U + +#endif /* __SWREG_AON_READOUT_MACRO__ */ + +/** @} end of readout */ + +/* macros for BlueprintGlobalNameSpace::SWREG_AON_core_id */ +/** + * @defgroup swreg_aon_regs_core_core_id core_id + * @brief Contains register fields associated with core_id. definitions. + * @{ + */ +#ifndef __SWREG_AON_CORE_ID_MACRO__ +#define __SWREG_AON_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup swreg_aon_regs_core_id_field id_field + * @brief macros for field id + * @details SWRA in ASCII + * @{ + */ +#define SWREG_AON_CORE_ID__ID__SHIFT 0 +#define SWREG_AON_CORE_ID__ID__WIDTH 32 +#define SWREG_AON_CORE_ID__ID__MASK 0xffffffffU +#define SWREG_AON_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define SWREG_AON_CORE_ID__ID__RESET_VALUE 0x53575241U +/** @} */ +#define SWREG_AON_CORE_ID__TYPE uint32_t +#define SWREG_AON_CORE_ID__READ 0xffffffffU +#define SWREG_AON_CORE_ID__PRESERVED 0x00000000U +#define SWREG_AON_CORE_ID__RESET_VALUE 0x53575241U + +#endif /* __SWREG_AON_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of SWREG_AON_REGS_CORE */ +#endif /* __REG_SWREG_AON_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/swreg_main_regs_core_macro.h b/ATM33xx-5/include/reg/swreg_main_regs_core_macro.h new file mode 100644 index 0000000..0c7315a --- /dev/null +++ b/ATM33xx-5/include/reg/swreg_main_regs_core_macro.h @@ -0,0 +1,2912 @@ +/* */ +/* File: swreg_main_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic swreg_main_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_SWREG_MAIN_REGS_CORE_H__ +#define __REG_SWREG_MAIN_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup SWREG_MAIN_REGS_CORE swreg_main_regs_core + * @ingroup AT_REG + * @brief swreg_main_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::SWREG_MAIN_main0 */ +/** + * @defgroup swreg_main_regs_core_main0 main0 + * @brief main swreg registers For fields that refer to the sources the order is: 2: BATT 1: STORE 0: HARV For fields that refer to the destinations the order is: 4: STORE 3: AVDD 2: VDDIO 1: VDDAUX 0: DVDD For fields that refer to the supplies the order is: 3: AVDD 2: VDDIO 1: VDDAUX 0: DVDD For fields that refer to the power transfer modes the order is: 14: STORE -> BATT13: BATT -> STORE12: HARV -> STORE11: HARV -> AVDD10: HARV -> VDDIO9: HARV -> VDDAUX8: HARV -> DVDD7: STORE -> AVDD6: STORE -> VDDIO5: STORE -> VDDAUX4: STORE -> DVDD3: BATT -> AVDD2: BATT -> VDDIO1: BATT -> VDDAUX0: BATT -> DVDD definitions. + * @{ + */ +#ifndef __SWREG_MAIN_MAIN0_MACRO__ +#define __SWREG_MAIN_MAIN0_MACRO__ + +/* macros for field enableGear_SH */ +/** + * @defgroup swreg_main_regs_core_enableGear_SH_field enableGear_SH_field + * @brief macros for field enableGear_SH + * @details enable using gears for the corresponding mode. Gears for (STORE -> BATT) are disabled. + * @{ + */ +#define SWREG_MAIN_MAIN0__ENABLEGEAR_SH__SHIFT 0 +#define SWREG_MAIN_MAIN0__ENABLEGEAR_SH__WIDTH 14 +#define SWREG_MAIN_MAIN0__ENABLEGEAR_SH__MASK 0x00003fffU +#define SWREG_MAIN_MAIN0__ENABLEGEAR_SH__READ(src) \ + ((uint32_t)(src)\ + & 0x00003fffU) +#define SWREG_MAIN_MAIN0__ENABLEGEAR_SH__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00003fffU) +#define SWREG_MAIN_MAIN0__ENABLEGEAR_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((uint32_t)(src) &\ + 0x00003fffU) +#define SWREG_MAIN_MAIN0__ENABLEGEAR_SH__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00003fffU))) +#define SWREG_MAIN_MAIN0__ENABLEGEAR_SH__RESET_VALUE 0x000020ffU +/** @} */ + +/* macros for field timeStepMax_SH */ +/** + * @defgroup swreg_main_regs_core_timeStepMax_SH_field timeStepMax_SH_field + * @brief macros for field timeStepMax_SH + * @details maximum time step used in steady state (x4+3) + * @{ + */ +#define SWREG_MAIN_MAIN0__TIMESTEPMAX_SH__SHIFT 14 +#define SWREG_MAIN_MAIN0__TIMESTEPMAX_SH__WIDTH 3 +#define SWREG_MAIN_MAIN0__TIMESTEPMAX_SH__MASK 0x0001c000U +#define SWREG_MAIN_MAIN0__TIMESTEPMAX_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x0001c000U) >> 14) +#define SWREG_MAIN_MAIN0__TIMESTEPMAX_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0001c000U) +#define SWREG_MAIN_MAIN0__TIMESTEPMAX_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((uint32_t)(src) <<\ + 14) & 0x0001c000U) +#define SWREG_MAIN_MAIN0__TIMESTEPMAX_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0001c000U))) +#define SWREG_MAIN_MAIN0__TIMESTEPMAX_SH__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field timeStepExitFullySettled_SH */ +/** + * @defgroup swreg_main_regs_core_timeStepExitFullySettled_SH_field timeStepExitFullySettled_SH_field + * @brief macros for field timeStepExitFullySettled_SH + * @details if the time step becomes higher than this value the fullySettled flag resets (x4+3) + * @{ + */ +#define SWREG_MAIN_MAIN0__TIMESTEPEXITFULLYSETTLED_SH__SHIFT 17 +#define SWREG_MAIN_MAIN0__TIMESTEPEXITFULLYSETTLED_SH__WIDTH 3 +#define SWREG_MAIN_MAIN0__TIMESTEPEXITFULLYSETTLED_SH__MASK 0x000e0000U +#define SWREG_MAIN_MAIN0__TIMESTEPEXITFULLYSETTLED_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x000e0000U) >> 17) +#define SWREG_MAIN_MAIN0__TIMESTEPEXITFULLYSETTLED_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x000e0000U) +#define SWREG_MAIN_MAIN0__TIMESTEPEXITFULLYSETTLED_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((uint32_t)(src) <<\ + 17) & 0x000e0000U) +#define SWREG_MAIN_MAIN0__TIMESTEPEXITFULLYSETTLED_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x000e0000U))) +#define SWREG_MAIN_MAIN0__TIMESTEPEXITFULLYSETTLED_SH__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field timePlanShort_SH */ +/** + * @defgroup swreg_main_regs_core_timePlanShort_SH_field timePlanShort_SH_field + * @brief macros for field timePlanShort_SH + * @details length of a short plan state + * @{ + */ +#define SWREG_MAIN_MAIN0__TIMEPLANSHORT_SH__SHIFT 20 +#define SWREG_MAIN_MAIN0__TIMEPLANSHORT_SH__WIDTH 2 +#define SWREG_MAIN_MAIN0__TIMEPLANSHORT_SH__MASK 0x00300000U +#define SWREG_MAIN_MAIN0__TIMEPLANSHORT_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00300000U) >> 20) +#define SWREG_MAIN_MAIN0__TIMEPLANSHORT_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00300000U) +#define SWREG_MAIN_MAIN0__TIMEPLANSHORT_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00300000U) | (((uint32_t)(src) <<\ + 20) & 0x00300000U) +#define SWREG_MAIN_MAIN0__TIMEPLANSHORT_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00300000U))) +#define SWREG_MAIN_MAIN0__TIMEPLANSHORT_SH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field attemptIncrGear_SH */ +/** + * @defgroup swreg_main_regs_core_attemptIncrGear_SH_field attemptIncrGear_SH_field + * @brief macros for field attemptIncrGear_SH + * @details number of attempts after which if the request is not satisfied the gear increases + * @{ + */ +#define SWREG_MAIN_MAIN0__ATTEMPTINCRGEAR_SH__SHIFT 22 +#define SWREG_MAIN_MAIN0__ATTEMPTINCRGEAR_SH__WIDTH 3 +#define SWREG_MAIN_MAIN0__ATTEMPTINCRGEAR_SH__MASK 0x01c00000U +#define SWREG_MAIN_MAIN0__ATTEMPTINCRGEAR_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x01c00000U) >> 22) +#define SWREG_MAIN_MAIN0__ATTEMPTINCRGEAR_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x01c00000U) +#define SWREG_MAIN_MAIN0__ATTEMPTINCRGEAR_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01c00000U) | (((uint32_t)(src) <<\ + 22) & 0x01c00000U) +#define SWREG_MAIN_MAIN0__ATTEMPTINCRGEAR_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x01c00000U))) +#define SWREG_MAIN_MAIN0__ATTEMPTINCRGEAR_SH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field attemptHopIncrGear_SH */ +/** + * @defgroup swreg_main_regs_core_attemptHopIncrGear_SH_field attemptHopIncrGear_SH_field + * @brief macros for field attemptHopIncrGear_SH + * @details number of attempts after which if the request is not satisfied the gear increases when the frequency has hopped + * @{ + */ +#define SWREG_MAIN_MAIN0__ATTEMPTHOPINCRGEAR_SH__SHIFT 25 +#define SWREG_MAIN_MAIN0__ATTEMPTHOPINCRGEAR_SH__WIDTH 3 +#define SWREG_MAIN_MAIN0__ATTEMPTHOPINCRGEAR_SH__MASK 0x0e000000U +#define SWREG_MAIN_MAIN0__ATTEMPTHOPINCRGEAR_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x0e000000U) >> 25) +#define SWREG_MAIN_MAIN0__ATTEMPTHOPINCRGEAR_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x0e000000U) +#define SWREG_MAIN_MAIN0__ATTEMPTHOPINCRGEAR_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0e000000U) | (((uint32_t)(src) <<\ + 25) & 0x0e000000U) +#define SWREG_MAIN_MAIN0__ATTEMPTHOPINCRGEAR_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x0e000000U))) +#define SWREG_MAIN_MAIN0__ATTEMPTHOPINCRGEAR_SH__RESET_VALUE 0x00000000U +/** @} */ +#define SWREG_MAIN_MAIN0__TYPE uint32_t +#define SWREG_MAIN_MAIN0__READ 0x0fffffffU +#define SWREG_MAIN_MAIN0__WRITE 0x0fffffffU +#define SWREG_MAIN_MAIN0__PRESERVED 0x00000000U +#define SWREG_MAIN_MAIN0__RESET_VALUE 0x0009e0ffU + +#endif /* __SWREG_MAIN_MAIN0_MACRO__ */ + +/** @} end of main0 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_MAIN_main1 */ +/** + * @defgroup swreg_main_regs_core_main1 main1 + * @brief main swreg registers definitions. + * @{ + */ +#ifndef __SWREG_MAIN_MAIN1_MACRO__ +#define __SWREG_MAIN_MAIN1_MACRO__ + +/* macros for field timeTargetCharge_SH */ +/** + * @defgroup swreg_main_regs_core_timeTargetCharge_SH_field timeTargetCharge_SH_field + * @brief macros for field timeTargetCharge_SH + * @details target time for charging store from battery and battery from store + * @{ + */ +#define SWREG_MAIN_MAIN1__TIMETARGETCHARGE_SH__SHIFT 0 +#define SWREG_MAIN_MAIN1__TIMETARGETCHARGE_SH__WIDTH 7 +#define SWREG_MAIN_MAIN1__TIMETARGETCHARGE_SH__MASK 0x0000007fU +#define SWREG_MAIN_MAIN1__TIMETARGETCHARGE_SH__READ(src) \ + ((uint32_t)(src)\ + & 0x0000007fU) +#define SWREG_MAIN_MAIN1__TIMETARGETCHARGE_SH__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000007fU) +#define SWREG_MAIN_MAIN1__TIMETARGETCHARGE_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((uint32_t)(src) &\ + 0x0000007fU) +#define SWREG_MAIN_MAIN1__TIMETARGETCHARGE_SH__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000007fU))) +#define SWREG_MAIN_MAIN1__TIMETARGETCHARGE_SH__RESET_VALUE 0x0000001eU +/** @} */ + +/* macros for field targetIsDumpCharge_SH */ +/** + * @defgroup swreg_main_regs_core_targetIsDumpCharge_SH_field targetIsDumpCharge_SH_field + * @brief macros for field targetIsDumpCharge_SH + * @details if 1 the target for the battery to store or store to battery mode is the dump time, otherwise it is the energize time + * @{ + */ +#define SWREG_MAIN_MAIN1__TARGETISDUMPCHARGE_SH__SHIFT 7 +#define SWREG_MAIN_MAIN1__TARGETISDUMPCHARGE_SH__WIDTH 1 +#define SWREG_MAIN_MAIN1__TARGETISDUMPCHARGE_SH__MASK 0x00000080U +#define SWREG_MAIN_MAIN1__TARGETISDUMPCHARGE_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define SWREG_MAIN_MAIN1__TARGETISDUMPCHARGE_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define SWREG_MAIN_MAIN1__TARGETISDUMPCHARGE_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define SWREG_MAIN_MAIN1__TARGETISDUMPCHARGE_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define SWREG_MAIN_MAIN1__TARGETISDUMPCHARGE_SH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define SWREG_MAIN_MAIN1__TARGETISDUMPCHARGE_SH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define SWREG_MAIN_MAIN1__TARGETISDUMPCHARGE_SH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field chargeStoreLimit_SH */ +/** + * @defgroup swreg_main_regs_core_chargeStoreLimit_SH_field chargeStoreLimit_SH_field + * @brief macros for field chargeStoreLimit_SH + * @details max number of charging cycles from battery or harvest to store per RTC period. 6'd63 is interpreted as no limit. + * @{ + */ +#define SWREG_MAIN_MAIN1__CHARGESTORELIMIT_SH__SHIFT 8 +#define SWREG_MAIN_MAIN1__CHARGESTORELIMIT_SH__WIDTH 6 +#define SWREG_MAIN_MAIN1__CHARGESTORELIMIT_SH__MASK 0x00003f00U +#define SWREG_MAIN_MAIN1__CHARGESTORELIMIT_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00003f00U) >> 8) +#define SWREG_MAIN_MAIN1__CHARGESTORELIMIT_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00003f00U) +#define SWREG_MAIN_MAIN1__CHARGESTORELIMIT_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((uint32_t)(src) <<\ + 8) & 0x00003f00U) +#define SWREG_MAIN_MAIN1__CHARGESTORELIMIT_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00003f00U))) +#define SWREG_MAIN_MAIN1__CHARGESTORELIMIT_SH__RESET_VALUE 0x0000003fU +/** @} */ + +/* macros for field chargeBattLimit_SH */ +/** + * @defgroup swreg_main_regs_core_chargeBattLimit_SH_field chargeBattLimit_SH_field + * @brief macros for field chargeBattLimit_SH + * @details max number of charging cycles from store or battery per RTC period. 6'd63 is interpreted as no limit. + * @{ + */ +#define SWREG_MAIN_MAIN1__CHARGEBATTLIMIT_SH__SHIFT 14 +#define SWREG_MAIN_MAIN1__CHARGEBATTLIMIT_SH__WIDTH 6 +#define SWREG_MAIN_MAIN1__CHARGEBATTLIMIT_SH__MASK 0x000fc000U +#define SWREG_MAIN_MAIN1__CHARGEBATTLIMIT_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x000fc000U) >> 14) +#define SWREG_MAIN_MAIN1__CHARGEBATTLIMIT_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x000fc000U) +#define SWREG_MAIN_MAIN1__CHARGEBATTLIMIT_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fc000U) | (((uint32_t)(src) <<\ + 14) & 0x000fc000U) +#define SWREG_MAIN_MAIN1__CHARGEBATTLIMIT_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x000fc000U))) +#define SWREG_MAIN_MAIN1__CHARGEBATTLIMIT_SH__RESET_VALUE 0x0000003fU +/** @} */ + +/* macros for field timeMax_SH */ +/** + * @defgroup swreg_main_regs_core_timeMax_SH_field timeMax_SH_field + * @brief macros for field timeMax_SH + * @details The max energize or dump time allowed for zero gear (x2+1) + * @{ + */ +#define SWREG_MAIN_MAIN1__TIMEMAX_SH__SHIFT 20 +#define SWREG_MAIN_MAIN1__TIMEMAX_SH__WIDTH 7 +#define SWREG_MAIN_MAIN1__TIMEMAX_SH__MASK 0x07f00000U +#define SWREG_MAIN_MAIN1__TIMEMAX_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x07f00000U) >> 20) +#define SWREG_MAIN_MAIN1__TIMEMAX_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x07f00000U) +#define SWREG_MAIN_MAIN1__TIMEMAX_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07f00000U) | (((uint32_t)(src) <<\ + 20) & 0x07f00000U) +#define SWREG_MAIN_MAIN1__TIMEMAX_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x07f00000U))) +#define SWREG_MAIN_MAIN1__TIMEMAX_SH__RESET_VALUE 0x0000007fU +/** @} */ + +/* macros for field gearMax_vstore_SH */ +/** + * @defgroup swreg_main_regs_core_gearMax_vstore_SH_field gearMax_vstore_SH_field + * @brief macros for field gearMax_vstore_SH + * @details max gear when the destination is store + * @{ + */ +#define SWREG_MAIN_MAIN1__GEARMAX_VSTORE_SH__SHIFT 27 +#define SWREG_MAIN_MAIN1__GEARMAX_VSTORE_SH__WIDTH 4 +#define SWREG_MAIN_MAIN1__GEARMAX_VSTORE_SH__MASK 0x78000000U +#define SWREG_MAIN_MAIN1__GEARMAX_VSTORE_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x78000000U) >> 27) +#define SWREG_MAIN_MAIN1__GEARMAX_VSTORE_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 27) & 0x78000000U) +#define SWREG_MAIN_MAIN1__GEARMAX_VSTORE_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x78000000U) | (((uint32_t)(src) <<\ + 27) & 0x78000000U) +#define SWREG_MAIN_MAIN1__GEARMAX_VSTORE_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 27) & ~0x78000000U))) +#define SWREG_MAIN_MAIN1__GEARMAX_VSTORE_SH__RESET_VALUE 0x0000000fU +/** @} */ +#define SWREG_MAIN_MAIN1__TYPE uint32_t +#define SWREG_MAIN_MAIN1__READ 0x7fffffffU +#define SWREG_MAIN_MAIN1__WRITE 0x7fffffffU +#define SWREG_MAIN_MAIN1__PRESERVED 0x00000000U +#define SWREG_MAIN_MAIN1__RESET_VALUE 0x7fffff1eU + +#endif /* __SWREG_MAIN_MAIN1_MACRO__ */ + +/** @} end of main1 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_MAIN_main2 */ +/** + * @defgroup swreg_main_regs_core_main2 main2 + * @brief main swreg registers definitions. + * @{ + */ +#ifndef __SWREG_MAIN_MAIN2_MACRO__ +#define __SWREG_MAIN_MAIN2_MACRO__ + +/* macros for field gearUpMax_vstore_SH */ +/** + * @defgroup swreg_main_regs_core_gearUpMax_vstore_SH_field gearUpMax_vstore_SH_field + * @brief macros for field gearUpMax_vstore_SH + * @details max gear up when the destination is store + * @{ + */ +#define SWREG_MAIN_MAIN2__GEARUPMAX_VSTORE_SH__SHIFT 0 +#define SWREG_MAIN_MAIN2__GEARUPMAX_VSTORE_SH__WIDTH 4 +#define SWREG_MAIN_MAIN2__GEARUPMAX_VSTORE_SH__MASK 0x0000000fU +#define SWREG_MAIN_MAIN2__GEARUPMAX_VSTORE_SH__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define SWREG_MAIN_MAIN2__GEARUPMAX_VSTORE_SH__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define SWREG_MAIN_MAIN2__GEARUPMAX_VSTORE_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define SWREG_MAIN_MAIN2__GEARUPMAX_VSTORE_SH__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define SWREG_MAIN_MAIN2__GEARUPMAX_VSTORE_SH__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field gearMax_avdd_SH */ +/** + * @defgroup swreg_main_regs_core_gearMax_avdd_SH_field gearMax_avdd_SH_field + * @brief macros for field gearMax_avdd_SH + * @details max gear when the destination is avdd + * @{ + */ +#define SWREG_MAIN_MAIN2__GEARMAX_AVDD_SH__SHIFT 4 +#define SWREG_MAIN_MAIN2__GEARMAX_AVDD_SH__WIDTH 4 +#define SWREG_MAIN_MAIN2__GEARMAX_AVDD_SH__MASK 0x000000f0U +#define SWREG_MAIN_MAIN2__GEARMAX_AVDD_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define SWREG_MAIN_MAIN2__GEARMAX_AVDD_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x000000f0U) +#define SWREG_MAIN_MAIN2__GEARMAX_AVDD_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((uint32_t)(src) <<\ + 4) & 0x000000f0U) +#define SWREG_MAIN_MAIN2__GEARMAX_AVDD_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x000000f0U))) +#define SWREG_MAIN_MAIN2__GEARMAX_AVDD_SH__RESET_VALUE 0x0000000fU +/** @} */ + +/* macros for field gearUpMax_avdd_SH */ +/** + * @defgroup swreg_main_regs_core_gearUpMax_avdd_SH_field gearUpMax_avdd_SH_field + * @brief macros for field gearUpMax_avdd_SH + * @details max gear up when the destination is avdd + * @{ + */ +#define SWREG_MAIN_MAIN2__GEARUPMAX_AVDD_SH__SHIFT 8 +#define SWREG_MAIN_MAIN2__GEARUPMAX_AVDD_SH__WIDTH 4 +#define SWREG_MAIN_MAIN2__GEARUPMAX_AVDD_SH__MASK 0x00000f00U +#define SWREG_MAIN_MAIN2__GEARUPMAX_AVDD_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00000f00U) >> 8) +#define SWREG_MAIN_MAIN2__GEARUPMAX_AVDD_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000f00U) +#define SWREG_MAIN_MAIN2__GEARUPMAX_AVDD_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((uint32_t)(src) <<\ + 8) & 0x00000f00U) +#define SWREG_MAIN_MAIN2__GEARUPMAX_AVDD_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000f00U))) +#define SWREG_MAIN_MAIN2__GEARUPMAX_AVDD_SH__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field gearMax_vddio_SH */ +/** + * @defgroup swreg_main_regs_core_gearMax_vddio_SH_field gearMax_vddio_SH_field + * @brief macros for field gearMax_vddio_SH + * @details max gear when the destination is vddio + * @{ + */ +#define SWREG_MAIN_MAIN2__GEARMAX_VDDIO_SH__SHIFT 12 +#define SWREG_MAIN_MAIN2__GEARMAX_VDDIO_SH__WIDTH 4 +#define SWREG_MAIN_MAIN2__GEARMAX_VDDIO_SH__MASK 0x0000f000U +#define SWREG_MAIN_MAIN2__GEARMAX_VDDIO_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x0000f000U) >> 12) +#define SWREG_MAIN_MAIN2__GEARMAX_VDDIO_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x0000f000U) +#define SWREG_MAIN_MAIN2__GEARMAX_VDDIO_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((uint32_t)(src) <<\ + 12) & 0x0000f000U) +#define SWREG_MAIN_MAIN2__GEARMAX_VDDIO_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x0000f000U))) +#define SWREG_MAIN_MAIN2__GEARMAX_VDDIO_SH__RESET_VALUE 0x0000000fU +/** @} */ + +/* macros for field gearUpMax_vddio_SH */ +/** + * @defgroup swreg_main_regs_core_gearUpMax_vddio_SH_field gearUpMax_vddio_SH_field + * @brief macros for field gearUpMax_vddio_SH + * @details max gear up when the destination is vddio + * @{ + */ +#define SWREG_MAIN_MAIN2__GEARUPMAX_VDDIO_SH__SHIFT 16 +#define SWREG_MAIN_MAIN2__GEARUPMAX_VDDIO_SH__WIDTH 4 +#define SWREG_MAIN_MAIN2__GEARUPMAX_VDDIO_SH__MASK 0x000f0000U +#define SWREG_MAIN_MAIN2__GEARUPMAX_VDDIO_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x000f0000U) >> 16) +#define SWREG_MAIN_MAIN2__GEARUPMAX_VDDIO_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x000f0000U) +#define SWREG_MAIN_MAIN2__GEARUPMAX_VDDIO_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((uint32_t)(src) <<\ + 16) & 0x000f0000U) +#define SWREG_MAIN_MAIN2__GEARUPMAX_VDDIO_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x000f0000U))) +#define SWREG_MAIN_MAIN2__GEARUPMAX_VDDIO_SH__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field gearMax_vaux_SH */ +/** + * @defgroup swreg_main_regs_core_gearMax_vaux_SH_field gearMax_vaux_SH_field + * @brief macros for field gearMax_vaux_SH + * @details max gear when the destination is vaux + * @{ + */ +#define SWREG_MAIN_MAIN2__GEARMAX_VAUX_SH__SHIFT 20 +#define SWREG_MAIN_MAIN2__GEARMAX_VAUX_SH__WIDTH 4 +#define SWREG_MAIN_MAIN2__GEARMAX_VAUX_SH__MASK 0x00f00000U +#define SWREG_MAIN_MAIN2__GEARMAX_VAUX_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00f00000U) >> 20) +#define SWREG_MAIN_MAIN2__GEARMAX_VAUX_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00f00000U) +#define SWREG_MAIN_MAIN2__GEARMAX_VAUX_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f00000U) | (((uint32_t)(src) <<\ + 20) & 0x00f00000U) +#define SWREG_MAIN_MAIN2__GEARMAX_VAUX_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00f00000U))) +#define SWREG_MAIN_MAIN2__GEARMAX_VAUX_SH__RESET_VALUE 0x0000000fU +/** @} */ + +/* macros for field gearUpMax_vaux_SH */ +/** + * @defgroup swreg_main_regs_core_gearUpMax_vaux_SH_field gearUpMax_vaux_SH_field + * @brief macros for field gearUpMax_vaux_SH + * @details max gear up when the destination is vaux + * @{ + */ +#define SWREG_MAIN_MAIN2__GEARUPMAX_VAUX_SH__SHIFT 24 +#define SWREG_MAIN_MAIN2__GEARUPMAX_VAUX_SH__WIDTH 4 +#define SWREG_MAIN_MAIN2__GEARUPMAX_VAUX_SH__MASK 0x0f000000U +#define SWREG_MAIN_MAIN2__GEARUPMAX_VAUX_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x0f000000U) >> 24) +#define SWREG_MAIN_MAIN2__GEARUPMAX_VAUX_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 24) & 0x0f000000U) +#define SWREG_MAIN_MAIN2__GEARUPMAX_VAUX_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f000000U) | (((uint32_t)(src) <<\ + 24) & 0x0f000000U) +#define SWREG_MAIN_MAIN2__GEARUPMAX_VAUX_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 24) & ~0x0f000000U))) +#define SWREG_MAIN_MAIN2__GEARUPMAX_VAUX_SH__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field gearMax_dvdd_SH */ +/** + * @defgroup swreg_main_regs_core_gearMax_dvdd_SH_field gearMax_dvdd_SH_field + * @brief macros for field gearMax_dvdd_SH + * @details max gear when the destination is dvdd + * @{ + */ +#define SWREG_MAIN_MAIN2__GEARMAX_DVDD_SH__SHIFT 28 +#define SWREG_MAIN_MAIN2__GEARMAX_DVDD_SH__WIDTH 4 +#define SWREG_MAIN_MAIN2__GEARMAX_DVDD_SH__MASK 0xf0000000U +#define SWREG_MAIN_MAIN2__GEARMAX_DVDD_SH__READ(src) \ + (((uint32_t)(src)\ + & 0xf0000000U) >> 28) +#define SWREG_MAIN_MAIN2__GEARMAX_DVDD_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0xf0000000U) +#define SWREG_MAIN_MAIN2__GEARMAX_DVDD_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf0000000U) | (((uint32_t)(src) <<\ + 28) & 0xf0000000U) +#define SWREG_MAIN_MAIN2__GEARMAX_DVDD_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0xf0000000U))) +#define SWREG_MAIN_MAIN2__GEARMAX_DVDD_SH__RESET_VALUE 0x0000000fU +/** @} */ +#define SWREG_MAIN_MAIN2__TYPE uint32_t +#define SWREG_MAIN_MAIN2__READ 0xffffffffU +#define SWREG_MAIN_MAIN2__WRITE 0xffffffffU +#define SWREG_MAIN_MAIN2__PRESERVED 0x00000000U +#define SWREG_MAIN_MAIN2__RESET_VALUE 0xf6f6f6f6U + +#endif /* __SWREG_MAIN_MAIN2_MACRO__ */ + +/** @} end of main2 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_MAIN_main3 */ +/** + * @defgroup swreg_main_regs_core_main3 main3 + * @brief main swreg registers definitions. + * @{ + */ +#ifndef __SWREG_MAIN_MAIN3_MACRO__ +#define __SWREG_MAIN_MAIN3_MACRO__ + +/* macros for field gearUpMax_dvdd_SH */ +/** + * @defgroup swreg_main_regs_core_gearUpMax_dvdd_SH_field gearUpMax_dvdd_SH_field + * @brief macros for field gearUpMax_dvdd_SH + * @details max gear up when the destination is dvdd + * @{ + */ +#define SWREG_MAIN_MAIN3__GEARUPMAX_DVDD_SH__SHIFT 0 +#define SWREG_MAIN_MAIN3__GEARUPMAX_DVDD_SH__WIDTH 4 +#define SWREG_MAIN_MAIN3__GEARUPMAX_DVDD_SH__MASK 0x0000000fU +#define SWREG_MAIN_MAIN3__GEARUPMAX_DVDD_SH__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define SWREG_MAIN_MAIN3__GEARUPMAX_DVDD_SH__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define SWREG_MAIN_MAIN3__GEARUPMAX_DVDD_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((uint32_t)(src) &\ + 0x0000000fU) +#define SWREG_MAIN_MAIN3__GEARUPMAX_DVDD_SH__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000000fU))) +#define SWREG_MAIN_MAIN3__GEARUPMAX_DVDD_SH__RESET_VALUE 0x00000006U +/** @} */ + +/* macros for field gearIncrThrToDecr_SH */ +/** + * @defgroup swreg_main_regs_core_gearIncrThrToDecr_SH_field gearIncrThrToDecr_SH_field + * @brief macros for field gearIncrThrToDecr_SH + * @details after so many gear sucessive increases it will attemp a decrease + * @{ + */ +#define SWREG_MAIN_MAIN3__GEARINCRTHRTODECR_SH__SHIFT 4 +#define SWREG_MAIN_MAIN3__GEARINCRTHRTODECR_SH__WIDTH 2 +#define SWREG_MAIN_MAIN3__GEARINCRTHRTODECR_SH__MASK 0x00000030U +#define SWREG_MAIN_MAIN3__GEARINCRTHRTODECR_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00000030U) >> 4) +#define SWREG_MAIN_MAIN3__GEARINCRTHRTODECR_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000030U) +#define SWREG_MAIN_MAIN3__GEARINCRTHRTODECR_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((uint32_t)(src) <<\ + 4) & 0x00000030U) +#define SWREG_MAIN_MAIN3__GEARINCRTHRTODECR_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000030U))) +#define SWREG_MAIN_MAIN3__GEARINCRTHRTODECR_SH__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field gearIncrAdditional_SH */ +/** + * @defgroup swreg_main_regs_core_gearIncrAdditional_SH_field gearIncrAdditional_SH_field + * @brief macros for field gearIncrAdditional_SH + * @details additional gear increase after decrease and bouncing back up + * @{ + */ +#define SWREG_MAIN_MAIN3__GEARINCRADDITIONAL_SH__SHIFT 6 +#define SWREG_MAIN_MAIN3__GEARINCRADDITIONAL_SH__WIDTH 2 +#define SWREG_MAIN_MAIN3__GEARINCRADDITIONAL_SH__MASK 0x000000c0U +#define SWREG_MAIN_MAIN3__GEARINCRADDITIONAL_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x000000c0U) >> 6) +#define SWREG_MAIN_MAIN3__GEARINCRADDITIONAL_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000000c0U) +#define SWREG_MAIN_MAIN3__GEARINCRADDITIONAL_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((uint32_t)(src) <<\ + 6) & 0x000000c0U) +#define SWREG_MAIN_MAIN3__GEARINCRADDITIONAL_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000000c0U))) +#define SWREG_MAIN_MAIN3__GEARINCRADDITIONAL_SH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field disableFastGearDecr_SH */ +/** + * @defgroup swreg_main_regs_core_disableFastGearDecr_SH_field disableFastGearDecr_SH_field + * @brief macros for field disableFastGearDecr_SH + * @details disable fast gear decrease + * @{ + */ +#define SWREG_MAIN_MAIN3__DISABLEFASTGEARDECR_SH__SHIFT 8 +#define SWREG_MAIN_MAIN3__DISABLEFASTGEARDECR_SH__WIDTH 1 +#define SWREG_MAIN_MAIN3__DISABLEFASTGEARDECR_SH__MASK 0x00000100U +#define SWREG_MAIN_MAIN3__DISABLEFASTGEARDECR_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define SWREG_MAIN_MAIN3__DISABLEFASTGEARDECR_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define SWREG_MAIN_MAIN3__DISABLEFASTGEARDECR_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define SWREG_MAIN_MAIN3__DISABLEFASTGEARDECR_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define SWREG_MAIN_MAIN3__DISABLEFASTGEARDECR_SH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define SWREG_MAIN_MAIN3__DISABLEFASTGEARDECR_SH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define SWREG_MAIN_MAIN3__DISABLEFASTGEARDECR_SH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field rtcCountMax_SH */ +/** + * @defgroup swreg_main_regs_core_rtcCountMax_SH_field rtcCountMax_SH_field + * @brief macros for field rtcCountMax_SH + * @details when disableFastGearDecr_SH=1, all gears are decreased by 1 every 4*(rtcCountMax_SH+1) rtc clock periods.the rtc clock period is 32KHz divided by (divCk32+1). 7 with divCk32=0 provides ~1 ms intervals. + * @{ + */ +#define SWREG_MAIN_MAIN3__RTCCOUNTMAX_SH__SHIFT 9 +#define SWREG_MAIN_MAIN3__RTCCOUNTMAX_SH__WIDTH 4 +#define SWREG_MAIN_MAIN3__RTCCOUNTMAX_SH__MASK 0x00001e00U +#define SWREG_MAIN_MAIN3__RTCCOUNTMAX_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00001e00U) >> 9) +#define SWREG_MAIN_MAIN3__RTCCOUNTMAX_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00001e00U) +#define SWREG_MAIN_MAIN3__RTCCOUNTMAX_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001e00U) | (((uint32_t)(src) <<\ + 9) & 0x00001e00U) +#define SWREG_MAIN_MAIN3__RTCCOUNTMAX_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00001e00U))) +#define SWREG_MAIN_MAIN3__RTCCOUNTMAX_SH__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field historyPeriods_SH */ +/** + * @defgroup swreg_main_regs_core_historyPeriods_SH_field historyPeriods_SH_field + * @brief macros for field historyPeriods_SH + * @details The sum of switching events (freqCountSum) per destination is counted for historyPeriods_SH periods of the RTC clock. Max valid value is 4. freqCountSum is used for frequency hoping and fast gear decrease. + * @{ + */ +#define SWREG_MAIN_MAIN3__HISTORYPERIODS_SH__SHIFT 13 +#define SWREG_MAIN_MAIN3__HISTORYPERIODS_SH__WIDTH 3 +#define SWREG_MAIN_MAIN3__HISTORYPERIODS_SH__MASK 0x0000e000U +#define SWREG_MAIN_MAIN3__HISTORYPERIODS_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x0000e000U) >> 13) +#define SWREG_MAIN_MAIN3__HISTORYPERIODS_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x0000e000U) +#define SWREG_MAIN_MAIN3__HISTORYPERIODS_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((uint32_t)(src) <<\ + 13) & 0x0000e000U) +#define SWREG_MAIN_MAIN3__HISTORYPERIODS_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x0000e000U))) +#define SWREG_MAIN_MAIN3__HISTORYPERIODS_SH__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field hopEnable_SH */ +/** + * @defgroup swreg_main_regs_core_hopEnable_SH_field hopEnable_SH_field + * @brief macros for field hopEnable_SH + * @details enable frequency hopping + * @{ + */ +#define SWREG_MAIN_MAIN3__HOPENABLE_SH__SHIFT 16 +#define SWREG_MAIN_MAIN3__HOPENABLE_SH__WIDTH 1 +#define SWREG_MAIN_MAIN3__HOPENABLE_SH__MASK 0x00010000U +#define SWREG_MAIN_MAIN3__HOPENABLE_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define SWREG_MAIN_MAIN3__HOPENABLE_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define SWREG_MAIN_MAIN3__HOPENABLE_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define SWREG_MAIN_MAIN3__HOPENABLE_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define SWREG_MAIN_MAIN3__HOPENABLE_SH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define SWREG_MAIN_MAIN3__HOPENABLE_SH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define SWREG_MAIN_MAIN3__HOPENABLE_SH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hopConditionRepeat_SH */ +/** + * @defgroup swreg_main_regs_core_hopConditionRepeat_SH_field hopConditionRepeat_SH_field + * @brief macros for field hopConditionRepeat_SH + * @details the condition [abs(freqcountsum - freqcountsumtoavoid) <= hopFreqCountTol] has to be met for so many successive RTC clock periods to trigger frequency hopping + * @{ + */ +#define SWREG_MAIN_MAIN3__HOPCONDITIONREPEAT_SH__SHIFT 17 +#define SWREG_MAIN_MAIN3__HOPCONDITIONREPEAT_SH__WIDTH 3 +#define SWREG_MAIN_MAIN3__HOPCONDITIONREPEAT_SH__MASK 0x000e0000U +#define SWREG_MAIN_MAIN3__HOPCONDITIONREPEAT_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x000e0000U) >> 17) +#define SWREG_MAIN_MAIN3__HOPCONDITIONREPEAT_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x000e0000U) +#define SWREG_MAIN_MAIN3__HOPCONDITIONREPEAT_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((uint32_t)(src) <<\ + 17) & 0x000e0000U) +#define SWREG_MAIN_MAIN3__HOPCONDITIONREPEAT_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x000e0000U))) +#define SWREG_MAIN_MAIN3__HOPCONDITIONREPEAT_SH__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field hopGearMaxIncr_SH */ +/** + * @defgroup swreg_main_regs_core_hopGearMaxIncr_SH_field hopGearMaxIncr_SH_field + * @brief macros for field hopGearMaxIncr_SH + * @details if the gear increases so many times after the frequency has hopped, it exits frequency hopping + * @{ + */ +#define SWREG_MAIN_MAIN3__HOPGEARMAXINCR_SH__SHIFT 20 +#define SWREG_MAIN_MAIN3__HOPGEARMAXINCR_SH__WIDTH 2 +#define SWREG_MAIN_MAIN3__HOPGEARMAXINCR_SH__MASK 0x00300000U +#define SWREG_MAIN_MAIN3__HOPGEARMAXINCR_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00300000U) >> 20) +#define SWREG_MAIN_MAIN3__HOPGEARMAXINCR_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x00300000U) +#define SWREG_MAIN_MAIN3__HOPGEARMAXINCR_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00300000U) | (((uint32_t)(src) <<\ + 20) & 0x00300000U) +#define SWREG_MAIN_MAIN3__HOPGEARMAXINCR_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x00300000U))) +#define SWREG_MAIN_MAIN3__HOPGEARMAXINCR_SH__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field freqCountSumToAvoid_0_SH */ +/** + * @defgroup swreg_main_regs_core_freqCountSumToAvoid_0_SH_field freqCountSumToAvoid_0_SH_field + * @brief macros for field freqCountSumToAvoid_0_SH + * @details freqCountSum to avoid + * @{ + */ +#define SWREG_MAIN_MAIN3__FREQCOUNTSUMTOAVOID_0_SH__SHIFT 22 +#define SWREG_MAIN_MAIN3__FREQCOUNTSUMTOAVOID_0_SH__WIDTH 8 +#define SWREG_MAIN_MAIN3__FREQCOUNTSUMTOAVOID_0_SH__MASK 0x3fc00000U +#define SWREG_MAIN_MAIN3__FREQCOUNTSUMTOAVOID_0_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x3fc00000U) >> 22) +#define SWREG_MAIN_MAIN3__FREQCOUNTSUMTOAVOID_0_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x3fc00000U) +#define SWREG_MAIN_MAIN3__FREQCOUNTSUMTOAVOID_0_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3fc00000U) | (((uint32_t)(src) <<\ + 22) & 0x3fc00000U) +#define SWREG_MAIN_MAIN3__FREQCOUNTSUMTOAVOID_0_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x3fc00000U))) +#define SWREG_MAIN_MAIN3__FREQCOUNTSUMTOAVOID_0_SH__RESET_VALUE 0x00000000U +/** @} */ +#define SWREG_MAIN_MAIN3__TYPE uint32_t +#define SWREG_MAIN_MAIN3__READ 0x3fffffffU +#define SWREG_MAIN_MAIN3__WRITE 0x3fffffffU +#define SWREG_MAIN_MAIN3__PRESERVED 0x00000000U +#define SWREG_MAIN_MAIN3__RESET_VALUE 0x00286e26U + +#endif /* __SWREG_MAIN_MAIN3_MACRO__ */ + +/** @} end of main3 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_MAIN_main4 */ +/** + * @defgroup swreg_main_regs_core_main4 main4 + * @brief main swreg registers definitions. + * @{ + */ +#ifndef __SWREG_MAIN_MAIN4_MACRO__ +#define __SWREG_MAIN_MAIN4_MACRO__ + +/* macros for field freqCountSumToAvoid_1_SH */ +/** + * @defgroup swreg_main_regs_core_freqCountSumToAvoid_1_SH_field freqCountSumToAvoid_1_SH_field + * @brief macros for field freqCountSumToAvoid_1_SH + * @details freqCountSum to avoid + * @{ + */ +#define SWREG_MAIN_MAIN4__FREQCOUNTSUMTOAVOID_1_SH__SHIFT 0 +#define SWREG_MAIN_MAIN4__FREQCOUNTSUMTOAVOID_1_SH__WIDTH 8 +#define SWREG_MAIN_MAIN4__FREQCOUNTSUMTOAVOID_1_SH__MASK 0x000000ffU +#define SWREG_MAIN_MAIN4__FREQCOUNTSUMTOAVOID_1_SH__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SWREG_MAIN_MAIN4__FREQCOUNTSUMTOAVOID_1_SH__WRITE(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SWREG_MAIN_MAIN4__FREQCOUNTSUMTOAVOID_1_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((uint32_t)(src) &\ + 0x000000ffU) +#define SWREG_MAIN_MAIN4__FREQCOUNTSUMTOAVOID_1_SH__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x000000ffU))) +#define SWREG_MAIN_MAIN4__FREQCOUNTSUMTOAVOID_1_SH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field freqCountSumToAvoid_2_SH */ +/** + * @defgroup swreg_main_regs_core_freqCountSumToAvoid_2_SH_field freqCountSumToAvoid_2_SH_field + * @brief macros for field freqCountSumToAvoid_2_SH + * @details freqCountSum to avoid + * @{ + */ +#define SWREG_MAIN_MAIN4__FREQCOUNTSUMTOAVOID_2_SH__SHIFT 8 +#define SWREG_MAIN_MAIN4__FREQCOUNTSUMTOAVOID_2_SH__WIDTH 8 +#define SWREG_MAIN_MAIN4__FREQCOUNTSUMTOAVOID_2_SH__MASK 0x0000ff00U +#define SWREG_MAIN_MAIN4__FREQCOUNTSUMTOAVOID_2_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SWREG_MAIN_MAIN4__FREQCOUNTSUMTOAVOID_2_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x0000ff00U) +#define SWREG_MAIN_MAIN4__FREQCOUNTSUMTOAVOID_2_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((uint32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SWREG_MAIN_MAIN4__FREQCOUNTSUMTOAVOID_2_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define SWREG_MAIN_MAIN4__FREQCOUNTSUMTOAVOID_2_SH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hopFreqCountTol_0_SH */ +/** + * @defgroup swreg_main_regs_core_hopFreqCountTol_0_SH_field hopFreqCountTol_0_SH_field + * @brief macros for field hopFreqCountTol_0_SH + * @details tolerance in freqCountSum to trigger frequency hopping + * @{ + */ +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_0_SH__SHIFT 16 +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_0_SH__WIDTH 3 +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_0_SH__MASK 0x00070000U +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_0_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00070000U) >> 16) +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_0_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00070000U) +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_0_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((uint32_t)(src) <<\ + 16) & 0x00070000U) +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_0_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00070000U))) +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_0_SH__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field hopFreqCountTol_1_SH */ +/** + * @defgroup swreg_main_regs_core_hopFreqCountTol_1_SH_field hopFreqCountTol_1_SH_field + * @brief macros for field hopFreqCountTol_1_SH + * @details tolerance in freqCountSum to trigger frequency hopping + * @{ + */ +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_1_SH__SHIFT 19 +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_1_SH__WIDTH 3 +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_1_SH__MASK 0x00380000U +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_1_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00380000U) >> 19) +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_1_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00380000U) +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_1_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00380000U) | (((uint32_t)(src) <<\ + 19) & 0x00380000U) +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_1_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00380000U))) +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_1_SH__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field hopFreqCountTol_2_SH */ +/** + * @defgroup swreg_main_regs_core_hopFreqCountTol_2_SH_field hopFreqCountTol_2_SH_field + * @brief macros for field hopFreqCountTol_2_SH + * @details tolerance in freqCountSum to trigger frequency hopping + * @{ + */ +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_2_SH__SHIFT 22 +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_2_SH__WIDTH 3 +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_2_SH__MASK 0x01c00000U +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_2_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x01c00000U) >> 22) +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_2_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x01c00000U) +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_2_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01c00000U) | (((uint32_t)(src) <<\ + 22) & 0x01c00000U) +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_2_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x01c00000U))) +#define SWREG_MAIN_MAIN4__HOPFREQCOUNTTOL_2_SH__RESET_VALUE 0x00000002U +/** @} */ + +/* macros for field hopDestFreqMatrix_vstore_SH */ +/** + * @defgroup swreg_main_regs_core_hopDestFreqMatrix_vstore_SH_field hopDestFreqMatrix_vstore_SH_field + * @brief macros for field hopDestFreqMatrix_vstore_SH + * @details enable frequency hopping for store (or vddpa), and the three freqCountSum to avoid + * @{ + */ +#define SWREG_MAIN_MAIN4__HOPDESTFREQMATRIX_VSTORE_SH__SHIFT 25 +#define SWREG_MAIN_MAIN4__HOPDESTFREQMATRIX_VSTORE_SH__WIDTH 3 +#define SWREG_MAIN_MAIN4__HOPDESTFREQMATRIX_VSTORE_SH__MASK 0x0e000000U +#define SWREG_MAIN_MAIN4__HOPDESTFREQMATRIX_VSTORE_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x0e000000U) >> 25) +#define SWREG_MAIN_MAIN4__HOPDESTFREQMATRIX_VSTORE_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 25) & 0x0e000000U) +#define SWREG_MAIN_MAIN4__HOPDESTFREQMATRIX_VSTORE_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0e000000U) | (((uint32_t)(src) <<\ + 25) & 0x0e000000U) +#define SWREG_MAIN_MAIN4__HOPDESTFREQMATRIX_VSTORE_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 25) & ~0x0e000000U))) +#define SWREG_MAIN_MAIN4__HOPDESTFREQMATRIX_VSTORE_SH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hopDestFreqMatrix_avdd_SH */ +/** + * @defgroup swreg_main_regs_core_hopDestFreqMatrix_avdd_SH_field hopDestFreqMatrix_avdd_SH_field + * @brief macros for field hopDestFreqMatrix_avdd_SH + * @details enable frequency hopping for avdd, and the three freqCountSum to avoid + * @{ + */ +#define SWREG_MAIN_MAIN4__HOPDESTFREQMATRIX_AVDD_SH__SHIFT 28 +#define SWREG_MAIN_MAIN4__HOPDESTFREQMATRIX_AVDD_SH__WIDTH 3 +#define SWREG_MAIN_MAIN4__HOPDESTFREQMATRIX_AVDD_SH__MASK 0x70000000U +#define SWREG_MAIN_MAIN4__HOPDESTFREQMATRIX_AVDD_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x70000000U) >> 28) +#define SWREG_MAIN_MAIN4__HOPDESTFREQMATRIX_AVDD_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x70000000U) +#define SWREG_MAIN_MAIN4__HOPDESTFREQMATRIX_AVDD_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x70000000U) | (((uint32_t)(src) <<\ + 28) & 0x70000000U) +#define SWREG_MAIN_MAIN4__HOPDESTFREQMATRIX_AVDD_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x70000000U))) +#define SWREG_MAIN_MAIN4__HOPDESTFREQMATRIX_AVDD_SH__RESET_VALUE 0x00000000U +/** @} */ +#define SWREG_MAIN_MAIN4__TYPE uint32_t +#define SWREG_MAIN_MAIN4__READ 0x7fffffffU +#define SWREG_MAIN_MAIN4__WRITE 0x7fffffffU +#define SWREG_MAIN_MAIN4__PRESERVED 0x00000000U +#define SWREG_MAIN_MAIN4__RESET_VALUE 0x00920000U + +#endif /* __SWREG_MAIN_MAIN4_MACRO__ */ + +/** @} end of main4 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_MAIN_main5 */ +/** + * @defgroup swreg_main_regs_core_main5 main5 + * @brief main swreg registers definitions. + * @{ + */ +#ifndef __SWREG_MAIN_MAIN5_MACRO__ +#define __SWREG_MAIN_MAIN5_MACRO__ + +/* macros for field hopDestFreqMatrix_vddio_SH */ +/** + * @defgroup swreg_main_regs_core_hopDestFreqMatrix_vddio_SH_field hopDestFreqMatrix_vddio_SH_field + * @brief macros for field hopDestFreqMatrix_vddio_SH + * @details enable frequency hopping for vddio, and the three freqCountSum to avoid + * @{ + */ +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_VDDIO_SH__SHIFT 0 +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_VDDIO_SH__WIDTH 3 +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_VDDIO_SH__MASK 0x00000007U +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_VDDIO_SH__READ(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_VDDIO_SH__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000007U) +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_VDDIO_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((uint32_t)(src) &\ + 0x00000007U) +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_VDDIO_SH__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000007U))) +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_VDDIO_SH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hopDestFreqMatrix_vaux_SH */ +/** + * @defgroup swreg_main_regs_core_hopDestFreqMatrix_vaux_SH_field hopDestFreqMatrix_vaux_SH_field + * @brief macros for field hopDestFreqMatrix_vaux_SH + * @details enable frequency hopping for vaux, and the three freqCountSum to avoid + * @{ + */ +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_VAUX_SH__SHIFT 3 +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_VAUX_SH__WIDTH 3 +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_VAUX_SH__MASK 0x00000038U +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_VAUX_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00000038U) >> 3) +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_VAUX_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000038U) +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_VAUX_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((uint32_t)(src) <<\ + 3) & 0x00000038U) +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_VAUX_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000038U))) +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_VAUX_SH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hopDestFreqMatrix_dvdd_SH */ +/** + * @defgroup swreg_main_regs_core_hopDestFreqMatrix_dvdd_SH_field hopDestFreqMatrix_dvdd_SH_field + * @brief macros for field hopDestFreqMatrix_dvdd_SH + * @details enable frequency hopping for dvdd, and the three freqCountSum to avoid + * @{ + */ +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_DVDD_SH__SHIFT 6 +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_DVDD_SH__WIDTH 3 +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_DVDD_SH__MASK 0x000001c0U +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_DVDD_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x000001c0U) >> 6) +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_DVDD_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x000001c0U) +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_DVDD_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((uint32_t)(src) <<\ + 6) & 0x000001c0U) +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_DVDD_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x000001c0U))) +#define SWREG_MAIN_MAIN5__HOPDESTFREQMATRIX_DVDD_SH__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hopJumpTime_vstore_SH */ +/** + * @defgroup swreg_main_regs_core_hopJumpTime_vstore_SH_field hopJumpTime_vstore_SH_field + * @brief macros for field hopJumpTime_vstore_SH + * @details when frequency hopping for store is activated, the target dump time increases by this number (x2) + * @{ + */ +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_VSTORE_SH__SHIFT 9 +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_VSTORE_SH__WIDTH 6 +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_VSTORE_SH__MASK 0x00007e00U +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_VSTORE_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00007e00U) >> 9) +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_VSTORE_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00007e00U) +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_VSTORE_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007e00U) | (((uint32_t)(src) <<\ + 9) & 0x00007e00U) +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_VSTORE_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00007e00U))) +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_VSTORE_SH__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field hopJumpTime_avdd_SH */ +/** + * @defgroup swreg_main_regs_core_hopJumpTime_avdd_SH_field hopJumpTime_avdd_SH_field + * @brief macros for field hopJumpTime_avdd_SH + * @details when frequency hopping for avdd is activated, the target dump time increases by this number (x2) + * @{ + */ +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_AVDD_SH__SHIFT 15 +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_AVDD_SH__WIDTH 6 +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_AVDD_SH__MASK 0x001f8000U +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_AVDD_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x001f8000U) >> 15) +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_AVDD_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x001f8000U) +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_AVDD_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f8000U) | (((uint32_t)(src) <<\ + 15) & 0x001f8000U) +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_AVDD_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x001f8000U))) +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_AVDD_SH__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field hopJumpTime_vddio_SH */ +/** + * @defgroup swreg_main_regs_core_hopJumpTime_vddio_SH_field hopJumpTime_vddio_SH_field + * @brief macros for field hopJumpTime_vddio_SH + * @details when frequency hopping for vddio is activated, the target dump time increases by this number (x2) + * @{ + */ +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_VDDIO_SH__SHIFT 21 +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_VDDIO_SH__WIDTH 6 +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_VDDIO_SH__MASK 0x07e00000U +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_VDDIO_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x07e00000U) >> 21) +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_VDDIO_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 21) & 0x07e00000U) +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_VDDIO_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07e00000U) | (((uint32_t)(src) <<\ + 21) & 0x07e00000U) +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_VDDIO_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 21) & ~0x07e00000U))) +#define SWREG_MAIN_MAIN5__HOPJUMPTIME_VDDIO_SH__RESET_VALUE 0x00000004U +/** @} */ +#define SWREG_MAIN_MAIN5__TYPE uint32_t +#define SWREG_MAIN_MAIN5__READ 0x07ffffffU +#define SWREG_MAIN_MAIN5__WRITE 0x07ffffffU +#define SWREG_MAIN_MAIN5__PRESERVED 0x00000000U +#define SWREG_MAIN_MAIN5__RESET_VALUE 0x00820800U + +#endif /* __SWREG_MAIN_MAIN5_MACRO__ */ + +/** @} end of main5 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_MAIN_main6 */ +/** + * @defgroup swreg_main_regs_core_main6 main6 + * @brief main swreg registers definitions. + * @{ + */ +#ifndef __SWREG_MAIN_MAIN6_MACRO__ +#define __SWREG_MAIN_MAIN6_MACRO__ + +/* macros for field hopJumpTime_vaux_SH */ +/** + * @defgroup swreg_main_regs_core_hopJumpTime_vaux_SH_field hopJumpTime_vaux_SH_field + * @brief macros for field hopJumpTime_vaux_SH + * @details when frequency hopping for vaux is activated, the target dump time increases by this number (x2) + * @{ + */ +#define SWREG_MAIN_MAIN6__HOPJUMPTIME_VAUX_SH__SHIFT 0 +#define SWREG_MAIN_MAIN6__HOPJUMPTIME_VAUX_SH__WIDTH 6 +#define SWREG_MAIN_MAIN6__HOPJUMPTIME_VAUX_SH__MASK 0x0000003fU +#define SWREG_MAIN_MAIN6__HOPJUMPTIME_VAUX_SH__READ(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define SWREG_MAIN_MAIN6__HOPJUMPTIME_VAUX_SH__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000003fU) +#define SWREG_MAIN_MAIN6__HOPJUMPTIME_VAUX_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((uint32_t)(src) &\ + 0x0000003fU) +#define SWREG_MAIN_MAIN6__HOPJUMPTIME_VAUX_SH__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000003fU))) +#define SWREG_MAIN_MAIN6__HOPJUMPTIME_VAUX_SH__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field hopJumpTime_dvdd_SH */ +/** + * @defgroup swreg_main_regs_core_hopJumpTime_dvdd_SH_field hopJumpTime_dvdd_SH_field + * @brief macros for field hopJumpTime_dvdd_SH + * @details when frequency hopping for dvdd is activated, the target dump time increases by this number (x2) + * @{ + */ +#define SWREG_MAIN_MAIN6__HOPJUMPTIME_DVDD_SH__SHIFT 6 +#define SWREG_MAIN_MAIN6__HOPJUMPTIME_DVDD_SH__WIDTH 6 +#define SWREG_MAIN_MAIN6__HOPJUMPTIME_DVDD_SH__MASK 0x00000fc0U +#define SWREG_MAIN_MAIN6__HOPJUMPTIME_DVDD_SH__READ(src) \ + (((uint32_t)(src)\ + & 0x00000fc0U) >> 6) +#define SWREG_MAIN_MAIN6__HOPJUMPTIME_DVDD_SH__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000fc0U) +#define SWREG_MAIN_MAIN6__HOPJUMPTIME_DVDD_SH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((uint32_t)(src) <<\ + 6) & 0x00000fc0U) +#define SWREG_MAIN_MAIN6__HOPJUMPTIME_DVDD_SH__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000fc0U))) +#define SWREG_MAIN_MAIN6__HOPJUMPTIME_DVDD_SH__RESET_VALUE 0x00000004U +/** @} */ + +/* macros for field legacyStart */ +/** + * @defgroup swreg_main_regs_core_legacyStart_field legacyStart_field + * @brief macros for field legacyStart + * @details legacy start with constant energize time before supply is ready //start + * @{ + */ +#define SWREG_MAIN_MAIN6__LEGACYSTART__SHIFT 12 +#define SWREG_MAIN_MAIN6__LEGACYSTART__WIDTH 1 +#define SWREG_MAIN_MAIN6__LEGACYSTART__MASK 0x00001000U +#define SWREG_MAIN_MAIN6__LEGACYSTART__READ(src) \ + (((uint32_t)(src)\ + & 0x00001000U) >> 12) +#define SWREG_MAIN_MAIN6__LEGACYSTART__WRITE(src) \ + (((uint32_t)(src)\ + << 12) & 0x00001000U) +#define SWREG_MAIN_MAIN6__LEGACYSTART__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((uint32_t)(src) <<\ + 12) & 0x00001000U) +#define SWREG_MAIN_MAIN6__LEGACYSTART__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 12) & ~0x00001000U))) +#define SWREG_MAIN_MAIN6__LEGACYSTART__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(1) << 12) +#define SWREG_MAIN_MAIN6__LEGACYSTART__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((uint32_t)(0) << 12) +#define SWREG_MAIN_MAIN6__LEGACYSTART__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field loadRegMain */ +/** + * @defgroup swreg_main_regs_core_loadRegMain_field loadRegMain_field + * @brief macros for field loadRegMain + * @details load the Main shadow register + * @{ + */ +#define SWREG_MAIN_MAIN6__LOADREGMAIN__SHIFT 13 +#define SWREG_MAIN_MAIN6__LOADREGMAIN__WIDTH 1 +#define SWREG_MAIN_MAIN6__LOADREGMAIN__MASK 0x00002000U +#define SWREG_MAIN_MAIN6__LOADREGMAIN__READ(src) \ + (((uint32_t)(src)\ + & 0x00002000U) >> 13) +#define SWREG_MAIN_MAIN6__LOADREGMAIN__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00002000U) +#define SWREG_MAIN_MAIN6__LOADREGMAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((uint32_t)(src) <<\ + 13) & 0x00002000U) +#define SWREG_MAIN_MAIN6__LOADREGMAIN__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00002000U))) +#define SWREG_MAIN_MAIN6__LOADREGMAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(1) << 13) +#define SWREG_MAIN_MAIN6__LOADREGMAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((uint32_t)(0) << 13) +#define SWREG_MAIN_MAIN6__LOADREGMAIN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field divCk32 */ +/** + * @defgroup swreg_main_regs_core_divCk32_field divCk32_field + * @brief macros for field divCk32 + * @details divide the 32KHz clock by (divCk32+1). Zero means no division + * @{ + */ +#define SWREG_MAIN_MAIN6__DIVCK32__SHIFT 14 +#define SWREG_MAIN_MAIN6__DIVCK32__WIDTH 3 +#define SWREG_MAIN_MAIN6__DIVCK32__MASK 0x0001c000U +#define SWREG_MAIN_MAIN6__DIVCK32__READ(src) \ + (((uint32_t)(src)\ + & 0x0001c000U) >> 14) +#define SWREG_MAIN_MAIN6__DIVCK32__WRITE(src) \ + (((uint32_t)(src)\ + << 14) & 0x0001c000U) +#define SWREG_MAIN_MAIN6__DIVCK32__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((uint32_t)(src) <<\ + 14) & 0x0001c000U) +#define SWREG_MAIN_MAIN6__DIVCK32__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 14) & ~0x0001c000U))) +#define SWREG_MAIN_MAIN6__DIVCK32__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field divCk32Mppt */ +/** + * @defgroup swreg_main_regs_core_divCk32Mppt_field divCk32Mppt_field + * @brief macros for field divCk32Mppt + * @details divide the 32KHz clock by (divCk32Mppt+1) for mppt purposes. Zero means no division + * @{ + */ +#define SWREG_MAIN_MAIN6__DIVCK32MPPT__SHIFT 17 +#define SWREG_MAIN_MAIN6__DIVCK32MPPT__WIDTH 5 +#define SWREG_MAIN_MAIN6__DIVCK32MPPT__MASK 0x003e0000U +#define SWREG_MAIN_MAIN6__DIVCK32MPPT__READ(src) \ + (((uint32_t)(src)\ + & 0x003e0000U) >> 17) +#define SWREG_MAIN_MAIN6__DIVCK32MPPT__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x003e0000U) +#define SWREG_MAIN_MAIN6__DIVCK32MPPT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((uint32_t)(src) <<\ + 17) & 0x003e0000U) +#define SWREG_MAIN_MAIN6__DIVCK32MPPT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x003e0000U))) +#define SWREG_MAIN_MAIN6__DIVCK32MPPT__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field scaleEnerg_ovr */ +/** + * @defgroup swreg_main_regs_core_scaleEnerg_ovr_field scaleEnerg_ovr_field + * @brief macros for field scaleEnerg_ovr + * @details override scaling of energize time + * @{ + */ +#define SWREG_MAIN_MAIN6__SCALEENERG_OVR__SHIFT 22 +#define SWREG_MAIN_MAIN6__SCALEENERG_OVR__WIDTH 1 +#define SWREG_MAIN_MAIN6__SCALEENERG_OVR__MASK 0x00400000U +#define SWREG_MAIN_MAIN6__SCALEENERG_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00400000U) >> 22) +#define SWREG_MAIN_MAIN6__SCALEENERG_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 22) & 0x00400000U) +#define SWREG_MAIN_MAIN6__SCALEENERG_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((uint32_t)(src) <<\ + 22) & 0x00400000U) +#define SWREG_MAIN_MAIN6__SCALEENERG_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 22) & ~0x00400000U))) +#define SWREG_MAIN_MAIN6__SCALEENERG_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(1) << 22) +#define SWREG_MAIN_MAIN6__SCALEENERG_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((uint32_t)(0) << 22) +#define SWREG_MAIN_MAIN6__SCALEENERG_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field scaleEnerg_ovrVal */ +/** + * @defgroup swreg_main_regs_core_scaleEnerg_ovrVal_field scaleEnerg_ovrVal_field + * @brief macros for field scaleEnerg_ovrVal + * @details override value for scaling of energize time, 3 bits for each source: setting of (0:7) corresponds to scaling of (1, 1.125, 1.375, 1.625, 2, 3, 4, 8) + * @{ + */ +#define SWREG_MAIN_MAIN6__SCALEENERG_OVRVAL__SHIFT 23 +#define SWREG_MAIN_MAIN6__SCALEENERG_OVRVAL__WIDTH 9 +#define SWREG_MAIN_MAIN6__SCALEENERG_OVRVAL__MASK 0xff800000U +#define SWREG_MAIN_MAIN6__SCALEENERG_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0xff800000U) >> 23) +#define SWREG_MAIN_MAIN6__SCALEENERG_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 23) & 0xff800000U) +#define SWREG_MAIN_MAIN6__SCALEENERG_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff800000U) | (((uint32_t)(src) <<\ + 23) & 0xff800000U) +#define SWREG_MAIN_MAIN6__SCALEENERG_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 23) & ~0xff800000U))) +#define SWREG_MAIN_MAIN6__SCALEENERG_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ +#define SWREG_MAIN_MAIN6__TYPE uint32_t +#define SWREG_MAIN_MAIN6__READ 0xffffffffU +#define SWREG_MAIN_MAIN6__WRITE 0xffffffffU +#define SWREG_MAIN_MAIN6__PRESERVED 0x00000000U +#define SWREG_MAIN_MAIN6__RESET_VALUE 0x000e0104U + +#endif /* __SWREG_MAIN_MAIN6_MACRO__ */ + +/** @} end of main6 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_MAIN_main7 */ +/** + * @defgroup swreg_main_regs_core_main7 main7 + * @brief main swreg registers definitions. + * @{ + */ +#ifndef __SWREG_MAIN_MAIN7_MACRO__ +#define __SWREG_MAIN_MAIN7_MACRO__ + +/* macros for field enableHarv2Sup_ovr */ +/** + * @defgroup swreg_main_regs_core_enableHarv2Sup_ovr_field enableHarv2Sup_ovr_field + * @brief macros for field enableHarv2Sup_ovr + * @details override enable for harvest to supplies modes + * @{ + */ +#define SWREG_MAIN_MAIN7__ENABLEHARV2SUP_OVR__SHIFT 0 +#define SWREG_MAIN_MAIN7__ENABLEHARV2SUP_OVR__WIDTH 1 +#define SWREG_MAIN_MAIN7__ENABLEHARV2SUP_OVR__MASK 0x00000001U +#define SWREG_MAIN_MAIN7__ENABLEHARV2SUP_OVR__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWREG_MAIN_MAIN7__ENABLEHARV2SUP_OVR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWREG_MAIN_MAIN7__ENABLEHARV2SUP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SWREG_MAIN_MAIN7__ENABLEHARV2SUP_OVR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SWREG_MAIN_MAIN7__ENABLEHARV2SUP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SWREG_MAIN_MAIN7__ENABLEHARV2SUP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SWREG_MAIN_MAIN7__ENABLEHARV2SUP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enableHarv2Sup_ovrVal */ +/** + * @defgroup swreg_main_regs_core_enableHarv2Sup_ovrVal_field enableHarv2Sup_ovrVal_field + * @brief macros for field enableHarv2Sup_ovrVal + * @details override value of the enable for harvest to supplies modes + * @{ + */ +#define SWREG_MAIN_MAIN7__ENABLEHARV2SUP_OVRVAL__SHIFT 1 +#define SWREG_MAIN_MAIN7__ENABLEHARV2SUP_OVRVAL__WIDTH 1 +#define SWREG_MAIN_MAIN7__ENABLEHARV2SUP_OVRVAL__MASK 0x00000002U +#define SWREG_MAIN_MAIN7__ENABLEHARV2SUP_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define SWREG_MAIN_MAIN7__ENABLEHARV2SUP_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define SWREG_MAIN_MAIN7__ENABLEHARV2SUP_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define SWREG_MAIN_MAIN7__ENABLEHARV2SUP_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define SWREG_MAIN_MAIN7__ENABLEHARV2SUP_OVRVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SWREG_MAIN_MAIN7__ENABLEHARV2SUP_OVRVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SWREG_MAIN_MAIN7__ENABLEHARV2SUP_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fixHarvEnerg_ovr */ +/** + * @defgroup swreg_main_regs_core_fixHarvEnerg_ovr_field fixHarvEnerg_ovr_field + * @brief macros for field fixHarvEnerg_ovr + * @details override fixing the energize time (fixHarvEnerg) for all destinations when the source is the harvester if fixHarvEnerg=1 the target for the harvest to supply modes is the energize time, otherwise it is the dump time if set, timeTargetHarv2Store_SH is used as the energize time + * @{ + */ +#define SWREG_MAIN_MAIN7__FIXHARVENERG_OVR__SHIFT 2 +#define SWREG_MAIN_MAIN7__FIXHARVENERG_OVR__WIDTH 1 +#define SWREG_MAIN_MAIN7__FIXHARVENERG_OVR__MASK 0x00000004U +#define SWREG_MAIN_MAIN7__FIXHARVENERG_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define SWREG_MAIN_MAIN7__FIXHARVENERG_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define SWREG_MAIN_MAIN7__FIXHARVENERG_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define SWREG_MAIN_MAIN7__FIXHARVENERG_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define SWREG_MAIN_MAIN7__FIXHARVENERG_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define SWREG_MAIN_MAIN7__FIXHARVENERG_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define SWREG_MAIN_MAIN7__FIXHARVENERG_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fixHarvEnerg_ovrVal */ +/** + * @defgroup swreg_main_regs_core_fixHarvEnerg_ovrVal_field fixHarvEnerg_ovrVal_field + * @brief macros for field fixHarvEnerg_ovrVal + * @details override value for fixing the energize time for all destinations when the source is the harvester + * @{ + */ +#define SWREG_MAIN_MAIN7__FIXHARVENERG_OVRVAL__SHIFT 3 +#define SWREG_MAIN_MAIN7__FIXHARVENERG_OVRVAL__WIDTH 1 +#define SWREG_MAIN_MAIN7__FIXHARVENERG_OVRVAL__MASK 0x00000008U +#define SWREG_MAIN_MAIN7__FIXHARVENERG_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define SWREG_MAIN_MAIN7__FIXHARVENERG_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define SWREG_MAIN_MAIN7__FIXHARVENERG_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define SWREG_MAIN_MAIN7__FIXHARVENERG_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define SWREG_MAIN_MAIN7__FIXHARVENERG_OVRVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define SWREG_MAIN_MAIN7__FIXHARVENERG_OVRVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define SWREG_MAIN_MAIN7__FIXHARVENERG_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field discardCanHarvest */ +/** + * @defgroup swreg_main_regs_core_discardCanHarvest_field discardCanHarvest_field + * @brief macros for field discardCanHarvest + * @details Discard the canHarvest comparator output and use mustHarvest instead + * @{ + */ +#define SWREG_MAIN_MAIN7__DISCARDCANHARVEST__SHIFT 4 +#define SWREG_MAIN_MAIN7__DISCARDCANHARVEST__WIDTH 1 +#define SWREG_MAIN_MAIN7__DISCARDCANHARVEST__MASK 0x00000010U +#define SWREG_MAIN_MAIN7__DISCARDCANHARVEST__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define SWREG_MAIN_MAIN7__DISCARDCANHARVEST__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define SWREG_MAIN_MAIN7__DISCARDCANHARVEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define SWREG_MAIN_MAIN7__DISCARDCANHARVEST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define SWREG_MAIN_MAIN7__DISCARDCANHARVEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define SWREG_MAIN_MAIN7__DISCARDCANHARVEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define SWREG_MAIN_MAIN7__DISCARDCANHARVEST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field buckBoost_ovr */ +/** + * @defgroup swreg_main_regs_core_buckBoost_ovr_field buckBoost_ovr_field + * @brief macros for field buckBoost_ovr + * @details override the buck or boost mode + * @{ + */ +#define SWREG_MAIN_MAIN7__BUCKBOOST_OVR__SHIFT 5 +#define SWREG_MAIN_MAIN7__BUCKBOOST_OVR__WIDTH 15 +#define SWREG_MAIN_MAIN7__BUCKBOOST_OVR__MASK 0x000fffe0U +#define SWREG_MAIN_MAIN7__BUCKBOOST_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x000fffe0U) >> 5) +#define SWREG_MAIN_MAIN7__BUCKBOOST_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x000fffe0U) +#define SWREG_MAIN_MAIN7__BUCKBOOST_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fffe0U) | (((uint32_t)(src) <<\ + 5) & 0x000fffe0U) +#define SWREG_MAIN_MAIN7__BUCKBOOST_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000fffe0U))) +#define SWREG_MAIN_MAIN7__BUCKBOOST_OVR__RESET_VALUE 0x00000000U +/** @} */ +#define SWREG_MAIN_MAIN7__TYPE uint32_t +#define SWREG_MAIN_MAIN7__READ 0x000fffffU +#define SWREG_MAIN_MAIN7__WRITE 0x000fffffU +#define SWREG_MAIN_MAIN7__PRESERVED 0x00000000U +#define SWREG_MAIN_MAIN7__RESET_VALUE 0x00000000U + +#endif /* __SWREG_MAIN_MAIN7_MACRO__ */ + +/** @} end of main7 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_MAIN_main8 */ +/** + * @defgroup swreg_main_regs_core_main8 main8 + * @brief main swreg registers definitions. + * @{ + */ +#ifndef __SWREG_MAIN_MAIN8_MACRO__ +#define __SWREG_MAIN_MAIN8_MACRO__ + +/* macros for field buck_ovrVal */ +/** + * @defgroup swreg_main_regs_core_buck_ovrVal_field buck_ovrVal_field + * @brief macros for field buck_ovrVal + * @details if set when the corresponding buckBoost_ovr bit is one, buck mode will be used for this power transfer mode + * @{ + */ +#define SWREG_MAIN_MAIN8__BUCK_OVRVAL__SHIFT 0 +#define SWREG_MAIN_MAIN8__BUCK_OVRVAL__WIDTH 15 +#define SWREG_MAIN_MAIN8__BUCK_OVRVAL__MASK 0x00007fffU +#define SWREG_MAIN_MAIN8__BUCK_OVRVAL__READ(src) \ + ((uint32_t)(src)\ + & 0x00007fffU) +#define SWREG_MAIN_MAIN8__BUCK_OVRVAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00007fffU) +#define SWREG_MAIN_MAIN8__BUCK_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007fffU) | ((uint32_t)(src) &\ + 0x00007fffU) +#define SWREG_MAIN_MAIN8__BUCK_OVRVAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00007fffU))) +#define SWREG_MAIN_MAIN8__BUCK_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field boost_ovrVal */ +/** + * @defgroup swreg_main_regs_core_boost_ovrVal_field boost_ovrVal_field + * @brief macros for field boost_ovrVal + * @details if set when the corresponding buckBoost_ovr bit is one and buck_ovrVal is zero, boost mode will be used for this power transfer mode.if both buck_ovrVal and boost_ovrVal are zero buck-boost mode will be used. + * @{ + */ +#define SWREG_MAIN_MAIN8__BOOST_OVRVAL__SHIFT 15 +#define SWREG_MAIN_MAIN8__BOOST_OVRVAL__WIDTH 15 +#define SWREG_MAIN_MAIN8__BOOST_OVRVAL__MASK 0x3fff8000U +#define SWREG_MAIN_MAIN8__BOOST_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x3fff8000U) >> 15) +#define SWREG_MAIN_MAIN8__BOOST_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 15) & 0x3fff8000U) +#define SWREG_MAIN_MAIN8__BOOST_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3fff8000U) | (((uint32_t)(src) <<\ + 15) & 0x3fff8000U) +#define SWREG_MAIN_MAIN8__BOOST_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 15) & ~0x3fff8000U))) +#define SWREG_MAIN_MAIN8__BOOST_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field readyForTinyLevel */ +/** + * @defgroup swreg_main_regs_core_readyForTinyLevel_field readyForTinyLevel_field + * @brief macros for field readyForTinyLevel + * @details transition to the tiny FSM is delayed until the main FSM has settled according to this setting:0: no wait1: wait until all enabled supplies are ready2: wait until all enabled supplies are ready and the targets have settled3: wait until all enabled supplies have fully settled + * @{ + */ +#define SWREG_MAIN_MAIN8__READYFORTINYLEVEL__SHIFT 30 +#define SWREG_MAIN_MAIN8__READYFORTINYLEVEL__WIDTH 2 +#define SWREG_MAIN_MAIN8__READYFORTINYLEVEL__MASK 0xc0000000U +#define SWREG_MAIN_MAIN8__READYFORTINYLEVEL__READ(src) \ + (((uint32_t)(src)\ + & 0xc0000000U) >> 30) +#define SWREG_MAIN_MAIN8__READYFORTINYLEVEL__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0xc0000000U) +#define SWREG_MAIN_MAIN8__READYFORTINYLEVEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((uint32_t)(src) <<\ + 30) & 0xc0000000U) +#define SWREG_MAIN_MAIN8__READYFORTINYLEVEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0xc0000000U))) +#define SWREG_MAIN_MAIN8__READYFORTINYLEVEL__RESET_VALUE 0x00000002U +/** @} */ +#define SWREG_MAIN_MAIN8__TYPE uint32_t +#define SWREG_MAIN_MAIN8__READ 0xffffffffU +#define SWREG_MAIN_MAIN8__WRITE 0xffffffffU +#define SWREG_MAIN_MAIN8__PRESERVED 0x00000000U +#define SWREG_MAIN_MAIN8__RESET_VALUE 0x80000000U + +#endif /* __SWREG_MAIN_MAIN8_MACRO__ */ + +/** @} end of main8 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_MAIN_main9 */ +/** + * @defgroup swreg_main_regs_core_main9 main9 + * @brief main swreg registers definitions. + * @{ + */ +#ifndef __SWREG_MAIN_MAIN9_MACRO__ +#define __SWREG_MAIN_MAIN9_MACRO__ + +/* macros for field chargeStore_ovr */ +/** + * @defgroup swreg_main_regs_core_chargeStore_ovr_field chargeStore_ovr_field + * @brief macros for field chargeStore_ovr + * @details override enable for charging store from the battery + * @{ + */ +#define SWREG_MAIN_MAIN9__CHARGESTORE_OVR__SHIFT 0 +#define SWREG_MAIN_MAIN9__CHARGESTORE_OVR__WIDTH 1 +#define SWREG_MAIN_MAIN9__CHARGESTORE_OVR__MASK 0x00000001U +#define SWREG_MAIN_MAIN9__CHARGESTORE_OVR__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWREG_MAIN_MAIN9__CHARGESTORE_OVR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWREG_MAIN_MAIN9__CHARGESTORE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SWREG_MAIN_MAIN9__CHARGESTORE_OVR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SWREG_MAIN_MAIN9__CHARGESTORE_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SWREG_MAIN_MAIN9__CHARGESTORE_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SWREG_MAIN_MAIN9__CHARGESTORE_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field chargeStore_ovrVal */ +/** + * @defgroup swreg_main_regs_core_chargeStore_ovrVal_field chargeStore_ovrVal_field + * @brief macros for field chargeStore_ovrVal + * @details override value of the enable for charging store from the battery + * @{ + */ +#define SWREG_MAIN_MAIN9__CHARGESTORE_OVRVAL__SHIFT 1 +#define SWREG_MAIN_MAIN9__CHARGESTORE_OVRVAL__WIDTH 1 +#define SWREG_MAIN_MAIN9__CHARGESTORE_OVRVAL__MASK 0x00000002U +#define SWREG_MAIN_MAIN9__CHARGESTORE_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000002U) >> 1) +#define SWREG_MAIN_MAIN9__CHARGESTORE_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x00000002U) +#define SWREG_MAIN_MAIN9__CHARGESTORE_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((uint32_t)(src) <<\ + 1) & 0x00000002U) +#define SWREG_MAIN_MAIN9__CHARGESTORE_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x00000002U))) +#define SWREG_MAIN_MAIN9__CHARGESTORE_OVRVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(1) << 1) +#define SWREG_MAIN_MAIN9__CHARGESTORE_OVRVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((uint32_t)(0) << 1) +#define SWREG_MAIN_MAIN9__CHARGESTORE_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field chargeBatt_ovr */ +/** + * @defgroup swreg_main_regs_core_chargeBatt_ovr_field chargeBatt_ovr_field + * @brief macros for field chargeBatt_ovr + * @details override enable for charging battery from the store + * @{ + */ +#define SWREG_MAIN_MAIN9__CHARGEBATT_OVR__SHIFT 2 +#define SWREG_MAIN_MAIN9__CHARGEBATT_OVR__WIDTH 1 +#define SWREG_MAIN_MAIN9__CHARGEBATT_OVR__MASK 0x00000004U +#define SWREG_MAIN_MAIN9__CHARGEBATT_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000004U) >> 2) +#define SWREG_MAIN_MAIN9__CHARGEBATT_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 2) & 0x00000004U) +#define SWREG_MAIN_MAIN9__CHARGEBATT_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((uint32_t)(src) <<\ + 2) & 0x00000004U) +#define SWREG_MAIN_MAIN9__CHARGEBATT_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 2) & ~0x00000004U))) +#define SWREG_MAIN_MAIN9__CHARGEBATT_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(1) << 2) +#define SWREG_MAIN_MAIN9__CHARGEBATT_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((uint32_t)(0) << 2) +#define SWREG_MAIN_MAIN9__CHARGEBATT_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field chargeBatt_ovrVal */ +/** + * @defgroup swreg_main_regs_core_chargeBatt_ovrVal_field chargeBatt_ovrVal_field + * @brief macros for field chargeBatt_ovrVal + * @details override value of the enable for charging battery from the store + * @{ + */ +#define SWREG_MAIN_MAIN9__CHARGEBATT_OVRVAL__SHIFT 3 +#define SWREG_MAIN_MAIN9__CHARGEBATT_OVRVAL__WIDTH 1 +#define SWREG_MAIN_MAIN9__CHARGEBATT_OVRVAL__MASK 0x00000008U +#define SWREG_MAIN_MAIN9__CHARGEBATT_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000008U) >> 3) +#define SWREG_MAIN_MAIN9__CHARGEBATT_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 3) & 0x00000008U) +#define SWREG_MAIN_MAIN9__CHARGEBATT_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((uint32_t)(src) <<\ + 3) & 0x00000008U) +#define SWREG_MAIN_MAIN9__CHARGEBATT_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 3) & ~0x00000008U))) +#define SWREG_MAIN_MAIN9__CHARGEBATT_OVRVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(1) << 3) +#define SWREG_MAIN_MAIN9__CHARGEBATT_OVRVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((uint32_t)(0) << 3) +#define SWREG_MAIN_MAIN9__CHARGEBATT_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field storeIsSup_ovr */ +/** + * @defgroup swreg_main_regs_core_storeIsSup_ovr_field storeIsSup_ovr_field + * @brief macros for field storeIsSup_ovr + * @details override storeIsSup, which repurposes store to be a the PA supply (vddpa) + * @{ + */ +#define SWREG_MAIN_MAIN9__STOREISSUP_OVR__SHIFT 4 +#define SWREG_MAIN_MAIN9__STOREISSUP_OVR__WIDTH 1 +#define SWREG_MAIN_MAIN9__STOREISSUP_OVR__MASK 0x00000010U +#define SWREG_MAIN_MAIN9__STOREISSUP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000010U) >> 4) +#define SWREG_MAIN_MAIN9__STOREISSUP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 4) & 0x00000010U) +#define SWREG_MAIN_MAIN9__STOREISSUP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((uint32_t)(src) <<\ + 4) & 0x00000010U) +#define SWREG_MAIN_MAIN9__STOREISSUP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 4) & ~0x00000010U))) +#define SWREG_MAIN_MAIN9__STOREISSUP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(1) << 4) +#define SWREG_MAIN_MAIN9__STOREISSUP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((uint32_t)(0) << 4) +#define SWREG_MAIN_MAIN9__STOREISSUP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field storeIsSup_ovrVal */ +/** + * @defgroup swreg_main_regs_core_storeIsSup_ovrVal_field storeIsSup_ovrVal_field + * @brief macros for field storeIsSup_ovrVal + * @details override value of storeIsSup + * @{ + */ +#define SWREG_MAIN_MAIN9__STOREISSUP_OVRVAL__SHIFT 5 +#define SWREG_MAIN_MAIN9__STOREISSUP_OVRVAL__WIDTH 1 +#define SWREG_MAIN_MAIN9__STOREISSUP_OVRVAL__MASK 0x00000020U +#define SWREG_MAIN_MAIN9__STOREISSUP_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define SWREG_MAIN_MAIN9__STOREISSUP_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x00000020U) +#define SWREG_MAIN_MAIN9__STOREISSUP_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((uint32_t)(src) <<\ + 5) & 0x00000020U) +#define SWREG_MAIN_MAIN9__STOREISSUP_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x00000020U))) +#define SWREG_MAIN_MAIN9__STOREISSUP_OVRVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define SWREG_MAIN_MAIN9__STOREISSUP_OVRVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define SWREG_MAIN_MAIN9__STOREISSUP_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mppt_ovr */ +/** + * @defgroup swreg_main_regs_core_mppt_ovr_field mppt_ovr_field + * @brief macros for field mppt_ovr + * @details override mppt controls + * @{ + */ +#define SWREG_MAIN_MAIN9__MPPT_OVR__SHIFT 6 +#define SWREG_MAIN_MAIN9__MPPT_OVR__WIDTH 1 +#define SWREG_MAIN_MAIN9__MPPT_OVR__MASK 0x00000040U +#define SWREG_MAIN_MAIN9__MPPT_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define SWREG_MAIN_MAIN9__MPPT_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define SWREG_MAIN_MAIN9__MPPT_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define SWREG_MAIN_MAIN9__MPPT_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define SWREG_MAIN_MAIN9__MPPT_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define SWREG_MAIN_MAIN9__MPPT_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define SWREG_MAIN_MAIN9__MPPT_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mpptStart_ovrVal */ +/** + * @defgroup swreg_main_regs_core_mpptStart_ovrVal_field mpptStart_ovrVal_field + * @brief macros for field mpptStart_ovrVal + * @details start mppt measurement in override mode. Needs to stay high until mpptDone becomes 1. + * @{ + */ +#define SWREG_MAIN_MAIN9__MPPTSTART_OVRVAL__SHIFT 7 +#define SWREG_MAIN_MAIN9__MPPTSTART_OVRVAL__WIDTH 1 +#define SWREG_MAIN_MAIN9__MPPTSTART_OVRVAL__MASK 0x00000080U +#define SWREG_MAIN_MAIN9__MPPTSTART_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define SWREG_MAIN_MAIN9__MPPTSTART_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x00000080U) +#define SWREG_MAIN_MAIN9__MPPTSTART_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((uint32_t)(src) <<\ + 7) & 0x00000080U) +#define SWREG_MAIN_MAIN9__MPPTSTART_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x00000080U))) +#define SWREG_MAIN_MAIN9__MPPTSTART_OVRVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define SWREG_MAIN_MAIN9__MPPTSTART_OVRVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define SWREG_MAIN_MAIN9__MPPTSTART_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mpptTargetIsPeriods_ovrVal */ +/** + * @defgroup swreg_main_regs_core_mpptTargetIsPeriods_ovrVal_field mpptTargetIsPeriods_ovrVal_field + * @brief macros for field mpptTargetIsPeriods_ovrVal + * @details if 1 the target number of periods, otherwise it is number of events in mppt override mode + * @{ + */ +#define SWREG_MAIN_MAIN9__MPPTTARGETISPERIODS_OVRVAL__SHIFT 8 +#define SWREG_MAIN_MAIN9__MPPTTARGETISPERIODS_OVRVAL__WIDTH 1 +#define SWREG_MAIN_MAIN9__MPPTTARGETISPERIODS_OVRVAL__MASK 0x00000100U +#define SWREG_MAIN_MAIN9__MPPTTARGETISPERIODS_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define SWREG_MAIN_MAIN9__MPPTTARGETISPERIODS_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 8) & 0x00000100U) +#define SWREG_MAIN_MAIN9__MPPTTARGETISPERIODS_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((uint32_t)(src) <<\ + 8) & 0x00000100U) +#define SWREG_MAIN_MAIN9__MPPTTARGETISPERIODS_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 8) & ~0x00000100U))) +#define SWREG_MAIN_MAIN9__MPPTTARGETISPERIODS_OVRVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define SWREG_MAIN_MAIN9__MPPTTARGETISPERIODS_OVRVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define SWREG_MAIN_MAIN9__MPPTTARGETISPERIODS_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mpptPeriodsTarget_ovrVal */ +/** + * @defgroup swreg_main_regs_core_mpptPeriodsTarget_ovrVal_field mpptPeriodsTarget_ovrVal_field + * @brief macros for field mpptPeriodsTarget_ovrVal + * @details the target number of rtc clock periods in mppt override mode + * @{ + */ +#define SWREG_MAIN_MAIN9__MPPTPERIODSTARGET_OVRVAL__SHIFT 9 +#define SWREG_MAIN_MAIN9__MPPTPERIODSTARGET_OVRVAL__WIDTH 9 +#define SWREG_MAIN_MAIN9__MPPTPERIODSTARGET_OVRVAL__MASK 0x0003fe00U +#define SWREG_MAIN_MAIN9__MPPTPERIODSTARGET_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x0003fe00U) >> 9) +#define SWREG_MAIN_MAIN9__MPPTPERIODSTARGET_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x0003fe00U) +#define SWREG_MAIN_MAIN9__MPPTPERIODSTARGET_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fe00U) | (((uint32_t)(src) <<\ + 9) & 0x0003fe00U) +#define SWREG_MAIN_MAIN9__MPPTPERIODSTARGET_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x0003fe00U))) +#define SWREG_MAIN_MAIN9__MPPTPERIODSTARGET_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mpptEventsTarget_ovrVal */ +/** + * @defgroup swreg_main_regs_core_mpptEventsTarget_ovrVal_field mpptEventsTarget_ovrVal_field + * @brief macros for field mpptEventsTarget_ovrVal + * @details the target number of switching events in mppt override mode + * @{ + */ +#define SWREG_MAIN_MAIN9__MPPTEVENTSTARGET_OVRVAL__SHIFT 18 +#define SWREG_MAIN_MAIN9__MPPTEVENTSTARGET_OVRVAL__WIDTH 10 +#define SWREG_MAIN_MAIN9__MPPTEVENTSTARGET_OVRVAL__MASK 0x0ffc0000U +#define SWREG_MAIN_MAIN9__MPPTEVENTSTARGET_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x0ffc0000U) >> 18) +#define SWREG_MAIN_MAIN9__MPPTEVENTSTARGET_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x0ffc0000U) +#define SWREG_MAIN_MAIN9__MPPTEVENTSTARGET_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0ffc0000U) | (((uint32_t)(src) <<\ + 18) & 0x0ffc0000U) +#define SWREG_MAIN_MAIN9__MPPTEVENTSTARGET_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x0ffc0000U))) +#define SWREG_MAIN_MAIN9__MPPTEVENTSTARGET_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ateSampleIndCurrent */ +/** + * @defgroup swreg_main_regs_core_ateSampleIndCurrent_field ateSampleIndCurrent_field + * @brief macros for field ateSampleIndCurrent + * @details sample inductor current sign in ate testing. To test the Zero Current Crossing comparator Activate a mode with ateModeSel, ateBuck in dump configuration with ateDump=1. It can be buck-boost or buck, but not boost. Set ateSampleIndCurrent=1. Apply a small positive/negative current to the source terminal of the inductor, which is grounded during dump. Terminate the mode by setting ateModeSel=5'd18, which will make the current flow through the internal sense resistor Read the indCurrentSign bit in the readout register, it should be 0/1 + * @{ + */ +#define SWREG_MAIN_MAIN9__ATESAMPLEINDCURRENT__SHIFT 28 +#define SWREG_MAIN_MAIN9__ATESAMPLEINDCURRENT__WIDTH 1 +#define SWREG_MAIN_MAIN9__ATESAMPLEINDCURRENT__MASK 0x10000000U +#define SWREG_MAIN_MAIN9__ATESAMPLEINDCURRENT__READ(src) \ + (((uint32_t)(src)\ + & 0x10000000U) >> 28) +#define SWREG_MAIN_MAIN9__ATESAMPLEINDCURRENT__WRITE(src) \ + (((uint32_t)(src)\ + << 28) & 0x10000000U) +#define SWREG_MAIN_MAIN9__ATESAMPLEINDCURRENT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((uint32_t)(src) <<\ + 28) & 0x10000000U) +#define SWREG_MAIN_MAIN9__ATESAMPLEINDCURRENT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 28) & ~0x10000000U))) +#define SWREG_MAIN_MAIN9__ATESAMPLEINDCURRENT__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(1) << 28) +#define SWREG_MAIN_MAIN9__ATESAMPLEINDCURRENT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((uint32_t)(0) << 28) +#define SWREG_MAIN_MAIN9__ATESAMPLEINDCURRENT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ateDump */ +/** + * @defgroup swreg_main_regs_core_ateDump_field ateDump_field + * @brief macros for field ateDump + * @details dump in ate testing + * @{ + */ +#define SWREG_MAIN_MAIN9__ATEDUMP__SHIFT 29 +#define SWREG_MAIN_MAIN9__ATEDUMP__WIDTH 1 +#define SWREG_MAIN_MAIN9__ATEDUMP__MASK 0x20000000U +#define SWREG_MAIN_MAIN9__ATEDUMP__READ(src) \ + (((uint32_t)(src)\ + & 0x20000000U) >> 29) +#define SWREG_MAIN_MAIN9__ATEDUMP__WRITE(src) \ + (((uint32_t)(src)\ + << 29) & 0x20000000U) +#define SWREG_MAIN_MAIN9__ATEDUMP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((uint32_t)(src) <<\ + 29) & 0x20000000U) +#define SWREG_MAIN_MAIN9__ATEDUMP__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 29) & ~0x20000000U))) +#define SWREG_MAIN_MAIN9__ATEDUMP__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(1) << 29) +#define SWREG_MAIN_MAIN9__ATEDUMP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((uint32_t)(0) << 29) +#define SWREG_MAIN_MAIN9__ATEDUMP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ateBoost */ +/** + * @defgroup swreg_main_regs_core_ateBoost_field ateBoost_field + * @brief macros for field ateBoost + * @details boost mode in ate testing + * @{ + */ +#define SWREG_MAIN_MAIN9__ATEBOOST__SHIFT 30 +#define SWREG_MAIN_MAIN9__ATEBOOST__WIDTH 1 +#define SWREG_MAIN_MAIN9__ATEBOOST__MASK 0x40000000U +#define SWREG_MAIN_MAIN9__ATEBOOST__READ(src) \ + (((uint32_t)(src)\ + & 0x40000000U) >> 30) +#define SWREG_MAIN_MAIN9__ATEBOOST__WRITE(src) \ + (((uint32_t)(src)\ + << 30) & 0x40000000U) +#define SWREG_MAIN_MAIN9__ATEBOOST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((uint32_t)(src) <<\ + 30) & 0x40000000U) +#define SWREG_MAIN_MAIN9__ATEBOOST__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 30) & ~0x40000000U))) +#define SWREG_MAIN_MAIN9__ATEBOOST__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(1) << 30) +#define SWREG_MAIN_MAIN9__ATEBOOST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((uint32_t)(0) << 30) +#define SWREG_MAIN_MAIN9__ATEBOOST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field ateBuck */ +/** + * @defgroup swreg_main_regs_core_ateBuck_field ateBuck_field + * @brief macros for field ateBuck + * @details buck mode in ate testing + * @{ + */ +#define SWREG_MAIN_MAIN9__ATEBUCK__SHIFT 31 +#define SWREG_MAIN_MAIN9__ATEBUCK__WIDTH 1 +#define SWREG_MAIN_MAIN9__ATEBUCK__MASK 0x80000000U +#define SWREG_MAIN_MAIN9__ATEBUCK__READ(src) \ + (((uint32_t)(src)\ + & 0x80000000U) >> 31) +#define SWREG_MAIN_MAIN9__ATEBUCK__WRITE(src) \ + (((uint32_t)(src)\ + << 31) & 0x80000000U) +#define SWREG_MAIN_MAIN9__ATEBUCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((uint32_t)(src) <<\ + 31) & 0x80000000U) +#define SWREG_MAIN_MAIN9__ATEBUCK__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 31) & ~0x80000000U))) +#define SWREG_MAIN_MAIN9__ATEBUCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(1) << 31) +#define SWREG_MAIN_MAIN9__ATEBUCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((uint32_t)(0) << 31) +#define SWREG_MAIN_MAIN9__ATEBUCK__RESET_VALUE 0x00000000U +/** @} */ +#define SWREG_MAIN_MAIN9__TYPE uint32_t +#define SWREG_MAIN_MAIN9__READ 0xffffffffU +#define SWREG_MAIN_MAIN9__WRITE 0xffffffffU +#define SWREG_MAIN_MAIN9__PRESERVED 0x00000000U +#define SWREG_MAIN_MAIN9__RESET_VALUE 0x00000000U + +#endif /* __SWREG_MAIN_MAIN9_MACRO__ */ + +/** @} end of main9 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_MAIN_main10 */ +/** + * @defgroup swreg_main_regs_core_main10 main10 + * @brief main swreg registers definitions. + * @{ + */ +#ifndef __SWREG_MAIN_MAIN10_MACRO__ +#define __SWREG_MAIN_MAIN10_MACRO__ + +/* macros for field ateModeSel */ +/** + * @defgroup swreg_main_regs_core_ateModeSel_field ateModeSel_field + * @brief macros for field ateModeSel + * @details the power transfer mode activated in ate testing + * @{ + */ +#define SWREG_MAIN_MAIN10__ATEMODESEL__SHIFT 0 +#define SWREG_MAIN_MAIN10__ATEMODESEL__WIDTH 5 +#define SWREG_MAIN_MAIN10__ATEMODESEL__MASK 0x0000001fU +#define SWREG_MAIN_MAIN10__ATEMODESEL__READ(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SWREG_MAIN_MAIN10__ATEMODESEL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x0000001fU) +#define SWREG_MAIN_MAIN10__ATEMODESEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((uint32_t)(src) &\ + 0x0000001fU) +#define SWREG_MAIN_MAIN10__ATEMODESEL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x0000001fU))) +#define SWREG_MAIN_MAIN10__ATEMODESEL__RESET_VALUE 0x00000012U +/** @} */ + +/* macros for field clkFixedCal */ +/** + * @defgroup swreg_main_regs_core_clkFixedCal_field clkFixedCal_field + * @brief macros for field clkFixedCal + * @details fixed time of the clock during calibration + * @{ + */ +#define SWREG_MAIN_MAIN10__CLKFIXEDCAL__SHIFT 5 +#define SWREG_MAIN_MAIN10__CLKFIXEDCAL__WIDTH 4 +#define SWREG_MAIN_MAIN10__CLKFIXEDCAL__MASK 0x000001e0U +#define SWREG_MAIN_MAIN10__CLKFIXEDCAL__READ(src) \ + (((uint32_t)(src)\ + & 0x000001e0U) >> 5) +#define SWREG_MAIN_MAIN10__CLKFIXEDCAL__WRITE(src) \ + (((uint32_t)(src)\ + << 5) & 0x000001e0U) +#define SWREG_MAIN_MAIN10__CLKFIXEDCAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001e0U) | (((uint32_t)(src) <<\ + 5) & 0x000001e0U) +#define SWREG_MAIN_MAIN10__CLKFIXEDCAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 5) & ~0x000001e0U))) +#define SWREG_MAIN_MAIN10__CLKFIXEDCAL__RESET_VALUE 0x00000003U +/** @} */ + +/* macros for field skipClkCal */ +/** + * @defgroup swreg_main_regs_core_skipClkCal_field skipClkCal_field + * @brief macros for field skipClkCal + * @details if set, the clock cal will not be performed and clkUnitDelReg will be used instead + * @{ + */ +#define SWREG_MAIN_MAIN10__SKIPCLKCAL__SHIFT 9 +#define SWREG_MAIN_MAIN10__SKIPCLKCAL__WIDTH 1 +#define SWREG_MAIN_MAIN10__SKIPCLKCAL__MASK 0x00000200U +#define SWREG_MAIN_MAIN10__SKIPCLKCAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define SWREG_MAIN_MAIN10__SKIPCLKCAL__WRITE(src) \ + (((uint32_t)(src)\ + << 9) & 0x00000200U) +#define SWREG_MAIN_MAIN10__SKIPCLKCAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((uint32_t)(src) <<\ + 9) & 0x00000200U) +#define SWREG_MAIN_MAIN10__SKIPCLKCAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 9) & ~0x00000200U))) +#define SWREG_MAIN_MAIN10__SKIPCLKCAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define SWREG_MAIN_MAIN10__SKIPCLKCAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define SWREG_MAIN_MAIN10__SKIPCLKCAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field clkCalCountTarget */ +/** + * @defgroup swreg_main_regs_core_clkCalCountTarget_field clkCalCountTarget_field + * @brief macros for field clkCalCountTarget + * @details the target count for the clock cal (550*32.768KHz ~= 18MHz) + * @{ + */ +#define SWREG_MAIN_MAIN10__CLKCALCOUNTTARGET__SHIFT 10 +#define SWREG_MAIN_MAIN10__CLKCALCOUNTTARGET__WIDTH 10 +#define SWREG_MAIN_MAIN10__CLKCALCOUNTTARGET__MASK 0x000ffc00U +#define SWREG_MAIN_MAIN10__CLKCALCOUNTTARGET__READ(src) \ + (((uint32_t)(src)\ + & 0x000ffc00U) >> 10) +#define SWREG_MAIN_MAIN10__CLKCALCOUNTTARGET__WRITE(src) \ + (((uint32_t)(src)\ + << 10) & 0x000ffc00U) +#define SWREG_MAIN_MAIN10__CLKCALCOUNTTARGET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((uint32_t)(src) <<\ + 10) & 0x000ffc00U) +#define SWREG_MAIN_MAIN10__CLKCALCOUNTTARGET__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define SWREG_MAIN_MAIN10__CLKCALCOUNTTARGET__RESET_VALUE 0x00000226U +/** @} */ + +/* macros for field spare */ +/** + * @defgroup swreg_main_regs_core_spare_field spare_field + * @brief macros for field spare + * @details spare + * @{ + */ +#define SWREG_MAIN_MAIN10__SPARE__SHIFT 20 +#define SWREG_MAIN_MAIN10__SPARE__WIDTH 8 +#define SWREG_MAIN_MAIN10__SPARE__MASK 0x0ff00000U +#define SWREG_MAIN_MAIN10__SPARE__READ(src) \ + (((uint32_t)(src)\ + & 0x0ff00000U) >> 20) +#define SWREG_MAIN_MAIN10__SPARE__WRITE(src) \ + (((uint32_t)(src)\ + << 20) & 0x0ff00000U) +#define SWREG_MAIN_MAIN10__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0ff00000U) | (((uint32_t)(src) <<\ + 20) & 0x0ff00000U) +#define SWREG_MAIN_MAIN10__SPARE__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 20) & ~0x0ff00000U))) +#define SWREG_MAIN_MAIN10__SPARE__RESET_VALUE 0x00000000U +/** @} */ +#define SWREG_MAIN_MAIN10__TYPE uint32_t +#define SWREG_MAIN_MAIN10__READ 0x0fffffffU +#define SWREG_MAIN_MAIN10__WRITE 0x0fffffffU +#define SWREG_MAIN_MAIN10__PRESERVED 0x00000000U +#define SWREG_MAIN_MAIN10__RESET_VALUE 0x00089872U + +#endif /* __SWREG_MAIN_MAIN10_MACRO__ */ + +/** @} end of main10 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_MAIN_readout0 */ +/** + * @defgroup swreg_main_regs_core_readout0 readout0 + * @brief main readout bits definitions. + * @{ + */ +#ifndef __SWREG_MAIN_READOUT0_MACRO__ +#define __SWREG_MAIN_READOUT0_MACRO__ + +/* macros for field request */ +/** + * @defgroup swreg_main_regs_core_request_field request_field + * @brief macros for field request + * @details supply sensing comparators for the 5 supplies + * @{ + */ +#define SWREG_MAIN_READOUT0__REQUEST__SHIFT 0 +#define SWREG_MAIN_READOUT0__REQUEST__WIDTH 5 +#define SWREG_MAIN_READOUT0__REQUEST__MASK 0x0000001fU +#define SWREG_MAIN_READOUT0__REQUEST__READ(src) ((uint32_t)(src) & 0x0000001fU) +#define SWREG_MAIN_READOUT0__REQUEST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field vbattGood */ +/** + * @defgroup swreg_main_regs_core_vbattGood_field vbattGood_field + * @brief macros for field vbattGood + * @details vbatt good comparator + * @{ + */ +#define SWREG_MAIN_READOUT0__VBATTGOOD__SHIFT 5 +#define SWREG_MAIN_READOUT0__VBATTGOOD__WIDTH 1 +#define SWREG_MAIN_READOUT0__VBATTGOOD__MASK 0x00000020U +#define SWREG_MAIN_READOUT0__VBATTGOOD__READ(src) \ + (((uint32_t)(src)\ + & 0x00000020U) >> 5) +#define SWREG_MAIN_READOUT0__VBATTGOOD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(1) << 5) +#define SWREG_MAIN_READOUT0__VBATTGOOD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((uint32_t)(0) << 5) +#define SWREG_MAIN_READOUT0__VBATTGOOD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field vstoreGood */ +/** + * @defgroup swreg_main_regs_core_vstoreGood_field vstoreGood_field + * @brief macros for field vstoreGood + * @details vstore good comparator + * @{ + */ +#define SWREG_MAIN_READOUT0__VSTOREGOOD__SHIFT 6 +#define SWREG_MAIN_READOUT0__VSTOREGOOD__WIDTH 1 +#define SWREG_MAIN_READOUT0__VSTOREGOOD__MASK 0x00000040U +#define SWREG_MAIN_READOUT0__VSTOREGOOD__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define SWREG_MAIN_READOUT0__VSTOREGOOD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define SWREG_MAIN_READOUT0__VSTOREGOOD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define SWREG_MAIN_READOUT0__VSTOREGOOD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field canHarvest */ +/** + * @defgroup swreg_main_regs_core_canHarvest_field canHarvest_field + * @brief macros for field canHarvest + * @details canharvest comparator + * @{ + */ +#define SWREG_MAIN_READOUT0__CANHARVEST__SHIFT 7 +#define SWREG_MAIN_READOUT0__CANHARVEST__WIDTH 1 +#define SWREG_MAIN_READOUT0__CANHARVEST__MASK 0x00000080U +#define SWREG_MAIN_READOUT0__CANHARVEST__READ(src) \ + (((uint32_t)(src)\ + & 0x00000080U) >> 7) +#define SWREG_MAIN_READOUT0__CANHARVEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(1) << 7) +#define SWREG_MAIN_READOUT0__CANHARVEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((uint32_t)(0) << 7) +#define SWREG_MAIN_READOUT0__CANHARVEST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mustHarvest */ +/** + * @defgroup swreg_main_regs_core_mustHarvest_field mustHarvest_field + * @brief macros for field mustHarvest + * @details mustharvest comparator + * @{ + */ +#define SWREG_MAIN_READOUT0__MUSTHARVEST__SHIFT 8 +#define SWREG_MAIN_READOUT0__MUSTHARVEST__WIDTH 1 +#define SWREG_MAIN_READOUT0__MUSTHARVEST__MASK 0x00000100U +#define SWREG_MAIN_READOUT0__MUSTHARVEST__READ(src) \ + (((uint32_t)(src)\ + & 0x00000100U) >> 8) +#define SWREG_MAIN_READOUT0__MUSTHARVEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(1) << 8) +#define SWREG_MAIN_READOUT0__MUSTHARVEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((uint32_t)(0) << 8) +#define SWREG_MAIN_READOUT0__MUSTHARVEST__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field indCurrentSign */ +/** + * @defgroup swreg_main_regs_core_indCurrentSign_field indCurrentSign_field + * @brief macros for field indCurrentSign + * @details inductor current sign comparator + * @{ + */ +#define SWREG_MAIN_READOUT0__INDCURRENTSIGN__SHIFT 9 +#define SWREG_MAIN_READOUT0__INDCURRENTSIGN__WIDTH 1 +#define SWREG_MAIN_READOUT0__INDCURRENTSIGN__MASK 0x00000200U +#define SWREG_MAIN_READOUT0__INDCURRENTSIGN__READ(src) \ + (((uint32_t)(src)\ + & 0x00000200U) >> 9) +#define SWREG_MAIN_READOUT0__INDCURRENTSIGN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(1) << 9) +#define SWREG_MAIN_READOUT0__INDCURRENTSIGN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((uint32_t)(0) << 9) +#define SWREG_MAIN_READOUT0__INDCURRENTSIGN__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field hop */ +/** + * @defgroup swreg_main_regs_core_hop_field hop_field + * @brief macros for field hop + * @details hop indicators for the 5 supplies + * @{ + */ +#define SWREG_MAIN_READOUT0__HOP__SHIFT 10 +#define SWREG_MAIN_READOUT0__HOP__WIDTH 5 +#define SWREG_MAIN_READOUT0__HOP__MASK 0x00007c00U +#define SWREG_MAIN_READOUT0__HOP__READ(src) \ + (((uint32_t)(src)\ + & 0x00007c00U) >> 10) +#define SWREG_MAIN_READOUT0__HOP__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field freqCountSum_dvdd */ +/** + * @defgroup swreg_main_regs_core_freqCountSum_dvdd_field freqCountSum_dvdd_field + * @brief macros for field freqCountSum_dvdd + * @details dvdd switching event count in recent history window + * @{ + */ +#define SWREG_MAIN_READOUT0__FREQCOUNTSUM_DVDD__SHIFT 15 +#define SWREG_MAIN_READOUT0__FREQCOUNTSUM_DVDD__WIDTH 8 +#define SWREG_MAIN_READOUT0__FREQCOUNTSUM_DVDD__MASK 0x007f8000U +#define SWREG_MAIN_READOUT0__FREQCOUNTSUM_DVDD__READ(src) \ + (((uint32_t)(src)\ + & 0x007f8000U) >> 15) +#define SWREG_MAIN_READOUT0__FREQCOUNTSUM_DVDD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field freqCountSum_vaux */ +/** + * @defgroup swreg_main_regs_core_freqCountSum_vaux_field freqCountSum_vaux_field + * @brief macros for field freqCountSum_vaux + * @details vaux switching event count in recent history window + * @{ + */ +#define SWREG_MAIN_READOUT0__FREQCOUNTSUM_VAUX__SHIFT 23 +#define SWREG_MAIN_READOUT0__FREQCOUNTSUM_VAUX__WIDTH 8 +#define SWREG_MAIN_READOUT0__FREQCOUNTSUM_VAUX__MASK 0x7f800000U +#define SWREG_MAIN_READOUT0__FREQCOUNTSUM_VAUX__READ(src) \ + (((uint32_t)(src)\ + & 0x7f800000U) >> 23) +#define SWREG_MAIN_READOUT0__FREQCOUNTSUM_VAUX__RESET_VALUE 0x00000000U +/** @} */ +#define SWREG_MAIN_READOUT0__TYPE uint32_t +#define SWREG_MAIN_READOUT0__READ 0x7fffffffU +#define SWREG_MAIN_READOUT0__PRESERVED 0x00000000U +#define SWREG_MAIN_READOUT0__RESET_VALUE 0x00000000U + +#endif /* __SWREG_MAIN_READOUT0_MACRO__ */ + +/** @} end of readout0 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_MAIN_readout1 */ +/** + * @defgroup swreg_main_regs_core_readout1 readout1 + * @brief main readout bits definitions. + * @{ + */ +#ifndef __SWREG_MAIN_READOUT1_MACRO__ +#define __SWREG_MAIN_READOUT1_MACRO__ + +/* macros for field freqCountSum_vddio */ +/** + * @defgroup swreg_main_regs_core_freqCountSum_vddio_field freqCountSum_vddio_field + * @brief macros for field freqCountSum_vddio + * @details vddio switching event count in recent history window + * @{ + */ +#define SWREG_MAIN_READOUT1__FREQCOUNTSUM_VDDIO__SHIFT 0 +#define SWREG_MAIN_READOUT1__FREQCOUNTSUM_VDDIO__WIDTH 8 +#define SWREG_MAIN_READOUT1__FREQCOUNTSUM_VDDIO__MASK 0x000000ffU +#define SWREG_MAIN_READOUT1__FREQCOUNTSUM_VDDIO__READ(src) \ + ((uint32_t)(src)\ + & 0x000000ffU) +#define SWREG_MAIN_READOUT1__FREQCOUNTSUM_VDDIO__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field freqCountSum_avdd */ +/** + * @defgroup swreg_main_regs_core_freqCountSum_avdd_field freqCountSum_avdd_field + * @brief macros for field freqCountSum_avdd + * @details avdd switching event count in recent history window + * @{ + */ +#define SWREG_MAIN_READOUT1__FREQCOUNTSUM_AVDD__SHIFT 8 +#define SWREG_MAIN_READOUT1__FREQCOUNTSUM_AVDD__WIDTH 8 +#define SWREG_MAIN_READOUT1__FREQCOUNTSUM_AVDD__MASK 0x0000ff00U +#define SWREG_MAIN_READOUT1__FREQCOUNTSUM_AVDD__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SWREG_MAIN_READOUT1__FREQCOUNTSUM_AVDD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field freqCountSum_vstore */ +/** + * @defgroup swreg_main_regs_core_freqCountSum_vstore_field freqCountSum_vstore_field + * @brief macros for field freqCountSum_vstore + * @details vstore switching event count in recent history window + * @{ + */ +#define SWREG_MAIN_READOUT1__FREQCOUNTSUM_VSTORE__SHIFT 16 +#define SWREG_MAIN_READOUT1__FREQCOUNTSUM_VSTORE__WIDTH 8 +#define SWREG_MAIN_READOUT1__FREQCOUNTSUM_VSTORE__MASK 0x00ff0000U +#define SWREG_MAIN_READOUT1__FREQCOUNTSUM_VSTORE__READ(src) \ + (((uint32_t)(src)\ + & 0x00ff0000U) >> 16) +#define SWREG_MAIN_READOUT1__FREQCOUNTSUM_VSTORE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mpptDone */ +/** + * @defgroup swreg_main_regs_core_mpptDone_field mpptDone_field + * @brief macros for field mpptDone + * @details if 1 the mppt the target number of periods or events is reached + * @{ + */ +#define SWREG_MAIN_READOUT1__MPPTDONE__SHIFT 24 +#define SWREG_MAIN_READOUT1__MPPTDONE__WIDTH 1 +#define SWREG_MAIN_READOUT1__MPPTDONE__MASK 0x01000000U +#define SWREG_MAIN_READOUT1__MPPTDONE__READ(src) \ + (((uint32_t)(src)\ + & 0x01000000U) >> 24) +#define SWREG_MAIN_READOUT1__MPPTDONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(1) << 24) +#define SWREG_MAIN_READOUT1__MPPTDONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((uint32_t)(0) << 24) +#define SWREG_MAIN_READOUT1__MPPTDONE__RESET_VALUE 0x00000000U +/** @} */ +#define SWREG_MAIN_READOUT1__TYPE uint32_t +#define SWREG_MAIN_READOUT1__READ 0x01ffffffU +#define SWREG_MAIN_READOUT1__PRESERVED 0x00000000U +#define SWREG_MAIN_READOUT1__RESET_VALUE 0x00000000U + +#endif /* __SWREG_MAIN_READOUT1_MACRO__ */ + +/** @} end of readout1 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_MAIN_readout2 */ +/** + * @defgroup swreg_main_regs_core_readout2 readout2 + * @brief main readout bits definitions. + * @{ + */ +#ifndef __SWREG_MAIN_READOUT2_MACRO__ +#define __SWREG_MAIN_READOUT2_MACRO__ + +/* macros for field mpptPeriodCount */ +/** + * @defgroup swreg_main_regs_core_mpptPeriodCount_field mpptPeriodCount_field + * @brief macros for field mpptPeriodCount + * @details the measured number of periods when mpptTargetIsPeriods=0 + * @{ + */ +#define SWREG_MAIN_READOUT2__MPPTPERIODCOUNT__SHIFT 0 +#define SWREG_MAIN_READOUT2__MPPTPERIODCOUNT__WIDTH 9 +#define SWREG_MAIN_READOUT2__MPPTPERIODCOUNT__MASK 0x000001ffU +#define SWREG_MAIN_READOUT2__MPPTPERIODCOUNT__READ(src) \ + ((uint32_t)(src)\ + & 0x000001ffU) +#define SWREG_MAIN_READOUT2__MPPTPERIODCOUNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field mpptEventCount */ +/** + * @defgroup swreg_main_regs_core_mpptEventCount_field mpptEventCount_field + * @brief macros for field mpptEventCount + * @details the measured number of events when mpptTargetIsPeriods=1. Also the exact number of events when mpptTargetIsPeriods=0. + * @{ + */ +#define SWREG_MAIN_READOUT2__MPPTEVENTCOUNT__SHIFT 9 +#define SWREG_MAIN_READOUT2__MPPTEVENTCOUNT__WIDTH 10 +#define SWREG_MAIN_READOUT2__MPPTEVENTCOUNT__MASK 0x0007fe00U +#define SWREG_MAIN_READOUT2__MPPTEVENTCOUNT__READ(src) \ + (((uint32_t)(src)\ + & 0x0007fe00U) >> 9) +#define SWREG_MAIN_READOUT2__MPPTEVENTCOUNT__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field gear_batt_dvdd */ +/** + * @defgroup swreg_main_regs_core_gear_batt_dvdd_field gear_batt_dvdd_field + * @brief macros for field gear_batt_dvdd + * @details gear for battery to dvdd mode + * @{ + */ +#define SWREG_MAIN_READOUT2__GEAR_BATT_DVDD__SHIFT 19 +#define SWREG_MAIN_READOUT2__GEAR_BATT_DVDD__WIDTH 4 +#define SWREG_MAIN_READOUT2__GEAR_BATT_DVDD__MASK 0x00780000U +#define SWREG_MAIN_READOUT2__GEAR_BATT_DVDD__READ(src) \ + (((uint32_t)(src)\ + & 0x00780000U) >> 19) +#define SWREG_MAIN_READOUT2__GEAR_BATT_DVDD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field gear_batt_vaux */ +/** + * @defgroup swreg_main_regs_core_gear_batt_vaux_field gear_batt_vaux_field + * @brief macros for field gear_batt_vaux + * @details gear for battery to vaux mode + * @{ + */ +#define SWREG_MAIN_READOUT2__GEAR_BATT_VAUX__SHIFT 23 +#define SWREG_MAIN_READOUT2__GEAR_BATT_VAUX__WIDTH 4 +#define SWREG_MAIN_READOUT2__GEAR_BATT_VAUX__MASK 0x07800000U +#define SWREG_MAIN_READOUT2__GEAR_BATT_VAUX__READ(src) \ + (((uint32_t)(src)\ + & 0x07800000U) >> 23) +#define SWREG_MAIN_READOUT2__GEAR_BATT_VAUX__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field gear_batt_vddio */ +/** + * @defgroup swreg_main_regs_core_gear_batt_vddio_field gear_batt_vddio_field + * @brief macros for field gear_batt_vddio + * @details gear for battery to vddio mode + * @{ + */ +#define SWREG_MAIN_READOUT2__GEAR_BATT_VDDIO__SHIFT 27 +#define SWREG_MAIN_READOUT2__GEAR_BATT_VDDIO__WIDTH 4 +#define SWREG_MAIN_READOUT2__GEAR_BATT_VDDIO__MASK 0x78000000U +#define SWREG_MAIN_READOUT2__GEAR_BATT_VDDIO__READ(src) \ + (((uint32_t)(src)\ + & 0x78000000U) >> 27) +#define SWREG_MAIN_READOUT2__GEAR_BATT_VDDIO__RESET_VALUE 0x00000000U +/** @} */ +#define SWREG_MAIN_READOUT2__TYPE uint32_t +#define SWREG_MAIN_READOUT2__READ 0x7fffffffU +#define SWREG_MAIN_READOUT2__PRESERVED 0x00000000U +#define SWREG_MAIN_READOUT2__RESET_VALUE 0x00000000U + +#endif /* __SWREG_MAIN_READOUT2_MACRO__ */ + +/** @} end of readout2 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_MAIN_readout3 */ +/** + * @defgroup swreg_main_regs_core_readout3 readout3 + * @brief main readout bits definitions. + * @{ + */ +#ifndef __SWREG_MAIN_READOUT3_MACRO__ +#define __SWREG_MAIN_READOUT3_MACRO__ + +/* macros for field gear_batt_avdd */ +/** + * @defgroup swreg_main_regs_core_gear_batt_avdd_field gear_batt_avdd_field + * @brief macros for field gear_batt_avdd + * @details gear for battery to avdd mode + * @{ + */ +#define SWREG_MAIN_READOUT3__GEAR_BATT_AVDD__SHIFT 0 +#define SWREG_MAIN_READOUT3__GEAR_BATT_AVDD__WIDTH 4 +#define SWREG_MAIN_READOUT3__GEAR_BATT_AVDD__MASK 0x0000000fU +#define SWREG_MAIN_READOUT3__GEAR_BATT_AVDD__READ(src) \ + ((uint32_t)(src)\ + & 0x0000000fU) +#define SWREG_MAIN_READOUT3__GEAR_BATT_AVDD__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field gear_batt_store */ +/** + * @defgroup swreg_main_regs_core_gear_batt_store_field gear_batt_store_field + * @brief macros for field gear_batt_store + * @details gear for battery to store mode + * @{ + */ +#define SWREG_MAIN_READOUT3__GEAR_BATT_STORE__SHIFT 4 +#define SWREG_MAIN_READOUT3__GEAR_BATT_STORE__WIDTH 4 +#define SWREG_MAIN_READOUT3__GEAR_BATT_STORE__MASK 0x000000f0U +#define SWREG_MAIN_READOUT3__GEAR_BATT_STORE__READ(src) \ + (((uint32_t)(src)\ + & 0x000000f0U) >> 4) +#define SWREG_MAIN_READOUT3__GEAR_BATT_STORE__RESET_VALUE 0x00000000U +/** @} */ +#define SWREG_MAIN_READOUT3__TYPE uint32_t +#define SWREG_MAIN_READOUT3__READ 0x000000ffU +#define SWREG_MAIN_READOUT3__PRESERVED 0x00000000U +#define SWREG_MAIN_READOUT3__RESET_VALUE 0x00000000U + +#endif /* __SWREG_MAIN_READOUT3_MACRO__ */ + +/** @} end of readout3 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_MAIN_core_id */ +/** + * @defgroup swreg_main_regs_core_core_id core_id + * @brief Contains register fields associated with core_id. definitions. + * @{ + */ +#ifndef __SWREG_MAIN_CORE_ID_MACRO__ +#define __SWREG_MAIN_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup swreg_main_regs_core_id_field id_field + * @brief macros for field id + * @details SWRM in ASCII + * @{ + */ +#define SWREG_MAIN_CORE_ID__ID__SHIFT 0 +#define SWREG_MAIN_CORE_ID__ID__WIDTH 32 +#define SWREG_MAIN_CORE_ID__ID__MASK 0xffffffffU +#define SWREG_MAIN_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define SWREG_MAIN_CORE_ID__ID__RESET_VALUE 0x5357524dU +/** @} */ +#define SWREG_MAIN_CORE_ID__TYPE uint32_t +#define SWREG_MAIN_CORE_ID__READ 0xffffffffU +#define SWREG_MAIN_CORE_ID__PRESERVED 0x00000000U +#define SWREG_MAIN_CORE_ID__RESET_VALUE 0x5357524dU + +#endif /* __SWREG_MAIN_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of SWREG_MAIN_REGS_CORE */ +#endif /* __REG_SWREG_MAIN_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/reg/swreg_simple_regs_core_macro.h b/ATM33xx-5/include/reg/swreg_simple_regs_core_macro.h new file mode 100644 index 0000000..d360a77 --- /dev/null +++ b/ATM33xx-5/include/reg/swreg_simple_regs_core_macro.h @@ -0,0 +1,464 @@ +/* */ +/* File: swreg_simple_regs_core_macro.h */ +/* */ +/* Arguments: /cad/tools/cadence/blueprint_3.7.5/Linux-64bit/blueprint -eval*/ +/* $DEFINE_PROPERTY=1; -ansic swreg_simple_regs_core.rdl */ +/* */ +/* Blueprint: 3.7.5 (Wed Feb 1 23:58:40 PST 2012) */ +/* Machine: gull */ +/* OS: Linux 2.6.32-696.13.2.el6.x86_64 */ +/* Description: */ +/* */ +/* No Description Provided */ +/* */ +/* Copyright (C) 2024 Atmosic Technologies. All rights reserved */ +/* */ + + +#ifndef __REG_SWREG_SIMPLE_REGS_CORE_H__ +#define __REG_SWREG_SIMPLE_REGS_CORE_H__ + +/** + ***************************************************************************** + * @defgroup SWREG_SIMPLE_REGS_CORE swreg_simple_regs_core + * @ingroup AT_REG + * @brief swreg_simple_regs_core definitions. + * @{ + ***************************************************************************** + */ + +/* macros for BlueprintGlobalNameSpace::SWREG_SIMPLE_simple0 */ +/** + * @defgroup swreg_simple_regs_core_simple0 simple0 + * @brief simple swreg registers For fields that refer to the sources the order is: 2: BATT 1: STORE 0: HARV For fields that refer to the destinations the order is: 4: STORE 3: AVDD 2: VDDIO 1: VDDAUX 0: DVDD For fields that refer to the supplies the order is: 3: AVDD 2: VDDIO 1: VDDAUX 0: DVDD For fields that refer to the power transfer modes the order is: 12: HARV -> STORE11: HARV -> AVDD10: HARV -> VDDIO9: HARV -> VDDAUX8: HARV -> DVDD7: STORE -> AVDD6: STORE -> VDDIO5: STORE -> VDDAUX4: STORE -> DVDD3: BATT -> AVDD2: BATT -> VDDIO1: BATT -> VDDAUX0: BATT -> DVDD definitions. + * @{ + */ +#ifndef __SWREG_SIMPLE_SIMPLE0_MACRO__ +#define __SWREG_SIMPLE_SIMPLE0_MACRO__ + +/* macros for field loadRegSimple */ +/** + * @defgroup swreg_simple_regs_core_loadRegSimple_field loadRegSimple_field + * @brief macros for field loadRegSimple + * @details load the Simple shadow register + * @{ + */ +#define SWREG_SIMPLE_SIMPLE0__LOADREGSIMPLE__SHIFT 0 +#define SWREG_SIMPLE_SIMPLE0__LOADREGSIMPLE__WIDTH 1 +#define SWREG_SIMPLE_SIMPLE0__LOADREGSIMPLE__MASK 0x00000001U +#define SWREG_SIMPLE_SIMPLE0__LOADREGSIMPLE__READ(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWREG_SIMPLE_SIMPLE0__LOADREGSIMPLE__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00000001U) +#define SWREG_SIMPLE_SIMPLE0__LOADREGSIMPLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((uint32_t)(src) &\ + 0x00000001U) +#define SWREG_SIMPLE_SIMPLE0__LOADREGSIMPLE__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00000001U))) +#define SWREG_SIMPLE_SIMPLE0__LOADREGSIMPLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(1) +#define SWREG_SIMPLE_SIMPLE0__LOADREGSIMPLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (uint32_t)(0) +#define SWREG_SIMPLE_SIMPLE0__LOADREGSIMPLE__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field divCk32Mppt */ +/** + * @defgroup swreg_simple_regs_core_divCk32Mppt_field divCk32Mppt_field + * @brief macros for field divCk32Mppt + * @details divide the 32KHz clock used in mppt by (divCk32Mppt+1). Zero means no division. + * @{ + */ +#define SWREG_SIMPLE_SIMPLE0__DIVCK32MPPT__SHIFT 1 +#define SWREG_SIMPLE_SIMPLE0__DIVCK32MPPT__WIDTH 5 +#define SWREG_SIMPLE_SIMPLE0__DIVCK32MPPT__MASK 0x0000003eU +#define SWREG_SIMPLE_SIMPLE0__DIVCK32MPPT__READ(src) \ + (((uint32_t)(src)\ + & 0x0000003eU) >> 1) +#define SWREG_SIMPLE_SIMPLE0__DIVCK32MPPT__WRITE(src) \ + (((uint32_t)(src)\ + << 1) & 0x0000003eU) +#define SWREG_SIMPLE_SIMPLE0__DIVCK32MPPT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003eU) | (((uint32_t)(src) <<\ + 1) & 0x0000003eU) +#define SWREG_SIMPLE_SIMPLE0__DIVCK32MPPT__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 1) & ~0x0000003eU))) +#define SWREG_SIMPLE_SIMPLE0__DIVCK32MPPT__RESET_VALUE 0x00000007U +/** @} */ + +/* macros for field scaleEnerg_ovr */ +/** + * @defgroup swreg_simple_regs_core_scaleEnerg_ovr_field scaleEnerg_ovr_field + * @brief macros for field scaleEnerg_ovr + * @details override scaling of energize time + * @{ + */ +#define SWREG_SIMPLE_SIMPLE0__SCALEENERG_OVR__SHIFT 6 +#define SWREG_SIMPLE_SIMPLE0__SCALEENERG_OVR__WIDTH 1 +#define SWREG_SIMPLE_SIMPLE0__SCALEENERG_OVR__MASK 0x00000040U +#define SWREG_SIMPLE_SIMPLE0__SCALEENERG_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00000040U) >> 6) +#define SWREG_SIMPLE_SIMPLE0__SCALEENERG_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 6) & 0x00000040U) +#define SWREG_SIMPLE_SIMPLE0__SCALEENERG_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((uint32_t)(src) <<\ + 6) & 0x00000040U) +#define SWREG_SIMPLE_SIMPLE0__SCALEENERG_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 6) & ~0x00000040U))) +#define SWREG_SIMPLE_SIMPLE0__SCALEENERG_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(1) << 6) +#define SWREG_SIMPLE_SIMPLE0__SCALEENERG_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((uint32_t)(0) << 6) +#define SWREG_SIMPLE_SIMPLE0__SCALEENERG_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field scaleEnerg_ovrVal */ +/** + * @defgroup swreg_simple_regs_core_scaleEnerg_ovrVal_field scaleEnerg_ovrVal_field + * @brief macros for field scaleEnerg_ovrVal + * @details override value for scaling of energize time, 3 bits for each source: setting of (0:7) corresponds to scaling of (1, 1.125, 1.375, 1.625, 2, 3, 4, 8) + * @{ + */ +#define SWREG_SIMPLE_SIMPLE0__SCALEENERG_OVRVAL__SHIFT 7 +#define SWREG_SIMPLE_SIMPLE0__SCALEENERG_OVRVAL__WIDTH 9 +#define SWREG_SIMPLE_SIMPLE0__SCALEENERG_OVRVAL__MASK 0x0000ff80U +#define SWREG_SIMPLE_SIMPLE0__SCALEENERG_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x0000ff80U) >> 7) +#define SWREG_SIMPLE_SIMPLE0__SCALEENERG_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 7) & 0x0000ff80U) +#define SWREG_SIMPLE_SIMPLE0__SCALEENERG_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff80U) | (((uint32_t)(src) <<\ + 7) & 0x0000ff80U) +#define SWREG_SIMPLE_SIMPLE0__SCALEENERG_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 7) & ~0x0000ff80U))) +#define SWREG_SIMPLE_SIMPLE0__SCALEENERG_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enableHarv2Sup_ovr */ +/** + * @defgroup swreg_simple_regs_core_enableHarv2Sup_ovr_field enableHarv2Sup_ovr_field + * @brief macros for field enableHarv2Sup_ovr + * @details override enable for harvest to supplies modes + * @{ + */ +#define SWREG_SIMPLE_SIMPLE0__ENABLEHARV2SUP_OVR__SHIFT 16 +#define SWREG_SIMPLE_SIMPLE0__ENABLEHARV2SUP_OVR__WIDTH 1 +#define SWREG_SIMPLE_SIMPLE0__ENABLEHARV2SUP_OVR__MASK 0x00010000U +#define SWREG_SIMPLE_SIMPLE0__ENABLEHARV2SUP_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00010000U) >> 16) +#define SWREG_SIMPLE_SIMPLE0__ENABLEHARV2SUP_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 16) & 0x00010000U) +#define SWREG_SIMPLE_SIMPLE0__ENABLEHARV2SUP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((uint32_t)(src) <<\ + 16) & 0x00010000U) +#define SWREG_SIMPLE_SIMPLE0__ENABLEHARV2SUP_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 16) & ~0x00010000U))) +#define SWREG_SIMPLE_SIMPLE0__ENABLEHARV2SUP_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(1) << 16) +#define SWREG_SIMPLE_SIMPLE0__ENABLEHARV2SUP_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((uint32_t)(0) << 16) +#define SWREG_SIMPLE_SIMPLE0__ENABLEHARV2SUP_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field enableHarv2Sup_ovrVal */ +/** + * @defgroup swreg_simple_regs_core_enableHarv2Sup_ovrVal_field enableHarv2Sup_ovrVal_field + * @brief macros for field enableHarv2Sup_ovrVal + * @details override value of the enable for harvest to supplies modes + * @{ + */ +#define SWREG_SIMPLE_SIMPLE0__ENABLEHARV2SUP_OVRVAL__SHIFT 17 +#define SWREG_SIMPLE_SIMPLE0__ENABLEHARV2SUP_OVRVAL__WIDTH 1 +#define SWREG_SIMPLE_SIMPLE0__ENABLEHARV2SUP_OVRVAL__MASK 0x00020000U +#define SWREG_SIMPLE_SIMPLE0__ENABLEHARV2SUP_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00020000U) >> 17) +#define SWREG_SIMPLE_SIMPLE0__ENABLEHARV2SUP_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 17) & 0x00020000U) +#define SWREG_SIMPLE_SIMPLE0__ENABLEHARV2SUP_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((uint32_t)(src) <<\ + 17) & 0x00020000U) +#define SWREG_SIMPLE_SIMPLE0__ENABLEHARV2SUP_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 17) & ~0x00020000U))) +#define SWREG_SIMPLE_SIMPLE0__ENABLEHARV2SUP_OVRVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(1) << 17) +#define SWREG_SIMPLE_SIMPLE0__ENABLEHARV2SUP_OVRVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((uint32_t)(0) << 17) +#define SWREG_SIMPLE_SIMPLE0__ENABLEHARV2SUP_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fixHarvEnerg_ovr */ +/** + * @defgroup swreg_simple_regs_core_fixHarvEnerg_ovr_field fixHarvEnerg_ovr_field + * @brief macros for field fixHarvEnerg_ovr + * @details override fixing the energize time (fixHarvEnerg) for all destinations when the source is the harvester if fixHarvEnerg=1 the target for the harvest to supply modes is the energize time, otherwise it is the dump time if set, timeTargetHarv2Store_SH is used as the energize time + * @{ + */ +#define SWREG_SIMPLE_SIMPLE0__FIXHARVENERG_OVR__SHIFT 18 +#define SWREG_SIMPLE_SIMPLE0__FIXHARVENERG_OVR__WIDTH 1 +#define SWREG_SIMPLE_SIMPLE0__FIXHARVENERG_OVR__MASK 0x00040000U +#define SWREG_SIMPLE_SIMPLE0__FIXHARVENERG_OVR__READ(src) \ + (((uint32_t)(src)\ + & 0x00040000U) >> 18) +#define SWREG_SIMPLE_SIMPLE0__FIXHARVENERG_OVR__WRITE(src) \ + (((uint32_t)(src)\ + << 18) & 0x00040000U) +#define SWREG_SIMPLE_SIMPLE0__FIXHARVENERG_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((uint32_t)(src) <<\ + 18) & 0x00040000U) +#define SWREG_SIMPLE_SIMPLE0__FIXHARVENERG_OVR__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 18) & ~0x00040000U))) +#define SWREG_SIMPLE_SIMPLE0__FIXHARVENERG_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(1) << 18) +#define SWREG_SIMPLE_SIMPLE0__FIXHARVENERG_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((uint32_t)(0) << 18) +#define SWREG_SIMPLE_SIMPLE0__FIXHARVENERG_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field fixHarvEnerg_ovrVal */ +/** + * @defgroup swreg_simple_regs_core_fixHarvEnerg_ovrVal_field fixHarvEnerg_ovrVal_field + * @brief macros for field fixHarvEnerg_ovrVal + * @details override value for fixing the energize time for all destinations when the source is the harvester + * @{ + */ +#define SWREG_SIMPLE_SIMPLE0__FIXHARVENERG_OVRVAL__SHIFT 19 +#define SWREG_SIMPLE_SIMPLE0__FIXHARVENERG_OVRVAL__WIDTH 1 +#define SWREG_SIMPLE_SIMPLE0__FIXHARVENERG_OVRVAL__MASK 0x00080000U +#define SWREG_SIMPLE_SIMPLE0__FIXHARVENERG_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x00080000U) >> 19) +#define SWREG_SIMPLE_SIMPLE0__FIXHARVENERG_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 19) & 0x00080000U) +#define SWREG_SIMPLE_SIMPLE0__FIXHARVENERG_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((uint32_t)(src) <<\ + 19) & 0x00080000U) +#define SWREG_SIMPLE_SIMPLE0__FIXHARVENERG_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 19) & ~0x00080000U))) +#define SWREG_SIMPLE_SIMPLE0__FIXHARVENERG_OVRVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(1) << 19) +#define SWREG_SIMPLE_SIMPLE0__FIXHARVENERG_OVRVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((uint32_t)(0) << 19) +#define SWREG_SIMPLE_SIMPLE0__FIXHARVENERG_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ +#define SWREG_SIMPLE_SIMPLE0__TYPE uint32_t +#define SWREG_SIMPLE_SIMPLE0__READ 0x000fffffU +#define SWREG_SIMPLE_SIMPLE0__WRITE 0x000fffffU +#define SWREG_SIMPLE_SIMPLE0__PRESERVED 0x00000000U +#define SWREG_SIMPLE_SIMPLE0__RESET_VALUE 0x0000000eU + +#endif /* __SWREG_SIMPLE_SIMPLE0_MACRO__ */ + +/** @} end of simple0 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_SIMPLE_simple1 */ +/** + * @defgroup swreg_simple_regs_core_simple1 simple1 + * @brief simple swreg registers definitions. + * @{ + */ +#ifndef __SWREG_SIMPLE_SIMPLE1_MACRO__ +#define __SWREG_SIMPLE_SIMPLE1_MACRO__ + +/* macros for field buckBoost_ovr */ +/** + * @defgroup swreg_simple_regs_core_buckBoost_ovr_field buckBoost_ovr_field + * @brief macros for field buckBoost_ovr + * @details override the buck or boost mode + * @{ + */ +#define SWREG_SIMPLE_SIMPLE1__BUCKBOOST_OVR__SHIFT 0 +#define SWREG_SIMPLE_SIMPLE1__BUCKBOOST_OVR__WIDTH 13 +#define SWREG_SIMPLE_SIMPLE1__BUCKBOOST_OVR__MASK 0x00001fffU +#define SWREG_SIMPLE_SIMPLE1__BUCKBOOST_OVR__READ(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define SWREG_SIMPLE_SIMPLE1__BUCKBOOST_OVR__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define SWREG_SIMPLE_SIMPLE1__BUCKBOOST_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fffU) | ((uint32_t)(src) &\ + 0x00001fffU) +#define SWREG_SIMPLE_SIMPLE1__BUCKBOOST_OVR__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00001fffU))) +#define SWREG_SIMPLE_SIMPLE1__BUCKBOOST_OVR__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field buck_ovrVal */ +/** + * @defgroup swreg_simple_regs_core_buck_ovrVal_field buck_ovrVal_field + * @brief macros for field buck_ovrVal + * @details if set when the corresponding buckBoost_ovr bit is one, buck mode will be used for this power transfer mode + * @{ + */ +#define SWREG_SIMPLE_SIMPLE1__BUCK_OVRVAL__SHIFT 13 +#define SWREG_SIMPLE_SIMPLE1__BUCK_OVRVAL__WIDTH 13 +#define SWREG_SIMPLE_SIMPLE1__BUCK_OVRVAL__MASK 0x03ffe000U +#define SWREG_SIMPLE_SIMPLE1__BUCK_OVRVAL__READ(src) \ + (((uint32_t)(src)\ + & 0x03ffe000U) >> 13) +#define SWREG_SIMPLE_SIMPLE1__BUCK_OVRVAL__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x03ffe000U) +#define SWREG_SIMPLE_SIMPLE1__BUCK_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03ffe000U) | (((uint32_t)(src) <<\ + 13) & 0x03ffe000U) +#define SWREG_SIMPLE_SIMPLE1__BUCK_OVRVAL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x03ffe000U))) +#define SWREG_SIMPLE_SIMPLE1__BUCK_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ +#define SWREG_SIMPLE_SIMPLE1__TYPE uint32_t +#define SWREG_SIMPLE_SIMPLE1__READ 0x03ffffffU +#define SWREG_SIMPLE_SIMPLE1__WRITE 0x03ffffffU +#define SWREG_SIMPLE_SIMPLE1__PRESERVED 0x00000000U +#define SWREG_SIMPLE_SIMPLE1__RESET_VALUE 0x00000000U + +#endif /* __SWREG_SIMPLE_SIMPLE1_MACRO__ */ + +/** @} end of simple1 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_SIMPLE_simple2 */ +/** + * @defgroup swreg_simple_regs_core_simple2 simple2 + * @brief simple swreg registers definitions. + * @{ + */ +#ifndef __SWREG_SIMPLE_SIMPLE2_MACRO__ +#define __SWREG_SIMPLE_SIMPLE2_MACRO__ + +/* macros for field boost_ovrVal */ +/** + * @defgroup swreg_simple_regs_core_boost_ovrVal_field boost_ovrVal_field + * @brief macros for field boost_ovrVal + * @details if set when the corresponding buckBoost_ovr bit is one and buck_ovrVal is zero, boost mode will be used for this power transfer mode.if both buck_ovrVal and boost_ovrVal are zero buck-boost mode will be used. + * @{ + */ +#define SWREG_SIMPLE_SIMPLE2__BOOST_OVRVAL__SHIFT 0 +#define SWREG_SIMPLE_SIMPLE2__BOOST_OVRVAL__WIDTH 13 +#define SWREG_SIMPLE_SIMPLE2__BOOST_OVRVAL__MASK 0x00001fffU +#define SWREG_SIMPLE_SIMPLE2__BOOST_OVRVAL__READ(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define SWREG_SIMPLE_SIMPLE2__BOOST_OVRVAL__WRITE(src) \ + ((uint32_t)(src)\ + & 0x00001fffU) +#define SWREG_SIMPLE_SIMPLE2__BOOST_OVRVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fffU) | ((uint32_t)(src) &\ + 0x00001fffU) +#define SWREG_SIMPLE_SIMPLE2__BOOST_OVRVAL__VERIFY(src) \ + (!(((uint32_t)(src)\ + & ~0x00001fffU))) +#define SWREG_SIMPLE_SIMPLE2__BOOST_OVRVAL__RESET_VALUE 0x00000000U +/** @} */ + +/* macros for field readyForTinyLevel */ +/** + * @defgroup swreg_simple_regs_core_readyForTinyLevel_field readyForTinyLevel_field + * @brief macros for field readyForTinyLevel + * @details transition to the tiny FSM is delayed until the simple FSM has settled according to this setting:0: no wait1: wait until all enabled supplies are ready2: wait until all enabled supplies are ready and the targets have settled3: wait until all enabled supplies have fully settled + * @{ + */ +#define SWREG_SIMPLE_SIMPLE2__READYFORTINYLEVEL__SHIFT 13 +#define SWREG_SIMPLE_SIMPLE2__READYFORTINYLEVEL__WIDTH 2 +#define SWREG_SIMPLE_SIMPLE2__READYFORTINYLEVEL__MASK 0x00006000U +#define SWREG_SIMPLE_SIMPLE2__READYFORTINYLEVEL__READ(src) \ + (((uint32_t)(src)\ + & 0x00006000U) >> 13) +#define SWREG_SIMPLE_SIMPLE2__READYFORTINYLEVEL__WRITE(src) \ + (((uint32_t)(src)\ + << 13) & 0x00006000U) +#define SWREG_SIMPLE_SIMPLE2__READYFORTINYLEVEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00006000U) | (((uint32_t)(src) <<\ + 13) & 0x00006000U) +#define SWREG_SIMPLE_SIMPLE2__READYFORTINYLEVEL__VERIFY(src) \ + (!((((uint32_t)(src)\ + << 13) & ~0x00006000U))) +#define SWREG_SIMPLE_SIMPLE2__READYFORTINYLEVEL__RESET_VALUE 0x00000002U +/** @} */ +#define SWREG_SIMPLE_SIMPLE2__TYPE uint32_t +#define SWREG_SIMPLE_SIMPLE2__READ 0x00007fffU +#define SWREG_SIMPLE_SIMPLE2__WRITE 0x00007fffU +#define SWREG_SIMPLE_SIMPLE2__PRESERVED 0x00000000U +#define SWREG_SIMPLE_SIMPLE2__RESET_VALUE 0x00004000U + +#endif /* __SWREG_SIMPLE_SIMPLE2_MACRO__ */ + +/** @} end of simple2 */ + +/* macros for BlueprintGlobalNameSpace::SWREG_SIMPLE_core_id */ +/** + * @defgroup swreg_simple_regs_core_core_id core_id + * @brief Contains register fields associated with core_id. definitions. + * @{ + */ +#ifndef __SWREG_SIMPLE_CORE_ID_MACRO__ +#define __SWREG_SIMPLE_CORE_ID_MACRO__ + +/* macros for field id */ +/** + * @defgroup swreg_simple_regs_core_id_field id_field + * @brief macros for field id + * @details SWRS in ASCII + * @{ + */ +#define SWREG_SIMPLE_CORE_ID__ID__SHIFT 0 +#define SWREG_SIMPLE_CORE_ID__ID__WIDTH 32 +#define SWREG_SIMPLE_CORE_ID__ID__MASK 0xffffffffU +#define SWREG_SIMPLE_CORE_ID__ID__READ(src) ((uint32_t)(src) & 0xffffffffU) +#define SWREG_SIMPLE_CORE_ID__ID__RESET_VALUE 0x53575253U +/** @} */ +#define SWREG_SIMPLE_CORE_ID__TYPE uint32_t +#define SWREG_SIMPLE_CORE_ID__READ 0xffffffffU +#define SWREG_SIMPLE_CORE_ID__PRESERVED 0x00000000U +#define SWREG_SIMPLE_CORE_ID__RESET_VALUE 0x53575253U + +#endif /* __SWREG_SIMPLE_CORE_ID_MACRO__ */ + +/** @} end of core_id */ + +/** @} end of SWREG_SIMPLE_REGS_CORE */ +#endif /* __REG_SWREG_SIMPLE_REGS_CORE_H__ */ diff --git a/ATM33xx-5/include/test_common.h b/ATM33xx-5/include/test_common.h new file mode 100644 index 0000000..4fabe6f --- /dev/null +++ b/ATM33xx-5/include/test_common.h @@ -0,0 +1,120 @@ +/** + ******************************************************************************* + * + * @file test_common.h + * + * @brief File to include architecture dependent macros/function definitions + * + * Copyright (C) Atmosic 2020-2023 + * + ******************************************************************************* + */ + +#pragma once + +#include +#include "ARMv8MBL.h" +#include "base_addr.h" +#include "retarget_uart.h" +#include "common_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Initialize Floating point + */ +__STATIC_INLINE void CommonInitFP(void) +{ +#ifdef __ARM_FP + SCB->CPACR |= SCB_CPACR_FPU; +#ifdef SECURE_MODE + SCB_NS->CPACR |= SCB_CPACR_FPU; + SCB->NSACR |= (0x3U << 10U); // enable non-secure access to CP10 and CP11 +#endif + __ISB(); + __ASM volatile ("VMSR fpscr, %0" : : "r" (0x00) : ); + return; +#endif // __ARM_FP +} + +// Common Initialization functions +/** + * @brief Initialize MPU regions + */ +void common_mpu_cfg(void); + +/** + * @brief Initialize CPU + */ +void CommonInitCPU(void); +/** + * @brief Initialize System + * @note Initializes SAU and MPC + */ +void CommonInitSystem(void); + +/** + * @brief Initialize System for early boot + * @note This function is safe to call before BSS/Data is initialized + */ +void CommonInitBoot(void); + +#ifdef AUTO_TEST +void secure_gcov_dump(void); +#ifndef SECURE_PROC_ENV +__NO_RETURN void gcov_dump(void); +#endif + +__NO_RETURN +__STATIC_INLINE void TEST_PASSED(void) +{ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + extern void __libc_fini_array(void); + __libc_fini_array(); +#endif + + c_print_str("[*** Test Success ***]\n"); + +#ifndef SECURE_PROC_ENV +#ifdef SECURE_GCOV + secure_gcov_dump(); +#endif +#endif // SECURE_PROC_ENV + /* Halt simulation */ + while (1) { +#ifndef LONG_TEST + c_print_char(4); +#endif + } +} + +__NO_RETURN +__STATIC_INLINE void TEST_FAILED(void) +{ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + extern void __libc_fini_array(void); + __libc_fini_array(); +#endif + + c_print_str(" ** TEST FAILED ** \n"); + +#ifndef SECURE_PROC_ENV +#ifdef SECURE_GCOV + secure_gcov_dump(); +#endif +#endif // SECURE_PROC_ENV + /* Halt simulation */ + while (1) { + c_print_char(3); + } +} +#else +#define TEST_PASSED() do { } while(0) +#define TEST_FAILED() do { } while(1) +#endif + +#ifdef __cplusplus +} +#endif diff --git a/ATM33xx-5/include/vectors.h b/ATM33xx-5/include/vectors.h new file mode 100644 index 0000000..48b9a77 --- /dev/null +++ b/ATM33xx-5/include/vectors.h @@ -0,0 +1,144 @@ +/** + ******************************************************************************* + * + * @file vectors.h + * + * @brief Vector Table Entries + * + * Copyright (C) Atmosic 2020-2024 + * + ******************************************************************************* + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/// Type for ARM machine vectors +typedef void (*isr_vector_t)(void); + +/// ARM machine vectors +#ifdef __ICCARM__ +#define __Vectors __vector_table +#endif +extern const isr_vector_t __Vectors[]; + +/* ARMv8MBL Processor Exceptions */ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManFault_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SecureFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +/* External Exceptions*/ +void NsRstWdog_Handler(void); +void NsIntWdog_Handler(void); +void S32kTimer_Handler(void); +void Timer0_Handler(void); +void Timer1_Handler(void); +void Reserved_Handler(void); +void DualTimer_Handler(void); +void MHU0_Handler(void); +void MHU1_Handler(void); +void MPCC_Handler(void); +void PPCC_Handler(void); +void MSC_Handler(void); +void BRD_Handler(void); + +/* EXP IRQ */ +void UARTRX0_Handler(void); +void UARTTX0_Handler(void); +void UARTRX1_Handler(void); +void UARTTX1_Handler(void); +void SPI1_Handler(void); +void SPI0_Handler(void); +void UARTOVF0_Handler(void); +void UARTOVF1_Handler(void); +void KSM_Handler(void); +void SLWTIMER_Handler(void); +void SPI2_Handler(void); +void PWM_Handler(void); +void SPI_RADIO_Handler(void); +void SPI_PMU_Handler(void); +void I2C0_Handler(void); +void I2C1_Handler(void); +void NVM_Handler(void); +void GADC_Handler(void); +void TRNG_Handler(void); +void RCOS_Handler(void); +void PDM0_Handler(void); +void PDM1_Handler(void); +void PDM2_Handler(void); +void PDM3_Handler(void); +void I2S_Handler(void); +void MDM_Handler(void); +void DMA0_Handler(void); +void DMA1_Handler(void); +void DMA2_Handler(void); +void DMA3_Handler(void); +void BLE_SW_Handler(void); +void BLE_FINETGT_Handler(void); +void BLE_TIMESTAMP_TGT1_Handler(void); +void BLE_TIMESTAMP_TGT2_Handler(void); +void BLE_TIMESTAMP_TGT3_Handler(void); +void BLE_CRYPT_Handler(void); +void BLE_SLP_Handler(void); +void BLE_HSLOT_Handler(void); +void BLE_FIFO_Handler(void); +void BLE_ERROR_Handler(void); +void BLE_HOP_Handler(void); +void BLE_ISOTS_0_Handler(void); +void BLE_ISOTS_1_Handler(void); +void BLE_ISOTS_2_Handler(void); +void BLE_ISOTS_3_Handler(void); +void BLE_ISOTS_4_Handler(void); +void BLE_ISOTS_5_Handler(void); +void BLE_ISOTS_6_Handler(void); +void BLE_ISOTS_7_Handler(void); +void PSEQ_Handler(void); +void PMU_Handler(void); +void PORT0_COMB_Handler(void); +void PORT1_COMB_Handler(void); +void PORT0_0_Handler(void); +void PORT0_1_Handler(void); +void PORT0_2_Handler(void); +void PORT0_3_Handler(void); +void PORT0_4_Handler(void); +void PORT0_5_Handler(void); +void PORT0_6_Handler(void); +void PORT0_7_Handler(void); +void PORT0_8_Handler(void); +void PORT0_9_Handler(void); +void PORT0_10_Handler(void); +void PORT0_11_Handler(void); +void PORT0_12_Handler(void); +void PORT0_13_Handler(void); +void PORT0_14_Handler(void); +void PORT0_15_Handler(void); +void PORT1_0_Handler(void); +void PORT1_1_Handler(void); +void PORT1_2_Handler(void); +void PORT1_3_Handler(void); +void PORT1_4_Handler(void); +void PORT1_5_Handler(void); +void PORT1_6_Handler(void); +void PORT1_7_Handler(void); +void PORT1_8_Handler(void); +void PORT1_9_Handler(void); +void PORT1_10_Handler(void); +void PORT1_11_Handler(void); +void PORT1_12_Handler(void); +void PORT1_13_Handler(void); +void PORT1_14_Handler(void); +void PORT1_15_Handler(void); + +#ifdef __cplusplus +} +#endif diff --git a/ATM33xx-5/lib/CMakeLists.txt b/ATM33xx-5/lib/CMakeLists.txt new file mode 100644 index 0000000..2fcf234 --- /dev/null +++ b/ATM33xx-5/lib/CMakeLists.txt @@ -0,0 +1,49 @@ +# Copyright (c) 2022-2024 Atmosic +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories( + atm_utils_c + atm_utils_math + atm_utils_reg +) + +if (CONFIG_AT_CMD) + zephyr_include_directories( + at_cmd + ) + + zephyr_sources( + at_cmd/at_cmd.c + at_cmd/at_cmd_pasr.c + ) +endif () + +if (CONFIG_ATM_AES_HW OR CONFIG_ATM_SHA2_HW OR CONFIG_ATM_SHA2_HW_BOOTUTIL) + zephyr_sources( + atm_utils_reg/atm_utils_reg.c + ) +endif () + +if (CONFIG_ATM_ASM) + add_subdirectory(atm_asm) +endif () + +if (CONFIG_ATM_UECC) + zephyr_include_directories( + ${ZEPHYR_BASE}/../modules/crypto/micro-ecc + ) +endif () + +if (CONFIG_TRUSTED_EXECUTION_SECURE) + zephyr_include_directories( + sec_service + ) + zephyr_sources( + sec_service/sec_service.c + ) +endif () + +if (CONFIG_ATM_VENDOR) + add_subdirectory(atm_vendor) +endif () diff --git a/ATM33xx-5/lib/Kconfig b/ATM33xx-5/lib/Kconfig new file mode 100644 index 0000000..a7fa9b1 --- /dev/null +++ b/ATM33xx-5/lib/Kconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2024 Atmosic +# +# SPDX-License-Identifier: Apache-2.0 + +config AT_CMD + bool "AT command support" + default n + +config ATM_ASM + bool "BLE state machine library" + default n + +config ATM_VENDOR + bool "ATM Vendor command library" + depends on BT_HCI_RAW && BT_HCI_RAW_H4 && BT_HCI_RAW_H4_ENABLE && BT_HCI_RAW_CMD_EXT + default n + +if ATM_ASM + +rsource "atm_asm/Kconfig" + +endif + +if ATM_VENDOR + +rsource "atm_vendor/Kconfig" + +endif diff --git a/ATM33xx-5/lib/at_cmd/at_cmd.c b/ATM33xx-5/lib/at_cmd/at_cmd.c new file mode 100644 index 0000000..594c775 --- /dev/null +++ b/ATM33xx-5/lib/at_cmd/at_cmd.c @@ -0,0 +1,522 @@ +/** + ******************************************************************************* + * + * @file at_cmd.c + * + * @brief Atmosic AT Command Core + * + * Copyright (C) Atmosic 2021-2024 + * + ******************************************************************************* + */ + +#include +#include +#include +#include +#include +#include "at_cmd.h" +#ifndef CONFIG_SOC_FAMILY_ATM +#include "atm_log.h" +ATM_LOG_LOCAL_SETTING("at_cmd", N); +#else +#include +#include +LOG_MODULE_REGISTER(at_cmd, LOG_LEVEL_INF); +#undef ATM_LOG +#define ATM_LOG(MSK, fmt, ...) LOG_INF(fmt, ##__VA_ARGS__) +#define ASSERT_ERR(arg) __ASSERT(arg, "%s", __func__) +#define ATM_LOG_FCYAN +#define ATM_LOG_FRED +#define ATM_LOG_FGREEN +#define ATM_LOG_DECOLOR +#define D_(d) #d +#define STR(d) D_(d) +#endif +#include "atm_utils_math.h" + +#ifndef AT_CMD_PREFIX_CTX +#define AT_CMD_PREFIX "\r\n" +#else // AT_CMD_PREFIX_CTX +#define AT_CMD_PREFIX STR(AT_CMD_PREFIX_CTX) +#endif // AT_CMD_PREFIX_CTX + +#ifndef AT_CMD_POSTFIX_CTX +#define AT_CMD_POSTFIX "\r\n" +#else // AT_CMD_POSTFIX_CTX +#define AT_CMD_POSTFIX STR(AT_CMD_POSTFIX_CTX) +#endif // AT_CMD_POSTFIX_CTX + +#ifndef AT_CMD_RESP_OK +#define AT_CMD_RESP_OK "OK" +#endif // AT_CMD_RESP_OK + +#ifndef AT_CMD_RESP_ERR +#define AT_CMD_RESP_ERR "ERR" +#endif // AT_CMD_RESP_ERR + +#ifndef AT_CMD_HDR +#define AT_CMD_HDR "AT+" +#endif // AT_CMD_HDR + +#define AT_CMD_HDR_LEN (sizeof(AT_CMD_HDR) - 1) + +#ifdef __ARMCC_VERSION +#define __at_cmd_start Load$$at_cmd$$Base +#define __at_cmd_end Load$$at_cmd$$Limit +#elif defined(__ICCARM__) +#define __at_cmd_start at_cmd$$Base +#define __at_cmd_end at_cmd$$Limit +#endif + +extern at_cmd_t const __at_cmd_start; +extern at_cmd_t const __at_cmd_end; +#define AT_CMD_START (&__at_cmd_start) +#define AT_CMD_END (&__at_cmd_end) + +static bool at_cmd_dbg; + +static at_cmd_alloc_ctx_t at_ctx[AT_CMD_XFER_MAX_NUM]; + +static void at_cmd_resp_data(at_cmd_ch_t ch, char const *data, uint16_t len) +{ + if (at_ctx[ch].resp) { + at_ctx[ch].resp(ch, data, len); + } +} + +static void +at_send_status(at_cmd_ch_t ch, at_cmd_err_t err, at_cmd_t const *cmd, ...) +{ + if (err == AT_CMD_ERR_NO_ERROR) { + at_cmd_resp_concat(ch, at_all, "%s", AT_CMD_RESP_OK); + } else if (err == AT_CMD_ERR_SPECIFIC_ERR) { + va_list args; + va_start(args, cmd); + uint16_t app_err = va_arg(args, int); + va_end(args); + at_cmd_resp_concat(ch, at_all, "+%s:%X", cmd->str, app_err); + at_cmd_resp_concat(ch, at_all, "%s", AT_CMD_RESP_ERR); + } else { + at_cmd_resp_concat(ch, at_all, "%s:%d", AT_CMD_RESP_ERR, err); + } +} + +static void at_cmd_check_args(at_cmd_param_t *param) +{ + param->err = AT_CMD_ERR_NO_ERROR; + param->args = at_pasr_param(); + uint16_t num = at_pasr_param_num_get(); + + ATM_LOG(V, "%s: param->argc (%d), num (%d)", __func__, param->argc, num); + + if (num != param->argc) { + // Apply correct parameter number to parser + param->argc = num; + param->err = AT_CMD_ERR_WRONG_ARGU_CNT; + return; + } + + for (int i = 0; i < num; i++) { + if (param->args[i]->status != AT_PASR_OK && + param->args[i]->status != AT_PASR_EMPTY_DATA) { + param->err = AT_CMD_ERR_WRONG_ARGU_TYPE_OR_RANGE; + ATM_LOG(V, "%s: [%d] status (%d)", __func__, i, + param->args[i]->status); + break; + } + } +} + +static char const * const at_cmd_dt_str[] = { + ATM_LOG_FCYAN STR(at_pasr_dt_i8) ATM_LOG_DECOLOR, + ATM_LOG_FCYAN STR(at_pasr_dt_u8) ATM_LOG_DECOLOR, + ATM_LOG_FCYAN STR(at_pasr_dt_i16) ATM_LOG_DECOLOR, + ATM_LOG_FCYAN STR(at_pasr_dt_u16) ATM_LOG_DECOLOR, + ATM_LOG_FCYAN STR(at_pasr_dt_i32) ATM_LOG_DECOLOR, + ATM_LOG_FCYAN STR(at_pasr_dt_u32) ATM_LOG_DECOLOR, + ATM_LOG_FCYAN STR(at_pasr_dt_array) ATM_LOG_DECOLOR, + ATM_LOG_FCYAN STR(at_pasr_dt_string) ATM_LOG_DECOLOR, + ATM_LOG_FRED STR(at_pasr_dt_unknow) ATM_LOG_DECOLOR, +}; + +static char const * const at_cmd_err_str[] = { + ATM_LOG_FGREEN STR(AT_PASR_OK) ATM_LOG_DECOLOR, + ATM_LOG_FRED STR(AT_PASR_RANGE_EXCEED) ATM_LOG_DECOLOR, + ATM_LOG_FRED STR(AT_PASR_WRONG_TYPE) ATM_LOG_DECOLOR, + ATM_LOG_FRED STR(AT_PASR_BUSY) ATM_LOG_DECOLOR, + ATM_LOG_FRED STR(AT_PASR_EMPTY_DATA) ATM_LOG_DECOLOR, + ATM_LOG_FRED STR(AT_PASR_NO_MEMORY) ATM_LOG_DECOLOR, + ATM_LOG_FRED STR(AT_PASR_INVALID_DATA) ATM_LOG_DECOLOR, + ATM_LOG_FRED STR(AT_PASR_MORE_DATA) ATM_LOG_DECOLOR +}; + +static void at_cmd_dbg_arg(at_pasr_tlv_t const *tlv) +{ + switch (tlv->type) { + case at_pasr_dt_i16: { + ATM_LOG(N, "%s : %d (%s)[%d~%d]", at_cmd_dt_str[tlv->type], + tlv->i16, at_cmd_err_str[tlv->status], tlv->i16min, tlv->i16max); + } break; + + case at_pasr_dt_u16: { + ATM_LOG(N, "%s : %u (%s)[%u~%u]", at_cmd_dt_str[tlv->type], + tlv->u16, at_cmd_err_str[tlv->status], tlv->u16min, tlv->u16max); + } break; + + case at_pasr_dt_u8: { + ATM_LOG(N, "%s : %u (%s)[%u~%u]", at_cmd_dt_str[tlv->type], + tlv->u8, at_cmd_err_str[tlv->status], tlv->u8min, tlv->u8max); + } break; + + case at_pasr_dt_i8: { + ATM_LOG(N, "%s : %d (%s)[%i~%i]", at_cmd_dt_str[tlv->type], + tlv->i8, at_cmd_err_str[tlv->status], tlv->i8min, tlv->i8max); + } break; + + case at_pasr_dt_array: { + ATM_LOG(N, "%s : 0x%02X...0x%02X (%s)", at_cmd_dt_str[tlv->type], + tlv->array[0], tlv->array[tlv->length - 1], + at_cmd_err_str[tlv->status]); + } break; + + case at_pasr_dt_i32: { + ATM_LOG(N, "%s : %" PRId32 " (%s)[%" PRId32 "~%" PRId32 "]", + at_cmd_dt_str[tlv->type], tlv->i32, + at_cmd_err_str[tlv->status], tlv->i32min, tlv->i32max); + } break; + + case at_pasr_dt_u32: { + ATM_LOG(N, "%s : %" PRIu32 " (%s)[%" PRIu32 "~%" PRIu32 "]", + at_cmd_dt_str[tlv->type], tlv->u32, + at_cmd_err_str[tlv->status], tlv->u32min, tlv->u32max); + } break; + + case at_pasr_dt_string: { + ATM_LOG(N, "%s : %.*s (%s)", at_cmd_dt_str[tlv->type], tlv->length, + tlv->string, at_cmd_err_str[tlv->status]); + } break; + + case at_pasr_dt_unknow: { + ATM_LOG(N, "%s : ", at_cmd_dt_str[tlv->type]); + } break; + + default: + break; + } +} + +static void at_call_handler(at_cmd_ch_t ch, at_cmd_type_t type, + at_cmd_t const *cmd, bool cmd_residue) +{ + at_cmd_param_t param = { + .type = type, + .argc = cmd->param_num, + .ch = ch, + .str = cmd->str, + }; + + if (type == at_cmd_type_exec) { + at_cmd_check_args(¶m); + + if (at_cmd_dbg) { + for (int i = 0; i < param.argc; i++) { + at_cmd_dbg_arg(param.args[i]); + } + } + + if (cmd_residue) { + param.err = AT_CMD_ERR_WRONG_ARGU_CNT; + } + cmd->hdlr(¶m); + at_send_status(param.ch, param.err, cmd, param.app_err); + } else { + param.err = AT_CMD_ERR_NO_ERROR; + cmd->hdlr(¶m); + } +} + +static at_cmd_t const *at_cmd_enum(at_cmd_t const *curr) +{ + if (!curr) { + return AT_CMD_START; + } + curr++; + + if (curr == AT_CMD_END) { + return NULL; + } + + return curr; +} + +static char const *at_cmd_xfer_uart(at_cmd_ch_t ch, void const *data, + uint16_t *len) +{ + uint16_t xlen = *len; + if (xlen <= AT_CMD_HDR_LEN) { + if ((xlen == AT_CMD_HDR_LEN - 1) && + !strncmp(data, AT_CMD_HDR, AT_CMD_HDR_LEN - 1)) { + *len = 0; + return data; + } + return NULL; + } + + *len -= AT_CMD_HDR_LEN; + return ((char const *)data + AT_CMD_HDR_LEN); +} + +static at_cmd_t const *at_cmd_content_get(uint16_t idx) +{ + if (idx >= at_cmd_count()) { + return NULL; + } + + return (AT_CMD_START + idx); +} + +static at_cmd_t const *at_cmd_is_available(char const *cmd_str) +{ + if (!*cmd_str) { + return NULL; + } + + char const *em = strchr(cmd_str, '='); + char const *qm = strchr(cmd_str, '?'); + size_t cmd_str_len; + if (!em && !qm) { + cmd_str_len = strlen(cmd_str); + } else { + char const *lm = (qm ? (em ? (qm > em ? em : qm) : qm) : em); + cmd_str_len = lm - cmd_str; + } + + if (!cmd_str_len) { + return NULL; + } + + uint16_t bottom = at_cmd_count(); + for (uint16_t upper = 0; upper < bottom; ) { + uint16_t middle = (upper + bottom) / 2; + at_cmd_t const *tcmd = at_cmd_content_get(middle); + if (!tcmd) { + ATM_LOG(E, "%s: Could not get AT command content!", __func__); + ASSERT_ERR(tcmd); + return false; + } + + size_t tlen = strlen(tcmd->str); + int result = strncmp(cmd_str, tcmd->str, ATM_MIN(cmd_str_len, tlen)); + + if (!result && (cmd_str_len == tlen)) { + return tcmd; + } else if (result ? (result > 0) : (cmd_str_len > tlen)) { + upper = middle + 1; + } else { + bottom = middle; + } + } + + return NULL; +} + +bool at_cmd_proc(at_cmd_ch_t ch, void const *data, uint16_t data_len) +{ + if (!data_len) { + return false; + } + + char const *astr = data; + uint16_t xlen = data_len; + if (at_ctx[ch].xfer) { + astr = at_ctx[ch].xfer(ch, data, &xlen); + if (!astr) { + at_send_status(ch, AT_CMD_ERR_NOT_SUPPORT, NULL); + return false; + } + + if (!xlen) { + at_send_status(ch, AT_CMD_ERR_NO_ERROR, NULL); + return true; + } + } + + ATM_LOG(V, "CMD (%s)", astr); + at_cmd_t const *cmd = at_cmd_is_available(astr); + if (!cmd) { + at_send_status(ch, AT_CMD_ERR_NOT_SUPPORT, NULL); + return false; + } + + size_t clen = strlen(cmd->str); + if (xlen == clen) { + at_send_status(ch, AT_CMD_ERR_NOT_SUPPORT, cmd); + return false; + } + + if ((xlen == clen + 1) && (astr[clen] == '?')) { + at_call_handler(ch, at_cmd_type_query, cmd, false); + at_send_status(ch, AT_CMD_ERR_NO_ERROR, cmd); + return true; + } + + if ((xlen == clen + 2) && (astr[clen] == '=') && (astr[clen + 1] == '?')) { + at_cmd_resp_concat(ch, at_all, "+%s:%s", cmd->str, cmd->test_str); + at_send_status(ch, AT_CMD_ERR_NO_ERROR, cmd); + return true; + } + + bool residue = (at_pasr_param_validate(astr + clen + 1, cmd->fmt) == + AT_PASR_MORE_DATA); + at_call_handler(ch, at_cmd_type_exec, cmd, residue); + at_pasr_clear(); + return true; +} + +at_cmd_ch_t at_cmd_alloc(at_cmd_alloc_ctx_t const *ctx) +{ + for (int ch = 0; ch < AT_CMD_XFER_MAX_NUM; ch++) { + if (!at_ctx[ch].resp) { + at_ctx[ch].xfer = (ctx->xfer != AT_CMD_DFT_XFER_UART) ? + ctx->xfer : at_cmd_xfer_uart; + at_ctx[ch].resp = ctx->resp; + return ch; + } + } + + ATM_LOG(E, "Please increase the AT_CMD_XFER_MAX_NUM in makefile to support " + "more transfer layer!"); + ASSERT_ERR(0); + return AT_CMD_INVALID_CH; +} + +static int at_cmd_prefix(char *buf, int offset, at_cmd_resp_flag_t flag) +{ + if (flag & at_prefix) { + strcpy(&buf[offset], AT_CMD_PREFIX); + offset += strlen(AT_CMD_PREFIX); + } + return offset; +} + +static int at_cmd_postfix(char *buf, int offset, at_cmd_resp_flag_t flag) +{ + if (flag & at_postfix) { + uint8_t plen = strlen(AT_CMD_POSTFIX); + if ((offset + plen) <= AT_CMD_RESP_LEN) { + strcpy(&buf[offset], AT_CMD_POSTFIX); + } + offset += plen; + } + + if (offset > AT_CMD_RESP_LEN) { + ATM_LOG(E, "Please increase AT_CMD_RESP_LEN in compile option!"); + offset = AT_CMD_RESP_LEN; + } + + return offset; +} + +void at_cmd_resp_array(at_cmd_ch_t ch, at_cmd_resp_flag_t flag, uint16_t len, + uint8_t const *dat) +{ + char buffer[AT_CMD_RESP_LEN + 1]; + int offset = 0; + + offset = at_cmd_prefix(buffer, offset, flag); + + for (uint16_t i = 0; i < len; i++) { + int elen = AT_CMD_RESP_LEN + 1 - offset; + int rlen = snprintf(&buffer[offset], elen, "%02X", dat[i]); + offset += rlen; + } + + offset = at_cmd_postfix(buffer, offset, flag); + + at_cmd_resp_data(ch, buffer, offset); +} + +void at_cmd_resp_concat(at_cmd_ch_t ch, at_cmd_resp_flag_t flag, + char const *fmt, ...) +{ + char buffer[AT_CMD_RESP_LEN + 1]; + int offset = 0; + + offset = at_cmd_prefix(buffer, offset, flag); + + if (flag & at_data) { + va_list args; + va_start(args, fmt); + int elen = AT_CMD_RESP_LEN + 1 - offset; + int rlen = vsnprintf(&buffer[offset], elen, fmt, args); + va_end(args); + + offset += rlen; + } + + offset = at_cmd_postfix(buffer, offset, flag); + + at_cmd_resp_data(ch, buffer, offset); +} + +void at_cmd_resp_raw(at_cmd_ch_t ch, void const *data, uint16_t len) +{ +#ifndef AUTO_TEST + if (at_ctx[ch].resp) { + at_ctx[ch].resp(ch, data, len); + } +#endif +} + +uint16_t at_cmd_count(void) +{ + return (AT_CMD_END - AT_CMD_START); +} + +/* + * AT COMMAND HANDLER (built-in command) + ******************************************************************************* + */ +#ifndef NO_AT_CMD_BUILTIN +#define CMD_NAME_LIST "LISTCMDS" +#define CMD_PARM_FMT_LIST "" +#define CMD_PARM_NUM_LIST 0 +#define CMD_PARM_DESC_LIST "" + +static void at_cmd_list_print(at_cmd_ch_t ch) +{ + ATM_LOG(V, "%s: %d AT commands available", __func__, at_cmd_count()); + for (at_cmd_t const *next = at_cmd_enum(NULL); next; + next = at_cmd_enum(next)) { + at_cmd_resp_concat(ch, at_prefix | at_data, "+%s:%s", next->str, + next->test_str); + } +} + +static void at_cmd_list_hdlr(at_cmd_param_t *param) +{ + if ((param->type == at_cmd_type_query) && !param->err) { + at_cmd_list_print(param->ch); + } +} + +AT_COMMAND(CMD_NAME_LIST, CMD_PARM_FMT_LIST, CMD_PARM_NUM_LIST, at_cmd_list_hdlr, + CMD_PARM_DESC_LIST); + +#define CMD_NAME_DBG "DEBUG" +#define CMD_PARM_FMT_DBG "B(0~1)" +#define CMD_PARM_NUM_DBG 1 +#define CMD_PARM_DESC_DBG "<1 or 0>" + +static void at_cmd_dbg_hdlr(at_cmd_param_t *param) +{ + if ((param->type == at_cmd_type_exec) && !param->err) { + at_cmd_dbg = AT_PASR_GET_PARAM(param, u8, 0); + } +} + +AT_COMMAND(CMD_NAME_DBG, CMD_PARM_FMT_DBG, CMD_PARM_NUM_DBG, at_cmd_dbg_hdlr, + CMD_PARM_DESC_DBG); +#endif // NO_AT_CMD_BUILTIN + diff --git a/ATM33xx-5/lib/at_cmd/at_cmd.h b/ATM33xx-5/lib/at_cmd/at_cmd.h new file mode 100644 index 0000000..707db1c --- /dev/null +++ b/ATM33xx-5/lib/at_cmd/at_cmd.h @@ -0,0 +1,262 @@ +/** + ******************************************************************************* + * + * @file at_cmd.h + * + * @brief Atmosic AT Command Core + * + * Copyright (C) Atmosic 2021-2024 + * + ******************************************************************************* + */ +#pragma once + +/** + ******************************************************************************* + * @defgroup ATM_BTFM_ATCORE AT command core + * @ingroup ATM_BTFM_PROC + * @brief ATM bluetooth framework AT command core + * + * This module contains the necessary procedure of AT command core. + * + * @{ + ******************************************************************************* + */ + +#include +#include "at_cmd_pasr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/// The length of AT command response +#ifndef AT_CMD_RESP_LEN +#define AT_CMD_RESP_LEN 256 +#endif // AT_CMD_RESP_LEN + +/// Invalid channel number +#define AT_CMD_INVALID_CH 0xFF + +/// The transfer layer support number +#ifndef AT_CMD_XFER_MAX_NUM +#define AT_CMD_XFER_MAX_NUM 3 +#endif // AT_CMD_XFER_MAX_NUM + +/// Command type +typedef enum { + /// Test command. "AT+=?" + at_cmd_type_test, + /// Read command. "AT+?" + at_cmd_type_query, + /// Exec command. "AT+=" + at_cmd_type_exec +} at_cmd_type_t; + +/// AT command error code +typedef enum { + /// No error + AT_CMD_ERR_NO_ERROR, + /// Command not support + AT_CMD_ERR_NOT_SUPPORT, + /// Wrong argument count + AT_CMD_ERR_WRONG_ARGU_CNT, + /// Wrong argument range + AT_CMD_ERR_WRONG_ARGU_RANGE, + /// Wrong argument type + AT_CMD_ERR_WRONG_ARGU_TYPE, + /// Wrong argument type or range + AT_CMD_ERR_WRONG_ARGU_TYPE_OR_RANGE, + /// Wrong argument content + AT_CMD_ERR_WRONG_ARGU_CONTENT, + /// Wrong execute type + AT_CMD_ERR_WRONG_EXECUTE_TYPE, + /// Specific error + AT_CMD_ERR_SPECIFIC_ERR = 0x80 +} at_cmd_err_t; + +/// AT command channel +typedef uint8_t at_cmd_ch_t; + +/// AT command parameter for handler +typedef struct { + /// AT command type + at_cmd_type_t type; + /// Error code + at_cmd_err_t err; + /// Argument count + uint16_t argc; + /// Argument content + at_pasr_tlv_t **args; + /// AT command data residue + bool data_residue; + /// Transport channel + at_cmd_ch_t ch; + /// Application error code + uint16_t app_err; + /// Command string + char const *str; +} at_cmd_param_t; + +/// The AT command handler +typedef void (*at_cmd_hdlr_t)(at_cmd_param_t *param); + +/// AT command definition +typedef struct { + /// Command string. Ex: BCSC for AT+BCSC= + char const *str; + /// AT command parameter format + char const *fmt; + /// Expect paramter numbers + uint16_t const param_num; + /// AT command handler + at_cmd_hdlr_t hdlr; + /// Test response string. If no, left NULL. + char const *test_str; +} at_cmd_t; + +typedef enum { + /// AT command response (prefix) + at_prefix = 1, + /// AT command response (data) + at_data = (1 << 1), + /// AT command response (postfix) + at_postfix = (1 << 2), + /// AT command response (prefix + data + postfix) + at_all = at_prefix | at_data | at_postfix +} at_cmd_resp_flag_t; + +/// The AT command response handler +typedef void (*at_cmd_resp_hdlr_t)(at_cmd_ch_t ch, void const *resp, + uint16_t len); + +/** + ******************************************************************************* + * @brief The transport layer handler + * @param[in] ch The channel got from @ref at_cmd_alloc + * @param[in, out] data Data string + * @param[in, out] len The length of data string + ******************************************************************************* + */ +typedef char const *(*at_cmd_xfer_hdlr_t)(at_cmd_ch_t ch, void const *data, + uint16_t *len); + +/// Built-in transport for UART +#define AT_CMD_DFT_XFER_UART ((at_cmd_xfer_hdlr_t)0x1) + +/// The context of AT command allocate +typedef struct { + /// Transport layer handler + at_cmd_xfer_hdlr_t xfer; + /// AT command response handler + at_cmd_resp_hdlr_t resp; +} at_cmd_alloc_ctx_t; + +/** + ******************************************************************************* + * @brief The link time module registration + * @param[in] cmd Command + * @param[in] fmt Command parameter format + * b(#~@) int8_t. (#: minimal number, @: maximal number) + * B(#~@) uint8_t. + * B(1~2), unsigned 8 bit number from 1 to 2. + * w(#~@) int16_t + * W(#~@) uint16_t. + * W(~5), unsigned 16 bit number from 0 to 5. + * d(#~@) int32_t. + * d(-3~10), signed 32 bit number from -3 to 10. + * d(~1000), signed 32 bit number from -2147483647 to 1000" + * D(#~@) uint32_t. + * D(30~), unsigned 32 bit number from 30 to 4294967295 + * A(#~@) byte array. + * A, byte array with any length + * A(3~), byte array with at least 3 bytes. + * A(2~5), byte array with length from 2 to 5 octets. + * A(6~6), byte array with 6 bytes exactly. + * S(#~@) UTF8 string. + * S, string with length 0 to 255 octets. + * S(3~), string with length from 3 to 255 octets. + * S(2~5), string with length from 2 to 5 octets. + * @param[in] num Number of command parameters + * @param[in] hdl Command handler + * @param[in] test Test command output + ******************************************************************************* + */ +#define AT_COMMAND(cmd, fmt, num, hdl, test) \ + AT_COMMAND_VAR(p##hdl, cmd, fmt, num, hdl, test) + +#define AT_COMMAND_VAR(var, cmd, fmt, num, hdl, test) \ + static const at_cmd_t __attribute__((section(".at_cmd." cmd), used)) \ + var = {cmd, fmt, num, hdl, test} +/** + ******************************************************************************* + * @brief Allocate and configure AT command context + * @param[in] ctx The context of AT command + * @return Channel number if successful; otherwise return AT_CMD_INVALID_CH + ******************************************************************************* + */ +__NONNULL_ALL +at_cmd_ch_t at_cmd_alloc(at_cmd_alloc_ctx_t const *ctx); + +/** + ******************************************************************************* + * @brief AT command process + * @param[in] ch The channel got from @ref at_cmd_alloc + * @param[in] data Input string w/o command header (i.e. AT+) + * @param[in] data_len The length of input string + * @return true if successful + ******************************************************************************* + */ +__NONNULL(2) +bool at_cmd_proc(at_cmd_ch_t ch, void const *data, uint16_t data_len); + +/** + ******************************************************************************* + * @brief Send response array + * @param[in] ch The channel got from @ref at_cmd_alloc + * @param[in] flag @ref at_cmd_resp_flag_t + * @param[in] len Length of dat. + * @param[in] dat Array. + ******************************************************************************* + */ +__NONNULL(4) +void at_cmd_resp_array(at_cmd_ch_t ch, at_cmd_resp_flag_t flag, uint16_t len, + uint8_t const *dat); + +/** + ******************************************************************************* + * @brief Generate response string + * @param[in] ch The channel got from @ref at_cmd_alloc + * @param[in] flag @ref at_cmd_resp_flag_t + * @param[in] fmt Response string + ******************************************************************************* + */ +__attribute__((format (printf, 3, 4))) +void at_cmd_resp_concat(at_cmd_ch_t ch, at_cmd_resp_flag_t flag, + char const *fmt, ...); + +/** + ******************************************************************************* + * @brief Apply response raw data + * @param[in] ch The channel got from @ref at_cmd_alloc + * @param[in] data Data + * @param[in] len Data length + ******************************************************************************* + */ +__NONNULL(2) +void at_cmd_resp_raw(at_cmd_ch_t ch, void const *data, uint16_t len); + +/** + ******************************************************************************* + * @brief Retrieve number of AT commands available + * @return How many AT commands available + ******************************************************************************* + */ +uint16_t at_cmd_count(void); + +#ifdef __cplusplus +} +#endif + +///@} ATM_BTFM_ATCORE + diff --git a/ATM33xx-5/lib/at_cmd/at_cmd_pasr.c b/ATM33xx-5/lib/at_cmd/at_cmd_pasr.c new file mode 100644 index 0000000..da8791c --- /dev/null +++ b/ATM33xx-5/lib/at_cmd/at_cmd_pasr.c @@ -0,0 +1,466 @@ +/** + ******************************************************************************* + * + * @file at_cmd_pasr.c + * + * @brief Atmosic AT Command Parser + * + * Copyright (C) Atmosic 2021-2024 + * + ******************************************************************************* + */ +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include "at_cmd_pasr.h" + +#ifndef CONFIG_SOC_FAMILY_ATM +#include "atm_log.h" +ATM_LOG_LOCAL_SETTING("at_pasr", N); +#else +#include +LOG_MODULE_REGISTER(at_pasr, LOG_LEVEL_INF); +#undef ATM_LOG +#define ATM_LOG(MSK, fmt, ...) LOG_INF(fmt, ##__VA_ARGS__) +#endif + +// the max parameters of AT command +#ifndef AT_PASR_PARAM_MAX_CNT +#define AT_PASR_PARAM_MAX_CNT 10 +#endif // AT_PASR_PARAM_MAX_CNT + +typedef struct at_pasr_dt_ctx_s { + char kword[at_pasr_dt_num]; + int32_t min[at_pasr_dt_num]; + uint32_t max[at_pasr_dt_num]; +} at_pasr_dt_ctx_t; + +static at_pasr_dt_ctx_t const dt_ctx = { + .kword = { + 'b', // int8_t + 'B', // uint8_t + 'w', // int16_t + 'W', // uint16_t + 'd', // int32_t + 'D', // uint32_t + 'A', // array + 'S', // string + }, + .min = { + SCHAR_MIN, + 0x0, + SHRT_MIN, + 0x0, + INT_MIN, + 0x0, + 0x0, + 0x0, + }, + .max = { + SCHAR_MAX, + UCHAR_MAX, + SHRT_MAX, + USHRT_MAX, + INT_MAX, + UINT_MAX, + 0xFF, + 0xFFF, + }, +}; + +static at_pasr_tlv_t *at_cmd_param[AT_PASR_PARAM_MAX_CNT]; +static int at_cmd_param_cnt; + +static char *at_pasr_input_num(char *str, char delimiter, uint32_t *val) +{ + char *ptr = str; + while (*ptr) { + if (*ptr == delimiter) { + break; + } + ptr++; + } + + if (*ptr) { + *ptr = 0; + *val = atoi(str); + return ptr + 1; + } + + return ptr; +} + +static void at_pasr_input_u8(char const *input, at_pasr_tlv_t **tlv) +{ + at_pasr_tlv_t *ptlv = *tlv; + char *end; + ptlv->u8 = strtoul(input, &end, 10); + if (!(*end) || (*end == ',')) { + ptlv->length = sizeof(uint8_t); + if ((ptlv->u8 >= ptlv->u8min) && (ptlv->u8 <= ptlv->u8max)) { + ptlv->status = AT_PASR_OK; + } else { + ptlv->status = AT_PASR_RANGE_EXCEED; + } + } else { + ptlv->u8 = 0; + ptlv->status = AT_PASR_WRONG_TYPE; + } +} + +static void at_pasr_input_i8(char const *input, at_pasr_tlv_t **tlv) +{ + at_pasr_tlv_t *ptlv = *tlv; + char *end; + ptlv->i8 = strtol(input, &end, 10); + if (!(*end) || (*end == ',')) { + ptlv->length = sizeof(int8_t); + if ((ptlv->i8 >= ptlv->i8min) && (ptlv->i8 <= ptlv->i8max)) { + ptlv->status = AT_PASR_OK; + } else { + ptlv->status = AT_PASR_RANGE_EXCEED; + } + } else { + ptlv->i8 = 0; + ptlv->status = AT_PASR_WRONG_TYPE; + } +} + +static void at_pasr_input_i16(char const *input, at_pasr_tlv_t **tlv) +{ + at_pasr_tlv_t *ptlv = *tlv; + char *end; + ptlv->i16 = strtol(input, &end, 10); + if (!(*end) || (*end == ',')) { + ptlv->length = sizeof(int16_t); + if ((ptlv->i16 >= ptlv->i16min) && (ptlv->i16 <= ptlv->i16max)) { + ptlv->status = AT_PASR_OK; + } else { + ptlv->status = AT_PASR_RANGE_EXCEED; + } + } else { + ptlv->i16 = 0; + ptlv->status = AT_PASR_WRONG_TYPE; + } +} + +static void at_pasr_input_u16(char const *input, at_pasr_tlv_t **tlv) +{ + at_pasr_tlv_t *ptlv = *tlv; + char *end; + ptlv->u16 = strtoul(input, &end, 10); + if (!(*end) || (*end == ',')) { + ptlv->length = sizeof(uint16_t); + if ((ptlv->u16 >= ptlv->u16min) && (ptlv->u16 <= ptlv->u16max)) { + ptlv->status = AT_PASR_OK; + } else { + ptlv->status = AT_PASR_RANGE_EXCEED; + } + } else { + ptlv->u16 = 0; + ptlv->status = AT_PASR_WRONG_TYPE; + } +} + +static void at_pasr_input_u32(char const *input, at_pasr_tlv_t **tlv) +{ + at_pasr_tlv_t *ptlv = *tlv; + char *end; + ptlv->u32 = strtoul(input, &end, 10); + if (!(*end) || (*end == ',')) { + ptlv->length = sizeof(uint32_t); + if ((ptlv->u32 >= ptlv->u32min) && (ptlv->u32 <= ptlv->u32max)) { + ptlv->status = AT_PASR_OK; + } else { + ptlv->status = AT_PASR_RANGE_EXCEED; + } + } else { + ptlv->u32 = 0; + ptlv->status = AT_PASR_WRONG_TYPE; + } +} + +static void at_pasr_input_i32(char const *input, at_pasr_tlv_t **tlv) +{ + at_pasr_tlv_t *ptlv = *tlv; + char *end; + ptlv->i32 = strtol(input, &end, 10); + if (!(*end) || (*end == ',')) { + ptlv->length = sizeof(int32_t); + if ((ptlv->i32 >= ptlv->i32min) && (ptlv->i32 <= ptlv->i32max)) { + ptlv->status = AT_PASR_OK; + } else { + ptlv->status = AT_PASR_RANGE_EXCEED; + } + } else { + ptlv->status = AT_PASR_WRONG_TYPE; + } +} + +#define SIZEOF_AT_PASR_TLV_T(__f, len) (offsetof(at_pasr_tlv_t, __f) + (len)) + +static void at_pasr_input_array(char const *input, at_pasr_tlv_t **tlv) +{ + char *next = strchr(input, ','); + if (!next) { + next = strchr(input, 0); + } + + uint16_t len = (next - input) / 2; + at_pasr_tlv_t *ptlv = realloc(*tlv, SIZEOF_AT_PASR_TLV_T(array, len)); + if (!ptlv) { + if (*tlv) { + free(*tlv); + *tlv = NULL; + } + + return; + } + *tlv = ptlv; + + char tmp[3] = {0, 0, 0}; + for (int i = 0; i < len; i++) { + memcpy(tmp, (input + i * 2), 2); + ptlv->array[i] = strtoul(tmp, NULL, 16); + } + + ptlv->length = len; + if ((len >= ptlv->arraymin) && (len <= ptlv->arraymax)) { + ptlv->status = AT_PASR_OK; + } else { + ptlv->status = AT_PASR_RANGE_EXCEED; + } + + if ((next - input) % 2) { + ptlv->status = AT_PASR_INVALID_DATA; + } +} + +static void at_pasr_input_string(char const *input, at_pasr_tlv_t **tlv) +{ + char *next = strchr(input, ','); + if (!next) { + next = strchr(input, 0); + } + + uint16_t len = next - input; + at_pasr_tlv_t *ptlv = realloc(*tlv, SIZEOF_AT_PASR_TLV_T(string, len)); + if (!ptlv) { + if (*tlv) { + free(*tlv); + *tlv = NULL; + } + + return; + } + *tlv = ptlv; + + memcpy(ptlv->string, input, len); + ptlv->length = len; + if ((len >= ptlv->stringmin) && (len <= ptlv->stringmax)) { + ptlv->status = AT_PASR_OK; + } else { + ptlv->status = AT_PASR_RANGE_EXCEED; + } +} + +static void at_pasr_input_wrong(char const *input, at_pasr_tlv_t **tlv) +{ + at_pasr_input_string(input, tlv); + (*tlv)->status = AT_PASR_WRONG_TYPE; +} + +typedef void (*at_pasr_input_ctx)(char const *input, at_pasr_tlv_t **tlv); + +static at_pasr_input_ctx const at_pasr_input_fn[] = { + at_pasr_input_i8, + at_pasr_input_u8, + at_pasr_input_i16, + at_pasr_input_u16, + at_pasr_input_i32, + at_pasr_input_u32, + at_pasr_input_array, + at_pasr_input_string, + at_pasr_input_wrong, +}; + +static bool at_pasr_input_walk(char const **in, at_pasr_tlv_t **tlv) +{ + char const *input = *in; + if (!input) { + return false; + } + + if (*input == ',' || !(*input)) { + (*tlv)->status = AT_PASR_EMPTY_DATA; + } else { + at_pasr_input_fn[(*tlv)->type](input, tlv); + } + + char *next = strchr(input, ','); + *in = next ? (next + 1) : 0; + + return true; +} + +static at_pasr_tlv_t *at_pasr_dt_identify(char *literal) +{ + uint8_t type = at_pasr_dt_unknow; + uint32_t max; + int32_t min; + for (int dt = at_pasr_dt_i8; dt < at_pasr_dt_num; dt++) { + if (literal[0] == dt_ctx.kword[dt]) { + type = dt; + min = dt_ctx.min[dt]; + max = dt_ctx.max[dt]; + break; + } + } + + switch (literal[1]) { + case '(': { + if (literal[2] == '~') { + char *str = at_pasr_input_num(literal + 3, ')', &max); + if (*str) { + type = at_pasr_dt_unknow; + } + } else { + char *str = at_pasr_input_num(literal + 2, '~', (uint32_t *)&min); + if (!str) { + type = at_pasr_dt_unknow; + } else if (str[0] != ')') { + str = at_pasr_input_num(str, ')', &max); + if (*str) { + type = at_pasr_dt_unknow; + } + } + } + } break; + + case 0: + default: + break; + } + +#define AT_PASR_PARAM_INIT(T, LEN) \ + case at_pasr_dt_##T: { \ + ptlv = calloc(1, SIZEOF_AT_PASR_TLV_T(T, LEN)); \ + ptlv->type = at_pasr_dt_##T; \ + ptlv->status = AT_PASR_EMPTY_DATA; \ + ptlv->T##min = min; \ + ptlv->T##max = max; \ + } break; + +#if defined(__GNUC__) && (__GNUC__ >= 10) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Warray-bounds" +#endif + at_pasr_tlv_t *ptlv = NULL; + switch (type) { + AT_PASR_PARAM_INIT(i8, sizeof(int8_t)); + AT_PASR_PARAM_INIT(u8, sizeof(uint8_t)); + AT_PASR_PARAM_INIT(i16, sizeof(int16_t)); + AT_PASR_PARAM_INIT(u16, sizeof(uint16_t)); + AT_PASR_PARAM_INIT(i32, sizeof(int32_t)); + AT_PASR_PARAM_INIT(u32, sizeof(uint32_t)); + AT_PASR_PARAM_INIT(array, 0); + AT_PASR_PARAM_INIT(string, 0); + + default: + ATM_LOG(E, "Unknown AT parser type!"); + break; + } +#if defined(__GNUC__) && (__GNUC__ >= 10) +#pragma GCC diagnostic pop +#endif + + if (!ptlv) { + ATM_LOG(E, "Not enough resource!"); + } + + return ptlv; +} + +static at_pasr_tlv_t *at_pasr_fmt_walk(char *format) +{ + static char *save_fmt; + char *fmt = !at_cmd_param_cnt ? format : NULL; + + char *token = strtok_r(fmt, ",", &save_fmt); + + if (!token) { + return NULL; + } + + return at_pasr_dt_identify(token); +} + +static void at_pasr_param_store(at_pasr_tlv_t *tlv) +{ + if (at_cmd_param_cnt < AT_PASR_PARAM_MAX_CNT) { + at_cmd_param[at_cmd_param_cnt++] = tlv; + } else { + free(tlv); + ATM_LOG(E, "Please increase AT_PASR_PARAM_MAX_CNT in compile option to " + "apply more parameters in AT command." ); + } +} + +static inline bool is_result_clear(void) +{ + return !at_cmd_param_cnt; +} + +at_pasr_err_t at_pasr_param_validate(char const *input, char const *format) +{ + if (!is_result_clear()) { + return AT_PASR_BUSY; + } + + char fmt[strlen(format) + 1]; + strcpy(fmt, format); + at_pasr_tlv_t *tlv; + while ((tlv = at_pasr_fmt_walk(fmt)) != NULL) { + if (!at_pasr_input_walk(&input, &tlv)) { + break; + } + at_pasr_param_store(tlv); + } + + return (input ? AT_PASR_MORE_DATA : AT_PASR_OK); +} + +at_pasr_tlv_t *at_pasr_param_get(uint16_t idx) +{ + if (idx >= at_cmd_param_cnt) { + return NULL; + } + + return at_cmd_param[idx]; +} + +uint16_t at_pasr_param_num_get(void) +{ + return at_cmd_param_cnt; +} + +at_pasr_tlv_t **at_pasr_param(void) +{ + ATM_LOG(V, "%s: at_cmd_param_cnt (%d)", __func__, at_cmd_param_cnt); + return at_cmd_param; +} + +void at_pasr_clear(void) +{ + for (int i = 0; i < at_cmd_param_cnt; i++) { + free(at_cmd_param[i]); + } + + at_cmd_param_cnt = 0; +} + diff --git a/ATM33xx-5/lib/at_cmd/at_cmd_pasr.h b/ATM33xx-5/lib/at_cmd/at_cmd_pasr.h new file mode 100644 index 0000000..08f9310 --- /dev/null +++ b/ATM33xx-5/lib/at_cmd/at_cmd_pasr.h @@ -0,0 +1,255 @@ +/** + ******************************************************************************* + * + * @file at_cmd_pasr.h + * + * @brief Atmosic AT Command Parser + * + * Copyright (C) Atmosic 2021 + * + ******************************************************************************* + */ +#pragma once + +/** + ******************************************************************************* + * @defgroup ATM_BTFM_ATPASR AT command parser + * @ingroup ATM_BTFM_PROC + * @brief ATM bluetooth framework AT command parser + * + * This module contains the necessary procedure AT command parser. + * + * @{ + ******************************************************************************* + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/// AT command parser error code +typedef enum { + /// OK + AT_PASR_OK, + /// Range exceed + AT_PASR_RANGE_EXCEED, + /// Wrong type + AT_PASR_WRONG_TYPE, + /// The parser not available + AT_PASR_BUSY, + /// No parameter + AT_PASR_EMPTY_DATA, + /// Insufficient resource + AT_PASR_NO_MEMORY, + /// Invalid parameter + AT_PASR_INVALID_DATA, + /// Extra parameter + AT_PASR_MORE_DATA, +} at_pasr_err_t; + +typedef enum { + /// int8_t (b) + at_pasr_dt_i8, + /// uint8_t (B) + at_pasr_dt_u8, + /// int16_t (w) + at_pasr_dt_i16, + /// uint16_t (W) + at_pasr_dt_u16, + /// int32_t (d) + at_pasr_dt_i32, + /// uint32_t (D) + at_pasr_dt_u32, + /// Array (A) + at_pasr_dt_array, + /// String (S) + at_pasr_dt_string, + /// Unknow + at_pasr_dt_unknow, + /// Data type number + at_pasr_dt_num = at_pasr_dt_unknow, +} at_pasr_dt_t; + +/** + ******************************************************************************* + * @brief Check parameter length + * @param[in] P Structure parameter (@ref at_pasr_tlv_t) + * @param[in] I Index + * @param[in] LEN Length + * @return true is enough size; otherwise return false + ******************************************************************************* + */ +#define AT_PASR_GET_PARAM_LEN_CHECK(P, I, LEN) ({ \ + (LEN == P->args[I]->length); \ +}) + +/** + ******************************************************************************* + * @brief Get parser parameter + * @param[in] P Structure parameter (@ref at_pasr_tlv_t) + * @param[in] T Type + * @param[in] I Index + * @return Parameter content + ******************************************************************************* + */ +#define AT_PASR_GET_PARAM(P, T, I) ({ \ + ASSERT_ERR(P->args[I]->type == at_pasr_dt_##T); \ + P->args[I]->T; \ +}) + +/** + ******************************************************************************* + * @brief Get parser parameter minimal value + * @param[in] P Structure parameter (@ref at_pasr_tlv_t) + * @param[in] T Type + * @param[in] I Index + * @return Parameter minimal value + ******************************************************************************* + */ +#define AT_PASR_GET_PARAM_MIN(P, T, I) ({ \ + P->args[I]->T##min; \ +}) + +/** + ******************************************************************************* + * @brief Get parser parameter maximal value + * @param[in] P Structure parameter (@ref at_pasr_tlv_t) + * @param[in] T Type + * @param[in] I Index + * @return Parameter maximal value + ******************************************************************************* + */ +#define AT_PASR_GET_PARAM_MAX(P, T, I) ({ \ + P->args[I]->T##max; \ +}) + +/** + ******************************************************************************* + * @brief Get parser parameter length + * @param[in] P Structure parameter (@ref at_pasr_tlv_t) + * @param[in] I Index + * @return Parameter length + ******************************************************************************* + */ +#define AT_PASR_GET_PARAM_LEN(P, I) ({ \ + P->args[I]->length; \ +}) + +typedef struct { + /// Data type + at_pasr_dt_t type; + /// Error code + at_pasr_err_t status; + /// The TLV length + uint16_t length; + + union { + /// uint32_t + struct { + uint32_t u32min; + uint32_t u32max; + uint32_t u32; + }; + + /// uint16_t + struct { + uint16_t u16min; + uint16_t u16max; + uint16_t u16; + }; + + /// uint8_t + struct { + uint8_t u8min; + uint8_t u8max; + uint8_t u8; + }; + + /// int32_t + struct { + int32_t i32min; + int32_t i32max; + int32_t i32; + }; + + /// int16_t + struct { + int16_t i16min; + int16_t i16max; + int16_t i16; + }; + + /// int8_t + struct { + int8_t i8min; + int8_t i8max; + int8_t i8; + }; + + /// array (uint8_t) + struct { + uint16_t arraymin; + uint16_t arraymax; + uint8_t array[]; + }; + + /// string (char) + struct { + uint16_t stringmin; + uint16_t stringmax; + char string[]; + }; + }; +} at_pasr_tlv_t; + +/** + ******************************************************************************* + * @brief Validate the AT command + * @param[in] input Input string + * @param[in] format The format of AT command + * @return Error code after parsing the input string + ******************************************************************************* + */ +__NONNULL(2) +at_pasr_err_t at_pasr_param_validate(char const *input, char const *format); + +/** + ******************************************************************************* + * @brief Get parameter of AT command after validating + * @return Parameter of AT command + ******************************************************************************* + */ +at_pasr_tlv_t **at_pasr_param(void); + +/** + ******************************************************************************* + * @brief Get parameter of AT command by index after validating + * @param[in] idx The parameter index of AT command + * @return Parameter of AT command + ******************************************************************************* + */ +at_pasr_tlv_t *at_pasr_param_get(uint16_t idx); + +/** + ******************************************************************************* + * @brief How manay parameters of AT command after validating + * @return Parameter of AT command + ******************************************************************************* + */ +uint16_t at_pasr_param_num_get(void); + +/** + ******************************************************************************* + * @brief Reset parser + ******************************************************************************* + */ +void at_pasr_clear(void); + +#ifdef __cplusplus +} +#endif + +/// @} ATM_BTFM_ATPASR diff --git a/ATM33xx-5/lib/atm_asm/CMakeLists.txt b/ATM33xx-5/lib/atm_asm/CMakeLists.txt new file mode 100644 index 0000000..dde2bcd --- /dev/null +++ b/ATM33xx-5/lib/atm_asm/CMakeLists.txt @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Atmosic +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories( + . +) + +zephyr_sources( + atm_asm.c +) + +zephyr_compile_definitions(CFG_S_MAX_ENTRY=CONFIG_ATM_ASM_MAX_ENTRY) diff --git a/ATM33xx-5/lib/atm_asm/Kconfig b/ATM33xx-5/lib/atm_asm/Kconfig new file mode 100644 index 0000000..32ccae0 --- /dev/null +++ b/ATM33xx-5/lib/atm_asm/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Atmosic +# +# SPDX-License-Identifier: Apache-2.0 + +config ATM_ASM_MAX_ENTRY + int "State Machine Max Entries." + default 1 diff --git a/ATM33xx-5/lib/atm_asm/atm_asm.c b/ATM33xx-5/lib/atm_asm/atm_asm.c new file mode 100644 index 0000000..f372928 --- /dev/null +++ b/ATM33xx-5/lib/atm_asm/atm_asm.c @@ -0,0 +1,184 @@ +/** + ******************************************************************************* + * + * @file atm_asm.c + * + * @brief Atmosic application state machine + * + * Copyright (C) Atmosic 2020-2024 + * + ******************************************************************************* + */ + +#ifdef CONFIG_SOC_FAMILY_ATM +#include +#include +#endif +#include "arch.h" +#include "atm_asm.h" + +/* + * DEFINES + * ***************************************************************************** + */ +#ifndef CFG_S_MAX_ENTRY +/// Number of state machine table instances +#define CFG_S_MAX_ENTRY 1 +#endif + +#ifdef CFG_ASM_BITWISE +#define ISONEHOT(x) (x && !(x & (x - 1))) +#endif + +/* + * VARIABLE + * ***************************************************************************** + */ +static struct { + state_entry const *table; + uint8_t table_cnt; + ASM_O operation; + ASM_S state; + ASM_S pre_state; + void (*cb_state_change)(ASM_S last_s, ASM_O op, ASM_S next_s); + void (*cb_state_changed)(ASM_S last_s, ASM_O op, ASM_S next_s); +#ifdef CONFIG_SOC_FAMILY_ATM + struct k_mutex mutex; +#endif +} atm_state[CFG_S_MAX_ENTRY]; + +/* + * GLOBAL + * ***************************************************************************** + */ +void atm_asm_init_table( + uint8_t idx, const state_entry s_tbl[], uint8_t s_tbl_size) +{ + ASSERT_INFO(idx < CFG_S_MAX_ENTRY, CFG_S_MAX_ENTRY, idx); + atm_state[idx].table = s_tbl; + atm_state[idx].table_cnt = s_tbl_size; +#ifdef CONFIG_SOC_FAMILY_ATM + k_mutex_init(&atm_state[idx].mutex); +#endif +} + +static void atm_asm_set_state(uint8_t idx, ASM_S state, ASM_O op_code, + state_handler handler) +{ +#ifdef CFG_ASM_BITWISE + ASSERT_ERR(ISONEHOT(state) && ISONEHOT(op_code)); +#endif + ASSERT_INFO(idx < CFG_S_MAX_ENTRY, CFG_S_MAX_ENTRY, idx); + +#ifdef CONFIG_SOC_FAMILY_ATM + k_mutex_lock(&atm_state[idx].mutex, K_FOREVER); +#endif + if (atm_state[idx].cb_state_change) { + atm_state[idx].cb_state_change(atm_state[idx].state, op_code, state); + } + + atm_state[idx].pre_state = atm_state[idx].state; + atm_state[idx].state = state; + atm_state[idx].operation = op_code; + + if (handler) { + handler(); + } + + if (atm_state[idx].cb_state_changed) { + atm_state[idx].cb_state_changed(atm_state[idx].pre_state, op_code, + state); + } + +#ifdef CONFIG_SOC_FAMILY_ATM + k_mutex_unlock(&atm_state[idx].mutex); +#endif +} + +void atm_asm_set_state_op(uint8_t idx, ASM_S state, ASM_O op_code) +{ + atm_asm_set_state(idx, state, op_code, NULL); +} + +ASM_S atm_asm_get_current_state(uint8_t idx) +{ + ASSERT_INFO(idx < CFG_S_MAX_ENTRY, CFG_S_MAX_ENTRY, idx); +#ifdef CONFIG_SOC_FAMILY_ATM + k_mutex_lock(&atm_state[idx].mutex, K_FOREVER); +#endif + ASM_S state = atm_state[idx].state; +#ifdef CONFIG_SOC_FAMILY_ATM + k_mutex_unlock(&atm_state[idx].mutex); +#endif + return state; +} + +void atm_asm_set_current_state(uint8_t idx, ASM_S state) +{ + atm_asm_set_state(idx, state, atm_state[idx].operation, NULL); +} + +atm_asm_trans atm_asm_get_latest_transition(uint8_t idx) +{ +#ifdef CONFIG_SOC_FAMILY_ATM + k_mutex_lock(&atm_state[idx].mutex, K_FOREVER); +#endif + atm_asm_trans trans = {atm_state[idx].pre_state, atm_state[idx].operation, + atm_state[idx].state}; +#ifdef CONFIG_SOC_FAMILY_ATM + k_mutex_unlock(&atm_state[idx].mutex); +#endif + return trans; +} + +void atm_asm_move(uint8_t idx, ASM_O next_op) +{ +#ifdef CFG_ASM_BITWISE + ASSERT_ERR(ISONEHOT(next_op)); +#endif + ASSERT_INFO(idx < CFG_S_MAX_ENTRY, CFG_S_MAX_ENTRY, idx); + state_entry const *s_tbl = atm_state[idx].table; + +#ifdef CONFIG_SOC_FAMILY_ATM + k_mutex_lock(&atm_state[idx].mutex, K_FOREVER); +#endif + + for (uint8_t i = 0; i < atm_state[idx].table_cnt; i++) { +#ifdef CFG_ASM_BITWISE + if ((atm_state[idx].state & s_tbl[i].state) && + (next_op & s_tbl[i].operation)) { +#else + if ((atm_state[idx].state == s_tbl[i].state) && + (next_op == s_tbl[i].operation)) { +#endif + atm_asm_set_state_op(idx, s_tbl[i].next_state, next_op); + if (s_tbl[i].handler) { + s_tbl[i].handler(); + } +#ifdef CONFIG_SOC_FAMILY_ATM + k_mutex_unlock(&atm_state[idx].mutex); +#endif + return; + } + } +#ifdef CONFIG_SOC_FAMILY_ATM + __ASSERT(0, "idx:%d state:%d next_op:%d can't find next state", idx, + atm_state[idx].state, next_op); +#else + ASSERT_INFO(0, atm_state[idx].state, next_op); +#endif +} + +void atm_asm_reg_state_change_cb( + uint8_t idx, void (*cb)(ASM_S last_s, ASM_O op, ASM_S next_s)) +{ + ASSERT_INFO(idx < CFG_S_MAX_ENTRY, CFG_S_MAX_ENTRY, idx); + atm_state[idx].cb_state_change = cb; +} + +void atm_asm_reg_state_changed_cb(uint8_t idx, + void (*cb)(ASM_S last_s, ASM_O op, ASM_S next_s)) +{ + ASSERT_INFO(idx < CFG_S_MAX_ENTRY, CFG_S_MAX_ENTRY, idx); + atm_state[idx].cb_state_changed = cb; +} diff --git a/ATM33xx-5/lib/atm_asm/atm_asm.h b/ATM33xx-5/lib/atm_asm/atm_asm.h new file mode 100644 index 0000000..f9177f4 --- /dev/null +++ b/ATM33xx-5/lib/atm_asm/atm_asm.h @@ -0,0 +1,163 @@ +/** + ******************************************************************************* + * + * @file atm_asm.h + * + * @brief Atmosic application state machine + * + * Copyright (C) Atmosic 2020-2023 + * + ******************************************************************************* + */ + +#pragma once + +/** + ******************************************************************************* + * @defgroup ATM_BTFM_PASM Application state machine + * @ingroup ATM_BTFM_PROC + * @brief ATM bluetooth framework state machine tool + * + * This module contains the necessary function of state machine tool + * + * @{ + ******************************************************************************* + */ + +#include +#include "atm_utils_math.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * MACROS + ******************************************************************************* + */ +#define S_OP(s, op) (s), (op) + +/* + * TYPEDEFINE + ******************************************************************************* + */ + +#ifdef CFG_ASM_BITWISE +typedef uint32_t ASM_T; +#else +typedef uint8_t ASM_T; +#endif +typedef ASM_T ASM_S; +typedef ASM_T ASM_O; + +/** + * @brief Simple handler + */ +typedef void (*state_handler)(void); + +typedef struct { + /// state code + ASM_S state; + /// operation code + ASM_O operation; + /// next state + ASM_S next_state; + /// handler function for state_operation + state_handler handler; +} state_entry; +typedef struct { + /// state code + ASM_S pre_state; + /// operation code + ASM_O operation; + /// next state + ASM_S cur_state; +} atm_asm_trans; + +/* + * GLOBAL + ******************************************************************************* + */ +/** + * @brief Insert application state machine table into framework + * @param[in] idx instance index + * @param[in] s_tbl state machine table + * @param[in] s_tbl_size size of state machine table + */ +void atm_asm_init_table(uint8_t idx, const state_entry s_tbl[], + uint8_t s_tbl_size); + +/** + * @brief Set state + * @param[in] idx instance index + * @param[in] state state value + */ +void atm_asm_set_current_state(uint8_t idx, ASM_S state); + +/** + * @brief Get current state + * @param[in] idx instance index + * @return current state + */ +ASM_S atm_asm_get_current_state(uint8_t idx); + +/** + * @brief Update current state and operation code + * @param[in] idx instance index + * @param[in] state state value + * @param[in] op_code operation code + */ +void atm_asm_set_state_op(uint8_t idx, ASM_S state, ASM_O op_code); + +/** + * @brief Get lastest transition + * @param[in] idx instance index + */ +atm_asm_trans atm_asm_get_latest_transition(uint8_t idx); + +/** + * @brief Move to handler function by operation code then update state + * @param[in] idx instance index + * @param[in] next_op move state to this + */ +void atm_asm_move(uint8_t idx, ASM_O next_op); + +/** + * @brief Set callback function to be informed before state machine transitions. + * @param[in] idx instance index + * @param[in] cb callback function + */ +void atm_asm_reg_state_change_cb(uint8_t idx, + void (*cb)(ASM_S last_s, ASM_O op, ASM_S next_s)); + +/** + * @brief Set callback function to be informed after state machine transitions. + * @param[in] idx instance index + * @param[in] cb callback function + */ +void atm_asm_reg_state_changed_cb(uint8_t idx, + void (*cb)(ASM_S last_s, ASM_O op, ASM_S next_s)); + +/** + ******************************************************************************* + * @brief Get ordinal number of ASM_O or ASM_S. + * @param code Specific state code or operation code. + * @return Ordinal number of this state. + ******************************************************************************* + */ +static inline uint8_t atm_asm_ordinal(ASM_T code) +{ +#ifdef CFG_ASM_BITWISE + return atm_ctz(code); +#else + return code; +#endif +} + +#ifdef __cplusplus +} +#endif + +///@} ATM_BTFM_PASM + + diff --git a/ATM33xx-5/lib/atm_utils_c/atm_utils_c.h b/ATM33xx-5/lib/atm_utils_c/atm_utils_c.h new file mode 100644 index 0000000..2a4873a --- /dev/null +++ b/ATM33xx-5/lib/atm_utils_c/atm_utils_c.h @@ -0,0 +1,247 @@ +/** + ******************************************************************************* + * + * @file atm_utils_c.h + * + * @brief ATM common utility functions + * + * Copyright (C) Atmosic 2022 + * + ******************************************************************************* + */ +#pragma once + +#include "arch.h" + +/** + * @defgroup ATM_UTILS_C Atmosic common utilities related to C + * @ingroup ATM_UTILS + * @brief ATM common utility C functions + * + * Common utility inline functions and macros + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ARRAY_LEN +// put the array name in the index operator intentionally +// this way the issue caused by operator overloading in C++ will be noticed +#define ARRAY_LEN(x) (sizeof(x) / sizeof(0[x])) +#endif + +#ifndef CONTAINER_OF +#define CONTAINER_OF(ptr, type, member) \ + ((type *)((char *)(ptr) - offsetof(type, member))) +#endif + +/** + * @brief Read a 16-bit little-endian value from any address in memory space. + * @param[in] ptr The address of the first byte of the value. + * @return The 16-bit value. + */ +__NONNULL_ALL +__INLINE uint16_t atm_get_le16(void const *ptr) +{ + struct { + uint16_t val; + } __PACKED const *pu16 = ptr; +#if (CPU_LE) + return pu16->val; +#else + return __REV16(pu16->val); +#endif +} + +/** + * @brief Read a 24-bit little-endian value from any address in memory space. + * @param[in] ptr The address of the first byte of the value. + * @return The 24-bit value. + */ +__NONNULL_ALL +__INLINE uint32_t atm_get_le24(void const *ptr) +{ + uint8_t const volatile *p = ptr; + return p[0] | (p[1] << 8) | (p[2] << 16); +} + +/** + * @brief Read a 32-bit little-endian value from any address in memory space. + * @param[in] ptr The address of the first byte of the value. + * @return The 32-bit value. + */ +__NONNULL_ALL +__INLINE uint32_t atm_get_le32(void const *ptr) +{ + struct { + uint32_t val; + } __PACKED const *pu32 = ptr; +#if (CPU_LE) + return pu32->val; +#else + return __REV(pu32->val); +#endif +} + +/** + * @brief Read a 16-bit big-endian value from any address in memory space. + * @param[in] ptr The address of the first byte of the value. + * @return The 16-bit value. + */ +__NONNULL_ALL +__INLINE uint16_t atm_get_be16(void const *ptr) +{ + struct { + uint16_t val; + } __PACKED const *pu16 = ptr; +#if (!CPU_LE) + return pu16->val; +#else + return __REV16(pu16->val); +#endif +} + +/** + * @brief Read a 24-bit big-endian value from any address in memory space. + * @param[in] ptr The address of the first byte of the value. + * @return The 24-bit value. + */ +__NONNULL_ALL +__INLINE uint32_t atm_get_be24(void const *ptr) +{ + uint8_t const volatile *p = ptr; + return p[2] | (p[1] << 8) | (p[0] << 16); +} + +/** + * @brief Read a 32-bit big-endian value from any address in memory space. + * @param[in] ptr The address of the first byte of the value. + * @return The 32-bit value. + */ +__NONNULL_ALL +__INLINE uint32_t atm_get_be32(void const *ptr) +{ + struct { + uint32_t val; + } __PACKED const *pu32 = ptr; +#if (!CPU_LE) + return pu32->val; +#else + return __REV(pu32->val); +#endif +} + +/** + * @brief Write a 16-bit value to any address in memory space. The value will be + * written in little-endian order. + * @param[in] ptr The address of the first byte to write the value. + * @param[in] value The 16-bit value to be written + */ +__NONNULL(1) +__INLINE void atm_set_le16(void *ptr, uint16_t value) +{ + struct { + uint16_t val; + } __PACKED *pu16 = ptr; +#if (CPU_LE) + pu16->val = value; +#else + pu16->val = __REV16(value); +#endif +} + +/** + * @brief Write a 24-bit value to any address in memory space. The value will be + * written in little-endian order. + * @param[in] ptr The address of the first byte to write the value. + * @param[in] value The 24-bit value to be written + */ +__NONNULL(1) +__INLINE void atm_set_le24(void *ptr, uint32_t value) +{ + uint8_t volatile *p = ptr; + p[0] = value; + p[1] = value >> 8; + p[2] = value >> 16; +} + +/** + * @brief Write a 32-bit value to any address in memory space. The value will be + * written in little-endian order. + * @param[in] ptr The address of the first byte to write the value. + * @param[in] value The 32-bit value to be written + */ +__NONNULL(1) +__INLINE void atm_set_le32(void *ptr, uint32_t value) +{ + struct { + uint32_t val; + } __PACKED *pu32 = ptr; +#if (CPU_LE) + pu32->val = value; +#else + pu32->val = __REV(value); +#endif +} + +/** + * @brief Write a 16-bit value to any address in memory space. The value will be + * written in big-endian order. + * @param[in] ptr The address of the first byte to write the value. + * @param[in] value The 16-bit value to be written + */ +__NONNULL(1) +__INLINE void atm_set_be16(void *ptr, uint16_t value) +{ + struct { + uint16_t val; + } __PACKED *pu16 = ptr; +#if (!CPU_LE) + pu16->val = value; +#else + pu16->val = __REV16(value); +#endif +} + +/** + * @brief Write a 24-bit value to any address in memory space. The value will be + * written in big-endian order. + * @param[in] ptr The address of the first byte to write the value. + * @param[in] value The 24-bit value to be written + */ +__NONNULL(1) +__INLINE void atm_set_be24(void *ptr, uint32_t value) +{ + uint8_t volatile *p = ptr; + p[2] = value; + p[1] = value >> 8; + p[0] = value >> 16; +} + +/** + * @brief Write a 32-bit value to any address in memory space. The value will be + * written in big-endian order. + * @param[in] ptr The address of the first byte to write the value. + * @param[in] value The 32-bit value to be written + */ +__NONNULL(1) +__INLINE void atm_set_be32(void *ptr, uint32_t value) +{ + struct { + uint32_t val; + } __PACKED *pu32 = ptr; +#if (!CPU_LE) + pu32->val = value; +#else + pu32->val = __REV(value); +#endif +} + +#ifdef __cplusplus +} +#endif + +/// @} ATM_UTILS diff --git a/ATM33xx-5/lib/atm_utils_math/atm_utils_math.h b/ATM33xx-5/lib/atm_utils_math/atm_utils_math.h new file mode 100644 index 0000000..1fa3df1 --- /dev/null +++ b/ATM33xx-5/lib/atm_utils_math/atm_utils_math.h @@ -0,0 +1,171 @@ +/** + ******************************************************************************* + * + * @file atm_utils_math.h + * + * @brief ATM common math functions + * + * Copyright (C) Atmosic 2022-2024 + * + ******************************************************************************* + */ + +#pragma once + +/** + * @defgroup ATM_UTILS_MATH Atmosic common math + * @ingroup ATM_UTILS + * @brief ATM common math macros and functions + * + * @{ + * + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "compiler.h" + +/// Macro to return a value with a single bit set +#define ATM_BIT(x) (1UL << (x)) + +/// Macro to return the next highest 4-byte aligned value +#define ATM_ALIGN_4_BYTES(x) (((uint32_t)(x) + 0x03) & ~0x03) + +/// Macro to return the smallest integer value greater than or equal to (x/y) +#define ATM_CEIL_VAL(x, y) (((x) + ((y)-1)) / (y)) + +/// Macro to return the nearest integer value of (x/y) +#define ATM_ROUND_VAL(x, y) (((x) + ((y) >> 1)) / (y)) + +/// Macro to return the minimum between two values +#define ATM_MIN(x, y) (((x) < (y)) ? (x) : (y)) + +/// Macro to return the maximum between two values +#define ATM_MAX(x, y) (((x) > (y)) ? (x) : (y)) + +/// Macro to return the absolute value +#define ATM_ABS(x) (((x) < 0) ? -(x) : (x)) + +#if (!defined(CONFIG_SOC_FAMILY_ATM) || defined(CONFIG_MINIMAL_LIBC_RAND)) +#define ATM_UTIL_MATH_LIBC_HAS_RAND +#endif // CONFIG_SOC_FAMILY_ATM + +#ifdef ATM_UTIL_MATH_LIBC_HAS_RAND +/** + * @brief Function to get an 8 bit random number. + * + * @note Known PRNG functions suffer from extreme + * predictability in the lower bits. Shift off to + * get better rand byte + */ +__STATIC_INLINE uint8_t atm_rand_byte(void) +{ + return ((rand() >> 16) & 0xFF); +} + +/** + * @brief Function to get an 16 bit random number. + * + * @note Known PRNG functions suffer from extreme + * predictability in the lower bits. Shift off to + * get better rand byte + */ +__STATIC_INLINE uint16_t atm_rand_hword(void) +{ + return (rand() >> 16); +} + +/** + * @brief Function to get an 32 bit random number. + */ +__STATIC_INLINE uint32_t atm_rand_word(void) +{ + return rand(); +} +#endif // ATM_UTIL_MATH_LIBC_HAS_RAND + +/** + * @brief Count leading zeros + * + * @param[in] val The input value to count + * @return Number of leading zeros + */ +__INLINE uint32_t atm_clz(uint32_t val) +{ +#if defined(__ICCARM__) + return __CLZ(val); +#elif defined(__arm__) + return __builtin_clz(val); +#elif defined(__GNUC__) + if (!val) { + return 32; + } + return __builtin_clz(val); +#else + if (!val) { + return 32; + } + uint32_t i = 0; + while (!(val & (1 << (31 - i)))) { + i++; + } + return i; +#endif +} + +/** + * @brief Count trailing zeros + * + * @param[in] val The input value to count + * @return Number of trailing zeros + */ +__INLINE uint32_t atm_ctz(uint32_t val) +{ +#if defined(__arm__) && defined(CFG_ROM) + return __builtin_ctz(val); +#elif defined(__GNUC__) + if (!val) { + return 32; + } + return __builtin_ctz(val); +#else + if (!val) { + return 32; + } + uint32_t count = 0; + while (!(val & 1)) { + count++; + val >>= 1; + } + return count; +#endif +} + +/** + * @brief Returns the number of one’s(set bits) in a 32-bit value + * + * @param[in] val The input value to count + * @return The number of one’s(set bits) + */ +__INLINE int atm_popcount(uint32_t val) +{ +#ifdef __GNUC__ + return __builtin_popcount(val); +#else + int i = 0; + for (; val; val &= val - 1) { + i++; + } + return i; +#endif +} + +#ifdef __cplusplus +} +#endif + +/// @} diff --git a/ATM33xx-5/lib/atm_utils_reg/atm_utils_reg.c b/ATM33xx-5/lib/atm_utils_reg/atm_utils_reg.c new file mode 100644 index 0000000..5324e3b --- /dev/null +++ b/ATM33xx-5/lib/atm_utils_reg/atm_utils_reg.c @@ -0,0 +1,97 @@ +/** + ******************************************************************************* + * + * @file atm_utils_reg.c + * + * @brief ATM utility functions for register access + * + * Copyright (C) Atmosic 2022 + * + ******************************************************************************* + */ + +#include +#include "atm_utils_reg.h" + +#ifdef __ARM_FEATURE_UNALIGNED +#define UNALIGNED_OK 1 +#else +#define UNALIGNED_OK 0 +#endif + +void atm_reg_write_multiple(uint32_t volatile *reg, uint8_t const *data, + size_t const num_bytes) +{ + size_t i = 0; + size_t num_words = num_bytes / sizeof(uint32_t); + if (UNALIGNED_OK || (uintptr_t)data % sizeof(uint32_t) == 0) { + // we can transfer (at least in part) with word writes + for (; i < num_words; i++) { + reg[i] = ((uint32_t __UNALIGNED const *)data)[i]; + } + } else { + // transfer full misaligned words + for (; i < num_words; i++) { + reg[i] = ((misaligned_uint32_t const *)data)[i].d; + } + } + + size_t trailing_bytes = i * sizeof(uint32_t); + union { + uint32_t u32; + uint8_t u8[sizeof(uint32_t)]; + } aligned_int = {.u32 = 0}; + switch (num_bytes - trailing_bytes) { + // transfer trailing bytes + case 3: + aligned_int.u8[2] = data[trailing_bytes + 2]; + /* FALLTHRU */ + case 2: + aligned_int.u8[1] = data[trailing_bytes + 1]; + /* FALLTHRU */ + case 1: + aligned_int.u8[0] = data[trailing_bytes]; + reg[i] = aligned_int.u32; + /* FALLTHRU */ + default: + break; + } +} + +void atm_reg_read_multiple(uint32_t volatile const *reg, uint8_t *data, + size_t const num_bytes) +{ + size_t i = 0; + size_t num_words = num_bytes / sizeof(uint32_t); + if (UNALIGNED_OK || (uintptr_t)data % sizeof(uint32_t) == 0) { + // we can transfer (at least in part) with word writes + for (; i < num_words; i++) { + ((uint32_t __UNALIGNED *)data)[i] = reg[i]; + } + } else { + // transfer full misaligned words + for (; i < num_words; i++) { + ((misaligned_uint32_t *)data)[i].d = reg[i]; + } + } + + size_t trailing_bytes = i * sizeof(uint32_t); + union { + uint32_t u32; + uint8_t u8[sizeof(uint32_t)]; + } aligned_int = {.u32 = reg[i]}; + switch (num_bytes - trailing_bytes) { + // transfer trailing bytes + case 3: + data[trailing_bytes + 2] = aligned_int.u8[2]; + /* FALLTHRU */ + case 2: + data[trailing_bytes + 1] = aligned_int.u8[1]; + /* FALLTHRU */ + case 1: + data[trailing_bytes] = aligned_int.u8[0]; + /* FALLTHRU */ + default: + break; + } +} \ No newline at end of file diff --git a/ATM33xx-5/lib/atm_utils_reg/atm_utils_reg.h b/ATM33xx-5/lib/atm_utils_reg/atm_utils_reg.h new file mode 100644 index 0000000..d3a188b --- /dev/null +++ b/ATM33xx-5/lib/atm_utils_reg/atm_utils_reg.h @@ -0,0 +1,92 @@ +/** + ******************************************************************************* + * + * @file atm_utils_reg.h + * + * @brief ATM utility functions for register access + * + * Copyright (C) Atmosic 2022 + * + ******************************************************************************* + */ +#pragma once + +#include +#include +#include "arch.h" + +/** + * @defgroup ATM_UTILS_REG ATM utility functions for register access + * @ingroup ATM_UTILS + * @brief ATM utility functions for register access + * + * Utility inline functions for register access + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint32_t d; +} __PACKED misaligned_uint32_t; + +/** + * @brief Write a register from a potentially unaligned source + * @param[out] reg The address of the register + * @param[in] data The address of the data + */ +__NONNULL_ALL +__INLINE +void atm_reg_write(uint32_t volatile *reg, void const *data) +{ + *reg = ((misaligned_uint32_t const *)data)->d; +} + +/** + * @brief Read a register to a potentially unaligned destination + * @param[in] reg The address of the register + * @param[out] data The address of the destination + */ +__NONNULL_ALL +__INLINE +void atm_reg_read(uint32_t volatile const *reg, void *data) +{ + ((misaligned_uint32_t *)data)->d = *reg; +} + +/** + * @brief Write a series of registers from a potentially unaligned source + * + * @note Register writes are always words. If there is not enough bytes to fill + * the final word it will be padded with 0s + * + * @param[out] reg The address of the register + * @param[in] data The address of the data + * @param[in] num_bytes The number of bytes from the source + */ +__NONNULL(1, 2) +void atm_reg_write_multiple(uint32_t volatile *reg, uint8_t const *data, + size_t const num_bytes); + +/** + * @brief Write a series of registers from a potentially unaligned source + * + * @note Register reads are always words. If there is not enough bytes to fill + * the final word it will be padded with 0s + * + * @param[in] reg The address of the register + * @param[out] data The address of the destination + * @param[in] num_bytes The number of bytes to write to the destination + */ +__NONNULL(1, 2) +void atm_reg_read_multiple(uint32_t volatile const *reg, uint8_t *data, + size_t const num_bytes); + +#ifdef __cplusplus +} +#endif + +/// @} ATM_UTILS_REG diff --git a/ATM33xx-5/lib/atm_vendor/CMakeLists.txt b/ATM33xx-5/lib/atm_vendor/CMakeLists.txt new file mode 100644 index 0000000..21012cc --- /dev/null +++ b/ATM33xx-5/lib/atm_vendor/CMakeLists.txt @@ -0,0 +1,59 @@ +# Copyright (c) 2024 Atmosic +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories( + . +) +zephyr_sources( + atm_vendor.c + atm_hci_uart.c +) + +zephyr_compile_definitions_ifdef(CONFIG_VND_DBG_MMR CFG_VND_DBG_MMR) +zephyr_compile_definitions_ifdef(CONFIG_VND_DBG_MMW CFG_VND_DBG_MMW) +zephyr_compile_definitions_ifdef(CONFIG_VND_BLE_REGR CFG_VND_BLE_REGR) +zephyr_compile_definitions_ifdef(CONFIG_VND_BLE_REGW CFG_VND_BLE_REGW) +zephyr_compile_definitions_ifdef(CONFIG_VND_EN_TXCW CFG_VND_EN_TXCW) +zephyr_compile_definitions_ifdef(CONFIG_VND_CAP CFG_VND_CAP) +zephyr_compile_definitions_ifdef(CONFIG_VND_SYS_MMR CFG_VND_SYS_MMR) +if (CONFIG_VND_PV_TEST) + zephyr_compile_definitions(CFG_VND_PV_TEST) + zephyr_compile_definitions(CFG_NONRF_HARV) + zephyr_compile_definitions(VHARV_RANGE=VHARV_RANGE_1P7V_2P0V) + zephyr_compile_definitions(VSTORE_MAX_EQ_3p3V) +endif() +zephyr_compile_definitions_ifdef(CONFIG_VND_PSM CFG_VND_PSM) +if (CONFIG_VND_GADC) + message("VND_GAD Not Support") +endif() +if (CONFIG_VND_IO_CTRL) + message("VND_IO_CTRL Not Support") +endif() +if (CONFIG_VND_TAG_RD) + message("VND_TAG_RD Not Support") +endif() +if (CONFIG_VND_SET_BDDR) + message("VND_SET_BDDR Not Support") +endif() +if (CONFIG_VND_MALLOC) + message("VND_MALLOC Not Support") +endif() +if (CONFIG_VND_PMU_RADIO_REGR) + message("VND_PMU_RADIO_REGR Not Support") +endif() +if (CONFIG_VND_PMU_RADIO_REGW) + message("VND_PMU_RADIO_REGW Not Support") +endif() +if (CONFIG_VND_COREMARK) + message("VND_COREMARK Not Support") +endif() +if (CONFIG_VND_WFI) + message("VND_WFI Not Support") +endif() +if (CONFIG_VND_NO_CLOCK) + message("VND_NO_CLOCK Not Support") +endif() +if (CONFIG_VND_WHILE_ONE) + message("VND_WHILE_ONE Not Support") +endif() diff --git a/ATM33xx-5/lib/atm_vendor/Kconfig b/ATM33xx-5/lib/atm_vendor/Kconfig new file mode 100644 index 0000000..911ad8a --- /dev/null +++ b/ATM33xx-5/lib/atm_vendor/Kconfig @@ -0,0 +1,96 @@ +# Copyright (c) 2024 Atmosic +# +# SPDX-License-Identifier: Apache-2.0 + +config VND_DBG_MMR + bool "[0xFC01] DBG Read Memory." + default y + +config VND_DBG_MMW + bool "[0xFC02] DBG Write Memory." + default y + +config VND_BLE_REGR + bool "[0xFC30] BLE Register Read." + default y + +config VND_BLE_REGW + bool "[0xFC31] BLE Register Write." + default y + +config VND_EN_TXCW + bool "[0xF802] Tx CW mode control - Enable TX CW mode on specific BLE RF Channel(0~39), RF Channel 255 is used to disable Tx CW mode." + default y + +config VND_CAP + bool "[0xF803] 16MXtal cap. control - set cap. value." + default y + +config VND_SYS_MMR + bool "[0xF804] Memory read - read system memory value by address." + default y + +config VND_PV_TEST + bool "[0xF80C] PV Test" + default y + +config VND_VND_PSM + bool "[0xF80F] PSM - set power save mode." + default n + +config VND_GADC + bool "[0xF80B] GADC - set gadc value." + default n + +config VND_IO_CTRL + bool "[0xF80A] IO Control - set io pin." + default n + +config VND_TAG_RD + bool "[0xF805] Read Flash NVDS Tag - read tag value." + default n + +config VND_SET_BDDR + bool "[0xF806] Set Public BD Address." + default n + +config VND_MALLOC + bool "[0xF809] Memory Allocate - Allocate n bytes memory (little endian)." + default n + +config VND_PMU_RADIO_REGR + bool "[0xFC33] PMU Radio Register Read." + default n + +config VND_COREMARK + bool "[0xF810] coremark - get coremark score multiplied by 100." + default n + +config VND_WFI + bool "[0xF811] wfi - do wfi to be used for power measure tests." + default n + +config VND_NO_CLOCK + bool "[0xF812] no_clock - turn off mpc clock to be used for power measure tests." + default n + +config VND_WHILE_ONE + bool "[0xF813] while_one - do while_one to be used for power measure tests" + default n + +config ATM_LOG_DEFAULT_LEVEL + int "atm vendor logging level" + depends on LOG + default LOG_DEFAULT_LEVEL + +config RUNTIME_EN_HCI_VENDOR + bool "Runtime Enable HCI vendor" + default n + +config ATM_VENDOR_TX_STACK_SIZE + int "ATM hci uart tx thread stack size" + default 400 + +config ATM_VENDOR_RX_STACK_SIZE + int "ATM hci uart rx thread stack size" + default 800 diff --git a/ATM33xx-5/lib/atm_vendor/atm_hci_uart.c b/ATM33xx-5/lib/atm_vendor/atm_hci_uart.c new file mode 100644 index 0000000..52c1d68 --- /dev/null +++ b/ATM33xx-5/lib/atm_vendor/atm_hci_uart.c @@ -0,0 +1,461 @@ +/* + ******************************************************************************* + * + * @file atm_hci_uart.c + * + * @brief ATM HCI data from uart to another device/CPU + * using and handle vendor command with hci_raw module for zephyr only + * + * Copyright (C) Atmosic 2024 + * + ******************************************************************************* + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include "atm_vendor_internal.h" +#include "atm_hci_uart.h" +#include "atm_utils_c.h" + +#define LOG_MODULE_NAME atm_hci_uart +LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_ATM_LOG_DEFAULT_LEVEL); + +static const struct device *const hci_uart_dev = + DEVICE_DT_GET(DT_NODELABEL(uart0)); +static K_THREAD_STACK_DEFINE(tx_thread_stack, CONFIG_ATM_VENDOR_TX_STACK_SIZE); +static struct k_thread tx_thread_data; +static K_THREAD_STACK_DEFINE(rx_thread_stack, CONFIG_ATM_VENDOR_RX_STACK_SIZE); +static struct k_thread rx_thread_data; +static K_FIFO_DEFINE(tx_queue); + +/* RX in terms of bluetooth communication */ +static K_FIFO_DEFINE(uart_tx_queue); + +#define H4_CMD 0x01 +#define H4_ACL 0x02 +#define H4_SCO 0x03 +#define H4_EVT 0x04 +#define H4_ISO 0x05 + +/* Receiver states. */ +#define ST_IDLE 0 /* Waiting for packet type. */ +#define ST_HDR 1 /* Receiving packet header. */ +#define ST_PAYLOAD 2 /* Receiving packet payload. */ +#define ST_DISCARD 3 /* Dropping packet. */ + +/* Length of a discard/flush buffer. + * This is sized to align with a BLE HCI packet: + * 1 byte H:4 header + 32 bytes ACL/event data + * Bigger values might overflow the stack since this is declared as a local + * variable, smaller ones will force the caller to call into discard more + * often. + */ +#define H4_DISCARD_LEN 33 + +#ifdef CONFIG_BT_HCI_RAW_CMD_EXT +struct vendor_handler const *vendor_hdlr; +static size_t vendor_hdlr_size; + +static void atm_hci_uart_hci_vs_send(uint8_t const *data, int data_len) +{ + for (int i = 0; i < data_len; i++) { + uart_poll_out(hci_uart_dev, data[i]); + } + return; +} + +static struct vendor_handler const *atm_hci_uart_find_vend_handler(uint16_t ocf, + uint16_t ogf) +{ + for (uint32_t i = 0; i < vendor_hdlr_size; i++) { + struct vendor_handler const *hdlr = &vendor_hdlr[i]; + if ((hdlr->ocf == ocf) && (hdlr->ogf == ogf)) { + return hdlr; + } + } + LOG_DBG("handler not found for ocf(0x%04X) ogf(0x%04X)", ocf, ogf); + return NULL; +} + +static uint8_t atm_hci_uart_dispatch_handler(uint16_t ocf, uint16_t ogf, + uint8_t const *data) +{ + struct vendor_handler const *hdlr = + atm_hci_uart_find_vend_handler(ocf, ogf); + if (!hdlr) { + return HCI_EVT_ERROR; + } + uint8_t *hdlr_data = (uint8_t *)CONTEXT_VOID_P(data); + hdlr->cmd_hdlr(hdlr_data); + uint32_t size; + uint8_t *bufptr; + hdlr->cmd_cmp_hdlr(&bufptr, &size); + atm_hci_uart_hci_vs_send(bufptr, size); + return BT_HCI_ERR_EXT_HANDLED; +} + +#define ATM_HCI_UART_OP(ocf, ogf) ((ogf << 8) | ocf) +#define ATM_VS_SET(name) \ + BT_HCI_RAW_CMD_EXT(ATM_HCI_UART_OP(name##_OCF, name##_OGF), name##_LEN, \ + name##_HDLR) +#define ATM_VS_HDLR(name) \ + static uint8_t name##_HDLR(struct net_buf *buf) \ + { \ + if (!name) { \ + LOG_DBG("%s not support", #name); \ + return HCI_EVT_ERROR; \ + } \ + return atm_hci_uart_dispatch_handler(name##_OCF, name##_OGF, \ + buf->data); \ + } + +/* + * How to add new vendor command + * Step 1. add new vendor command definitions in + * atm_vendor/atm_vendor_internal.h + * Step 2. implement vendor command hdlr and cmp_hdlr in atm_vendor/atm_vendor.c + * Step 3. add new vendor command to cmd_ext by ATM_VS_SET and ATM_VS_HDLR + */ + +ATM_VS_HDLR(RD_MEM_CMD) +ATM_VS_HDLR(WR_MEM_CMD) +ATM_VS_HDLR(BLE_REG_RD_CMD) +ATM_VS_HDLR(BLE_REG_WR_CMD) +ATM_VS_HDLR(EN_TXCW_CMD) +ATM_VS_HDLR(FREQCAL_CMD) +ATM_VS_HDLR(MM_R_CMD) +ATM_VS_HDLR(PV_TEST_CMD) + +static struct bt_hci_raw_cmd_ext cmd_ext[] = { + ATM_VS_SET(RD_MEM_CMD), + ATM_VS_SET(WR_MEM_CMD), + ATM_VS_SET(BLE_REG_RD_CMD), + ATM_VS_SET(BLE_REG_WR_CMD), + ATM_VS_SET(EN_TXCW_CMD), + ATM_VS_SET(FREQCAL_CMD), + ATM_VS_SET(MM_R_CMD), + ATM_VS_SET(PV_TEST_CMD), +}; + +#endif // CONFIG_BT_HCI_RAW_CMD_EXT + +static int atm_hci_uart_h4_send(struct net_buf *buf) +{ + net_buf_put(&uart_tx_queue, buf); + uart_irq_tx_enable(hci_uart_dev); + return 0; +} + +static int h4_read(struct device const *uart, uint8_t *buf, size_t len) +{ + return uart_fifo_read(uart, buf, len); +} + +static bool valid_type(uint8_t type) +{ + return (type == H4_CMD) | (type == H4_ACL) | (type == H4_ISO); +} + +/* Function expects that type is validated and only CMD, ISO or ACL will be + used. +*/ +static uint32_t get_len(uint8_t const *hdr_buf, uint8_t type) +{ + switch (type) { + case H4_CMD: + return ((struct bt_hci_cmd_hdr const *)hdr_buf)->param_len; + case H4_ISO: + return bt_iso_hdr_len( + sys_le16_to_cpu(((struct bt_hci_iso_hdr const *)hdr_buf)->len)); + case H4_ACL: + return sys_le16_to_cpu( + ((struct bt_hci_acl_hdr const *)hdr_buf)->len); + default: + LOG_ERR("Invalid type: %u", type); + return 0; + } +} + +/* Function expects that type is validated and only CMD, ISO or ACL will be + used. +*/ +static int hdr_len(uint8_t type) +{ + switch (type) { + case H4_CMD: + return sizeof(struct bt_hci_cmd_hdr); + case H4_ISO: + return sizeof(struct bt_hci_iso_hdr); + case H4_ACL: + return sizeof(struct bt_hci_acl_hdr); + default: + LOG_ERR("Invalid type: %u", type); + return 0; + } +} + +static void rx_isr(void) +{ + static struct net_buf *buf; + static int remaining; + static uint8_t state; + static uint8_t type; + static uint8_t hdr_buf[MAX(sizeof(struct bt_hci_cmd_hdr), + sizeof(struct bt_hci_acl_hdr))]; + int read; + do { + switch (state) { + case ST_IDLE: { + /* Get packet type */ + read = h4_read(hci_uart_dev, &type, sizeof(type)); + /* since we read in loop until no data is in the fifo, + * it is possible that read = 0. + */ + if (read) { + if (valid_type(type)) { + /* Get expected header size and switch + * to receiving header. + */ + remaining = hdr_len(type); + state = ST_HDR; + } else { + LOG_ERR("Unknown header %d", type); + } + } + } break; + case ST_HDR: { + read = h4_read(hci_uart_dev, + &hdr_buf[hdr_len(type) - remaining], remaining); + remaining -= read; + if (!remaining) { + /* Header received. Allocate buffer and get + * payload length. If allocation fails leave + * interrupt. On failed allocation state machine + * is reset. + */ + buf = bt_buf_get_tx(BT_BUF_H4, K_NO_WAIT, &type, + sizeof(type)); + if (!buf) { + LOG_ERR("No available command buffers!"); + state = ST_IDLE; + return; + } + + remaining = get_len(hdr_buf, type); + net_buf_add_mem(buf, hdr_buf, hdr_len(type)); + if (remaining > net_buf_tailroom(buf)) { + LOG_ERR("Not enough space in buffer"); + net_buf_unref(buf); + state = ST_DISCARD; + } else { + state = ST_PAYLOAD; + } + } + } break; + case ST_PAYLOAD: { + read = h4_read(hci_uart_dev, net_buf_tail(buf), remaining); + buf->len += read; + remaining -= read; + if (!remaining) { + /* Packet received */ + net_buf_put(&tx_queue, buf); + state = ST_IDLE; + } + } break; + case ST_DISCARD: { + uint8_t discard[H4_DISCARD_LEN]; + size_t to_read = MIN(remaining, sizeof(discard)); + + read = h4_read(hci_uart_dev, discard, to_read); + remaining -= read; + if (!remaining) { + state = ST_IDLE; + } + } break; + default: { + read = 0; + __ASSERT_NO_MSG(0); + } break; + } + } while (read); +} + +static void tx_isr(void) +{ + static struct net_buf *buf; + + if (!buf) { + buf = net_buf_get(&uart_tx_queue, K_NO_WAIT); + if (!buf) { + uart_irq_tx_disable(hci_uart_dev); + return; + } + } + int len = uart_fifo_fill(hci_uart_dev, buf->data, buf->len); + net_buf_pull(buf, len); + if (!buf->len) { + net_buf_unref(buf); + buf = NULL; + } +} + +static void bt_uart_isr(struct device const *unused, void *user_data) +{ + ARG_UNUSED(unused); + ARG_UNUSED(user_data); + + if (!(uart_irq_rx_ready(hci_uart_dev) || uart_irq_tx_ready(hci_uart_dev))) { + LOG_ERR("spurious interrupt"); + } + + if (uart_irq_tx_ready(hci_uart_dev)) { + tx_isr(); + } + + if (uart_irq_rx_ready(hci_uart_dev)) { + rx_isr(); + } +} + +static void tx_thread(void *p1, void *p2, void *p3) +{ + for (;;) { + /* Wait until a buffer is available */ + struct net_buf *buf = net_buf_get(&tx_queue, K_FOREVER); + /* Pass buffer to the stack */ + int err = bt_send(buf); + if (err) { + net_buf_unref(buf); + } + /* Give other threads a chance to run if tx_queue keeps getting + * new data all the time. + */ + k_yield(); + } +} + +static void rx_thread(void *p1, void *p2, void *p3) +{ + /* incoming events and data from the controller */ + static K_FIFO_DEFINE(rx_queue); + + /* Enable the raw interface, this will in turn open the HCI driver */ + bt_enable_raw(&rx_queue); + +#ifdef CONFIG_BT_HCI_RAW_CMD_EXT + bt_hci_raw_cmd_ext_register(cmd_ext, ARRAY_SIZE(cmd_ext)); + LOG_DBG("HCI raw cmd extention register done"); +#endif + + for (;;) { + struct net_buf *buf = net_buf_get(&rx_queue, K_FOREVER); + int err = atm_hci_uart_h4_send(buf); + if (err) { + LOG_ERR("Failed to send atm_hci_uart_h4_send"); + } + k_yield(); + } +} + +void atm_uart_init(void) +{ + LOG_DBG("start"); + if (!device_is_ready(hci_uart_dev)) { + LOG_DBG("HCI UART %s is not ready", hci_uart_dev->name); +#ifdef CONFIG_AUTO_TEST + printk("[*** Test Fail ***]\n\x03\n"); +#endif + return; + } + + uart_irq_rx_disable(hci_uart_dev); + uart_irq_tx_disable(hci_uart_dev); + + uart_irq_callback_set(hci_uart_dev, bt_uart_isr); + + uart_irq_rx_enable(hci_uart_dev); + LOG_DBG("done"); + return; +} + +void atm_hci_init(void) +{ + LOG_DBG("start"); + + __ASSERT(hci_uart_dev, "UART device is NULL"); + + if (IS_ENABLED(CONFIG_BT_WAIT_NOP)) { + /* Issue a Command Complete with NOP */ + const struct { + uint8_t const h4; + struct bt_hci_evt_hdr const hdr; + struct bt_hci_evt_cmd_complete const cc; + } __packed cc_evt = { + .h4 = H4_EVT, + .hdr = + { + .evt = BT_HCI_EVT_CMD_COMPLETE, + .len = sizeof(struct bt_hci_evt_cmd_complete), + }, + .cc = + { + .ncmd = 1, + .opcode = sys_cpu_to_le16(BT_OP_NOP), + }, + }; + + for (int i = 0; i < sizeof(cc_evt); i++) { + uart_poll_out(hci_uart_dev, *(((uint8_t const *)&cc_evt) + i)); + } + } + + /* Spawn the TX thread and start feeding commands and data to the + * controller + */ + k_thread_create(&tx_thread_data, tx_thread_stack, + K_THREAD_STACK_SIZEOF(tx_thread_stack), tx_thread, NULL, NULL, NULL, + K_PRIO_COOP(7), 0, K_NO_WAIT); + k_thread_name_set(&tx_thread_data, "HCI uart TX"); + + /* Spawn the RX thread and passthrough incoming events and data from the + * controller + */ + k_thread_create(&rx_thread_data, rx_thread_stack, + K_THREAD_STACK_SIZEOF(rx_thread_stack), rx_thread, NULL, NULL, NULL, + K_PRIO_COOP(7), 0, K_NO_WAIT); + k_thread_name_set(&rx_thread_data, "HCI uart RX"); + + LOG_DBG("done"); + +#ifdef CONFIG_AUTO_TEST + printk("[*** Test Success ***]\n\x04\n"); +#endif +} + +#ifdef CONFIG_BT_HCI_RAW_CMD_EXT +void atm_vendor_handler_register(struct vendor_handler const *hdrs, size_t size) +{ + vendor_hdlr = hdrs; + vendor_hdlr_size = size; +} +#endif diff --git a/ATM33xx-5/lib/atm_vendor/atm_hci_uart.h b/ATM33xx-5/lib/atm_vendor/atm_hci_uart.h new file mode 100644 index 0000000..53c25cd --- /dev/null +++ b/ATM33xx-5/lib/atm_vendor/atm_hci_uart.h @@ -0,0 +1,61 @@ +/** + ******************************************************************************* + * + * @file atm_hci_uart.h + * + * @brief Header File - ATM HCI data from uart to another device/CPU + * using and handle vendor command with hci_raw module for zephyr only + * + * Copyright (C) Atmosic 2024 + * + ******************************************************************************* + */ + +#pragma once + +#include "compiler.h" // __NORETURN inline functions + +#ifdef CONFIG_BT_HCI_RAW_CMD_EXT +#include "atm_vendor_internal.h" +#endif + +/** + * @defgroup ATM_BTFM_HCI_UART ATM HCI uart + * @ingroup ATM_BTFM_PROC + * @brief ATM HCI uart + * + * This module contains the necessary API to int uart and hci data handler. + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable and initial uart device handler + */ +void atm_uart_init(void); + +/** + * @brief Enable and initial hci raw data handler + */ +void atm_hci_init(void); + +#ifdef CONFIG_BT_HCI_RAW_CMD_EXT +/** + * @brief ATM vendor command handler register + * @param[in] hdrs ATM vendor command handlers. + * @param[in] size Array size of ATM vendor command handlers. + */ +__NONNULL_ALL +void atm_vendor_handler_register(struct vendor_handler const *hdrs, + size_t size); +#endif + +#ifdef __cplusplus +} +#endif + +///@} diff --git a/ATM33xx-5/lib/atm_vendor/atm_vendor.c b/ATM33xx-5/lib/atm_vendor/atm_vendor.c new file mode 100644 index 0000000..284e569 --- /dev/null +++ b/ATM33xx-5/lib/atm_vendor/atm_vendor.c @@ -0,0 +1,1727 @@ +/** + ****************************************************************************** + * + * @file atm_vendor.c + * + * @brief Atmosic HCI Vendor Command + * + * Copyright (C) Atmosic 2020-2024 + * + ****************************************************************************** + */ +#ifdef CONFIG_SOC_FAMILY_ATM +#include +#include +#include +#include +#include +#include +#include "atm_hci_uart.h" +#endif +#include +#include +#include "arch.h" +#include "at_apb_pseq_regs_core_macro.h" +#include "at_wrpr.h" +#include "rif_regs_core_macro.h" +#include "string.h" +#include "atm_vendor.h" +#include "atm_vendor_internal.h" +#include "atm_utils_c.h" +#include "_reg_blecore.h" +#include "spi.h" +#include "pmu_spi.h" +#include "radio_spi.h" +#include "at_clkrstgen.h" +#include "atm_bp_clock.h" +#ifndef CONFIG_SOC_FAMILY_ATM +#include "vectors.h" +#include "intisr.h" +#include "hci.h" +#include "interrupt.h" +#include "ahi.h" +#include "atm_ble.h" +#include "uart_rep_vec.h" +#include "reset.h" +#include "uart.h" +#include "sw_event.h" +#endif + +#ifdef CFG_VND_IO_CTRL +#include "atm_gpio.h" +#endif + +#ifdef CFG_VND_TAG_RD +#include "nvds.h" +#endif + +#ifdef CFG_VND_SET_BDDR +#include "framework_lib.h" +#endif + +#ifdef CFG_VND_GPIO_TEST +#include "at_pinmux.h" +#include "pinmux.h" +#endif + +#ifdef CFG_VND_PSM +#include "pseq.h" +#endif + +#ifdef CFG_NONRF_HARV +#include "pmu.h" +#endif + +#ifdef CFG_VND_COREMARK +#include "atm_coremark_port.h" +#endif + +#ifdef CONFIG_SOC_FAMILY_ATM +#ifndef H4_MSG_LC_HCI_EVT +#define H4_MSG_LC_HCI_EVT 0x04 +#endif +#endif + +#define SET_HCI_EVT_STATUS(status) *(*bufptr + HCI_EVT_STATUS_POS) = status; + +#ifdef CONFIG_SOC_FAMILY_ATM +#define LOG_HCI_VENDOR_MODULE_NAME atm_vendor +LOG_MODULE_REGISTER(LOG_HCI_VENDOR_MODULE_NAME, CONFIG_ATM_LOG_DEFAULT_LEVEL); +#else +static uint8_t const AG_READY_EVT[] = {H4_MSG_LC_HCI_EVT, HCI_EVT_VENDOR, 0x06, + SEVT_DUT_READY, 'A', 'T', 'M', 'F', 'G'}; +static uint8_t *ag_ready_evt; +static struct vendor_handler const *curr_vnd_hdlr; +static uint8_t rx_state; +static bool internal_reset; +#endif // CONFIG_SOC_FAMILY_ATM + +static uint8_t hcievent_buffer[258]; +__UNINIT static bool volatile hci_vendor_en; + +static union { +#ifdef CFG_VND_EN_TXCW + // vendor_stage: S_VENDOR_EN_TXCW + en_txsw_cmd_t en_txcw_cmd; +#endif +#ifdef CFG_VND_CAP + // vendor_stage: VENDOR_FREQ_CAL + freqcal_cmd_t freq_cal_cmd; +#endif +#ifdef CFG_VND_SYS_MMR + // vendor_stage: VENDOR_MMR + mm_r_cmd_t mmr_cmd; +#endif +#ifdef CFG_VND_PV_TEST + // vendor_stage: VENDOR_PV_TEST + pv_test_cmd_t pv_test_cmd; +#endif +#ifdef CFG_VND_PSM + // vendor_stage: VENDOR_PSM + psm_cmd_t psm_cmd; +#endif +#ifdef CFG_VND_GADC + // vendor_stage: VENDOR_GADC_CH_SAMPLE_START + // vendor_state: VENDOR_GADC_CH_SAMPLE_GET + // vendor_state: VENDOR_GADC_CH_CALI_START + // vendor_state: VENDOR_GADC_CH_CALI_GET + // vendor_state: VENDOR_GADC_CALI_SETTING + gadc_cmd_t gadc_cmd; +#endif +#ifdef CFG_VND_IO_CTRL + // vendor_stage: VENDOR_IO + io_cmd_t io_cmd; +#endif +#ifdef CFG_VND_TAG_RD + // vendor_stage: VENDOR_TAG_READ + tag_r_cmd_t tag_cmd; +#endif +#ifdef CFG_VND_SET_BDDR + // vendor_stage: VENDOR_SET_BDADDR + set_bd_addr_cmd_t bd_addr_cmd; +#endif +#ifdef CFG_VND_MALLOC + // vendor_stage: VENDOR_MALLOC + malloc_cmd_t malloc_cmd; + malloc_ctx_t malloc_ctx; +#endif +#ifdef CFG_VND_DBG_MMR + // vendor_stage: VENDOR_RD_MEM + rd_mem_cmd_t dbg_rd_mem_cmd; +#endif +#ifdef CFG_VND_DBG_MMW + // vendor_stage: VENDOR_WR_MEM + wr_mem_cmd_t dbg_wr_mem_cmd; +#endif +#ifdef CFG_VND_BLE_REGR + // vendor_stage: VENDOR_BLE_REG_RD + ble_reg_rd_cmd_t dbg_ble_reg_rd_cmd; +#endif +#ifdef CFG_VND_BLE_REGW + // vendor_stage: VENDOR_BLE_REG_WR + ble_reg_wr_cmd_t dbg_ble_reg_wr_cmd; +#endif +#ifdef CFG_VND_PMU_RADIO_REGR + // vendor_stage: VENDOR_PMU_RADIO_REG_RD + pmu_radio_reg_rd_cmd_t dbg_pmu_radio_reg_rd_cmd; +#endif +#ifdef CFG_VND_PMU_RADIO_REGW + // vendor_stage: VENDOR_PMU_RADIO_REG_WR + pmu_radio_reg_wr_cmd_t dbg_pmu_radio_reg_wr_cmd; +#endif +#ifdef CFG_VND_COREMARK + // vendor_stage: VENDOR_COREMARK + coremark_cmd_t coremark_cmd; +#endif +#if (defined(CFG_VND_WFI) || defined(CFG_VND_NO_CLOCK) || \ + defined(CFG_VND_WHILE_ONE)) + // power_cmd is used by these commands below + // vendor_stage: VENDOR_WFI + // vendor_stage: VENDOR_NO_CLOCK + // vendor_stage: VENDOR_WHILE_ONE + power_cmd_t power_cmd; +#endif + uint8_t dummy; +} dat; + +#if defined(CFG_VND_BLE_REGR) || defined(CFG_VND_BLE_REGW) || \ + defined(CFG_VND_PMU_RADIO_REGR) || defined(CFG_VND_PMU_RADIO_REGW) || \ + defined(CFG_VND_DBG_MMR) || defined(CFG_VND_DBG_MMW) +__INLINE bool check_evt_unsupport(uint8_t **bufptr) +{ +#ifdef CONFIG_SOC_FAMILY_ATM + return true; +#else + if ((*(*bufptr + 1) == HCI_EVT_CMD_CPM && + *(*bufptr + HCI_EVT_STATUS_POS) == HCI_EVT_ERROR) || + (*(*bufptr + 1) == HCI_EVT_CMD_CS && + *(*bufptr + HCI_EVT_CS_STATUS_POS) == HCI_EVT_ERROR)) { + return true; + } + return false; +#endif +} +#endif + +static void init_hci_event(uint8_t ocf, uint8_t ogf, uint8_t extra_len, + uint8_t status, uint8_t **bufptr, uint32_t *size) +{ + hcievent_buffer[0] = H4_MSG_LC_HCI_EVT; + hcievent_buffer[1] = HCI_EVT_CMD_CPM; + hcievent_buffer[2] = (extra_len + BASIC_HCI_EVT_HD_LEN); + hcievent_buffer[3] = HCI_EVT_NOC; + hcievent_buffer[4] = ocf; + hcievent_buffer[5] = ogf; + hcievent_buffer[6] = status; + *bufptr = hcievent_buffer; + *size = (extra_len + BASIC_HCI_EVT_CMD_LEN); +} + +#ifdef CFG_VND_SET_BDDR +static void vendor_set_public_bd_addr_handler(uint8_t *buf) +{ + memcpy(dat.bd_addr_cmd.bd_addr, buf, BD_ADDR_LEN); +} + +static void set_bd_addr(uint8_t const *addr) +{ + if (!addr) { + return; + } + framework_set_llm_env_pub_addr((ble_bdaddr_t const *)addr); +} + +static void vendor_set_public_bd_addr_cmp_handler(uint8_t **bufptr, + uint32_t *size) +{ + set_bd_addr(dat.bd_addr_cmd.bd_addr); + init_hci_event(SET_BD_ADDR_CMD_OCF, SET_BD_ADDR_CMD_OGF, 0, + HCI_EVT_SUCCESS, bufptr, size); +} +#endif + +#ifdef CFG_VND_SET_ADV_CH +static uint8_t ch_offset; +static adv_channel_t ch_mask; +static void vendor_set_adv_ch_handler(uint8_t *buf) +{ + ch_mask = *buf; + ch_offset = *(buf + 1); +} + +// Handle set advertising channel HCI command +static void set_adv_ch(adv_channel_t mask, uint8_t offset_mhz) +{ + static bool reset_ch_offsets = false; + if (!reset_ch_offsets) { + atm_ble_reset_ch_offsets(); + reset_ch_offsets = true; + } + + atm_ble_set_adv_channel(mask, offset_mhz); + APP_TRACE(" set adv ch [%u] to [%u] MHz", mask, offset_mhz); +} + +static void vendor_set_adv_ch_cmp_handler(uint8_t **bufptr, uint32_t *size) +{ + init_hci_event(SET_ADV_CH_CMD_OCF, SET_ADV_CH_CMD_OGF, 0, HCI_EVT_SUCCESS, + bufptr, size); + + if (!(ch_mask & (BLE_ADV_CHANNEL_37 | BLE_ADV_CHANNEL_38 | + BLE_ADV_CHANNEL_39)) || !((ch_offset >= 0) && (ch_offset <= 80))) { + SET_HCI_EVT_STATUS(HCI_EVT_ERROR); + } else { + set_adv_ch(ch_mask, ch_offset); + } +} +#endif + +#ifdef CFG_VND_BLE_REGR +static void vendor_dbg_ble_reg_rd_handler(uint8_t *buf) +{ + dat.dbg_ble_reg_rd_cmd.reg_addr = atm_get_le16(buf); +} + +static void vendor_dbg_ble_reg_rd_cmp_handler(uint8_t **bufptr, uint32_t *size) +{ + if (!check_evt_unsupport(bufptr)) { + // stack support + APP_TRACE("stack support"); + return; + } + +#define REG_BLE_RD(addr) (*(volatile uint32_t *)(REG_BLECORE_BASE_ADDR + addr)) + + // stack not support, implement here + APP_TRACE("stack not support"); + uint32_t value = REG_BLE_RD(dat.dbg_ble_reg_rd_cmd.reg_addr); + init_hci_event(BLE_REG_RD_CMD_OCF, BLE_REG_RD_CMD_OGF, 6, HCI_EVT_SUCCESS, + bufptr, size); + + atm_set_le16(&hcievent_buffer[7], dat.dbg_ble_reg_rd_cmd.reg_addr); + atm_set_le32(&hcievent_buffer[9], value); +} +#endif + +#ifdef CFG_VND_BLE_REGW +static void vendor_dbg_ble_reg_wr_handler(uint8_t *buf) +{ + dat.dbg_ble_reg_wr_cmd.reg_addr = atm_get_le16(buf); + dat.dbg_ble_reg_wr_cmd.reg_value = atm_get_le32(&buf[2]); +} + +static void vendor_dbg_ble_reg_wr_cmp_handler(uint8_t **bufptr, uint32_t *size) +{ + if (!check_evt_unsupport(bufptr)) { + // stack support + APP_TRACE("stack support"); + return; + } + +#define REG_BLE_WR(addr, value) \ + (*(volatile uint32_t *)(REG_BLECORE_BASE_ADDR + addr)) = (value) + + // stack not support, implement here + APP_TRACE("stack not support"); + REG_BLE_WR(dat.dbg_ble_reg_wr_cmd.reg_addr, + dat.dbg_ble_reg_wr_cmd.reg_value); + init_hci_event(BLE_REG_WR_CMD_OCF, BLE_REG_WR_CMD_OGF, 2, HCI_EVT_SUCCESS, + bufptr, size); + + atm_set_le16(&hcievent_buffer[7], dat.dbg_ble_reg_wr_cmd.reg_addr); +} +#endif + +#ifdef CFG_VND_PMU_RADIO_REGR + +static uint32_t do_pmu_radio_read(uint32_t block, uint32_t addr, uint8_t is_pmu) +{ + int resp; + + if (is_pmu) { + WRPR_CTRL_PUSH(CMSDK_PMU, WRPR_CTRL__CLK_ENABLE) + { + resp = spi_pmuradio_read_word(&spi_pmu, block, addr); + } + WRPR_CTRL_POP(); + } else { + WRPR_CTRL_PUSH(CMSDK_RADIO, WRPR_CTRL__CLK_ENABLE) + { + resp = spi_pmuradio_read_word(&spi_radio, block, addr); + } + WRPR_CTRL_POP(); + } + + DEBUG_TRACE("pmu_radio read block=%" PRIu32 ", addr=%" PRIu32 ", is_pmu=%d," + " resp=%d", + block, addr, is_pmu, resp); + return resp; +} + +static void vendor_dbg_pmu_radio_reg_rd_handler(uint8_t *buf) +{ + dat.dbg_pmu_radio_reg_rd_cmd.reg_block = atm_get_le32(buf); + dat.dbg_pmu_radio_reg_rd_cmd.reg_addr = atm_get_le32(&buf[4]); + dat.dbg_pmu_radio_reg_rd_cmd.is_pmu = buf[8]; +} + +static void vendor_dbg_pmu_radio_reg_rd_cmp_handler(uint8_t **bufptr, + uint32_t *size) +{ + if (!check_evt_unsupport(bufptr)) { + // stack support + APP_TRACE("stack support"); + return; + } + + // stack not support, implement here + APP_TRACE("stack not support"); + uint32_t value = do_pmu_radio_read(dat.dbg_pmu_radio_reg_rd_cmd.reg_block, + dat.dbg_pmu_radio_reg_rd_cmd.reg_addr, + dat.dbg_pmu_radio_reg_rd_cmd.is_pmu); + init_hci_event(PMU_RADIO_REG_RD_CMD_OCF, PMU_RADIO_REG_RD_CMD_OGF, 12, + HCI_EVT_SUCCESS, bufptr, size); + + atm_set_le32(&hcievent_buffer[7], dat.dbg_pmu_radio_reg_rd_cmd.reg_block); + atm_set_le32(&hcievent_buffer[11], dat.dbg_pmu_radio_reg_rd_cmd.reg_addr); + atm_set_le32(&hcievent_buffer[15], value); +} +#endif + +#ifdef CFG_VND_PMU_RADIO_REGW + +static void do_pmu_radio_write(uint32_t block, uint32_t addr, uint32_t wdata, + uint8_t is_pmu) +{ + if (is_pmu) { + WRPR_CTRL_PUSH(CMSDK_PMU, WRPR_CTRL__CLK_ENABLE) + { + spi_pmuradio_write_word(&spi_pmu, block, addr, wdata); + } + WRPR_CTRL_POP(); + } else { + WRPR_CTRL_PUSH(CMSDK_RADIO, WRPR_CTRL__CLK_ENABLE) + { + spi_pmuradio_write_word(&spi_radio, block, addr, wdata); + } + WRPR_CTRL_POP(); + } + DEBUG_TRACE("pmu_radio write block=%" PRIu32 ", addr=%" PRIu32 + ", is_pmu=%d, wdata=%" PRIu32, + block, addr, is_pmu, wdata); +} + +static void vendor_dbg_pmu_radio_reg_wr_handler(uint8_t *buf) +{ + dat.dbg_pmu_radio_reg_wr_cmd.reg_block = atm_get_le32(buf); + dat.dbg_pmu_radio_reg_wr_cmd.reg_addr = atm_get_le32(&buf[4]); + dat.dbg_pmu_radio_reg_wr_cmd.reg_value = atm_get_le32(&buf[8]); + dat.dbg_pmu_radio_reg_wr_cmd.is_pmu = buf[12]; +} + +static void vendor_dbg_pmu_radio_reg_wr_cmp_handler(uint8_t **bufptr, + uint32_t *size) +{ + if (!check_evt_unsupport(bufptr)) { + // stack support + APP_TRACE("stack not support"); + return; + } + + // stack not support, implement here + APP_TRACE("stack support"); + do_pmu_radio_write(dat.dbg_pmu_radio_reg_wr_cmd.reg_block, + dat.dbg_pmu_radio_reg_wr_cmd.reg_addr, + dat.dbg_pmu_radio_reg_wr_cmd.reg_value, + dat.dbg_pmu_radio_reg_wr_cmd.is_pmu); + init_hci_event(PMU_RADIO_REG_WR_CMD_OCF, PMU_RADIO_REG_WR_CMD_OGF, 12, + HCI_EVT_SUCCESS, bufptr, size); + + atm_set_le32(&hcievent_buffer[7], dat.dbg_pmu_radio_reg_wr_cmd.reg_block); + atm_set_le32(&hcievent_buffer[11], dat.dbg_pmu_radio_reg_wr_cmd.reg_addr); + atm_set_le32(&hcievent_buffer[15], dat.dbg_pmu_radio_reg_wr_cmd.reg_value); +} +#endif + +#ifdef CFG_VND_EN_TXCW +static void vendor_entxcw_handler(uint8_t *buf) +{ + dat.en_txcw_cmd.enabled = *buf; +} + +// Handle enable TX CW mode HCI command +static void en_txcw_mode(uint8_t rx_byte) +{ + // input value: channel_idx or 0xff to disable + if (rx_byte == 0xFF) { + WRPR_CTRL_SET(CMSDK_RIF, WRPR_CTRL__CLK_ENABLE); + CMSDK_RIF->MODE_CNTL = 0; + APP_TRACE(" tx cw off"); + return; + } + + uint8_t freq = rx_byte * 2; // 2402+k*2MHz + uint32_t txCWCfg = (RIF_MODE_CNTL__RADIO_EN_OVR__WRITE(1) | + RIF_MODE_CNTL__RADIO_EN__WRITE(1) | RIF_MODE_CNTL__TX_EN_OVR__WRITE(1) | + RIF_MODE_CNTL__TX_EN__WRITE(1) | RIF_MODE_CNTL__CHAN_IDX_OVR__WRITE(1) | + RIF_MODE_CNTL__CHAN_IDX__WRITE(freq) | + RIF_MODE_CNTL__TX_POWER_OVR__WRITE(1) | AG_RF_POWER_MAX); + + WRPR_CTRL_SET(CMSDK_RIF, WRPR_CTRL__CLK_ENABLE); + + // Enable Tx CW + CMSDK_RIF->MODE_CNTL = txCWCfg; + APP_TRACE(" tx cw on RF Channel k[%d] MODE_CNTL[0x%" PRIx32 "]", rx_byte, + txCWCfg); +} + +static void vendor_entxcw_cmp_handler(uint8_t **bufptr, uint32_t *size) +{ + en_txcw_mode(dat.en_txcw_cmd.enabled); + init_hci_event(EN_TXCW_CMD_OCF, EN_TXCW_CMD_OGF, 0, HCI_EVT_SUCCESS, bufptr, + size); +} +#endif + +#ifdef CFG_VND_CAP +static void vendor_freqcal_handler(uint8_t *buf) +{ + dat.freq_cal_cmd.rx_byte = *buf; +} + +// Handle 16MXtal cap. value set HCI command +static void xtal_cap_set(uint8_t rx_byte) +{ + uint8_t val = rx_byte; + + WRPR_CTRL_SET(CMSDK_PSEQ, WRPR_CTRL__CLK_ENABLE); + + // xtal cap value set + CMSDK_PSEQ->XTAL_BITS0 = (PSEQ_XTAL_BITS0__XOCAPOUT__WRITE(val)) | + (PSEQ_XTAL_BITS0__XOCAPIN__WRITE(val)); + + APP_TRACE(" xtal cap. set[%d]", val); +} + +static void vendor_freqcal_cmp_handler(uint8_t **bufptr, uint32_t *size) +{ + xtal_cap_set(dat.freq_cal_cmd.rx_byte); + init_hci_event(FREQCAL_CMD_OCF, FREQCAL_CMD_OGF, 0, HCI_EVT_SUCCESS, bufptr, + size); +} +#endif + +#ifdef CFG_VND_PV_TEST +static void vendor_enpvtest_handler(uint8_t *buf) +{ + dat.pv_test_cmd.pv_test_times = atm_get_le16(buf); +} + +#ifdef CFG_NONRF_HARV +static uint16_t pv_test(uint16_t times) +{ + APP_TRACE("pv test-read %d times.", times); + return pmu_harv_get_harvcnt(times); +} +#endif + +static void vendor_enpvtest_cmp_handler(uint8_t **bufptr, uint32_t *size) +{ + init_hci_event(PV_TEST_CMD_OCF, PV_TEST_CMD_OGF, 2, HCI_EVT_SUCCESS, bufptr, + size); + +#ifdef CFG_NONRF_HARV + uint16_t pv_count = pv_test(dat.pv_test_cmd.pv_test_times); + + // Update memory read data into HCI event buffer + atm_set_le16(*bufptr + BASIC_HCI_EVT_CMD_LEN, pv_count); + SET_HCI_EVT_STATUS(HCI_EVT_SUCCESS); +#else + SET_HCI_EVT_STATUS(HCI_EVT_ERROR); +#endif +} +#endif + +#ifdef CFG_VND_GADC +// Calibration setting, this should keep outside the dat union +static float volt4cli; +static float ratio4cli; +static bool gadc_setting_valid(void) +{ + if (!dat.gadc_cmd.gext) { + return (volt4cli >= 1.8f && volt4cli <= 3.3f) && (ratio4cli >= 3.0f && + ratio4cli <= 6.0f); + } + + if (dat.gadc_cmd.gext == 1) { + return (volt4cli >= 1.1f && volt4cli <= 1.8f) && (ratio4cli >= 1.5f && + ratio4cli <= 3.0f); + } + + return false; +} + +static void gadc_result(float result, struct gadc_fifo_s raw_fifo, + struct gadc_cal_s cal, gadc_cb_ctx_t const *ctx) +{ + int16_t raw = raw_fifo.sample_x2 / 2; + APP_TRACE("[ch%d] volt, raw, curcal = %f, %d, %#" PRIx32, + dat.gadc_cmd.sample_ch, (double)result, raw, cal.value); + if (dat.gadc_cmd.gadc_op == GADC_CH_SAMPLE_START) { + dat.gadc_cmd.ch_volt = result; + dat.gadc_cmd.ch_raw = raw; + dat.gadc_cmd.ch_curcal.value = cal.value; + } else if (dat.gadc_cmd.gadc_op == GADC_CH_CALIBRATE_START) { + dat.gadc_cmd.ch_raw = raw; + dat.gadc_cmd.sample_ch = CORE; + dat.gadc_cmd.gadc_op = GADC_CH_CALIBRATE_VDD1A_INTERNAL; + gadc_sample_channel(CORE, gadc_result, CORE_GEXT_DEFAULT, NULL); + } else if (dat.gadc_cmd.gadc_op == GADC_CH_CALIBRATE_VDD1A_INTERNAL) { +#define VDD1A 1.012f + dat.gadc_cmd.vdd1a_raw = raw; + dat.gadc_cmd.ch_newoffset_x2 = + (volt4cli * dat.gadc_cmd.vdd1a_raw - + ratio4cli * VDD1A * dat.gadc_cmd.ch_raw) / + (ratio4cli * VDD1A - volt4cli) * 2; + dat.gadc_cmd.ch_newgain.value = volt4cli / + (dat.gadc_cmd.ch_raw + 0.5f * dat.gadc_cmd.ch_newoffset_x2); + dat.gadc_cmd.ch_newcal.c0_x2 = dat.gadc_cmd.ch_newoffset_x2; + dat.gadc_cmd.ch_newcal.c1_mantissa = + dat.gadc_cmd.ch_newgain.number.fraction >> (23 - 12); + dat.gadc_cmd.ch_newcal.c1_exponent = + dat.gadc_cmd.ch_newgain.number.exponent - (127 - 31); + dat.gadc_cmd.ch_newcal.c1_sign = dat.gadc_cmd.ch_newgain.number.sign; + APP_TRACE("[setting] volt,ratio = %f,%f", (double)volt4cli, + (double)ratio4cli); + + if (gadc_setting_valid()) { + APP_TRACE("[ch%d] new (cal, gain, offset) = (%#" PRIx32 ", %f,%d)", + dat.gadc_cmd.ch, dat.gadc_cmd.ch_newcal.value, + (double)dat.gadc_cmd.ch_newgain.value, + dat.gadc_cmd.ch_newoffset_x2); + // check new volt + float new_volt = 0.988f * dat.gadc_cmd.ch_newgain.value * + (dat.gadc_cmd.ch_raw + 0.5f * dat.gadc_cmd.ch_newoffset_x2); + DEBUG_TRACE("Pass: new volt = %f", (double)new_volt); + } else { + DEBUG_TRACE("Fail: wrong setting"); + dat.gadc_cmd.gadc_status = GADC_ERR_WRONG_CALI_SETTING; + } + } +} + +static void vendor_gadc_handler(uint8_t *buf) +{ + dat.gadc_cmd.gadc_op = buf[0]; + switch (dat.gadc_cmd.gadc_op) { + case GADC_CH_SAMPLE_START: { + dat.gadc_cmd.gadc_status = GADC_ERR_OK; + dat.gadc_cmd.ch = buf[1]; + dat.gadc_cmd.gext = buf[2]; + dat.gadc_cmd.sample_ch = dat.gadc_cmd.ch; + gadc_sample_channel(dat.gadc_cmd.ch, gadc_result, dat.gadc_cmd.gext, + NULL); + } break; + + case GADC_CH_SAMPLE_GET: { + if (dat.gadc_cmd.ch != buf[1]) { + dat.gadc_cmd.gadc_status = GADC_ERR_WRONG_CHANNEL; + } else { + dat.gadc_cmd.gadc_status = GADC_ERR_OK; + } + } break; + + case GADC_CH_CALIBRATE_VDD1A_INTERNAL: + case GADC_CH_CALIBRATE_START: { + dat.gadc_cmd.gadc_status = GADC_ERR_OK; + dat.gadc_cmd.ch = buf[1]; + dat.gadc_cmd.gext = buf[2]; + dat.gadc_cmd.sample_ch = dat.gadc_cmd.ch; + gadc_sample_channel(dat.gadc_cmd.ch, gadc_result, dat.gadc_cmd.gext, + NULL); + } break; + + case GADC_CH_CALIBRATE_GET: { + if (dat.gadc_cmd.ch != buf[1]) { + dat.gadc_cmd.gadc_status = GADC_ERR_WRONG_CHANNEL; + } + } break; + + case GADC_CH_CALIBRATION_SETTING: { + struct { + uint8_t op; + float volt; + float ratio; + } __PACKED *payload = (void *)buf; + + volt4cli = payload->volt; + ratio4cli = payload->ratio; + dat.gadc_cmd.gadc_status = GADC_ERR_OK; + } break; + + default: { + dat.gadc_cmd.gadc_status = GADC_ERR_INVALID_OP; + } break; + } +} + +static void vendor_gadc_cmp_handler(uint8_t **bufptr, uint32_t *size) +{ + switch (dat.gadc_cmd.gadc_op) { + case GADC_CH_SAMPLE_START: + case GADC_CH_CALIBRATE_VDD1A_INTERNAL: + case GADC_CH_CALIBRATE_START: + case GADC_CH_CALIBRATION_SETTING: { + init_hci_event(GADC_CMD_OCF, GADC_CMD_OGF, 0, + dat.gadc_cmd.gadc_status, bufptr, size); + } break; + + case GADC_CH_SAMPLE_GET: { + struct hci_evt_para { + float volt; + int16_t raw; + uint32_t curcal; + } __PACKED; + + init_hci_event(GADC_CMD_OCF, GADC_CMD_OGF, + sizeof(struct hci_evt_para), dat.gadc_cmd.gadc_status, bufptr, + size); + struct hci_evt_para *gadc_hcievent_para = + (struct hci_evt_para *)&hcievent_buffer[BASIC_HCI_EVT_CMD_LEN]; + + gadc_hcievent_para->volt = dat.gadc_cmd.ch_volt; + gadc_hcievent_para->raw = dat.gadc_cmd.ch_raw; + gadc_hcievent_para->curcal = dat.gadc_cmd.ch_curcal.value; + } break; + + case GADC_CH_CALIBRATE_GET: { + struct hci_evt_para { + uint32_t newcal; + }; + + init_hci_event(GADC_CMD_OCF, GADC_CMD_OGF, + sizeof(struct hci_evt_para), dat.gadc_cmd.gadc_status, bufptr, + size); + struct hci_evt_para *gadc_hcievent_para = + (struct hci_evt_para *)&hcievent_buffer[BASIC_HCI_EVT_CMD_LEN]; + gadc_hcievent_para->newcal = dat.gadc_cmd.ch_newcal.value; + } break; + + default: { + DEBUG_TRACE("Invalid gadc op: %d", dat.gadc_cmd.gadc_op); + ASSERT_ERR(0); + } + } +} +#endif + +#ifdef CFG_VND_IO_CTRL +static void vendor_io_handler(uint8_t *buf) +{ + dat.io_cmd.op = buf[0]; + dat.io_cmd.io = buf[1]; + dat.io_cmd.par = buf[2]; +} + +// Handle IO control HCI command +static void io_control(void) +{ + switch (dat.io_cmd.op) { + case IO_CMD_OP_SETUP: { + atm_gpio_setup(dat.io_cmd.io); + if (dat.io_cmd.par) { + atm_gpio_set_output(dat.io_cmd.io); + } else { + atm_gpio_set_input(dat.io_cmd.io); + } + } break; + case IO_CMD_OP_READ: { + dat.io_cmd.par = atm_gpio_read_gpio(dat.io_cmd.io); + } break; + case IO_CMD_OP_WRITE: { + atm_gpio_write(dat.io_cmd.io, dat.io_cmd.par); + } break; + default: { + } break; + } +} + +static void vendor_io_cmp_handler(uint8_t **bufptr, uint32_t *size) +{ + init_hci_event(IO_CMD_OCF, IO_CMD_OGF, 1, HCI_EVT_SUCCESS, bufptr, size); + io_control(); + hcievent_buffer[7] = dat.io_cmd.par; +} +#endif + +#ifdef CFG_VND_GPIO_TEST +static bool gpio_self_test_failed; +static bool gpio_self_test(uint8_t input_io, uint8_t output_io) +{ + bool test_pass = true; + + atm_gpio_setup(input_io); + atm_gpio_setup(output_io); +#ifdef PIN_UART1_TX + if ((input_io == PIN_UART1_TX) || (output_io == PIN_UART1_TX)) { +#define _PINMUX_GPIO_SET(inst) PINMUX_GPIO_SET(inst) + _PINMUX_GPIO_SET(PIN2GPIO(PIN_UART1_TX)); + } +#endif + atm_gpio_set_input(input_io); + atm_gpio_set_output(output_io); + atm_gpio_write(output_io, 0); + if (atm_gpio_read_gpio(input_io)) { + test_pass = false; + } + atm_gpio_write(output_io, 1); + if (!atm_gpio_read_gpio(input_io)) { + test_pass = false; + } + atm_gpio_set_input(output_io); +#ifdef PIN_UART1_TX + if ((input_io == PIN_UART1_TX) || (output_io == PIN_UART1_TX)) { + PINMUX_UART_SET(1, TX); + } +#endif + DEBUG_TRACE("input: %d output: %d pass:%d", input_io, output_io, test_pass); + return test_pass; +} + +static void vendor_gpio_self_test_handler(uint8_t *buf) +{ + uint8_t num_pair = buf[0]; + DEBUG_TRACE("num_pair %d", num_pair); + gpio_self_test_failed = false; + for (uint8_t i = 0; i < num_pair; i++) { + uint8_t io_0 = buf[1 + i * 2]; + uint8_t io_1 = buf[2 + i * 2]; + DEBUG_TRACE("GPIO self test Pair_%d: [%d, %d]", i, io_0, io_1); + + if (!gpio_self_test(io_0, io_1) || !gpio_self_test(io_1, io_0)) { + gpio_self_test_failed = true; + } + } +} + +static void vendor_gpio_self_test_cmp_handler(uint8_t **bufptr, uint32_t *size) +{ + init_hci_event(GPIO_SELF_TEST_CMD_OCF, GPIO_SELF_TEST_CMD_OGF, 0, + HCI_EVT_SUCCESS, bufptr, size); + if (gpio_self_test_failed) { + DEBUG_TRACE("gpio_self_test failed"); + SET_HCI_EVT_STATUS(HCI_EVT_ERROR); + } +} +#endif + +#ifdef CFG_VND_MALLOC +static void vendor_malloc_handler(uint8_t *buf) +{ + dat.malloc_cmd.type = buf[0]; + uint32_t u32parm = atm_get_le32(&buf[1]); + if (dat.malloc_cmd.type == MALLOC_ALLOC) { + if (dat.malloc_ctx.malloc_mem) { + dat.malloc_cmd.type = MALLOC_ERR_NO_MEM; + } else { + dat.malloc_ctx.malloc_size = u32parm; + } + } else if (dat.malloc_cmd.type == MALLOC_FREE) { + if (!dat.malloc_ctx.malloc_mem || (void *)u32parm != + dat.malloc_ctx.malloc_mem) { + dat.malloc_cmd.type = MALLOC_ERR_BAD_FREE; + } + } +} + +static void vendor_malloc_cmp_handler(uint8_t **bufptr, uint32_t *size) +{ + init_hci_event(MALLOC_CMD_OCF, MALLOC_CMD_OGF, 0, HCI_EVT_SUCCESS, bufptr, + size); + if (dat.malloc_cmd.type == MALLOC_FREE) { + free(dat.malloc_ctx.malloc_mem); + SET_HCI_EVT_STATUS(HCI_EVT_SUCCESS); + dat.malloc_ctx.malloc_mem = NULL; + } else if (dat.malloc_cmd.type == MALLOC_ALLOC) { + dat.malloc_ctx.malloc_mem = malloc(dat.malloc_ctx.malloc_size); + if (!dat.malloc_ctx.malloc_mem) { + SET_HCI_EVT_STATUS(MALLOC_ERR_NO_MEM); + } else { + init_hci_event(MALLOC_CMD_OCF, MALLOC_CMD_OGF, 4, HCI_EVT_SUCCESS, + bufptr, size); + atm_set_le32(&hcievent_buffer[BASIC_HCI_EVT_CMD_LEN], + (uint32_t)dat.malloc_ctx.malloc_mem); + } + } else { + SET_HCI_EVT_STATUS(dat.malloc_cmd.type); + } +} +#endif + +#ifdef CFG_VND_SYS_MMR +static void vendor_mmr_handler(uint8_t *buf) +{ + memcpy(dat.mmr_cmd.buf, buf, MMR_ADDR_LEN); +} + +static void vendor_mmr_cmp_handler(uint8_t **bufptr, uint32_t *size) +{ + init_hci_event(MM_R_CMD_OCF, MM_R_CMD_OGF, 4, HCI_EVT_SUCCESS, bufptr, + size); + + WRPR_CTRL_SET(CMSDK_PSEQ, WRPR_CTRL__CLK_ENABLE); + uint32_t mmr_data = (*(volatile unsigned int *)(dat.mmr_cmd.value)); + + // Update memory read data into HCI event buffer + memcpy(&hcievent_buffer[BASIC_HCI_EVT_CMD_LEN], &mmr_data, + sizeof(mmr_data)); + + APP_TRACE(" mmr[0x%" PRIx32 "]=0x%" PRIx32, dat.mmr_cmd.value, mmr_data); +} +#endif + +#ifdef CFG_VND_TAG_RD +static void vendor_tagmfg_handler(uint8_t *buf) +{ + dat.tag_cmd.tag_id = *buf; +} + +static void vendor_tagmfg_cmp_handler(uint8_t **bufptr, uint32_t *size) +{ + // shift to hci event payload start address + nvds_tag_len_t tag_len = NVDS_TAG_MFG_BUFF_LEN - BASIC_HCI_EVT_CMD_LEN; + if (nvds_get(dat.tag_cmd.tag_id, &tag_len, + (uint8_t *)&hcievent_buffer[BASIC_HCI_EVT_CMD_LEN]) != NVDS_OK) { + init_hci_event(TAG_R_CMD_OCF, TAG_R_CMD_OGF, 0, HCI_EVT_ERROR, bufptr, + size); + APP_TRACE(" read fail tag_cmd.tag_id=%d", dat.tag_cmd.tag_id); + } else { + // update HCI EVT payload length + init_hci_event(TAG_R_CMD_OCF, TAG_R_CMD_OGF, tag_len, HCI_EVT_SUCCESS, + bufptr, size); + + APP_TRACE(" read okay real tag_cmd.tag_id=%d tag_len=%d", + dat.tag_cmd.tag_id, tag_len); + } +} +#endif + +#ifdef CFG_VND_DBG_MMR +static void vendor_dbg_rd_mem_handler(uint8_t *buf) +{ + dat.dbg_rd_mem_cmd.start_addr = atm_get_le32(buf); + dat.dbg_rd_mem_cmd.type = buf[4]; + dat.dbg_rd_mem_cmd.length = buf[5]; +} + +static void read_memory(uint8_t *buffer) +{ + uint32_t i = 0; + uint32_t value = 0; + + /* Check type of data to be read */ + if (dat.dbg_rd_mem_cmd.type == 8) { + /* Read bytes */ + for (i = 0; i < dat.dbg_rd_mem_cmd.length; i++) { + /* Read value at @ set in Param1+i */ + buffer[i] = + *(volatile uint8_t *)(dat.dbg_rd_mem_cmd.start_addr + i); + } + } else if (dat.dbg_rd_mem_cmd.type == 16) { + for (i = 0; i < dat.dbg_rd_mem_cmd.length; i += 2) { + /* Read value at @ set in Param1+i */ + value = (*(volatile uint16_t *)(dat.dbg_rd_mem_cmd.start_addr + i)); + + /* store in the buffer */ + atm_set_le16(&buffer[i], value); + } + } else if (dat.dbg_rd_mem_cmd.type == 32) { + /* Read 32 bit word */ + for (i = 0; i < dat.dbg_rd_mem_cmd.length; i += 4) { + value = (*(volatile uint32_t *)(dat.dbg_rd_mem_cmd.start_addr + i)); + + /* store in the buffer */ + atm_set_le32(&buffer[i], value); + } + } +} + +static void vendor_dbg_rd_mem_cmp_handler(uint8_t **bufptr, uint32_t *size) +{ + if (!check_evt_unsupport(bufptr)) { + // stack support + APP_TRACE("stack support"); + return; + } + + // stack not support, implement here + APP_TRACE("stack not support"); + + if ((dat.dbg_rd_mem_cmd.length == 0) || (dat.dbg_rd_mem_cmd.length > 128)) { + init_hci_event(RD_MEM_CMD_OCF, RD_MEM_CMD_OGF, 0, HCI_EVT_ERR_INVD_PARA, + bufptr, size); + } else { + init_hci_event(RD_MEM_CMD_OCF, RD_MEM_CMD_OGF, + 1 + dat.dbg_rd_mem_cmd.length, HCI_EVT_SUCCESS, bufptr, size); + + hcievent_buffer[BASIC_HCI_EVT_CMD_LEN] = dat.dbg_rd_mem_cmd.length; + + read_memory(&hcievent_buffer[BASIC_HCI_EVT_CMD_LEN + 1]); + } +} +#endif + +#ifdef CFG_VND_DBG_MMW +static void vendor_dbg_wr_mem_handler(uint8_t *buf) +{ + dat.dbg_wr_mem_cmd.start_addr = atm_get_le32(buf); + dat.dbg_wr_mem_cmd.type = buf[4]; + dat.dbg_wr_mem_cmd.length = buf[5]; + memcpy(dat.dbg_wr_mem_cmd.data, &buf[6], buf[5]); +} + +static void write_memory(void) +{ + uint32_t i = 0; + + /* Check type of data to be written */ + if (dat.dbg_wr_mem_cmd.type == 8) { + /* Write bytes */ + for (i = 0; i < dat.dbg_wr_mem_cmd.length; i++) { + /* Set value type at @ Param1 */ + *(volatile uint8_t *)(dat.dbg_wr_mem_cmd.start_addr + i) = + dat.dbg_wr_mem_cmd.data[i]; + } + } else if (dat.dbg_wr_mem_cmd.type == 16) { + /* Write 16 bits word */ + for (i = 0; i < dat.dbg_wr_mem_cmd.length; i += 2) { + /* Set value type at @ Param1 */ + *(volatile uint16_t *)(dat.dbg_wr_mem_cmd.start_addr + i) = + atm_get_le16(&dat.dbg_wr_mem_cmd.data[i]); + } + } else if (dat.dbg_wr_mem_cmd.type == 32) { + /* Write 32 bit word */ + for (i = 0; i < dat.dbg_wr_mem_cmd.length; i += 4) { + /* Set value at @ Param1 */ + *(volatile uint32_t *)(dat.dbg_wr_mem_cmd.start_addr + i) = + atm_get_le32(&dat.dbg_wr_mem_cmd.data[i]); + } + } +} + +static void vendor_dbg_wr_mem_cmp_handler(uint8_t **bufptr, uint32_t *size) +{ + if (!check_evt_unsupport(bufptr)) { + // stack support + APP_TRACE("stack support"); + return; + } + + // stack not support, implement here + APP_TRACE("stack not support"); + init_hci_event(WR_MEM_CMD_OCF, WR_MEM_CMD_OGF, 0, HCI_EVT_SUCCESS, bufptr, + size); + + if ((dat.dbg_wr_mem_cmd.length == 0) || + (dat.dbg_wr_mem_cmd.length > 128)) { + SET_HCI_EVT_STATUS(HCI_EVT_ERR_INVD_PARA); + } else { + write_memory(); + } +} +#endif + +#ifdef CFG_VND_PSM +static void vendor_psm_handler(uint8_t *buf) +{ + dat.psm_cmd.psm_mode = buf[0]; +} + +static uint8_t cmd_psm; + +static void vendor_psm_cmp_handler(uint8_t **bufptr, uint32_t *size) +{ + init_hci_event(PSM_CMD_OCF, PSM_CMD_OGF, 1, HCI_EVT_SUCCESS, bufptr, size); + uint8_t pgse = pseq_get_sleep_enable(); + hcievent_buffer[7] = pgse; + if ((dat.psm_cmd.psm_mode > pgse) || + ((pgse == PSM_SOC_OFF) && (dat.psm_cmd.psm_mode == PSM_HIBERNATE))) { + cmd_psm = PSM_NONE; + SET_HCI_EVT_STATUS(HCI_EVT_ERROR); + return; + } + + switch (dat.psm_cmd.psm_mode) { + case PSM_NONE: { + cmd_psm = dat.psm_cmd.psm_mode; + uart_set_park_state(UART_UNPARK); + } break; + + case PSM_DEEP: + case PSM_RETAIN: + case PSM_RETAIN_DROP: + case PSM_HIBERNATE: + case PSM_SOC_OFF: { + cmd_psm = dat.psm_cmd.psm_mode; + uart_set_park_state(UART_PARK); + } break; + + default: { + cmd_psm = PSM_NONE; + SET_HCI_EVT_STATUS(HCI_EVT_ERROR); + } break; + }; +} +#endif + +#ifdef CFG_VND_COREMARK +static void vendor_coremark_handler(uint8_t *buf) +{ + dat.coremark_cmd.iterations = atm_get_le16(buf); + dat.coremark_cmd.clock_mhz = buf[2]; +} + +static void vendor_coremark_cmp_handler(uint8_t **bufptr, uint32_t *size) +{ + uint32_t wdog; + uint16_t score; + uint8_t err; + + /* + * we could get WDOG while doing coremark tests depending on iterations + * and time spent here. + * safer to set wdog to some high value and reset after coremark finishes + */ + DEBUG_TRACE("Adjusting wdog to %d seconds..", POWER_MEASURE_WDOG_SECONDS); + DEBUG_TRACE("coremark:iterations=%d, freq=%d", dat.coremark_cmd.iterations, + dat.coremark_cmd.clock_mhz); + wdog = POWER_MEASURE_WDOG_SECONDS * atm_bp_clock_get(); + CMSDK_WATCHDOG->LOCK = WDOG_LOCK_MAGIC; + CMSDK_WATCHDOG->LOAD = wdog; + CMSDK_WATCHDOG->LOCK = 0; + + if (!coremark(dat.coremark_cmd.iterations, dat.coremark_cmd.clock_mhz, + &score)) { + err = HCI_EVT_ERROR; + } else { + err = HCI_EVT_SUCCESS; + atm_set_le16(&hcievent_buffer[BASIC_HCI_EVT_CMD_LEN], score); + } + // reset wdog to original value +#define WDOG_INIT_TIMEOUT 0x0a000000 // ~10s + CMSDK_WATCHDOG->LOCK = WDOG_LOCK_MAGIC; + CMSDK_WATCHDOG->LOAD = WDOG_INIT_TIMEOUT; + CMSDK_WATCHDOG->LOCK = 0; + + init_hci_event(COREMARK_CMD_OCF, COREMARK_CMD_OGF, COREMARK_RTN_VALUE_LEN, + err, bufptr, size); +} +#endif + +#if defined(CFG_VND_WFI) || defined(CFG_VND_NO_CLOCK) || \ + defined(CFG_VND_WHILE_ONE) +#define INT_REG_NUM 4 +/* + * This routine does all the preparation work for power measure + * functions like wfi, no_clock, while_one + * place certain modules in shutdown or disabled state, adjust bp_freq + * also set wdog to large enough value so power measure tests complete + * without any interruption + * + * CAUTION Some of these tests and settings may leave the system + * in a unrecoverable or indeterminate state. + * A hard pwd reset may be required to recover. + * These are intended for power measure tests only and power measure + * tests do issue a pwd reset upon every test. + */ +static void power_measure_prologue_work(uint16_t power_config_mode, + uint8_t bp_freq) +{ + uint32_t wdog, freq; + + // shutdown ble52_mdm block if needed + if (power_config_mode & PWR_BLE52_DISABLE) { + DEBUG_TRACE("Turning off BLE52 HCLK..."); + CMSDK_CLKRSTGEN_NONSECURE->USER_CLK_GATE_FORCE_ON = 0; + } + + // Disable MDM clock if needed + if (power_config_mode & PWR_MDM_CLK_DISABLE) { + DEBUG_TRACE("Disabling MDM clock..."); + CMSDK_CLKRSTGEN_NONSECURE->USER_CLK_DISABLES = + CLKRSTGEN_USER_CLK_DISABLES__MDM_RIF__WRITE(1); + } + + // shutdown rram if needed + if (power_config_mode & PWR_RRAM_SD) { + DEBUG_TRACE("Shuting down rram..."); + CMSDK_AT_PRRF_NONSECURE->RRAM_MEM_CONFIG = 0; + // Place RRAM in shutdown + WRPR_CTRL_SET(CMSDK_PSEQ_NONSECURE, WRPR_CTRL__CLK_ENABLE); + { + CMSDK_PSEQ_NONSECURE->OVERRIDES3 = 0; + CMSDK_PSEQ_NONSECURE->OVERRIDES3 = + PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC__MASK | + PSEQ_OVERRIDES3__OVERRIDE_RRAM_POC_VAL__MASK; + } + WRPR_CTRL_SET(CMSDK_PSEQ_NONSECURE, WRPR_CTRL__CLK_DISABLE); + } + + /* + * For these tests, we want to stay in there forever. + * A reset to the device is the way out, and test scripts will reset + * when required. Usually, it is within few seconds, after capturing + * necessary power measurement data + * make certain we are not interrupted while in these state + */ + DEBUG_TRACE("Disabling all interrupts..."); + for (int i = 0; i < INT_REG_NUM; i++) { + uint32_t ise = NVIC->ISER[i]; + if (ise) { + NVIC->ICER[i] = ise; + } + } + + // Adjust bp_freq if necessary + if (power_config_mode & PWR_BP_FREQ_ADJUST) { + if (!bp_freq) { + // a value 0 implies it is 0.5Mhz + freq = 500000; + } else { + freq = bp_freq * 1000000; + } + + DEBUG_TRACE("Adjusting bp_freq to %" PRIu32, freq); + atm_bp_clock_set(freq); + } + + /* + * set wdog to some large value, so it doesnt fire while in + * power measurement OR just in case if someone forgot to reset/pwd + */ + DEBUG_TRACE("Adjusting wdog to %d seconds..", POWER_MEASURE_WDOG_SECONDS); + wdog = POWER_MEASURE_WDOG_SECONDS * atm_bp_clock_get(); + CMSDK_WATCHDOG->LOCK = WDOG_LOCK_MAGIC; + CMSDK_WATCHDOG->LOAD = wdog; + CMSDK_WATCHDOG->LOCK = 0; +} +#endif + +#ifdef CFG_VND_WFI +static void vendor_wfi_handler(uint8_t *buf) +{ + dat.power_cmd.power_cfg = atm_get_le16(buf); + dat.power_cmd.bp_freq = buf[2]; +} + +static void vendor_wfi_cmp_handler(uint8_t **bufptr, uint32_t *size) +{ + uint32_t save_freq; + uint8_t err; + DEBUG_TRACE("wfi cmp handler: power_cfg=%x, bp_freq=%d", + dat.power_cmd.power_cfg, dat.power_cmd.bp_freq); + + save_freq = atm_bp_clock_get(); + power_measure_prologue_work(dat.power_cmd.power_cfg, dat.power_cmd.bp_freq); + + // do the wfi + WFI(); + + // This code below may not execute + // restore bp_freq here just in case. + DEBUG_TRACE("Restoring bp_freq to %" PRIu32, save_freq); + atm_bp_clock_set(save_freq); + DEBUG_TRACE("Finished doing wfi ..."); + err = HCI_EVT_SUCCESS; + init_hci_event(WFI_CMD_OCF, WFI_CMD_OGF, 0, err, bufptr, size); +} +#endif + +#ifdef CFG_VND_NO_CLOCK +static void vendor_no_clock_handler(uint8_t *buf) +{ + dat.power_cmd.power_cfg = atm_get_le16(buf); + dat.power_cmd.bp_freq = buf[2]; +} + +static void vendor_no_clock_cmp_handler(uint8_t **bufptr, uint32_t *size) +{ + uint32_t save_freq; + uint8_t err; + + DEBUG_TRACE("no_clock cmp handler: power_cfg=%x, bp_freq=%d", + dat.power_cmd.power_cfg, dat.power_cmd.bp_freq); + + save_freq = atm_bp_clock_get(); + power_measure_prologue_work(dat.power_cmd.power_cfg, dat.power_cmd.bp_freq); + +#define PARIS_PINMUX_DBG 160 + // bring out clk_mpc on debug bus (Gen_MDMCLK) + // want it on P11 + // dbg.din6 [12] + WRPRPINS_DBG_CTRL__DBG_ENABLE__MODIFY(CMSDK_WRPR0_NONSECURE->DBG_CTRL, 1); + WRPRPINS_DBG_CTRL__DBG_SHFT__MODIFY(CMSDK_WRPR0_NONSECURE->DBG_CTRL, 1); + WRPRPINS_DBG_CTRL__DBG_SEL__MODIFY(CMSDK_WRPR0_NONSECURE->DBG_CTRL, 6); + WRPRPINS_PSEL_C__P11_SEL__MODIFY(CMSDK_WRPR0_NONSECURE->PSEL_C, + PARIS_PINMUX_DBG); + + WRPR_CTRL_SET(CMSDK_PSEQ, WRPR_CTRL__CLK_ENABLE); + { + // Disable MPC + PSEQ_XTAL_BITS1__CLKMPC_EN__CLR(CMSDK_PSEQ_NONSECURE->XTAL_BITS1); + } + WRPR_CTRL_SET(CMSDK_PSEQ, WRPR_CTRL__CLK_DISABLE); + + /* + * should get stuck here forever, below code is for safety completion + */ + DEBUG_TRACE("Finished turning off clock ..."); + // restore bp_freq, just in case + atm_bp_clock_set(save_freq); + err = HCI_EVT_SUCCESS; + atm_set_le16(&hcievent_buffer[BASIC_HCI_EVT_CMD_LEN], 90); + init_hci_event(NO_CLOCK_CMD_OCF, NO_CLOCK_CMD_OGF, 2, err, bufptr, size); +} +#endif + +#ifdef CFG_VND_WHILE_ONE +static void vendor_while_one_handler(uint8_t *buf) +{ + dat.power_cmd.power_cfg = atm_get_le16(buf); + dat.power_cmd.bp_freq = buf[2]; +} + +static void vendor_while_one_cmp_handler(uint8_t **bufptr, uint32_t *size) +{ + DEBUG_TRACE("while_one cmp handler: power_cfg=%x, bp_freq=%d", + dat.power_cmd.power_cfg, dat.power_cmd.bp_freq); + + power_measure_prologue_work(dat.power_cmd.power_cfg, dat.power_cmd.bp_freq); + + // go into forever loop now + while (1) { + } +} +#endif + +static void vendor_exit_vendor_mode_handler(uint8_t *buf) +{ + memset(&dat, 0, sizeof(dat)); +} + +#ifndef CONFIG_SOC_FAMILY_ATM +__FAST +static void exit_deferred_cb(sw_event_id_t event_id, const void *ctx) +{ + APP_TRACE("exit_deferred_cb"); + atm_vendor_exit_hci_vendor_mode(); +} +#endif +static void vendor_exit_vendor_mode_cmp_handler(uint8_t **bufptr, + uint32_t *size) +{ +#ifndef CONFIG_SOC_FAMILY_ATM + init_hci_event(EXIT_VENDOR_CMD_OCF, EXIT_VENDOR_CMD_OGF, 0, + HCI_EVT_SUCCESS, bufptr, size); + + /* let hci event in to uart tx buffer first*/ + sw_event_id_t eid = sw_event_alloc(exit_deferred_cb, NULL); + sw_event_set(eid); +#endif +} + +static struct vendor_handler const vendor_handler_tab[] = { +#ifdef CFG_VND_EN_TXCW + {EN_TXCW_CMD_OCF, EN_TXCW_CMD_OGF, EN_TXCW_CMD_LEN, true, + vendor_entxcw_handler, vendor_entxcw_cmp_handler}, +#endif +#ifdef CFG_VND_CAP + {FREQCAL_CMD_OCF, FREQCAL_CMD_OGF, FREQCAL_CMD_LEN, true, + vendor_freqcal_handler, vendor_freqcal_cmp_handler}, +#endif +#ifdef CFG_VND_SYS_MMR + {MM_R_CMD_OCF, MM_R_CMD_OGF, MM_R_CMD_LEN, true, vendor_mmr_handler, + vendor_mmr_cmp_handler}, +#endif +#ifdef CFG_VND_TAG_RD + {TAG_R_CMD_OCF, TAG_R_CMD_OGF, TAG_R_CMD_LEN, true, vendor_tagmfg_handler, + vendor_tagmfg_cmp_handler}, +#endif +#ifdef CFG_VND_SET_BDDR + {SET_BD_ADDR_CMD_OCF, SET_BD_ADDR_CMD_OGF, SET_BD_ADDR_CMD_LEN, true, + vendor_set_public_bd_addr_handler, + vendor_set_public_bd_addr_cmp_handler}, +#endif +#ifdef CFG_VND_SET_ADV_CH + {SET_ADV_CH_CMD_OCF, SET_ADV_CH_CMD_OGF, SET_ADV_CH_CMD_LEN, true, + vendor_set_adv_ch_handler, vendor_set_adv_ch_cmp_handler}, +#endif +#ifdef CFG_VND_MALLOC + {MALLOC_CMD_OCF, MALLOC_CMD_OGF, MALLOC_CMD_LEN, true, + vendor_malloc_handler, vendor_malloc_cmp_handler}, +#endif +#ifdef CFG_VND_IO_CTRL + {IO_CMD_OCF, IO_CMD_OGF, IO_CMD_LEN, true, vendor_io_handler, + vendor_io_cmp_handler}, +#endif +#ifdef CFG_VND_GADC + {GADC_CMD_OCF, GADC_CMD_OGF, GADC_CMD_LEN, false, vendor_gadc_handler, + vendor_gadc_cmp_handler}, +#endif +#ifdef CFG_VND_PV_TEST + {PV_TEST_CMD_OCF, PV_TEST_CMD_OGF, PV_TEST_CMD_LEN, true, + vendor_enpvtest_handler, vendor_enpvtest_cmp_handler}, +#endif +#ifdef CFG_VND_GPIO_TEST + {GPIO_SELF_TEST_CMD_OCF, GPIO_SELF_TEST_CMD_OGF, GPIO_SELF_TEST_CMD_LEN, + false, vendor_gpio_self_test_handler, + vendor_gpio_self_test_cmp_handler}, +#endif +#ifdef CFG_VND_PSM + {PSM_CMD_OCF, PSM_CMD_OGF, PSM_CMD_LEN, true, vendor_psm_handler, + vendor_psm_cmp_handler}, +#endif +#ifdef CFG_VND_COREMARK + {COREMARK_CMD_OCF, COREMARK_CMD_OGF, COREMARK_CMD_LEN, true, + vendor_coremark_handler, vendor_coremark_cmp_handler}, +#endif +#ifdef CFG_VND_WFI + {WFI_CMD_OCF, WFI_CMD_OGF, WFI_CMD_LEN, true, vendor_wfi_handler, + vendor_wfi_cmp_handler}, +#endif +#ifdef CFG_VND_NO_CLOCK + {NO_CLOCK_CMD_OCF, NO_CLOCK_CMD_OGF, NO_CLOCK_CMD_LEN, true, + vendor_no_clock_handler, vendor_no_clock_cmp_handler}, +#endif +#ifdef CFG_VND_WHILE_ONE + {WHILE_ONE_CMD_OCF, WHILE_ONE_CMD_OGF, WHILE_ONE_CMD_LEN, true, + vendor_while_one_handler, vendor_while_one_cmp_handler}, +#endif +#ifdef CFG_VND_DBG_MMR + {RD_MEM_CMD_OCF, RD_MEM_CMD_OGF, RD_MEM_CMD_LEN, true, + vendor_dbg_rd_mem_handler, vendor_dbg_rd_mem_cmp_handler}, +#endif +#ifdef CFG_VND_DBG_MMW + {WR_MEM_CMD_OCF, WR_MEM_CMD_OGF, WR_MEM_CMD_LEN, false, + vendor_dbg_wr_mem_handler, vendor_dbg_wr_mem_cmp_handler}, +#endif +#ifdef CFG_VND_BLE_REGR + {BLE_REG_RD_CMD_OCF, BLE_REG_RD_CMD_OGF, BLE_REG_RD_CMD_LEN, true, + vendor_dbg_ble_reg_rd_handler, vendor_dbg_ble_reg_rd_cmp_handler}, +#endif +#ifdef CFG_VND_BLE_REGW + {BLE_REG_WR_CMD_OCF, BLE_REG_WR_CMD_OGF, BLE_REG_WR_CMD_LEN, true, + vendor_dbg_ble_reg_wr_handler, vendor_dbg_ble_reg_wr_cmp_handler}, +#endif +#ifdef CFG_VND_PMU_RADIO_REGR + {PMU_RADIO_REG_RD_CMD_OCF, PMU_RADIO_REG_RD_CMD_OGF, + PMU_RADIO_REG_RD_CMD_LEN, true, vendor_dbg_pmu_radio_reg_rd_handler, + vendor_dbg_pmu_radio_reg_rd_cmp_handler}, +#endif +#ifdef CFG_VND_PMU_RADIO_REGW + {PMU_RADIO_REG_WR_CMD_OCF, PMU_RADIO_REG_WR_CMD_OGF, + PMU_RADIO_REG_WR_CMD_LEN, true, vendor_dbg_pmu_radio_reg_wr_handler, + vendor_dbg_pmu_radio_reg_wr_cmp_handler}, +#endif + {EXIT_VENDOR_CMD_OCF, EXIT_VENDOR_CMD_OGF, EXIT_VENDOR_CMD_LEN, true, + vendor_exit_vendor_mode_handler, vendor_exit_vendor_mode_cmp_handler}, +}; + +#ifndef CONFIG_SOC_FAMILY_ATM +static struct vendor_handler const *find_vend_handler(uint8_t *op_len_buf) +{ + for (uint32_t i = 0; i < ARRAY_LEN(vendor_handler_tab); i++) { + struct vendor_handler const *hdlr = &vendor_handler_tab[i]; + if ((hdlr->ocf == op_len_buf[0]) && (hdlr->ogf == op_len_buf[1]) && + (!hdlr->check_cmd_len || (hdlr->cmd_len == op_len_buf[2]))) { + return hdlr; + } + } + + return NULL; +} + +// return true if having HCI vendor command for MFG +static bool fake_hcievent(void) +{ + return (curr_vnd_hdlr != NULL); +} + +// check HCI event/command status payload if having HCI vendor command for MFG +static bool check_evt_opcode(uint8_t const *bufptr) +{ + uint8_t evt_type = bufptr[1]; + // check hci packet and event type + if ((*bufptr != H4_MSG_LC_HCI_EVT) || + ((evt_type != HCI_EVT_CMD_CPM) && (evt_type != HCI_EVT_CMD_CS))) { + return false; + } + + // offset for hci command complete event + uint8_t ofg_offset = 5; + uint8_t ocf_offset = 4; + + if (evt_type == HCI_EVT_CMD_CS) { + // offset for hci command status event + ofg_offset = 6; + ocf_offset = 5; + } + + // check OGF and OCF + if ((bufptr[ofg_offset] == MFG_OGF_SB1) && + (bufptr[ocf_offset] >= MFG_OCF_EN_TXCW) && + (bufptr[ocf_offset] < MFG_OCF_END)) { + return true; + } + + if ((bufptr[ofg_offset] == VND_OGF_SB1)) { + if ((bufptr[ocf_offset] == RD_MEM_CMD_OCF) || + (bufptr[ocf_offset] == WR_MEM_CMD_OCF) || + (bufptr[ocf_offset] == BLE_REG_RD_CMD_OCF) || + (bufptr[ocf_offset] == BLE_REG_WR_CMD_OCF) || + (bufptr[ocf_offset] == PMU_RADIO_REG_RD_CMD_OCF) || + (bufptr[ocf_offset] == PMU_RADIO_REG_WR_CMD_OCF)) { + return true; + } + } + + return false; +} + +// check HCI event payload if having HCI Reset Command +static bool check_evt_reset(uint8_t const *bufptr) +{ + // check hci packet and event type + if ((*bufptr != H4_MSG_LC_HCI_EVT) || (*(bufptr + 1) != HCI_EVT_CMD_CPM)) { + return false; + } + + // Is HCI_RESET command + if (*((uint16_t const *)(bufptr + BASIC_HCI_EVT_HD_LEN)) == HCI_RESET_U16) { + return true; + } + return false; +} + +// Restore to default +static void reset_stage(void) +{ + curr_vnd_hdlr = NULL; +} + +// Hook uart driver's event function for HCI command parser +__FAST +static rep_vec_err_t vendor_uart_event(uint32_t buf_size, uint8_t *buf) +{ + static uint8_t hci_op_len_buf[HCI_CMD_HDR_LEN]; + ASSERT_ERR(buf); + ASSERT_ERR(buf_size); + + if ((rx_state == HCIV_STATE_RX_INIT) && + (buf_size == HCI_TRANSPORT_HDR_LEN) && (*buf == H4_MSG_LC_HCI_CMD)) { + rx_state = HCIV_STATE_RX_START; + } else if ((rx_state == HCIV_STATE_RX_START) && + (buf_size == HCI_CMD_HDR_LEN)) { + // Update HCI OpCode and Length + memcpy(hci_op_len_buf, buf, HCI_CMD_HDR_LEN); + + // Update HCI command's payload length + // payload length is zero then move to next state + uint8_t hci_payload_len = *(buf + HCI_CMD_LEN_POS); + rx_state = hci_payload_len ? HCIV_STATE_RX_HDR : HCIV_STATE_RX_PAYL; + + } else if (rx_state == HCIV_STATE_RX_HDR) { + rx_state = HCIV_STATE_RX_PAYL; + } + + if (rx_state == HCIV_STATE_RX_PAYL) { + rx_state = HCIV_STATE_RX_INIT; + + curr_vnd_hdlr = find_vend_handler(hci_op_len_buf); + if (curr_vnd_hdlr) { + curr_vnd_hdlr->cmd_hdlr(buf); + } + } + + return (RV_NEXT); +} + +// Hook uart driver's write function for HCI Event overwrite +__FAST +static rep_vec_err_t vendor_uart_write(uint8_t **bufptr, uint32_t *size) +{ + if ((*size == BASIC_HCI_EVT_HD_LEN) && (**bufptr == H4_MSG_LC_HCI_EVT) && + (*(*bufptr + HCI_EVT_CODE_POS) == HCI_HW_ERR_EVT_CODE)) { + APP_TRACE("HCI out of sync"); + rx_state = HCIV_STATE_RX_INIT; + reset_stage(); + } else if ((*size == BASIC_HCI_EVT_CMD_LEN) && (internal_reset == true) && + check_evt_reset(*bufptr)) { + // change interval HCI reset event to AG Ready Evt + memcpy(ag_ready_evt, AG_READY_EVT, sizeof(AG_READY_EVT)); + *bufptr = ag_ready_evt; + *size = sizeof(AG_READY_EVT); + internal_reset = false; + APP_TRACE(" AG Ready"); + } else if (check_evt_opcode(*bufptr) && fake_hcievent()) { + // Overwrite HCI Event + curr_vnd_hdlr->cmd_cmp_hdlr(bufptr, size); + reset_stage(); + } else { + reset_stage(); + } + return (RV_NEXT); +} + +#ifdef CFG_VND_PSM +__FAST static rep_vec_err_t +vendor_specific_prevent_ble_sleep(bool *prevent) +{ + if (cmd_psm >= PSM_DEEP) { + return RV_NEXT; + } + + *prevent = true; + return (RV_DONE); +} + +__FAST static rep_vec_err_t +vendor_specific_prevent_ret(bool *prevent, int32_t *pseq_dur, int32_t ble_dur) +{ + if (cmd_psm >= PSM_RETAIN) { + return RV_NEXT; + } + + *prevent = true; + return RV_DONE; +} + +__FAST static rep_vec_err_t +vendor_specific_prevent_hib(bool *prevent, int32_t *pseq_dur, int32_t ble_dur) +{ + if (cmd_psm >= PSM_HIBERNATE) { + return RV_NEXT; + } + + *prevent = true; + return RV_DONE; +} +#endif + +static rep_vec_err_t vendor_specific_plf_reset(void) +{ + uart_deinit(); + return (RV_NEXT); +} + +#ifdef FORCE_TX_PWR +static rep_vec_err_t atm_vendor_tx_pwr_init(void) +{ + DEBUG_TRACE("default Tx power: %d dBm", FORCE_TX_PWR); + atm_ble_set_rftest_txpwr(FORCE_TX_PWR); + atm_ble_set_txpwr_max(FORCE_TX_PWR); + return RV_NEXT; +} +#endif +#endif // CONFIG_SOC_FAMILY_ATM + +#ifdef CONFIG_SOC_FAMILY_ATM +static int sys_vendor_init(void) +{ +#ifdef CFG_RUNTIME_EN_HCI_VENDOR + if (is_boot_uninit()) { + LOG_DBG("is_boot_uninit, clear hci_vendor_en flag"); + hci_vendor_en = false; + return 0; + } + + if (!hci_vendor_en) { + LOG_DBG("!hci_vendor_en"); + return 0; + } +#endif + atm_uart_init(); + return 0; +} +SYS_INIT(sys_vendor_init, APPLICATION, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); + +void atm_vendor_init(void) +{ +#ifdef CFG_RUNTIME_EN_HCI_VENDOR + if (!hci_vendor_en) { + LOG_DBG("!hci_vendor_en"); + return; + } +#endif + atm_vendor_handler_register(vendor_handler_tab, + ARRAY_SIZE(vendor_handler_tab)); + atm_hci_init(); +} +#else // CONFIG_SOC_FAMILY_ATM +#ifdef CFG_RUNTIME_EN_HCI_VENDOR +__attribute__((constructor)) +static void +vendor_specific_init_constructor(void) +{ + if (is_boot_uninit()) { + APP_TRACE("is_boot_uninit, clear hci_vendor_en flag"); + hci_vendor_en = false; + return; + } + + if (!hci_vendor_en) { + APP_TRACE("!hci_vendor_en"); + return; + } + + uart_init(); +#else +void vendor_specific_init(void) +{ + hci_vendor_en = true; +#endif + + RV_PLF_UART_RX_BUFFER_ADD(vendor_uart_event); + RV_PLF_UART_WRITE_ADD(vendor_uart_write); + RV_PLF_RESET_ADD_LAST(vendor_specific_plf_reset); + +#ifdef CFG_VND_PSM + RV_PREVENT_BLE_SLEEP_ADD(vendor_specific_prevent_ble_sleep); + RV_PLF_PREVENT_RETENTION_ADD(vendor_specific_prevent_ret); + RV_PLF_PREVENT_HIBERNATION_ADD(vendor_specific_prevent_hib); + + DEBUG_TRACE("sleep_enable: %#x", pseq_get_sleep_enable()); +#endif + +#ifdef FORCE_TX_PWR + RV_APPM_INIT_ADD(atm_vendor_tx_pwr_init); +#endif + + ag_ready_evt = malloc(sizeof(AG_READY_EVT)); +} +#endif // CONFIG_SOC_FAMILY_ATM + +void atm_vendor_enter_hci_vendor_mode(void) +{ + hci_vendor_en = true; +#ifdef CONFIG_SOC_FAMILY_ATM + sys_reboot(RESET_NO_ERROR); +#else + platform_reset(RESET_NO_ERROR); +#endif +} + +void atm_vendor_exit_hci_vendor_mode(void) +{ + hci_vendor_en = false; +#ifdef CONFIG_SOC_FAMILY_ATM + sys_reboot(RESET_NO_ERROR); +#else + platform_reset(RESET_NO_ERROR); +#endif +} + +bool atm_vendor_get_hci_vendor_en(void) +{ + return hci_vendor_en; +} diff --git a/ATM33xx-5/lib/atm_vendor/atm_vendor.h b/ATM33xx-5/lib/atm_vendor/atm_vendor.h new file mode 100644 index 0000000..61f33c8 --- /dev/null +++ b/ATM33xx-5/lib/atm_vendor/atm_vendor.h @@ -0,0 +1,80 @@ +/** + ******************************************************************************* + * + * @file atm_vendor.h + * + * @brief Header File - HCI Vendor Command + * + * Copyright (C) Atmosic 2020-2024 + * + ******************************************************************************* + */ + +#pragma once + +#ifdef CONFIG_SOC_FAMILY_ATM +#include "compiler.h" +#endif + +/** + * @defgroup ATM_BTFM_VEND HCI Vendor Command + * @ingroup ATM_BTFM_PROC + * @brief HCI Vendor Command + * + * This module contains the necessary API to deal with vendor command. + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#define AG_VERSION 7 +#define AG_RF_POWER_MAX 7 + +#ifdef CHK_BUILD +#define APP_TRACE DEBUG_TRACE +#else +#define APP_TRACE(fmt, ...) DEBUG_TRACE_COND(0, fmt, ##__VA_ARGS__) +#endif + +#ifdef GPIO_CTRL +void ag_gpio_init(void); +#endif + +/** + * @brief Enter hci vendor mode + */ +__NORETURN void atm_vendor_enter_hci_vendor_mode(void); + +/** + * @brief Exit hci vendor mode + */ +__NORETURN void atm_vendor_exit_hci_vendor_mode(void); + +/** + * @brief Get current hci vendor mode enable status + * @return Hci vendor mode enable status + */ +bool atm_vendor_get_hci_vendor_en(void); + +#ifdef CONFIG_SOC_FAMILY_ATM +/** + * @brief Enable and initial HCI vendor + */ +void atm_vendor_init(void); +#else +#ifndef CFG_RUNTIME_EN_HCI_VENDOR +/** + * @brief Enable and initial HCI vendor + */ +void vendor_specific_init(void); +#endif +#endif // CONFIG_SOC_FAMILY_ATM + +#ifdef __cplusplus +} +#endif + +///@} diff --git a/ATM33xx-5/lib/atm_vendor/atm_vendor_internal.h b/ATM33xx-5/lib/atm_vendor/atm_vendor_internal.h new file mode 100644 index 0000000..3f68c55 --- /dev/null +++ b/ATM33xx-5/lib/atm_vendor/atm_vendor_internal.h @@ -0,0 +1,556 @@ +/** + ******************************************************************************* + * + * @file atm_vendor_internal.h + * + * @brief Header File - HCI Vendor Command internal definitions + * + * Copyright (C) Atmosic 2024 + * + ******************************************************************************* + */ + +#pragma once + +#ifdef CFG_VND_GADC +#include "gadc.h" +#endif + +#ifdef CFG_VND_SET_BDDR +#include "ble_common.h" +#endif + +/** + * @addtogroup ATM_BTFM_VEND HCI Vendor Command + * @ingroup ATM_BTFM_PROC + * @brief HCI Vendor Command + * + * This module contains the necessary definitions to deal with vendor command + * internally. + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#define MFG_OGF 0x3E +#define MFG_OGF_SB1 (MFG_OGF << 2) // 0xF8 + +#define VND_OGF 0x3F +#define VND_OGF_SB1 (VND_OGF << 2) // 0xFC + +typedef enum { + MFG_OCF_LED = 0x01, + MFG_OCF_EN_TXCW, + MFG_OCF_CAP, + MFG_OCF_MMR, + MFG_OCF_TAG_R, + MFG_OCF_SET_BDADDR, + MFG_OCF_SET_ADV_CH, + MFG_OCF_OTP_PUSH, + MFG_OCF_MALLOC, + MFG_OCF_IO, + MFG_OCF_GADC, + MFG_OCF_PV_TEST, + MFG_OCF_EXIT_VENDOR, + MFG_OCF_GPIO_SELF_TEST, + MFG_OCF_PSM, + MFG_OCF_COREMARK, + MFG_OCF_WFI, + MFG_OCF_NO_CLOCK, + MFG_OCF_WHILE_ONE, + + MFG_OCF_END +} MFG_OCF; + +typedef enum { + VND_OCF_RD_MEM = 0x01, + VND_OCF_WR_MEM, + VND_OCF_BLE_REG_RD = 0x30, + VND_OCF_BLE_REG_WR, + VND_OCF_PMU_RADIO_REG_RD, + VND_OCF_PMU_RADIO_REG_WR, + + VND_OCF_END +} VND_OCF; + +// Enable Tx CW mode (0xF802) +#define EN_TXCW_CMD_OCF MFG_OCF_EN_TXCW +#define EN_TXCW_CMD_OGF MFG_OGF_SB1 +#define EN_TXCW_CMD_LEN 0x01 + +// set 16MXtal cap. value (0xF803) +#define FREQCAL_CMD_OCF MFG_OCF_CAP +#define FREQCAL_CMD_OGF MFG_OGF_SB1 +#define FREQCAL_CMD_LEN 0x01 + +// generic memory read (0xF804) +#define MM_R_CMD_OCF MFG_OCF_MMR +#define MM_R_CMD_OGF MFG_OGF_SB1 +#define MM_R_CMD_LEN 0x04 + +// generic Flash NVDS Tag read (0xF805) +#define TAG_R_CMD_OCF MFG_OCF_TAG_R +#define TAG_R_CMD_OGF MFG_OGF_SB1 +#define TAG_R_CMD_LEN 0x01 + +// set public bd addr (0xF806) +#define SET_BD_ADDR_CMD_OCF MFG_OCF_SET_BDADDR +#define SET_BD_ADDR_CMD_OGF MFG_OGF_SB1 +#define SET_BD_ADDR_CMD_LEN 0x06 + +// set advertising channels (0xF807) +#define SET_ADV_CH_CMD_OCF MFG_OCF_SET_ADV_CH +#define SET_ADV_CH_CMD_OGF MFG_OGF_SB1 +#define SET_ADV_CH_CMD_LEN 0x02 + +// OTP Push (0xF808) +#define OTP_PUSH_CMD_OCF MFG_OCF_OTP_PUSH +#define OTP_PUSH_CMD_OGF MFG_OGF_SB1 +#define OTP_PUSH_CMD_LEN 0x05 + +// Malloc (0xF809) +#define MALLOC_CMD_OCF MFG_OCF_MALLOC +#define MALLOC_CMD_OGF MFG_OGF_SB1 +#define MALLOC_CMD_LEN 0x05 + +// IO Control (0xF80A) +#define IO_CMD_OCF MFG_OCF_IO +#define IO_CMD_OGF MFG_OGF_SB1 +#define IO_CMD_LEN 0x03 +#define IO_CMD_OP_SETUP 0x00 +#define IO_CMD_OP_READ 0x01 +#define IO_CMD_OP_WRITE 0x02 + +// GADC (0xF80B) +#define GADC_CMD_OCF MFG_OCF_GADC +#define GADC_CMD_OGF MFG_OGF_SB1 +#define GADC_CMD_LEN 0x03 +#define GADC_CMD_ALT_LEN 0x09 + +// Enable PV test (0xF80C) +#define PV_TEST_CMD_OCF MFG_OCF_PV_TEST +#define PV_TEST_CMD_OGF MFG_OGF_SB1 +#define PV_TEST_CMD_LEN 0x02 + +// Exit HCI vendor mode (0xF80D) +#define EXIT_VENDOR_CMD_OCF MFG_OCF_EXIT_VENDOR +#define EXIT_VENDOR_CMD_OGF MFG_OGF_SB1 +#define EXIT_VENDOR_CMD_LEN 0x00 + +// GPIO Self test (0xF80E) +#define GPIO_SELF_TEST_CMD_OCF MFG_OCF_GPIO_SELF_TEST +#define GPIO_SELF_TEST_CMD_OGF MFG_OGF_SB1 +#define GPIO_SELF_TEST_CMD_LEN 0x00 + +// Power Save Mode (0xF80F) +#define PSM_CMD_OCF MFG_OCF_PSM +#define PSM_CMD_OGF MFG_OGF_SB1 +#define PSM_CMD_LEN 0x01 + +#define PSM_NONE SLEEP_ENABLE_NONE +#define PSM_DEEP SLEEP_ENABLE_DEEP +#define PSM_RETAIN SLEEP_ENABLE_RETAIN +#define PSM_RETAIN_DROP SLEEP_ENABLE_RETAIN_DROP +#define PSM_HIBERNATE SLEEP_ENABLE_HIBERNATE +#define PSM_SOC_OFF SLEEP_ENABLE_SOC_OFF + +// Coremark (0xF810) +#define COREMARK_CMD_OCF MFG_OCF_COREMARK +#define COREMARK_CMD_OGF MFG_OGF_SB1 +#define COREMARK_CMD_LEN 0x03 +#define COREMARK_RTN_VALUE_LEN 2 + +/* + * CAUTION + * WFI, NO_CLOCK, WHILE_ONE will leave the system in usable state, + * require pwd reset to recover. These commands and operations are + * intended only for internal debug use, not recommended for others + */ +// WFI (0xF811) +#define WFI_CMD_OCF MFG_OCF_WFI +#define WFI_CMD_OGF MFG_OGF_SB1 +#define WFI_CMD_LEN 0x03 + +// NO_CLOCK (0xF812) +#define NO_CLOCK_CMD_OCF MFG_OCF_NO_CLOCK +#define NO_CLOCK_CMD_OGF MFG_OGF_SB1 +#define NO_CLOCK_CMD_LEN 0x03 + +// WHILE_ONE (0xF813) +#define WHILE_ONE_CMD_OCF MFG_OCF_WHILE_ONE +#define WHILE_ONE_CMD_OGF MFG_OGF_SB1 +#define WHILE_ONE_CMD_LEN 0x03 + +// bit Defines for WFI, NO_CLOCK power config, used in power measure tests +#define PWR_BP_FREQ_ADJUST 0x0001 +#define PWR_BLE52_DISABLE 0x0002 +#define PWR_MDM_CLK_DISABLE 0x0004 +#define PWR_RRAM_SD 0x0008 + +// set wdog to a long enough value, so power measure tests complete +#define POWER_MEASURE_WDOG_SECONDS 30 +#define WDOG_LOCK_MAGIC 0x1ACCE551 + +// Read memory (0xFC01) +#define RD_MEM_CMD_OCF VND_OCF_RD_MEM +#define RD_MEM_CMD_OGF VND_OGF_SB1 +#define RD_MEM_CMD_LEN 0x06 + +// Write memory (0xFC02) +#define WR_MEM_CMD_OCF VND_OCF_WR_MEM +#define WR_MEM_CMD_OGF VND_OGF_SB1 +#define WR_MEM_CMD_LEN 0x00 + +// BLE register Read (0xFC30) +#define BLE_REG_RD_CMD_OCF VND_OCF_BLE_REG_RD +#define BLE_REG_RD_CMD_OGF VND_OGF_SB1 +#define BLE_REG_RD_CMD_LEN 0x02 + +// BLE register write (0xFC31) +#define BLE_REG_WR_CMD_OCF VND_OCF_BLE_REG_WR +#define BLE_REG_WR_CMD_OGF VND_OGF_SB1 +#define BLE_REG_WR_CMD_LEN 0x06 + +// PMU, RADIO register Read (0xFC32) +#define PMU_RADIO_REG_RD_CMD_OCF VND_OCF_PMU_RADIO_REG_RD +#define PMU_RADIO_REG_RD_CMD_OGF VND_OGF_SB1 +#define PMU_RADIO_REG_RD_CMD_LEN 0x09 + +// PMU, RADIO register write (0xFC33) +#define PMU_RADIO_REG_WR_CMD_OCF VND_OCF_PMU_RADIO_REG_WR +#define PMU_RADIO_REG_WR_CMD_OGF VND_OGF_SB1 +#define PMU_RADIO_REG_WR_CMD_LEN 0x0D + +#define HCI_OP_LEN_SIZE 3 +#define HCI_CMD_LEN_POS (HCI_OP_LEN_SIZE - 1) +#define HCI_EVT_CODE_POS 1 +#define HCI_EVT_LEN_POS 2 +#define HCI_EVT_STATUS_POS 6 +#define HCI_EVT_CS_STATUS_POS 3 +#define HCI_EVT_NOC 5 +#define HCI_EVT_CMD_CPM 0x0E +#define HCI_EVT_CMD_CS 0x0F +#define HCI_EVT_VENDOR 0xFF +#define HCI_RESET_U16 0x0c03 +#define HCI_EVT_SUCCESS 0 +#define HCI_EVT_ERROR 1 +#define HCI_EVT_ERR_INVD_PARA 18 +#define BASIC_HCI_EVT_HD_LEN 4 +#define BASIC_HCI_EVT_CMD_LEN 7 +#define MMR_ADDR_LEN 4 + +#define NVDS_TAG_MFG 0xAF +#define NVDS_TAG_MFG_BUFF_LEN 256 + +struct vendor_handler { + uint8_t ocf; + uint8_t ogf; + uint8_t cmd_len; + bool check_cmd_len; + void (*cmd_hdlr)(uint8_t *buf); + void (*cmd_cmp_hdlr)(uint8_t **bufptr, uint32_t *size); +}; + +typedef enum { + SEVT_DUT_READY, +} HCI_EVT_SUB_EVT_TYPE; + +typedef union { + uint8_t op; + uint8_t io; + uint8_t val; +} IO_CTRL_CMD; + +// HCI_vendor RX states +enum H4TL_STATE_RX { + // init state + HCIV_STATE_RX_INIT, + // receive message type + HCIV_STATE_RX_START, + // receive message header + HCIV_STATE_RX_HDR, + // receive (rest of) message payload + HCIV_STATE_RX_PAYL, +}; + +// gadc +enum gadc_op { + GADC_CH_SAMPLE_START, + GADC_CH_SAMPLE_GET, + GADC_CH_CALIBRATE_START, + GADC_CH_CALIBRATE_GET, + GADC_CH_CALIBRATE_VDD1A_INTERNAL, + GADC_CH_CALIBRATION_SETTING, +}; + +enum gadc_err { + GADC_ERR_OK = HCI_EVT_SUCCESS, + GADC_ERR_INVALID_OP, + GADC_ERR_WRONG_CALI_SETTING, + GADC_ERR_WRONG_CHANNEL, +}; + +enum malloc_type { + MALLOC_FREE, + MALLOC_ALLOC, + MALLOC_ERR_NO_MEM, + MALLOC_ERR_BAD_FREE, +}; + +#ifdef CFG_VND_EN_TXCW +#define EN_TXCW_CMD 1 +typedef struct { + uint8_t enabled; +} en_txsw_cmd_t; +#else +#define EN_TXCW_CMD 0 +#endif + +#ifdef CFG_VND_CAP +#define FREQCAL_CMD 1 +typedef struct { + uint8_t rx_byte; +} freqcal_cmd_t; +#else +#define FREQCAL_CMD 0 +#endif + +#ifdef CFG_VND_SYS_MMR +#define MM_R_CMD 1 +typedef struct { + union { + uint8_t buf[MMR_ADDR_LEN]; + uint32_t value; + }; +} mm_r_cmd_t; +#else +#define MM_R_CMD 0 +#endif + +#ifdef CFG_VND_PV_TEST +#define PV_TEST_CMD 1 +typedef struct { + uint16_t pv_test_times; +} pv_test_cmd_t; +#else +#define PV_TEST_CMD 0 +#endif + +#ifdef CFG_VND_GPIO_TEST +#define GPIO_SELF_TEST_CMD 1 +#else +#define GPIO_SELF_TEST_CMD 0 +#endif + +#ifdef CFG_VND_PSM +#define PSM_CMD 1 +typedef struct { + uint8_t psm_mode; +} psm_cmd_t; +#else +#define PSM_CMD 0 +#endif + +#ifdef CFG_VND_GADC +#define GADC_CMD 1 +typedef struct { + enum gadc_err gadc_status; + enum gadc_op gadc_op; + uint8_t ch; + uint8_t sample_ch; + uint8_t gext; + int16_t ch_raw; + int16_t vdd1a_raw; + float ch_volt; + struct gadc_cal_s ch_curcal; + struct gadc_cal_s ch_newcal; + __ieee_float_shape_type ch_newgain; + int16_t ch_newoffset_x2; +} gadc_cmd_t; +#else +#define GADC_CMD 0 +#endif + +#ifdef CFG_VND_IO_CTRL +#define IO_CMD 1 +typedef struct { + uint8_t op; + uint8_t io; + bool par; +} io_cmd_t; +#else +#define IO_CMD 0 +#endif + +#ifdef CFG_VND_TAG_RD +#define TAG_R_CMD 1 +typedef struct { + uint8_t tag_id; +} tag_r_cmd_t; +#else +#define TAG_R_CMD 0 +#endif + +#ifdef CFG_VND_SET_BDDR +#define SET_BD_ADDR_CMD 1 +typedef struct { + uint8_t bd_addr[BLE_BDADDR_LEN]; +} set_bd_addr_cmd_t; +#else +#define SET_BD_ADDR_CMD 0 +#endif + +#ifdef CFG_VND_SET_ADV_CH +#define SET_ADV_CH_CMD 1 +#else +#define SET_ADV_CH_CMD 0 +#endif + +#ifdef CFG_VND_MALLOC +#define MALLOC_CMD 1 +typedef struct { + enum malloc_type type; +} malloc_cmd_t; + +typedef struct { + union { + size_t malloc_size; + void *malloc_mem; + }; +} malloc_ctx_t; +#else +#define MALLOC_CMD 0 +#endif + +#ifdef CFG_VND_DBG_MMR +#define RD_MEM_CMD 1 +typedef struct { + // Start address to read + uint32_t start_addr; + // Access size + uint8_t type; + // Length to read + uint8_t length; +} rd_mem_cmd_t; +#else +#define RD_MEM_CMD 0 +#endif + +#ifdef CFG_VND_DBG_MMW +#define WR_MEM_CMD 1 +typedef struct { + // Start address to read + uint32_t start_addr; + // Access size + uint8_t type; + // length of buffer + uint8_t length; + // data of 128 bytes length + uint8_t data[128]; +} wr_mem_cmd_t; +#else +#define WR_MEM_CMD 0 +#endif + +#ifdef CFG_VND_BLE_REGR +#define BLE_REG_RD_CMD 1 +typedef struct { + // register address + uint16_t reg_addr; +} ble_reg_rd_cmd_t; +#else +#define BLE_REG_RD_CMD 0 +#endif + +#ifdef CFG_VND_BLE_REGW +#define BLE_REG_WR_CMD 1 +typedef struct { + // register address + uint16_t reg_addr; + // register value + uint32_t reg_value; +} ble_reg_wr_cmd_t; +#else +#define BLE_REG_WR_CMD 0 +#endif + +#ifdef CFG_VND_PMU_RADIO_REGR +#define PMU_RADIO_REG_RD_CMD 1 +typedef struct { + // register block address + uint32_t reg_block; + // register address + uint32_t reg_addr; + uint8_t is_pmu; +} pmu_radio_reg_rd_cmd_t; +#else +#define PMU_RADIO_REG_RD_CMD 0 +#endif + +#ifdef CFG_VND_PMU_RADIO_REGW +#define PMU_RADIO_REG_WR_CMD 1 +typedef struct { + // register block address + uint32_t reg_block; + // register address + uint32_t reg_addr; + uint32_t reg_value; + uint8_t is_pmu; +} pmu_radio_reg_wr_cmd_t; +#else +#define PMU_RADIO_REG_WR_CMD 0 +#endif + +#ifdef CFG_VND_COREMARK +#define COREMARK_CMD 1 +typedef struct { + // iterations + uint16_t iterations; + // MCU clock, unit: MHz + uint8_t clock_mhz; +} coremark_cmd_t; +#else +#define COREMARK_CMD 0 +#endif + +#if (defined(CFG_VND_WFI) || defined(CFG_VND_NO_CLOCK) || \ + defined(CFG_VND_WHILE_ONE)) +typedef struct { + // power config, various bit settings for adjusting bp_clock, + // ble52_disable, mdm_clk_disable, rram_sd + uint16_t power_cfg; + // MCU clock, unit: MHz + // value 0 to be interpreted as 0.5 Mhz + uint8_t bp_freq; +} power_cmd_t; +#endif + +#ifdef CFG_VND_WFI +#define WFI_CMD 1 +#define wfi_cmd_t power_cmd_t +#else +#define WFI_CMD 0 +#endif + +#ifdef CFG_VND_NO_CLOCK +#define NO_CLOCK_CMD 1 +#define no_lock_cmd_t power_cmd_t +#else +#define NO_CLOCK_CMD 0 +#endif + +#ifdef CFG_VND_WHILE_ONE +#define WHILE_ONE_CMD 1 +#define while_one_cmd_t power_cmd_t +#else +#define WHILE_ONE_CMD 0 +#endif + +#ifdef __cplusplus +} +#endif + +///@} diff --git a/ATM33xx-5/lib/sec_service/sec_service.c b/ATM33xx-5/lib/sec_service/sec_service.c new file mode 100644 index 0000000..2d14ab4 --- /dev/null +++ b/ATM33xx-5/lib/sec_service/sec_service.c @@ -0,0 +1,134 @@ +/** + ****************************************************************************** + * + * @file sec_service.c + * + * @brief Secure services + * + * Copyright (C) Atmosic 2022-2024 + * + ****************************************************************************** + */ +#ifdef CFG_NO_SPE +#define SECURE_MODE +#endif +#include "arch.h" +#include "compiler.h" +#include +#include +#include +#include "sec_service.h" +#include "at_tz_ppc.h" +#if VERIFY_ATMWSTK +#include +#include "atm_sha2.h" +#define _STR(s) #s +#define STR(s) _STR(s) +#include STR(ATMWSTK_SHA_H) +#endif + +#ifdef MCUBOOT_RD_PROTECT +#include "sec_assert.h" +#include "rram_rom_prot.h" +#include "mcuboot_slot_partitions.h" +#ifdef DEBUG_MCUBOOT_RD_PROTECT +#include "sec_cache.h" +#endif +#endif + +#if (!defined(SECURE_MODE) && !defined(CFG_NO_SPE)) +#error "sec_service is a secure-only library." +#endif + +bool mem_check_has_access(void const *ptr, uint32_t len, bool ns_caller, + bool write) +{ + int flags = (write) ? CMSE_MPU_READWRITE : CMSE_MPU_READ; + + if (ns_caller) { + CONTROL_Type ctrl; + ctrl.w = __TZ_get_CONTROL_NS(); + if (ctrl.b.nPRIV) { + flags |= CMSE_MPU_UNPRIV; + } + flags |= CMSE_NONSECURE; + } + + return cmse_check_address_range(CONTEXT_VOID_P(ptr), len, flags); +} + +#if VERIFY_ATMWSTK +bool verify_atmwstk(void) +{ + static uint32_t const atmwstk_sha[SHA256_DIG_WORDS] = ATMWSTK_SHA; + uint8_t digest[SHA256_DIG_LEN]; + atm_sha256_params_t const sha256_params = { + .mode = ATM_SHA256_SHA_MODE, + .byte_endianess = ATM_SHA256_ENDIANESS_BIG, + .digest_endianess = ATM_SHA256_ENDIANESS_LITTLE, + }; + if (atm_sha256_init(&sha256_params) != ATM_SHA256_RES_SUCCESS) { + return false; + } + + if (atm_sha256_update_pio((void *)ATMWSTK_START, ATMWSTK_SIZE) != + ATM_SHA256_RES_SUCCESS) { + atm_sha256_disable(); + return false; + } + atm_sha256_final(digest); + atm_sha256_disable(); + if (memcmp(digest, atmwstk_sha, SHA256_DIG_LEN)) { + return false; + } + return true; +} +#endif + +#ifdef MCUBOOT_RD_PROTECT +// read protect MCUBOOT image partition +static void rd_protect_mcuboot(void) +{ +#ifdef DEBUG_MCUBOOT_RD_PROTECT + ICACHE_FLUSH(); + uint32_t mcuboot0 = *(uint32_t *)MCUBOOT_START_ADDRESS; + uint32_t mcuboot1 = *(uint32_t *)(MCUBOOT_START_ADDRESS + 4); + printf("MCUBOOT data 0x%" PRIx32 " 0:0x%" PRIx32 " 1:0x%" PRIx32 "\n", + (uint32_t)MCUBOOT_START_ADDRESS, mcuboot0, mcuboot1); +#endif // DEBUG_MCUBOOT_RD_PROTECT + uint32_t mcuboot_addr = + RRAM_ADDR_TO_OFFSET((uint32_t)MCUBOOT_START_ADDRESS); + uint32_t mcuboot_size = MCUBOOT_SIZE; + bool rdprot_s = rram_prot_sticky_read_disable(mcuboot_addr, mcuboot_size); + SEC_ASSERT(rdprot_s); +#ifdef DEBUG_MCUBOOT_RD_PROTECT + printf("Rd lock MCUBOOT: 0x%" PRIx32 " l:0x%" PRIx32 "\n", mcuboot_addr, + mcuboot_size); +#endif +#ifdef DEBUG_MCUBOOT_RD_PROTECT + ICACHE_FLUSH(); + // these should not match + uint32_t mcuboot_prot0 = *(uint32_t *)MCUBOOT_START_ADDRESS; + uint32_t mcuboot_prot1 = *(uint32_t *)(MCUBOOT_START_ADDRESS + 4); + printf("AFTER LOCK data 0x%" PRIx32 " 0:0x%" PRIx32 " 1:0x%" PRIx32 "\n", + (uint32_t)MCUBOOT_START_ADDRESS, mcuboot_prot0, mcuboot_prot1); + SEC_ASSERT(mcuboot_prot0 != mcuboot0); + SEC_ASSERT(mcuboot_prot1 != mcuboot1); +#endif // DEBUG_MCUBOOT_RD_PROTECT +} +#endif // MCUBOOT_RD_PROTECT + +void sec_lockdown(void) +{ +#ifdef MCUBOOT_RD_PROTECT + rd_protect_mcuboot(); +#endif +} + +// Default PPC configuration function +static void __sec_ppc_cfg(void) +{ + at_tz_ppc_init_ns_cfg(); +} + +void sec_ppc_cfg(void) __attribute__ ((weak, alias("__sec_ppc_cfg"))); diff --git a/ATM33xx-5/lib/sec_service/sec_service.h b/ATM33xx-5/lib/sec_service/sec_service.h new file mode 100644 index 0000000..9a59a51 --- /dev/null +++ b/ATM33xx-5/lib/sec_service/sec_service.h @@ -0,0 +1,79 @@ +/** + ****************************************************************************** + * + * @file sec_service.h + * + * @brief Secure Services + * + * Copyright (C) Atmosic 2022-2024 + * + ****************************************************************************** + */ + +#pragma once + +/** + * @defgroup SEC_SERVICE Secure Services + * @ingroup SPE_API + * @brief Library functions for secure services + * @{ + */ + +#ifdef SECURE_PROC_ENV +#define __SPE_NSC __attribute__((cmse_nonsecure_entry)) __attribute__((used)) +#else +#define __SPE_NSC +#endif + +#ifndef VERIFY_ATMWSTK +#if defined(ATMWSTK) && (defined(CFG_PLF_DEBUG) || defined(USE_SECURE_BOOT)) +#define VERIFY_ATMWSTK 1 +#else +#define VERIFY_ATMWSTK 0 +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @brief checks if caller has access to passed address range + * + * @param ptr ptr to address in question + * @param len length of region + * @param ns_caller true if from NS space + * @param write check for write access + * @return true if access is OK, false otherwise + */ +bool mem_check_has_access(void const *ptr, uint32_t len, bool ns_caller, + bool write); + +#if VERIFY_ATMWSTK +/** + * @brief Verify the integrity of the ATMWSTK + * @return true if stack verifies, else false + */ +bool verify_atmwstk(void); +#endif + +/** + * @brief Lock down security settings for the platform + */ +void sec_lockdown(void); + + +/** + * @brief Perform secure PPC configuration. + * + * @note, weak alias, override-able via SPE extensions + */ +void sec_ppc_cfg(void); + +#ifdef __cplusplus +} +#endif + +/// @} diff --git a/ATM33xx-5/noinit.ld b/ATM33xx-5/noinit.ld new file mode 100644 index 0000000..52e69a5 --- /dev/null +++ b/ATM33xx-5/noinit.ld @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2023-2024 Atmosic + * + * SPDX-License-Identifier: Apache-2.0 + */ + + *(".uninit*") diff --git a/ATM33xx-5/ramfunc-section.ld b/ATM33xx-5/ramfunc-section.ld new file mode 100644 index 0000000..04c22b3 --- /dev/null +++ b/ATM33xx-5/ramfunc-section.ld @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2023-2024 Atmosic + * + * SPDX-License-Identifier: Apache-2.0 + */ + + *(".data_text*") diff --git a/CMakeLists.txt b/CMakeLists.txt new file mode 100644 index 0000000..7d1495e --- /dev/null +++ b/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2021-2024 Atmosic +# +# SPDX-License-Identifier: Apache-2.0 + +if (CONFIG_SOC_FAMILY_ATM) + +add_subdirectory(${CONFIG_SOC}) + +endif () diff --git a/Kconfig b/Kconfig new file mode 100644 index 0000000..51b9fb0 --- /dev/null +++ b/Kconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2023-2024 Atmosic +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_ATM33xx_5 + +rsource "ATM33xx-5/drivers/Kconfig" +rsource "ATM33xx-5/lib/Kconfig" + +endif # SOC_ATM33xx_5 + +rsource "tools/Kconfig" + +config ATM_ENABLE_NSC_EXAMPLE + bool "Enable NSC example function for extending SPE" + default n + +config ATM_PLF_DEBUG + bool "Debugging for low level platform drivers" + default y + depends on PRINTK diff --git a/tools/Kconfig b/tools/Kconfig new file mode 100644 index 0000000..cf7a104 --- /dev/null +++ b/tools/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2024 Atmosic +# +# SPDX-License-Identifier: Apache-2.0 + +config GEN_PARTITION_INFO + bool "Generate partition info" + default y + +config GEN_PARTITION_INFO_SCRIPT + string "Generate partition info script path" + default "${ZEPHYR_BASE}/../modules/hal/atmosic/tools/scripts/gen_atm_partition_info.py" diff --git a/tools/scripts/atm_openocd.py b/tools/scripts/atm_openocd.py new file mode 100644 index 0000000..0fab99b --- /dev/null +++ b/tools/scripts/atm_openocd.py @@ -0,0 +1,177 @@ +''' +@file atm_openocd.py + +@brief Helper file for Atmosic openocd + +Copyright (C) Atmosic 2024 +''' +import contextlib +import glob +import os +from pathlib import Path +import platform +import subprocess + +def get_atm_plat_dir_from_board(board): + """Generates the partial platform path from a specific board + + Returns: + str: partial platform path + """ + try: + # if a revision is passed, strip it before continuing + board,_ = board.split("@") + except: + board = board + # if a ns board is passed, strip before continuing + if board.endswith('_ns'): + board = board[:-3] + if "ATMEVK-33" in board: + return "ATM33xx-5" + if "ATMEVK-34" in board: + plat = "ATM34xx" + rev = board.split("-")[-1] + return f"{plat}/rev-{rev}" + + + +@contextlib.contextmanager +def _temp_environ(update_dict): + """create a temp env context manager + """ + env = os.environ + update = update_dict or {} + + try: + env.update(update) + yield + finally: + [env.pop(i) for i in update] + +def get_atm_openocd(): + """Retrieves Atmosic openocd executable and seach path. + + Returns: + openocd executable and search path + """ + # Unfortunately the env var ZEPHYR_MODULES is only defined during + # Zephyr CMake builds... so we have to derive that from ZEPHYR_BASE + zephyr_modules = os.path.join(os.path.dirname( + os.path.abspath(os.environ['ZEPHYR_BASE'])), 'modules') + atm_openocd_base = os.path.join( + zephyr_modules, 'hal', 'atmosic_lib', 'tools', 'openocd') + openocd_search = os.path.join(atm_openocd_base, 'tcl') + openocd = None + openocd_search = None + if atm_openocd_base is not None: + plat = platform.system() + if plat.startswith('MSYS'): + plat = 'Windows' + openocd = os.path.join(atm_openocd_base, 'bin', plat, 'openocd') + openocd_search = os.path.join(atm_openocd_base, 'tcl') + print("Using ATM OpenOCD '{}'".format(openocd)) + return (openocd, openocd_search) + + +def get_atm_openocd_cfg(board): + """Returns the correct openocd.cfg for a given Atmosic platform. + + Args: + board (str): board of atmosic platform + + Returns: + str: path to openocd.cfg + """ + # Unfortunately the env var ZEPHYR_MODULES is only defined during + # Zephyr CMake builds... so we have to derive that from ZEPHYR_BASE + zephyr_modules = os.path.join(os.path.dirname( + os.path.abspath(os.environ['ZEPHYR_BASE'])), 'modules') + + atm_plat_dir = get_atm_plat_dir_from_board(board) + def_path = os.path.join(zephyr_modules, 'hal', 'atmosic_lib', atm_plat_dir, 'openocd', '*openocd.cfg') + try: + default = glob.glob(def_path, recursive=True)[0] + # even if glob succeeds, sanity check file exists + if os.path.exists(default): + return default + return None + except: + # glob raises exception when nothing is found + return None + + +class AtmOpenOCD(): + + def __init__(self, board, device, jlink, openocd_bin=None, openocd_search=None, openocd_cfg=None) -> None: + atm_openocd_bin, atm_openocd_search = get_atm_openocd() + + if not openocd_bin: + self.openocd_bin = atm_openocd_bin + else: + self.openocd_bin = openocd_bin + + if not openocd_search: + self.openocd_search = atm_openocd_search + else: + self.openocd_search = openocd_search + + if self.openocd_bin is None: + raise RuntimeError("Could not find Openocd executable") + if self.openocd_search is None: + raise RuntimeError("Could not find Openocd search directory.") + + if not openocd_cfg: + self.openocd_cfg = get_atm_openocd_cfg(board) + else: + self.openocd_cfg = openocd_cfg + + if self.openocd_cfg is None: + raise RuntimeError("Could not find openocd.cfg file") + + self.device = device + if jlink: + self.swdif = "JLINK" + ser_name = "JLINK_SERIAL" + else: + self.swdif = "FTDI" + ser_name = "SYDNEY_SERIAL" + + self.env_dict = { + "SWDIF": self.swdif, + ser_name: str(self.device) + } + + @property + def base_cmd(self): + return [self.openocd_bin] + ['-s', os.path.dirname(self.openocd_cfg)] + \ + ['-s', self.openocd_search] + ['-f', self.openocd_cfg] + + def execute_cmd(self, cmds, env_var={}): + """Executes openocd command on device + Args: + cmd (List[str]): open ocd command to run + env_var (optional): dictionary of environmental commands to add to cmd + + Returns: + Tuple(returncode, stdout and stderr) of command + """ + exec_env = dict(self.env_dict) + exec_env.update(env_var) + openocd_cmds = ["-c " + s for s in cmds] + + with _temp_environ(exec_env): + call = subprocess.run(self.base_cmd + ['-c init'] + + openocd_cmds + ['-c exit'], + check=True, + capture_output=True) + + return (call.returncode, call.stdout, call.stderr) + + def reset_target(self): + """Issues `reset_target` on device + Args: + device (str): device jlink serial + base_openocd_cmd (str): base openocd command + """ + return self.execute_cmd(["release_reset", "sleep 100", "set_normal_boot"], + env_var={"FTDI_BENIGN_BOOT": '1', "FTDI_HARD_RESET": '1'}) diff --git a/tools/scripts/atm_otp/__init__.py b/tools/scripts/atm_otp/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/tools/scripts/atm_otp/atm_otp.py b/tools/scripts/atm_otp/atm_otp.py new file mode 100644 index 0000000..7cf2b95 --- /dev/null +++ b/tools/scripts/atm_otp/atm_otp.py @@ -0,0 +1,207 @@ +''' +@file atm_otp.py + +@brief Atmosic OTP Managment + +Copyright (C) Atmosic 2024 +''' + +import textwrap + +class AtmOTP(): + def __init__(self, name, idx, size=1, value=0, bit_fields=[]) -> None: + self.name = name + self.idx = idx + if size < 1: + raise RuntimeError("OTP must be at least 1 bit long") + self.size = size + self.value = value + + # bit_fields is an optional sub-naming of individual bits. + # If passed, then they need to match size of OTP + if len(bit_fields) and len(bit_fields) != self.size: + raise RuntimeError( + "total size of OTP must match length of bit_fields if provided") + self.bit_fields = bit_fields + + @property + def end_idx(self): + return (self.idx + self.size) + + def get_field(self, name): + try: + idx = self.bit_fields.index(name) + return (self.value >> idx) & 0x1 + except: + raise RuntimeError("Field does not exist!") + + def get_idx(self, idx): + if idx < self.size: + return (self.value >> idx) & 0x1 + raise RuntimeError(f"index ({idx}) not available in {self.name}") + + @property + def stat_str(self): + """Returns string of stats of OTP. + + Does not include information regarding value of the OTP + """ + return f"{self.name} [{self.idx}{'-' + str(self.end_idx) if self.size > 1 else ''}]" + + @property + def pprint_str(self): + pprint_str = str(self) + if len(self.bit_fields): + bits_str = "" + for i, bit_field in enumerate(self.bit_fields): + bits_str += f"{bit_field}: {(self.value >> i) & 0x1}".ljust(23) + pprint_str += "\n" + \ + textwrap.fill(bits_str, width=55, + initial_indent=" ", subsequent_indent=" ") + return pprint_str + + def pprint(self): + print(self.pprint_str) + + def __str__(self) -> str: + # +2 is to account for '0b' + bin_repr_size = self.size + 2 + return f"{self.stat_str}: {format(self.value, f'#0{bin_repr_size}b')}" + + +class AtmOTPArray(): + otp_array = [] + + def __init__(self, bits=b'\x00\x00\x00\x00\x00\x00\x00\x00', size=64) -> None: + self.value = int.from_bytes(bits, byteorder="little") + self.size = size + self.populate_otp() + + def populate_otp(self): + for otp in self.otp_array: + otp.value = (self.value >> otp.idx) & ((1 << otp.size) - 1) + + def get_otp_group_by_name(self, name) -> AtmOTP: + if "." in name: + name, _ = name.split(".") + try: + return next(filter(lambda p: p.name == name, self.__class__.otp_array)) + except: + raise RuntimeError("OTP does not exist") + + def get_otp_group_by_idx(self, idx) -> AtmOTP: + try: + return next(filter(lambda p: p.idx <= idx < p.end_idx, self.__class__.otp_array)) + except: + raise RuntimeError("OTP does not exist") + + def get_otp_group_and_idx(self, val): + try: + idx = int(val) + otp = self.get_otp_group_by_idx(idx) + return (otp, idx - otp.idx) + except: + name = val + sub = None + if "." in name: + name, sub = name.split(".") + otp = self.get_otp_group_by_name(name) + if sub is None: + if otp.size > 1: + return (otp, None) + return (otp, 0) + try: + idx = int(sub) + return (otp, idx) + except: + return (otp, otp.bit_fields.index(sub)) + + def get_otp_bits(self, val): + otp, idx = self.get_otp_group_and_idx(val) + + if idx is None: + return format(otp.value, f'#0{otp.size + 2}b') + return bin(otp.get_idx(idx)) + + def __str__(self): + pstr = f"OTP: {hex(self.value)}\n" + for otp in self.otp_array: + pstr += otp.pprint_str + "\n" + return pstr + + @property + def otp_array_str(self): + pstr = "" + for otp in self.otp_array: + pstr += f"{otp.stat_str}\n" + return pstr + + def print_otp_array(self): + print(self.otp_array_str) + + +class Atmx3_OTPArray(AtmOTPArray): + otp_array = [ + AtmOTP("NABG_TRIM_LATCH", 0, 9), + AtmOTP("USE_LDO_LATCH", 9), + AtmOTP("DISABLE_CHPU_LATCH", 10), + AtmOTP("HARV_DISABLED_LATCH", 11), + AtmOTP("RECT_CTUNE_LATCH", 12, 3), + AtmOTP("INTERNAL_SPARE_LATCH", 15, 4), + AtmOTP("DISABLE_XTAL32K_LATCH", 19), + AtmOTP("NOIND_LATCH", 20), + AtmOTP("DISABLE_VDDIOGEN_LATCH", 21), + AtmOTP("DISABLE_VDDGEN_LATCH", 22), + AtmOTP("DISABLE_5V_LATCH", 23), + AtmOTP("VBATT_LEVEL_LATCH", 24), + AtmOTP("BATT_TYPE_LATCH", 25, 2), + AtmOTP("VBATT_GOOD_LATCH", 27, 3), + AtmOTP("VBATT_BROWNOUT_LATCH", 30, 7), + AtmOTP("MPPT_TYPE_LATCH", 37, 2), + AtmOTP("DISABLE_RFHARV_LATCH", 39), + AtmOTP("VHARV_START_LATCH", 40, 2), + AtmOTP("VSTORE_GOOD_LATCH", 42, 2), + AtmOTP("VSTORE_MAX_LATCH", 44, 3), + AtmOTP("RRAM_WRITE_LOCK", 48, 7, bit_fields=[ + "BOOT_BLOCK_0", "BOOT_BLOCK_1", "BOOT_BLOCK_2", "BOOT_BLOCK_3", "PROTECTED_DATA", "SECURE_COUNTERS", "PRIVATE_KEY_STORAGE"]), + AtmOTP("SEC_DBG_CONFIG", 60, 2, bit_fields=[ + "DEBUG_DISABLED", "DEBUG_SECURED"]), + AtmOTP("RRAM_JTAG_BYPASS", 62), + ] + + def __init__(self, bits=b'\x00\x00\x00\x00\x00\x00\x00\x00', size=64) -> None: + super().__init__(bits, size) + + +class Atm34_OTPArray(AtmOTPArray): + otp_array = [ + AtmOTP("NABG_TRIM_LATCH", 0, 9), + AtmOTP("USE_LDO_LATCH", 9), + AtmOTP("DISABLE_CHPU_LATCH", 10), + AtmOTP("HARV_DISABLED_LATCH", 11), + AtmOTP("RECT_CTUNE_LATCH", 12, 3), + AtmOTP("INTERNAL_SPARE_LATCH", 15, 4), + AtmOTP("DISABLE_XTAL32K_LATCH", 19), + AtmOTP("NOIND_LATCH", 20), + AtmOTP("DISABLE_VDDIOGEN_LATCH", 21), + AtmOTP("DISABLE_VDDGEN_LATCH", 22), + AtmOTP("DISABLE_5V_LATCH", 23), + AtmOTP("VBATT_LEVEL_LATCH", 24), + AtmOTP("BATT_TYPE_LATCH", 25, 2), + AtmOTP("VBATT_GOOD_LATCH", 27, 3), + AtmOTP("VBATT_BROWNOUT_LATCH", 30, 7), + AtmOTP("MPPT_TYPE_LATCH", 37, 2), + AtmOTP("DISABLE_RFHARV_LATCH", 39), + AtmOTP("VHARV_START_LATCH", 40, 2), + AtmOTP("VSTORE_GOOD_LATCH", 42, 2), + AtmOTP("VSTORE_MAX_LATCH", 44, 3), + AtmOTP("RRAM_WRITE_LOCK", 48, 7, bit_fields=[ + "BOOT_BLOCK_0", "BOOT_BLOCK_1", "BOOT_BLOCK_2", "BOOT_BLOCK_3", "PROTECTED_DATA", "SECURE_COUNTERS", "PRIVATE_KEY_STORAGE"]), + AtmOTP("UART1_RX_DISABLE", 56), + AtmOTP("SEC_DBG_CONFIG", 60, 2, bit_fields=[ + "DEBUG_DISABLED", "DEBUG_SECURED"]), + AtmOTP("RRAM_JTAG_BYPASS", 62), + ] + + def __init__(self, bits=b'\x00\x00\x00\x00\x00\x00\x00\x00', size=64) -> None: + super().__init__(bits, size) diff --git a/tools/scripts/atm_otp/test_atm_otp.py b/tools/scripts/atm_otp/test_atm_otp.py new file mode 100644 index 0000000..f7a18f9 --- /dev/null +++ b/tools/scripts/atm_otp/test_atm_otp.py @@ -0,0 +1,92 @@ +''' +@file test_atm_otp.py + +@brief OTP Managment Unit tests + +Copyright (C) Atmosic 2024 +''' +import unittest +import atm_otp + + +class TestAtmOTPMethods(unittest.TestCase): + """Test AtmOTP class""" + + def test_variables_are_set_correctly(self): + otp = atm_otp.AtmOTP("OTP_NAME", 0, 1) + self.assertTrue(otp.idx == 0) + self.assertTrue(otp.end_idx == 1) + otp = atm_otp.AtmOTP("OTP_NAME", 2, 4) + self.assertTrue(otp.idx == 2) + self.assertTrue(otp.size == 4) + self.assertTrue(otp.end_idx == 6) + + def test_field_access(self): + otp = atm_otp.AtmOTP("OTP_A", 7, 4, value=0x1, bit_fields=[ + "sub_bit_0", "sub_bit_1", "sub_bit_2", "sub_bit_3",]) + self.assertEqual(otp.get_field("sub_bit_0"), 1) + self.assertEqual(otp.get_idx(0), 1) + + otp = atm_otp.AtmOTP("OTP_A", 7, 4, value=0x5, bit_fields=[ + "sub_bit_0", "sub_bit_1", "sub_bit_2", "sub_bit_3",]) + self.assertEqual(otp.get_field("sub_bit_2"), 1) + self.assertEqual(otp.get_field("sub_bit_0"), 1) + self.assertEqual(otp.get_idx(0), 1) + self.assertEqual(otp.get_idx(2), 1) + + def test_error_when_bit_fields_wrong_size(self): + self.assertRaises(RuntimeError, atm_otp.AtmOTP, "OTP_A", 7, 4, value=0x5, bit_fields=[ + "sub_bit_1", "sub_bit_2", "sub_bit_3",]) + + def test_print_functional(self): + otp = atm_otp.AtmOTP("OTP_A", 7, 4, value=0x5, bit_fields=[ + "sub_bit_0", "sub_bit_1", "sub_bit_2", "sub_bit_3",]) + print(otp) + otp.pprint() + + +class TestAtmOTPArrayMethods(unittest.TestCase): + """Test AtmOTPArray class""" + + def test_variables_are_initialized(self): + otpArray = atm_otp.Atmx3_OTPArray() + self.assertEqual(otpArray.size, 64, + "Verify Array defaults to correct size") + self.assertEqual(otpArray.value, 0, "Verify value defaults to 0") + + otpArray = atm_otp.Atmx3_OTPArray(b'?\x00\x00\x00\x00\x00 \x00') + self.assertEqual(otpArray.size, 64, + "Verify Array defaults to correct size") + self.assertEqual(otpArray.value, 0x2000000000003f, + "Verify value set correctly") + otp = otpArray.get_otp_group_by_name("RRAM_WRITE_LOCK") + self.assertEqual(otp.value, 0b100000, "Verify OTP is set correctly") + otp = otpArray.get_otp_group_by_idx(52) + self.assertEqual(otp.value, 0b100000, "Verify OTP is set correctly") + + def test_print_functional(self): + otpArray = atm_otp.Atmx3_OTPArray(b'?\x00\x00\x00\x00\x00 \x00') + otpArray.print_otp_array() + print(otpArray) + + def test_accesing_otp_bits(self): + otpArray = atm_otp.Atmx3_OTPArray(b'?\x00\x00\x00\x00\x00 \x00') + self.assertEqual(otpArray.get_otp_bits("RRAM_WRITE_LOCK"), "0b0100000") + self.assertEqual(otpArray.get_otp_bits( + "RRAM_WRITE_LOCK.SECURE_COUNTERS"), "0b1") + self.assertEqual(otpArray.get_otp_bits("RRAM_WRITE_LOCK.5"), "0b1") + self.assertEqual(otpArray.get_otp_bits(53), "0b1") + self.assertEqual(otpArray.get_otp_bits(48), "0b0") + self.assertEqual(otpArray.get_otp_bits(49), "0b0") + self.assertEqual(otpArray.get_otp_bits(50), "0b0") + self.assertEqual(otpArray.get_otp_bits("NABG_TRIM_LATCH"), "0b000111111") + self.assertEqual(otpArray.get_otp_bits("NABG_TRIM_LATCH.0"), "0b1") + self.assertEqual(otpArray.get_otp_bits("NABG_TRIM_LATCH.8"), "0b0") + self.assertEqual(otpArray.get_otp_bits("NABG_TRIM_LATCH.8"), "0b0") + + self.assertRaises(RuntimeError, otpArray.get_otp_bits, "NABG_TRIM_LATCH.9") + + self.assertEqual(otpArray.get_otp_bits("NOIND_LATCH"), "0b0") + +if __name__ == '__main__': + unittest.main() diff --git a/tools/scripts/gen_atm_partition_info.py b/tools/scripts/gen_atm_partition_info.py new file mode 100644 index 0000000..5a98c64 --- /dev/null +++ b/tools/scripts/gen_atm_partition_info.py @@ -0,0 +1,640 @@ +#!/usr/bin/env python +""" +@file Main.py + +@Defines to parse dts file for generating the partition_info.map file with arguments + +Copyright (C) Atmosic 2024 +""" + +import sys +import argparse +import os +from pathlib import Path + +ZEPHYR_BASE = os.getenv("ZEPHYR_BASE") +if not ZEPHYR_BASE: + # set ZEPHYR_BASE. + ZEPHYR_BASE = os.path.join(str(Path(__file__).resolve().parents[5]), + 'zephyr') + # Propagate this decision to child processes. + os.environ['ZEPHYR_BASE'] = ZEPHYR_BASE + print(f'ZEPHYR_BASE unset, using "{ZEPHYR_BASE}"') + +# import devicetree code from zephyr repository until zephyr support to use +# standalone repository +sys.path.append(os.path.join(ZEPHYR_BASE, 'scripts', 'dts', + 'python-devicetree', 'src')) + +from devicetree import dtlib + + +SEC_BASE_ADDR=0x10000000 +DEFAULT_ROM_OFFSET=0x0 +DEFAULT_ROM_SIZE=0x10000 +ST_PASS = 0 +ST_ERROR = 1 + +def utils_get_node_by_lable(dt_node, labelname): + for node in dt_node.node_iter(): + for label in node.labels: + if label == labelname: + return node + return None + +def utils_get_node_property_reg(dt_node): + ret = ST_ERROR + reg0 = None + reg1 = None + try: + reginfo = dt_node.props.get('reg', 'Not found') + if not reginfo: + return ST_ERROR, None, None + nums = dtlib.to_nums(reginfo.value) + if len(nums) == 2: + ret = ST_PASS + reg0 = nums[0] + reg1 = nums[1] + except: + print("except Error") + return ret, reg0, reg1 + +def parse_args(): + global args + base_parser = argparse.ArgumentParser(add_help=False) + base_parser.add_argument("-d", "--debug", action='store_true', + help="debug enabled, default false") + parser = argparse.ArgumentParser(description="Atmosic Zephyr Generate " + "Partition Info Map Tool") + subparsers = parser.add_subparsers(dest='opcode') + gen_parser = subparsers.add_parser('gen', parents=[base_parser]) + gen_parser.add_argument("-i", "--input_file", required=True, default=None, + help="input devicetree .dts file path") + gen_parser.add_argument("-o", "--output_file", required=True, default=None, + help="output partition_info file path") + gen_parser.add_argument("-p", "--platform_name", required=True,default=None, + help="platform name, ex: ATM33 or ATM34") + gen_parser.add_argument("-f", "--platform_family", + required=True, default=None, + help="platform family, ex: ATM33xx-5 or ATM34xx-5") + gen_parser.add_argument("-b", "--board", required=False, default=None, + help="board name, ex: ATMEVK-3330e-QN") + gen_parser.add_argument("-use_mcuboot", "--use_mcuboot", + action='store_true', + help="USE_MCUBOOT enabled, default false") + gen_parser.add_argument("-atm_no_spe", "--atm_no_spe", action='store_true', + help="ATM_NO_SPE enabled, default false") + gen_parser.add_argument("-use_mcuboot_overwrite", "--use_mcuboot_overwrite", + action='store_true', + help="USE_MCUBOOT_OVERWRITE enabled, default false") + gen_parser.add_argument("-mcuboot_secondary_ext_flash", + "--mcuboot_secondary_ext_flash", + action='store_true', + help="MCUBOOT_SECONDARY_EXT_FLASH enabled, " + "default false") + gen_parser.add_argument("-max_sector_size", "--max_sector_size", + required=False, default=None, help="max sector size") + gen_parser.add_argument("-rom_start", "--rom_start", required=False, + default=None, help="rom start") + gen_parser.add_argument("-rom_size", "--rom_size", required=False, + default=None, help="rom size") + gen_parser.add_argument("-user_data_offset", "--user_data_offset", + required=False, default=None, + help="user data offset") + gen_parser.add_argument("-user_data_size", "--user_data_size", + required=False, default=None, help="user data size") + merge_parser = subparsers.add_parser('merge', parents=[base_parser]) + merge_parser.add_argument("-i1", "--input_file1", required=True, + default=None, + help="input partition_info file path to be merge") + merge_parser.add_argument("-i2", "--input_file2", required=True, + default=None, + help="input partition_info file path to be merge") + merge_parser.add_argument("-o", "--output_file", required=True, default=None, + help="output partition_info file path") + args = parser.parse_args() + + +class AtmPartInfo: + def __init(self): + ROM_ADDR = None + ROM_SIZE = None + PRIMARY_IMG_START = None + PRIMARY_IMG_SIZE = None + SPE_START = None + SPE_SIZE = None + NS_APP_START = None + NS_APP_SIZE = None + OTA_STAGING_START = None + OTA_STAGING_SIZE = None + NVDS_START = None + NVDS_SIZE = None + USER_DATA_START = None + USER_DATA_SIZE = None + SEC_JRNL_START = None + SEC_JRNL_SIZE = None + SEC_CNTRS_KEYS_START = None + SEC_CNTRS_KEYS_SIZE = None + MCUBOOT_START = None + MCUBOOT_SIZE = None + MCUBOOT_SCRATCH_START = None + MCUBOOT_SCRATCH_SIZE = None + ATMWSTK_START = None + ATMWSTK_SIZE = None + TOTAL_RRAM_START = None + RRAM_START = None + RRAM_SIZE = None + USE_MCUBOOT = None + USE_MCUBOOT_OVERWRITE = None + MCUBOOT_MAX_IMG_SECTORS = None + EXT_FLASH_START = None + EXT_FLASH_SIZE = None + EXT_FLASH_MCUBOOT_SCRATCH_START = None + EXT_FLASH_MCUBOOT_SCRATCH_SIZE = None + EXT_FLASH_OTA_STAGING_START = None + EXT_FLASH_OTA_STAGING_SIZE = None + EXT_FLASH_UNUSED_START = None + EXT_FLASH_UNUSED_SIZE = None + EXT_FLASH_USER_DATA_START = None + BOARD = None + PLATFORM_NAME = None + PLATFORM_FAMILY = None + + +class PartInfoMerge: + def __init__(self, infile1, infile2, outfile): + self.infile1 = infile1 + self.infile2 = infile2 + self.outfile = outfile + self.input_part_info = None + self.output_part_info = None + + def init(self): + self.input1_part_info = self.parse_part_info(self.infile1) + self.input2_part_info = self.parse_part_info(self.infile2) + + def parse_part_info(self, filename): + part_info = AtmPartInfo() + with open(filename) as f: + for line in f.readlines(): + try: + key, value = line.strip().split("=") + part_info.__setattr__(key, value) + except: + # ignore + pass + return part_info + + def merge_info(self): + for key, value in self.input1_part_info.__dict__.items(): + if value is not None: + if hasattr(self.input2_part_info, key) and \ + self.input2_part_info.__getattribute__(key): + # ignore key already in input2_part_info + pass + else: + self.input2_part_info.__setattr__(key, value) + + def update_data(self): + with open(self.outfile, "w+") as f: + for key, value in self.input2_part_info.__dict__.items(): + if value is not None: + f.write(f"{key}={value}\n") + f.close() + + + def printPartInfo(self, part_info): + print("PartInfo:") + for key, value in part_info.__dict__.items(): + print(f"key = {key} value = {value}") + +class DevStreeParser: + def __init__(self, args): + self.dts_file = args.input_file + self.outfile = args.output_file + self.debug = args.debug + self.platform_name = args.platform_name + self.platform_family = args.platform_family + self.board = None + if args.board: + self.board = args.board + self.use_mcuboot = args.use_mcuboot + self.use_mcuboot_overwrite = args.use_mcuboot_overwrite + self.mcuboot_secondary_ext_flash = args.mcuboot_secondary_ext_flash + self.atm_no_spe = args.atm_no_spe + self.part_info = None + self.max_sector_size = None + self.rom_start = None + self.rom_size = None + self.user_data_offset = None + self.user_data_size = None + self.sec_jrnl_offset = None + self.sec_jrnl_size = None + self.sec_cntrs_keys_offset = None + self.sec_cntrs_keys_size = None + if args.max_sector_size: + self.max_sector_size = args.max_sector_size + if args.rom_start: + self.rom_start = int(args.rom_start, 16) + else: + self.rom_start = DEFAULT_ROM_OFFSET + if args.rom_size: + self.rom_size = int(args.rom_size, 16) + else: + self.rom_start = DEFAULT_ROM_SIZE + if args.user_data_offset: + self.user_data_offset = int(args.user_data_offset, 16) + if args.user_data_size: + self.user_data_size = int(args.user_data_size, 16) + + def init(self): + dt = dtlib.DT(self.dts_file) + if dt: + self.dt = dt + else: + print(f"DeviceTree parsing {args.input_file} failed") + sys.exit(1) + if os.path.exists(self.outfile): + os.remove(self.outfile) + self.part_info = AtmPartInfo() + self.part_info.PLATFORM_NAME = self.platform_name + self.part_info.PLATFORM_FAMILY = self.platform_family.lower() + if self.use_mcuboot: + self.part_info.USE_MCUBOOT = 1 + if self.part_info.PLATFORM_FAMILY != 'atmx2': + if self.max_sector_size: + self.part_info.MCUBOOT_MAX_IMG_SECTORS = self.max_sector_size + if self.use_mcuboot_overwrite: + self.part_info.USE_MCUBOOT_OVERWRITE = 1 + if self.rom_start: + self.part_info.ROM_ADDR = hex(self.rom_start) + if self.rom_size: + self.part_info.ROM_SIZE = hex(self.rom_size) + + def debug_print(self, msg): + if self.debug: + print(msg) + + def update_data(self): + with open(self.outfile, "a+") as f: + for key, value in self.part_info.__dict__.items(): + if value is not None: + f.write(f"{key}={value}\n") + f.close() + + def parsing_board(self): + # transfer BOARD + # atmosic_sdk : ATMEVK_3330e_QN, Zephyr: ATMEVK-3330e-QN_ns + board_name_prefix = None + if self.board: + name_split = self.board.split('_') + if len(name_split) > 2: + board_name_prefix = self.board + else: + board_name_prefix = name_split[0] + self.part_info.BOARD = board_name_prefix.replace("-", "_") + + def parsing_not_use_mcuboot(self, rram0, rram_start, rram_size): + # PRIMARY image as RRAM + self.part_info.PRIMARY_IMG_START = hex(rram_start) + self.part_info.PRIMARY_IMG_SIZE = hex(rram_size) + if not self.atm_no_spe: + spe_partition = utils_get_node_by_lable(rram0, "spe_partition") + if spe_partition: + ret, spe_start, spe_size = \ + utils_get_node_property_reg(spe_partition) + if ret == ST_PASS: + self.debug_print(f"spe_start = {hex(spe_start)}, " + f"spe_size = {hex(spe_size)}") + self.part_info.SPE_START = hex(spe_start + rram_start) + self.part_info.SPE_SIZE = hex(spe_size) + nspe_partition = utils_get_node_by_lable(rram0, "nspe_partition") + if nspe_partition: + ret, nspe_start, nspe_size = \ + utils_get_node_property_reg(nspe_partition) + if ret == ST_PASS: + self.debug_print(f"nspe_start = {hex(nspe_start)}, " + f"nspe_size = {hex(nspe_size)}") + self.part_info.NS_APP_START = hex(nspe_start + rram_start) + self.part_info.NS_APP_SIZE = hex(nspe_size) + else: + print("to do") + + def parsing_use_mcuboot(self, rram0, rram_start, rram_size): + # MCUBOOT from boot_partition + boot_partition = utils_get_node_by_lable(rram0, "boot_partition") + if boot_partition: + ret, mcuboot_start, mcuboot_size = \ + utils_get_node_property_reg(boot_partition) + if ret == ST_PASS: + self.debug_print(f"mcuboot_start = {hex(mcuboot_start)}, " + f"mcuboot_size = {hex(mcuboot_size)}") + self.part_info.MCUBOOT_START = hex(mcuboot_start + rram_start) + self.part_info.MCUBOOT_SIZE = hex(mcuboot_size) + # MCUBOOT_SCRASH from scratch_partition + scratch_partition = utils_get_node_by_lable(rram0, "scratch_partition") + if scratch_partition: + ret, scratch_start, scratch_size = \ + utils_get_node_property_reg(scratch_partition) + if ret == ST_PASS: + self.debug_print(f"rram0 scratch_start = {hex(scratch_start)}, " + f"scratch_size = {hex(scratch_size)}") + self.part_info.MCUBOOT_SCRATCH_START = \ + hex(scratch_start + rram_start) + self.part_info.MCUBOOT_SCRATCH_SIZE = hex(scratch_size) + # PRIMARY image from slot0_partition + slot0_partition = utils_get_node_by_lable(rram0, "slot0_partition") + if not slot0_partition: + return + ret, primary_start, primary_size = \ + utils_get_node_property_reg(slot0_partition) + if ret == ST_PASS: + self.debug_print(f"primary_start = {hex(primary_start)}, " + f"primary_size = {hex(primary_size)}") + self.part_info.PRIMARY_IMG_START = hex(primary_start + rram_start) + self.part_info.PRIMARY_IMG_SIZE = hex(primary_size) + if not self.atm_no_spe: + spe_partition = utils_get_node_by_lable(rram0, "spe_partition") + if spe_partition: + ret, spe_start, spe_size = \ + utils_get_node_property_reg(spe_partition) + if ret == ST_PASS: + self.debug_print(f"spe_start = {hex(spe_start)}, " + f"spe_size = {hex(spe_size)}") + self.part_info.SPE_START = hex(spe_start + rram_start) + self.part_info.SPE_SIZE = hex(spe_size) + nspe_partition = utils_get_node_by_lable(rram0, "nspe_partition") + if nspe_partition: + ret, nspe_start, nspe_size = \ + utils_get_node_property_reg(nspe_partition) + if ret == ST_PASS: + self.debug_print(f"nspe_start = {hex(nspe_start)}, " + f"nspe_size = {hex(nspe_size)}") + self.part_info.NS_APP_START = hex(nspe_start + rram_start) + self.part_info.NS_APP_SIZE = hex(nspe_size) + else: + print("to do") + # OTA_STAGING from slot1_partition + slot1_partition = utils_get_node_by_lable(rram0, "slot1_partition") + if slot1_partition: + ret, ota_staging_start, ota_staging_size = \ + utils_get_node_property_reg(slot1_partition) + if ret == ST_PASS: + self.debug_print(f"ota_staging_start = {hex(ota_staging_start)}, " + f"ota_staging_size = {hex(ota_staging_size)}") + self.part_info.OTA_STAGING_START = \ + hex(ota_staging_start + rram_start) + self.part_info.OTA_STAGING_SIZE = hex(ota_staging_size) + # ATMWSTK from slot2_partition + slot2_partition = utils_get_node_by_lable(rram0, "slot2_partition") + if slot2_partition: + ret, atmwstk_start, atmwstk_size = \ + utils_get_node_property_reg(slot2_partition) + if ret == ST_PASS: + self.debug_print(f"atmwstk_start = {hex(atmwstk_start)}, " + f"atmwstk_size = {hex(atmwstk_size)}") + self.part_info.ATMWSTK_START = hex(atmwstk_start + rram_start) + self.part_info.ATMWSTK_SIZE = hex(atmwstk_size) + + def parsing_rram(self): + rram_controller = utils_get_node_by_lable(self.dt, "rram_controller") + ret, rram0_start, rram0_size = \ + utils_get_node_property_reg(rram_controller) + if ret == ST_ERROR: + print("Parsing rram_controller failed") + return + self.debug_print(f"rram0_start = {hex(rram0_start)}, " + f"rram0_size = {hex(rram0_size)}") + if rram0_start > SEC_BASE_ADDR: + rram0_start = rram0_start - SEC_BASE_ADDR + self.part_info.RRAM_START = hex(rram0_start) + self.part_info.RRAM_SIZE = hex(rram0_size) + rram0 = utils_get_node_by_lable(rram_controller, "rram0") + if not rram0: + print("Parsing rram0 failed") + return + if not self.use_mcuboot: + self.parsing_not_use_mcuboot(rram0, rram0_start, rram0_size) + else: + self.parsing_use_mcuboot(rram0, rram0_start, rram0_size) + # NVDS from storage_partition + storage_partition = utils_get_node_by_lable(rram0, "storage_partition") + if storage_partition: + ret, nvds_start, nvds_size = \ + utils_get_node_property_reg(storage_partition) + if ret == ST_ERROR: + print("Parsing rram storage failed") + return + self.debug_print(f"nvds_start = {hex(nvds_start)}, " + f"nvds_size = {hex(nvds_size)}") + self.part_info.NVDS_START = hex(nvds_start + rram0_start) + self.part_info.NVDS_SIZE = hex(nvds_size) + + # partition info from input arguments + if self.user_data_offset: + self.part_info.USER_DATA_START = \ + hex(self.user_data_offset + rram0_start) + if self.user_data_size: + self.part_info.USER_DATA_SIZE = hex(self.user_data_size) + + def parsing_flash(self): + flash_controller = utils_get_node_by_lable(self.dt, "flash_controller") + if flash_controller: + ret, flash0_start, flash0_size = \ + utils_get_node_property_reg(flash_controller) + if ret == ST_ERROR: + print("Parsing flash_controller failed") + return + self.debug_print(f"flash0_start = {hex(flash0_start)}, " + f"flash0_size = {hex(flash0_size)}") + if flash0_start > SEC_BASE_ADDR: + flash0_start = flash0_start - SEC_BASE_ADDR + self.part_info.EXT_FLASH_START = hex(flash0_start) + self.part_info.EXT_FLASH_SIZE = hex(flash0_size) + flash0 = utils_get_node_by_lable(flash_controller, "flash0") + if not flash0: + print("Parsing flash0 failed") + return + # MCUBOOT_SCRASH from scratch_partition + scratch_partition = utils_get_node_by_lable(flash0, "scratch_partition") + if scratch_partition: + ret, scratch_start, scratch_size = \ + utils_get_node_property_reg(scratch_partition) + if ret == ST_PASS: + self.debug_print(f"flash0 scratch_start = {hex(scratch_start)}, " + f"scratch_size = {hex(scratch_size)}") + self.part_info.EXT_FLASH_MCUBOOT_SCRATCH_START = \ + hex(scratch_start + flash0_start) + self.part_info.EXT_FLASH_MCUBOOT_SCRATCH_SIZE = hex(scratch_size) + # OTA_STAGING from slot1_partition + slot1_partition = utils_get_node_by_lable(flash0, "slot1_partition") + if slot1_partition: + ret, ota_staging_start, ota_staging_size = \ + utils_get_node_property_reg(slot1_partition) + if ret == ST_PASS: + self.debug_print(f"ota_staging_start = {hex(ota_staging_start)}, " + f"ota_staging_size = {hex(ota_staging_size)}") + self.part_info.EXT_FLASH_OTA_STAGING_START = \ + hex(ota_staging_start + flash0_start) + self.part_info.EXT_FLASH_OTA_STAGING_SIZE = hex(ota_staging_size) + if not self.atm_no_spe: + nspe_partition = utils_get_node_by_lable(flash0, "nspe_partition") + if nspe_partition: + ret, nspe_start, nspe_size = \ + utils_get_node_property_reg(nspe_partition) + if ret == ST_PASS: + self.debug_print(f"nspe_start = {hex(nspe_start)}, " + f"nspe_size = {hex(nspe_size)}") + self.part_info.NS_APP_START = hex(nspe_start + flash0_start) + self.part_info.NS_APP_SIZE = hex(nspe_size) + else: + print("to do") + + def parsing_ext_flash(self): + flash_controller = utils_get_node_by_lable(self.dt, "flash_controller") + if not flash_controller: + print("Parsing flash_controller failed") + return + flash0 = utils_get_node_by_lable(flash_controller, "flash0") + if not flash0: + print("Parsing flash0 failed") + return + ret, flash0_start, flash0_size = utils_get_node_property_reg(flash0) + if ret == ST_ERROR: + print("Parsing flash_controller failed") + return + self.debug_print(f"flash0_start = {hex(flash0_start)}, " + f"flash0_size = {hex(flash0_size)}") + self.part_info.FLASH_START = hex(flash0_start) + self.part_info.FLASH_SIZE = hex(flash0_size) + self.part_info.FLASH_TOTAL = hex(flash0_size) + # MCUBOOT from boot_partition + boot_partition = utils_get_node_by_lable(flash0, "boot_partition") + if boot_partition: + ret, mcuboot_start, mcuboot_size = \ + utils_get_node_property_reg(boot_partition) + if ret == ST_PASS: + self.debug_print(f"mcuboot_start = {hex(mcuboot_start)}, " + f"mcuboot_size = {hex(mcuboot_size)}") + self.part_info.MCUBOOT_START = hex(mcuboot_start + flash0_start) + self.part_info.MCUBOOT_SIZE = hex(mcuboot_size) + # MCUBOOT_SCRASH from scratch_partition + scratch_partition = utils_get_node_by_lable(flash0, "scratch_partition") + if scratch_partition: + ret, scratch_start, scratch_size = \ + utils_get_node_property_reg(scratch_partition) + if ret == ST_PASS: + self.debug_print(f"rram0 scratch_start = {hex(scratch_start)}, " + f"scratch_size = {hex(scratch_size)}") + self.part_info.MCUBOOT_SCRATCH_START = \ + hex(scratch_start + flash0_start) + self.part_info.MCUBOOT_SCRATCH_SIZE = hex(scratch_size) + # PRIMARY image from slot0_partition + slot0_partition = utils_get_node_by_lable(flash0, "slot0_partition") + if not slot0_partition: + return + ret, primary_start, primary_size = \ + utils_get_node_property_reg(slot0_partition) + if ret == ST_PASS: + self.debug_print(f"primary_start = {hex(primary_start)}, " + f"primary_size = {hex(primary_size)}") + self.part_info.PRIMARY_IMG_START = hex(primary_start + flash0_start) + self.part_info.PRIMARY_IMG_SIZE = hex(primary_size) + # OTA_STAGING from slot1_partition + slot1_partition = utils_get_node_by_lable(flash0, "slot1_partition") + if slot1_partition: + ret, ota_staging_start, ota_staging_size = \ + utils_get_node_property_reg(slot1_partition) + if ret == ST_PASS: + self.debug_print(f"ota_staging_start = {hex(ota_staging_start)}, " + f"ota_staging_size = {hex(ota_staging_size)}") + self.part_info.OTA_STAGING_START = \ + hex(ota_staging_start + flash0_start) + self.part_info.OTA_STAGING_SIZE = hex(ota_staging_size) + # NVDS from storage_partition + storage_partition = utils_get_node_by_lable(flash0, "storage_partition") + if storage_partition: + ret, nvds_start, nvds_size = \ + utils_get_node_property_reg(storage_partition) + if ret == ST_ERROR: + print("Parsing rram storage failed") + return + self.debug_print(f"nvds_start = {hex(nvds_start)}, " + f"nvds_size = {hex(nvds_size)}") + self.part_info.NVDS_START = hex(nvds_start + flash0_start) + self.part_info.NVDS_SIZE = hex(nvds_size) + + + def parsing_sec_jrnl_and_key(self): + sec_jrnl = utils_get_node_by_lable(self.dt, "sec_jrnl") + if sec_jrnl: + ret, sec_jrnl_start, sec_jrnl_size = \ + utils_get_node_property_reg(sec_jrnl) + if ret == ST_PASS: + self.debug_print(f"sec_jrnl_start = {hex(sec_jrnl_start)}, " + f"sec_jrnl_size = {hex(sec_jrnl_size)}") + if sec_jrnl_start > SEC_BASE_ADDR: + sec_jrnl_start = sec_jrnl_start - SEC_BASE_ADDR + self.part_info.SEC_JRNL_START = hex(sec_jrnl_start) + self.part_info.SEC_JRNL_SIZE = hex(sec_jrnl_size) + + sec_cntr_keys = utils_get_node_by_lable(self.dt, "sec_cntr_keys") + if sec_cntr_keys: + ret, sec_cntr_keys_start, sec_cntr_keys_size = \ + utils_get_node_property_reg(sec_cntr_keys) + if ret == ST_PASS: + self.debug_print( + f"sec_cntr_keys_start = {hex(sec_cntr_keys_start)}, " + f"sec_cntr_keys_size = {hex(sec_cntr_keys_size)}") + if sec_cntr_keys_start > SEC_BASE_ADDR: + sec_cntr_keys_start = sec_cntr_keys_start - SEC_BASE_ADDR + self.part_info.SEC_CNTRS_KEYS_START = hex(sec_cntr_keys_start) + self.part_info.SEC_CNTRS_KEYS_SIZE = hex(sec_cntr_keys_size) + + def summary(self): + if hasattr(self.part_info, "RRAM_START") and \ + hasattr(self.part_info, "RRAM_SIZE") and \ + hasattr(self.part_info, "SEC_JRNL_SIZE") and \ + hasattr(self.part_info, "SEC_CNTRS_KEYS_SIZE"): + self.part_info.TOTAL_RRAM_START = \ + hex(int(self.part_info.RRAM_START, 16) + + int(self.part_info.RRAM_SIZE, 16) + + int(self.part_info.SEC_JRNL_SIZE, 16) + + int(self.part_info.SEC_CNTRS_KEYS_SIZE, 16)) + +def main(): + parse_args() + if args.opcode == 'gen': + if not os.path.exists(args.input_file): + print(f"{args.input_file} not exist") + sys.exit(1) + dtsParser = DevStreeParser(args) + dtsParser.init() + dtsParser.parsing_board() + if dtsParser.platform_family.lower() != 'atmx2': + dtsParser.parsing_rram() + dtsParser.parsing_flash() + dtsParser.parsing_sec_jrnl_and_key() + else: + dtsParser.parsing_ext_flash() + dtsParser.summary() + dtsParser.update_data() + elif args.opcode == 'merge': + if not os.path.exists(args.input_file1): + print(f"{args.input_file1} not exist") + sys.exit(1) + if not os.path.exists(args.input_file2): + print(f"{args.input_file2} not exist") + sys.exit(1) + partinfomerge = PartInfoMerge( + args.input_file1, args.input_file2, args.output_file) + partinfomerge.init() + partinfomerge.merge_info() + partinfomerge.update_data() + else: + print(f"opcode {args.opcode} not support") + sys.exit(1) + + +if __name__ == '__main__': + main() diff --git a/tools/scripts/sec_jrnl_tlv/__init__.py b/tools/scripts/sec_jrnl_tlv/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/tools/scripts/sec_jrnl_tlv/sec_jrnl_tlv.py b/tools/scripts/sec_jrnl_tlv/sec_jrnl_tlv.py new file mode 100644 index 0000000..22df0ae --- /dev/null +++ b/tools/scripts/sec_jrnl_tlv/sec_jrnl_tlv.py @@ -0,0 +1,351 @@ +''' +@file sec_jrnl_tlv.py + +@brief Secure Journal Managment + +Copyright (C) Atmosic 2024 +''' +import struct + +SEC_JRNL_MAGIC = bytes([0x4E, 0x56, 0x44, 0x53]) +SEC_JRNL_MAGIC_SIZE = 4 +TLV_META_HEADER_FORMAT = 'BBH' +TLV_META_SIZE = struct.calcsize(TLV_META_HEADER_FORMAT) + +SEC_JRNL_WALK_CONT = 0 +SEC_JRNL_WALK_DONE = 1 + + +class BadMagicException(Exception): + """Magic is not the correct value + """ + pass + + +class InvalidTLVException(Exception): + """TLV tag value is invalid + """ + pass + + +class TLVStatus(): + SEC_JRNL_STATUS_VALID_IDX = 0x01 + SEC_JRNL_STATUS_VALID_MASK = 0x01 + SEC_JRNL_STATUS_LOCKED_IDX = 0x02 + SEC_JRNL_STATUS_LOCKED_MASK = 1 << (SEC_JRNL_STATUS_LOCKED_IDX - 1) + SEC_JRNL_STATUS_ERASED_IDX = 0x03 + SEC_JRNL_STATUS_ERASED_MASK = 1 << (SEC_JRNL_STATUS_ERASED_IDX - 1) + + def __init__(self, status=0x06) -> None: + self.status = status + + def set_status_bit(self, idx, val): + self.status = (self.status & (~(1 << (idx - 1)))) | (val << (idx - 1)) + + @property + def valid(self): + return not (self.status & TLVStatus.SEC_JRNL_STATUS_VALID_MASK) + + @valid.setter + def valid(self, value): + self.set_status_bit( + TLVStatus.SEC_JRNL_STATUS_VALID_IDX, not bool(value)) + + @property + def locked(self): + return not (self.status & TLVStatus.SEC_JRNL_STATUS_LOCKED_MASK) + + @locked.setter + def locked(self, value): + self.set_status_bit( + TLVStatus.SEC_JRNL_STATUS_LOCKED_IDX, not bool(value)) + + @property + def erased(self): + return not (self.status & TLVStatus.SEC_JRNL_STATUS_ERASED_MASK) + + @erased.setter + def erased(self, value): + self.set_status_bit( + TLVStatus.SEC_JRNL_STATUS_ERASED_IDX, not bool(value)) + + def __str__(self) -> str: + valid_str = f"[{'!' if not self.valid else '' }V]" + erased_str = f"[{'!' if not self.erased else '' }E]" + locked_str = f"[{'!' if not self.locked else '' }L]" + return f"{valid_str}{locked_str}{erased_str}" + + +class TLV(): + PTAG_LJUST_SIZE = 10 + TAG_NAMES = { + 0xb8: "ATE", + 0xb9: "CHIP_INFO", + 0xb0: "RIF_CAL", + 0xb1: "MDM_CAL", + 0xbc: "MISC_CAL", + } + + def __init__(self, tag, status, raw_len, data, idx=-1) -> None: + if tag == 0xff: + raise InvalidTLVException("Bad tag") + self.tag = tag + if isinstance(status, TLVStatus): + self.status = status + else: + self.status = TLVStatus(status) + self.data = data + self.raw_len = raw_len + self.header_size = TLV.get_header_size(raw_len) + self.tlv_len = TLV.get_tlv_size(raw_len) + if self.tlv_len != len(data): + raise InvalidTLVException("Invalid Length") + # optionally track index where TLV is located + self.idx = idx + + @staticmethod + def get_header_size(raw_len): + """Calculate proper header size (i.e. if using compressed format) + + Args: + raw_len (int): raw length stored as uint16_t in binary data + + Returns: + int: correct header size + """ + if raw_len & 0x80: + return TLV_META_SIZE + return (TLV_META_SIZE - 1) + + @staticmethod + def get_tlv_size(raw_len): + """Calculates length of TLV data + + Args: + raw_len (int): raw length stored as uint16_t in binary data + + Returns: + int: length of TLV + """ + tlv_len = raw_len & 0x7f + if raw_len & 0x80: + tlv_len += ((raw_len & 0xff00) >> 1) + return tlv_len + + @property + def bin(self): + """returns binary representation of TLV + """ + header = struct.pack('BBH', self.tag, self.status.status, self.raw_len) + header = header[0:self.get_header_size(self.raw_len)] + return header + self.data + + @property + def total_size(self): + """Calculates total size of tlv in bytes (header + data) + + Returns: + int: size of TLV + """ + return TLV.get_header_size(self.raw_len) + TLV.get_tlv_size(self.raw_len) + + @classmethod + def from_bin(cls, bin, idx): + """Returns TLV class from a binary data format + + Args: + bin (bytes): binary + idx (int): index in binary + + Raises: + InvalidTLVException: if passed binary is not valid or reached end + + Returns: + TLV: tlv class from binary + """ + if idx + TLV_META_SIZE >= len(bin): + raise InvalidTLVException + + tlv_type, tlv_status, raw_tlv_len = struct.unpack( + TLV_META_HEADER_FORMAT, bin[idx: idx + TLV_META_SIZE]) + + header_size = TLV.get_header_size(raw_tlv_len) + data_idx = idx + header_size + + tlv_len = TLV.get_tlv_size(raw_tlv_len) + tlv_data = bin[data_idx: data_idx + tlv_len] + return cls(tlv_type, tlv_status, raw_tlv_len, tlv_data, idx=idx) + + @classmethod + def from_contents(cls, tag, content, locked=False): + """Returns TLV class from data + + Note: this should be used when generating a new TLV, not related to an + existing binary. This class properly builds meta header data from just + tag and content + + Args: + tag (int): tag for tlv + content: data for tlv + locked (bool): sets locked bit in status. + + Raises: + InvalidTLVException: if passed binary is not valid or reached end + + Returns: + TLV: tlv class from binary + """ + tlv_status = TLVStatus() + tlv_status.locked = locked + data_len = len(content) + if data_len > 0x7f: + data_len = (data_len & 0x7f) & ((data_len << 1) & 0xff) + + return cls(tag, tlv_status, data_len, content) + + @property + def ptag(self): + """Print format for given tag. + + Returns: + str: name of tag, or default format + """ + if self.tag in TLV.TAG_NAMES: + return TLV.TAG_NAMES[self.tag].ljust(TLV.PTAG_LJUST_SIZE) + return f"tag:({'{:02x}'.format(self.tag)})".ljust(TLV.PTAG_LJUST_SIZE) + + @property + def pidx(self): + """Print format for given tag. + + Returns: + str: name of tag, or default format + """ + if self.idx == -1: + return "" + return f"@{'{:04x}'.format(self.idx + self.header_size)} " + + def __str__(self) -> str: + p_str = f"{self.pidx}{self.ptag} {self.status} data: [{' '.join('{:02x}'.format(b) for b in self.data)}]" + return p_str + + +class SecJrnl(): + SEC_JRNL_TAIL_PAD_LEN = 4 + SEC_JRNL_SECURE_ONLY_MASK = 0xfc + SEC_JRNL_SECURE_ONLY_VAL = 0xec + + @classmethod + def is_secure_tag(cls, tag): + return (tag & cls.SEC_JRNL_SECURE_ONLY_MASK) == cls.SEC_JRNL_SECURE_ONLY_VAL + + def __init__(self, bin=None, max_len=1776) -> None: + if bin is None: + bin = b"NVDS"+b"\xFF"*(max_len-SEC_JRNL_MAGIC_SIZE) + self.raw_bin = bin + self.magic = struct.unpack('BBBB', bin[0:SEC_JRNL_MAGIC_SIZE]) + self.max_len = max_len + + @classmethod + def from_file(cls, bin_file): + """Create a SecJrnl class from a given binary file + + Args: + bin_file: filepath to sec jrnl data + """ + with open(bin_file, 'rb') as bin_fd: + return cls(bin_fd.read()) + + @property + def len(self): + return self.walk_bin(self.raw_bin) + SecJrnl.SEC_JRNL_TAIL_PAD_LEN + + @property + def bin(self): + return self.raw_bin[0:self.len] + + def walk_bin(self, bin=None, func=lambda tlv: SEC_JRNL_WALK_CONT): + """Provides an interface to iterate through binary + + Note: the function passed must return SEC_JRNL_WALK_CONT to continue + iterating, if it returns SEC_JRNL_WALK_DONE, walk_bin will exit on the current TLV. + + Args: + bin: binary file to iterate. Defaults to self.bin + func: function to execute on each TLV, Defaults to lambda tlv:SEC_JRNL_WALK_CONT. + + Returns: + int: index of TLV (or if completed, length of TLVs) + """ + if bin is None: + bin = self.raw_bin + tlv_off = SEC_JRNL_MAGIC_SIZE + while tlv_off < self.max_len: + try: + tlv = TLV.from_bin(bin, tlv_off) + except InvalidTLVException as e: + return tlv_off + if func(tlv) == SEC_JRNL_WALK_DONE: + return tlv_off + tlv_off += tlv.total_size + return tlv_off + + def __iter__(self): + self.iter_tlv_off = SEC_JRNL_MAGIC_SIZE + return self + + def __next__(self): + try: + tlv = TLV.from_bin(self.bin, self.iter_tlv_off) + self.iter_tlv_off += tlv.total_size + return tlv + except InvalidTLVException as e: + raise StopIteration + + def get(self, tag_val): + ret = None + for tlv in iter(self): + if tag_val == tlv.tag: + ret = tlv + if tlv.status.locked: + return ret + return ret + + def __str__(self): + tlv_str_array = [] + for tlv in iter(self): + tlv_str_array.append(str(tlv)) + return "\n".join(tlv_str_array) + + def append_tag(self, tag, data, locked=False): + """Append tag to Secure Journal + + Args: + tag (int): tag + data: data content of TLV + locked (bool, optional): Lock down tag. Defaults to False. + """ + new_tlv = TLV.from_contents(tag, data, locked) + if (self.ratchet_idx + new_tlv.total_size) > self.max_len: + raise RuntimeError("Secure Journal can hold no more data") + self.raw_bin = self.raw_bin[0:self.ratchet_idx] + new_tlv.bin + \ + self.raw_bin[self.ratchet_idx + new_tlv.total_size:] + + @property + def ratchet_idx(self): + """returns Value of ratchet index to lock down entire Secure Journal + """ + return self.len - SecJrnl.SEC_JRNL_TAIL_PAD_LEN + + +if __name__ == "__main__": + import argparse + parser = argparse.ArgumentParser( + prog='ProgramName', + description='What the program does', + epilog='Text at the bottom of help') + parser.add_argument('filename') + args = parser.parse_args() + jrnl = SecJrnl.from_file(args.filename) + print(jrnl) + print(jrnl.raw_bin) diff --git a/tools/scripts/sec_jrnl_tlv/test_sec_jrnl_tlv.py b/tools/scripts/sec_jrnl_tlv/test_sec_jrnl_tlv.py new file mode 100644 index 0000000..765cc07 --- /dev/null +++ b/tools/scripts/sec_jrnl_tlv/test_sec_jrnl_tlv.py @@ -0,0 +1,152 @@ +''' +@file test_sec_jrnl_tlv.py + +@brief Secure Journal Managment Unit tests + +Copyright (C) Atmosic 2024 +''' +import unittest +import sec_jrnl_tlv + + +class TestTLVStatusMethods(unittest.TestCase): + """Test TLVStatus class""" + + def test_default_status(self): + tlv_status = sec_jrnl_tlv.TLVStatus() + self.assertEqual(tlv_status.status, 6) + self.assertEqual(tlv_status.valid, True) + self.assertEqual(tlv_status.locked, False) + self.assertEqual(tlv_status.erased, False) + + def test_override_default_status(self): + tlv_status = sec_jrnl_tlv.TLVStatus(1) + self.assertEqual(tlv_status.valid, False) + self.assertEqual(tlv_status.locked, True) + self.assertEqual(tlv_status.erased, True) + tlv_status = sec_jrnl_tlv.TLVStatus(3) + self.assertEqual(tlv_status.valid, False) + self.assertEqual(tlv_status.locked, False) + self.assertEqual(tlv_status.erased, True) + tlv_status = sec_jrnl_tlv.TLVStatus(4) + self.assertEqual(tlv_status.valid, True) + self.assertEqual(tlv_status.locked, True) + self.assertEqual(tlv_status.erased, False) + + def test_valid_property_setter(self): + tlv_status = sec_jrnl_tlv.TLVStatus(0) + self.assertEqual(tlv_status.valid, True) + tlv_status.valid = False + self.assertEqual(tlv_status.valid, False) + self.assertEqual(tlv_status.status, 1) + + def test_locked_property_setter(self): + tlv_status = sec_jrnl_tlv.TLVStatus(0) + self.assertEqual(tlv_status.locked, True) + tlv_status.locked = False + self.assertEqual(tlv_status.locked, False) + self.assertEqual(tlv_status.status, 2) + + def test_erased_property_setter(self): + tlv_status = sec_jrnl_tlv.TLVStatus(0) + self.assertEqual(tlv_status.erased, True) + tlv_status.erased = False + self.assertEqual(tlv_status.erased, False) + self.assertEqual(tlv_status.status, 4) + + +class TestTLVMethods(unittest.TestCase): + """Test TLV class""" + + def test_basic_TLV_creation(self): + tlv = sec_jrnl_tlv.TLV(0xaa, 0x7, 2, b'\xde\xad') + self.assertEqual(tlv.idx, -1) + self.assertEqual(tlv.total_size, 5) + tlv = sec_jrnl_tlv.TLV( + 0xaa, sec_jrnl_tlv.TLVStatus(4), 2, b'\xde\xad', idx=23) + self.assertEqual(tlv.idx, 23) + self.assertEqual(tlv.total_size, 5) + tlv = sec_jrnl_tlv.TLV(0xaa, 0x7, 2, b'\xde\xad', idx=23) + self.assertEqual(tlv.idx, 23) + self.assertEqual(tlv.total_size, 5) + + def test_TLV_creation_fail_on_bad_tag(self): + with self.assertRaises(sec_jrnl_tlv.InvalidTLVException): + tlv = sec_jrnl_tlv.TLV(0xff, 0x7, 2, b'\xde\xad') + + def test_TLV_creation_fail_on_bad_length(self): + with self.assertRaises(sec_jrnl_tlv.InvalidTLVException): + # length should be 2 but is set to 5 + tlv = sec_jrnl_tlv.TLV(0xaa, 0x7, 5, b'\xde\xad') + + def test_TLV_bin_property(self): + tlv = sec_jrnl_tlv.TLV(0xaa, 0x7, 2, b'\xde\xad') + self.assertEqual(tlv.bin, b"\xaa\x07\x02\xde\xad") + + def test_TLV_from_bin(self): + tlv = sec_jrnl_tlv.TLV.from_bin(b"\xaa\x07\x02\xde\xad", 0) + self.assertEqual(tlv.tag, 0xaa) + self.assertEqual(tlv.idx, 0) + self.assertEqual(tlv.status.status, 0x7) + self.assertEqual(tlv.total_size, 0x5) + tlv = sec_jrnl_tlv.TLV.from_bin(b"\x00\x00\xaa\x07\x02\xde\xad", 2) + self.assertEqual(tlv.tag, 0xaa) + self.assertEqual(tlv.idx, 2) + self.assertEqual(tlv.status.status, 0x7) + self.assertEqual(tlv.total_size, 0x5) + + def test_TLV_from_content(self): + tlv = sec_jrnl_tlv.TLV.from_contents(0xde, b"\xde\xad") + self.assertEqual(tlv.bin, b"\xde\x06\x02\xde\xad") + self.assertEqual(tlv.tag, 0xde) + self.assertEqual(tlv.idx, -1) + self.assertEqual(tlv.status.locked, False) + tlv = sec_jrnl_tlv.TLV.from_contents(0xde, b"\xde\xad", True) + self.assertEqual(tlv.bin, b"\xde\x04\x02\xde\xad") + self.assertEqual(tlv.tag, 0xde) + self.assertEqual(tlv.idx, -1) + self.assertEqual(tlv.status.locked, True) + + +class TestSecJrnlMethods(unittest.TestCase): + """Test SecJrnl class""" + + def setUp(self) -> None: + self.sec_jrnl_bin = b'NVDS\xb8\x06\x1c\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x92E(\x0c\x02\x03\xd4\x00\x00\x00\x00\x00\xb9\x06\x04\x11\x00\x01\x01\xb0\x06\x1c\xe1!\x00\x00\xd8\x05\x00\x00\xa0\x80*\x02P\x80\x10\x01\x10\x00\x00\x00\xcd\r\x1f\x00\x1b\x06\x00\x00\xb1\x06<\x15P\x8b)L\x00P\x04\xfb\xfb\x01\x00LS\x17\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x0f\x0f\x17\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01\x00\x02\xbc\x06,\x11\x00\x00\x00\x07\x00\x06*\x08\xc0\x04*\x10\x00\xfa.\xba;t<\xfc\x10\x16\x0ey\x18%\x00\x93d\x7f\x00\xd6\x94\xd2\x06?\x00\x00\x00\x00\x00\x02\x00\xd0\x06\x04\xde\xad\xbe\xef\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\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+ return super().setUp() + + def test_sec_jrnl_creation(self): + secjrnl = sec_jrnl_tlv.SecJrnl(self.sec_jrnl_bin) + tags = [] + for tag in iter(secjrnl): + tags.append(tag.tag) + self.assertEqual([0xb8, 0xb9, 0xb0, 0xb1, 0xbc, 0xd0], tags) + + def test_sec_jrnl_get_tag(self): + secjrnl = sec_jrnl_tlv.SecJrnl(self.sec_jrnl_bin) + tlv = secjrnl.get(0xb0) + self.assertEqual(tlv.tag, 0xb0) + tlv = secjrnl.get(0x11) + self.assertEqual(tlv, None) + + def test_sec_jrnl_append_tag(self): + secjrnl = sec_jrnl_tlv.SecJrnl(self.sec_jrnl_bin) + tlv = secjrnl.get(0x01) + self.assertEqual(tlv, None) + secjrnl.append_tag(0x01, b"hello", False) + tlv = secjrnl.get(0x01) + self.assertEqual(tlv.tag, 0x01) + + + def test_sec_jrnl_append_tag(self): + secjrnl = sec_jrnl_tlv.SecJrnl(self.sec_jrnl_bin) + tlv = secjrnl.get(0x01) + self.assertEqual(tlv, None) + secjrnl.append_tag(0x01, b"hello", False) + tlv = secjrnl.get(0x01) + self.assertEqual(tlv.tag, 0x01) + + + +if __name__ == '__main__': + unittest.main() diff --git a/west/__init__.py b/west/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/west/atm_arch_extension.py b/west/atm_arch_extension.py new file mode 100644 index 0000000..43e7923 --- /dev/null +++ b/west/atm_arch_extension.py @@ -0,0 +1,379 @@ +#!/usr/bin/env python +""" +@file atm_arch_extension.py + +@Defines to generate/show/burn atm isp atm file + +Copyright (C) Atmosic 2024 +""" + +import argparse +import os +from pathlib import Path +import sys +from west.commands import WestCommand + +ROOT_DIR = Path(os.path.dirname(os.path.realpath(__file__))) + +BASE_ADDR = 0x10000000 + +TYPE_NVDS = 0 +TYPE_SPE = 1 +TYPE_APP = 2 +TYPE_MCUBOOT = 3 +TYPE_ATMWSTK = 4 +TYPE_EXTRA_FILE = 5 + +ARCH_USAGE = ''' \ +west atmarch [-h] [-i {input file name} | --append] [-s] [-d] + [-o {output file name}] + [-p {partition_info map file}] + [--atm_isp_path {atm_isp exe file}] + [--nvds_file {nvds file}] + [--spe_file {spe file}] + [--app_file {app file}] + [--mcuboot_file {mcuboot file}] + [--atmwstk_file {atmwstk file}] +''' + +class AtmPartInfo: + def __init(self): + pass + + def setattr(self, name, value): + self.__setattr__(name, value) + + def parse_info(self, filepath): + f = open(filepath, 'r') + for line in f.readlines(): + key, value = line.strip().split('=') + if key is not None and value is not None: + self.setattr(key, value) + f.close() + + +class AtmIsp: + def __init__(self, atm_isp_path, debug=False): + self.atm_isp_exe_path = atm_isp_path + self.partInfo = None + self.debug = debug + + def decode_atm(self, input_file): + # atm_isp decode [-h] [-i ARCHIVE] + cmd_arg = [self.atm_isp_exe_path, 'decode', '-i', input_file] + return self.exe_cmd(cmd_arg) + + def burn_atm(self, input_file, openocd_pkg_root, device=None, dst_dir=None, + openocd_script_only=False): + # atm_isp decode [-h] [-i ARCHIVE] + cmd_arg = [self.atm_isp_exe_path, 'burn', '-i', input_file, '-z', + '--openocd_pkg_root', openocd_pkg_root] + if dst_dir: + cmd_arg.append('-d') + cmd_arg.append(dst_dir) + if openocd_script_only: + cmd_arg.append('-E') + return self.exe_cmd(cmd_arg) + + def update_partInfo(self, partInfo): + self.partInfo = partInfo + + def init_atm(self, output_file): + if not self.partInfo.PLATFORM_FAMILY or \ + not self.partInfo.PLATFORM_NAME or \ + not self.partInfo.BOARD: + print(f"Cannot find PLATFORM_FAMILY or PLATFORM_NAME " + "or BOARD info") + sys.exit(1) + # atm_isp init [-o NEW_ARCHIVE] [-t] [-s] \ + # [-sec_dbg_key_checksum sec_dbg_key_checksum] \ + # [-b] family name board + cmd_arg = [self.atm_isp_exe_path, 'init', '-o', output_file, '-z'] + cmd_arg.append(self.partInfo.PLATFORM_FAMILY) + cmd_arg.append(self.partInfo.PLATFORM_NAME) + cmd_arg.append(self.partInfo.BOARD) + return self.exe_cmd(cmd_arg) + + def append(self, load_type, filepath, input_file, output_file): + if hasattr(self.partInfo, 'PLATFORM_FAMILY') and \ + self.partInfo.PLATFORM_FAMILY == 'atmx2': + return self.add_flash(load_type, filepath, input_file, output_file) + else: + return self.add_rram(load_type, filepath, input_file, output_file) + + def add_rram(self, load_type, filepath, input_file, output_file): + base_addr = hex(BASE_ADDR) + if load_type == TYPE_NVDS: + if not self.partInfo.NVDS_START or not self.partInfo.NVDS_SIZE: + print(f"Cannot find NVDS_START and NVDS_SIZE info") + sys.exit(1) + region_start = self.partInfo.NVDS_START + region_size = self.partInfo.NVDS_SIZE + extra_info = 'NVDS' + elif load_type == TYPE_SPE: + if not self.partInfo.SPE_START or \ + not self.partInfo.SPE_SIZE: + print(f"Cannot find SPE_START and SPE_SIZE info") + sys.exit(1) + region_start = self.partInfo.SPE_START + region_size = self.partInfo.SPE_SIZE + extra_info = 'BOOTLOADER' + elif load_type == TYPE_APP: + if not hasattr(self.partInfo, 'USE_MCUBOOT'): + extra_info = 'APP' + if not self.partInfo.NS_APP_START or \ + not self.partInfo.NS_APP_SIZE: + print(f"Cannot find NS_APP_START and NS_APP_SIZE info") + sys.exit(1) + region_start = self.partInfo.NS_APP_START + region_size = self.partInfo.NS_APP_SIZE + else: + extra_info = 'SIGNED_APP' + if not self.partInfo.PRIMARY_IMG_START or \ + not self.partInfo.PRIMARY_IMG_SIZE: + print(f"Cannot find PRIMARY_IMG_START and " + "PRIMARY_IMG_SIZE info") + sys.exit(1) + region_start = self.partInfo.PRIMARY_IMG_START + region_size = self.partInfo.PRIMARY_IMG_SIZE + elif load_type == TYPE_MCUBOOT: + if not self.partInfo.MCUBOOT_START or \ + not self.partInfo.MCUBOOT_SIZE: + print(f"Cannot find MCUBOOT_START and MCUBOOT_SIZE info") + sys.exit(1) + region_start = self.partInfo.MCUBOOT_START + region_size = self.partInfo.MCUBOOT_SIZE + extra_info = 'MCUBOOT' + elif load_type == TYPE_ATMWSTK: + if not self.partInfo.ATMWSTK_START or \ + not self.partInfo.ATMWSTK_SIZE: + print(f"Cannot find ATMWSTK_START and ATMWSTK_SIZE info") + sys.exit(1) + region_start = self.partInfo.ATMWSTK_START + region_size = self.partInfo.ATMWSTK_SIZE + extra_info = 'ATMWSTK' + else: + print(f"Unknown type {load_type}") + sys.exit(1) + # atm_isp loadRram [-h] [-i ARCHIVE] [-o NEW_ARCHIVE] [-v] + # [-mpr_start MPR_START] [-mpr_size MPR_SIZE] + # [-mpr_lock_size MPR_LOCK_SIZE] [-extrainfo EXTRAINFO] + # image [region_start] [region_size] [address] + cmd_arg = [self.atm_isp_exe_path, 'loadRram', '-i', input_file, + '-o', output_file, '-extrainfo', extra_info] + cmd_arg.append(filepath) + cmd_arg.append(region_start) + cmd_arg.append(region_size) + cmd_arg.append(base_addr) + return self.exe_cmd(cmd_arg) + + def add_flash(self, load_type, filepath, input_file, output_file): + if load_type == TYPE_NVDS: + if not self.partInfo.NVDS_START or not self.partInfo.NVDS_SIZE: + print(f"Cannot find NVDS_START and NVDS_SIZE info") + sys.exit(1) + region_start = self.partInfo.NVDS_START + region_size = self.partInfo.NVDS_SIZE + extra_info = 'NVDS' + elif load_type == TYPE_APP: + extra_info = 'SIGNED_APP' + if not self.partInfo.PRIMARY_IMG_START or \ + not self.partInfo.PRIMARY_IMG_SIZE: + print(f"Cannot find PRIMARY_IMG_START and " + "PRIMARY_IMG_SIZE info") + sys.exit(1) + region_start = self.partInfo.PRIMARY_IMG_START + region_size = self.partInfo.PRIMARY_IMG_SIZE + elif load_type == TYPE_MCUBOOT: + if not self.partInfo.MCUBOOT_START or \ + not self.partInfo.MCUBOOT_SIZE: + print(f"Cannot find MCUBOOT_START and MCUBOOT_SIZE info") + sys.exit(1) + region_start = self.partInfo.MCUBOOT_START + region_size = self.partInfo.MCUBOOT_SIZE + extra_info = 'MCUBOOT' + else: + print(f"Unknown type {load_type}") + sys.exit(1) + # atm_isp loadFlashNvds [-h] [-i ARCHIVE] [-o NEW_ARCHIVE] [-v] + # [-mpr_start MPR_START] [-mpr_size MPR_SIZE] + # [-mpr_lock_size MPR_LOCK_SIZE] [-extrainfo EXTRAINFO] + # image [region_start] [region_size] [address] + cmd_arg = [self.atm_isp_exe_path, 'loadFlashNvds', '-i', input_file, + '-o', output_file, '-extrainfo', extra_info] + cmd_arg.append(filepath) + cmd_arg.append(region_start) + cmd_arg.append(region_size) + return self.exe_cmd(cmd_arg) + + def add_extra(self, filepath, input_file, output_file): + img_type = 0 + # atm_isp cmdExtend [-h] [-i ARCHIVE] [-o NEW_ARCHIVE] [-v] + # [-extrainfo EXTRAINFO] image [type] + cmd_arg = [self.atm_isp_exe_path, 'cmdExtend', '-i', input_file, + '-o', output_file, '-extrainfo', 'LAYOUT_MAP'] + cmd_arg.append(filepath) + cmd_arg.append(f"{img_type}") + return self.exe_cmd(cmd_arg) + + def exe_cmd(self, cmd_arg): + cmd = ' '.join(cmd_arg) + if self.debug: + print(f"Executing [{cmd}]") + exit_code = os.system(cmd) + if exit_code != 0: + raise Exception(f"[{cmd}]command returned status [{exit_code}]") + + +class AtmArchCommand(WestCommand): + def __init__(self): + super().__init__( + 'atm_arch', + # Keep this in sync with the string in west-commands.yml. + 'Atmosic Archive flash required files and info', + "Atmosic Archive flash required files and info.", + accepts_unknown_args=True) + + def do_add_parser(self, parser_adder): + parser = parser_adder.add_parser( + self.name, + help=self.help, + formatter_class=argparse.RawDescriptionHelpFormatter, + description=self.description, + usage=ARCH_USAGE) + group = parser.add_argument_group('atm isp archive tool') + group.add_argument("-atm_isp_path", "--atm_isp_path", + required=True, default=None, + help="specify atm_isp exe path path") + group.add_argument("-d", "--debug", action='store_true', + help="debug enabled, default false") + group.add_argument("-s", "--show", action='store_true', + help="show archive") + group.add_argument("-b", "--burn", action='store_true', + help="burn archive") + group.add_argument("-a", "--append", action='store_true', + help="append to input atm file") + group.add_argument("-i", "--input_atm_file", + required=False, default=None, + help="input atm file path") + group.add_argument("-o", "--output_atm_file", + required=False, default=None, + help="output atm file path") + group.add_argument("-p", "--partition_info_file", + required=False, default=None, + help="partition info file path") + group.add_argument("-nvds_file", "--nvds_file", + required=False, default=None, + help="nvds file path") + group.add_argument("-spe_file", "--spe_file", + required=False, default=None, + help="spe file path") + group.add_argument("-app_file", "--app_file", + required=False, default=None, + help="application file path") + group.add_argument("-mcuboot_file", "--mcuboot_file", + required=False, default=None, + help="mcuboot file path") + group.add_argument("-atmwstk_file", "--atmwstk_file", + required=False, default=None, + help="atmwstk file path") + group.add_argument("-openocd_pkg_root", "--openocd_pkg_root", + required=False, default=None, + help="Path to directory where openocd and its " + "scripts are found") + group.add_argument("-dst_dir", "--dst_dir", + required=False, default=None, + help="Use this directory to dump openocd script in") + group.add_argument('-e', '--openocd_script_only', action='store_true', + help='Stop after preparing OpenOCD script') + return parser + + + def do_run(self, args, remainder): + if not os.path.exists(args.atm_isp_path): + print(f"{args.atm_isp_path} not exist") + sys.exit(1) + atmisp = AtmIsp(args.atm_isp_path, args.debug) + if args.show: + if not args.input_atm_file: + print(f"Required input_atm_file") + sys.exit(1) + if not os.path.exists(args.input_atm_file): + print(f"{args.input_atm_file} not exist") + sys.exit(1) + return atmisp.decode_atm(args.input_atm_file) + + if args.burn: + if args.dst_dir: + dst_dir = args.dst_dir + else: + dst_dir = None + if not args.input_atm_file: + print(f"Required input_atm_file") + sys.exit(1) + if not os.path.exists(args.input_atm_file): + print(f"{args.input_atm_file} not exist") + sys.exit(1) + if not args.openocd_pkg_root: + print(f"Required openocd_pkg_root") + sys.exit(1) + if not os.path.exists(args.openocd_pkg_root): + print(f"{args.openocd_pkg_root} not exist") + sys.exit(1) + return atmisp.burn_atm(args.input_atm_file, args.openocd_pkg_root, + None, dst_dir, args.openocd_script_only) + + if not args.partition_info_file: + print(f"Required partition_info_file") + sys.exit(1) + if not args.output_atm_file: + print(f"Required output_atm_file") + sys.exit(1) + if not os.path.exists(args.partition_info_file): + print(f"{args.partition_info_file} not exist") + sys.exit(1) + if args.append: + if not os.path.exists(args.input_atm_file): + print(f"{args.input_atm_file} not exist") + sys.exit(1) + input_file = args.input_atm_file + else: + input_file = args.output_atm_file + partInfo = AtmPartInfo() + partInfo.parse_info(args.partition_info_file) + atmisp.update_partInfo(partInfo) + if not args.append: + atmisp.init_atm(args.output_atm_file) + if args.nvds_file: + if not os.path.exists(args.nvds_file): + print(f"{args.nvds_file} not exist") + sys.exit(1) + + atmisp.append(TYPE_NVDS, args.nvds_file, input_file, + args.output_atm_file) + if args.spe_file: + if not os.path.exists(args.spe_file): + print(f"{args.spe_file} not exist") + sys.exit(1) + atmisp.append(TYPE_SPE, args.spe_file, input_file, + args.output_atm_file) + if args.app_file: + if not os.path.exists(args.app_file): + print(f"{args.app_file} not exist") + sys.exit(1) + atmisp.append(TYPE_APP, args.app_file, input_file, + args.output_atm_file) + if args.mcuboot_file: + if not os.path.exists(args.mcuboot_file): + print(f"{args.mcuboot_file} not exist") + sys.exit(1) + atmisp.append(TYPE_MCUBOOT, args.mcuboot_file, input_file, + args.output_atm_file) + if args.atmwstk_file: + if not os.path.exists(args.atmwstk_file): + print(f"{args.atmwstk_file} not exist") + sys.exit(1) + atmisp.append(TYPE_ATMWSTK, args.atmwstk_file, input_file, + args.output_atm_file) + atmisp.add_extra(args.partition_info_file, input_file, + args.output_atm_file) \ No newline at end of file diff --git a/west/atm_otp_west_extension.py b/west/atm_otp_west_extension.py new file mode 100644 index 0000000..ff0f36f --- /dev/null +++ b/west/atm_otp_west_extension.py @@ -0,0 +1,178 @@ +''' +@file atm_otp_west_extension.py + +@brief West extension for managing OTP + +Copyright (c) Atmosic 2024 +''' + +import binascii +import tempfile +from textwrap import dedent + +from west.commands import WestCommand, Verbosity +import os +import sys +sys.path.append(os.path.join(os.path.dirname( + os.path.dirname(os.path.abspath(__file__))), 'tools', 'scripts')) +from atm_otp.atm_otp import Atmx3_OTPArray, Atm34_OTPArray +import atm_openocd + +from atm_west_utils import wrap_color, TermColors +class AtmOtpCommand(WestCommand): + def __init__(self): + super().__init__( + 'atmotp', # gets stored as self.name + 'Interface with OTP on supported Atmosic chips', # self.help + # self.description: + dedent( + ''' + Interface with OTP on supported chips + + Allows users to read out OTP bits as well as burn them to configure devices. + ''' + ) + ) + + def create_default_subparser(self, subparsers, subcmd_str, help_str): + """adds subparser with default arguments. + + Args: + subparsers : subparser object + subcmd_str (str): name of sub command + help_str (str): help string + """ + s_parser = subparsers.add_parser(subcmd_str, help=help_str) + s_parser.add_argument('--jlink', default=True, required=False, action='store_true', + help='if using JLINK') + s_parser.add_argument('--device', required=True, + help='selects FTDI interface, e.g: ATRDIxxxx, or JLINK') + s_parser.add_argument('--board', required=True, + help='board to build for with optional board revision') + s_parser.add_argument('--openocd_config', required=False, + help='Specifies the config file for openocd') + s_parser.set_defaults(subcmd=subcmd_str) + return s_parser + + def do_add_parser(self, parser_adder): + parser = parser_adder.add_parser(self.name, + help=self.help, + description=self.description) + subparsers = parser.add_subparsers( + help='sub-command to run', required=True) + + list_otp_parser = self.create_default_subparser( + subparsers, 'list_otp', 'Lists available OTP bits to burn') + + dump_parser = self.create_default_subparser( + subparsers, 'dump', 'Dump all OTP data on specific device') + + burn_parser = self.create_default_subparser( + subparsers, 'burn', 'Burns a single OTP bit') + burn_parser.add_argument('--otp', + help="OTP Bit to burn, can either be either absolute index (e.g. 23) or . or .") + + get_parser = self.create_default_subparser( + subparsers, 'get', 'Retrieve value of OTP by name. (use `list_otp` target to get list of available OTP bits)') + get_parser.add_argument('--otp', + help=dedent(f'''\ + Either index (e.g. 23) or Name of specific OTP to retrieve + + If retrieving OTP by name and the OTP spans multiple bits, you can use OTP.sub_name or OTP.idx to get specific bit + (e.g. SEC_DBG_CONFIG.DEBUG_SECURED or SEC_DBG_CONFIG.1 to retrieve OTP bit 61) + ''' + ) + ) + + return parser + + def pull_otp(self): + '''Pulls OTP from device + ''' + self.openocd.reset_target() + tf = tempfile.NamedTemporaryFile('w+b') + cmd_ret, _, _ = self.openocd.execute_cmd([f'otp_dump_image {tf.name}']) + self.atm_otp = tf.read() + tf.close() + return cmd_ret + + def list_otp(self, args): + """List available OTP bits for a given device + + Args: + args: args passed at the command line + """ + print(self.OTParray().print_otp_array()) + + def burn(self, args): + """Burn OTP bits for a given device + + Args: + args: args passed at the command line + """ + self.pull_otp() + otpArray = self.OTParray(self.atm_otp) + otp, idx = otpArray.get_otp_group_and_idx(args.otp) + if idx is None: + raise RuntimeError("Can only burn single bits at a time. Cannot burn an entire multi-bit OTP config. " + "Please use . to burn a single bit") + curr_val = otp.get_idx(idx) + if curr_val == 1: + raise RuntimeError( + "OTP bit already blown. Cannot re-burn OTP bits") + + print(wrap_color( + "WARNING: This is an irreversible process. Once burned, OTP bits cannot be reversed", TermColors.RED)) + print(wrap_color(f"Current value of otp: {otp}", TermColors.RED)) + otp.value |= (1 << idx) + print(wrap_color(f"New value of otp: {otp}", TermColors.RED)) + print(f"Are you sure you want to burn {otp.name}.{idx}?") + answer = input() + if answer.lower() == "no": + return + if answer.lower() != "yes": + print("Please enter yes or no.") + return + # dont know the format of the commandline input, calculate absolute idx + abs_idx = otp.idx + idx + self.openocd.reset_target() + self.openocd.execute_cmd([f'otp_burn_bit {abs_idx}']) + + def get(self, args): + """get OTP bit for a given device + + Args: + args: args passed at the command line + """ + self.pull_otp() + otpArray = self.OTParray(self.atm_otp) + print(otpArray.get_otp_bits(args.otp)) + + def dump(self, args): + """Dumps OTP bits from device + + Args: + args: args passed at the command line + """ + self.pull_otp() + print(self.OTParray(self.atm_otp)) + + def do_run(self, args, unknown_args): + self.board = args.board + + plat_dir = atm_openocd.get_atm_plat_dir_from_board(self.board) + if (plat_dir == "ATM33xx-5"): + self.OTParray = Atmx3_OTPArray + elif ("ATM34xx" in self.atm_plat): + self.OTParray = Atm34_OTPArray + else: + raise RuntimeError("Unsupported platform") + + try: + self.openocd = atm_openocd.AtmOpenOCD(self.board, args.device, args.jlink, openocd_cfg=args.openocd_config) + except: + raise RuntimeError("Invalid configuration. Please use supported device") + + subcmd = getattr(self, args.subcmd) + subcmd(args) + diff --git a/west/atm_west_utils.py b/west/atm_west_utils.py new file mode 100644 index 0000000..1d89d15 --- /dev/null +++ b/west/atm_west_utils.py @@ -0,0 +1,37 @@ +''' +@file atm_west_utils.py + +@brief Common utility functions for Atmosic west extensions + +Copyright (c) Atmosic 2024 +''' + +from enum import Enum + +class TermColors(Enum): + """Terminal Colors for pretty printing + """ + HEADER = '\033[95m' + OKBLUE = '\033[94m' + OKCYAN = '\033[96m' + OKGREEN = '\033[92m' + WARNING = '\033[93m' + RED = '\033[91m' + ENDC = '\033[0m' + BOLD = '\033[1m' + UNDERLINE = '\033[4m' + MAGENTA = '\u001b[35m' + + +def wrap_color(print_str: str, color: TermColors) -> str: + """wrap a string in a specific terminal color + + Args: + print_str (str): string to wrap in a color + color (TermColors): Terminal color + + Returns: + str: colorified string + """ + return f"{color.value}{print_str}{TermColors.ENDC.value}" + diff --git a/west/sec_jrnl_west_extension.py b/west/sec_jrnl_west_extension.py new file mode 100644 index 0000000..737ecf0 --- /dev/null +++ b/west/sec_jrnl_west_extension.py @@ -0,0 +1,290 @@ +''' +@file sec_jrnl_west_ext.py + +@brief West extension for managing secure journal + +Copyright (c) Atmosic 2024 +''' + +import binascii +import codecs +import subprocess +import tempfile +from textwrap import dedent +from west.util import quote_sh_list +from atm_west_utils import wrap_color, TermColors +import argparse +from west.commands import WestCommand, Verbosity +from os import path +import os +import sys +sys.path.append(os.path.join(os.path.dirname(os.path.dirname(os.path.abspath(__file__))), 'tools', 'scripts')) +import atm_openocd +from sec_jrnl_tlv.sec_jrnl_tlv import SecJrnl + +def auto_int(x): + """arg parse type that parses all int types when passes as param""" + return int(x, 0) + +def unescaped_str(arg_str): + return codecs.decode(str(arg_str), 'unicode_escape') + + +class SecJrnlCommand(WestCommand): + + def __init__(self): + super().__init__( + 'secjrnl', # gets stored as self.name + 'Interface with secure journal on supported chips', # self.help + # self.description: + dedent(''' + Interface with secure journal on supported chips . + + Allows users to manage the secure journal through a variety of sub + commands.''')) + self.sec_jrnl = None + + def create_default_subparser(self, subparsers, subcmd_str, help_str): + """adds subparser with default arguments. + + Args: + subparsers : subparser object + subcmd_str (str): name of sub command + help_str (str): help string + """ + s_parser = subparsers.add_parser(subcmd_str, help=help_str) + s_parser.add_argument('--jlink', default=True, required=False, action='store_true', + help='if using JLINK') + s_parser.add_argument('--device', required=True, + help='selects FTDI interface, e.g: ATRDIxxxx, or JLINK') + s_parser.add_argument('--board', required=True, + help='board to build for with optional board revision') + s_parser.add_argument('--openocd_config', required=False, + help='Specifies the config file for openocd') + s_parser.set_defaults(subcmd=subcmd_str) + return s_parser + + def do_add_parser(self, parser_adder): + parser = parser_adder.add_parser(self.name, + help=self.help, + description=self.description) + subparsers = parser.add_subparsers( + help='sub-command to run', required=True) + + dump_parser = self.create_default_subparser( + subparsers, 'dump', 'Dump all TLVs from the secure journal') + dump_parser.add_argument('-b','--binary', default=False, required=False, + action='store_true', help='Dump secure jrnl as raw bin') + dump_parser.add_argument('--hex', default=False, required=False, + action='store_true', help='Dump secure jrnl as hex') + + get_parser = self.create_default_subparser( + subparsers, 'get', 'Get individual TLV from secure journal') + get_parser.add_argument('--tag', required=True, type=auto_int, help='Tag for TLV') + + self.create_default_subparser( + subparsers, 'erase', 'Erase all non-ratcheted TLVs from the secure journal') + self.create_default_subparser( + subparsers, 'get_ratchet', 'Return secure ratchet index') + + append_parser = self.create_default_subparser( + subparsers, 'append', 'Appends a single TLV to the secure journal') + append_parser.add_argument('--tag', required=True, type=auto_int, help='Tag for TLV') + append_parser.add_argument('--data', required=True, type=unescaped_str, help='Data for TLV') + append_parser.add_argument('--locked', default=False, required=False, + action='store_true', + help='Lock down tag, prevent overriding') + append_parser.add_argument('--dry-run', default=False, required=False, + action='store_true', + help='Append tag but dont push to device') + ratchet_jrnl_parser = self.create_default_subparser( + subparsers, 'ratchet_jrnl', 'Increment secure ratchet index') + ratchet_jrnl_parser.add_argument('-y', default=False, required=False, + action='store_true', help='Skip user input and ratchet Secure Journal') + create_parser = subparsers.add_parser('create', help="Build a local secure journal binary file") + create_parser.add_argument('--len', type=auto_int, required=False, help='Length of outputed bin file', default=1776) + create_parser.add_argument('-t', '--tag', type=auto_int, required=False, action='append', + help='tag to append, each tag and data will be processed sequentially') + create_parser.add_argument('-d', '--data', type=unescaped_str, required=False, help='tag data to append.', action='append') + create_parser.add_argument('--board', required=True, + help='board to build for with optional board revision') + create_parser.add_argument('-o', '--outfile', required=False, type=argparse.FileType('wb'), default='-') + + create_parser.set_defaults(subcmd='create') + + return parser + + def pull_sec_jrnl(self, force=False): + '''Pulls secure journal from device + + Args: + force (bool, optional): force pull sec_jrnl nvds even if local copy exists. Defaults to False. + ''' + self.openocd.reset_target() + if (self.sec_jrnl is None) or (force): + tf = tempfile.NamedTemporaryFile('w+b') + cmd_ret, _, _ = self.openocd.execute_cmd([f'atm_dump_sec_jrnl_nvds {tf.name}']) + self.sec_jrnl = tf.read() + tf.close() + return cmd_ret + + def push_sec_jrnl(self, bin): + '''Push secure journal from device + ''' + tf = tempfile.NamedTemporaryFile('w+b') + tf.write(bin) + tf.flush() + cmd_ret, _, _ = self.openocd.execute_cmd([f'atm_load_sec_jrnl_nvds {tf.name}']) + tf.close() + return cmd_ret + + def append(self, args): + '''Append tag to secure journal. DOES NOT INCR RATCHET + + Args: + args: args passed at the command line + + ''' + self.pull_sec_jrnl() + sec_jrnl = SecJrnl(self.sec_jrnl) + locked = args.locked + old_tlv = sec_jrnl.get(args.tag) + if (old_tlv is not None) and old_tlv.status.locked: + raise RuntimeError(f"Existing tag ({old_tlv.tag}) is already locked down in Secure Journal. Cannot overwrite with new data.") + + if (hasattr(sec_jrnl, 'is_secure_tag')) and sec_jrnl.is_secure_tag(args.tag): + print(f"\nWARNING: Tag {wrap_color(hex(args.tag), TermColors.BOLD)} is a user-secure tag. This means the tag can only be accessed via the secure application.") + print(f"All user-secure tags {wrap_color('must', TermColors.BOLD)} be locked. You will not be able to update this value after ratcheting") + print("Are you sure you want this?") + answer = input() + if answer.lower() == "no": + return + if answer.lower() != "yes": + print("Please enter yes or no.") + return + # secure-only tags MUST be locked down - force it. + locked = True + sec_jrnl.append_tag(args.tag, args.data.encode('ascii'), locked) + if (args.dry_run): + print(sec_jrnl) + else: + self.push_sec_jrnl(sec_jrnl.bin) + + def create(self, args): + '''Create a brand new secure journal bin file. + + Note: The `create` target is used to build binary files locally. If the + device already has entries in the secure journal, you will not be + able to use the output of this function + + Args: + args: args passed at the command line + ''' + sec_jrnl = SecJrnl(max_len=args.len) + if len(args.tag) != len(args.data): + raise RuntimeError("There must be an equal number of --data flags to --tag flags.") + for tag, data in zip(args.tag, args.data): + tag_data = data + if os.path.isfile(data): + with open(data, 'rb') as fd: + tag_data = bytes(fd.read()) + else: + tag_data = bytes.fromhex("".join("{:02x}".format(ord(c)) for c in data)) + sec_jrnl.append_tag(tag, tag_data, False) + args.outfile.write(sec_jrnl.raw_bin) + args.outfile.flush() + args.outfile.close() + + + def dump(self, args): + """Dumps secure journal from device + + Args: + args: args passed at the command line + """ + self.pull_sec_jrnl() + if args.binary: + print(self.sec_jrnl) + elif args.hex: + print(binascii.b2a_hex(SecJrnl(self.sec_jrnl).bin).decode("utf-8")) + else: + print(SecJrnl(self.sec_jrnl)) + + def get(self, args): + """Returns single TLV from secure journal + + Args: + args: args passed at the command line + """ + self.pull_sec_jrnl() + tlv = SecJrnl(self.sec_jrnl).get(args.tag) + if tlv is None: + raise RuntimeError("TLV does not exist on device") + print(tlv) + + def erase(self, args): + """Erases non-ratcheted secure journal + + Args: + args: args passed at the command line + """ + self.openocd.reset_target() + _,_,cmd_stderr = self.openocd.execute_cmd(['atm_erase_sec_jrnl_nvds']) + print(cmd_stderr.decode("utf-8")) + + def _get_ratchet(self): + self.openocd.reset_target() + _,_,cmd_stderr = self.openocd.execute_cmd(['atm_sec_jrnl_get_ratchet']) + # TODO: handle return string output better. + return auto_int(cmd_stderr.decode().split()[-1]) + + def get_ratchet(self, args): + """Get secure ratchet index + + Args: + args: args passed at the command line + """ + ratchet_val = self._get_ratchet() + # TODO: handle return string output better. + print(f"Secure Counter = {ratchet_val}") + + def ratchet_jrnl(self, args): + """Increment secure ratchet index + + Args: + args: args passed at the command line + """ + self.pull_sec_jrnl() + sec_jrnl = SecJrnl(self.sec_jrnl) + # check current ratchet value + ratchet_val = self._get_ratchet() + new_ratchet_val = sec_jrnl.ratchet_idx + if (ratchet_val == new_ratchet_val): + raise RuntimeError("No unratcheted tags found. Cannot ratchet empty data." + "Please append new tags before attempting to ratchet_jrnl") + if not args.y: + print(f"WARNING: The following tags will be ratcheted down:") + for tag in iter(sec_jrnl): + if tag.idx >= ratchet_val: + print(f"\t{tag}{wrap_color(' ; Note: this tag is LOCKED and cannot be updated if you ratchet', TermColors.RED) if tag.status.locked else ''}") + print(f"Are you sure you want to increment the ratchet index from {ratchet_val} to {new_ratchet_val}?") + answer = input() + if answer.lower() == "no": + return + if answer.lower() != "yes": + print("Please enter yes or no.") + return + self.openocd.reset_target() + self.openocd.execute_cmd(f'atm_sec_jrnl_incr_ratchet_to {new_ratchet_val}') + + def do_run(self, args, unknown_args): + self.board = args.board + # If we need to interact with a physical device, set openocd. + if hasattr(args, 'device'): + try: + self.openocd = atm_openocd.AtmOpenOCD(self.board, args.device, args.jlink, openocd_cfg=args.openocd_config) + except: + raise RuntimeError("Invalid configuration. Please use supported device") + + subcmd = getattr(self, args.subcmd) + subcmd(args) diff --git a/west/tests/__init__.py b/west/tests/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/west/tests/test_atm_arch_west_extension.py b/west/tests/test_atm_arch_west_extension.py new file mode 100644 index 0000000..b765328 --- /dev/null +++ b/west/tests/test_atm_arch_west_extension.py @@ -0,0 +1,154 @@ +''' +@file test_atm_arch_west_extension.py + +@brief Unit test for atm_arch west extension + +Copyright (c) Atmosic 2024 +''' + +import os +import subprocess +import sys +import pytest + + +@pytest.fixture +def atm_arch_base_cmd(): + return ["west", "atm_arch"] + + +@pytest.fixture() +def atm_arch_show_args(atm_arch_base_cmd): + return atm_arch_base_cmd + ["--show"] + + +@pytest.fixture() +def atm_arch_show_extra_args(atm_arch_base_cmd): + assert os.environ.get('ATM_ISP_FILE') is not None + assert os.environ.get('INPUT_ATM_FILE') is not None + return ['--atm_isp_path', os.environ.get('ATM_ISP_PATH'), + '--input_atm_file', os.environ.get('INPUT_ATM_FILE')] + + +@pytest.fixture() +def atm_arch_burn_args(atm_arch_base_cmd): + return atm_arch_base_cmd + ["--burn"] + + +@pytest.fixture() +def atm_arch_burn_extra_args(): + assert os.environ.get('ATM_ISP_FILE') is not None + assert os.environ.get('OPENOCD_PKG_ROOT') is not None + assert os.environ.get('INPUT_ATM_FILE') is not None + return ['--atm_isp_path', os.environ.get('ATM_ISP_PATH'), + '--input_atm_file', os.environ.get('INPUT_ATM_FILE'), + '--openocd_pkg_root', os.environ.get('OPENOCD_PKG_ROOT')] + + +@pytest.fixture() +def atm_arch_create_args(atm_arch_base_cmd): + return atm_arch_base_cmd + + +@pytest.fixture() +def atm_arch_create_extra_args(): + assert os.environ.get('ATM_ISP_FILE') is not None + assert os.environ.get('PATITION_INFO_FILE') is not None + assert os.environ.get('OUTPUT_ATM_FILE') is not None + return ['--atm_isp_path', os.environ.get('ATM_ISP_PATH'), + '--partition_info_file', os.environ.get('PATITION_INFO_FILE'), + '--output_atm_file', os.environ.get('OUTPUT_ATM_FILE')] + + +@pytest.fixture() +def atm_arch_append_args(atm_arch_base_cmd): + return atm_arch_base_cmd + ["--append"] + + +@pytest.fixture() +def atm_arch_append_extra_args(): + extra_args = [] + assert os.environ.get('ATM_ISP_FILE') is not None + extra_args.append('--atm_isp_path') + extra_args.append(os.environ.get('ATM_ISP_FILE')) + assert os.environ.get('INPUT_ATM_FILE') is not None + extra_args.append('--input_atm_file') + extra_args.append(os.environ.get('OUTPUT_ATM_FILE')) + assert os.environ.get('PATITION_INFO_FILE') is not None + extra_args.append('--partition_info_file') + extra_args.append(os.environ.get('PATITION_INFO_FILE')) + assert os.environ.get('OUTPUT_ATM_FILE') is not None + extra_args.append('--output_atm_file') + extra_args.append(os.environ.get('OUTPUT_ATM_FILE')) + if os.environ.get('NVDS_FILE') is not None: + extra_args.append('--nvds_file') + extra_args.append(os.environ.get('NVDS_FILE')) + if os.environ.get('SPE_FILE') is not None: + extra_args.append('--spe_file') + extra_args.append(os.environ.get('SPE_FILE')) + if os.environ.get('APP_FILE') is not None: + extra_args.append('--app_file') + extra_args.append(os.environ.get('APP_FILE')) + if os.environ.get('MCUBOOT_FILE') is not None: + extra_args.append('--mcuboot_file') + extra_args.append(os.environ.get('MCUBOOT_FILE')) + if os.environ.get('ATMWSTK_FILE') is not None: + extra_args.append('--atmwstk_file') + extra_args.append(os.environ.get('ATMWSTK_FILE')) + return extra_args + + +def test_atm_arch_show(atm_arch_show_args, atm_arch_show_extra_args): + '''Tests atm_arch subcmd: show.''' + # show contents of file + with pytest.raises(Exception): + subprocess.run(atm_arch_show_args, + check=True, + capture_output=True) + subproc_cmd = atm_arch_show_args + atm_arch_show_extra_args + # test just sanity checks the commands do not fail. + subprocess.run(subproc_cmd, + check=True, + capture_output=True) + + +def test_atm_arch_burn(atm_arch_burn_args, atm_arch_burn_extra_args): + '''Tests atm_arch subcmd: burn.''' + # show contents of file + with pytest.raises(Exception): + subprocess.run(atm_arch_show_args, + check=True, + capture_output=True) + subproc_cmd = atm_arch_burn_args + atm_arch_burn_extra_args + # test just sanity checks the commands do not fail. + subprocess.run(subproc_cmd, + check=True, + capture_output=True) + + +def test_atm_arch_create(atm_arch_create_args, atm_arch_create_extra_args): + '''Tests atm_arch subcmd: create.''' + # show contents of file + with pytest.raises(Exception): + subprocess.run(atm_arch_show_args, + check=True, + capture_output=True) + subproc_cmd = atm_arch_create_args + atm_arch_create_extra_args + # test just sanity checks the commands do not fail. + subprocess.run(subproc_cmd, + check=True, + capture_output=True) + + +def test_atm_arch_append(atm_arch_append_args, atm_arch_append_extra_args): + '''Tests atm_arch subcmd: append.''' + # show contents of file + with pytest.raises(Exception): + subprocess.run(atm_arch_show_args, + check=True, + capture_output=True) + subproc_cmd = atm_arch_append_args + atm_arch_append_extra_args + # test just sanity checks the commands do not fail. + subprocess.run(subproc_cmd, + check=True, + capture_output=True) diff --git a/west/tests/test_atm_otp_west_extension.py b/west/tests/test_atm_otp_west_extension.py new file mode 100644 index 0000000..1553fbe --- /dev/null +++ b/west/tests/test_atm_otp_west_extension.py @@ -0,0 +1,108 @@ +''' +@file test_atm_otp_west_extension.py + +@brief Unit test for atmotp west extension + +Copyright (c) Atmosic 2024 +''' + +import os +import subprocess +import sys +import pytest +import re + + +@pytest.fixture +def atmotp_base_cmd(): + return ["west", "atmotp"] + + +@pytest.fixture(autouse=True) +def atmotp_base_subcmd_args(): + assert os.environ.get('BOARD') is not None + assert os.environ.get('JLINK_SERIAL') is not None + return ["--board", os.environ.get('BOARD'), "--device", os.environ.get('JLINK_SERIAL')] + + +@pytest.fixture() +def atmotp_dump_args(atmotp_base_cmd): + return atmotp_base_cmd + ["dump"] + + +@pytest.fixture() +def atmotp_list_otp_args(atmotp_base_cmd): + return atmotp_base_cmd + ["list_otp"] + + +@pytest.fixture() +def atmotp_get_args(atmotp_base_cmd): + return atmotp_base_cmd + ["get"] + + +def test_atmotp_list_otp(atmotp_list_otp_args, atmotp_base_subcmd_args): + '''Tests atmotp subcmd: list_otp.''' + # Verify that the command fails without the proper flags + with pytest.raises(Exception): + subprocess.run(atmotp_list_otp_args, + check=True, + capture_output=True) + + subproc_cmd = atmotp_list_otp_args + atmotp_base_subcmd_args + # Each board will have a differernt output so this test just sanity checks the commands + # do not fail. The output cannot really be tested easily + subprocess.run(subproc_cmd, + check=True, + capture_output=True) + + +def test_atmotp_dump(atmotp_dump_args, atmotp_base_subcmd_args): + '''Tests atmotp subcmd: dump.''' + # Verify that the command fails without the proper flags + with pytest.raises(Exception): + subprocess.run(atmotp_dump_args, + check=True, + capture_output=True) + subproc_cmd = atmotp_dump_args + atmotp_base_subcmd_args + subprocess.run(subproc_cmd, + check=True, + capture_output=True) + + +def test_atmotp_get(atmotp_get_args, atmotp_base_subcmd_args): + '''Tests atmotp subcmd: get commands''' + # Verify that the command fails without the proper flags + with pytest.raises(Exception): + subprocess.run(atmotp_get_args, + check=True, + capture_output=True) + subproc_cmd = atmotp_get_args + atmotp_base_subcmd_args + call = subprocess.run(subproc_cmd + ["--otp", "RRAM_WRITE_LOCK"], + check=True, + capture_output=True) + bin_output = call.stdout.split(b"\n")[1].decode(encoding='utf-8', errors='strict') # strip OpenOCD print + expected_len = 7 + assert re.search(fr"0b[0-1]{{{expected_len}}}", bin_output) + call = subprocess.run(subproc_cmd + ["--otp", "53"], + check=True, + capture_output=True) + + bin_output_53 = call.stdout.split(b"\n")[1].decode(encoding='utf-8', errors='strict') # strip OpenOCD print + expected_len = 1 + assert re.search(fr"0b[0-1]{{{expected_len}}}", bin_output_53) + call = subprocess.run(subproc_cmd + ["--otp", "RRAM_WRITE_LOCK.5"], + check=True, + capture_output=True) + bin_output_RRAM_WRITE_LOCK_5 = call.stdout.split( + b"\n")[1].decode(encoding='utf-8', errors='strict') # strip OpenOCD print + expected_len = 1 + assert re.search(fr"0b[0-1]{{{expected_len}}}", bin_output_RRAM_WRITE_LOCK_5) + call = subprocess.run(subproc_cmd + ["--otp", "RRAM_WRITE_LOCK.SECURE_COUNTERS"], + check=True, + capture_output=True) + bin_output_RRAM_WRITE_LOCK_SECURE_COUNTERS = call.stdout.split(b"\n")[ + 1].decode(encoding='utf-8', errors='strict') # strip OpenOCD print + expected_len = 1 + assert re.search(fr"0b[0-1]{{{expected_len}}}", + bin_output_RRAM_WRITE_LOCK_SECURE_COUNTERS) + assert bin_output_53 == bin_output_RRAM_WRITE_LOCK_5 == bin_output_RRAM_WRITE_LOCK_SECURE_COUNTERS diff --git a/west/tests/test_sec_jrnl_west_extension.py b/west/tests/test_sec_jrnl_west_extension.py new file mode 100644 index 0000000..92b1ea1 --- /dev/null +++ b/west/tests/test_sec_jrnl_west_extension.py @@ -0,0 +1,143 @@ +''' +@file test_sec_jrnl_west_extension.py + +@brief Unit test for secjrnl west extension + +Copyright (c) Atmosic 2024 +''' + +import os +import subprocess +import sys +import pytest + +@pytest.fixture +def secjrnl_base_cmd(): + return ["west", "secjrnl"] + +@pytest.fixture(autouse=True) +def secjrnl_base_subcmd_args(): + assert os.environ.get('BOARD') is not None + assert os.environ.get('JLINK_SERIAL') is not None + return ["--board", os.environ.get('BOARD'), "--device", os.environ.get('JLINK_SERIAL')] + +@pytest.fixture() +def secjrnl_dump_args(secjrnl_base_cmd): + return secjrnl_base_cmd + ["dump"] + +@pytest.fixture() +def secjrnl_append_args(secjrnl_base_cmd): + return secjrnl_base_cmd + ["append"] + +@pytest.fixture() +def secjrnl_get_args(secjrnl_base_cmd): + return secjrnl_base_cmd + ["get"] + +@pytest.fixture() +def secjrnl_get_ratchet_args(secjrnl_base_cmd): + return secjrnl_base_cmd + ["get_ratchet"] + +@pytest.fixture() +def secjrnl_erase_args(secjrnl_base_cmd): + return secjrnl_base_cmd + ["erase"] + + +def test_secjrnl_dump(secjrnl_dump_args, secjrnl_base_subcmd_args): + '''Tests secjrnl subcmd: dump.''' + # Verify that the command fails without the proper flags + with pytest.raises(Exception): + subprocess.run(secjrnl_dump_args, + check=True, + capture_output=True) + + subproc_cmd = secjrnl_dump_args + secjrnl_base_subcmd_args + # Each board will have a differernt output so this test just sanity checks the commands + # do not fail. The output cannot really be tested easily + subprocess.run(subproc_cmd, + check=True, + capture_output=True) + subprocess.run(subproc_cmd + ["--binary"], + check=True, + capture_output=True) + subprocess.run(subproc_cmd + ["--hex"], + check=True, + capture_output=True) + +def test_secjrnl_get_ratchet(secjrnl_get_ratchet_args, secjrnl_base_subcmd_args): + '''Tests secjrnl subcmd: append.''' + # Verify that the command fails without the proper flags + with pytest.raises(Exception): + subprocess.run(secjrnl_get_ratchet_args, + check=True, + capture_output=True) + subproc_cmd = secjrnl_get_ratchet_args + secjrnl_base_subcmd_args + call = subprocess.run(subproc_cmd, + check=True, + capture_output=True) + # Verify the output of the command includes the expected output + assert b"Secure Counter =" in call.stdout + +def test_secjrnl_get_append(secjrnl_append_args, secjrnl_get_args, secjrnl_base_subcmd_args): + '''Tests secjrnl subcmd: append and get commands''' + # Verify that the command fails without the proper flags + with pytest.raises(Exception): + subprocess.run(secjrnl_append_args, + check=True, + capture_output=True) + subproc_cmd = secjrnl_append_args + secjrnl_base_subcmd_args + call = subprocess.run(subproc_cmd + ["--tag", "0x01", "--data", "\x68\x65\x6c\x6c\x6f"], + check=True, + capture_output=True) + call = subprocess.run(secjrnl_get_args + secjrnl_base_subcmd_args + ["--tag", "0x01"], + check=True, + capture_output=True) + + assert b"tag:(01)" in call.stdout + +def test_secjrnl_get_erase(secjrnl_erase_args, secjrnl_append_args, secjrnl_get_args, secjrnl_base_subcmd_args): + # Verify that the command fails without the proper flags + with pytest.raises(Exception): + subprocess.run(secjrnl_erase_args, + check=True, + capture_output=True) + subproc_erase_cmd = secjrnl_erase_args + secjrnl_base_subcmd_args + subproc_append_cmd = secjrnl_append_args + secjrnl_base_subcmd_args + subproc_get_cmd = secjrnl_get_args + secjrnl_base_subcmd_args + call = subprocess.run(subproc_append_cmd + ["--tag", "0x05", "--data", "\x68\x65\x6c\x6c\x6f"], + check=True, + capture_output=True) + call = subprocess.run(subproc_append_cmd + ["--tag", "0x06", "--data", "\x68\x65\x6c\x6c\x6f"], + check=True, + capture_output=True) + call = subprocess.run(subproc_append_cmd + ["--tag", "0x07", "--data", "\x68\x65\x6c\x6c\x6f"], + check=True, + capture_output=True) + # Sanity check all three tags were appended. + call = subprocess.run(subproc_get_cmd + ["--tag", "0x05"], + check=True, + capture_output=True) + assert b"tag:(05)" in call.stdout + call = subprocess.run(subproc_get_cmd + ["--tag", "0x06"], + check=True, + capture_output=True) + assert b"tag:(06)" in call.stdout + call = subprocess.run(subproc_get_cmd + ["--tag", "0x07"], + check=True, + capture_output=True) + assert b"tag:(07)" in call.stdout + + call = subprocess.run(subproc_erase_cmd, + check=True, + capture_output=True) + with pytest.raises(Exception): + subprocess.run(subproc_get_cmd + ["--tag", "0x05"], + check=True, + capture_output=True) + with pytest.raises(Exception): + subprocess.run(subproc_get_cmd + ["--tag", "0x06"], + check=True, + capture_output=True) + with pytest.raises(Exception): + subprocess.run(subproc_get_cmd + ["--tag", "0x07"], + check=True, + capture_output=True) \ No newline at end of file diff --git a/west/west-commands.yml b/west/west-commands.yml new file mode 100644 index 0000000..a56529b --- /dev/null +++ b/west/west-commands.yml @@ -0,0 +1,16 @@ +west-commands: + - file: west/sec_jrnl_west_extension.py + commands: + - name: secjrnl + class: SecJrnlCommand + help: Atmosic tools for secure journal management. + - file: west/atm_otp_west_extension.py + commands: + - name: atmotp + class: AtmOtpCommand + help: Atmosic tools for OTP management. + - file: west/atm_arch_extension.py + commands: + - name: atm_arch + class: AtmArchCommand + help: Atmosic ISP file generate, show and program with bin files diff --git a/zephyr/module.yml b/zephyr/module.yml new file mode 100644 index 0000000..44b80b9 --- /dev/null +++ b/zephyr/module.yml @@ -0,0 +1,7 @@ +# Copyright (c) 2021-2024 Atmosic +# +# SPDX-License-Identifier: Apache-2.0 + +build: + cmake: . + kconfig: Kconfig