diff --git a/AXI/AXI.bsv b/AXI/AXI.bsv index e9f91ea..7c39475 100644 --- a/AXI/AXI.bsv +++ b/AXI/AXI.bsv @@ -1,8 +1,11 @@ /*- * Copyright (c) 2018 Alexandre Joannou + * Copyright (c) 2021 Ivan Ribeiro * All rights reserved. * - * This software was developed by SRI International and the University of + * This hardware design was developed by the University of Cambridge Computer + * Laboratory (Department of Computer Science and Technology) under EPSRC award + * EP/S030867/1 ("SIPP"); and by SRI International and the University of * Cambridge Computer Laboratory (Department of Computer Science and * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the * DARPA SSITH research programme. @@ -28,7 +31,7 @@ package AXI; -import AXI4_AXI4Lite_Types :: *; +import AXI4_Common_Types :: *; import AXI4_Types :: *; import AXI4_AW_Utils :: *; import AXI4_W_Utils :: *; @@ -47,7 +50,7 @@ import AXI4Lite_Utils :: *; import AXI4Lite_Interconnect :: *; import AXI4_AXI4Lite_Bridges :: *; -export AXI4_AXI4Lite_Types :: *; +export AXI4_Common_Types :: *; export AXI4_Types :: *; export AXI4_AW_Utils :: *; export AXI4_W_Utils :: *; diff --git a/AXI/AXI4.bsv b/AXI/AXI4.bsv index 10ac152..0385eb8 100644 --- a/AXI/AXI4.bsv +++ b/AXI/AXI4.bsv @@ -1,8 +1,11 @@ /*- * Copyright (c) 2018 Alexandre Joannou + * Copyright (c) 2021 Ivan Ribeiro * All rights reserved. * - * This software was developed by SRI International and the University of + * This hardware design was developed by the University of Cambridge Computer + * Laboratory (Department of Computer Science and Technology) under EPSRC award + * EP/S030867/1 ("SIPP"); and by SRI International and the University of * Cambridge Computer Laboratory (Department of Computer Science and * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the * DARPA SSITH research programme. @@ -28,7 +31,7 @@ package AXI4; -import AXI4_AXI4Lite_Types :: *; +import AXI4_Common_Types :: *; import AXI4_Types :: *; import AXI4_AW_Utils :: *; import AXI4_W_Utils :: *; @@ -38,7 +41,7 @@ import AXI4_R_Utils :: *; import AXI4_Utils :: *; import AXI4_Interconnect :: *; -export AXI4_AXI4Lite_Types :: *; +export AXI4_Common_Types :: *; export AXI4_Types :: *; export AXI4_AW_Utils :: *; export AXI4_W_Utils :: *; diff --git a/AXI/AXI4Lite.bsv b/AXI/AXI4Lite.bsv index aea5eb5..8c06dda 100644 --- a/AXI/AXI4Lite.bsv +++ b/AXI/AXI4Lite.bsv @@ -1,8 +1,11 @@ /*- * Copyright (c) 2018 Alexandre Joannou + * Copyright (c) 2021 Ivan Ribeiro * All rights reserved. * - * This software was developed by SRI International and the University of + * This hardware design was developed by the University of Cambridge Computer + * Laboratory (Department of Computer Science and Technology) under EPSRC award + * EP/S030867/1 ("SIPP"); and by SRI International and the University of * Cambridge Computer Laboratory (Department of Computer Science and * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the * DARPA SSITH research programme. @@ -28,7 +31,7 @@ package AXI4Lite; -import AXI4_AXI4Lite_Types :: *; +import AXI4_Common_Types :: *; import AXI4Lite_Types :: *; import AXI4Lite_AW_Utils :: *; import AXI4Lite_W_Utils :: *; @@ -38,7 +41,7 @@ import AXI4Lite_R_Utils :: *; import AXI4Lite_Utils :: *; import AXI4Lite_Interconnect :: *; -export AXI4_AXI4Lite_Types :: *; +export AXI4_Common_Types :: *; export AXI4Lite_Types :: *; export AXI4Lite_AW_Utils :: *; export AXI4Lite_W_Utils :: *; diff --git a/AXI/AXI4Lite_Types.bsv b/AXI/AXI4Lite_Types.bsv index 9208b1e..2295216 100644 --- a/AXI/AXI4Lite_Types.bsv +++ b/AXI/AXI4Lite_Types.bsv @@ -1,8 +1,11 @@ /*- * Copyright (c) 2018-2021 Alexandre Joannou + * Copyright (c) 2021 Ivan Ribeiro * All rights reserved. * - * This software was developed by SRI International and the University of + * This hardware design was developed by the University of Cambridge Computer + * Laboratory (Department of Computer Science and Technology) under EPSRC award + * EP/S030867/1 ("SIPP"); and by SRI International and the University of * Cambridge Computer Laboratory (Department of Computer Science and * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the * DARPA SSITH research programme. @@ -35,7 +38,7 @@ import Routable :: *; import SourceSink :: *; import MasterSlave :: *; -import AXI4_AXI4Lite_Types :: *; +import AXI4_Common_Types :: *; //////////////////////////////////// // AXI4Lite Address Write Channel // diff --git a/AXI/AXI4Stream.bsv b/AXI/AXI4Stream.bsv new file mode 100644 index 0000000..56f76a6 --- /dev/null +++ b/AXI/AXI4Stream.bsv @@ -0,0 +1,41 @@ +/*- + * Copyright (c) 2021 Ivan Ribeiro + * All rights reserved. + * + * This hardware design was developed by the University of Cambridge Computer + * Laboratory (Department of Computer Science and Technology) under EPSRC award + * EP/S030867/1 ("SIPP"); and by SRI International and the University of + * Cambridge Computer Laboratory (Department of Computer Science and + * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the + * DARPA SSITH research programme. + * + * @BERI_LICENSE_HEADER_START@ + * + * Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor + * license agreements. See the NOTICE file distributed with this work for + * additional information regarding copyright ownership. BERI licenses this + * file to you under the BERI Hardware-Software License, Version 1.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * + * http://www.beri-open-systems.org/legal/license-1-0.txt + * + * Unless required by applicable law or agreed to in writing, Work distributed + * under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @BERI_LICENSE_HEADER_END@ + */ + +package AXI4Stream; + +import AXI4_Common_Types :: *; +import AXI4Stream_Types :: *; +import AXI4Stream_Utils :: *; + +export AXI4_Common_Types :: *; +export AXI4Stream_Types :: *; +export AXI4Stream_Utils :: *; + +endpackage diff --git a/AXI/AXI4Stream_Types.bsv b/AXI/AXI4Stream_Types.bsv new file mode 100644 index 0000000..68db375 --- /dev/null +++ b/AXI/AXI4Stream_Types.bsv @@ -0,0 +1,123 @@ +/*- + * Copyright (c) 2021 Ivan Ribeiro + * All rights reserved. + * + * This hardware design was developed by the University of Cambridge Computer + * Laboratory (Department of Computer Science and Technology) under EPSRC award + * EP/S030867/1 ("SIPP"); and by SRI International and the University of + * Cambridge Computer Laboratory (Department of Computer Science and + * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the + * DARPA SSITH research programme. + * + * @BERI_LICENSE_HEADER_START@ + * + * Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor + * license agreements. See the NOTICE file distributed with this work for + * additional information regarding copyright ownership. BERI licenses this + * file to you under the BERI Hardware-Software License, Version 1.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * + * http://www.beri-open-systems.org/legal/license-1-0.txt + * + * Unless required by applicable law or agreed to in writing, Work distributed + * under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @BERI_LICENSE_HEADER_END@ + */ + +// Based on AXI4-Stream specification from: +// +// AMBA AXI-Stream Protocol Specification +// ARM IHI 0051B (ID122117) +// https://developer.arm.com/documentation/ihi0051/b/ + +package AXI4Stream_Types; + +import Connectable :: *; + +// BlueBasics import +import SourceSink :: *; + +import AXI4_Common_Types :: *; + +typedef struct { + Bit #(data_) tdata; + Bit #(TDiv #(data_, 8)) tstrb; + Bit #(TDiv #(data_, 8)) tkeep; + Bool tlast; + Bit #(id_) tid; + Bit #(dest_) tdest; + Bit #(user_) tuser; +} AXI4Stream_Flit #( numeric type id_ + , numeric type data_ + , numeric type dest_ + , numeric type user_) +deriving (Bits, FShow); + +(* always_ready, always_enabled *) +interface AXI4Stream_Master_Synth #( numeric type id_ + , numeric type data_ + , numeric type dest_ + , numeric type user_); + method Bit #(data_) tdata; + method Bit #(TDiv #(data_, 8)) tstrb; + method Bit #(TDiv #(data_, 8)) tkeep; + method Bool tlast; + method Bit #(id_) tid; + method Bit #(dest_) tdest; + method Bit #(user_) tuser; + method Bool tvalid; + (* prefix="" *) method Action tready (Bool tready); +endinterface + +(* always_ready, always_enabled *) +interface AXI4Stream_Slave_Synth #( numeric type id_ + , numeric type data_ + , numeric type dest_ + , numeric type user_); + (* prefix="" *) method Action tflit ( Bool tvalid + , Bit #(data_) tdata + , Bit #(TDiv #(data_, 8)) tstrb + , Bit #(TDiv #(data_, 8)) tkeep + , Bool tlast + , Bit #(id_) tid + , Bit #(dest_) tdest + , Bit #(user_) tuser); + method Bool tready; +endinterface + +typedef Source #(AXI4Stream_Flit #(id_, data_, dest_, user_)) + AXI4Stream_Master #( numeric type id_ + , numeric type data_ + , numeric type dest_ + , numeric type user_); + +typedef Sink #(AXI4Stream_Flit #(id_, data_, dest_, user_)) + AXI4Stream_Slave #( numeric type id_ + , numeric type data_ + , numeric type dest_ + , numeric type user_); + + +instance CulDeSac#(AXI4Stream_Master #(id_, data_, dest_, user_)); + function culDeSac = nullSource; +endinstance + +instance CulDeSac#(AXI4Stream_Slave #(id_, data_, dest_, user_)); + function culDeSac = nullSink; +endinstance + +interface AXI4Stream_Shim #( numeric type id_ + , numeric type data_ + , numeric type dest_ + , numeric type user_); + method Action clear; + interface AXI4Stream_Master #(id_, data_, dest_, user_) master; + interface AXI4Stream_Slave #(id_, data_, dest_, user_) slave; +endinterface + + +endpackage diff --git a/AXI/AXI4Stream_Utils.bsv b/AXI/AXI4Stream_Utils.bsv new file mode 100644 index 0000000..c45b081 --- /dev/null +++ b/AXI/AXI4Stream_Utils.bsv @@ -0,0 +1,153 @@ +/*- + * Copyright (c) 2021 Ivan Ribeiro + * All rights reserved. + * + * This hardware design was developed by the University of Cambridge Computer + * Laboratory (Department of Computer Science and Technology) under EPSRC award + * EP/S030867/1 ("SIPP"); and by SRI International and the University of + * Cambridge Computer Laboratory (Department of Computer Science and + * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the + * DARPA SSITH research programme. + * + * @BERI_LICENSE_HEADER_START@ + * + * Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor + * license agreements. See the NOTICE file distributed with this work for + * additional information regarding copyright ownership. BERI licenses this + * file to you under the BERI Hardware-Software License, Version 1.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * + * http://www.beri-open-systems.org/legal/license-1-0.txt + * + * Unless required by applicable law or agreed to in writing, Work distributed + * under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * @BERI_LICENSE_HEADER_END@ + */ + +package AXI4Stream_Utils; + +import FIFOF :: *; +import SpecialFIFOs :: *; + +// BlueBasics import +import SourceSink :: *; + +// AXI4 import +import AXI4Stream_Types :: *; + +`define defAXI4StreamShimFIFOF (name, mkFF)\ +module mkAXI4StreamShim``name (AXI4Stream_Shim#(a, b, c, d));\ + let tff <- mkFF;\ + method clear = action\ + tff.clear;\ + endaction;\ + interface master = toSource(tff);\ + interface slave = toSink(tff);\ +endmodule + +`defAXI4StreamShimFIFOF(BypassFIFOF, mkBypassFIFOF) +`defAXI4StreamShimFIFOF(BypassFF1, mkSizedBypassFIFOF(1)) +`defAXI4StreamShimFIFOF(FF1, mkFIFOF1) +`defAXI4StreamShimFIFOF(FF, mkFIFOF) +`defAXI4StreamShimFIFOF(SizedFIFOF4, mkSizedFIFOF(4)) +`defAXI4StreamShimFIFOF(SizedFIFOF32, mkSizedFIFOF(32)) +`defAXI4StreamShimFIFOF(UGSizedFIFOF32, mkUGSizedFIFOF(32)) +`defAXI4StreamShimFIFOF(UGSizedFIFOF4, mkUGSizedFIFOF(4)) + + +typeclass ToAXI4Stream_Flit #( type t + , numeric type id_ + , numeric type data_ + , numeric type dest_ + , numeric type user_); + function AXI4Stream_Flit #(id_, data_, dest_, user_) toAXI4Stream_Flit (t x); +endtypeclass + +instance ToAXI4Stream_Flit #( AXI4Stream_Flit #(id_, data_, dest_, user_) + , id_, data_, dest_, user_); + function toAXI4Stream_Flit = id; +endinstance + +typeclass FromAXI4Stream_Flit #( type t + , numeric type id_ + , numeric type data_ + , numeric type dest_ + , numeric type user_); + function t + fromAXI4Stream_Flit (AXI4Stream_Flit #(id_, data_, dest_, user_) x); +endtypeclass + +instance FromAXI4Stream_Flit #( AXI4Stream_Flit #(id_, data_, dest_, user_) + , id_, data_, dest_, user_); + function fromAXI4Stream_Flit = id; +endinstance + + +module toAXI4Stream_Master_Synth #(src_t #(t) s) + (AXI4Stream_Master_Synth #(id_, data_, dest_, user_)) + provisos ( ToSource #(src_t #(t), t) + , ToAXI4Stream_Flit #(t, id_, data_, dest_, user_) + , Bits #(t, t_sz)); + let src <- toUnguardedSource (s, ?); + AXI4Stream_Flit #(id_, data_, dest_, user_) + flit = toAXI4Stream_Flit (src.peek); + method tdata = flit.tdata; + method tstrb = flit.tstrb; + method tkeep = flit.tkeep; + method tlast = flit.tlast; + method tid = flit.tid; + method tdest = flit.tdest; + method tuser = flit.tuser; + method tvalid = src.canPeek; + method tready (rdy) = action if (src.canPeek && rdy) src.drop; endaction; +endmodule + + +module toAXI4Stream_Slave_Synth #(snk_t s) + (AXI4Stream_Slave_Synth #(id_, data_, dest_, user_)) + provisos ( ToSink #(snk_t, t) + , FromAXI4Stream_Flit #(t, id_, data_, dest_, user_) + , Bits #(t, t_sz)); + let snk <- toUnguardedSink (s); + + method tflit (tvalid, tdata, tstrb, tkeep, tlast, tid, tdest, tuser) = + action + if (tvalid && snk.canPut) + snk.put (fromAXI4Stream_Flit (AXI4Stream_Flit { tdata: tdata + , tstrb: tstrb + , tkeep: tkeep + , tlast: tlast + , tid : tid + , tdest: tdest + , tuser: tuser })); + endaction; + method tready = snk.canPut; +endmodule + +function AXI4Stream_Master #(id_, data_, dest_, user_) + debugAXI4Stream_Master ( AXI4Stream_Master #(id_, data_, dest_, user_) m + , Fmt msg) = debugSource (m, $format (msg, " t")); + +function AXI4Stream_Slave #(id_, data_, dest_, user_) + debugAXI4Stream_Slave ( AXI4Stream_Slave #(id_, data_, dest_, user_) s + , Fmt msg) = debugSink (s,$format (msg, " t")); + +module toUnguarded_AXI4Stream_Master + #(AXI4Stream_Master #(id_, data_, dest_, user_) m) + (AXI4Stream_Master #(id_, data_, dest_, user_)); + let ugm <- toUnguardedSource (m, ?); + return ugm; +endmodule + +module toUnguarded_AXI4Stream_Slave + #(AXI4Stream_Slave #(id_, data_, dest_, user_) s) + (AXI4Stream_Slave #(id_, data_, dest_, user_)); + let ugs <- toUnguardedSink (s); + return ugs; +endmodule + +endpackage diff --git a/AXI/AXI4_AXI4Lite_Bridges.bsv b/AXI/AXI4_AXI4Lite_Bridges.bsv index 0ed5869..6235f4f 100644 --- a/AXI/AXI4_AXI4Lite_Bridges.bsv +++ b/AXI/AXI4_AXI4Lite_Bridges.bsv @@ -1,8 +1,11 @@ /*- * Copyright (c) 2018-2021 Alexandre Joannou + * Copyright (c) 2021 Ivan Ribeiro * All rights reserved. * - * This software was developed by SRI International and the University of + * This hardware design was developed by the University of Cambridge Computer + * Laboratory (Department of Computer Science and Technology) under EPSRC award + * EP/S030867/1 ("SIPP"); and by SRI International and the University of * Cambridge Computer Laboratory (Department of Computer Science and * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the * DARPA SSITH research programme. @@ -29,7 +32,7 @@ // AXI imports import AXI4_Types :: *; import AXI4Lite_Types :: *; -import AXI4_AXI4Lite_Types :: *; +import AXI4_Common_Types :: *; // BlueBasics import import SourceSink :: *; diff --git a/AXI/AXI4_AXI4Lite_Types.bsv b/AXI/AXI4_Common_Types.bsv similarity index 94% rename from AXI/AXI4_AXI4Lite_Types.bsv rename to AXI/AXI4_Common_Types.bsv index 50c3b4c..806ffdd 100644 --- a/AXI/AXI4_AXI4Lite_Types.bsv +++ b/AXI/AXI4_Common_Types.bsv @@ -1,8 +1,11 @@ /*- * Copyright (c) 2018-2021 Alexandre Joannou + * Copyright (c) 2021 Ivan Ribeiro * All rights reserved. * - * This software was developed by SRI International and the University of + * This hardware design was developed by the University of Cambridge Computer + * Laboratory (Department of Computer Science and Technology) under EPSRC award + * EP/S030867/1 ("SIPP"); and by SRI International and the University of * Cambridge Computer Laboratory (Department of Computer Science and * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the * DARPA SSITH research programme. @@ -31,6 +34,9 @@ // AMBA AXI and ACE Protocol Specification // AXI3, AXI4, AXI5, ACE and ACE5 // ARM IHI 0022F.b (ID122117) +// https://developer.arm.com/documentation/ihi0022/fb + +package AXI4_Common_Types; import Printf :: *; @@ -179,3 +185,5 @@ typedef enum { typeclass CulDeSac#(type t); function t culDeSac; endtypeclass + +endpackage diff --git a/AXI/AXI4_Types.bsv b/AXI/AXI4_Types.bsv index 3e764dd..f94527f 100644 --- a/AXI/AXI4_Types.bsv +++ b/AXI/AXI4_Types.bsv @@ -2,9 +2,12 @@ * Copyright (c) 2018-2021 Alexandre Joannou * Copyright (c) 2019 Peter Rugg * Copyright (c) 2020 Jonas Fiala + * Copyright (c) 2021 Ivan Ribeiro * All rights reserved. * - * This software was developed by SRI International and the University of + * This hardware design was developed by the University of Cambridge Computer + * Laboratory (Department of Computer Science and Technology) under EPSRC award + * EP/S030867/1 ("SIPP"); and by SRI International and the University of * Cambridge Computer Laboratory (Department of Computer Science and * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the * DARPA SSITH research programme. @@ -37,7 +40,7 @@ import Routable :: *; import SourceSink :: *; import MasterSlave :: *; -import AXI4_AXI4Lite_Types :: *; +import AXI4_Common_Types :: *; //////////////////////////////// // AXI4 Address Write Channel // diff --git a/AXI/AXI4_Utils.bsv b/AXI/AXI4_Utils.bsv index 5967380..0c59e63 100644 --- a/AXI/AXI4_Utils.bsv +++ b/AXI/AXI4_Utils.bsv @@ -3,9 +3,12 @@ * Copyright (c) 2019 Peter Rugg * Copyright (c) 2020 Jonas Fiala * Copyright (c) 2021 Marno van der Maas + * Copyright (c) 2021 Ivan Ribeiro * All rights reserved. * - * This software was developed by SRI International and the University of + * This hardware design was developed by the University of Cambridge Computer + * Laboratory (Department of Computer Science and Technology) under EPSRC award + * EP/S030867/1 ("SIPP"); and by SRI International and the University of * Cambridge Computer Laboratory (Department of Computer Science and * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the * DARPA SSITH research programme. @@ -30,7 +33,7 @@ */ // AXI4 imports -import AXI4_AXI4Lite_Types :: *; +import AXI4_Common_Types :: *; import AXI4_Types :: *; import AXI4_AW_Utils :: *; import AXI4_W_Utils :: *; diff --git a/AXI/doc.md b/AXI/doc.md index 851dc7e..c1676da 100644 --- a/AXI/doc.md +++ b/AXI/doc.md @@ -1,9 +1,13 @@ -Bluestuff's [`AXI4_AXI4Lite_Types`](AXI4_AXI4Lite_Types.bsv) and [AXI4_Types`](AXI4_Types.bsv) packages provide a set of types and interface capturing the AXI4 protocol described in the specification in +Bluestuff's [`AXI4_Common_Types`](AXI4_Common_Types.bsv) and [`AXI4_Types`](AXI4_Types.bsv) packages provide a set of types and interfaces capturing the AXI4 protocol described in the specification in > AMBA AXI and ACE Protocol Specification > AXI3, AXI4, AXI5, ACE and ACE5 -> ARM IHI 0022F.b (ID122117) +> ARM IHI 0022F.b (ID122117) (found [here](https://developer.arm.com/documentation/ihi0022/fb)) -# AXI4_AXI4Lite_Types +The [`AXI4Stream_Types`](AXI4Stream_Types.bsv) package provides types and interfaces capturing the AXI4-Stream protocol described in the specification in +> AMBA AXI-Stream Protocol Specification +> ARM IHI 0051B (ID040921) (found [here](https://developer.arm.com/documentation/ihi0051/b)) + +# AXI4_Common_Types - To capture AXI4 burst length (A3-48), the `AXI4_Len` type - To capture AXI4 burst size (A3-49), the `AXI4_Size` type - To capture AXI4 burst type (A3-49), the `AXI4_Burst` type