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SIMTight_hw.tcl
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# TCL File Generated by Component Editor 19.2
# Fri Aug 13 21:09:02 BST 2021
# DO NOT MODIFY
#
# SIMTight "SIMTight" v1.0
# 2021.08.13.21:09:02
#
#
#
# request TCL package from ACDS 19.4
#
package require -exact qsys 19.4
#
# module SIMTight
#
set_module_property DESCRIPTION ""
set_module_property NAME SIMTight
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME SIMTight
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
set_module_property LOAD_ELABORATION_LIMIT 0
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL SIMTight
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file SIMTight.v VERILOG PATH ../src/SIMTight.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point dram_master
#
add_interface dram_master avalon start
set_interface_property dram_master addressGroup 0
set_interface_property dram_master addressUnits WORDS
set_interface_property dram_master associatedClock simt_clock
set_interface_property dram_master associatedReset simt_reset
set_interface_property dram_master bitsPerSymbol 8
set_interface_property dram_master burstOnBurstBoundariesOnly false
set_interface_property dram_master burstcountUnits WORDS
set_interface_property dram_master doStreamReads false
set_interface_property dram_master doStreamWrites false
set_interface_property dram_master holdTime 0
set_interface_property dram_master linewrapBursts false
set_interface_property dram_master maximumPendingReadTransactions 0
set_interface_property dram_master maximumPendingWriteTransactions 0
set_interface_property dram_master minimumResponseLatency 1
set_interface_property dram_master readLatency 0
set_interface_property dram_master readWaitTime 1
set_interface_property dram_master setupTime 0
set_interface_property dram_master timingUnits Cycles
set_interface_property dram_master waitrequestAllowance 0
set_interface_property dram_master writeWaitTime 0
set_interface_property dram_master ENABLED true
set_interface_property dram_master EXPORT_OF ""
set_interface_property dram_master PORT_NAME_MAP ""
set_interface_property dram_master CMSIS_SVD_VARIABLES ""
set_interface_property dram_master SVD_ADDRESS_GROUP ""
set_interface_property dram_master IPXACT_REGISTER_MAP_VARIABLES ""
add_interface_port dram_master in0_socDRAMIns_avl_dram_readdata readdata Input 512
add_interface_port dram_master in0_socDRAMIns_avl_dram_readdatavalid readdatavalid Input 1
set_port_property in0_socDRAMIns_avl_dram_readdatavalid VHDL_TYPE STD_LOGIC_VECTOR
add_interface_port dram_master in0_socDRAMIns_avl_dram_waitrequest waitrequest Input 1
set_port_property in0_socDRAMIns_avl_dram_waitrequest VHDL_TYPE STD_LOGIC_VECTOR
add_interface_port dram_master out_socDRAMOuts_avl_dram_address address Output 26
add_interface_port dram_master out_socDRAMOuts_avl_dram_burstcount burstcount Output 4
add_interface_port dram_master out_socDRAMOuts_avl_dram_byteen byteenable Output 64
add_interface_port dram_master out_socDRAMOuts_avl_dram_read read Output 1
set_port_property out_socDRAMOuts_avl_dram_read VHDL_TYPE STD_LOGIC_VECTOR
add_interface_port dram_master out_socDRAMOuts_avl_dram_write write Output 1
set_port_property out_socDRAMOuts_avl_dram_write VHDL_TYPE STD_LOGIC_VECTOR
add_interface_port dram_master out_socDRAMOuts_avl_dram_writedata writedata Output 512
#
# connection point uart_master
#
add_interface uart_master avalon start
set_interface_property uart_master addressGroup 0
set_interface_property uart_master addressUnits SYMBOLS
set_interface_property uart_master associatedClock cpu_clock
set_interface_property uart_master associatedReset cpu_reset
set_interface_property uart_master bitsPerSymbol 8
set_interface_property uart_master burstOnBurstBoundariesOnly false
set_interface_property uart_master burstcountUnits WORDS
set_interface_property uart_master doStreamReads false
set_interface_property uart_master doStreamWrites false
set_interface_property uart_master holdTime 0
set_interface_property uart_master linewrapBursts false
set_interface_property uart_master maximumPendingReadTransactions 0
set_interface_property uart_master maximumPendingWriteTransactions 0
set_interface_property uart_master minimumResponseLatency 1
set_interface_property uart_master readLatency 0
set_interface_property uart_master readWaitTime 1
set_interface_property uart_master setupTime 0
set_interface_property uart_master timingUnits Cycles
set_interface_property uart_master waitrequestAllowance 0
set_interface_property uart_master writeWaitTime 0
set_interface_property uart_master ENABLED true
set_interface_property uart_master EXPORT_OF ""
set_interface_property uart_master PORT_NAME_MAP ""
set_interface_property uart_master CMSIS_SVD_VARIABLES ""
set_interface_property uart_master SVD_ADDRESS_GROUP ""
set_interface_property uart_master IPXACT_REGISTER_MAP_VARIABLES ""
add_interface_port uart_master in0_socUARTIns_avl_jtaguart_readdata readdata Input 32
add_interface_port uart_master in0_socUARTIns_avl_jtaguart_waitrequest waitrequest Input 1
set_port_property in0_socUARTIns_avl_jtaguart_waitrequest VHDL_TYPE STD_LOGIC_VECTOR
add_interface_port uart_master out_socUARTOuts_avl_jtaguart_address address Output 3
add_interface_port uart_master out_socUARTOuts_avl_jtaguart_read read Output 1
set_port_property out_socUARTOuts_avl_jtaguart_read VHDL_TYPE STD_LOGIC_VECTOR
add_interface_port uart_master out_socUARTOuts_avl_jtaguart_write write Output 1
set_port_property out_socUARTOuts_avl_jtaguart_write VHDL_TYPE STD_LOGIC_VECTOR
add_interface_port uart_master out_socUARTOuts_avl_jtaguart_writedata writedata Output 32
#
# connection point simt_clock
#
add_interface simt_clock clock end
set_interface_property simt_clock ENABLED true
set_interface_property simt_clock EXPORT_OF ""
set_interface_property simt_clock PORT_NAME_MAP ""
set_interface_property simt_clock CMSIS_SVD_VARIABLES ""
set_interface_property simt_clock SVD_ADDRESS_GROUP ""
set_interface_property simt_clock IPXACT_REGISTER_MAP_VARIABLES ""
add_interface_port simt_clock in0_socSIMTClk clk Input 1
set_port_property in0_socSIMTClk VHDL_TYPE STD_LOGIC_VECTOR
#
# connection point cpu_clock
#
add_interface cpu_clock clock end
set_interface_property cpu_clock ENABLED true
set_interface_property cpu_clock EXPORT_OF ""
set_interface_property cpu_clock PORT_NAME_MAP ""
set_interface_property cpu_clock CMSIS_SVD_VARIABLES ""
set_interface_property cpu_clock SVD_ADDRESS_GROUP ""
set_interface_property cpu_clock IPXACT_REGISTER_MAP_VARIABLES ""
add_interface_port cpu_clock in0_socCPUClk clk Input 1
set_port_property in0_socCPUClk VHDL_TYPE STD_LOGIC_VECTOR
#
# connection point simt_reset
#
add_interface simt_reset reset end
set_interface_property simt_reset associatedClock simt_clock
set_interface_property simt_reset synchronousEdges DEASSERT
set_interface_property simt_reset ENABLED true
set_interface_property simt_reset EXPORT_OF ""
set_interface_property simt_reset PORT_NAME_MAP ""
set_interface_property simt_reset CMSIS_SVD_VARIABLES ""
set_interface_property simt_reset SVD_ADDRESS_GROUP ""
set_interface_property simt_reset IPXACT_REGISTER_MAP_VARIABLES ""
add_interface_port simt_reset in0_socSIMTRst reset Input 1
set_port_property in0_socSIMTRst VHDL_TYPE STD_LOGIC_VECTOR
#
# connection point cpu_reset
#
add_interface cpu_reset reset end
set_interface_property cpu_reset associatedClock cpu_clock
set_interface_property cpu_reset synchronousEdges DEASSERT
set_interface_property cpu_reset ENABLED true
set_interface_property cpu_reset EXPORT_OF ""
set_interface_property cpu_reset PORT_NAME_MAP ""
set_interface_property cpu_reset CMSIS_SVD_VARIABLES ""
set_interface_property cpu_reset SVD_ADDRESS_GROUP ""
set_interface_property cpu_reset IPXACT_REGISTER_MAP_VARIABLES ""
add_interface_port cpu_reset in0_socCPURst reset Input 1
set_port_property in0_socCPURst VHDL_TYPE STD_LOGIC_VECTOR