diff --git a/apps/TestSuite/CHERI/A/camoadd_w.S b/apps/TestSuite/CHERI/A/camoadd_w.S
index cfac316..989d329 100644
--- a/apps/TestSuite/CHERI/A/camoadd_w.S
+++ b/apps/TestSuite/CHERI/A/camoadd_w.S
@@ -20,7 +20,7 @@ RVTEST_CODE_BEGIN
   #define ADDR (\
     1 << (DRAMAddrWidth + DRAMBeatLogBytes) - \
     1 << (SIMTLogLanes + SIMTLogWarps + SIMTLogBytesPerStack) - \
-    1 << (SIMTLogLanes + SIMTLogWordsPerSRAMBank + 2))
+    1 << (SIMTLogSRAMBanks + SIMTLogWordsPerSRAMBank + 2))
 
   # Use only a single thread for this test
   csrrw t3, 0xf14, zero
diff --git a/apps/TestSuite/CHERI/A/camoand_w.S b/apps/TestSuite/CHERI/A/camoand_w.S
index 437e3fa..27801d0 100644
--- a/apps/TestSuite/CHERI/A/camoand_w.S
+++ b/apps/TestSuite/CHERI/A/camoand_w.S
@@ -20,7 +20,7 @@ RVTEST_CODE_BEGIN
   #define ADDR (\
     1 << (DRAMAddrWidth + DRAMBeatLogBytes) - \
     1 << (SIMTLogLanes + SIMTLogWarps + SIMTLogBytesPerStack) - \
-    1 << (SIMTLogLanes + SIMTLogWordsPerSRAMBank + 2))
+    1 << (SIMTLogSRAMBanks + SIMTLogWordsPerSRAMBank + 2))
 
   # Use only a single thread for this test
   csrrw t3, 0xf14, zero
diff --git a/apps/TestSuite/CHERI/A/camomax_w.S b/apps/TestSuite/CHERI/A/camomax_w.S
index 03108bd..92d463f 100644
--- a/apps/TestSuite/CHERI/A/camomax_w.S
+++ b/apps/TestSuite/CHERI/A/camomax_w.S
@@ -20,7 +20,7 @@ RVTEST_CODE_BEGIN
   #define ADDR (\
     1 << (DRAMAddrWidth + DRAMBeatLogBytes) - \
     1 << (SIMTLogLanes + SIMTLogWarps + SIMTLogBytesPerStack) - \
-    1 << (SIMTLogLanes + SIMTLogWordsPerSRAMBank + 2))
+    1 << (SIMTLogSRAMBanks + SIMTLogWordsPerSRAMBank + 2))
 
   # Use only a single thread for this test
   csrrw t3, 0xf14, zero
diff --git a/apps/TestSuite/CHERI/A/camomaxu_w.S b/apps/TestSuite/CHERI/A/camomaxu_w.S
index fcca36e..6a03f3e 100644
--- a/apps/TestSuite/CHERI/A/camomaxu_w.S
+++ b/apps/TestSuite/CHERI/A/camomaxu_w.S
@@ -20,7 +20,7 @@ RVTEST_CODE_BEGIN
   #define ADDR (\
     1 << (DRAMAddrWidth + DRAMBeatLogBytes) - \
     1 << (SIMTLogLanes + SIMTLogWarps + SIMTLogBytesPerStack) - \
-    1 << (SIMTLogLanes + SIMTLogWordsPerSRAMBank + 2))
+    1 << (SIMTLogSRAMBanks + SIMTLogWordsPerSRAMBank + 2))
 
   # Use only a single thread for this test
   csrrw t3, 0xf14, zero
diff --git a/apps/TestSuite/CHERI/A/camomin_w.S b/apps/TestSuite/CHERI/A/camomin_w.S
index 4d0ad02..b823175 100644
--- a/apps/TestSuite/CHERI/A/camomin_w.S
+++ b/apps/TestSuite/CHERI/A/camomin_w.S
@@ -20,7 +20,7 @@ RVTEST_CODE_BEGIN
   #define ADDR (\
     1 << (DRAMAddrWidth + DRAMBeatLogBytes) - \
     1 << (SIMTLogLanes + SIMTLogWarps + SIMTLogBytesPerStack) - \
-    1 << (SIMTLogLanes + SIMTLogWordsPerSRAMBank + 2))
+    1 << (SIMTLogSRAMBanks + SIMTLogWordsPerSRAMBank + 2))
 
   # Use only a single thread for this test
   csrrw t3, 0xf14, zero
diff --git a/apps/TestSuite/CHERI/A/camominu_w.S b/apps/TestSuite/CHERI/A/camominu_w.S
index 075cb80..fccca7f 100644
--- a/apps/TestSuite/CHERI/A/camominu_w.S
+++ b/apps/TestSuite/CHERI/A/camominu_w.S
@@ -20,7 +20,7 @@ RVTEST_CODE_BEGIN
   #define ADDR (\
     1 << (DRAMAddrWidth + DRAMBeatLogBytes) - \
     1 << (SIMTLogLanes + SIMTLogWarps + SIMTLogBytesPerStack) - \
-    1 << (SIMTLogLanes + SIMTLogWordsPerSRAMBank + 2))
+    1 << (SIMTLogSRAMBanks + SIMTLogWordsPerSRAMBank + 2))
 
   # Use only a single thread for this test
   csrrw t3, 0xf14, zero
diff --git a/apps/TestSuite/CHERI/A/camoor_w.S b/apps/TestSuite/CHERI/A/camoor_w.S
index 768e020..faedc4c 100644
--- a/apps/TestSuite/CHERI/A/camoor_w.S
+++ b/apps/TestSuite/CHERI/A/camoor_w.S
@@ -20,7 +20,7 @@ RVTEST_CODE_BEGIN
   #define ADDR (\
     1 << (DRAMAddrWidth + DRAMBeatLogBytes) - \
     1 << (SIMTLogLanes + SIMTLogWarps + SIMTLogBytesPerStack) - \
-    1 << (SIMTLogLanes + SIMTLogWordsPerSRAMBank + 2))
+    1 << (SIMTLogSRAMBanks + SIMTLogWordsPerSRAMBank + 2))
 
   # Use only a single thread for this test
   csrrw t3, 0xf14, zero
diff --git a/apps/TestSuite/CHERI/A/camoswap_w.S b/apps/TestSuite/CHERI/A/camoswap_w.S
index bf9df4c..561dfeb 100644
--- a/apps/TestSuite/CHERI/A/camoswap_w.S
+++ b/apps/TestSuite/CHERI/A/camoswap_w.S
@@ -20,7 +20,7 @@ RVTEST_CODE_BEGIN
   #define ADDR (\
     1 << (DRAMAddrWidth + DRAMBeatLogBytes) - \
     1 << (SIMTLogLanes + SIMTLogWarps + SIMTLogBytesPerStack) - \
-    1 << (SIMTLogLanes + SIMTLogWordsPerSRAMBank + 2))
+    1 << (SIMTLogSRAMBanks + SIMTLogWordsPerSRAMBank + 2))
 
   # Use only a single thread for this test
   csrrw t3, 0xf14, zero
diff --git a/apps/TestSuite/CHERI/A/camoxor_w.S b/apps/TestSuite/CHERI/A/camoxor_w.S
index 4fca395..4b98cdc 100644
--- a/apps/TestSuite/CHERI/A/camoxor_w.S
+++ b/apps/TestSuite/CHERI/A/camoxor_w.S
@@ -20,7 +20,7 @@ RVTEST_CODE_BEGIN
   #define ADDR (\
     1 << (DRAMAddrWidth + DRAMBeatLogBytes) - \
     1 << (SIMTLogLanes + SIMTLogWarps + SIMTLogBytesPerStack) - \
-    1 << (SIMTLogLanes + SIMTLogWordsPerSRAMBank + 2))
+    1 << (SIMTLogSRAMBanks + SIMTLogWordsPerSRAMBank + 2))
 
   # Use only a single thread for this test
   csrrw t3, 0xf14, zero