From 7fcae7126cbecb7a53ef13e48c8b79c78443c6c7 Mon Sep 17 00:00:00 2001 From: Matthew Naylor Date: Wed, 5 Oct 2022 21:22:17 +0100 Subject: [PATCH] DE10Pro revE project --- Makefile | 1 + apps/Common/app.mk | 3 +- apps/TestSuite/Makefile | 6 +- boot/Makefile | 5 +- de10-pro-e/DE10_Pro.qpf | 6 + de10-pro-e/DE10_Pro.qsf | 1737 +++ de10-pro-e/DE10_Pro.sdc | 101 + de10-pro-e/DE10_Pro.v | 117 + de10-pro-e/DE10_Pro_QSYS.qsys | 11015 ++++++++++++++++ de10-pro-e/DE10_Pro_assignment_defaults.qdf | 711 + de10-pro-e/Makefile | 51 + de10-pro-e/SIMTight_hw.tcl | 206 + .../DE10_Pro_QSYS/DE10_Pro_QSYS_SIMTight_0.ip | 1630 +++ .../DE10_Pro_QSYS/DE10_Pro_QSYS_clock_in.ip | 361 + .../DE10_Pro_QSYS_ddr4_local_reset_req.ip | 792 ++ .../DE10_Pro_QSYS_emif_s10_ddr4_b.ip | 10158 ++++++++++++++ .../ip/DE10_Pro_QSYS/DE10_Pro_QSYS_iopll_0.ip | 2091 +++ .../DE10_Pro_QSYS_jtag_uart_0.ip | 1299 ++ ...0_Pro_QSYS_mm_clock_crossing_bridge_50m.ip | 1984 +++ .../DE10_Pro_QSYS_mm_clockcross_DDR4.ip | 1994 +++ .../ip/DE10_Pro_QSYS/DE10_Pro_QSYS_pio_0.ip | 726 + .../DE10_Pro_QSYS/DE10_Pro_QSYS_reset_in.ip | 434 + de10-pro-e/prepare_dse.sh | 10 + de10-pro-e/reset_release.ip | 140 + scripts/sweep.py | 5 + src/Makefile | 1 + test/test.sh | 22 +- 27 files changed, 35595 insertions(+), 11 deletions(-) create mode 100644 de10-pro-e/DE10_Pro.qpf create mode 100644 de10-pro-e/DE10_Pro.qsf create mode 100644 de10-pro-e/DE10_Pro.sdc create mode 100644 de10-pro-e/DE10_Pro.v create mode 100644 de10-pro-e/DE10_Pro_QSYS.qsys create mode 100644 de10-pro-e/DE10_Pro_assignment_defaults.qdf create mode 100644 de10-pro-e/Makefile create mode 100644 de10-pro-e/SIMTight_hw.tcl create mode 100644 de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_SIMTight_0.ip create mode 100644 de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_clock_in.ip create mode 100644 de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_ddr4_local_reset_req.ip create mode 100644 de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_emif_s10_ddr4_b.ip create mode 100644 de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_iopll_0.ip create mode 100644 de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_jtag_uart_0.ip create mode 100644 de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_mm_clock_crossing_bridge_50m.ip create mode 100644 de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_mm_clockcross_DDR4.ip create mode 100644 de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_pio_0.ip create mode 100644 de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_reset_in.ip create mode 100755 de10-pro-e/prepare_dse.sh create mode 100644 de10-pro-e/reset_release.ip diff --git a/Makefile b/Makefile index aac2d87..4ee3317 100644 --- a/Makefile +++ b/Makefile @@ -14,5 +14,6 @@ clean: make -C apps clean make -C src clean make -C de10-pro clean + make -C de10-pro-e clean make -C sim clean make -C pebbles clean diff --git a/apps/Common/app.mk b/apps/Common/app.mk index b3d778d..e79fbb0 100644 --- a/apps/Common/app.mk +++ b/apps/Common/app.mk @@ -66,7 +66,8 @@ link.ld: $(SIMTIGHT_APPS_ROOT)/Common/link.ld.h Run: checkenv code.v data.v $(RUN_CPP) $(RUN_H) g++ -std=c++11 -O2 -I $(PEBBLES_ROOT)/inc \ -I $(SIMTIGHT_ROOT)/inc -o Run $(RUN_CPP) \ - -fno-exceptions -ljtag_atlantic -ljtag_client \ + -fno-exceptions -ljtag_atlantic -lpthread \ + -Wl,--no-as-needed -ljtag_client \ -L $(QUARTUS_ROOTDIR)/linux64/ -Wl,-rpath,$(QUARTUS_ROOTDIR)/linux64 RunSim: code.v data.v $(RUN_CPP) $(RUN_H) diff --git a/apps/TestSuite/Makefile b/apps/TestSuite/Makefile index e8eed08..b926df5 100644 --- a/apps/TestSuite/Makefile +++ b/apps/TestSuite/Makefile @@ -99,7 +99,8 @@ StartSIMT.o: StartSIMT.cpp TestCPU: checkenv TestCPU.cpp @g++ -std=c++11 -O2 -I $(PEBBLES_ROOT)/inc -o TestCPU TestCPU.cpp \ -I $(SIMTIGHT_ROOT)/inc \ - -fno-exceptions -ljtag_atlantic -ljtag_client \ + -fno-exceptions -lpthread -ljtag_atlantic \ + -Wl,--no-as-needed -ljtag_client \ -L $(QUARTUS_ROOTDIR)/linux64/ -Wl,-rpath,$(QUARTUS_ROOTDIR)/linux64 TestCPUSim: TestCPU.cpp @@ -110,7 +111,8 @@ TestCPUSim: TestCPU.cpp TestSIMT: checkenv TestSIMT.cpp @g++ -std=c++11 -O2 -I $(PEBBLES_ROOT)/inc -o TestSIMT TestSIMT.cpp \ -I $(SIMTIGHT_ROOT)/inc \ - -fno-exceptions -ljtag_atlantic -ljtag_client \ + -fno-exceptions -lpthread -ljtag_atlantic \ + -Wl,--no-as-needed -ljtag_client \ -L $(QUARTUS_ROOTDIR)/linux64/ -Wl,-rpath,$(QUARTUS_ROOTDIR)/linux64 TestSIMTSim: TestSIMT.cpp diff --git a/boot/Makefile b/boot/Makefile index c1f5329..a94f0e1 100644 --- a/boot/Makefile +++ b/boot/Makefile @@ -56,7 +56,7 @@ LOG_INSTR_BYTES = $(shell echo -n CPUInstrMemLogWords \ INSTR_BYTES = $(shell echo "3 * (2 ^ $(LOG_INSTR_BYTES))" | bc) .PHONY: all -all: $(SIM)/boot.hex ../de10-pro/boot.mif +all: $(SIM)/boot.hex ../de10-pro/boot.mif ../de10-pro-e/boot.mif link.ld: link.ld.h cpp -P -I $(SIMTIGHT_ROOT)/inc link.ld.h > link.ld @@ -69,6 +69,9 @@ $(SIM)/boot.hex: InstrMem.ihex ./ihex-to-img.py InstrMem.ihex mif $(INSTR_BASE) 4 $(INSTR_BYTES) 1 \ > ../de10-pro/boot.mif +../de10-pro-e/boot.mif: ../de10-pro/boot.mif + cp ../de10-pro/boot.mif ../de10-pro-e/boot.mif + InstrMem.ihex: out.elf $(RV_OBJCOPY) --only-section=.text -O ihex out.elf InstrMem.ihex diff --git a/de10-pro-e/DE10_Pro.qpf b/de10-pro-e/DE10_Pro.qpf new file mode 100644 index 0000000..dc61d2f --- /dev/null +++ b/de10-pro-e/DE10_Pro.qpf @@ -0,0 +1,6 @@ +DATE = "Wed Jan 31 14:15:58 2018" +QUARTUS_VERSION = "17.1.0" + +# Revisions + +PROJECT_REVISION = "DE10_Pro" \ No newline at end of file diff --git a/de10-pro-e/DE10_Pro.qsf b/de10-pro-e/DE10_Pro.qsf new file mode 100644 index 0000000..c8a4132 --- /dev/null +++ b/de10-pro-e/DE10_Pro.qsf @@ -0,0 +1,1737 @@ +#============================================================ +# Build by Terasic V2.0.0 +#============================================================ + +set_global_assignment -name FAMILY "Stratix 10" +set_global_assignment -name DEVICE 1SX280HU2F50E1VG +set_global_assignment -name TOP_LEVEL_ENTITY "DE10_Pro" +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "17.1.0 PRO EDITION" +set_global_assignment -name LAST_QUARTUS_VERSION "21.3.0 Pro Edition" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "Wed Jan 31 14:15:58 2018" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +#============================================================ +# CLOCK +#============================================================ +set_instance_assignment -name IO_STANDARD "1.8 V" -to CLK_100_B3I +set_instance_assignment -name IO_STANDARD "1.2 V" -to CLK_50_B2C +set_instance_assignment -name IO_STANDARD "1.2 V" -to CLK_50_B2L +set_instance_assignment -name IO_STANDARD "1.2 V" -to CLK_50_B3C +set_instance_assignment -name IO_STANDARD "1.8 V" -to CLK_50_B3I +set_instance_assignment -name IO_STANDARD "1.2 V" -to CLK_50_B3L +set_location_assignment PIN_U24 -to CLK_100_B3I +set_location_assignment PIN_AW38 -to CLK_50_B2C +set_location_assignment PIN_J25 -to CLK_50_B2L +set_location_assignment PIN_BF21 -to CLK_50_B3C +set_location_assignment PIN_M24 -to CLK_50_B3I +set_location_assignment PIN_J20 -to CLK_50_B3L + +#============================================================ +# Buttons +#============================================================ +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPU_RESET_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to BUTTON[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to BUTTON[1] +set_location_assignment PIN_BF27 -to CPU_RESET_n +set_location_assignment PIN_D24 -to BUTTON[0] +set_location_assignment PIN_D23 -to BUTTON[1] + +#============================================================ +# Swtiches +#============================================================ +set_instance_assignment -name IO_STANDARD "1.8 V" -to SW[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to SW[1] +set_location_assignment PIN_C23 -to SW[0] +set_location_assignment PIN_B23 -to SW[1] + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "1.8 V" -to LED[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to LED[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to LED[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to LED[3] +set_location_assignment PIN_B24 -to LED[0] +set_location_assignment PIN_A24 -to LED[1] +set_location_assignment PIN_A25 -to LED[2] +set_location_assignment PIN_A26 -to LED[3] + +#============================================================ +# FLASH +#============================================================ +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_CLK +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[14] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[16] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[17] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[18] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[19] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[20] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[21] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[22] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[23] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[24] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[25] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[26] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_A[27] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_D[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_D[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_D[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_D[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_D[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_D[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_D[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_D[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_D[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_D[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_D[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_D[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_D[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_D[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_D[14] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_D[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_CE_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_WE_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_OE_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_ADV_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_RESET_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to FLASH_RDY_BSY_n +set_location_assignment PIN_U23 -to FLASH_CLK +set_location_assignment PIN_V22 -to FLASH_A[1] +set_location_assignment PIN_P23 -to FLASH_A[2] +set_location_assignment PIN_K22 -to FLASH_A[3] +set_location_assignment PIN_R21 -to FLASH_A[4] +set_location_assignment PIN_K24 -to FLASH_A[5] +set_location_assignment PIN_K23 -to FLASH_A[6] +set_location_assignment PIN_R24 -to FLASH_A[7] +set_location_assignment PIN_AR28 -to FLASH_A[8] +set_location_assignment PIN_AR27 -to FLASH_A[9] +set_location_assignment PIN_AN26 -to FLASH_A[10] +set_location_assignment PIN_AP26 -to FLASH_A[11] +set_location_assignment PIN_AN25 -to FLASH_A[12] +set_location_assignment PIN_AU27 -to FLASH_A[13] +set_location_assignment PIN_AP28 -to FLASH_A[14] +set_location_assignment PIN_AT27 -to FLASH_A[15] +set_location_assignment PIN_AY28 -to FLASH_A[16] +set_location_assignment PIN_AY26 -to FLASH_A[17] +set_location_assignment PIN_AP30 -to FLASH_A[18] +set_location_assignment PIN_AW25 -to FLASH_A[19] +set_location_assignment PIN_BB27 -to FLASH_A[20] +set_location_assignment PIN_AT26 -to FLASH_A[21] +set_location_assignment PIN_AP31 -to FLASH_A[22] +set_location_assignment PIN_P24 -to FLASH_A[23] +set_location_assignment PIN_AV26 -to FLASH_A[24] +set_location_assignment PIN_AV27 -to FLASH_A[25] +set_location_assignment PIN_AP29 -to FLASH_A[26] +set_location_assignment PIN_N22 -to FLASH_A[27] +set_location_assignment PIN_N23 -to FLASH_D[0] +set_location_assignment PIN_R22 -to FLASH_D[1] +set_location_assignment PIN_U20 -to FLASH_D[2] +set_location_assignment PIN_L22 -to FLASH_D[3] +set_location_assignment PIN_J23 -to FLASH_D[4] +set_location_assignment PIN_U22 -to FLASH_D[5] +set_location_assignment PIN_V23 -to FLASH_D[6] +set_location_assignment PIN_V21 -to FLASH_D[7] +set_location_assignment PIN_M23 -to FLASH_D[8] +set_location_assignment PIN_R23 -to FLASH_D[9] +set_location_assignment PIN_T20 -to FLASH_D[10] +set_location_assignment PIN_V24 -to FLASH_D[11] +set_location_assignment PIN_M22 -to FLASH_D[12] +set_location_assignment PIN_T22 -to FLASH_D[13] +set_location_assignment PIN_T21 -to FLASH_D[14] +set_location_assignment PIN_J24 -to FLASH_D[15] +set_location_assignment PIN_AR26 -to FLASH_CE_n +set_location_assignment PIN_AT25 -to FLASH_WE_n +set_location_assignment PIN_AV25 -to FLASH_OE_n +set_location_assignment PIN_AU25 -to FLASH_ADV_n +set_location_assignment PIN_AP25 -to FLASH_RESET_n +set_location_assignment PIN_AW26 -to FLASH_RDY_BSY_n + +#============================================================ +# DDR4A +#============================================================ +set_instance_assignment -name IO_STANDARD "LVDS" -to DDR4A_REFCLK_p +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[0] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[1] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[2] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[3] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[4] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[5] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[6] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[7] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[8] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[9] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[10] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[11] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[12] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[13] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[14] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[15] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_A[16] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_BA[0] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_BA[1] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_BG[0] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_BG[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to DDR4A_CK +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to DDR4A_CK_n +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_CKE +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS[4] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS[5] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS[6] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS[7] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS[8] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS_n[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS_n[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS_n[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS_n[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS_n[4] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS_n[5] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS_n[6] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS_n[7] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4A_DQS_n[8] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[0] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[1] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[2] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[3] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[4] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[5] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[6] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[7] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[8] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[9] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[10] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[11] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[12] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[13] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[14] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[15] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[16] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[17] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[18] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[19] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[20] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[21] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[22] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[23] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[24] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[25] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[26] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[27] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[28] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[29] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[30] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[31] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[32] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[33] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[34] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[35] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[36] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[37] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[38] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[39] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[40] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[41] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[42] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[43] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[44] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[45] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[46] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[47] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[48] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[49] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[50] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[51] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[52] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[53] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[54] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[55] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[56] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[57] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[58] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[59] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[60] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[61] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[62] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[63] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[64] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[65] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[66] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[67] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[68] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[69] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[70] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DQ[71] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DBI_n[0] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DBI_n[1] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DBI_n[2] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DBI_n[3] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DBI_n[4] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DBI_n[5] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DBI_n[6] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DBI_n[7] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4A_DBI_n[8] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_CS_n +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4A_RESET_n +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_ODT +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_PAR +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4A_ALERT_n +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4A_ACT_n +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4A_EVENT_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to DDR4A_SCL +set_instance_assignment -name IO_STANDARD "1.8 V" -to DDR4A_SDA +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4A_RZQ +set_location_assignment PIN_M35 -to DDR4A_REFCLK_p +set_location_assignment PIN_K38 -to DDR4A_A[0] +set_location_assignment PIN_L37 -to DDR4A_A[1] +set_location_assignment PIN_M37 -to DDR4A_A[2] +set_location_assignment PIN_M38 -to DDR4A_A[3] +set_location_assignment PIN_J39 -to DDR4A_A[4] +set_location_assignment PIN_J38 -to DDR4A_A[5] +set_location_assignment PIN_K39 -to DDR4A_A[6] +set_location_assignment PIN_L39 -to DDR4A_A[7] +set_location_assignment PIN_P37 -to DDR4A_A[8] +set_location_assignment PIN_R37 -to DDR4A_A[9] +set_location_assignment PIN_N37 -to DDR4A_A[10] +set_location_assignment PIN_P38 -to DDR4A_A[11] +set_location_assignment PIN_P35 -to DDR4A_A[12] +set_location_assignment PIN_K36 -to DDR4A_A[13] +set_location_assignment PIN_K37 -to DDR4A_A[14] +set_location_assignment PIN_N36 -to DDR4A_A[15] +set_location_assignment PIN_P36 -to DDR4A_A[16] +set_location_assignment PIN_L36 -to DDR4A_BA[0] +set_location_assignment PIN_T35 -to DDR4A_BA[1] +set_location_assignment PIN_R36 -to DDR4A_BG[0] +set_location_assignment PIN_D40 -to DDR4A_BG[1] +set_location_assignment PIN_F39 -to DDR4A_CK +set_location_assignment PIN_G39 -to DDR4A_CK_n +set_location_assignment PIN_L40 -to DDR4A_CKE +set_location_assignment PIN_A36 -to DDR4A_DQS[0] +set_location_assignment PIN_E36 -to DDR4A_DQS[1] +set_location_assignment PIN_G33 -to DDR4A_DQS[2] +set_location_assignment PIN_L32 -to DDR4A_DQS[3] +set_location_assignment PIN_T26 -to DDR4A_DQS[4] +set_location_assignment PIN_V28 -to DDR4A_DQS[5] +set_location_assignment PIN_J26 -to DDR4A_DQS[6] +set_location_assignment PIN_E26 -to DDR4A_DQS[7] +set_location_assignment PIN_R32 -to DDR4A_DQS[8] +set_location_assignment PIN_A35 -to DDR4A_DQS_n[0] +set_location_assignment PIN_F36 -to DDR4A_DQS_n[1] +set_location_assignment PIN_G34 -to DDR4A_DQS_n[2] +set_location_assignment PIN_L31 -to DDR4A_DQS_n[3] +set_location_assignment PIN_R27 -to DDR4A_DQS_n[4] +set_location_assignment PIN_V27 -to DDR4A_DQS_n[5] +set_location_assignment PIN_K26 -to DDR4A_DQS_n[6] +set_location_assignment PIN_F26 -to DDR4A_DQS_n[7] +set_location_assignment PIN_T32 -to DDR4A_DQS_n[8] +set_location_assignment PIN_A37 -to DDR4A_DQ[0] +set_location_assignment PIN_B37 -to DDR4A_DQ[1] +set_location_assignment PIN_B35 -to DDR4A_DQ[2] +set_location_assignment PIN_C37 -to DDR4A_DQ[3] +set_location_assignment PIN_B38 -to DDR4A_DQ[4] +set_location_assignment PIN_C38 -to DDR4A_DQ[5] +set_location_assignment PIN_C35 -to DDR4A_DQ[6] +set_location_assignment PIN_D36 -to DDR4A_DQ[7] +set_location_assignment PIN_H37 -to DDR4A_DQ[8] +set_location_assignment PIN_E39 -to DDR4A_DQ[9] +set_location_assignment PIN_E37 -to DDR4A_DQ[10] +set_location_assignment PIN_D35 -to DDR4A_DQ[11] +set_location_assignment PIN_E38 -to DDR4A_DQ[12] +set_location_assignment PIN_D38 -to DDR4A_DQ[13] +set_location_assignment PIN_D34 -to DDR4A_DQ[14] +set_location_assignment PIN_F37 -to DDR4A_DQ[15] +set_location_assignment PIN_F35 -to DDR4A_DQ[16] +set_location_assignment PIN_J36 -to DDR4A_DQ[17] +set_location_assignment PIN_J35 -to DDR4A_DQ[18] +set_location_assignment PIN_E34 -to DDR4A_DQ[19] +set_location_assignment PIN_G35 -to DDR4A_DQ[20] +set_location_assignment PIN_H36 -to DDR4A_DQ[21] +set_location_assignment PIN_H35 -to DDR4A_DQ[22] +set_location_assignment PIN_H33 -to DDR4A_DQ[23] +set_location_assignment PIN_N32 -to DDR4A_DQ[24] +set_location_assignment PIN_M33 -to DDR4A_DQ[25] +set_location_assignment PIN_K34 -to DDR4A_DQ[26] +set_location_assignment PIN_M34 -to DDR4A_DQ[27] +set_location_assignment PIN_N33 -to DDR4A_DQ[28] +set_location_assignment PIN_N31 -to DDR4A_DQ[29] +set_location_assignment PIN_K33 -to DDR4A_DQ[30] +set_location_assignment PIN_K32 -to DDR4A_DQ[31] +set_location_assignment PIN_M25 -to DDR4A_DQ[32] +set_location_assignment PIN_P25 -to DDR4A_DQ[33] +set_location_assignment PIN_T25 -to DDR4A_DQ[34] +set_location_assignment PIN_R26 -to DDR4A_DQ[35] +set_location_assignment PIN_L25 -to DDR4A_DQ[36] +set_location_assignment PIN_N27 -to DDR4A_DQ[37] +set_location_assignment PIN_U25 -to DDR4A_DQ[38] +set_location_assignment PIN_P26 -to DDR4A_DQ[39] +set_location_assignment PIN_U27 -to DDR4A_DQ[40] +set_location_assignment PIN_T29 -to DDR4A_DQ[41] +set_location_assignment PIN_V25 -to DDR4A_DQ[42] +set_location_assignment PIN_U29 -to DDR4A_DQ[43] +set_location_assignment PIN_U28 -to DDR4A_DQ[44] +set_location_assignment PIN_T30 -to DDR4A_DQ[45] +set_location_assignment PIN_V26 -to DDR4A_DQ[46] +set_location_assignment PIN_U30 -to DDR4A_DQ[47] +set_location_assignment PIN_F25 -to DDR4A_DQ[48] +set_location_assignment PIN_K27 -to DDR4A_DQ[49] +set_location_assignment PIN_L27 -to DDR4A_DQ[50] +set_location_assignment PIN_H26 -to DDR4A_DQ[51] +set_location_assignment PIN_H25 -to DDR4A_DQ[52] +set_location_assignment PIN_H27 -to DDR4A_DQ[53] +set_location_assignment PIN_M27 -to DDR4A_DQ[54] +set_location_assignment PIN_G25 -to DDR4A_DQ[55] +set_location_assignment PIN_D26 -to DDR4A_DQ[56] +set_location_assignment PIN_B27 -to DDR4A_DQ[57] +set_location_assignment PIN_G27 -to DDR4A_DQ[58] +set_location_assignment PIN_B25 -to DDR4A_DQ[59] +set_location_assignment PIN_C27 -to DDR4A_DQ[60] +set_location_assignment PIN_C26 -to DDR4A_DQ[61] +set_location_assignment PIN_F27 -to DDR4A_DQ[62] +set_location_assignment PIN_D25 -to DDR4A_DQ[63] +set_location_assignment PIN_R31 -to DDR4A_DQ[64] +set_location_assignment PIN_T34 -to DDR4A_DQ[65] +set_location_assignment PIN_R34 -to DDR4A_DQ[66] +set_location_assignment PIN_P33 -to DDR4A_DQ[67] +set_location_assignment PIN_T31 -to DDR4A_DQ[68] +set_location_assignment PIN_U33 -to DDR4A_DQ[69] +set_location_assignment PIN_V32 -to DDR4A_DQ[70] +set_location_assignment PIN_U32 -to DDR4A_DQ[71] +set_location_assignment PIN_C36 -to DDR4A_DBI_n[0] +set_location_assignment PIN_D39 -to DDR4A_DBI_n[1] +set_location_assignment PIN_F34 -to DDR4A_DBI_n[2] +set_location_assignment PIN_J34 -to DDR4A_DBI_n[3] +set_location_assignment PIN_N25 -to DDR4A_DBI_n[4] +set_location_assignment PIN_V30 -to DDR4A_DBI_n[5] +set_location_assignment PIN_L26 -to DDR4A_DBI_n[6] +set_location_assignment PIN_E27 -to DDR4A_DBI_n[7] +set_location_assignment PIN_U34 -to DDR4A_DBI_n[8] +set_location_assignment PIN_G38 -to DDR4A_CS_n +set_location_assignment PIN_E40 -to DDR4A_RESET_n +set_location_assignment PIN_G40 -to DDR4A_ODT +set_location_assignment PIN_H40 -to DDR4A_PAR +set_location_assignment PIN_A38 -to DDR4A_ALERT_n +set_location_assignment PIN_H38 -to DDR4A_ACT_n +set_location_assignment PIN_J33 -to DDR4A_EVENT_n +set_location_assignment PIN_L24 -to DDR4A_SCL +set_location_assignment PIN_T24 -to DDR4A_SDA +set_location_assignment PIN_P34 -to DDR4A_RZQ + +#============================================================ +# DDR4B +#============================================================ +set_instance_assignment -name IO_STANDARD "LVDS" -to DDR4B_REFCLK_p +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[0] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[1] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[2] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[3] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[4] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[5] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[6] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[7] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[8] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[9] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[10] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[11] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[12] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[13] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[14] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[15] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_A[16] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_BA[0] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_BA[1] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_BG[0] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_BG[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to DDR4B_CK +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to DDR4B_CK_n +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_CKE +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS[4] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS[5] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS[6] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS[7] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS[8] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS_n[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS_n[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS_n[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS_n[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS_n[4] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS_n[5] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS_n[6] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS_n[7] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4B_DQS_n[8] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[0] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[1] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[2] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[3] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[4] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[5] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[6] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[7] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[8] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[9] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[10] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[11] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[12] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[13] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[14] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[15] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[16] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[17] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[18] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[19] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[20] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[21] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[22] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[23] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[24] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[25] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[26] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[27] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[28] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[29] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[30] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[31] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[32] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[33] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[34] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[35] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[36] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[37] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[38] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[39] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[40] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[41] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[42] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[43] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[44] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[45] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[46] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[47] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[48] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[49] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[50] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[51] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[52] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[53] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[54] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[55] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[56] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[57] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[58] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[59] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[60] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[61] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[62] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[63] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[64] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[65] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[66] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[67] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[68] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[69] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[70] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DQ[71] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DBI_n[0] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DBI_n[1] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DBI_n[2] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DBI_n[3] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DBI_n[4] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DBI_n[5] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DBI_n[6] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DBI_n[7] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4B_DBI_n[8] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_CS_n +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4B_RESET_n +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_ODT +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_PAR +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4B_ALERT_n +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4B_ACT_n +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4B_EVENT_n +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4B_SCL +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4B_SDA +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4B_RZQ +set_location_assignment PIN_J16 -to DDR4B_REFCLK_p +set_location_assignment PIN_C16 -to DDR4B_A[0] +set_location_assignment PIN_D16 -to DDR4B_A[1] +set_location_assignment PIN_A14 -to DDR4B_A[2] +set_location_assignment PIN_A15 -to DDR4B_A[3] +set_location_assignment PIN_B14 -to DDR4B_A[4] +set_location_assignment PIN_B13 -to DDR4B_A[5] +set_location_assignment PIN_A16 -to DDR4B_A[6] +set_location_assignment PIN_B15 -to DDR4B_A[7] +set_location_assignment PIN_C15 -to DDR4B_A[8] +set_location_assignment PIN_D15 -to DDR4B_A[9] +set_location_assignment PIN_E16 -to DDR4B_A[10] +set_location_assignment PIN_F16 -to DDR4B_A[11] +set_location_assignment PIN_L14 -to DDR4B_A[12] +set_location_assignment PIN_H15 -to DDR4B_A[13] +set_location_assignment PIN_J15 -to DDR4B_A[14] +set_location_assignment PIN_G15 -to DDR4B_A[15] +set_location_assignment PIN_F15 -to DDR4B_A[16] +set_location_assignment PIN_H17 -to DDR4B_BA[0] +set_location_assignment PIN_K14 -to DDR4B_BA[1] +set_location_assignment PIN_J14 -to DDR4B_BG[0] +set_location_assignment PIN_G13 -to DDR4B_BG[1] +set_location_assignment PIN_E14 -to DDR4B_CK +set_location_assignment PIN_D14 -to DDR4B_CK_n +set_location_assignment PIN_C13 -to DDR4B_CKE +set_location_assignment PIN_U17 -to DDR4B_DQS[0] +set_location_assignment PIN_P12 -to DDR4B_DQS[1] +set_location_assignment PIN_L12 -to DDR4B_DQS[2] +set_location_assignment PIN_H12 -to DDR4B_DQS[3] +set_location_assignment PIN_M20 -to DDR4B_DQS[4] +set_location_assignment PIN_F20 -to DDR4B_DQS[5] +set_location_assignment PIN_D20 -to DDR4B_DQS[6] +set_location_assignment PIN_C17 -to DDR4B_DQS[7] +set_location_assignment PIN_L17 -to DDR4B_DQS[8] +set_location_assignment PIN_T17 -to DDR4B_DQS_n[0] +set_location_assignment PIN_P13 -to DDR4B_DQS_n[1] +set_location_assignment PIN_M12 -to DDR4B_DQS_n[2] +set_location_assignment PIN_G12 -to DDR4B_DQS_n[3] +set_location_assignment PIN_L20 -to DDR4B_DQS_n[4] +set_location_assignment PIN_F21 -to DDR4B_DQS_n[5] +set_location_assignment PIN_C20 -to DDR4B_DQS_n[6] +set_location_assignment PIN_C18 -to DDR4B_DQS_n[7] +set_location_assignment PIN_K17 -to DDR4B_DQS_n[8] +set_location_assignment PIN_T16 -to DDR4B_DQ[0] +set_location_assignment PIN_V18 -to DDR4B_DQ[1] +set_location_assignment PIN_R19 -to DDR4B_DQ[2] +set_location_assignment PIN_U18 -to DDR4B_DQ[3] +set_location_assignment PIN_U19 -to DDR4B_DQ[4] +set_location_assignment PIN_W18 -to DDR4B_DQ[5] +set_location_assignment PIN_R18 -to DDR4B_DQ[6] +set_location_assignment PIN_V17 -to DDR4B_DQ[7] +set_location_assignment PIN_P16 -to DDR4B_DQ[8] +set_location_assignment PIN_P14 -to DDR4B_DQ[9] +set_location_assignment PIN_P15 -to DDR4B_DQ[10] +set_location_assignment PIN_R13 -to DDR4B_DQ[11] +set_location_assignment PIN_R17 -to DDR4B_DQ[12] +set_location_assignment PIN_N13 -to DDR4B_DQ[13] +set_location_assignment PIN_R14 -to DDR4B_DQ[14] +set_location_assignment PIN_M13 -to DDR4B_DQ[15] +set_location_assignment PIN_J11 -to DDR4B_DQ[16] +set_location_assignment PIN_K10 -to DDR4B_DQ[17] +set_location_assignment PIN_K11 -to DDR4B_DQ[18] +set_location_assignment PIN_J13 -to DDR4B_DQ[19] +set_location_assignment PIN_K13 -to DDR4B_DQ[20] +set_location_assignment PIN_L10 -to DDR4B_DQ[21] +set_location_assignment PIN_K12 -to DDR4B_DQ[22] +set_location_assignment PIN_H11 -to DDR4B_DQ[23] +set_location_assignment PIN_F10 -to DDR4B_DQ[24] +set_location_assignment PIN_E10 -to DDR4B_DQ[25] +set_location_assignment PIN_H10 -to DDR4B_DQ[26] +set_location_assignment PIN_F12 -to DDR4B_DQ[27] +set_location_assignment PIN_G10 -to DDR4B_DQ[28] +set_location_assignment PIN_F11 -to DDR4B_DQ[29] +set_location_assignment PIN_E11 -to DDR4B_DQ[30] +set_location_assignment PIN_E12 -to DDR4B_DQ[31] +set_location_assignment PIN_N20 -to DDR4B_DQ[32] +set_location_assignment PIN_H21 -to DDR4B_DQ[33] +set_location_assignment PIN_P21 -to DDR4B_DQ[34] +set_location_assignment PIN_K19 -to DDR4B_DQ[35] +set_location_assignment PIN_K21 -to DDR4B_DQ[36] +set_location_assignment PIN_J21 -to DDR4B_DQ[37] +set_location_assignment PIN_N21 -to DDR4B_DQ[38] +set_location_assignment PIN_L19 -to DDR4B_DQ[39] +set_location_assignment PIN_H18 -to DDR4B_DQ[40] +set_location_assignment PIN_G19 -to DDR4B_DQ[41] +set_location_assignment PIN_J18 -to DDR4B_DQ[42] +set_location_assignment PIN_G20 -to DDR4B_DQ[43] +set_location_assignment PIN_G18 -to DDR4B_DQ[44] +set_location_assignment PIN_F19 -to DDR4B_DQ[45] +set_location_assignment PIN_K18 -to DDR4B_DQ[46] +set_location_assignment PIN_H20 -to DDR4B_DQ[47] +set_location_assignment PIN_E17 -to DDR4B_DQ[48] +set_location_assignment PIN_D21 -to DDR4B_DQ[49] +set_location_assignment PIN_E18 -to DDR4B_DQ[50] +set_location_assignment PIN_C22 -to DDR4B_DQ[51] +set_location_assignment PIN_D19 -to DDR4B_DQ[52] +set_location_assignment PIN_F17 -to DDR4B_DQ[53] +set_location_assignment PIN_D18 -to DDR4B_DQ[54] +set_location_assignment PIN_C21 -to DDR4B_DQ[55] +set_location_assignment PIN_B20 -to DDR4B_DQ[56] +set_location_assignment PIN_B18 -to DDR4B_DQ[57] +set_location_assignment PIN_B22 -to DDR4B_DQ[58] +set_location_assignment PIN_A17 -to DDR4B_DQ[59] +set_location_assignment PIN_B19 -to DDR4B_DQ[60] +set_location_assignment PIN_A20 -to DDR4B_DQ[61] +set_location_assignment PIN_A22 -to DDR4B_DQ[62] +set_location_assignment PIN_A19 -to DDR4B_DQ[63] +set_location_assignment PIN_P18 -to DDR4B_DQ[64] +set_location_assignment PIN_K16 -to DDR4B_DQ[65] +set_location_assignment PIN_M15 -to DDR4B_DQ[66] +set_location_assignment PIN_M18 -to DDR4B_DQ[67] +set_location_assignment PIN_N16 -to DDR4B_DQ[68] +set_location_assignment PIN_L16 -to DDR4B_DQ[69] +set_location_assignment PIN_N18 -to DDR4B_DQ[70] +set_location_assignment PIN_M17 -to DDR4B_DQ[71] +set_location_assignment PIN_T19 -to DDR4B_DBI_n[0] +set_location_assignment PIN_M14 -to DDR4B_DBI_n[1] +set_location_assignment PIN_J10 -to DDR4B_DBI_n[2] +set_location_assignment PIN_D11 -to DDR4B_DBI_n[3] +set_location_assignment PIN_L21 -to DDR4B_DBI_n[4] +set_location_assignment PIN_J19 -to DDR4B_DBI_n[5] +set_location_assignment PIN_E19 -to DDR4B_DBI_n[6] +set_location_assignment PIN_A21 -to DDR4B_DBI_n[7] +set_location_assignment PIN_N15 -to DDR4B_DBI_n[8] +set_location_assignment PIN_E13 -to DDR4B_CS_n +set_location_assignment PIN_H13 -to DDR4B_RESET_n +set_location_assignment PIN_G14 -to DDR4B_ODT +set_location_assignment PIN_A12 -to DDR4B_PAR +set_location_assignment PIN_T15 -to DDR4B_ALERT_n +set_location_assignment PIN_D13 -to DDR4B_ACT_n +set_location_assignment PIN_L11 -to DDR4B_EVENT_n +set_location_assignment PIN_D10 -to DDR4B_SCL +set_location_assignment PIN_P20 -to DDR4B_SDA +set_location_assignment PIN_L15 -to DDR4B_RZQ + +#============================================================ +# DDR4C +#============================================================ +set_instance_assignment -name IO_STANDARD "LVDS" -to DDR4C_REFCLK_p +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_A[0] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_A[1] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_A[2] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_A[3] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_A[4] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_A[5] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_A[6] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_A[7] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_A[8] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_A[9] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_A[10] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_A[11] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_A[12] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_A[13] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_A[14] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_A[15] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_A[16] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_BA[0] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_BA[1] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_BG[0] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_BG[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to DDR4C_CK +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to DDR4C_CK_n +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_CKE +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4C_DQS[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4C_DQS[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4C_DQS[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4C_DQS[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4C_DQS[4] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4C_DQS[5] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4C_DQS[6] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4C_DQS[7] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4C_DQS[8] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4C_DQS_n[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4C_DQS_n[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4C_DQS_n[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4C_DQS_n[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4C_DQS_n[4] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4C_DQS_n[5] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4C_DQS_n[6] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4C_DQS_n[7] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4C_DQS_n[8] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[0] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[1] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[2] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[3] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[4] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[5] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[6] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[7] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[8] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[9] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[10] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[11] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[12] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[13] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[14] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[15] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[16] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[17] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[18] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[19] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[20] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[21] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[22] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[23] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[24] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[25] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[26] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[27] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[28] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[29] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[30] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[31] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[32] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[33] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[34] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[35] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[36] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[37] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[38] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[39] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[40] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[41] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[42] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[43] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[44] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[45] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[46] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[47] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[48] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[49] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[50] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[51] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[52] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[53] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[54] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[55] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[56] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[57] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[58] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[59] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[60] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[61] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[62] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[63] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[64] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[65] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[66] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[67] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[68] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[69] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[70] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DQ[71] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DBI_n[0] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DBI_n[1] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DBI_n[2] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DBI_n[3] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DBI_n[4] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DBI_n[5] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DBI_n[6] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DBI_n[7] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4C_DBI_n[8] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_CS_n +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4C_RESET_n +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_ODT +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_PAR +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4C_ALERT_n +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4C_ACT_n +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4C_EVENT_n +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4C_SCL +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4C_SDA +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4C_RZQ +set_location_assignment PIN_BH33 -to DDR4C_REFCLK_p +set_location_assignment PIN_AY34 -to DDR4C_A[0] +set_location_assignment PIN_BA34 -to DDR4C_A[1] +set_location_assignment PIN_BA36 -to DDR4C_A[2] +set_location_assignment PIN_AY36 -to DDR4C_A[3] +set_location_assignment PIN_AW34 -to DDR4C_A[4] +set_location_assignment PIN_AW35 -to DDR4C_A[5] +set_location_assignment PIN_BB35 -to DDR4C_A[6] +set_location_assignment PIN_BA35 -to DDR4C_A[7] +set_location_assignment PIN_AW33 -to DDR4C_A[8] +set_location_assignment PIN_AY33 -to DDR4C_A[9] +set_location_assignment PIN_AW36 -to DDR4C_A[10] +set_location_assignment PIN_AV36 -to DDR4C_A[11] +set_location_assignment PIN_BJ36 -to DDR4C_A[12] +set_location_assignment PIN_BE33 -to DDR4C_A[13] +set_location_assignment PIN_BE34 -to DDR4C_A[14] +set_location_assignment PIN_BH35 -to DDR4C_A[15] +set_location_assignment PIN_BG35 -to DDR4C_A[16] +set_location_assignment PIN_BJ34 -to DDR4C_BA[0] +set_location_assignment PIN_BG34 -to DDR4C_BA[1] +set_location_assignment PIN_BF34 -to DDR4C_BG[0] +set_location_assignment PIN_AU34 -to DDR4C_BG[1] +set_location_assignment PIN_AV33 -to DDR4C_CK +set_location_assignment PIN_AV32 -to DDR4C_CK_n +set_location_assignment PIN_AT35 -to DDR4C_CKE +set_location_assignment PIN_AT37 -to DDR4C_DQS[0] +set_location_assignment PIN_AY38 -to DDR4C_DQS[1] +set_location_assignment PIN_BF37 -to DDR4C_DQS[2] +set_location_assignment PIN_BD39 -to DDR4C_DQS[3] +set_location_assignment PIN_BH31 -to DDR4C_DQS[4] +set_location_assignment PIN_BC30 -to DDR4C_DQS[5] +set_location_assignment PIN_BA32 -to DDR4C_DQS[6] +set_location_assignment PIN_AW28 -to DDR4C_DQS[7] +set_location_assignment PIN_BD34 -to DDR4C_DQS[8] +set_location_assignment PIN_AT36 -to DDR4C_DQS_n[0] +set_location_assignment PIN_AY39 -to DDR4C_DQS_n[1] +set_location_assignment PIN_BE37 -to DDR4C_DQS_n[2] +set_location_assignment PIN_BD38 -to DDR4C_DQS_n[3] +set_location_assignment PIN_BJ31 -to DDR4C_DQS_n[4] +set_location_assignment PIN_BD30 -to DDR4C_DQS_n[5] +set_location_assignment PIN_BB32 -to DDR4C_DQS_n[6] +set_location_assignment PIN_AV28 -to DDR4C_DQS_n[7] +set_location_assignment PIN_BD35 -to DDR4C_DQS_n[8] +set_location_assignment PIN_AP35 -to DDR4C_DQ[0] +set_location_assignment PIN_AT38 -to DDR4C_DQ[1] +set_location_assignment PIN_AP36 -to DDR4C_DQ[2] +set_location_assignment PIN_AR33 -to DDR4C_DQ[3] +set_location_assignment PIN_AN33 -to DDR4C_DQ[4] +set_location_assignment PIN_AR37 -to DDR4C_DQ[5] +set_location_assignment PIN_AR36 -to DDR4C_DQ[6] +set_location_assignment PIN_AR34 -to DDR4C_DQ[7] +set_location_assignment PIN_AU38 -to DDR4C_DQ[8] +set_location_assignment PIN_AV40 -to DDR4C_DQ[9] +set_location_assignment PIN_AW40 -to DDR4C_DQ[10] +set_location_assignment PIN_AV37 -to DDR4C_DQ[11] +set_location_assignment PIN_AU37 -to DDR4C_DQ[12] +set_location_assignment PIN_AW39 -to DDR4C_DQ[13] +set_location_assignment PIN_AV38 -to DDR4C_DQ[14] +set_location_assignment PIN_BA37 -to DDR4C_DQ[15] +set_location_assignment PIN_BD40 -to DDR4C_DQ[16] +set_location_assignment PIN_BF39 -to DDR4C_DQ[17] +set_location_assignment PIN_BG38 -to DDR4C_DQ[18] +set_location_assignment PIN_BH36 -to DDR4C_DQ[19] +set_location_assignment PIN_BE38 -to DDR4C_DQ[20] +set_location_assignment PIN_BE39 -to DDR4C_DQ[21] +set_location_assignment PIN_BG37 -to DDR4C_DQ[22] +set_location_assignment PIN_BH37 -to DDR4C_DQ[23] +set_location_assignment PIN_BB38 -to DDR4C_DQ[24] +set_location_assignment PIN_BB39 -to DDR4C_DQ[25] +set_location_assignment PIN_BC38 -to DDR4C_DQ[26] +set_location_assignment PIN_BC37 -to DDR4C_DQ[27] +set_location_assignment PIN_BA40 -to DDR4C_DQ[28] +set_location_assignment PIN_AY40 -to DDR4C_DQ[29] +set_location_assignment PIN_BC40 -to DDR4C_DQ[30] +set_location_assignment PIN_BB37 -to DDR4C_DQ[31] +set_location_assignment PIN_BF29 -to DDR4C_DQ[32] +set_location_assignment PIN_BE28 -to DDR4C_DQ[33] +set_location_assignment PIN_BJ28 -to DDR4C_DQ[34] +set_location_assignment PIN_BJ30 -to DDR4C_DQ[35] +set_location_assignment PIN_BE32 -to DDR4C_DQ[36] +set_location_assignment PIN_BG32 -to DDR4C_DQ[37] +set_location_assignment PIN_BH28 -to DDR4C_DQ[38] +set_location_assignment PIN_BJ29 -to DDR4C_DQ[39] +set_location_assignment PIN_BE31 -to DDR4C_DQ[40] +set_location_assignment PIN_BD29 -to DDR4C_DQ[41] +set_location_assignment PIN_BF31 -to DDR4C_DQ[42] +set_location_assignment PIN_BG30 -to DDR4C_DQ[43] +set_location_assignment PIN_BF30 -to DDR4C_DQ[44] +set_location_assignment PIN_BE29 -to DDR4C_DQ[45] +set_location_assignment PIN_BG29 -to DDR4C_DQ[46] +set_location_assignment PIN_BH30 -to DDR4C_DQ[47] +set_location_assignment PIN_BA31 -to DDR4C_DQ[48] +set_location_assignment PIN_BC32 -to DDR4C_DQ[49] +set_location_assignment PIN_BB30 -to DDR4C_DQ[50] +set_location_assignment PIN_AW31 -to DDR4C_DQ[51] +set_location_assignment PIN_BC31 -to DDR4C_DQ[52] +set_location_assignment PIN_AY32 -to DDR4C_DQ[53] +set_location_assignment PIN_BB29 -to DDR4C_DQ[54] +set_location_assignment PIN_BA30 -to DDR4C_DQ[55] +set_location_assignment PIN_AU28 -to DDR4C_DQ[56] +set_location_assignment PIN_AT29 -to DDR4C_DQ[57] +set_location_assignment PIN_AW29 -to DDR4C_DQ[58] +set_location_assignment PIN_AY29 -to DDR4C_DQ[59] +set_location_assignment PIN_AT30 -to DDR4C_DQ[60] +set_location_assignment PIN_AU29 -to DDR4C_DQ[61] +set_location_assignment PIN_AU30 -to DDR4C_DQ[62] +set_location_assignment PIN_BA29 -to DDR4C_DQ[63] +set_location_assignment PIN_BD36 -to DDR4C_DQ[64] +set_location_assignment PIN_BF35 -to DDR4C_DQ[65] +set_location_assignment PIN_BC36 -to DDR4C_DQ[66] +set_location_assignment PIN_BD33 -to DDR4C_DQ[67] +set_location_assignment PIN_BE36 -to DDR4C_DQ[68] +set_location_assignment PIN_BF36 -to DDR4C_DQ[69] +set_location_assignment PIN_BB34 -to DDR4C_DQ[70] +set_location_assignment PIN_BB33 -to DDR4C_DQ[71] +set_location_assignment PIN_AP33 -to DDR4C_DBI_n[0] +set_location_assignment PIN_AY37 -to DDR4C_DBI_n[1] +set_location_assignment PIN_BE40 -to DDR4C_DBI_n[2] +set_location_assignment PIN_BB40 -to DDR4C_DBI_n[3] +set_location_assignment PIN_BF32 -to DDR4C_DBI_n[4] +set_location_assignment PIN_BD31 -to DDR4C_DBI_n[5] +set_location_assignment PIN_AW30 -to DDR4C_DBI_n[6] +set_location_assignment PIN_AV30 -to DDR4C_DBI_n[7] +set_location_assignment PIN_BC35 -to DDR4C_DBI_n[8] +set_location_assignment PIN_AV35 -to DDR4C_CS_n +set_location_assignment PIN_AU33 -to DDR4C_RESET_n +set_location_assignment PIN_AR32 -to DDR4C_ODT +set_location_assignment PIN_AT32 -to DDR4C_PAR +set_location_assignment PIN_AP34 -to DDR4C_ALERT_n +set_location_assignment PIN_AU35 -to DDR4C_ACT_n +set_location_assignment PIN_AY31 -to DDR4C_EVENT_n +set_location_assignment PIN_BB28 -to DDR4C_SCL +set_location_assignment PIN_BH32 -to DDR4C_SDA +set_location_assignment PIN_BJ35 -to DDR4C_RZQ + +#============================================================ +# DDR4D +#============================================================ +set_instance_assignment -name IO_STANDARD "LVDS" -to DDR4D_REFCLK_p +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_A[0] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_A[1] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_A[2] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_A[3] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_A[4] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_A[5] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_A[6] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_A[7] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_A[8] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_A[9] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_A[10] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_A[11] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_A[12] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_A[13] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_A[14] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_A[15] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_A[16] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_BA[0] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_BA[1] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_BG[0] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_BG[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to DDR4D_CK +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to DDR4D_CK_n +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_CKE +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4D_DQS[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4D_DQS[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4D_DQS[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4D_DQS[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4D_DQS[4] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4D_DQS[5] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4D_DQS[6] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4D_DQS[7] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4D_DQS[8] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4D_DQS_n[0] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4D_DQS_n[1] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4D_DQS_n[2] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4D_DQS_n[3] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4D_DQS_n[4] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4D_DQS_n[5] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4D_DQS_n[6] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4D_DQS_n[7] +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to DDR4D_DQS_n[8] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[0] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[1] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[2] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[3] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[4] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[5] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[6] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[7] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[8] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[9] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[10] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[11] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[12] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[13] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[14] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[15] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[16] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[17] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[18] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[19] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[20] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[21] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[22] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[23] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[24] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[25] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[26] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[27] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[28] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[29] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[30] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[31] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[32] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[33] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[34] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[35] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[36] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[37] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[38] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[39] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[40] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[41] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[42] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[43] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[44] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[45] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[46] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[47] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[48] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[49] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[50] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[51] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[52] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[53] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[54] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[55] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[56] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[57] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[58] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[59] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[60] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[61] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[62] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[63] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[64] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[65] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[66] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[67] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[68] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[69] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[70] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DQ[71] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DBI_n[0] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DBI_n[1] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DBI_n[2] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DBI_n[3] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DBI_n[4] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DBI_n[5] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DBI_n[6] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DBI_n[7] +set_instance_assignment -name IO_STANDARD "1.2-V POD" -to DDR4D_DBI_n[8] +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_CS_n +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4D_RESET_n +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_ODT +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_PAR +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4D_ALERT_n +set_instance_assignment -name IO_STANDARD "SSTL-12" -to DDR4D_ACT_n +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4D_EVENT_n +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4D_SCL +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4D_SDA +set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4D_RZQ +set_location_assignment PIN_AT17 -to DDR4D_REFCLK_p +set_location_assignment PIN_AY11 -to DDR4D_A[0] +set_location_assignment PIN_AW11 -to DDR4D_A[1] +set_location_assignment PIN_BA10 -to DDR4D_A[2] +set_location_assignment PIN_BA11 -to DDR4D_A[3] +set_location_assignment PIN_BA12 -to DDR4D_A[4] +set_location_assignment PIN_AY12 -to DDR4D_A[5] +set_location_assignment PIN_AV11 -to DDR4D_A[6] +set_location_assignment PIN_AV12 -to DDR4D_A[7] +set_location_assignment PIN_AW13 -to DDR4D_A[8] +set_location_assignment PIN_AY13 -to DDR4D_A[9] +set_location_assignment PIN_AW10 -to DDR4D_A[10] +set_location_assignment PIN_AV10 -to DDR4D_A[11] +set_location_assignment PIN_AN18 -to DDR4D_A[12] +set_location_assignment PIN_AR17 -to DDR4D_A[13] +set_location_assignment PIN_AR16 -to DDR4D_A[14] +set_location_assignment PIN_AT15 -to DDR4D_A[15] +set_location_assignment PIN_AT16 -to DDR4D_A[16] +set_location_assignment PIN_AU14 -to DDR4D_BA[0] +set_location_assignment PIN_AP18 -to DDR4D_BA[1] +set_location_assignment PIN_AR18 -to DDR4D_BG[0] +set_location_assignment PIN_BF11 -to DDR4D_BG[1] +set_location_assignment PIN_BC12 -to DDR4D_CK +set_location_assignment PIN_BB12 -to DDR4D_CK_n +set_location_assignment PIN_BC10 -to DDR4D_CKE +set_location_assignment PIN_BJ19 -to DDR4D_DQS[0] +set_location_assignment PIN_BE19 -to DDR4D_DQS[1] +set_location_assignment PIN_AN21 -to DDR4D_DQS[2] +set_location_assignment PIN_AW21 -to DDR4D_DQS[3] +set_location_assignment PIN_AW18 -to DDR4D_DQS[4] +set_location_assignment PIN_BA14 -to DDR4D_DQS[5] +set_location_assignment PIN_BJ15 -to DDR4D_DQS[6] +set_location_assignment PIN_BF16 -to DDR4D_DQS[7] +set_location_assignment PIN_AP12 -to DDR4D_DQS[8] +set_location_assignment PIN_BJ20 -to DDR4D_DQS_n[0] +set_location_assignment PIN_BF19 -to DDR4D_DQS_n[1] +set_location_assignment PIN_AP21 -to DDR4D_DQS_n[2] +set_location_assignment PIN_AY21 -to DDR4D_DQS_n[3] +set_location_assignment PIN_AV18 -to DDR4D_DQS_n[4] +set_location_assignment PIN_BB14 -to DDR4D_DQS_n[5] +set_location_assignment PIN_BH15 -to DDR4D_DQS_n[6] +set_location_assignment PIN_BE16 -to DDR4D_DQS_n[7] +set_location_assignment PIN_AR13 -to DDR4D_DQS_n[8] +set_location_assignment PIN_BF17 -to DDR4D_DQ[0] +set_location_assignment PIN_BG19 -to DDR4D_DQ[1] +set_location_assignment PIN_BH20 -to DDR4D_DQ[2] +set_location_assignment PIN_BG17 -to DDR4D_DQ[3] +set_location_assignment PIN_BG18 -to DDR4D_DQ[4] +set_location_assignment PIN_BH17 -to DDR4D_DQ[5] +set_location_assignment PIN_BH21 -to DDR4D_DQ[6] +set_location_assignment PIN_BJ18 -to DDR4D_DQ[7] +set_location_assignment PIN_BD20 -to DDR4D_DQ[8] +set_location_assignment PIN_BB18 -to DDR4D_DQ[9] +set_location_assignment PIN_BD19 -to DDR4D_DQ[10] +set_location_assignment PIN_BE18 -to DDR4D_DQ[11] +set_location_assignment PIN_BE21 -to DDR4D_DQ[12] +set_location_assignment PIN_BC18 -to DDR4D_DQ[13] +set_location_assignment PIN_BD18 -to DDR4D_DQ[14] +set_location_assignment PIN_BG20 -to DDR4D_DQ[15] +set_location_assignment PIN_AT19 -to DDR4D_DQ[16] +set_location_assignment PIN_AR21 -to DDR4D_DQ[17] +set_location_assignment PIN_AU20 -to DDR4D_DQ[18] +set_location_assignment PIN_AV20 -to DDR4D_DQ[19] +set_location_assignment PIN_AR19 -to DDR4D_DQ[20] +set_location_assignment PIN_AT21 -to DDR4D_DQ[21] +set_location_assignment PIN_AT20 -to DDR4D_DQ[22] +set_location_assignment PIN_AP20 -to DDR4D_DQ[23] +set_location_assignment PIN_BC20 -to DDR4D_DQ[24] +set_location_assignment PIN_BD21 -to DDR4D_DQ[25] +set_location_assignment PIN_BA21 -to DDR4D_DQ[26] +set_location_assignment PIN_BA19 -to DDR4D_DQ[27] +set_location_assignment PIN_AW19 -to DDR4D_DQ[28] +set_location_assignment PIN_AW20 -to DDR4D_DQ[29] +set_location_assignment PIN_BA20 -to DDR4D_DQ[30] +set_location_assignment PIN_BB19 -to DDR4D_DQ[31] +set_location_assignment PIN_AY16 -to DDR4D_DQ[32] +set_location_assignment PIN_AV17 -to DDR4D_DQ[33] +set_location_assignment PIN_BB17 -to DDR4D_DQ[34] +set_location_assignment PIN_AY17 -to DDR4D_DQ[35] +set_location_assignment PIN_AV16 -to DDR4D_DQ[36] +set_location_assignment PIN_AW16 -to DDR4D_DQ[37] +set_location_assignment PIN_BC17 -to DDR4D_DQ[38] +set_location_assignment PIN_BA17 -to DDR4D_DQ[39] +set_location_assignment PIN_BC15 -to DDR4D_DQ[40] +set_location_assignment PIN_BA16 -to DDR4D_DQ[41] +set_location_assignment PIN_AV15 -to DDR4D_DQ[42] +set_location_assignment PIN_BC13 -to DDR4D_DQ[43] +set_location_assignment PIN_AW14 -to DDR4D_DQ[44] +set_location_assignment PIN_BA15 -to DDR4D_DQ[45] +set_location_assignment PIN_AW15 -to DDR4D_DQ[46] +set_location_assignment PIN_BB13 -to DDR4D_DQ[47] +set_location_assignment PIN_BJ16 -to DDR4D_DQ[48] +set_location_assignment PIN_BH12 -to DDR4D_DQ[49] +set_location_assignment PIN_BJ14 -to DDR4D_DQ[50] +set_location_assignment PIN_BF12 -to DDR4D_DQ[51] +set_location_assignment PIN_BG13 -to DDR4D_DQ[52] +set_location_assignment PIN_BH16 -to DDR4D_DQ[53] +set_location_assignment PIN_BJ13 -to DDR4D_DQ[54] +set_location_assignment PIN_BG12 -to DDR4D_DQ[55] +set_location_assignment PIN_BF14 -to DDR4D_DQ[56] +set_location_assignment PIN_BD15 -to DDR4D_DQ[57] +set_location_assignment PIN_BD16 -to DDR4D_DQ[58] +set_location_assignment PIN_BC16 -to DDR4D_DQ[59] +set_location_assignment PIN_BD14 -to DDR4D_DQ[60] +set_location_assignment PIN_BF15 -to DDR4D_DQ[61] +set_location_assignment PIN_BE13 -to DDR4D_DQ[62] +set_location_assignment PIN_BG15 -to DDR4D_DQ[63] +set_location_assignment PIN_AT12 -to DDR4D_DQ[64] +set_location_assignment PIN_AP15 -to DDR4D_DQ[65] +set_location_assignment PIN_AT14 -to DDR4D_DQ[66] +set_location_assignment PIN_AR14 -to DDR4D_DQ[67] +set_location_assignment PIN_AP13 -to DDR4D_DQ[68] +set_location_assignment PIN_AP16 -to DDR4D_DQ[69] +set_location_assignment PIN_AU12 -to DDR4D_DQ[70] +set_location_assignment PIN_AV13 -to DDR4D_DQ[71] +set_location_assignment PIN_BE17 -to DDR4D_DBI_n[0] +set_location_assignment PIN_BF20 -to DDR4D_DBI_n[1] +set_location_assignment PIN_AN20 -to DDR4D_DBI_n[2] +set_location_assignment PIN_BC21 -to DDR4D_DBI_n[3] +set_location_assignment PIN_AY18 -to DDR4D_DBI_n[4] +set_location_assignment PIN_AY14 -to DDR4D_DBI_n[5] +set_location_assignment PIN_BG14 -to DDR4D_DBI_n[6] +set_location_assignment PIN_BD13 -to DDR4D_DBI_n[7] +set_location_assignment PIN_AU13 -to DDR4D_DBI_n[8] +set_location_assignment PIN_BE10 -to DDR4D_CS_n +set_location_assignment PIN_BF10 -to DDR4D_RESET_n +set_location_assignment PIN_BE12 -to DDR4D_ODT +set_location_assignment PIN_BC11 -to DDR4D_PAR +set_location_assignment PIN_BH18 -to DDR4D_ALERT_n +set_location_assignment PIN_BD10 -to DDR4D_ACT_n +set_location_assignment PIN_BH13 -to DDR4D_EVENT_n +set_location_assignment PIN_BE14 -to DDR4D_SCL +set_location_assignment PIN_AY19 -to DDR4D_SDA +set_location_assignment PIN_AN17 -to DDR4D_RZQ + +#============================================================ +# SI5340A0 +#============================================================ +set_instance_assignment -name IO_STANDARD "1.8 V" -to SI5340A0_I2C_SCL +set_instance_assignment -name IO_STANDARD "1.8 V" -to SI5340A0_I2C_SDA +set_instance_assignment -name IO_STANDARD "1.8 V" -to SI5340A0_INTR +set_instance_assignment -name IO_STANDARD "1.8 V" -to SI5340A0_OE_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to SI5340A0_RST_n +set_location_assignment PIN_BJ25 -to SI5340A0_I2C_SCL +set_location_assignment PIN_BJ26 -to SI5340A0_I2C_SDA +set_location_assignment PIN_BH26 -to SI5340A0_INTR +set_location_assignment PIN_BH25 -to SI5340A0_OE_n +set_location_assignment PIN_BH27 -to SI5340A0_RST_n + +#============================================================ +# SI5340A1 +#============================================================ +set_instance_assignment -name IO_STANDARD "1.8 V" -to SI5340A1_I2C_SCL +set_instance_assignment -name IO_STANDARD "1.8 V" -to SI5340A1_I2C_SDA +set_instance_assignment -name IO_STANDARD "1.8 V" -to SI5340A1_INTR +set_instance_assignment -name IO_STANDARD "1.8 V" -to SI5340A1_OE_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to SI5340A1_RST_n +set_location_assignment PIN_G22 -to SI5340A1_I2C_SCL +set_location_assignment PIN_H22 -to SI5340A1_I2C_SDA +set_location_assignment PIN_H23 -to SI5340A1_INTR +set_location_assignment PIN_G23 -to SI5340A1_OE_n +set_location_assignment PIN_G24 -to SI5340A1_RST_n + +#============================================================ +# I2Cs +#============================================================ +set_instance_assignment -name IO_STANDARD "1.8 V" -to FAN_I2C_SCL +set_instance_assignment -name IO_STANDARD "1.8 V" -to FAN_I2C_SDA +set_instance_assignment -name IO_STANDARD "1.8 V" -to FAN_ALERT_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to POWER_MONITOR_I2C_SCL +set_instance_assignment -name IO_STANDARD "1.8 V" -to POWER_MONITOR_I2C_SDA +set_instance_assignment -name IO_STANDARD "1.8 V" -to POWER_MONITOR_ALERT_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to TEMP_I2C_SCL +set_instance_assignment -name IO_STANDARD "1.8 V" -to TEMP_I2C_SDA +set_location_assignment PIN_BD26 -to FAN_I2C_SCL +set_location_assignment PIN_BE27 -to FAN_I2C_SDA +set_location_assignment PIN_BE26 -to FAN_ALERT_n +set_location_assignment PIN_F24 -to POWER_MONITOR_I2C_SCL +set_location_assignment PIN_F22 -to POWER_MONITOR_I2C_SDA +set_location_assignment PIN_E24 -to POWER_MONITOR_ALERT_n +set_location_assignment PIN_E22 -to TEMP_I2C_SCL +set_location_assignment PIN_E23 -to TEMP_I2C_SDA + +#============================================================ +# GPIO +#============================================================ +set_instance_assignment -name IO_STANDARD "1.8 V" -to GPIO_CLK[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to GPIO_CLK[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to GPIO_P[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to GPIO_P[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to GPIO_P[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to GPIO_P[3] +set_location_assignment PIN_BA27 -to GPIO_CLK[0] +set_location_assignment PIN_BA26 -to GPIO_CLK[1] +set_location_assignment PIN_BB25 -to GPIO_P[0] +set_location_assignment PIN_BC26 -to GPIO_P[1] +set_location_assignment PIN_BC25 -to GPIO_P[2] +set_location_assignment PIN_BA25 -to GPIO_P[3] + +#============================================================ +# PCIE +#============================================================ +set_instance_assignment -name IO_STANDARD "1.2 V" -to PCIE_SMBCLK +set_instance_assignment -name IO_STANDARD "1.2 V" -to PCIE_SMBDAT +set_instance_assignment -name IO_STANDARD "HCSL" -to PCIE_REFCLK_p +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_p[0] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_p[1] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_p[2] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_p[3] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_p[4] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_p[5] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_p[6] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_p[7] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_p[8] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_p[9] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_p[10] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_p[11] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_p[12] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_p[13] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_p[14] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_p[15] +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to PCIE_RX_p[0] +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to PCIE_RX_p[1] +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to PCIE_RX_p[2] +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to PCIE_RX_p[3] +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to PCIE_RX_p[4] +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to PCIE_RX_p[5] +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to PCIE_RX_p[6] +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to PCIE_RX_p[7] +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to PCIE_RX_p[8] +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to PCIE_RX_p[9] +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to PCIE_RX_p[10] +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to PCIE_RX_p[11] +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to PCIE_RX_p[12] +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to PCIE_RX_p[13] +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to PCIE_RX_p[14] +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to PCIE_RX_p[15] +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PCIE_PERST_n +set_instance_assignment -name IO_STANDARD "1.2 V" -to PCIE_WAKE_n +set_location_assignment PIN_BA39 -to PCIE_SMBCLK +set_location_assignment PIN_BF40 -to PCIE_SMBDAT +set_location_assignment PIN_AM41 -to PCIE_REFCLK_p +set_location_assignment PIN_BJ46 -to PCIE_TX_p[0] +set_location_assignment PIN_BF45 -to PCIE_TX_p[1] +set_location_assignment PIN_BG47 -to PCIE_TX_p[2] +set_location_assignment PIN_BE47 -to PCIE_TX_p[3] +set_location_assignment PIN_BF49 -to PCIE_TX_p[4] +set_location_assignment PIN_BC47 -to PCIE_TX_p[5] +set_location_assignment PIN_BD49 -to PCIE_TX_p[6] +set_location_assignment PIN_BA47 -to PCIE_TX_p[7] +set_location_assignment PIN_BB49 -to PCIE_TX_p[8] +set_location_assignment PIN_AW47 -to PCIE_TX_p[9] +set_location_assignment PIN_AY49 -to PCIE_TX_p[10] +set_location_assignment PIN_AU47 -to PCIE_TX_p[11] +set_location_assignment PIN_AV49 -to PCIE_TX_p[12] +set_location_assignment PIN_AR47 -to PCIE_TX_p[13] +set_location_assignment PIN_AT49 -to PCIE_TX_p[14] +set_location_assignment PIN_AP49 -to PCIE_TX_p[15] +set_location_assignment PIN_BH41 -to PCIE_RX_p[0] +set_location_assignment PIN_BJ43 -to PCIE_RX_p[1] +set_location_assignment PIN_BG43 -to PCIE_RX_p[2] +set_location_assignment PIN_BE43 -to PCIE_RX_p[3] +set_location_assignment PIN_BC43 -to PCIE_RX_p[4] +set_location_assignment PIN_BD45 -to PCIE_RX_p[5] +set_location_assignment PIN_BA43 -to PCIE_RX_p[6] +set_location_assignment PIN_BB45 -to PCIE_RX_p[7] +set_location_assignment PIN_AW43 -to PCIE_RX_p[8] +set_location_assignment PIN_AY45 -to PCIE_RX_p[9] +set_location_assignment PIN_AU43 -to PCIE_RX_p[10] +set_location_assignment PIN_AV45 -to PCIE_RX_p[11] +set_location_assignment PIN_AR43 -to PCIE_RX_p[12] +set_location_assignment PIN_AT45 -to PCIE_RX_p[13] +set_location_assignment PIN_AP45 -to PCIE_RX_p[14] +set_location_assignment PIN_AN43 -to PCIE_RX_p[15] +set_location_assignment PIN_AJ34 -to PCIE_PERST_n +set_location_assignment PIN_BC33 -to PCIE_WAKE_n + +#============================================================ +# QSFP28A +#============================================================ +set_instance_assignment -name IO_STANDARD "LVDS" -to QSFP28A_REFCLK_p +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28A_TX_p[0] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28A_TX_p[1] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28A_TX_p[2] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28A_TX_p[3] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28A_RX_p[0] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28A_RX_p[1] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28A_RX_p[2] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28A_RX_p[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28A_INTERRUPT_n +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28A_LP_MODE +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28A_MOD_PRS_n +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28A_MOD_SEL_n +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28A_RST_n +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28A_SCL +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28A_SDA +set_location_assignment PIN_T41 -to QSFP28A_REFCLK_p +set_location_assignment PIN_F49 -to QSFP28A_TX_p[0] +set_location_assignment PIN_G47 -to QSFP28A_TX_p[1] +set_location_assignment PIN_E47 -to QSFP28A_TX_p[2] +set_location_assignment PIN_C47 -to QSFP28A_TX_p[3] +set_location_assignment PIN_G43 -to QSFP28A_RX_p[0] +set_location_assignment PIN_D45 -to QSFP28A_RX_p[1] +set_location_assignment PIN_C43 -to QSFP28A_RX_p[2] +set_location_assignment PIN_A43 -to QSFP28A_RX_p[3] +set_location_assignment PIN_AB35 -to QSFP28A_INTERRUPT_n +set_location_assignment PIN_AB36 -to QSFP28A_LP_MODE +set_location_assignment PIN_AB34 -to QSFP28A_MOD_PRS_n +set_location_assignment PIN_AD35 -to QSFP28A_MOD_SEL_n +set_location_assignment PIN_AC33 -to QSFP28A_RST_n +set_location_assignment PIN_AC36 -to QSFP28A_SCL +set_location_assignment PIN_AC35 -to QSFP28A_SDA + +#============================================================ +# QSFP28B +#============================================================ +set_instance_assignment -name IO_STANDARD "LVDS" -to QSFP28B_REFCLK_p +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28B_TX_p[0] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28B_TX_p[1] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28B_TX_p[2] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28B_TX_p[3] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28B_RX_p[0] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28B_RX_p[1] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28B_RX_p[2] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28B_RX_p[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28B_INTERRUPT_n +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28B_LP_MODE +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28B_MOD_PRS_n +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28B_MOD_SEL_n +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28B_RST_n +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28B_SCL +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28B_SDA +set_location_assignment PIN_AM38 -to QSFP28B_REFCLK_p +set_location_assignment PIN_AK49 -to QSFP28B_TX_p[0] +set_location_assignment PIN_AL47 -to QSFP28B_TX_p[1] +set_location_assignment PIN_AJ47 -to QSFP28B_TX_p[2] +set_location_assignment PIN_AF49 -to QSFP28B_TX_p[3] +set_location_assignment PIN_AL43 -to QSFP28B_RX_p[0] +set_location_assignment PIN_AH45 -to QSFP28B_RX_p[1] +set_location_assignment PIN_AF45 -to QSFP28B_RX_p[2] +set_location_assignment PIN_AG43 -to QSFP28B_RX_p[3] +set_location_assignment PIN_AF17 -to QSFP28B_INTERRUPT_n +set_location_assignment PIN_AF34 -to QSFP28B_LP_MODE +set_location_assignment PIN_AH17 -to QSFP28B_MOD_PRS_n +set_location_assignment PIN_AJ33 -to QSFP28B_MOD_SEL_n +set_location_assignment PIN_AG34 -to QSFP28B_RST_n +set_location_assignment PIN_AH32 -to QSFP28B_SCL +set_location_assignment PIN_AE36 -to QSFP28B_SDA + +#============================================================ +# QSFP28C +#============================================================ +set_instance_assignment -name IO_STANDARD "LVDS" -to QSFP28C_REFCLK_p +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28C_TX_p[0] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28C_TX_p[1] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28C_TX_p[2] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28C_TX_p[3] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28C_RX_p[0] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28C_RX_p[1] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28C_RX_p[2] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28C_RX_p[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28C_INTERRUPT_n +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28C_LP_MODE +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28C_MOD_PRS_n +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28C_MOD_SEL_n +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28C_RST_n +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28C_SCL +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28C_SDA +set_location_assignment PIN_AM12 -to QSFP28C_REFCLK_p +set_location_assignment PIN_AK1 -to QSFP28C_TX_p[0] +set_location_assignment PIN_AL3 -to QSFP28C_TX_p[1] +set_location_assignment PIN_AJ3 -to QSFP28C_TX_p[2] +set_location_assignment PIN_AF1 -to QSFP28C_TX_p[3] +set_location_assignment PIN_AL7 -to QSFP28C_RX_p[0] +set_location_assignment PIN_AH5 -to QSFP28C_RX_p[1] +set_location_assignment PIN_AF5 -to QSFP28C_RX_p[2] +set_location_assignment PIN_AG7 -to QSFP28C_RX_p[3] +set_location_assignment PIN_AF16 -to QSFP28C_INTERRUPT_n +set_location_assignment PIN_AE16 -to QSFP28C_LP_MODE +set_location_assignment PIN_AH16 -to QSFP28C_MOD_PRS_n +set_location_assignment PIN_AE14 -to QSFP28C_MOD_SEL_n +set_location_assignment PIN_AD15 -to QSFP28C_RST_n +set_location_assignment PIN_AD16 -to QSFP28C_SCL +set_location_assignment PIN_AF15 -to QSFP28C_SDA + +#============================================================ +# QSFP28D +#============================================================ +set_instance_assignment -name IO_STANDARD "LVDS" -to QSFP28D_REFCLK_p +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28D_TX_p[0] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28D_TX_p[1] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28D_TX_p[2] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28D_TX_p[3] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28D_RX_p[0] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28D_RX_p[1] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28D_RX_p[2] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP28D_RX_p[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28D_INTERRUPT_n +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28D_LP_MODE +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28D_MOD_PRS_n +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28D_MOD_SEL_n +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28D_RST_n +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28D_SCL +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to QSFP28D_SDA +set_location_assignment PIN_T9 -to QSFP28D_REFCLK_p +set_location_assignment PIN_F1 -to QSFP28D_TX_p[0] +set_location_assignment PIN_G3 -to QSFP28D_TX_p[1] +set_location_assignment PIN_E3 -to QSFP28D_TX_p[2] +set_location_assignment PIN_C3 -to QSFP28D_TX_p[3] +set_location_assignment PIN_G7 -to QSFP28D_RX_p[0] +set_location_assignment PIN_D5 -to QSFP28D_RX_p[1] +set_location_assignment PIN_C7 -to QSFP28D_RX_p[2] +set_location_assignment PIN_A7 -to QSFP28D_RX_p[3] +set_location_assignment PIN_AD14 -to QSFP28D_INTERRUPT_n +set_location_assignment PIN_AB15 -to QSFP28D_LP_MODE +set_location_assignment PIN_AC15 -to QSFP28D_MOD_PRS_n +set_location_assignment PIN_AB12 -to QSFP28D_MOD_SEL_n +set_location_assignment PIN_AB13 -to QSFP28D_RST_n +set_location_assignment PIN_AB14 -to QSFP28D_SCL +set_location_assignment PIN_AC14 -to QSFP28D_SDA + +#============================================================ +# EXP +#============================================================ +set_instance_assignment -name IO_STANDARD "1.8 V" -to EXP_EN +set_location_assignment PIN_BG25 -to EXP_EN + +#============================================================ +# M5S10 +#============================================================ +set_instance_assignment -name IO_STANDARD "1.2 V" -to M5S10_R[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to M5S10_R[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to M5S10_R[2] +set_instance_assignment -name IO_STANDARD "1.2 V" -to M5S10_R[3] +set_location_assignment PIN_B17 -to M5S10_R[0] +set_location_assignment PIN_E21 -to M5S10_R[1] +set_location_assignment PIN_R16 -to M5S10_R[2] +set_location_assignment PIN_N17 -to M5S10_R[3] + +#============================================================ +# UFL +#============================================================ +set_instance_assignment -name IO_STANDARD "1.8 V" -to UFL_CLKIN_p +set_instance_assignment -name IO_STANDARD "1.8 V" -to UFL_CLKIN_n +set_location_assignment PIN_AN27 -to UFL_CLKIN_p +set_location_assignment PIN_AN28 -to UFL_CLKIN_n + +#============================================================ +# HPS +#============================================================ +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_SD_CLK +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_SD_CMD +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_SD_DATA[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_SD_DATA[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_SD_DATA[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_SD_DATA[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_OSC_CLK +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB0_CLK +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB0_STP +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB0_DIR +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB0_NXT +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB0_DATA[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB0_DATA[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB0_DATA[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB0_DATA[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB0_DATA[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB0_DATA[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB0_DATA[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB0_DATA[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_EMAC0_TX_CLK +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_EMAC0_TX_CTL +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_EMAC0_RX_CLK +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_EMAC0_RX_CTL +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_EMAC0_RXD[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_EMAC0_TXD[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_EMAC0_RXD[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_EMAC0_TXD[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_EMAC0_RXD[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_EMAC0_TXD[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_EMAC0_RXD[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_EMAC0_TXD[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_LED +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_KEY +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_UART0_TX +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_UART0_RX +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_FPGA_UART1_TX +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_FPGA_UART1_RX +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_JTAG_TCK +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_JTAG_TMS +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_JTAG_TDO +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_JTAG_TDI +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_CARD_PRSNT_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_EMAC0_MDIO +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_EMAC0_MDC +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_SD_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_SD_CMD +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_SD_DATA[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_SD_DATA[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_SD_DATA[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_SD_DATA[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_USB0_STP +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_USB0_DATA[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_USB0_DATA[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_USB0_DATA[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_USB0_DATA[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_USB0_DATA[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_USB0_DATA[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_USB0_DATA[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_USB0_DATA[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to HPS_EMAC0_TX_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_EMAC0_TX_CTL +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_EMAC0_TXD[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_EMAC0_TXD[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_EMAC0_TXD[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_EMAC0_TXD[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HPS_LED +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to HPS_KEY +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to HPS_UART0_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to HPS_FPGA_UART1_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to HPS_JTAG_TDO +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to HPS_CARD_PRSNT_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to HPS_EMAC0_MDIO +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to HPS_EMAC0_MDC +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_SD_CMD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_SD_DATA[0] -entity ghrd_s10_top +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_SD_DATA[1] -entity ghrd_s10_top +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_SD_DATA[2] -entity ghrd_s10_top +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_SD_DATA[3] -entity ghrd_s10_top +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_USB0_CLK +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_USB0_DIR +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_USB0_NXT +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_USB0_DATA[0] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_USB0_DATA[1] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_USB0_DATA[2] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_USB0_DATA[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_USB0_DATA[4] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_USB0_DATA[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_USB0_DATA[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_USB0_DATA[7] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_EMAC0_RX_CLK +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_EMAC0_RX_CTL +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_EMAC0_RXD[0] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_EMAC0_RXD[1] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_EMAC0_RXD[2] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_EMAC0_RXD[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_UART0_RX +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_LED +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_KEY +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_JTAG_TCK +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_JTAG_TMS +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_JTAG_TDI +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_CARD_PRSNT_n +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HPS_EMAC0_MDIO +set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to HPS_EMAC0_MDIO + + +#============================================================ +# VID Assignments +#============================================================ +set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 +set_global_assignment -name USE_PWRMGT_SDA SDM_IO12 +set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" +set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ" +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 4F +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00 +set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "AUTO DISCOVERY" +set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 + +#============================================================ +# Configuration scheme/pin +#============================================================ +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X8" +set_global_assignment -name USE_CONF_DONE SDM_IO16 + +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ + +# for HPS +#set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4" +#set_global_assignment -name INI_VARS "ASM_ENABLE_ADVANCED_DEVICES=ON; hps_dump_handoff_data=on" +#set_global_assignment -name USE_HPS_COLD_RESET SDM_IO15 +#set_global_assignment -name HPS_INITIALIZATION "AFTER INIT_DONE" +#set_global_assignment -name HPS_DAP_SPLIT_MODE "SDM PINS" + +#============================================================ +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name GENERATE_PR_RBF_FILE ON +set_global_assignment -name ENABLE_ED_CRC_CHECK ON +set_global_assignment -name MINIMUM_SEU_INTERVAL 0 +set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name IP_FILE reset_release.ip +set_global_assignment -name MIF_FILE boot.mif +set_global_assignment -name MIF_FILE ScalarCapRegFileInit.mif +set_global_assignment -name MIF_FILE SIMTCapRegFileInit.mif +set_global_assignment -name QSYS_FILE DE10_Pro_QSYS.qsys +set_global_assignment -name SDC_FILE DE10_Pro.sdc +set_global_assignment -name IP_FILE ip/DE10_Pro_QSYS/DE10_Pro_QSYS_iopll_0.ip +set_global_assignment -name IP_FILE ip/DE10_Pro_QSYS/DE10_Pro_QSYS_mm_clock_crossing_bridge_50m.ip +set_global_assignment -name IP_FILE ip/DE10_Pro_QSYS/DE10_Pro_QSYS_pio_0.ip +set_global_assignment -name IP_FILE ip/DE10_Pro_QSYS/DE10_Pro_QSYS_reset_in.ip +set_global_assignment -name IP_FILE ip/DE10_Pro_QSYS/DE10_Pro_QSYS_ddr4_local_reset_req.ip +set_global_assignment -name IP_FILE ip/DE10_Pro_QSYS/DE10_Pro_QSYS_emif_s10_ddr4_b.ip +set_global_assignment -name IP_FILE ip/DE10_Pro_QSYS/DE10_Pro_QSYS_clock_in.ip +set_global_assignment -name IP_FILE ip/DE10_Pro_QSYS/DE10_Pro_QSYS_jtag_uart_0.ip +set_global_assignment -name IP_FILE ip/DE10_Pro_QSYS/DE10_Pro_QSYS_SIMTight_0.ip +set_global_assignment -name IP_FILE ip/DE10_Pro_QSYS/DE10_Pro_QSYS_mm_clockcross_DDR4.ip +set_global_assignment -name SEARCH_PATH ../src +set_global_assignment -name SEARCH_PATH ../pebbles/blarney/Verilog/Altera/ +set_global_assignment -name SEARCH_PATH ../pebbles/src/CHERI/Verilog/ +set_global_assignment -name SEED 2 +set_global_assignment -name IP_FILE ../pebbles/blarney/blarney-vendor-ip/IntelFPGA/AvalonStreamClockCrosser/AvalonStreamClockCrosser.ip +set_global_assignment -name VERILOG_FILE ../pebbles/blarney/blarney-vendor-ip/IntelFPGA/PipelinedDivider/PipelinedDivider.v diff --git a/de10-pro-e/DE10_Pro.sdc b/de10-pro-e/DE10_Pro.sdc new file mode 100644 index 0000000..f9294d1 --- /dev/null +++ b/de10-pro-e/DE10_Pro.sdc @@ -0,0 +1,101 @@ +#************************************************************** +# This .sdc file is created by Terasic Tool. +# Users are recommended to modify this file to match users logic. +#************************************************************** + +#************************************************************** +# Create Clock +#************************************************************** +# CLOCK +create_clock -period 10 [get_ports CLK_100_B3I] +create_clock -period 20 [get_ports CLK_50_B2C] +create_clock -period 20 [get_ports CLK_50_B2L] +create_clock -period 20 [get_ports CLK_50_B3C] +create_clock -period 20 [get_ports CLK_50_B3I] +create_clock -period 20 [get_ports CLK_50_B3L] + +create_clock -period "266.666666 MHz" [get_ports DDR4A_REFCLK_p] +create_clock -period "166.666666 MHz" [get_ports DDR4B_REFCLK_p] +create_clock -period "166.666666 MHz" [get_ports DDR4C_REFCLK_p] +create_clock -period "166.666666 MHz" [get_ports DDR4D_REFCLK_p] + +#************************************************************** +# Create Generated Clock +#************************************************************** +derive_pll_clocks + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** +derive_clock_uncertainty + + +#************************************************************** +# Set Input Delay +#************************************************************** + + + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** +set_clock_groups -asynchronous -group {[get_clocks { CLK_50_B3I }]} +set_clock_groups -asynchronous -group {[get_clocks { DDR4A_REFCLK_p }]} +set_clock_groups -asynchronous -group {[get_clocks { DDR4B_REFCLK_p }]} +set_clock_groups -asynchronous -group {[get_clocks { DDR4C_REFCLK_p }]} +set_clock_groups -asynchronous -group {[get_clocks { DDR4D_REFCLK_p }]} + + + +#************************************************************** +# Set False Path +#************************************************************** +set_false_path -from * -to [get_cells {DE10_Pro_QSYS_inst|ddr4_status|pio_0|readdata*} ] +set_false_path -from [get_ports CPU_RESET_n*] -to * +set_false_path -from [get_ports BUTTON*] -to * + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + + + +#************************************************************** +# Set Load +#************************************************************** + + + diff --git a/de10-pro-e/DE10_Pro.v b/de10-pro-e/DE10_Pro.v new file mode 100644 index 0000000..6df78fb --- /dev/null +++ b/de10-pro-e/DE10_Pro.v @@ -0,0 +1,117 @@ +module DE10_Pro( + input CLK_100_B3I, + input CLK_50_B2C, + input CLK_50_B2L, + input CLK_50_B3C, + input CLK_50_B3I, + input CLK_50_B3L, + + input CPU_RESET_n, + input [1:0] BUTTON, + input [1:0] SW, + output [3:0] LED, + + inout SI5340A0_I2C_SCL, + inout SI5340A0_I2C_SDA, + input SI5340A0_INTR, + output SI5340A0_OE_n, + output SI5340A0_RST_n, + + inout SI5340A1_I2C_SCL, + inout SI5340A1_I2C_SDA, + input SI5340A1_INTR, + output SI5340A1_OE_n, + output SI5340A1_RST_n, + + output FLASH_CLK, + output [27:1] FLASH_A, + inout [15:0] FLASH_D, + output FLASH_CE_n, + output FLASH_WE_n, + output FLASH_OE_n, + output FLASH_ADV_n, + output FLASH_RESET_n, + input FLASH_RDY_BSY_n, + + input DDR4B_REFCLK_p, + output [16:0] DDR4B_A, + output [1:0] DDR4B_BA, + output [1:0] DDR4B_BG, + output DDR4B_CK, + output DDR4B_CK_n, + output DDR4B_CKE, + inout [8:0] DDR4B_DQS, + inout [8:0] DDR4B_DQS_n, + inout [71:0] DDR4B_DQ, + inout [8:0] DDR4B_DBI_n, + output DDR4B_CS_n, + output DDR4B_RESET_n, + output DDR4B_ODT, + output DDR4B_PAR, + input DDR4B_ALERT_n, + output DDR4B_ACT_n, + input DDR4B_EVENT_n, + inout DDR4B_SCL, + inout DDR4B_SDA, + input DDR4B_RZQ, + + input EXP_EN, + + inout UFL_CLKIN_p, + inout UFL_CLKIN_n +); + +wire reset_n; +wire ddr4_local_reset_req; + +wire ddr4_b_local_reset_done; +wire ddr4_b_status_local_cal_fail; +wire ddr4_b_status_local_cal_success; + +wire [11:0] ddr4_status; + +// Reset release +wire ninit_done; +reset_release reset_release ( + .ninit_done(ninit_done) + ); + +assign reset_n = !ninit_done && CPU_RESET_n; +assign ddr4_status = + {ddr4_b_status_local_cal_fail, + ddr4_b_status_local_cal_success, + ddr4_b_local_reset_done}; + +DE10_Pro_QSYS DE10_Pro_QSYS_inst ( + .clk_clk(CLK_50_B3I), + .reset_reset(~reset_n), + .emif_s10_ddr4_b_mem_mem_ck(DDR4B_CK), + .emif_s10_ddr4_b_mem_mem_ck_n(DDR4B_CK_n), + .emif_s10_ddr4_b_mem_mem_a(DDR4B_A), + .emif_s10_ddr4_b_mem_mem_act_n(DDR4B_ACT_n), + .emif_s10_ddr4_b_mem_mem_ba(DDR4B_BA), + .emif_s10_ddr4_b_mem_mem_bg(DDR4B_BG), + .emif_s10_ddr4_b_mem_mem_cke(DDR4B_CKE), + .emif_s10_ddr4_b_mem_mem_cs_n(DDR4B_CS_n), + .emif_s10_ddr4_b_mem_mem_odt(DDR4B_ODT), + .emif_s10_ddr4_b_mem_mem_reset_n(DDR4B_RESET_n), + .emif_s10_ddr4_b_mem_mem_par(DDR4B_PAR), + .emif_s10_ddr4_b_mem_mem_alert_n(DDR4B_ALERT_n), + .emif_s10_ddr4_b_mem_mem_dqs(DDR4B_DQS), + .emif_s10_ddr4_b_mem_mem_dqs_n(DDR4B_DQS_n), + .emif_s10_ddr4_b_mem_mem_dq(DDR4B_DQ), + .emif_s10_ddr4_b_mem_mem_dbi_n(DDR4B_DBI_n), + .emif_s10_ddr4_b_oct_oct_rzqin(DDR4B_RZQ), + .emif_s10_ddr4_b_pll_ref_clk_clk(DDR4B_REFCLK_p), + .emif_s10_ddr4_b_status_local_cal_success(ddr4_b_status_local_cal_success), + .emif_s10_ddr4_b_status_local_cal_fail(ddr4_b_status_local_cal_fail), + .iopll_0_locked_export() + ); + +assign SI5340A0_RST_n = 1'b1; +assign SI5340A1_RST_n = 1'b1; + +assign SI5340A0_OE_n = 1'b0; +assign SI5340A1_OE_n = 1'b0; + +endmodule diff --git a/de10-pro-e/DE10_Pro_QSYS.qsys b/de10-pro-e/DE10_Pro_QSYS.qsys new file mode 100644 index 0000000..e344508 --- /dev/null +++ b/de10-pro-e/DE10_Pro_QSYS.qsys @@ -0,0 +1,11015 @@ + + + + Altera Corporation + DE10_Pro_QSYS + DE10_Pro_QSYS + 1.0 + + + + $${FILENAME} + $${FILENAME} + 1.0 + + + System + QsysPro + + + + + bonusData + bonusData + bonusData +{ + element SIMTight_0 + { + datum _sortIndex + { + value = "3"; + type = "int"; + } + } + element clock_in + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } + element ddr4_local_reset_req + { + datum _sortIndex + { + value = "9"; + type = "int"; + } + } + element ddr4_local_reset_req.s1 + { + datum baseAddress + { + value = "64"; + type = "String"; + } + } + element ddr4_status + { + datum _sortIndex + { + value = "8"; + type = "int"; + } + } + element ddr4_status.s1 + { + datum baseAddress + { + value = "48"; + type = "String"; + } + } + element emif_s10_ddr4_b + { + datum _sortIndex + { + value = "7"; + type = "int"; + } + } + element emif_s10_ddr4_b.ctrl_amm_0 + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "0"; + type = "String"; + } + } + element iopll_0 + { + datum _sortIndex + { + value = "2"; + type = "int"; + } + } + element jtag_uart_0 + { + datum _sortIndex + { + value = "5"; + type = "int"; + } + } + element jtag_uart_0.avalon_jtag_slave + { + datum baseAddress + { + value = "0"; + type = "String"; + } + } + element mm_clockcross_50Mhz + { + datum _sortIndex + { + value = "4"; + type = "int"; + } + } + element mm_clockcross_50Mhz.s0 + { + datum baseAddress + { + value = "0"; + type = "String"; + } + } + element mm_clockcross_DDR4 + { + datum _sortIndex + { + value = "6"; + type = "int"; + } + } + element reset_in + { + datum _sortIndex + { + value = "1"; + type = "int"; + } + } +} + + + + designId + designId + + + + device + Device + 1SX280HU2F50E1VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 1 + + + fabricMode + fabricMode + QSYS + + + generateLegacySim + generateLegacySim + false + + + generationId + Generation Id + 0 + + + globalResetBus + Global reset + false + + + hdlLanguage + hdlLanguage + VERILOG + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + + + + sopcBorderPoints + Use SOPC Builder port naming + false + + + systemHash + systemHash + 0 + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + systemScripts + systemScripts + + + + testBenchDutName + Use Test Bench Naming Pattern + + + + timeStamp + timeStamp + 0 + + + useTestBenchNamingPattern + Use Test Bench Naming Pattern + false + + + + + + + + + Altera Corporation + SIMTight_0 + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>dram_master</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>in0_socDRAMIns_avl_dram_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>in0_socDRAMIns_avl_dram_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>in0_socDRAMIns_avl_dram_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socDRAMOuts_avl_dram_address</name> + <role>address</role> + <direction>Output</direction> + <width>28</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socDRAMOuts_avl_dram_burstcount</name> + <role>burstcount</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socDRAMOuts_avl_dram_byteen</name> + <role>byteenable</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socDRAMOuts_avl_dram_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socDRAMOuts_avl_dram_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socDRAMOuts_avl_dram_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>simt_clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>simt_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>uart_master</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>in0_socUARTIns_avl_jtaguart_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>in0_socUARTIns_avl_jtaguart_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socUARTOuts_avl_jtaguart_address</name> + <role>address</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socUARTOuts_avl_jtaguart_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socUARTOuts_avl_jtaguart_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socUARTOuts_avl_jtaguart_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>cpu_clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>cpu_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>simt_clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in0_socSIMTClk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>cpu_clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in0_socCPUClk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>simt_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in0_socSIMTRst</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>simt_clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>cpu_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in0_socCPURst</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>cpu_clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>SIMTight</className> + <version>1.0</version> + <displayName>SIMTight</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>dram_master</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>in0_socDRAMIns_avl_dram_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>in0_socDRAMIns_avl_dram_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>in0_socDRAMIns_avl_dram_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socDRAMOuts_avl_dram_address</name> + <role>address</role> + <direction>Output</direction> + <width>28</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socDRAMOuts_avl_dram_burstcount</name> + <role>burstcount</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socDRAMOuts_avl_dram_byteen</name> + <role>byteenable</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socDRAMOuts_avl_dram_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socDRAMOuts_avl_dram_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socDRAMOuts_avl_dram_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>simt_clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>simt_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>uart_master</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>in0_socUARTIns_avl_jtaguart_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>in0_socUARTIns_avl_jtaguart_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socUARTOuts_avl_jtaguart_address</name> + <role>address</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socUARTOuts_avl_jtaguart_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socUARTOuts_avl_jtaguart_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socUARTOuts_avl_jtaguart_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>cpu_clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>cpu_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>simt_clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in0_socSIMTClk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>cpu_clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in0_socCPUClk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>simt_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in0_socSIMTRst</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>simt_clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>cpu_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in0_socCPURst</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>cpu_clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>DE10_Pro_QSYS_SIMTight_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>DE10_Pro_QSYS_SIMTight_0</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_SIMTight_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>DE10_Pro_QSYS_SIMTight_0</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_SIMTight_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>DE10_Pro_QSYS_SIMTight_0</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_SIMTight_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/DE10_Pro_QSYS/DE10_Pro_QSYS_SIMTight_0.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + clock_in + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>in_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>in_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>50000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_clock_bridge</className> + <version>19.2.0</version> + <displayName>Clock Bridge Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>DERIVED_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>in_clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>in_clk</key> + <value> + <connectionPointName>in_clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>out_clk</key> + <value> + <connectionPointName>out_clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>50000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>in_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>in_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>50000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>DE10_Pro_QSYS_clock_in</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>DE10_Pro_QSYS_clock_in</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_clock_in</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>DE10_Pro_QSYS_clock_in</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_clock_in</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>DE10_Pro_QSYS_clock_in</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_clock_in</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/DE10_Pro_QSYS/DE10_Pro_QSYS_clock_in.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + ddr4_local_reset_req + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>external_connection</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>out_port</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s1</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>address</name> + <role>address</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>write_n</name> + <role>write_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>chipselect</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>4</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt; +&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt; + &lt;peripherals&gt; + &lt;peripheral&gt; + &lt;name&gt;altera_avalon_pio&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt; + &lt;addressBlock&gt; + &lt;offset&gt;0x0&lt;/offset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;usage&gt;registers&lt;/usage&gt; + &lt;/addressBlock&gt; + &lt;registers&gt; + &lt;register&gt; + &lt;name&gt;DATA&lt;/name&gt; + &lt;displayName&gt;Data&lt;/displayName&gt; + &lt;description&gt;Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).&lt;/description&gt; + &lt;addressOffset&gt;0x0&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;data&lt;/name&gt; + &lt;description&gt;Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;DIRECTION&lt;/name&gt; + &lt;displayName&gt;Direction&lt;/displayName&gt; + &lt;description&gt;The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.&lt;/description&gt; + &lt;addressOffset&gt;0x4&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;direction&lt;/name&gt; + &lt;description&gt;Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;IRQ_MASK&lt;/name&gt; + &lt;displayName&gt;Interrupt mask&lt;/displayName&gt; + &lt;description&gt;Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.&lt;/description&gt; + &lt;addressOffset&gt;0x8&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;interruptmask&lt;/name&gt; + &lt;description&gt;IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;EDGE_CAP&lt;/name&gt; + &lt;displayName&gt;Edge capture&lt;/displayName&gt; + &lt;description&gt;Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.&lt;/description&gt; + &lt;addressOffset&gt;0xc&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;edgecapture&lt;/name&gt; + &lt;description&gt;Edge detection for each input port.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;SET_BIT&lt;/name&gt; + &lt;displayName&gt;Outset&lt;/displayName&gt; + &lt;description&gt;You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt; + &lt;addressOffset&gt;0x10&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;write-only&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;outset&lt;/name&gt; + &lt;description&gt;Specifies which bit of the output port to set.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;write-only&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;CLEAR_BITS&lt;/name&gt; + &lt;displayName&gt;Outclear&lt;/displayName&gt; + &lt;description&gt;You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt; + &lt;addressOffset&gt;0x14&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;write-only&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;outclear&lt;/name&gt; + &lt;description&gt;Specifies which output bit to clear.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;write-only&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;/registers&gt; + &lt;/peripheral&gt; + &lt;/peripherals&gt; +&lt;/device&gt; </cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars/> + </cmsisInfo> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_avalon_pio</className> + <version>19.1</version> + <displayName>PIO (Parallel I/O) Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>clockRate</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>50000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>s1</key> + <value> + <connectionPointName>s1</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='s1' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>4</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>external_connection</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>out_port</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s1</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>address</name> + <role>address</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>write_n</name> + <role>write_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>chipselect</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>4</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt; +&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt; + &lt;peripherals&gt; + &lt;peripheral&gt; + &lt;name&gt;altera_avalon_pio&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt; + &lt;addressBlock&gt; + &lt;offset&gt;0x0&lt;/offset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;usage&gt;registers&lt;/usage&gt; + &lt;/addressBlock&gt; + &lt;registers&gt; + &lt;register&gt; + &lt;name&gt;DATA&lt;/name&gt; + &lt;displayName&gt;Data&lt;/displayName&gt; + &lt;description&gt;Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).&lt;/description&gt; + &lt;addressOffset&gt;0x0&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;data&lt;/name&gt; + &lt;description&gt;Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;DIRECTION&lt;/name&gt; + &lt;displayName&gt;Direction&lt;/displayName&gt; + &lt;description&gt;The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.&lt;/description&gt; + &lt;addressOffset&gt;0x4&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;direction&lt;/name&gt; + &lt;description&gt;Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;IRQ_MASK&lt;/name&gt; + &lt;displayName&gt;Interrupt mask&lt;/displayName&gt; + &lt;description&gt;Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.&lt;/description&gt; + &lt;addressOffset&gt;0x8&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;interruptmask&lt;/name&gt; + &lt;description&gt;IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;EDGE_CAP&lt;/name&gt; + &lt;displayName&gt;Edge capture&lt;/displayName&gt; + &lt;description&gt;Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.&lt;/description&gt; + &lt;addressOffset&gt;0xc&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;edgecapture&lt;/name&gt; + &lt;description&gt;Edge detection for each input port.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;SET_BIT&lt;/name&gt; + &lt;displayName&gt;Outset&lt;/displayName&gt; + &lt;description&gt;You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt; + &lt;addressOffset&gt;0x10&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;write-only&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;outset&lt;/name&gt; + &lt;description&gt;Specifies which bit of the output port to set.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;write-only&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;CLEAR_BITS&lt;/name&gt; + &lt;displayName&gt;Outclear&lt;/displayName&gt; + &lt;description&gt;You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt; + &lt;addressOffset&gt;0x14&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;write-only&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;outclear&lt;/name&gt; + &lt;description&gt;Specifies which output bit to clear.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;write-only&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;/registers&gt; + &lt;/peripheral&gt; + &lt;/peripherals&gt; +&lt;/device&gt; </cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars/> + </cmsisInfo> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>DE10_Pro_QSYS_ddr4_local_reset_req</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>DE10_Pro_QSYS_ddr4_local_reset_req</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_ddr4_local_reset_req</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>DE10_Pro_QSYS_ddr4_local_reset_req</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_ddr4_local_reset_req</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>DE10_Pro_QSYS_ddr4_local_reset_req</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_ddr4_local_reset_req</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/DE10_Pro_QSYS/DE10_Pro_QSYS_ddr4_local_reset_req.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap> + <entry> + <key>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.CAPTURE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DATA_WIDTH</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DRIVEN_SIM_VALUE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.EDGE_TYPE</key> + <value>NONE</value> + </entry> + <entry> + <key>embeddedsw.CMacro.FREQ</key> + <value>50000000</value> + </entry> + <entry> + <key>embeddedsw.CMacro.HAS_IN</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.HAS_OUT</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.HAS_TRI</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.IRQ_TYPE</key> + <value>NONE</value> + </entry> + <entry> + <key>embeddedsw.CMacro.RESET_VALUE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.dts.compatible</key> + <value>altr,pio-1.0</value> + </entry> + <entry> + <key>embeddedsw.dts.group</key> + <value>gpio</value> + </entry> + <entry> + <key>embeddedsw.dts.name</key> + <value>pio</value> + </entry> + <entry> + <key>embeddedsw.dts.params.altr,gpio-bank-width</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.dts.params.resetvalue</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.dts.vendor</key> + <value>altr</value> + </entry> + </assignmentValueMap> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + ddr4_status + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>external_connection</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_port</name> + <role>export</role> + <direction>Input</direction> + <width>12</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s1</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>address</name> + <role>address</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>4</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt; +&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt; + &lt;peripherals&gt; + &lt;peripheral&gt; + &lt;name&gt;altera_avalon_pio&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt; + &lt;addressBlock&gt; + &lt;offset&gt;0x0&lt;/offset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;usage&gt;registers&lt;/usage&gt; + &lt;/addressBlock&gt; + &lt;registers&gt; + &lt;register&gt; + &lt;name&gt;DATA&lt;/name&gt; + &lt;displayName&gt;Data&lt;/displayName&gt; + &lt;description&gt;Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).&lt;/description&gt; + &lt;addressOffset&gt;0x0&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;data&lt;/name&gt; + &lt;description&gt;Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;DIRECTION&lt;/name&gt; + &lt;displayName&gt;Direction&lt;/displayName&gt; + &lt;description&gt;The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.&lt;/description&gt; + &lt;addressOffset&gt;0x4&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;direction&lt;/name&gt; + &lt;description&gt;Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;IRQ_MASK&lt;/name&gt; + &lt;displayName&gt;Interrupt mask&lt;/displayName&gt; + &lt;description&gt;Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.&lt;/description&gt; + &lt;addressOffset&gt;0x8&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;interruptmask&lt;/name&gt; + &lt;description&gt;IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;EDGE_CAP&lt;/name&gt; + &lt;displayName&gt;Edge capture&lt;/displayName&gt; + &lt;description&gt;Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.&lt;/description&gt; + &lt;addressOffset&gt;0xc&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;edgecapture&lt;/name&gt; + &lt;description&gt;Edge detection for each input port.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;SET_BIT&lt;/name&gt; + &lt;displayName&gt;Outset&lt;/displayName&gt; + &lt;description&gt;You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt; + &lt;addressOffset&gt;0x10&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;write-only&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;outset&lt;/name&gt; + &lt;description&gt;Specifies which bit of the output port to set.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;write-only&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;CLEAR_BITS&lt;/name&gt; + &lt;displayName&gt;Outclear&lt;/displayName&gt; + &lt;description&gt;You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt; + &lt;addressOffset&gt;0x14&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;write-only&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;outclear&lt;/name&gt; + &lt;description&gt;Specifies which output bit to clear.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;write-only&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;/registers&gt; + &lt;/peripheral&gt; + &lt;/peripherals&gt; +&lt;/device&gt; </cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars/> + </cmsisInfo> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_avalon_pio</className> + <version>19.1</version> + <displayName>PIO (Parallel I/O) Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>clockRate</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>50000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>s1</key> + <value> + <connectionPointName>s1</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='s1' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>4</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>external_connection</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_port</name> + <role>export</role> + <direction>Input</direction> + <width>12</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s1</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>address</name> + <role>address</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>4</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt; +&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt; + &lt;peripherals&gt; + &lt;peripheral&gt; + &lt;name&gt;altera_avalon_pio&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt; + &lt;addressBlock&gt; + &lt;offset&gt;0x0&lt;/offset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;usage&gt;registers&lt;/usage&gt; + &lt;/addressBlock&gt; + &lt;registers&gt; + &lt;register&gt; + &lt;name&gt;DATA&lt;/name&gt; + &lt;displayName&gt;Data&lt;/displayName&gt; + &lt;description&gt;Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).&lt;/description&gt; + &lt;addressOffset&gt;0x0&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;data&lt;/name&gt; + &lt;description&gt;Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;DIRECTION&lt;/name&gt; + &lt;displayName&gt;Direction&lt;/displayName&gt; + &lt;description&gt;The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.&lt;/description&gt; + &lt;addressOffset&gt;0x4&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;direction&lt;/name&gt; + &lt;description&gt;Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;IRQ_MASK&lt;/name&gt; + &lt;displayName&gt;Interrupt mask&lt;/displayName&gt; + &lt;description&gt;Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.&lt;/description&gt; + &lt;addressOffset&gt;0x8&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;interruptmask&lt;/name&gt; + &lt;description&gt;IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;EDGE_CAP&lt;/name&gt; + &lt;displayName&gt;Edge capture&lt;/displayName&gt; + &lt;description&gt;Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.&lt;/description&gt; + &lt;addressOffset&gt;0xc&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;edgecapture&lt;/name&gt; + &lt;description&gt;Edge detection for each input port.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;SET_BIT&lt;/name&gt; + &lt;displayName&gt;Outset&lt;/displayName&gt; + &lt;description&gt;You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt; + &lt;addressOffset&gt;0x10&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;write-only&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;outset&lt;/name&gt; + &lt;description&gt;Specifies which bit of the output port to set.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;write-only&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;CLEAR_BITS&lt;/name&gt; + &lt;displayName&gt;Outclear&lt;/displayName&gt; + &lt;description&gt;You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt; + &lt;addressOffset&gt;0x14&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;write-only&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;outclear&lt;/name&gt; + &lt;description&gt;Specifies which output bit to clear.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;32&lt;/bitWidth&gt; + &lt;access&gt;write-only&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;/registers&gt; + &lt;/peripheral&gt; + &lt;/peripherals&gt; +&lt;/device&gt; </cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars/> + </cmsisInfo> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>DE10_Pro_QSYS_pio_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>DE10_Pro_QSYS_pio_0</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_pio_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>DE10_Pro_QSYS_pio_0</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_pio_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>DE10_Pro_QSYS_pio_0</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_pio_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/DE10_Pro_QSYS/DE10_Pro_QSYS_pio_0.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap> + <entry> + <key>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.CAPTURE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DATA_WIDTH</key> + <value>12</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DRIVEN_SIM_VALUE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.EDGE_TYPE</key> + <value>NONE</value> + </entry> + <entry> + <key>embeddedsw.CMacro.FREQ</key> + <value>50000000</value> + </entry> + <entry> + <key>embeddedsw.CMacro.HAS_IN</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.HAS_OUT</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.HAS_TRI</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.IRQ_TYPE</key> + <value>NONE</value> + </entry> + <entry> + <key>embeddedsw.CMacro.RESET_VALUE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.dts.compatible</key> + <value>altr,pio-1.0</value> + </entry> + <entry> + <key>embeddedsw.dts.group</key> + <value>gpio</value> + </entry> + <entry> + <key>embeddedsw.dts.name</key> + <value>pio</value> + </entry> + <entry> + <key>embeddedsw.dts.params.altr,gpio-bank-width</key> + <value>12</value> + </entry> + <entry> + <key>embeddedsw.dts.params.resetvalue</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.dts.vendor</key> + <value>altr</value> + </entry> + </assignmentValueMap> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + emif_s10_ddr4_b + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>local_reset_req</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>local_reset_req</name> + <role>local_reset_req</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>local_reset_status</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>local_reset_done</name> + <role>local_reset_done</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>pll_ref_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>pll_ref_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>oct</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>oct_rzqin</name> + <role>oct_rzqin</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>mem_ck</name> + <role>mem_ck</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_ck_n</name> + <role>mem_ck_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_a</name> + <role>mem_a</role> + <direction>Output</direction> + <width>17</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_act_n</name> + <role>mem_act_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_ba</name> + <role>mem_ba</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_bg</name> + <role>mem_bg</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_cke</name> + <role>mem_cke</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_cs_n</name> + <role>mem_cs_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_odt</name> + <role>mem_odt</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_reset_n</name> + <role>mem_reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_par</name> + <role>mem_par</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_alert_n</name> + <role>mem_alert_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_dqs</name> + <role>mem_dqs</role> + <direction>Bidir</direction> + <width>9</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_dqs_n</name> + <role>mem_dqs_n</role> + <direction>Bidir</direction> + <width>9</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_dq</name> + <role>mem_dq</role> + <direction>Bidir</direction> + <width>72</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_dbi_n</name> + <role>mem_dbi_n</role> + <direction>Bidir</direction> + <width>9</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>status</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>local_cal_success</name> + <role>local_cal_success</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>local_cal_fail</name> + <role>local_cal_fail</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>emif_usr_reset_n</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>emif_usr_reset_n</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>none</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>emif_usr_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>emif_usr_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + </entry> + <entry> + <key>clockRate</key> + <value>333333333</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ctrl_ecc_user_interrupt_0</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>ctrl_ecc_user_interrupt_0</name> + <role>ctrl_ecc_user_interrupt</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ctrl_amm_0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>amm_ready_0</name> + <role>waitrequest_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_read_0</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_write_0</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_address_0</name> + <role>address</role> + <direction>Input</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_readdata_0</name> + <role>readdata</role> + <direction>Output</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_writedata_0</name> + <role>writedata</role> + <direction>Input</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_burstcount_0</name> + <role>burstcount</role> + <direction>Input</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_byteenable_0</name> + <role>byteenable</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_readdatavalid_0</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8589934592</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>emif_usr_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>emif_usr_reset_n</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>true</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>64</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_emif_s10</className> + <version>19.2.4</version> + <displayName>External Memory Interfaces Intel Stratix 10 FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>50000000</parameterDefaultValue> + <parameterName>CAL_DEBUG_CLOCK_FREQUENCY</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>cal_debug_clk_clock_sink</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>SYS_INFO_DEVICE</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>SYS_INFO_DEVICE_DIE_REVISIONS</parameterName> + <parameterType>[Ljava.lang.String;</parameterType> + <systemInfotype>DEVICE_DIE_REVISIONS</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>SYS_INFO_DEVICE_FAMILY</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE_FAMILY</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>SYS_INFO_DEVICE_POWER_MODEL</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>DEVICE_POWER_MODEL</systemInfoArgs> + <systemInfotype>PART_TRAIT</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>SYS_INFO_DEVICE_SPEEDGRADE</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>SYS_INFO_DEVICE_TEMPERATURE_GRADE</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>DEVICE_TEMPERATURE_GRADE</systemInfoArgs> + <systemInfotype>PART_TRAIT</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>SYS_INFO_UNIQUE_ID</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>UNIQUE_ID</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>UNKNOWN</parameterDefaultValue> + <parameterName>TRAIT_IOBANK_REVISION</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>DEVICE_IOBANK_REVISION</systemInfoArgs> + <systemInfotype>PART_TRAIT</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>TRAIT_SUPPORTS_VID</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>SUPPORTS_VID</systemInfoArgs> + <systemInfotype>PART_TRAIT</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>ctrl_amm_0</key> + <value> + <connectionPointName>ctrl_amm_0</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='ctrl_amm_0' start='0x0' end='0x200000000' datawidth='512' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>33</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>512</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>emif_usr_clk</key> + <value> + <connectionPointName>emif_usr_clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>333333333</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>local_reset_req</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>local_reset_req</name> + <role>local_reset_req</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>local_reset_status</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>local_reset_done</name> + <role>local_reset_done</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>pll_ref_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>pll_ref_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>oct</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>oct_rzqin</name> + <role>oct_rzqin</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>mem_ck</name> + <role>mem_ck</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_ck_n</name> + <role>mem_ck_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_a</name> + <role>mem_a</role> + <direction>Output</direction> + <width>17</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_act_n</name> + <role>mem_act_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_ba</name> + <role>mem_ba</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_bg</name> + <role>mem_bg</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_cke</name> + <role>mem_cke</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_cs_n</name> + <role>mem_cs_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_odt</name> + <role>mem_odt</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_reset_n</name> + <role>mem_reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_par</name> + <role>mem_par</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_alert_n</name> + <role>mem_alert_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_dqs</name> + <role>mem_dqs</role> + <direction>Bidir</direction> + <width>9</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_dqs_n</name> + <role>mem_dqs_n</role> + <direction>Bidir</direction> + <width>9</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_dq</name> + <role>mem_dq</role> + <direction>Bidir</direction> + <width>72</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_dbi_n</name> + <role>mem_dbi_n</role> + <direction>Bidir</direction> + <width>9</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>status</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>local_cal_success</name> + <role>local_cal_success</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>local_cal_fail</name> + <role>local_cal_fail</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>emif_usr_reset_n</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>emif_usr_reset_n</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>none</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>emif_usr_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>emif_usr_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + </entry> + <entry> + <key>clockRate</key> + <value>333333333</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ctrl_ecc_user_interrupt_0</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>ctrl_ecc_user_interrupt_0</name> + <role>ctrl_ecc_user_interrupt</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ctrl_amm_0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>amm_ready_0</name> + <role>waitrequest_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_read_0</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_write_0</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_address_0</name> + <role>address</role> + <direction>Input</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_readdata_0</name> + <role>readdata</role> + <direction>Output</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_writedata_0</name> + <role>writedata</role> + <direction>Input</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_burstcount_0</name> + <role>burstcount</role> + <direction>Input</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_byteenable_0</name> + <role>byteenable</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_readdatavalid_0</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8589934592</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>emif_usr_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>emif_usr_reset_n</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>true</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>64</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>DE10_Pro_QSYS_emif_s10_ddr4_b</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>DE10_Pro_QSYS_emif_s10_ddr4_b</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_emif_s10_ddr4_b</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>DE10_Pro_QSYS_emif_s10_ddr4_b</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_emif_s10_ddr4_b</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>DE10_Pro_QSYS_emif_s10_ddr4_b</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_emif_s10_ddr4_b</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/DE10_Pro_QSYS/DE10_Pro_QSYS_emif_s10_ddr4_b.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + iopll_0 + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>ui.blockdiagram.direction</key> + <value>input</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>refclk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>refclk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>ui.blockdiagram.direction</key> + <value>input</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>50000000</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>locked</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>locked</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>ui.blockdiagram.direction</key> + <value>output</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>outclk0</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>outclk_0</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>ui.blockdiagram.direction</key> + <value>output</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + </entry> + <entry> + <key>clockRate</key> + <value>50000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>outclk1</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>outclk_1</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>ui.blockdiagram.direction</key> + <value>output</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + </entry> + <entry> + <key>clockRate</key> + <value>200000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>outclk2</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>outclk_2</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>ui.blockdiagram.direction</key> + <value>output</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + </entry> + <entry> + <key>clockRate</key> + <value>200000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_iopll</className> + <version>19.3.1</version> + <displayName>IOPLL Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>system_info_device_component</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>system_info_device_family</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE_FAMILY</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>system_info_device_speed_grade</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>system_part_trait_iobank_rev</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>DEVICE_IOBANK_REVISION</systemInfoArgs> + <systemInfotype>PART_TRAIT</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>system_part_trait_speed_grade</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>DEVICE_SPEEDGRADE</systemInfoArgs> + <systemInfotype>PART_TRAIT</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>outclk0</key> + <value> + <connectionPointName>outclk0</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>50000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>outclk1</key> + <value> + <connectionPointName>outclk1</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>200000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>outclk2</key> + <value> + <connectionPointName>outclk2</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>200000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>ui.blockdiagram.direction</key> + <value>input</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>refclk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>refclk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>ui.blockdiagram.direction</key> + <value>input</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>50000000</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>locked</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>locked</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>ui.blockdiagram.direction</key> + <value>output</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>outclk0</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>outclk_0</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>ui.blockdiagram.direction</key> + <value>output</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + </entry> + <entry> + <key>clockRate</key> + <value>50000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>outclk1</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>outclk_1</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>ui.blockdiagram.direction</key> + <value>output</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + </entry> + <entry> + <key>clockRate</key> + <value>200000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>outclk2</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>outclk_2</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>ui.blockdiagram.direction</key> + <value>output</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + </entry> + <entry> + <key>clockRate</key> + <value>200000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>DE10_Pro_QSYS_iopll_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>DE10_Pro_QSYS_iopll_0</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_iopll_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>DE10_Pro_QSYS_iopll_0</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_iopll_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>DE10_Pro_QSYS_iopll_0</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_iopll_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/DE10_Pro_QSYS/DE10_Pro_QSYS_iopll_0.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap> + <entry> + <key>embeddedsw.dts.compatible</key> + <value>altr,pll</value> + </entry> + <entry> + <key>embeddedsw.dts.group</key> + <value>clock</value> + </entry> + <entry> + <key>embeddedsw.dts.vendor</key> + <value>altr</value> + </entry> + </assignmentValueMap> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + jtag_uart_0 + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>avalon_jtag_slave</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>av_chipselect</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_read_n</name> + <role>read_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_write_n</name> + <role>write_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>1</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>2</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>true</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt; +&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt; + &lt;peripherals&gt; + &lt;peripheral&gt; + &lt;name&gt;altera_avalon_jtag_uart&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt; + &lt;addressBlock&gt; + &lt;offset&gt;0x0&lt;/offset&gt; + &lt;size&gt;8&lt;/size&gt; + &lt;usage&gt;registers&lt;/usage&gt; + &lt;/addressBlock&gt; + &lt;registers&gt; + &lt;register&gt; + &lt;name&gt;DATA&lt;/name&gt; + &lt;displayName&gt;Data&lt;/displayName&gt; + &lt;description&gt;Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost.&lt;/description&gt; + &lt;addressOffset&gt;0x0&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;data&lt;/name&gt; + &lt;description&gt;The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;8&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;rvalid&lt;/name&gt; + &lt;description&gt;Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined.&lt;/description&gt; + &lt;bitOffset&gt;0xf&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;ravail&lt;/name&gt; + &lt;description&gt;The number of characters remaining in the read FIFO (after the current read).&lt;/description&gt; + &lt;bitOffset&gt;0x10&lt;/bitOffset&gt; + &lt;bitWidth&gt;16&lt;/bitWidth&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;CONTROL&lt;/name&gt; + &lt;displayName&gt;Control&lt;/displayName&gt; + &lt;description&gt;Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit.&lt;/description&gt; + &lt;addressOffset&gt;0x4&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;re&lt;/name&gt; + &lt;description&gt;Interrupt-enable bit for read interrupts.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;we&lt;/name&gt; + &lt;description&gt;Interrupt-enable bit for write interrupts&lt;/description&gt; + &lt;bitOffset&gt;0x1&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;ri&lt;/name&gt; + &lt;description&gt;Indicates that the read interrupt is pending.&lt;/description&gt; + &lt;bitOffset&gt;0x8&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;wi&lt;/name&gt; + &lt;description&gt;Indicates that the write interrupt is pending.&lt;/description&gt; + &lt;bitOffset&gt;0x9&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;ac&lt;/name&gt; + &lt;description&gt;Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0.&lt;/description&gt; + &lt;bitOffset&gt;0xa&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;wspace&lt;/name&gt; + &lt;description&gt;The number of spaces available in the write FIFO&lt;/description&gt; + &lt;bitOffset&gt;0x10&lt;/bitOffset&gt; + &lt;bitWidth&gt;16&lt;/bitWidth&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;/registers&gt; + &lt;/peripheral&gt; + &lt;/peripherals&gt; +&lt;/device&gt; </cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars/> + </cmsisInfo> + </interface> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>irq</name> + <type>interrupt</type> + <isStart>false</isStart> + <ports> + <port> + <name>av_irq</name> + <role>irq</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + <value>jtag_uart_0.avalon_jtag_slave</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bridgedReceiverOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToReceiver</key> + </entry> + <entry> + <key>irqScheme</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_avalon_jtag_uart</className> + <version>19.1.0</version> + <displayName>JTAG UART Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>avalonSpec</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>AVALON_SPEC</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>clkFreq</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>avalon_jtag_slave</key> + <value> + <connectionPointName>avalon_jtag_slave</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='avalon_jtag_slave' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>50000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>avalon_jtag_slave</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>av_chipselect</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>av_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>av_read_n</name> + <role>read_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>av_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>av_write_n</name> + <role>write_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>av_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>av_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>1</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>2</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>true</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt; +&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt; + &lt;peripherals&gt; + &lt;peripheral&gt; + &lt;name&gt;altera_avalon_jtag_uart&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt; + &lt;addressBlock&gt; + &lt;offset&gt;0x0&lt;/offset&gt; + &lt;size&gt;8&lt;/size&gt; + &lt;usage&gt;registers&lt;/usage&gt; + &lt;/addressBlock&gt; + &lt;registers&gt; + &lt;register&gt; + &lt;name&gt;DATA&lt;/name&gt; + &lt;displayName&gt;Data&lt;/displayName&gt; + &lt;description&gt;Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost.&lt;/description&gt; + &lt;addressOffset&gt;0x0&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;data&lt;/name&gt; + &lt;description&gt;The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;8&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;rvalid&lt;/name&gt; + &lt;description&gt;Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined.&lt;/description&gt; + &lt;bitOffset&gt;0xf&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;ravail&lt;/name&gt; + &lt;description&gt;The number of characters remaining in the read FIFO (after the current read).&lt;/description&gt; + &lt;bitOffset&gt;0x10&lt;/bitOffset&gt; + &lt;bitWidth&gt;16&lt;/bitWidth&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;CONTROL&lt;/name&gt; + &lt;displayName&gt;Control&lt;/displayName&gt; + &lt;description&gt;Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit.&lt;/description&gt; + &lt;addressOffset&gt;0x4&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;re&lt;/name&gt; + &lt;description&gt;Interrupt-enable bit for read interrupts.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;we&lt;/name&gt; + &lt;description&gt;Interrupt-enable bit for write interrupts&lt;/description&gt; + &lt;bitOffset&gt;0x1&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;ri&lt;/name&gt; + &lt;description&gt;Indicates that the read interrupt is pending.&lt;/description&gt; + &lt;bitOffset&gt;0x8&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;wi&lt;/name&gt; + &lt;description&gt;Indicates that the write interrupt is pending.&lt;/description&gt; + &lt;bitOffset&gt;0x9&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;ac&lt;/name&gt; + &lt;description&gt;Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0.&lt;/description&gt; + &lt;bitOffset&gt;0xa&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;wspace&lt;/name&gt; + &lt;description&gt;The number of spaces available in the write FIFO&lt;/description&gt; + &lt;bitOffset&gt;0x10&lt;/bitOffset&gt; + &lt;bitWidth&gt;16&lt;/bitWidth&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;/registers&gt; + &lt;/peripheral&gt; + &lt;/peripherals&gt; +&lt;/device&gt; </cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars/> + </cmsisInfo> + </interface> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>irq</name> + <type>interrupt</type> + <isStart>false</isStart> + <ports> + <port> + <name>av_irq</name> + <role>irq</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + <value>jtag_uart_0.avalon_jtag_slave</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bridgedReceiverOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToReceiver</key> + </entry> + <entry> + <key>irqScheme</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>DE10_Pro_QSYS_jtag_uart_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>DE10_Pro_QSYS_jtag_uart_0</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_jtag_uart_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>DE10_Pro_QSYS_jtag_uart_0</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_jtag_uart_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>DE10_Pro_QSYS_jtag_uart_0</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_jtag_uart_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/DE10_Pro_QSYS/DE10_Pro_QSYS_jtag_uart_0.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap> + <entry> + <key>embeddedsw.CMacro.READ_DEPTH</key> + <value>64</value> + </entry> + <entry> + <key>embeddedsw.CMacro.READ_THRESHOLD</key> + <value>8</value> + </entry> + <entry> + <key>embeddedsw.CMacro.WRITE_DEPTH</key> + <value>64</value> + </entry> + <entry> + <key>embeddedsw.CMacro.WRITE_THRESHOLD</key> + <value>8</value> + </entry> + <entry> + <key>embeddedsw.dts.compatible</key> + <value>altr,juart-1.0</value> + </entry> + <entry> + <key>embeddedsw.dts.group</key> + <value>serial</value> + </entry> + <entry> + <key>embeddedsw.dts.name</key> + <value>juart</value> + </entry> + <entry> + <key>embeddedsw.dts.vendor</key> + <value>altr</value> + </entry> + </assignmentValueMap> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + mm_clockcross_50Mhz + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>m0</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>m0_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_burstcount</name> + <role>burstcount</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_address</name> + <role>address</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_debugaccess</name> + <role>debugaccess</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>m0_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>m0_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>m0_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>m0_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>m0_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>m0_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>m0_clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_burstcount</name> + <role>burstcount</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_address</name> + <role>address</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_debugaccess</name> + <role>debugaccess</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>s0_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>s0_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + <value>mm_clockcross_50Mhz.m0</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>8</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>s0_clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>mm_ccb</className> + <version>19.2.0</version> + <displayName>Avalon Memory Mapped Clock Crossing Bridge Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>10</parameterDefaultValue> + <parameterName>SYSINFO_ADDR_WIDTH</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>m0</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>m0</key> + <value> + <connectionPointName>m0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>s0</key> + <value> + <connectionPointName>s0</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>m0</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>m0_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>m0_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>m0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>m0_burstcount</name> + <role>burstcount</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>m0_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>m0_address</name> + <role>address</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>m0_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>m0_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>m0_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>m0_debugaccess</name> + <role>debugaccess</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>m0_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>m0_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>m0_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>m0_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>m0_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>m0_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>m0_clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>s0_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>s0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>s0_burstcount</name> + <role>burstcount</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>s0_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>s0_address</name> + <role>address</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>s0_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>s0_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>s0_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>s0_debugaccess</name> + <role>debugaccess</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>s0_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>s0_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + <value>mm_clockcross_50Mhz.m0</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>8</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>s0_clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>DE10_Pro_QSYS_mm_clock_crossing_bridge_50m</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>DE10_Pro_QSYS_mm_clock_crossing_bridge_50m</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_mm_clock_crossing_bridge_50m</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>DE10_Pro_QSYS_mm_clock_crossing_bridge_50m</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_mm_clock_crossing_bridge_50m</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>DE10_Pro_QSYS_mm_clock_crossing_bridge_50m</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_mm_clock_crossing_bridge_50m</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList> + <hdlParameterDescriptorDefinition> + <description>Bridge data width</description> + <enabled>true</enabled> + <exported>false</exported> + <parameterHdlType>INTEGER</parameterHdlType> + <parameterName>DATA_WIDTH</parameterName> + <parameterType>java.lang.Integer</parameterType> + <parameterValue>32</parameterValue> + </hdlParameterDescriptorDefinition> + <hdlParameterDescriptorDefinition> + <description>Symbol (byte) width</description> + <enabled>true</enabled> + <exported>false</exported> + <parameterHdlType>INTEGER</parameterHdlType> + <parameterName>SYMBOL_WIDTH</parameterName> + <parameterType>java.lang.Integer</parameterType> + <parameterValue>8</parameterValue> + </hdlParameterDescriptorDefinition> + <hdlParameterDescriptorDefinition> + <enabled>true</enabled> + <exported>false</exported> + <parameterHdlType>INTEGER</parameterHdlType> + <parameterName>HDL_ADDR_WIDTH</parameterName> + <parameterType>java.lang.Integer</parameterType> + <parameterValue>3</parameterValue> + </hdlParameterDescriptorDefinition> + <hdlParameterDescriptorDefinition> + <description>Burstcount width</description> + <enabled>true</enabled> + <exported>false</exported> + <parameterHdlType>INTEGER</parameterHdlType> + <parameterName>BURSTCOUNT_WIDTH</parameterName> + <parameterType>java.lang.Integer</parameterType> + <parameterValue>1</parameterValue> + </hdlParameterDescriptorDefinition> + <hdlParameterDescriptorDefinition> + <description>Command (master-to-slave) FIFO depth</description> + <enabled>true</enabled> + <exported>false</exported> + <parameterHdlType>INTEGER</parameterHdlType> + <parameterName>COMMAND_FIFO_DEPTH</parameterName> + <parameterType>java.lang.Integer</parameterType> + <parameterValue>4</parameterValue> + </hdlParameterDescriptorDefinition> + <hdlParameterDescriptorDefinition> + <description>Response (slave-to-master) FIFO depth</description> + <enabled>true</enabled> + <exported>false</exported> + <parameterHdlType>INTEGER</parameterHdlType> + <parameterName>RESPONSE_FIFO_DEPTH</parameterName> + <parameterType>java.lang.Integer</parameterType> + <parameterValue>4</parameterValue> + </hdlParameterDescriptorDefinition> + <hdlParameterDescriptorDefinition> + <description>Specifies the number of pipeline stages used to avoid metastable events</description> + <enabled>true</enabled> + <exported>false</exported> + <parameterHdlType>INTEGER</parameterHdlType> + <parameterName>MASTER_SYNC_DEPTH</parameterName> + <parameterType>java.lang.Integer</parameterType> + <parameterValue>2</parameterValue> + </hdlParameterDescriptorDefinition> + <hdlParameterDescriptorDefinition> + <description>Specifies the number of pipeline stages used to avoid metastable events</description> + <enabled>true</enabled> + <exported>false</exported> + <parameterHdlType>INTEGER</parameterHdlType> + <parameterName>SLAVE_SYNC_DEPTH</parameterName> + <parameterType>java.lang.Integer</parameterType> + <parameterValue>2</parameterValue> + </hdlParameterDescriptorDefinition> + <hdlParameterDescriptorDefinition> + <description>0 means allows asynchronous resets, 1 means internal reset synchronization</description> + <enabled>true</enabled> + <exported>false</exported> + <parameterHdlType>INTEGER</parameterHdlType> + <parameterName>SYNC_RESET</parameterName> + <parameterType>java.lang.Integer</parameterType> + <parameterValue>0</parameterValue> + </hdlParameterDescriptorDefinition> +</hdlParameterDescriptorDefinitionList> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/DE10_Pro_QSYS/DE10_Pro_QSYS_mm_clock_crossing_bridge_50m.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + mm_clockcross_DDR4 + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>m0_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>m0_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>m0_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>m0_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>m0_clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>s0_clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_burstcount</name> + <role>burstcount</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_address</name> + <role>address</role> + <direction>Input</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_debugaccess</name> + <role>debugaccess</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8589934592</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>s0_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>s0_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + <value>mm_clockcross_DDR4.m0</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>64</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>m0</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>m0_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_burstcount</name> + <role>burstcount</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_address</name> + <role>address</role> + <direction>Output</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_debugaccess</name> + <role>debugaccess</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>m0_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>m0_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>mm_ccb</className> + <version>19.2.0</version> + <displayName>Avalon Memory Mapped Clock Crossing Bridge Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>10</parameterDefaultValue> + <parameterName>SYSINFO_ADDR_WIDTH</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>m0</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>m0</key> + <value> + <connectionPointName>m0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_WIDTH</key> + <value>33</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>s0</key> + <value> + <connectionPointName>s0</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>m0_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>m0_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>m0_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>m0_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>m0_clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>s0_clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_burstcount</name> + <role>burstcount</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_address</name> + <role>address</role> + <direction>Input</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_debugaccess</name> + <role>debugaccess</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8589934592</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>s0_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>s0_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + <value>mm_clockcross_DDR4.m0</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>64</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>m0</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>m0_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_burstcount</name> + <role>burstcount</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_address</name> + <role>address</role> + <direction>Output</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_debugaccess</name> + <role>debugaccess</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>m0_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>m0_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>DE10_Pro_QSYS_mm_clockcross_DDR4</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>DE10_Pro_QSYS_mm_clockcross_DDR4</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_mm_clockcross_DDR4</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>DE10_Pro_QSYS_mm_clockcross_DDR4</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_mm_clockcross_DDR4</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>DE10_Pro_QSYS_mm_clockcross_DDR4</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_mm_clockcross_DDR4</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList> + <hdlParameterDescriptorDefinition> + <description>Bridge data width</description> + <enabled>true</enabled> + <exported>false</exported> + <parameterHdlType>INTEGER</parameterHdlType> + <parameterName>DATA_WIDTH</parameterName> + <parameterType>java.lang.Integer</parameterType> + <parameterValue>512</parameterValue> + </hdlParameterDescriptorDefinition> + <hdlParameterDescriptorDefinition> + <description>Symbol (byte) width</description> + <enabled>true</enabled> + <exported>false</exported> + <parameterHdlType>INTEGER</parameterHdlType> + <parameterName>SYMBOL_WIDTH</parameterName> + <parameterType>java.lang.Integer</parameterType> + <parameterValue>8</parameterValue> + </hdlParameterDescriptorDefinition> + <hdlParameterDescriptorDefinition> + <enabled>true</enabled> + <exported>false</exported> + <parameterHdlType>INTEGER</parameterHdlType> + <parameterName>HDL_ADDR_WIDTH</parameterName> + <parameterType>java.lang.Integer</parameterType> + <parameterValue>27</parameterValue> + </hdlParameterDescriptorDefinition> + <hdlParameterDescriptorDefinition> + <description>Burstcount width</description> + <enabled>true</enabled> + <exported>false</exported> + <parameterHdlType>INTEGER</parameterHdlType> + <parameterName>BURSTCOUNT_WIDTH</parameterName> + <parameterType>java.lang.Integer</parameterType> + <parameterValue>3</parameterValue> + </hdlParameterDescriptorDefinition> + <hdlParameterDescriptorDefinition> + <description>Command (master-to-slave) FIFO depth</description> + <enabled>true</enabled> + <exported>false</exported> + <parameterHdlType>INTEGER</parameterHdlType> + <parameterName>COMMAND_FIFO_DEPTH</parameterName> + <parameterType>java.lang.Integer</parameterType> + <parameterValue>32</parameterValue> + </hdlParameterDescriptorDefinition> + <hdlParameterDescriptorDefinition> + <description>Response (slave-to-master) FIFO depth</description> + <enabled>true</enabled> + <exported>false</exported> + <parameterHdlType>INTEGER</parameterHdlType> + <parameterName>RESPONSE_FIFO_DEPTH</parameterName> + <parameterType>java.lang.Integer</parameterType> + <parameterValue>32</parameterValue> + </hdlParameterDescriptorDefinition> + <hdlParameterDescriptorDefinition> + <description>Specifies the number of pipeline stages used to avoid metastable events</description> + <enabled>true</enabled> + <exported>false</exported> + <parameterHdlType>INTEGER</parameterHdlType> + <parameterName>MASTER_SYNC_DEPTH</parameterName> + <parameterType>java.lang.Integer</parameterType> + <parameterValue>2</parameterValue> + </hdlParameterDescriptorDefinition> + <hdlParameterDescriptorDefinition> + <description>Specifies the number of pipeline stages used to avoid metastable events</description> + <enabled>true</enabled> + <exported>false</exported> + <parameterHdlType>INTEGER</parameterHdlType> + <parameterName>SLAVE_SYNC_DEPTH</parameterName> + <parameterType>java.lang.Integer</parameterType> + <parameterValue>2</parameterValue> + </hdlParameterDescriptorDefinition> + <hdlParameterDescriptorDefinition> + <description>0 means allows asynchronous resets, 1 means internal reset synchronization</description> + <enabled>true</enabled> + <exported>false</exported> + <parameterHdlType>INTEGER</parameterHdlType> + <parameterName>SYNC_RESET</parameterName> + <parameterType>java.lang.Integer</parameterType> + <parameterValue>0</parameterValue> + </hdlParameterDescriptorDefinition> +</hdlParameterDescriptorDefinitionList> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/DE10_Pro_QSYS/DE10_Pro_QSYS_mm_clockcross_DDR4.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + reset_in + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_reset</name> + <role>reset</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_reset_bridge</className> + <version>19.2.0</version> + <displayName>Reset Bridge Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_CLK_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>50000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_reset</name> + <role>reset</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>DE10_Pro_QSYS_reset_in</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>DE10_Pro_QSYS_reset_in</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_reset_in</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>DE10_Pro_QSYS_reset_in</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_reset_in</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>DE10_Pro_QSYS_reset_in</fileSetName> + <fileSetFixedName>DE10_Pro_QSYS_reset_in</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/DE10_Pro_QSYS/DE10_Pro_QSYS_reset_in.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Intel Corporation + addressMap + addressMap + 1.0 + + + mm_clockcross_DDR4.s0 + + + + emif_s10_ddr4_b.ctrl_amm_0 + + + + SIMTight_0.dram_master + + + + 0x0000_0000_0000_0000 + + + + + mm_clockcross_50Mhz.s0 + + + + jtag_uart_0.avalon_jtag_slave + + + + SIMTight_0.uart_master + + + + 0x0000 + + + + + jtag_uart_0.avalon_jtag_slave + + + + mm_clockcross_50Mhz.m0 + + + + 0x0000 + + + + + emif_s10_ddr4_b.ctrl_amm_0 + + + + mm_clockcross_DDR4.m0 + + + + 0x0000_0000_0000_0000 + + + + + + + SIMTight_0.dram_master + + + mm_clockcross_DDR4.s0 + 0x0000_0000_0000_0000 + 0x0000_0002_0000_0000 + + + emif_s10_ddr4_b.ctrl_amm_0 via mm_clockcross_DDR4 + 0x0000_0000_0000_0000 + 0x0000_0002_0000_0000 + + + + + SIMTight_0.uart_master + + + mm_clockcross_50Mhz.s0 + 0x0000 + 0x0008 + + + jtag_uart_0.avalon_jtag_slave via mm_clockcross_50Mhz + 0x0000 + 0x0008 + + + + + mm_clockcross_50Mhz.m0 + + + jtag_uart_0.avalon_jtag_slave + 0x0000 + 0x0008 + + + + + mm_clockcross_DDR4.m0 + + + emif_s10_ddr4_b.ctrl_amm_0 + 0x0000_0000_0000_0000 + 0x0000_0002_0000_0000 + + + + + + + + true + false + + \ No newline at end of file diff --git a/de10-pro-e/DE10_Pro_assignment_defaults.qdf b/de10-pro-e/DE10_Pro_assignment_defaults.qdf new file mode 100644 index 0000000..9be331f --- /dev/null +++ b/de10-pro-e/DE10_Pro_assignment_defaults.qdf @@ -0,0 +1,711 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2019 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 19.1.0 Build 240 03/26/2019 SJ Pro Edition +# Date created = 11:49:45 May 05, 2019 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name MAX_IGNORED_ASGN_MSG 10 +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name INVALID_DESIGN_SOURCE Off +set_global_assignment -name FLOW_ENABLE_DESIGN_ASSISTANT Off +set_global_assignment -name DESIGN_ASSISTANT_INCLUDE_IP_BLOCKS Off +set_global_assignment -name DESIGN_ASSISTANT_MAX_VIOLATIONS_PER_RULE 500 +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Falcon Mesa" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 GX" +set_global_assignment -name TIMING_ANALYZER_SIMULTANEOUS_MULTICORNER_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off +set_global_assignment -name TIMING_ANALYZER_DO_REPORT_CDC_VIEWER Off +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off +set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Falcon Mesa" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 GX" +set_global_assignment -name FLOW_ENABLE_TIMING_ANALYZER_AFTER_PLAN_STAGE Off +set_global_assignment -name FLOW_ENABLE_TIMING_ANALYZER_AFTER_EARLY_PLACE_STAGE Off +set_global_assignment -name MIN_MTBF_REQUIREMENT 9 +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name ALLOW_REGISTER_RETIMING On +set_global_assignment -name ALLOW_RAM_RETIMING Off +set_global_assignment -name ALLOW_DSP_RETIMING Off +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL Enable +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone 10 GX" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Auto +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix 10" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Falcon Mesa" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone 10 GX" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Falcon Mesa" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix 10" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name SIZE_OF_LATCH_REPORT 100 +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE On +set_global_assignment -name ENABLE_FORMAL_VERIFICATION Off +set_global_assignment -name SIZE_OF_PR_INITIAL_CONDITIONS_REPORT 15 +set_global_assignment -name REPORT_PR_INITIAL_VALUES_AS_ERROR Off +set_global_assignment -name FRACTAL_SYNTHESIS Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS On -family "Falcon Mesa" +set_global_assignment -name PHYSICAL_SYNTHESIS Off -family "Arria 10" +set_global_assignment -name PHYSICAL_SYNTHESIS On -family "Stratix 10" +set_global_assignment -name PHYSICAL_SYNTHESIS Off -family "Cyclone 10 GX" +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Active Serial x4" -family "Falcon Mesa" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Active Serial x4" -family "Stratix 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone 10 GX" +set_global_assignment -name VID_OPERATION_MODE "PMBus Master" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name USE_HPS_COLD_RESET AUTO +set_global_assignment -name USE_HPS_WARM_RESET AUTO +set_global_assignment -name HPS_WARM_RESET_PIN_MODE BIDIRECTIONAL +set_global_assignment -name HPS_COLD_RESET_PIN_MODE BIDIRECTIONAL +set_global_assignment -name USE_UIB_CATTRIP AUTO +set_global_assignment -name SDM_PCIE_CALIB_START AUTO +set_global_assignment -name USE_PWRMGT_PWM0 AUTO +set_global_assignment -name SDM_DIRECT_TO_FACTORY_IMAGE AUTO +set_global_assignment -name USE_DATA_UNLOCK AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name ALLOW_VCCR_VCCT_PER_BANK Off +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Falcon Mesa" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Falcon Mesa" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 GX" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Cyclone 10 GX" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Falcon Mesa" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 GX" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone 10 GX" +set_global_assignment -name ENABLE_ED_CRC_CHECK On -family "Falcon Mesa" +set_global_assignment -name ENABLE_ED_CRC_CHECK On -family "Stratix 10" +set_global_assignment -name ALLOW_SEU_FAULT_INJECTION Off -family "Falcon Mesa" +set_global_assignment -name ALLOW_SEU_FAULT_INJECTION Off -family "Stratix 10" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone 10 GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ -family "Falcon Mesa" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ -family "Stratix 10" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name FLOW_ENABLE_EARLY_PLACE Off +set_global_assignment -name GLOBAL_PLACEMENT_EFFORT Normal +set_global_assignment -name OPTIMIZE_PERSONA_ROUTABILITY Off +set_global_assignment -name NUMBER_OF_EXAMPLE_NODES_REPORTED 50 +set_global_assignment -name PR_SECURITY_VALIDATION Off +set_global_assignment -name MODULE_BLOATING_FACTOR 0.0 +set_global_assignment -name ENABLE_INTERMEDIATE_SNAPSHOTS Off +set_global_assignment -name FITTER_EARLY_RETIMING On -family "Falcon Mesa" +set_global_assignment -name FITTER_EARLY_RETIMING On -family "Stratix 10" +set_global_assignment -name HYPER_AWARE_OPTIMIZE_REGISTER_CHAINS OFF -family "Falcon Mesa" +set_global_assignment -name HYPER_AWARE_OPTIMIZE_REGISTER_CHAINS OFF -family "Stratix 10" +set_global_assignment -name FLOW_ENABLE_HYPER_RETIMER_FAST_FORWARD Off -family "Falcon Mesa" +set_global_assignment -name FLOW_ENABLE_HYPER_RETIMER_FAST_FORWARD Off -family "Stratix 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_CUT_ALL_CLOCK_TRANSFERS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name CRITICAL_CHAIN_VIEWER On +set_global_assignment -name HYPER_RETIMER_ENABLE_ADD_PIPELINING On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name DISABLE_REGISTER_POWERUP_INITIALIZATION Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_TABLE_VERSION 1 +set_global_assignment -name PWRMGT_ADV_VOLTAGE_STABLE_DELAY 10 +set_global_assignment -name PWRMGT_ADV_FPGA_RELEASE_DELAY 10 +set_global_assignment -name PWRMGT_ADV_INITIAL_DELAY 0 +set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHz" +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTM4677 +set_global_assignment -name PWRMGT_DEVICE_ADDRESS_IN_PMBUS_SLAVE_MODE 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name PWRMGT_LINEAR_FORMAT_N 0 +set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT Volts +set_global_assignment -name PWRMGT_ADV_DATA_SETUP_TIME 0 +set_global_assignment -name PWRMGT_ADV_DATA_HOLD_TIME 0 +set_global_assignment -name PWRMGT_ADV_CLOCK_DATA_FALL_TIME 0 +set_global_assignment -name PWRMGT_ADV_CLOCK_DATA_RISE_TIME 0 +set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE Off +set_global_assignment -name PWRMGT_ADV_VOUT_READING_ERR_MARGIN 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_PR_RBF_FILE On -family "Falcon Mesa" +set_global_assignment -name GENERATE_PR_RBF_FILE On -family "Stratix 10" +set_global_assignment -name GENERATE_PR_RBF_FILE Off -family "Arria 10" +set_global_assignment -name GENERATE_PR_RBF_FILE Off -family "Cyclone 10 GX" +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name RBF_FILE_GENERATION_FOR_SUPR On +set_global_assignment -name ENABLE_PR_POF_ID On +set_global_assignment -name HPS_INITIALIZATION "After INIT_DONE" +set_global_assignment -name HPS_DAP_SPLIT_MODE Disabled +set_global_assignment -name PRIORITY_SEU_AREA Off +set_global_assignment -name ENCRYPT_PROGRAMMING_BITSTREAM Off +set_global_assignment -name PROGRAMMING_BITSTREAM_ENCRYPTION_KEY_SELECT "Backup Battery RAM" +set_global_assignment -name PROGRAMMING_BITSTREAM_ENCRYPTION_UPDATE_RATIO 0 +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On -family "Cyclone 10 GX" +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On -family "Arria 10" +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_COOLING_FOR_MAX_TJ Off -family "Stratix 10" +set_global_assignment -name POWER_MAX_TJ_VALUE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_SDF_FOR_POWER Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? diff --git a/de10-pro-e/Makefile b/de10-pro-e/Makefile new file mode 100644 index 0000000..0fbdf41 --- /dev/null +++ b/de10-pro-e/Makefile @@ -0,0 +1,51 @@ +SIMTIGHT_ROOT ?= $(realpath ..) +NUM_SEEDS ?= 4 +QPF = DE10_Pro.qpf + +.PHONY: one +one: checkenv ip + time quartus_sh --flow compile $(QPF) + +.PHONY: many +many: checkenv ip + quartus_dse $(QPF) \ + --num-seeds $$(($(NUM_SEEDS) - 1)) \ + --launcher local \ + --num-concurrent 4 + quartus_dse $(QPF) --report utilization + quartus_dse $(QPF) --report fmax_summary + +.PHONY: ip +ip: checkenv + make -C $(SIMTIGHT_ROOT)/src + make -C $(SIMTIGHT_ROOT)/boot + quartus_ipgenerate DE10_Pro.qpf + ../pebbles/blarney/blarney-vendor-ip/IntelFPGA/AvalonStreamClockCrosser/post-ipgenerate.sh + +.PHONY: report +report: checkenv + quartus_dse $(QPF) --report utilization + quartus_dse $(QPF) --report fmax_summary + +.PHONY: update-mif +update-mif: checkenv + quartus_cdb --update_mif DE10_Pro.qpf + quartus_asm DE10_Pro.qpf + +.PHONY: download-sof +download-sof: checkenv + quartus_pgm -m jtag -o "p;output_files/DE10_Pro.sof" + +.PHONY: clean +clean: + rm -rf tmp-clearbox synth_dumps qdb output_files + rm -rf DE10_Pro_QSYS reset_release db dse* + rm -rf ../pebbles/blarney/blarney-vendor-ip/IntelFPGA/AvalonStreamClockCrosser/AvalonStreamClockCrosser + rm -f DE10_Pro.qws *.rpt *.csv *.mif + ls ip/DE10_Pro_QSYS/ | grep -v -E '\.ip$$' \ + | xargs -i rm -rf ip/DE10_Pro_QSYS/{} + +# Raise error if QUARTUS_ROOTDIR not set +.PHONY: checkenv +checkenv: + $(if $(value QUARTUS_ROOTDIR), , $(error Please set QUARTUS_ROOTDIR)) diff --git a/de10-pro-e/SIMTight_hw.tcl b/de10-pro-e/SIMTight_hw.tcl new file mode 100644 index 0000000..cd22300 --- /dev/null +++ b/de10-pro-e/SIMTight_hw.tcl @@ -0,0 +1,206 @@ +# TCL File Generated by Component Editor 21.3 +# Tue Oct 04 10:49:58 BST 2022 +# DO NOT MODIFY + + +# +# SIMTight "SIMTight" v1.0 +# 2022.10.04.10:49:58 +# +# + +# +# request TCL package from ACDS 21.3 +# +package require -exact qsys 21.3 + + +# +# module SIMTight +# +set_module_property DESCRIPTION "" +set_module_property NAME SIMTight +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME SIMTight +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false +set_module_property LOAD_ELABORATION_LIMIT 0 + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL SIMTight +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file SIMTight.v VERILOG PATH ../src/SIMTight.v TOP_LEVEL_FILE + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point dram_master +# +add_interface dram_master avalon start +set_interface_property dram_master addressGroup 0 +set_interface_property dram_master addressUnits WORDS +set_interface_property dram_master associatedClock simt_clock +set_interface_property dram_master associatedReset simt_reset +set_interface_property dram_master bitsPerSymbol 8 +set_interface_property dram_master burstOnBurstBoundariesOnly false +set_interface_property dram_master burstcountUnits WORDS +set_interface_property dram_master doStreamReads false +set_interface_property dram_master doStreamWrites false +set_interface_property dram_master holdTime 0 +set_interface_property dram_master linewrapBursts false +set_interface_property dram_master maximumPendingReadTransactions 0 +set_interface_property dram_master maximumPendingWriteTransactions 0 +set_interface_property dram_master minimumResponseLatency 1 +set_interface_property dram_master readLatency 0 +set_interface_property dram_master readWaitTime 1 +set_interface_property dram_master setupTime 0 +set_interface_property dram_master timingUnits Cycles +set_interface_property dram_master waitrequestAllowance 0 +set_interface_property dram_master writeWaitTime 0 +set_interface_property dram_master ENABLED true +set_interface_property dram_master EXPORT_OF "" +set_interface_property dram_master PORT_NAME_MAP "" +set_interface_property dram_master CMSIS_SVD_VARIABLES "" +set_interface_property dram_master SVD_ADDRESS_GROUP "" +set_interface_property dram_master IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port dram_master in0_socDRAMIns_avl_dram_readdata readdata Input 512 +add_interface_port dram_master in0_socDRAMIns_avl_dram_readdatavalid readdatavalid Input 1 +set_port_property in0_socDRAMIns_avl_dram_readdatavalid VHDL_TYPE STD_LOGIC_VECTOR +add_interface_port dram_master in0_socDRAMIns_avl_dram_waitrequest waitrequest Input 1 +set_port_property in0_socDRAMIns_avl_dram_waitrequest VHDL_TYPE STD_LOGIC_VECTOR +add_interface_port dram_master out_socDRAMOuts_avl_dram_address address Output 28 +add_interface_port dram_master out_socDRAMOuts_avl_dram_burstcount burstcount Output 4 +add_interface_port dram_master out_socDRAMOuts_avl_dram_byteen byteenable Output 64 +add_interface_port dram_master out_socDRAMOuts_avl_dram_read read Output 1 +set_port_property out_socDRAMOuts_avl_dram_read VHDL_TYPE STD_LOGIC_VECTOR +add_interface_port dram_master out_socDRAMOuts_avl_dram_write write Output 1 +set_port_property out_socDRAMOuts_avl_dram_write VHDL_TYPE STD_LOGIC_VECTOR +add_interface_port dram_master out_socDRAMOuts_avl_dram_writedata writedata Output 512 + + +# +# connection point uart_master +# +add_interface uart_master avalon start +set_interface_property uart_master addressGroup 0 +set_interface_property uart_master addressUnits SYMBOLS +set_interface_property uart_master associatedClock cpu_clock +set_interface_property uart_master associatedReset cpu_reset +set_interface_property uart_master bitsPerSymbol 8 +set_interface_property uart_master burstOnBurstBoundariesOnly false +set_interface_property uart_master burstcountUnits WORDS +set_interface_property uart_master doStreamReads false +set_interface_property uart_master doStreamWrites false +set_interface_property uart_master holdTime 0 +set_interface_property uart_master linewrapBursts false +set_interface_property uart_master maximumPendingReadTransactions 0 +set_interface_property uart_master maximumPendingWriteTransactions 0 +set_interface_property uart_master minimumResponseLatency 1 +set_interface_property uart_master readLatency 0 +set_interface_property uart_master readWaitTime 1 +set_interface_property uart_master setupTime 0 +set_interface_property uart_master timingUnits Cycles +set_interface_property uart_master waitrequestAllowance 0 +set_interface_property uart_master writeWaitTime 0 +set_interface_property uart_master ENABLED true +set_interface_property uart_master EXPORT_OF "" +set_interface_property uart_master PORT_NAME_MAP "" +set_interface_property uart_master CMSIS_SVD_VARIABLES "" +set_interface_property uart_master SVD_ADDRESS_GROUP "" +set_interface_property uart_master IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port uart_master in0_socUARTIns_avl_jtaguart_readdata readdata Input 32 +add_interface_port uart_master in0_socUARTIns_avl_jtaguart_waitrequest waitrequest Input 1 +set_port_property in0_socUARTIns_avl_jtaguart_waitrequest VHDL_TYPE STD_LOGIC_VECTOR +add_interface_port uart_master out_socUARTOuts_avl_jtaguart_address address Output 3 +add_interface_port uart_master out_socUARTOuts_avl_jtaguart_read read Output 1 +set_port_property out_socUARTOuts_avl_jtaguart_read VHDL_TYPE STD_LOGIC_VECTOR +add_interface_port uart_master out_socUARTOuts_avl_jtaguart_write write Output 1 +set_port_property out_socUARTOuts_avl_jtaguart_write VHDL_TYPE STD_LOGIC_VECTOR +add_interface_port uart_master out_socUARTOuts_avl_jtaguart_writedata writedata Output 32 + + +# +# connection point simt_clock +# +add_interface simt_clock clock end +set_interface_property simt_clock ENABLED true +set_interface_property simt_clock EXPORT_OF "" +set_interface_property simt_clock PORT_NAME_MAP "" +set_interface_property simt_clock CMSIS_SVD_VARIABLES "" +set_interface_property simt_clock SVD_ADDRESS_GROUP "" +set_interface_property simt_clock IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port simt_clock in0_socSIMTClk clk Input 1 +set_port_property in0_socSIMTClk VHDL_TYPE STD_LOGIC_VECTOR + + +# +# connection point cpu_clock +# +add_interface cpu_clock clock end +set_interface_property cpu_clock ENABLED true +set_interface_property cpu_clock EXPORT_OF "" +set_interface_property cpu_clock PORT_NAME_MAP "" +set_interface_property cpu_clock CMSIS_SVD_VARIABLES "" +set_interface_property cpu_clock SVD_ADDRESS_GROUP "" +set_interface_property cpu_clock IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port cpu_clock in0_socCPUClk clk Input 1 +set_port_property in0_socCPUClk VHDL_TYPE STD_LOGIC_VECTOR + + +# +# connection point simt_reset +# +add_interface simt_reset reset end +set_interface_property simt_reset associatedClock simt_clock +set_interface_property simt_reset synchronousEdges DEASSERT +set_interface_property simt_reset ENABLED true +set_interface_property simt_reset EXPORT_OF "" +set_interface_property simt_reset PORT_NAME_MAP "" +set_interface_property simt_reset CMSIS_SVD_VARIABLES "" +set_interface_property simt_reset SVD_ADDRESS_GROUP "" +set_interface_property simt_reset IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port simt_reset in0_socSIMTRst reset Input 1 +set_port_property in0_socSIMTRst VHDL_TYPE STD_LOGIC_VECTOR + + +# +# connection point cpu_reset +# +add_interface cpu_reset reset end +set_interface_property cpu_reset associatedClock cpu_clock +set_interface_property cpu_reset synchronousEdges DEASSERT +set_interface_property cpu_reset ENABLED true +set_interface_property cpu_reset EXPORT_OF "" +set_interface_property cpu_reset PORT_NAME_MAP "" +set_interface_property cpu_reset CMSIS_SVD_VARIABLES "" +set_interface_property cpu_reset SVD_ADDRESS_GROUP "" +set_interface_property cpu_reset IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port cpu_reset in0_socCPURst reset Input 1 +set_port_property in0_socCPURst VHDL_TYPE STD_LOGIC_VECTOR + diff --git a/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_SIMTight_0.ip b/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_SIMTight_0.ip new file mode 100644 index 0000000..48f3b3a --- /dev/null +++ b/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_SIMTight_0.ip @@ -0,0 +1,1630 @@ + + + + Altera Corporation + DE10_Pro_QSYS_SIMTight_0 + SIMTight_0 + 1.0 + + + dram_master + + + + + + + + readdata + + + in0_socDRAMIns_avl_dram_readdata + + + + + readdatavalid + + + in0_socDRAMIns_avl_dram_readdatavalid + + + + + waitrequest + + + in0_socDRAMIns_avl_dram_waitrequest + + + + + address + + + out_socDRAMOuts_avl_dram_address + + + + + burstcount + + + out_socDRAMOuts_avl_dram_burstcount + + + + + byteenable + + + out_socDRAMOuts_avl_dram_byteen + + + + + read + + + out_socDRAMOuts_avl_dram_read + + + + + write + + + out_socDRAMOuts_avl_dram_write + + + + + writedata + + + out_socDRAMOuts_avl_dram_writedata + + + + + + + + + adaptsTo + Adapts to + + + + addressGroup + Address group + 0 + + + addressUnits + Address units + WORDS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + simt_clock + + + associatedReset + Associated reset + simt_reset + + + bitsPerSymbol + Bits per symbol + 8 + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + dBSBigEndian + dBS big endian + false + + + doStreamReads + Use flow control for read transfers + false + + + doStreamWrites + Use flow control for write transfers + false + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isAsynchronous + Is asynchronous + false + + + isBigEndian + Is big endian + false + + + isReadable + Is readable + false + + + isWriteable + Is writeable + false + + + linewrapBursts + Linewrap bursts + false + + + maxAddressWidth + Maximum address width + 32 + + + maximumPendingReadTransactions + Maximum pending read transactions + 0 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + readLatency + Read latency + 0 + + + readWaitTime + Read wait + 1 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + waitrequestAllowance + Waitrequest allowance + 0 + + + writeWaitTime + Write wait + 0 + + + + + uart_master + + + + + + + + readdata + + + in0_socUARTIns_avl_jtaguart_readdata + + + + + waitrequest + + + in0_socUARTIns_avl_jtaguart_waitrequest + + + + + address + + + out_socUARTOuts_avl_jtaguart_address + + + + + read + + + out_socUARTOuts_avl_jtaguart_read + + + + + write + + + out_socUARTOuts_avl_jtaguart_write + + + + + writedata + + + out_socUARTOuts_avl_jtaguart_writedata + + + + + + + + + adaptsTo + Adapts to + + + + addressGroup + Address group + 0 + + + addressUnits + Address units + SYMBOLS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + cpu_clock + + + associatedReset + Associated reset + cpu_reset + + + bitsPerSymbol + Bits per symbol + 8 + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + dBSBigEndian + dBS big endian + false + + + doStreamReads + Use flow control for read transfers + false + + + doStreamWrites + Use flow control for write transfers + false + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isAsynchronous + Is asynchronous + false + + + isBigEndian + Is big endian + false + + + isReadable + Is readable + false + + + isWriteable + Is writeable + false + + + linewrapBursts + Linewrap bursts + false + + + maxAddressWidth + Maximum address width + 32 + + + maximumPendingReadTransactions + Maximum pending read transactions + 0 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + readLatency + Read latency + 0 + + + readWaitTime + Read wait + 1 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + waitrequestAllowance + Waitrequest allowance + 0 + + + writeWaitTime + Write wait + 0 + + + + + simt_clock + + + + + + + + clk + + + in0_socSIMTClk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + cpu_clock + + + + + + + + clk + + + in0_socCPUClk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + simt_reset + + + + + + + + reset + + + in0_socSIMTRst + + + + + + + + + associatedClock + Associated clock + simt_clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + cpu_reset + + + + + + + + reset + + + in0_socCPURst + + + + + + + + + associatedClock + Associated clock + cpu_clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + SIMTight + + QUARTUS_SYNTH + + + + + + + in0_socDRAMIns_avl_dram_readdata + + in + + + 0 + 511 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + in0_socDRAMIns_avl_dram_readdatavalid + + in + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + in0_socDRAMIns_avl_dram_waitrequest + + in + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + out_socDRAMOuts_avl_dram_address + + out + + + 0 + 27 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + out_socDRAMOuts_avl_dram_burstcount + + out + + + 0 + 3 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + out_socDRAMOuts_avl_dram_byteen + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + out_socDRAMOuts_avl_dram_read + + out + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + out_socDRAMOuts_avl_dram_write + + out + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + out_socDRAMOuts_avl_dram_writedata + + out + + + 0 + 511 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + in0_socUARTIns_avl_jtaguart_readdata + + in + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + in0_socUARTIns_avl_jtaguart_waitrequest + + in + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + out_socUARTOuts_avl_jtaguart_address + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + out_socUARTOuts_avl_jtaguart_read + + out + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + out_socUARTOuts_avl_jtaguart_write + + out + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + out_socUARTOuts_avl_jtaguart_writedata + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + in0_socSIMTClk + + in + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + in0_socCPUClk + + in + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + in0_socSIMTRst + + in + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + in0_socCPURst + + in + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + + + + Altera Corporation + DE10_Pro_QSYS_SIMTight_0 + SIMTight + 1.0 + + + + + + + + device + Device + 1SX280HU2F50E1VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 1 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element $system + { + datum _originalDeviceFamily + { + value = "Stratix 10"; + type = "String"; + } + } + element SIMTight_0 + { + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>dram_master</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>in0_socDRAMIns_avl_dram_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>in0_socDRAMIns_avl_dram_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>in0_socDRAMIns_avl_dram_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socDRAMOuts_avl_dram_address</name> + <role>address</role> + <direction>Output</direction> + <width>28</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socDRAMOuts_avl_dram_burstcount</name> + <role>burstcount</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socDRAMOuts_avl_dram_byteen</name> + <role>byteenable</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socDRAMOuts_avl_dram_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socDRAMOuts_avl_dram_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socDRAMOuts_avl_dram_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>simt_clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>simt_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>uart_master</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>in0_socUARTIns_avl_jtaguart_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>in0_socUARTIns_avl_jtaguart_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socUARTOuts_avl_jtaguart_address</name> + <role>address</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socUARTOuts_avl_jtaguart_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socUARTOuts_avl_jtaguart_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>out_socUARTOuts_avl_jtaguart_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>cpu_clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>cpu_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>simt_clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in0_socSIMTClk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>cpu_clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in0_socCPUClk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>simt_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in0_socSIMTRst</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>simt_clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>cpu_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in0_socCPURst</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>cpu_clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_clock_in.ip b/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_clock_in.ip new file mode 100644 index 0000000..179558e --- /dev/null +++ b/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_clock_in.ip @@ -0,0 +1,361 @@ + + + + Intel Corporation + DE10_Pro_QSYS_clock_in + clock_in + 19.2.0 + + + in_clk + + + + + + + + clk + + + in_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + out_clk + + + + + + + + clk + + + out_clk + + + + + + + + + associatedDirectClock + Associated direct clock + in_clk + + + clockRate + Clock rate + 50000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_clock_bridge + + QUARTUS_SYNTH + + + + + + + in_clk + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + out_clk + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + DE10_Pro_QSYS_clock_in + altera_clock_bridge + 19.2.0 + + + + + DERIVED_CLOCK_RATE + Derived clock rate + 0 + + + EXPLICIT_CLOCK_RATE + Explicit clock rate + 50000000 + + + NUM_CLOCK_OUTPUTS + Number of Clock Outputs + 1 + + + + + + + device + Device + 1SX280HU2F50E1VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 1 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element $system + { + datum _originalDeviceFamily + { + value = "Stratix 10"; + type = "String"; + } + } + element clock_in + { + datum _originalVersion + { + value = "19.1"; + type = "String"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>in_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>in_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>50000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>in_clk</key> + <value> + <connectionPointName>in_clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>out_clk</key> + <value> + <connectionPointName>out_clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>50000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_ddr4_local_reset_req.ip b/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_ddr4_local_reset_req.ip new file mode 100644 index 0000000..e670cbb --- /dev/null +++ b/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_ddr4_local_reset_req.ip @@ -0,0 +1,792 @@ + + + Intel Corporation + DE10_Pro_QSYS_ddr4_local_reset_req + DE10_Pro_QSYS_ddr4_local_reset_req + 19.1 + + + clk + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + reset_n + + + + + + + + + associatedClock + Associated clock + clk + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + s1 + + + + + + + + address + + + address + + + + + write_n + + + write_n + + + + + writedata + + + writedata + + + + + chipselect + + + chipselect + + + + + readdata + + + readdata + + + + + + + + + addressAlignment + Slave addressing + NATIVE + + + addressGroup + Address group + 0 + + + addressSpan + Address span + 4 + + + addressUnits + Address units + WORDS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + clk + + + associatedReset + Associated reset + reset + + + bitsPerSymbol + Bits per symbol + 8 + + + bridgedAddressOffset + Bridged Address Offset + 0 + + + bridgesToMaster + Bridges to master + + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + explicitAddressSpan + Explicit address span + 0 + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isBigEndian + Big endian + false + + + isFlash + Flash memory + false + + + isMemoryDevice + Memory device + false + + + isNonVolatileStorage + Non-volatile storage + false + + + linewrapBursts + Linewrap bursts + false + + + maximumPendingReadTransactions + Maximum pending read transactions + 0 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + minimumUninterruptedRunLength + Minimum uninterrupted run length + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + printableDevice + Can receive stdout/stderr + false + + + readLatency + Read latency + 0 + + + readWaitStates + Read wait states + 1 + + + readWaitTime + Read wait + 1 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + transparentBridge + Transparent bridge + false + + + waitrequestAllowance + Waitrequest allowance + 0 + + + wellBehavedWaitrequest + Well-behaved waitrequest + false + + + writeLatency + Write latency + 0 + + + writeWaitStates + Write wait states + 0 + + + writeWaitTime + Write wait + 0 + + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + + + + + external_connection + + + + + + + + export + + + out_port + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_avalon_pio + + QUARTUS_SYNTH + + + + + + + clk + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + reset_n + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + address + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + write_n + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + writedata + + in + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + chipselect + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + readdata + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + out_port + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + DE10_Pro_QSYS_ddr4_local_reset_req + altera_avalon_pio + 19.1 + + + + + bitClearingEdgeCapReg + Enable bit-clearing for edge capture register + false + + + bitModifyingOutReg + Enable individual bit setting/clearing + false + + + captureEdge + Synchronously capture + false + + + direction + Direction + Output + + + edgeType + Edge Type + RISING + + + generateIRQ + Generate IRQ + false + + + irqType + IRQ Type + LEVEL + + + resetValue + Output Port Reset Value + 0 + + + simDoTestBenchWiring + Hardwire PIO inputs in test bench + false + + + simDrivenValue + Drive inputs to field. + 0 + + + width + Width (1-32 bits) + 1 + + + clockRate + clockRate + 50000000 + + + derived_has_tri + derived_has_tri + false + + + derived_has_out + derived_has_out + true + + + derived_has_in + derived_has_in + false + + + derived_do_test_bench_wiring + derived_do_test_bench_wiring + false + + + derived_capture + derived_capture + false + + + derived_edge_type + derived_edge_type + NONE + + + derived_irq_type + derived_irq_type + NONE + + + derived_has_irq + derived_has_irq + false + + + + + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 1 + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0 + + + embeddedsw.CMacro.EDGE_TYPE + NONE + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.IRQ_TYPE + NONE + + + embeddedsw.CMacro.RESET_VALUE + 0 + + + embeddedsw.dts.compatible + altr,pio-1.0 + + + embeddedsw.dts.group + gpio + + + embeddedsw.dts.name + pio + + + embeddedsw.dts.params.altr,gpio-bank-width + 1 + + + embeddedsw.dts.params.resetvalue + 0 + + + embeddedsw.dts.vendor + altr + + + + + + + device + Device + 1SX280HU2F50E1VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 1 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData { element $system { datum _originalDeviceFamily { value = "Stratix 10"; type = "String"; } } element DE10_Pro_QSYS_ddr4_local_reset_req { } } + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> <interfaces> <interface> <name>clk</name> <type>clock</type> <isStart>false</isStart> <ports> <port> <name>clk</name> <role>clk</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>clockRate</key> <value>0</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>reset</name> <type>reset</type> <isStart>false</isStart> <ports> <port> <name>reset_n</name> <role>reset_n</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>clk</value> </entry> <entry> <key>synchronousEdges</key> <value>DEASSERT</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>s1</name> <type>avalon</type> <isStart>false</isStart> <ports> <port> <name>address</name> <role>address</role> <direction>Input</direction> <width>2</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>write_n</name> <role>write_n</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>writedata</name> <role>writedata</role> <direction>Input</direction> <width>32</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>chipselect</name> <role>chipselect</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> <port> <name>readdata</name> <role>readdata</role> <direction>Output</direction> <width>32</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> </ports> <assignments> <assignmentValueMap> <entry> <key>embeddedsw.configuration.isFlash</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isMemoryDevice</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isNonVolatileStorage</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isPrintableDevice</key> <value>0</value> </entry> </assignmentValueMap> </assignments> <parameters> <parameterValueMap> <entry> <key>addressAlignment</key> <value>NATIVE</value> </entry> <entry> <key>addressGroup</key> <value>0</value> </entry> <entry> <key>addressSpan</key> <value>4</value> </entry> <entry> <key>addressUnits</key> <value>WORDS</value> </entry> <entry> <key>alwaysBurstMaxBurst</key> <value>false</value> </entry> <entry> <key>associatedClock</key> <value>clk</value> </entry> <entry> <key>associatedReset</key> <value>reset</value> </entry> <entry> <key>bitsPerSymbol</key> <value>8</value> </entry> <entry> <key>bridgedAddressOffset</key> <value>0</value> </entry> <entry> <key>bridgesToMaster</key> </entry> <entry> <key>burstOnBurstBoundariesOnly</key> <value>false</value> </entry> <entry> <key>burstcountUnits</key> <value>WORDS</value> </entry> <entry> <key>constantBurstBehavior</key> <value>false</value> </entry> <entry> <key>explicitAddressSpan</key> <value>0</value> </entry> <entry> <key>holdTime</key> <value>0</value> </entry> <entry> <key>interleaveBursts</key> <value>false</value> </entry> <entry> <key>isBigEndian</key> <value>false</value> </entry> <entry> <key>isFlash</key> <value>false</value> </entry> <entry> <key>isMemoryDevice</key> <value>false</value> </entry> <entry> <key>isNonVolatileStorage</key> <value>false</value> </entry> <entry> <key>linewrapBursts</key> <value>false</value> </entry> <entry> <key>maximumPendingReadTransactions</key> <value>0</value> </entry> <entry> <key>maximumPendingWriteTransactions</key> <value>0</value> </entry> <entry> <key>minimumReadLatency</key> <value>1</value> </entry> <entry> <key>minimumResponseLatency</key> <value>1</value> </entry> <entry> <key>minimumUninterruptedRunLength</key> <value>1</value> </entry> <entry> <key>prSafe</key> <value>false</value> </entry> <entry> <key>printableDevice</key> <value>false</value> </entry> <entry> <key>readLatency</key> <value>0</value> </entry> <entry> <key>readWaitStates</key> <value>1</value> </entry> <entry> <key>readWaitTime</key> <value>1</value> </entry> <entry> <key>registerIncomingSignals</key> <value>false</value> </entry> <entry> <key>registerOutgoingSignals</key> <value>false</value> </entry> <entry> <key>setupTime</key> <value>0</value> </entry> <entry> <key>timingUnits</key> <value>Cycles</value> </entry> <entry> <key>transparentBridge</key> <value>false</value> </entry> <entry> <key>waitrequestAllowance</key> <value>0</value> </entry> <entry> <key>wellBehavedWaitrequest</key> <value>false</value> </entry> <entry> <key>writeLatency</key> <value>0</value> </entry> <entry> <key>writeWaitStates</key> <value>0</value> </entry> <entry> <key>writeWaitTime</key> <value>0</value> </entry> </parameterValueMap> </parameters> <cmsisInfo> <cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt; &lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt; &lt;peripherals&gt; &lt;peripheral&gt; &lt;name&gt;altera_avalon_pio&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt; &lt;addressBlock&gt; &lt;offset&gt;0x0&lt;/offset&gt; &lt;size&gt;32&lt;/size&gt; &lt;usage&gt;registers&lt;/usage&gt; &lt;/addressBlock&gt; &lt;registers&gt; &lt;register&gt; &lt;name&gt;DATA&lt;/name&gt; &lt;displayName&gt;Data&lt;/displayName&gt; &lt;description&gt;Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).&lt;/description&gt; &lt;addressOffset&gt;0x0&lt;/addressOffset&gt; &lt;size&gt;32&lt;/size&gt; &lt;access&gt;read-write&lt;/access&gt; &lt;resetValue&gt;0x0&lt;/resetValue&gt; &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; &lt;fields&gt; &lt;field&gt;&lt;name&gt;data&lt;/name&gt; &lt;description&gt;Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.&lt;/description&gt; &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; &lt;bitWidth&gt;32&lt;/bitWidth&gt; &lt;access&gt;read-write&lt;/access&gt; &lt;/field&gt; &lt;/fields&gt; &lt;/register&gt; &lt;register&gt; &lt;name&gt;DIRECTION&lt;/name&gt; &lt;displayName&gt;Direction&lt;/displayName&gt; &lt;description&gt;The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.&lt;/description&gt; &lt;addressOffset&gt;0x4&lt;/addressOffset&gt; &lt;size&gt;32&lt;/size&gt; &lt;access&gt;read-write&lt;/access&gt; &lt;resetValue&gt;0x0&lt;/resetValue&gt; &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; &lt;fields&gt; &lt;field&gt;&lt;name&gt;direction&lt;/name&gt; &lt;description&gt;Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.&lt;/description&gt; &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; &lt;bitWidth&gt;32&lt;/bitWidth&gt; &lt;access&gt;read-write&lt;/access&gt; &lt;/field&gt; &lt;/fields&gt; &lt;/register&gt; &lt;register&gt; &lt;name&gt;IRQ_MASK&lt;/name&gt; &lt;displayName&gt;Interrupt mask&lt;/displayName&gt; &lt;description&gt;Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.&lt;/description&gt; &lt;addressOffset&gt;0x8&lt;/addressOffset&gt; &lt;size&gt;32&lt;/size&gt; &lt;access&gt;read-write&lt;/access&gt; &lt;resetValue&gt;0x0&lt;/resetValue&gt; &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; &lt;fields&gt; &lt;field&gt;&lt;name&gt;interruptmask&lt;/name&gt; &lt;description&gt;IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.&lt;/description&gt; &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; &lt;bitWidth&gt;32&lt;/bitWidth&gt; &lt;access&gt;read-write&lt;/access&gt; &lt;/field&gt; &lt;/fields&gt; &lt;/register&gt; &lt;register&gt; &lt;name&gt;EDGE_CAP&lt;/name&gt; &lt;displayName&gt;Edge capture&lt;/displayName&gt; &lt;description&gt;Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.&lt;/description&gt; &lt;addressOffset&gt;0xc&lt;/addressOffset&gt; &lt;size&gt;32&lt;/size&gt; &lt;access&gt;read-write&lt;/access&gt; &lt;resetValue&gt;0x0&lt;/resetValue&gt; &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; &lt;fields&gt; &lt;field&gt;&lt;name&gt;edgecapture&lt;/name&gt; &lt;description&gt;Edge detection for each input port.&lt;/description&gt; &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; &lt;bitWidth&gt;32&lt;/bitWidth&gt; &lt;access&gt;read-write&lt;/access&gt; &lt;/field&gt; &lt;/fields&gt; &lt;/register&gt; &lt;register&gt; &lt;name&gt;SET_BIT&lt;/name&gt; &lt;displayName&gt;Outset&lt;/displayName&gt; &lt;description&gt;You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt; &lt;addressOffset&gt;0x10&lt;/addressOffset&gt; &lt;size&gt;32&lt;/size&gt; &lt;access&gt;write-only&lt;/access&gt; &lt;resetValue&gt;0x0&lt;/resetValue&gt; &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; &lt;fields&gt; &lt;field&gt;&lt;name&gt;outset&lt;/name&gt; &lt;description&gt;Specifies which bit of the output port to set.&lt;/description&gt; &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; &lt;bitWidth&gt;32&lt;/bitWidth&gt; &lt;access&gt;write-only&lt;/access&gt; &lt;/field&gt; &lt;/fields&gt; &lt;/register&gt; &lt;register&gt; &lt;name&gt;CLEAR_BITS&lt;/name&gt; &lt;displayName&gt;Outclear&lt;/displayName&gt; &lt;description&gt;You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt; &lt;addressOffset&gt;0x14&lt;/addressOffset&gt; &lt;size&gt;32&lt;/size&gt; &lt;access&gt;write-only&lt;/access&gt; &lt;resetValue&gt;0x0&lt;/resetValue&gt; &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; &lt;fields&gt; &lt;field&gt;&lt;name&gt;outclear&lt;/name&gt; &lt;description&gt;Specifies which output bit to clear.&lt;/description&gt; &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; &lt;bitWidth&gt;32&lt;/bitWidth&gt; &lt;access&gt;write-only&lt;/access&gt; &lt;/field&gt; &lt;/fields&gt; &lt;/register&gt; &lt;/registers&gt; &lt;/peripheral&gt; &lt;/peripherals&gt; &lt;/device&gt; </cmsisSrcFileContents> <addressGroup></addressGroup> <cmsisVars/> </cmsisInfo> </interface> <interface> <name>external_connection</name> <type>conduit</type> <isStart>false</isStart> <ports> <port> <name>out_port</name> <role>export</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>associatedReset</key> </entry> <entry> <key>prSafe</key> <value>false</value> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> <connPtSystemInfos> <entry> <key>clk</key> <value> <connectionPointName>clk</connectionPointName> <suppliedSystemInfos> <entry> <key>CLOCK_RATE</key> <value>50000000</value> </entry> </suppliedSystemInfos> <consumedSystemInfos/> </value> </entry> <entry> <key>s1</key> <value> <connectionPointName>s1</connectionPointName> <suppliedSystemInfos/> <consumedSystemInfos> <entry> <key>ADDRESS_MAP</key> <value>&lt;address-map&gt;&lt;slave name='s1' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value> </entry> <entry> <key>ADDRESS_WIDTH</key> <value>4</value> </entry> <entry> <key>MAX_SLAVE_DATA_WIDTH</key> <value>32</value> </entry> </consumedSystemInfos> </value> </entry> </connPtSystemInfos> </systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_emif_s10_ddr4_b.ip b/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_emif_s10_ddr4_b.ip new file mode 100644 index 0000000..1a5bd25 --- /dev/null +++ b/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_emif_s10_ddr4_b.ip @@ -0,0 +1,10158 @@ + + + + Intel Corporation + DE10_Pro_QSYS_emif_s10_ddr4_b + DE10_Pro_QSYS_emif_s10_ddr4_b + 19.2.4 + + + local_reset_req + + + + + + + + local_reset_req + + + local_reset_req + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + local_reset_status + + + + + + + + local_reset_done + + + local_reset_done + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + pll_ref_clk + + + + + + + + clk + + + pll_ref_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + oct + + + + + + + + oct_rzqin + + + oct_rzqin + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + mem + + + + + + + + mem_ck + + + mem_ck + + + + + mem_ck_n + + + mem_ck_n + + + + + mem_a + + + mem_a + + + + + mem_act_n + + + mem_act_n + + + + + mem_ba + + + mem_ba + + + + + mem_bg + + + mem_bg + + + + + mem_cke + + + mem_cke + + + + + mem_cs_n + + + mem_cs_n + + + + + mem_odt + + + mem_odt + + + + + mem_reset_n + + + mem_reset_n + + + + + mem_par + + + mem_par + + + + + mem_alert_n + + + mem_alert_n + + + + + mem_dqs + + + mem_dqs + + + + + mem_dqs_n + + + mem_dqs_n + + + + + mem_dq + + + mem_dq + + + + + mem_dbi_n + + + mem_dbi_n + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + status + + + + + + + + local_cal_success + + + local_cal_success + + + + + local_cal_fail + + + local_cal_fail + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + emif_usr_reset_n + + + + + + + + reset_n + + + emif_usr_reset_n + + + + + + + + + associatedClock + Associated clock + + + + associatedDirectReset + Associated direct reset + + + + associatedResetSinks + Associated reset sinks + none + + + synchronousEdges + Synchronous edges + NONE + + + + + emif_usr_clk + + + + + + + + clk + + + emif_usr_clk + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 333333333 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + ctrl_ecc_user_interrupt_0 + + + + + + + + ctrl_ecc_user_interrupt + + + ctrl_ecc_user_interrupt_0 + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + ctrl_amm_0 + + + + + + + + waitrequest_n + + + amm_ready_0 + + + + + read + + + amm_read_0 + + + + + write + + + amm_write_0 + + + + + address + + + amm_address_0 + + + + + readdata + + + amm_readdata_0 + + + + + writedata + + + amm_writedata_0 + + + + + burstcount + + + amm_burstcount_0 + + + + + byteenable + + + amm_byteenable_0 + + + + + readdatavalid + + + amm_readdatavalid_0 + + + + + + + + + addressAlignment + Agent addressing + DYNAMIC + + + addressGroup + Address group + 0 + + + addressSpan + Address span + 8589934592 + + + addressUnits + Address units + WORDS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + emif_usr_clk + + + associatedReset + Associated reset + emif_usr_reset_n + + + bitsPerSymbol + Bits per symbol + 8 + + + bridgedAddressOffset + Bridged Address Offset + 0 + + + bridgesToMaster + Bridges to host + + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + explicitAddressSpan + Explicit address span + 0 + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isBigEndian + Big endian + false + + + isFlash + Flash memory + false + + + isMemoryDevice + Memory device + true + + + isNonVolatileStorage + Non-volatile storage + false + + + linewrapBursts + Linewrap bursts + false + + + maximumPendingReadTransactions + Maximum pending read transactions + 64 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + minimumUninterruptedRunLength + Minimum uninterrupted run length + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + printableDevice + Can receive stdout/stderr + false + + + readLatency + Read latency + 0 + + + readWaitStates + Read wait states + 1 + + + readWaitTime + Read wait + 1 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + transparentBridge + Transparent bridge + false + + + waitrequestAllowance + Waitrequest allowance + 0 + + + wellBehavedWaitrequest + Well-behaved waitrequest + false + + + writeLatency + Write latency + 0 + + + writeWaitStates + Write wait states + 0 + + + writeWaitTime + Write wait + 0 + + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_emif_s10 + + QUARTUS_SYNTH + + + + + + + local_reset_req + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + local_reset_done + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + pll_ref_clk + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + oct_rzqin + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + mem_ck + + out + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_ck_n + + out + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_a + + out + + + 0 + 16 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_act_n + + out + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_ba + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_bg + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_cke + + out + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_cs_n + + out + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_odt + + out + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_reset_n + + out + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_par + + out + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_alert_n + + in + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_dqs + + inout + + + 0 + 8 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_dqs_n + + inout + + + 0 + 8 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_dq + + inout + + + 0 + 71 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_dbi_n + + inout + + + 0 + 8 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + local_cal_success + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + local_cal_fail + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + emif_usr_reset_n + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + emif_usr_clk + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + ctrl_ecc_user_interrupt_0 + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + amm_ready_0 + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + amm_read_0 + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + amm_write_0 + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + amm_address_0 + + in + + + 0 + 26 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + amm_readdata_0 + + out + + + 0 + 511 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + amm_writedata_0 + + in + + + 0 + 511 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + amm_burstcount_0 + + in + + + 0 + 6 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + amm_byteenable_0 + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + amm_readdatavalid_0 + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + DE10_Pro_QSYS_emif_s10_ddr4_b + altera_emif_s10 + 19.2.4 + + + + + SYS_INFO_DEVICE_FAMILY + PARAM_SYS_INFO_DEVICE_FAMILY_NAME + Stratix 10 + + + SYS_INFO_DEVICE + PARAM_SYS_INFO_DEVICE_NAME + 1SX280HU2F50E1VG + + + SYS_INFO_DEVICE_SPEEDGRADE + PARAM_SYS_INFO_DEVICE_SPEEDGRADE_NAME + 1 + + + SYS_INFO_DEVICE_TEMPERATURE_GRADE + PARAM_SYS_INFO_DEVICE_TEMPERATURE_GRADE_NAME + EXTENDED + + + SYS_INFO_DEVICE_POWER_MODEL + PARAM_SYS_INFO_DEVICE_POWER_MODEL_NAME + SMART_VID + + + SYS_INFO_DEVICE_DIE_REVISIONS + PARAM_SYS_INFO_DEVICE_DIE_REVISIONS_NAME + HSSI_CRETE2E_REVB,MAIN_ND5_REVC + + + TRAIT_SUPPORTS_VID + PARAM_TRAIT_SUPPORTS_VID_NAME + 1 + + + TRAIT_IOBANK_REVISION + PARAM_TRAIT_IOBANK_REVISION_NAME + + + + PROTOCOL_ENUM + Protocol + PROTOCOL_DDR4 + + + IS_ED_SLAVE + PARAM_IS_ED_SLAVE_NAME + false + + + INTERNAL_TESTING_MODE + PARAM_INTERNAL_TESTING_MODE_NAME + false + + + CAL_DEBUG_CLOCK_FREQUENCY + PARAM_CAL_DEBUG_CLOCK_FREQUENCY_NAME + 50000000 + + + SYS_INFO_UNIQUE_ID + PARAM_SYS_INFO_UNIQUE_ID_NAME + DE10_Pro_QSYS_emif_s10_ddr4_b_DE10_Pro_QSYS_emif_s10_ddr4_b + + + PLL_ADD_EXTRA_CLKS + Specify additional core clocks based on existing PLL + false + + + PLL_USER_NUM_OF_EXTRA_CLKS + Number of additional core clocks + 0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_0 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_0 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_1 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_1 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_2 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_2 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_3 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_3 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_4 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_4 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8_NAME + 50.0 + + + PHY_DDR3_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_HARD_CTRL + + + PHY_DDR3_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_DDR3_MEM_CLK_FREQ_MHZ + Memory clock frequency + 1066.667 + + + PHY_DDR3_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_DDR3_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_DDR3_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_DDR3_RATE_ENUM + Clock rate of user logic + RATE_QUARTER + + + PHY_DDR3_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_DDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_DDR3_IO_VOLTAGE + Voltage + 1.5 + + + PHY_DDR3_DEFAULT_IO + Use default I/O settings + true + + + PHY_DDR3_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDR3_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + false + + + PHY_DDR3_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_DDR3_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_DDR3_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_DDR3_USER_AC_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_DDR3_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDR3_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_DDR3_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_DDR3_USER_CK_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_DDR3_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDR3_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_DDR3_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_DDR3_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_DDR3_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDR3_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_DDR3_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_DDR3_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_DDR3_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + PHY_DDR3_CAL_ADDR0 + PARAM_PHY_DDR3_CAL_ADDR0_NAME + 0 + + + PHY_DDR3_CAL_ADDR1 + PARAM_PHY_DDR3_CAL_ADDR1_NAME + 8 + + + PHY_DDR3_CAL_ENABLE_NON_DES + PARAM_PHY_DDR3_CAL_ENABLE_NON_DES_NAME + false + + + PHY_DDR4_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_HARD_CTRL + + + PHY_DDR4_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_DDR4_USER_CLAMSHELL_EN + Use clamshell layout + false + + + PHY_DDR4_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + false + + + PHY_DDR4_MEM_CLK_FREQ_MHZ + Memory clock frequency + 1333.333333 + + + PHY_DDR4_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_DDR4_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_DDR4_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_DDR4_RATE_ENUM + Clock rate of user logic + RATE_QUARTER + + + PHY_DDR4_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_DDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_DDR4_IO_VOLTAGE + Voltage + 1.2 + + + PHY_DDR4_DEFAULT_IO + Use default I/O settings + false + + + PHY_DDR4_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDR4_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_DDR4_USER_AC_IO_STD_ENUM + I/O standard + IO_STD_SSTL_12 + + + PHY_DDR4_USER_AC_MODE_ENUM + Output mode + OUT_OCT_40_CAL + + + PHY_DDR4_USER_AC_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_DDR4_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDR4_USER_CK_IO_STD_ENUM + I/O standard + IO_STD_SSTL_12 + + + PHY_DDR4_USER_CK_MODE_ENUM + Output mode + OUT_OCT_40_CAL + + + PHY_DDR4_USER_CK_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_DDR4_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDR4_USER_DATA_IO_STD_ENUM + I/O standard + IO_STD_POD_12 + + + PHY_DDR4_USER_DATA_OUT_MODE_ENUM + Output mode + OUT_OCT_34_CAL + + + PHY_DDR4_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_DDR4_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDR4_USER_DATA_IN_MODE_ENUM + Input mode + IN_OCT_48_CAL + + + PHY_DDR4_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_DDR4_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + IO_STD_LVDS_NO_OCT + + + PHY_DDR4_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + IO_STD_CMOS_12 + + + PHY_QDR2_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_QDR2_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_QDR2_MEM_CLK_FREQ_MHZ + Memory clock frequency + 633.333 + + + PHY_QDR2_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_QDR2_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_QDR2_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_QDR2_RATE_ENUM + Clock rate of user logic + RATE_HALF + + + PHY_QDR2_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_QDR2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_QDR2_IO_VOLTAGE + Voltage + 1.5 + + + PHY_QDR2_DEFAULT_IO + Use default I/O settings + true + + + PHY_QDR2_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_QDR2_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + false + + + PHY_QDR2_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_QDR2_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_QDR2_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_QDR2_USER_AC_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_QDR2_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_QDR2_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_QDR2_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_QDR2_USER_CK_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_QDR2_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_QDR2_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_QDR2_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_QDR2_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_QDR2_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_QDR2_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_QDR2_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_QDR2_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_QDR2_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + PHY_QDR4_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_QDR4_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_QDR4_MEM_CLK_FREQ_MHZ + Memory clock frequency + 1066.667 + + + PHY_QDR4_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_QDR4_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_QDR4_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_QDR4_RATE_ENUM + Clock rate of user logic + RATE_QUARTER + + + PHY_QDR4_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_QDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_QDR4_IO_VOLTAGE + Voltage + 1.2 + + + PHY_QDR4_DEFAULT_IO + Use default I/O settings + true + + + PHY_QDR4_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_QDR4_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + false + + + PHY_QDR4_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_QDR4_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_QDR4_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_QDR4_USER_AC_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_QDR4_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_QDR4_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_QDR4_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_QDR4_USER_CK_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_QDR4_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_QDR4_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_QDR4_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_QDR4_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_QDR4_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_QDR4_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_QDR4_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_QDR4_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_QDR4_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + PHY_RLD2_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_RLD2_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_RLD2_MEM_CLK_FREQ_MHZ + Memory clock frequency + 533.333 + + + PHY_RLD2_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_RLD2_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_RLD2_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_RLD2_RATE_ENUM + Clock rate of user logic + RATE_HALF + + + PHY_RLD2_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_RLD2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_RLD2_IO_VOLTAGE + Voltage + 1.8 + + + PHY_RLD2_DEFAULT_IO + Use default I/O settings + true + + + PHY_RLD2_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_RLD2_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + false + + + PHY_RLD2_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_RLD2_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_RLD2_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_RLD2_USER_AC_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_RLD2_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_RLD2_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_RLD2_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_RLD2_USER_CK_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_RLD2_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_RLD2_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_RLD2_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_RLD2_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_RLD2_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_RLD2_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_RLD2_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_RLD2_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_RLD2_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + PHY_RLD3_CONFIG_ENUM + Configuration + CONFIG_PHY_ONLY + + + PHY_RLD3_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_RLD3_MEM_CLK_FREQ_MHZ + Memory clock frequency + 1066.667 + + + PHY_RLD3_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_RLD3_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_RLD3_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_RLD3_RATE_ENUM + Clock rate of user logic + RATE_QUARTER + + + PHY_RLD3_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_RLD3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_RLD3_IO_VOLTAGE + Voltage + 1.2 + + + PHY_RLD3_DEFAULT_IO + Use default I/O settings + true + + + PHY_RLD3_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_RLD3_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + false + + + PHY_RLD3_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_RLD3_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_RLD3_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_RLD3_USER_AC_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_RLD3_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_RLD3_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_RLD3_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_RLD3_USER_CK_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_RLD3_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_RLD3_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_RLD3_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_RLD3_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_RLD3_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_RLD3_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_RLD3_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_RLD3_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_RLD3_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + PHY_LPDDR3_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_HARD_CTRL + + + PHY_LPDDR3_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_LPDDR3_MEM_CLK_FREQ_MHZ + Memory clock frequency + 800.0 + + + PHY_LPDDR3_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_LPDDR3_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_LPDDR3_RATE_ENUM + Clock rate of user logic + RATE_QUARTER + + + PHY_LPDDR3_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_LPDDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_LPDDR3_IO_VOLTAGE + Voltage + 1.2 + + + PHY_LPDDR3_DEFAULT_IO + Use default I/O settings + true + + + PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_LPDDR3_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + false + + + PHY_LPDDR3_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_LPDDR3_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_LPDDR3_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_LPDDR3_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_LPDDR3_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_LPDDR3_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_LPDDR3_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_LPDDR3_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_LPDDR3_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_LPDDR3_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_LPDDR3_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_LPDDR3_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_LPDDR3_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_LPDDR3_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + PHY_DDRT_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_DDRT_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_DDRT_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + false + + + PHY_DDRT_MEM_CLK_FREQ_MHZ + Memory clock frequency + 1200.0 + + + PHY_DDRT_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_DDRT_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_DDRT_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_DDRT_RATE_ENUM + Clock rate of user logic + RATE_QUARTER + + + PHY_DDRT_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_DDRT_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_DDRT_IO_VOLTAGE + Voltage + 1.2 + + + PHY_DDRT_DEFAULT_IO + Use default I/O settings + true + + + PHY_DDRT_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_DDRT_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDRT_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_DDRT_IC_EN + Enable I2C Master + true + + + PHY_DDRT_2CH_EN + Enable 2 Channel + false + + + PHY_DDRT_USE_OLD_SMBUS_MULTICOL + Enable I2C Multicolumn + false + + + PHY_DDRT_EXPORT_CLK_STP_IF + Export Clock Stop Interface + false + + + PHY_DDRT_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_DDRT_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_DDRT_USER_AC_IN_MODE_ENUM + Input mode + unset + + + PHY_DDRT_USER_AC_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_DDRT_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDRT_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_DDRT_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_DDRT_USER_CK_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_DDRT_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDRT_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_DDRT_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_DDRT_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_DDRT_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDRT_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_DDRT_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_DDRT_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_DDRT_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_DDRT_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + MEM_DDR3_FORMAT_ENUM + Memory format + MEM_FORMAT_UDIMM + + + MEM_DDR3_DQ_WIDTH + DQ width + 72 + + + MEM_DDR3_DQ_PER_DQS + DQ pins per DQS group + 8 + + + MEM_DDR3_DISCRETE_CS_WIDTH + Number of chip selects + 1 + + + MEM_DDR3_NUM_OF_DIMMS + Number of DIMMs + 1 + + + MEM_DDR3_RANKS_PER_DIMM + Number of physical ranks per DIMM + 1 + + + MEM_DDR3_CKE_PER_DIMM + Number of clock enables per DIMM + 1 + + + MEM_DDR3_CK_WIDTH + Number of clocks + 1 + + + MEM_DDR3_ROW_ADDR_WIDTH + Row address width + 15 + + + MEM_DDR3_COL_ADDR_WIDTH + Column address width + 10 + + + MEM_DDR3_BANK_ADDR_WIDTH + Bank address width + 3 + + + MEM_DDR3_DM_EN + Enable DM pins + true + + + MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN + Enable address mirroring for odd chip-selects + false + + + MEM_DDR3_MIRROR_ADDRESSING_EN + Enable address mirroring for odd ranks + true + + + MEM_DDR3_HIDE_ADV_MR_SETTINGS + Hide advanced mode register settings + true + + + MEM_DDR3_RDIMM_CONFIG + DDR3 RDIMM/LRDIMM control words + 0000000000000000 + + + MEM_DDR3_LRDIMM_EXTENDED_CONFIG + DDR3 LRDIMM additional control words + 000000000000000000 + + + MEM_DDR3_ALERT_N_PLACEMENT_ENUM + ALERT# pin placement + DDR3_ALERT_N_PLACEMENT_AC_LANES + + + MEM_DDR3_ALERT_N_DQS_GROUP + DQS group of ALERT# + 0 + + + MEM_DDR3_BL_ENUM + Burst Length + DDR3_BL_BL8 + + + MEM_DDR3_BT_ENUM + Read Burst Type + DDR3_BT_SEQUENTIAL + + + MEM_DDR3_ASR_ENUM + Auto self-refresh method + DDR3_ASR_MANUAL + + + MEM_DDR3_SRT_ENUM + Self-refresh temperature + DDR3_SRT_NORMAL + + + MEM_DDR3_PD_ENUM + DLL precharge power down + DDR3_PD_OFF + + + MEM_DDR3_DRV_STR_ENUM + Output drive strength setting + DDR3_DRV_STR_RZQ_7 + + + MEM_DDR3_DLL_EN + Enable the DLL in memory device + true + + + MEM_DDR3_RTT_NOM_ENUM + ODT Rtt nominal value + DDR3_RTT_NOM_ODT_DISABLED + + + MEM_DDR3_RTT_WR_ENUM + Dynamic ODT (Rtt_WR) value + DDR3_RTT_WR_RZQ_4 + + + MEM_DDR3_WTCL + Memory write CAS latency setting + 10 + + + MEM_DDR3_ATCL_ENUM + Memory additive CAS latency setting + DDR3_ATCL_DISABLED + + + MEM_DDR3_TCL + Memory CAS latency setting + 14 + + + MEM_DDR3_USE_DEFAULT_ODT + Use Default ODT Assertion Tables + true + + + MEM_DDR3_R_ODTN_1X1 + Read Target + Rank 0 + + + MEM_DDR3_R_ODT0_1X1 + ODT0 + off + + + MEM_DDR3_W_ODTN_1X1 + Write Target + Rank 0 + + + MEM_DDR3_W_ODT0_1X1 + ODT0 + on + + + MEM_DDR3_R_ODTN_2X2 + Read Target + Rank 0,Rank 1 + + + MEM_DDR3_R_ODT0_2X2 + ODT0 + off,off + + + MEM_DDR3_R_ODT1_2X2 + ODT1 + off,off + + + MEM_DDR3_W_ODTN_2X2 + Write Target + Rank 0,Rank 1 + + + MEM_DDR3_W_ODT0_2X2 + ODT0 + on,off + + + MEM_DDR3_W_ODT1_2X2 + ODT1 + off,on + + + MEM_DDR3_R_ODTN_4X2 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_R_ODT0_4X2 + ODT0 + off,off,on,on + + + MEM_DDR3_R_ODT1_4X2 + ODT1 + on,on,off,off + + + MEM_DDR3_W_ODTN_4X2 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_W_ODT0_4X2 + ODT0 + off,off,on,on + + + MEM_DDR3_W_ODT1_4X2 + ODT1 + on,on,off,off + + + MEM_DDR3_R_ODTN_4X4 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_R_ODT0_4X4 + ODT0 + off,off,off,off + + + MEM_DDR3_R_ODT1_4X4 + ODT1 + off,off,on,on + + + MEM_DDR3_R_ODT2_4X4 + ODT2 + off,off,off,off + + + MEM_DDR3_R_ODT3_4X4 + ODT3 + on,on,off,off + + + MEM_DDR3_W_ODTN_4X4 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_W_ODT0_4X4 + ODT0 + on,on,off,off + + + MEM_DDR3_W_ODT1_4X4 + ODT1 + off,off,on,on + + + MEM_DDR3_W_ODT2_4X4 + ODT2 + off,off,on,on + + + MEM_DDR3_W_ODT3_4X4 + ODT3 + on,on,off,off + + + MEM_DDR3_SPEEDBIN_ENUM + Speed bin + DDR3_SPEEDBIN_2133 + + + MEM_DDR3_TIS_PS + tIS (base) + 60 + + + MEM_DDR3_TIS_AC_MV + tIS (base) AC level + 135 + + + MEM_DDR3_TIH_PS + tIH (base) + 95 + + + MEM_DDR3_TIH_DC_MV + tIH (base) DC level + 100 + + + MEM_DDR3_TDS_PS + tDS (base) + 53 + + + MEM_DDR3_TDS_AC_MV + tDS (base) AC level + 135 + + + MEM_DDR3_TDH_PS + tDH (base) + 55 + + + MEM_DDR3_TDH_DC_MV + tDH (base) DC level + 100 + + + MEM_DDR3_TDQSQ_PS + tDQSQ + 75 + + + MEM_DDR3_TQH_CYC + tQH + 0.38 + + + MEM_DDR3_TDQSCK_PS + tDQSCK + 180 + + + MEM_DDR3_TDQSS_CYC + tDQSS + 0.27 + + + MEM_DDR3_TQSH_CYC + tQSH + 0.4 + + + MEM_DDR3_TDSH_CYC + tDSH + 0.18 + + + MEM_DDR3_TWLS_PS + tWLS + 125.0 + + + MEM_DDR3_TWLH_PS + tWLH + 125.0 + + + MEM_DDR3_TDSS_CYC + tDSS + 0.18 + + + MEM_DDR3_TINIT_US + tINIT + 500 + + + MEM_DDR3_TMRD_CK_CYC + tMRD + 4 + + + MEM_DDR3_TRAS_NS + tRAS + 33.0 + + + MEM_DDR3_TRCD_NS + tRCD + 13.09 + + + MEM_DDR3_TRP_NS + tRP + 13.09 + + + MEM_DDR3_TREFI_US + tREFI + 7.8 + + + MEM_DDR3_TRFC_NS + tRFC + 160.0 + + + MEM_DDR3_TWR_NS + tWR + 15.0 + + + MEM_DDR3_TWTR_CYC + tWTR + 8 + + + MEM_DDR3_TFAW_NS + tFAW + 25.0 + + + MEM_DDR3_TRRD_CYC + tRRD + 6 + + + MEM_DDR3_TRTP_CYC + tRTP + 8 + + + MEM_DDR3_CFG_GEN_SBE + PARAM_MEM_DDR3_CFG_GEN_SBE_NAME + false + + + MEM_DDR3_CFG_GEN_DBE + PARAM_MEM_DDR3_CFG_GEN_DBE_NAME + false + + + MEM_DDR4_FORMAT_ENUM + Memory format + MEM_FORMAT_SODIMM + + + MEM_DDR4_DQ_WIDTH + DQ width + 72 + + + MEM_DDR4_DQ_PER_DQS + DQ pins per DQS group + 8 + + + MEM_DDR4_DISCRETE_CS_WIDTH + Number of chip selects + 1 + + + MEM_DDR4_NUM_OF_DIMMS + Number of DIMMs + 1 + + + MEM_DDR4_CHIP_ID_WIDTH + Chip ID width + 0 + + + MEM_DDR4_RANKS_PER_DIMM + Number of physical ranks per DIMM + 1 + + + MEM_DDR4_CKE_PER_DIMM + Number of clock enables per DIMM + 1 + + + MEM_DDR4_CK_WIDTH + Number of clocks + 1 + + + MEM_DDR4_ROW_ADDR_WIDTH + Row address width + 16 + + + MEM_DDR4_COL_ADDR_WIDTH + Column address width + 10 + + + MEM_DDR4_BANK_ADDR_WIDTH + Bank address width + 2 + + + MEM_DDR4_BANK_GROUP_WIDTH + Bank group width + 2 + + + MEM_DDR4_DM_EN + Data mask + true + + + MEM_DDR4_ALERT_PAR_EN + Enable ALERT#/PAR pins + true + + + MEM_DDR4_ALERT_N_PLACEMENT_ENUM + ALERT# pin placement + DDR4_ALERT_N_PLACEMENT_DATA_LANES + + + MEM_DDR4_ALERT_N_DQS_GROUP + DQS group of ALERT# + 0 + + + MEM_DDR4_ALERT_N_AC_LANE + Address/command I/O lane of ALERT# + 0 + + + MEM_DDR4_ALERT_N_AC_PIN + Pin index of ALERT# + 0 + + + MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN + Enable address mirroring for odd chip-selects + false + + + MEM_DDR4_MIRROR_ADDRESSING_EN + Enable address mirroring for odd ranks + true + + + MEM_DDR4_HIDE_ADV_MR_SETTINGS + Hide advanced mode register settings + false + + + MEM_DDR4_INTEL_DEFAULT_TERM + Use Default Memory I/O Settings + true + + + MEM_DDR4_BL_ENUM + Burst Length + DDR4_BL_BL8 + + + MEM_DDR4_BT_ENUM + Read Burst Type + DDR4_BT_SEQUENTIAL + + + MEM_DDR4_TCL + Memory CAS latency setting + 22 + + + MEM_DDR4_RTT_NOM_ENUM + ODT Rtt nominal value + DDR4_RTT_NOM_RZQ_5 + + + MEM_DDR4_DLL_EN + Enable the DLL in memory device + true + + + MEM_DDR4_ATCL_ENUM + Memory additive CAS latency setting + DDR4_ATCL_DISABLED + + + MEM_DDR4_DRV_STR_ENUM + Output drive strength setting + DDR4_DRV_STR_RZQ_7 + + + MEM_DDR4_ASR_ENUM + Auto self-refresh method + DDR4_ASR_MANUAL_NORMAL + + + MEM_DDR4_RTT_WR_ENUM + Dynamic ODT (Rtt_WR) value + DDR4_RTT_WR_ODT_DISABLED + + + MEM_DDR4_WTCL + Memory write CAS latency setting + 18 + + + MEM_DDR4_WRITE_CRC + Write CRC enable + false + + + MEM_DDR4_GEARDOWN + DDR4 geardown mode + DDR4_GEARDOWN_HR + + + MEM_DDR4_PER_DRAM_ADDR + Per-DRAM addressability + false + + + MEM_DDR4_TEMP_SENSOR_READOUT + Temperature sensor readout + false + + + MEM_DDR4_FINE_GRANULARITY_REFRESH + Fine granularity refresh + DDR4_FINE_REFRESH_FIXED_1X + + + MEM_DDR4_MPR_READ_FORMAT + MPR read format + DDR4_MPR_READ_FORMAT_SERIAL + + + MEM_DDR4_MAX_POWERDOWN + Maximum power down mode + false + + + MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE + Temperature controlled refresh range + DDR4_TEMP_CONTROLLED_RFSH_NORMAL + + + MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA + Temperature controlled refresh enable + false + + + MEM_DDR4_INTERNAL_VREFDQ_MONITOR + Internal VrefDQ monitor + false + + + MEM_DDR4_CAL_MODE + CS to Addr/CMD Latency + 0 + + + MEM_DDR4_SELF_RFSH_ABORT + Self refresh abort + false + + + MEM_DDR4_READ_PREAMBLE_TRAINING + Read preamble training mode enable + false + + + MEM_DDR4_READ_PREAMBLE + Read preamble + 2 + + + MEM_DDR4_WRITE_PREAMBLE + Write preamble + 1 + + + MEM_DDR4_AC_PARITY_LATENCY + Addr/CMD parity latency + DDR4_AC_PARITY_LATENCY_DISABLE + + + MEM_DDR4_ODT_IN_POWERDOWN + ODT input buffer during powerdown mode + true + + + MEM_DDR4_RTT_PARK + RTT PARK + DDR4_RTT_PARK_ODT_DISABLED + + + MEM_DDR4_AC_PERSISTENT_ERROR + Addr/CMD persistent error + false + + + MEM_DDR4_WRITE_DBI + Write DBI + false + + + MEM_DDR4_READ_DBI + Read DBI + true + + + MEM_DDR4_DEFAULT_VREFOUT + Use recommended initial VrefDQ value + true + + + MEM_DDR4_USER_VREFDQ_TRAINING_VALUE + VrefDQ training value + 56.0 + + + MEM_DDR4_USER_VREFDQ_TRAINING_RANGE + VrefDQ training range + DDR4_VREFDQ_TRAINING_RANGE_1 + + + MEM_DDR4_RCD_CA_IBT_ENUM + RCD CA Input Bus Termination + DDR4_RCD_CA_IBT_100 + + + MEM_DDR4_RCD_CS_IBT_ENUM + RCD DCS[3:0]_n Input Bus Termination + DDR4_RCD_CS_IBT_100 + + + MEM_DDR4_RCD_CKE_IBT_ENUM + RCD DCKE Input Bus Termination + DDR4_RCD_CKE_IBT_100 + + + MEM_DDR4_RCD_ODT_IBT_ENUM + RCD DODT Input Bus Termination + DDR4_RCD_ODT_IBT_100 + + + MEM_DDR4_DB_RTT_NOM_ENUM + DB Host Interface DQ RTT_NOM + DDR4_DB_RTT_NOM_ODT_DISABLED + + + MEM_DDR4_DB_RTT_WR_ENUM + DB Host Interface DQ RTT_WR + DDR4_DB_RTT_WR_RZQ_3 + + + MEM_DDR4_DB_RTT_PARK_ENUM + DB Host Interface DQ RTT_PARK + DDR4_DB_RTT_PARK_ODT_DISABLED + + + MEM_DDR4_DB_DQ_DRV_ENUM + DB Host Interface DQ Driver + DDR4_DB_DRV_STR_RZQ_7 + + + MEM_DDR4_SPD_137_RCD_CA_DRV + SPD Byte 137 - RCD Drive Strength for Command/Address + 101 + + + MEM_DDR4_SPD_138_RCD_CK_DRV + SPD Byte 138 - RCD Drive Strength for CK + 5 + + + MEM_DDR4_SPD_140_DRAM_VREFDQ_R0 + SPD Byte 140 - DRAM VrefDQ for Package Rank 0 + 29 + + + MEM_DDR4_SPD_141_DRAM_VREFDQ_R1 + SPD Byte 141 - DRAM VrefDQ for Package Rank 1 + 29 + + + MEM_DDR4_SPD_142_DRAM_VREFDQ_R2 + SPD Byte 142 - DRAM VrefDQ for Package Rank 2 + 29 + + + MEM_DDR4_SPD_143_DRAM_VREFDQ_R3 + SPD Byte 143 - DRAM VrefDQ for Package Rank 3 + 29 + + + MEM_DDR4_SPD_144_DB_VREFDQ + SPD Byte 144 - DB VrefDQ for DRAM Interface + 37 + + + MEM_DDR4_SPD_145_DB_MDQ_DRV + SPD Byte 145-147 - DB MDQ Drive Strength and RTT + 21 + + + MEM_DDR4_SPD_148_DRAM_DRV + SPD Byte 148 - DRAM Drive Strength + 0 + + + MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM + SPD Byte 149-151 - DRAM ODT (RTT_WR and RTT_NOM) + 20 + + + MEM_DDR4_SPD_152_DRAM_RTT_PARK + SPD Byte 152-154 - DRAM ODT (RTT_PARK) + 39 + + + MEM_DDR4_SPD_155_DB_VREFDQ_RANGE + SPD Byte 155 - DB VrefDQ for DRAM Interface Range + 0 + + + MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB + RCD and DB Manufacturer (LSB) + 0 + + + MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB + RCD and DB Manufacturer (MSB) + 0 + + + MEM_DDR4_SPD_135_RCD_REV + RCD Revision Number + 0 + + + MEM_DDR4_SPD_139_DB_REV + DB Revision Number + 0 + + + MEM_DDR4_LRDIMM_ODT_LESS_BS + PARAM_MEM_DDR4_LRDIMM_ODT_LESS_BS_NAME + true + + + MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM + PARAM_MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM_NAME + 240 + + + MEM_DDR4_USE_DEFAULT_ODT + Use Default ODT Assertion Tables + true + + + MEM_DDR4_R_ODTN_1X1 + Read Target + Rank 0 + + + MEM_DDR4_R_ODT0_1X1 + ODT0 + off + + + MEM_DDR4_W_ODTN_1X1 + Write Target + Rank 0 + + + MEM_DDR4_W_ODT0_1X1 + ODT0 + on + + + MEM_DDR4_R_ODTN_2X2 + Read Target + Rank 0,Rank 1 + + + MEM_DDR4_R_ODT0_2X2 + ODT0 + off,off + + + MEM_DDR4_R_ODT1_2X2 + ODT1 + off,off + + + MEM_DDR4_W_ODTN_2X2 + Write Target + Rank 0,Rank 1 + + + MEM_DDR4_W_ODT0_2X2 + ODT0 + on,off + + + MEM_DDR4_W_ODT1_2X2 + ODT1 + off,on + + + MEM_DDR4_R_ODTN_4X2 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_R_ODT0_4X2 + ODT0 + off,off,on,on + + + MEM_DDR4_R_ODT1_4X2 + ODT1 + on,on,off,off + + + MEM_DDR4_W_ODTN_4X2 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_W_ODT0_4X2 + ODT0 + off,off,on,on + + + MEM_DDR4_W_ODT1_4X2 + ODT1 + on,on,off,off + + + MEM_DDR4_R_ODTN_4X4 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_R_ODT0_4X4 + ODT0 + off,off,off,off + + + MEM_DDR4_R_ODT1_4X4 + ODT1 + off,off,on,on + + + MEM_DDR4_R_ODT2_4X4 + ODT2 + off,off,off,off + + + MEM_DDR4_R_ODT3_4X4 + ODT3 + on,on,off,off + + + MEM_DDR4_W_ODTN_4X4 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_W_ODT0_4X4 + ODT0 + on,on,off,off + + + MEM_DDR4_W_ODT1_4X4 + ODT1 + off,off,on,on + + + MEM_DDR4_W_ODT2_4X4 + ODT2 + off,off,on,on + + + MEM_DDR4_W_ODT3_4X4 + ODT3 + on,on,off,off + + + MEM_DDR4_SPEEDBIN_ENUM + Speed bin + DDR4_SPEEDBIN_2666 + + + MEM_DDR4_TIS_PS + tIS (base) + 60 + + + MEM_DDR4_TIS_AC_MV + tIS (base) AC level + 100 + + + MEM_DDR4_TIH_PS + tIH (base) + 95 + + + MEM_DDR4_TIH_DC_MV + tIH (base) DC level + 75 + + + MEM_DDR4_TDIVW_TOTAL_UI + TdiVW_total + 0.22 + + + MEM_DDR4_VDIVW_TOTAL + VdiVW_total + 120 + + + MEM_DDR4_TDQSQ_UI + tDQSQ + 0.18 + + + MEM_DDR4_TQH_UI + tQH + 0.74 + + + MEM_DDR4_TDVWP_UI + tDVWp + 0.72 + + + MEM_DDR4_TDQSCK_PS + tDQSCK + 170 + + + MEM_DDR4_TDQSS_CYC + tDQSS + 0.27 + + + MEM_DDR4_TQSH_CYC + tQSH + 0.4 + + + MEM_DDR4_TDSH_CYC + tDSH + 0.18 + + + MEM_DDR4_TDSS_CYC + tDSS + 0.18 + + + MEM_DDR4_TWLS_CYC + tWLS + 0.13 + + + MEM_DDR4_TWLH_CYC + tWLH + 0.13 + + + MEM_DDR4_TINIT_US + tINIT + 500 + + + MEM_DDR4_TMRD_CK_CYC + tMRD + 8 + + + MEM_DDR4_TRAS_NS + tRAS + 32.0 + + + MEM_DDR4_TRCD_NS + tRCD + 14.25 + + + MEM_DDR4_TRP_NS + tRP + 14.25 + + + MEM_DDR4_TREFI_US + tREFI + 7.8 + + + MEM_DDR4_TRFC_NS + tRFC + 350.0 + + + MEM_DDR4_TWR_NS + tWR + 15.0 + + + MEM_DDR4_TWTR_L_CYC + tWTR_L + 10 + + + MEM_DDR4_TWTR_S_CYC + tWTR_S + 4 + + + MEM_DDR4_TFAW_NS + tFAW + 21.0 + + + MEM_DDR4_TRRD_L_CYC + tRRD_L + 7 + + + MEM_DDR4_TRRD_S_CYC + tRRD_S + 4 + + + MEM_DDR4_TCCD_L_CYC + tCCD_L + 7 + + + MEM_DDR4_TCCD_S_CYC + tCCD_S + 4 + + + MEM_DDR4_TRFC_DLR_NS + tRFC_dlr + 90.0 + + + MEM_DDR4_TFAW_DLR_CYC + tFAW_dlr + 16 + + + MEM_DDR4_TRRD_DLR_CYC + tRRD_dlr + 4 + + + MEM_DDR4_TDIVW_DJ_CYC + PARAM_MEM_DDR4_TDIVW_DJ_CYC_NAME + 0.1 + + + MEM_DDR4_TDQSQ_PS + PARAM_MEM_DDR4_TDQSQ_PS_NAME + 66 + + + MEM_DDR4_TQH_CYC + PARAM_MEM_DDR4_TQH_CYC_NAME + 0.38 + + + MEM_DDR4_CFG_GEN_SBE + PARAM_MEM_DDR4_CFG_GEN_SBE_NAME + false + + + MEM_DDR4_CFG_GEN_DBE + PARAM_MEM_DDR4_CFG_GEN_DBE_NAME + false + + + MEM_DDR4_LRDIMM_VREFDQ_VALUE + PARAM_MEM_DDR4_LRDIMM_VREFDQ_VALUE_NAME + + + + MEM_DDR4_TWLS_PS + PARAM_MEM_DDR4_TWLS_PS_NAME + 0.0 + + + MEM_DDR4_TWLH_PS + PARAM_MEM_DDR4_TWLH_PS_NAME + 0.0 + + + MEM_QDR2_WIDTH_EXPANDED + Enable width expansion + false + + + MEM_QDR2_DATA_PER_DEVICE + Data width per device + 36 + + + MEM_QDR2_ADDR_WIDTH + Address width + 19 + + + MEM_QDR2_BWS_EN + Enable BWS# pins + true + + + MEM_QDR2_BL + Burst length + 4 + + + MEM_QDR2_SPEEDBIN_ENUM + Speed bin + QDR2_SPEEDBIN_633 + + + MEM_QDR2_TRL_CYC + tRL + 2.5 + + + MEM_QDR2_TSA_NS + tSA + 0.23 + + + MEM_QDR2_THA_NS + tHA + 0.18 + + + MEM_QDR2_TSD_NS + tSD + 0.23 + + + MEM_QDR2_THD_NS + tHD + 0.18 + + + MEM_QDR2_TCQD_NS + tCQD + 0.09 + + + MEM_QDR2_TCQDOH_NS + tCQDOH + -0.09 + + + MEM_QDR2_INTERNAL_JITTER_NS + Internal Jitter + 0.08 + + + MEM_QDR2_TCQH_NS + tCQH + 0.71 + + + MEM_QDR2_TCCQO_NS + tCCQO + 0.45 + + + MEM_QDR4_WIDTH_EXPANDED + Enable width expansion + false + + + MEM_QDR4_DQ_PER_PORT_PER_DEVICE + DQ width per device + 36 + + + MEM_QDR4_ADDR_WIDTH + Address width + 21 + + + MEM_QDR4_SKIP_ODT_SWEEPING + Skip automatic optimization of Clock and Address/Command ODT setting during calibration + true + + + MEM_QDR4_CK_ODT_MODE_ENUM + ODT (Clock) + QDR4_ODT_25_PCT + + + MEM_QDR4_AC_ODT_MODE_ENUM + ODT (Address/Command) + QDR4_ODT_25_PCT + + + MEM_QDR4_DATA_ODT_MODE_ENUM + ODT (Data) + QDR4_ODT_25_PCT + + + MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM + Output drive (pull-up) + QDR4_OUTPUT_DRIVE_25_PCT + + + MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM + Output drive (pull-down) + QDR4_OUTPUT_DRIVE_25_PCT + + + MEM_QDR4_MEM_TYPE_ENUM + Memory Type + MEM_XP + + + MEM_QDR4_DATA_INV_ENA + Data bus inversion + true + + + MEM_QDR4_ADDR_INV_ENA + Address bus inversion + false + + + MEM_QDR4_USE_ADDR_PARITY + Use address parity bit + false + + + MEM_QDR4_SPEEDBIN_ENUM + Speed bin + QDR4_SPEEDBIN_2133 + + + MEM_QDR4_TISH_PS + tISH + 150 + + + MEM_QDR4_TQKQ_MAX_PS + tQKQ_max + 75 + + + MEM_QDR4_TQH_CYC + tQH + 0.4 + + + MEM_QDR4_TCKDK_MAX_PS + tCKDK_max + 150 + + + MEM_QDR4_TCKDK_MIN_PS + tCKDK_min + -150 + + + MEM_QDR4_TCKQK_MAX_PS + tCKQK_max + 225 + + + MEM_QDR4_TASH_PS + tASH + 170 + + + MEM_QDR4_TCSH_PS + tCSH + 170 + + + MEM_RLD2_WIDTH_EXPANDED + Enable width expansion + false + + + MEM_RLD2_DQ_PER_DEVICE + DQ width per device + 9 + + + MEM_RLD2_ADDR_WIDTH + Address width + 21 + + + MEM_RLD2_BANK_ADDR_WIDTH + Bank address width + 3 + + + MEM_RLD2_DM_EN + Enable DM pins + true + + + MEM_RLD2_BL + Burst length + 4 + + + MEM_RLD2_CONFIG_ENUM + Configuration + RLD2_CONFIG_TRC_8_TRL_8_TWL_9 + + + MEM_RLD2_DRIVE_IMPEDENCE_ENUM + Drive Impedance + RLD2_DRIVE_IMPEDENCE_INTERNAL_50 + + + MEM_RLD2_ODT_MODE_ENUM + On-Die Termination + RLD2_ODT_ON + + + MEM_RLD2_SPEEDBIN_ENUM + Speed bin + RLD2_SPEEDBIN_18 + + + MEM_RLD2_REFRESH_INTERVAL_US + Refresh Interval + 0.24 + + + MEM_RLD2_TCKH_CYC + tCKH + 0.45 + + + MEM_RLD2_TQKH_HCYC + tQKH + 0.9 + + + MEM_RLD2_TAS_NS + tAS + 0.3 + + + MEM_RLD2_TAH_NS + tAH + 0.3 + + + MEM_RLD2_TDS_NS + tDS + 0.17 + + + MEM_RLD2_TDH_NS + tDH + 0.17 + + + MEM_RLD2_TQKQ_MAX_NS + tQKQ_max + 0.12 + + + MEM_RLD2_TQKQ_MIN_NS + tQKQ_min + -0.12 + + + MEM_RLD2_TCKDK_MAX_NS + tCKDK_max + 0.3 + + + MEM_RLD2_TCKDK_MIN_NS + tCKDK_min + -0.3 + + + MEM_RLD2_TCKQK_MAX_NS + tCKQK_max + 0.2 + + + MEM_RLD3_WIDTH_EXPANDED + Enable width expansion + false + + + MEM_RLD3_DEPTH_EXPANDED + Enable depth expansion using twin die package + false + + + MEM_RLD3_DQ_PER_DEVICE + DQ width per device + 36 + + + MEM_RLD3_ADDR_WIDTH + Address width + 20 + + + MEM_RLD3_BANK_ADDR_WIDTH + Bank address width + 4 + + + MEM_RLD3_DM_EN + Enable DM pins + true + + + MEM_RLD3_BL + Burst length + 2 + + + MEM_RLD3_DATA_LATENCY_MODE_ENUM + Data Latency + RLD3_DL_RL16_WL17 + + + MEM_RLD3_T_RC_MODE_ENUM + tRC + RLD3_TRC_9 + + + MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM + Output drive + RLD3_OUTPUT_DRIVE_40 + + + MEM_RLD3_ODT_MODE_ENUM + ODT + RLD3_ODT_40 + + + MEM_RLD3_AREF_PROTOCOL_ENUM + AREF protocol + RLD3_AREF_BAC + + + MEM_RLD3_WRITE_PROTOCOL_ENUM + Write protocol + RLD3_WRITE_1BANK + + + MEM_RLD3_SPEEDBIN_ENUM + Speed bin + RLD3_SPEEDBIN_093E + + + MEM_RLD3_TDS_PS + tDS (base) + -30 + + + MEM_RLD3_TDS_AC_MV + tDS (base) AC level + 150 + + + MEM_RLD3_TDH_PS + tDH (base) + 5 + + + MEM_RLD3_TDH_DC_MV + tDH (base) DC level + 100 + + + MEM_RLD3_TQKQ_MAX_PS + tQKQ_max + 75 + + + MEM_RLD3_TQH_CYC + tQH + 0.38 + + + MEM_RLD3_TCKDK_MAX_CYC + tCKDK_max + 0.27 + + + MEM_RLD3_TCKDK_MIN_CYC + tCKDK_min + -0.27 + + + MEM_RLD3_TCKQK_MAX_PS + tCKQK_max + 135 + + + MEM_RLD3_TIS_PS + tIS (base) + 85 + + + MEM_RLD3_TIS_AC_MV + tIS (base) AC level + 150 + + + MEM_RLD3_TIH_PS + tIH (base) + 65 + + + MEM_RLD3_TIH_DC_MV + tIH (base) DC level + 100 + + + MEM_LPDDR3_DQ_WIDTH + DQ width + 32 + + + MEM_LPDDR3_DISCRETE_CS_WIDTH + Number of chip selects + 1 + + + MEM_LPDDR3_CK_WIDTH + Number of clocks + 1 + + + MEM_LPDDR3_DM_EN + Enable DM pins + true + + + MEM_LPDDR3_ROW_ADDR_WIDTH + Row address width + 15 + + + MEM_LPDDR3_COL_ADDR_WIDTH + Column address width + 10 + + + MEM_LPDDR3_BANK_ADDR_WIDTH + Bank address width + 3 + + + MEM_LPDDR3_BL + Burst length + LPDDR3_BL_BL8 + + + MEM_LPDDR3_DATA_LATENCY + Data latency + LPDDR3_DL_RL12_WL6 + + + MEM_LPDDR3_DRV_STR + Output drive strength setting + LPDDR3_DRV_STR_40D_40U + + + MEM_LPDDR3_DQODT + DQ ODT + LPDDR3_DQODT_DISABLE + + + MEM_LPDDR3_PDODT + Power down ODT + LPDDR3_PDODT_DISABLED + + + MEM_LPDDR3_USE_DEFAULT_ODT + Use Default ODT Assertion Tables + true + + + MEM_LPDDR3_R_ODTN_1X1 + Read Target + Rank 0 + + + MEM_LPDDR3_R_ODT0_1X1 + ODT0 + off + + + MEM_LPDDR3_W_ODTN_1X1 + Write Target + Rank 0 + + + MEM_LPDDR3_W_ODT0_1X1 + ODT0 + on + + + MEM_LPDDR3_R_ODTN_2X2 + Read Target + Rank 0,Rank 1 + + + MEM_LPDDR3_R_ODT0_2X2 + ODT0 + off,off + + + MEM_LPDDR3_R_ODT1_2X2 + ODT1 + off,off + + + MEM_LPDDR3_W_ODTN_2X2 + Write Target + Rank 0,Rank 1 + + + MEM_LPDDR3_W_ODT0_2X2 + ODT0 + on,on + + + MEM_LPDDR3_W_ODT1_2X2 + ODT1 + off,off + + + MEM_LPDDR3_R_ODTN_4X4 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_LPDDR3_R_ODT0_4X4 + ODT0 + off,off,off,off + + + MEM_LPDDR3_R_ODT1_4X4 + ODT1 + off,off,off,off + + + MEM_LPDDR3_R_ODT2_4X4 + ODT2 + off,off,off,off + + + MEM_LPDDR3_R_ODT3_4X4 + ODT3 + off,off,off,off + + + MEM_LPDDR3_W_ODTN_4X4 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_LPDDR3_W_ODT0_4X4 + ODT0 + on,on,on,on + + + MEM_LPDDR3_W_ODT1_4X4 + ODT1 + off,off,off,off + + + MEM_LPDDR3_W_ODT2_4X4 + ODT2 + off,off,off,off + + + MEM_LPDDR3_W_ODT3_4X4 + ODT3 + off,off,off,off + + + MEM_LPDDR3_SPEEDBIN_ENUM + Speed bin + LPDDR3_SPEEDBIN_1600 + + + MEM_LPDDR3_TIS_PS + tISCA (base) + 75 + + + MEM_LPDDR3_TIS_AC_MV + tISCA (base) AC level + 150 + + + MEM_LPDDR3_TIH_PS + tIHCA (base) + 100 + + + MEM_LPDDR3_TIH_DC_MV + tIHCA (base) DC level + 100 + + + MEM_LPDDR3_TDS_PS + tDS (base) + 75 + + + MEM_LPDDR3_TDS_AC_MV + tDS (base) AC level + 150 + + + MEM_LPDDR3_TDH_PS + tDH (base) + 100 + + + MEM_LPDDR3_TDH_DC_MV + tDH (base) DC level + 100 + + + MEM_LPDDR3_TDQSQ_PS + tDQSQ + 135 + + + MEM_LPDDR3_TQH_CYC + tQH + 0.38 + + + MEM_LPDDR3_TDQSCKDL + tDQSCKDL + 614 + + + MEM_LPDDR3_TDQSS_CYC + tDQSS (max) + 1.25 + + + MEM_LPDDR3_TQSH_CYC + tQSH + 0.38 + + + MEM_LPDDR3_TDSH_CYC + tDSH + 0.2 + + + MEM_LPDDR3_TWLS_PS + tWLS + 175.0 + + + MEM_LPDDR3_TWLH_PS + tWLH + 175.0 + + + MEM_LPDDR3_TDSS_CYC + tDSS + 0.2 + + + MEM_LPDDR3_TINIT_US + tINIT + 500 + + + MEM_LPDDR3_TMRR_CK_CYC + tMRR + 4 + + + MEM_LPDDR3_TMRW_CK_CYC + tMRW + 10 + + + MEM_LPDDR3_TRAS_NS + tRAS + 42.5 + + + MEM_LPDDR3_TRCD_NS + tRCD + 18.0 + + + MEM_LPDDR3_TRP_NS + tRPpb + 18.0 + + + MEM_LPDDR3_TREFI_US + tREFI + 3.9 + + + MEM_LPDDR3_TRFC_NS + tRFCab + 210.0 + + + MEM_LPDDR3_TWR_NS + tWR + 15.0 + + + MEM_LPDDR3_TWTR_CYC + tWTR + 6 + + + MEM_LPDDR3_TFAW_NS + tFAW + 50.0 + + + MEM_LPDDR3_TRRD_CYC + tRRD + 8 + + + MEM_LPDDR3_TRTP_CYC + tRTP + 6 + + + MEM_DDRT_FORMAT_ENUM + Memory format + MEM_FORMAT_LRDIMM + + + MEM_DDRT_DQ_WIDTH + DQ width + 72 + + + MEM_DDRT_DQ_PER_DQS + DQ pins per DQS group + 4 + + + MEM_DDRT_DISCRETE_CS_WIDTH + Number of chip selects + 1 + + + MEM_DDRT_NUM_OF_DIMMS + Number of DIMMs + 1 + + + MEM_DDRT_RANKS_PER_DIMM + Number of physical ranks per DIMM + 1 + + + MEM_DDRT_CKE_PER_DIMM + Number of clock enables per DIMM + 1 + + + MEM_DDRT_ROW_ADDR_WIDTH + Row address width + 18 + + + MEM_DDRT_COL_ADDR_WIDTH + Column address width + 10 + + + MEM_DDRT_BANK_ADDR_WIDTH + Bank address width + 2 + + + MEM_DDRT_BANK_GROUP_WIDTH + Bank group width + 2 + + + MEM_DDRT_DM_EN + Data mask + false + + + MEM_DDRT_ALERT_PAR_EN + Enable ALERT#/PAR pins + true + + + MEM_DDRT_ALERT_N_PLACEMENT_ENUM + ALERT# pin placement + DDRT_ALERT_N_PLACEMENT_AUTO + + + MEM_DDRT_ALERT_N_DQS_GROUP + DQS group of ALERT# + 0 + + + MEM_DDRT_ALERT_N_AC_LANE + Address/command I/O lane of ALERT# + 0 + + + MEM_DDRT_ALERT_N_AC_PIN + Pin index of ALERT# + 0 + + + MEM_DDRT_DISCRETE_MIRROR_ADDRESSING_EN + Enable address mirroring for odd chip-selects + false + + + MEM_DDRT_MIRROR_ADDRESSING_EN + Enable address mirroring for odd ranks + true + + + MEM_DDRT_HIDE_ADV_MR_SETTINGS + Hide advanced mode register settings + true + + + MEM_DDRT_HIDE_LATENCY_SETTINGS + Hide advanced latency settings + true + + + MEM_DDRT_PWR_MODE + DIMM Power Mode + DDRT_PWR_MODE_12W + + + MEM_DDRT_BL_ENUM + Burst Length + DDRT_BL_BL8 + + + MEM_DDRT_BT_ENUM + Read Burst Type + DDRT_BT_SEQUENTIAL + + + MEM_DDRT_TCL + Memory CAS latency setting + 15 + + + MEM_DDRT_RTT_NOM_ENUM + ODT Rtt nominal value + DDRT_RTT_NOM_RZQ_4 + + + MEM_DDRT_DLL_EN + Enable the DLL in memory device + true + + + MEM_DDRT_ATCL_ENUM + Memory additive CAS latency setting + DDRT_ATCL_DISABLED + + + MEM_DDRT_DRV_STR_ENUM + Output drive strength setting + DDRT_DRV_STR_RZQ_7 + + + MEM_DDRT_ASR_ENUM + Auto self-refresh method + DDRT_ASR_MANUAL_NORMAL + + + MEM_DDRT_RTT_WR_ENUM + Dynamic ODT (Rtt_WR) value + DDRT_RTT_WR_ODT_DISABLED + + + MEM_DDRT_WTCL + Memory write CAS latency setting + 18 + + + MEM_DDRT_WRITE_CRC + Write CRC enable + false + + + MEM_DDRT_GEARDOWN + DDRT geardown mode + DDRT_GEARDOWN_HR + + + MEM_DDRT_PER_DRAM_ADDR + Per-DRAM addressability + false + + + MEM_DDRT_TEMP_SENSOR_READOUT + Temperature sensor readout + false + + + MEM_DDRT_FINE_GRANULARITY_REFRESH + Fine granularity refresh + DDRT_FINE_REFRESH_FIXED_1X + + + MEM_DDRT_MPR_READ_FORMAT + MPR read format + DDRT_MPR_READ_FORMAT_SERIAL + + + MEM_DDRT_MAX_POWERDOWN + Maximum power down mode + false + + + MEM_DDRT_TEMP_CONTROLLED_RFSH_RANGE + Temperature controlled refresh range + DDRT_TEMP_CONTROLLED_RFSH_NORMAL + + + MEM_DDRT_TEMP_CONTROLLED_RFSH_ENA + Temperature controlled refresh enable + false + + + MEM_DDRT_INTERNAL_VREFDQ_MONITOR + Internal VrefDQ monitor + false + + + MEM_DDRT_CAL_MODE + CS to Addr/CMD Latency + 0 + + + MEM_DDRT_SELF_RFSH_ABORT + Self refresh abort + false + + + MEM_DDRT_READ_PREAMBLE_TRAINING + Read preamble training mode enable + false + + + MEM_DDRT_DEFAULT_PREAMBLE + Use recommended preamble settings + true + + + MEM_DDRT_USER_READ_PREAMBLE + Read preamble + 1 + + + MEM_DDRT_USER_WRITE_PREAMBLE + Write preamble + 1 + + + MEM_DDRT_AC_PARITY_LATENCY + Addr/CMD parity latency + DDRT_AC_PARITY_LATENCY_DISABLE + + + MEM_DDRT_ODT_IN_POWERDOWN + ODT input buffer during powerdown mode + true + + + MEM_DDRT_RTT_PARK + CTT PARK + DDRT_RTT_PARK_ODT_DISABLED + + + MEM_DDRT_AC_PERSISTENT_ERROR + Addr/CMD persistent error + false + + + MEM_DDRT_WRITE_DBI + Write DBI + false + + + MEM_DDRT_READ_DBI + Read DBI + false + + + MEM_DDRT_PARTIAL_WRITES + Partial Writes + false + + + MEM_DDRT_DEFAULT_VREFOUT + Use recommended initial VrefDQ value + true + + + MEM_DDRT_USER_VREFDQ_TRAINING_VALUE + VrefDQ training value + 56.0 + + + MEM_DDRT_USER_VREFDQ_TRAINING_RANGE + VrefDQ training range + DDRT_VREFDQ_TRAINING_RANGE_1 + + + MEM_DDRT_DEFAULT_ADDED_LATENCY + Use recommended additional latency settings + true + + + MEM_DDRT_USER_TCL_ADDED + Additional CAS latency at PHY + 0 + + + MEM_DDRT_USER_WTCL_ADDED + Additional write CAS latency at PHY + 6 + + + MEM_DDRT_RCD_CA_IBT_ENUM + RCD CA Input Bus Termination + DDRT_RCD_CA_IBT_100 + + + MEM_DDRT_RCD_CS_IBT_ENUM + RCD DCS[3:0]_n Input Bus Termination + DDRT_RCD_CS_IBT_100 + + + MEM_DDRT_RCD_CKE_IBT_ENUM + RCD DCKE Input Bus Termination + DDRT_RCD_CKE_IBT_100 + + + MEM_DDRT_RCD_ODT_IBT_ENUM + RCD DODT Input Bus Termination + DDRT_RCD_ODT_IBT_100 + + + MEM_DDRT_DB_RTT_NOM_ENUM + DB Host Interface DQ RTT_NOM + DDRT_DB_RTT_NOM_ODT_DISABLED + + + MEM_DDRT_DB_RTT_WR_ENUM + DB Host Interface DQ RTT_WR + DDRT_DB_RTT_WR_RZQ_4 + + + MEM_DDRT_DB_RTT_PARK_ENUM + DB Host Interface DQ RTT_PARK + DDRT_DB_RTT_PARK_ODT_DISABLED + + + MEM_DDRT_DB_DQ_DRV_ENUM + DB Host Interface DQ Driver + DDRT_DB_DRV_STR_RZQ_7 + + + MEM_DDRT_SPD_137_RCD_CA_DRV + SPD Byte 137 - RCD Drive Strength for Command/Address + 85 + + + MEM_DDRT_SPD_138_RCD_CK_DRV + SPD Byte 138 - RCD Drive Strength for CK + 5 + + + MEM_DDRT_SPD_140_DRAM_VREFDQ_R0 + SPD Byte 140 - DRAM VrefDQ for Package Rank 0 + 29 + + + MEM_DDRT_SPD_141_DRAM_VREFDQ_R1 + SPD Byte 141 - DRAM VrefDQ for Package Rank 1 + 29 + + + MEM_DDRT_SPD_142_DRAM_VREFDQ_R2 + SPD Byte 142 - DRAM VrefDQ for Package Rank 2 + 29 + + + MEM_DDRT_SPD_143_DRAM_VREFDQ_R3 + SPD Byte 143 - DRAM VrefDQ for Package Rank 3 + 29 + + + MEM_DDRT_SPD_144_DB_VREFDQ + SPD Byte 144 - DB VrefDQ for DRAM Interface + 25 + + + MEM_DDRT_SPD_145_DB_MDQ_DRV + SPD Byte 145-147 - DB MDQ Drive Strength and RTT + 21 + + + MEM_DDRT_SPD_148_DRAM_DRV + SPD Byte 148 - DRAM Drive Strength + 0 + + + MEM_DDRT_SPD_149_DRAM_RTT_WR_NOM + SPD Byte 149-151 - DRAM ODT (RTT_WR and RTT_NOM) + 20 + + + MEM_DDRT_SPD_152_DRAM_RTT_PARK + SPD Byte 152-154 - DRAM ODT (RTT_PARK) + 39 + + + MEM_DDRT_SPD_133_RCD_DB_VENDOR_LSB + RCD and DB Manufacturer (LSB) + 0 + + + MEM_DDRT_SPD_134_RCD_DB_VENDOR_MSB + RCD and DB Manufacturer (MSB) + 0 + + + MEM_DDRT_SPD_135_RCD_REV + RCD Revision Number + 0 + + + MEM_DDRT_SPD_139_DB_REV + DB Revision Number + 0 + + + MEM_DDRT_LRDIMM_ODT_LESS_BS + PARAM_MEM_DDRT_LRDIMM_ODT_LESS_BS_NAME + false + + + MEM_DDRT_LRDIMM_ODT_LESS_BS_PARK_OHM + PARAM_MEM_DDRT_LRDIMM_ODT_LESS_BS_PARK_OHM_NAME + 240 + + + MEM_DDRT_I2C_DIMM_0_SA + I2C SA Value for DIMM 0 + 0 + + + MEM_DDRT_I2C_DIMM_1_SA + I2C SA Value for DIMM 1 + 1 + + + MEM_DDRT_I2C_DIMM_2_SA + I2C SA Value for DIMM 2 + 2 + + + MEM_DDRT_I2C_DIMM_3_SA + I2C SA Value for DIMM 3 + 3 + + + MEM_DDRT_PERSISTENT_MODE + Persistent Mode + 1 + + + MEM_DDRT_USE_DEFAULT_ODT + Use Default ODT Assertion Tables + true + + + MEM_DDRT_R_ODTN_1X1 + Read Target + Rank 0 + + + MEM_DDRT_R_ODT0_1X1 + ODT0 + off + + + MEM_DDRT_W_ODTN_1X1 + Write Target + Rank 0 + + + MEM_DDRT_W_ODT0_1X1 + ODT0 + on + + + MEM_DDRT_R_ODTN_2X2 + Read Target + Rank 0,Rank 1 + + + MEM_DDRT_R_ODT0_2X2 + ODT0 + off,off + + + MEM_DDRT_R_ODT1_2X2 + ODT1 + off,off + + + MEM_DDRT_W_ODTN_2X2 + Write Target + Rank 0,Rank 1 + + + MEM_DDRT_W_ODT0_2X2 + ODT0 + on,off + + + MEM_DDRT_W_ODT1_2X2 + ODT1 + off,on + + + MEM_DDRT_R_ODTN_4X2 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_R_ODT0_4X2 + ODT0 + off,off,on,on + + + MEM_DDRT_R_ODT1_4X2 + ODT1 + on,on,off,off + + + MEM_DDRT_W_ODTN_4X2 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_W_ODT0_4X2 + ODT0 + off,off,on,on + + + MEM_DDRT_W_ODT1_4X2 + ODT1 + on,on,off,off + + + MEM_DDRT_R_ODTN_4X4 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_R_ODT0_4X4 + ODT0 + off,off,off,off + + + MEM_DDRT_R_ODT1_4X4 + ODT1 + off,off,on,on + + + MEM_DDRT_R_ODT2_4X4 + ODT2 + off,off,off,off + + + MEM_DDRT_R_ODT3_4X4 + ODT3 + on,on,off,off + + + MEM_DDRT_W_ODTN_4X4 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_W_ODT0_4X4 + ODT0 + on,on,off,off + + + MEM_DDRT_W_ODT1_4X4 + ODT1 + off,off,on,on + + + MEM_DDRT_W_ODT2_4X4 + ODT2 + off,off,on,on + + + MEM_DDRT_W_ODT3_4X4 + ODT3 + on,on,off,off + + + MEM_DDRT_SPEEDBIN_ENUM + Speed bin + DDRT_SPEEDBIN_2400 + + + MEM_DDRT_TIS_PS + tIS (base) + 60 + + + MEM_DDRT_TIS_AC_MV + tIS (base) AC level + 100 + + + MEM_DDRT_TIH_PS + tIH (base) + 95 + + + MEM_DDRT_TIH_DC_MV + tIH (base) DC level + 75 + + + MEM_DDRT_TDIVW_TOTAL_UI + TdiVW_total + 0.2 + + + MEM_DDRT_VDIVW_TOTAL + VdiVW_total + 136 + + + MEM_DDRT_TDQSQ_UI + tDQSQ + 0.16 + + + MEM_DDRT_TQH_UI + tQH + 0.76 + + + MEM_DDRT_TDVWP_UI + tDVWp + 0.72 + + + MEM_DDRT_TDQSCK_PS + tDQSCK + 165 + + + MEM_DDRT_TDQSS_CYC + tDQSS + 0.27 + + + MEM_DDRT_TQSH_CYC + tQSH + 0.38 + + + MEM_DDRT_TDSH_CYC + tDSH + 0.18 + + + MEM_DDRT_TDSS_CYC + tDSS + 0.18 + + + MEM_DDRT_TWLS_CYC + tWLS + 0.13 + + + MEM_DDRT_TWLH_CYC + tWLH + 0.13 + + + MEM_DDRT_TINIT_US + tINIT + 500 + + + MEM_DDRT_TMRD_CK_CYC + tMRD + 8 + + + MEM_DDRT_TRAS_NS + tRAS + 32.0 + + + MEM_DDRT_TRCD_NS + tRCD + 15.0 + + + MEM_DDRT_TRP_NS + tRP + 15.0 + + + MEM_DDRT_TREFI_US + tREFI + 7.8 + + + MEM_DDRT_TRFC_NS + tRFC + 260.0 + + + MEM_DDRT_TWR_NS + tWR + 15.0 + + + MEM_DDRT_TWTR_L_CYC + tWTR_L + 9 + + + MEM_DDRT_TWTR_S_CYC + tWTR_S + 3 + + + MEM_DDRT_TFAW_NS + tFAW + 21.0 + + + MEM_DDRT_TRRD_L_CYC + tRRD_L + 6 + + + MEM_DDRT_TRRD_S_CYC + tRRD_S + 4 + + + MEM_DDRT_TCCD_L_CYC + tCCD_L + 6 + + + MEM_DDRT_TCCD_S_CYC + tCCD_S + 4 + + + MEM_DDRT_TRFC_DLR_NS + tRFC_dlr + 90.0 + + + MEM_DDRT_TFAW_DLR_CYC + tFAW_dlr + 16 + + + MEM_DDRT_TRRD_DLR_CYC + tRRD_dlr + 4 + + + MEM_DDRT_TDIVW_DJ_CYC + PARAM_MEM_DDRT_TDIVW_DJ_CYC_NAME + 0.1 + + + MEM_DDRT_TDQSQ_PS + PARAM_MEM_DDRT_TDQSQ_PS_NAME + 66 + + + MEM_DDRT_TQH_CYC + PARAM_MEM_DDRT_TQH_CYC_NAME + 0.38 + + + MEM_DDRT_CFG_GEN_SBE + PARAM_MEM_DDRT_CFG_GEN_SBE_NAME + false + + + MEM_DDRT_CFG_GEN_DBE + PARAM_MEM_DDRT_CFG_GEN_DBE_NAME + false + + + MEM_DDRT_LRDIMM_VREFDQ_VALUE + PARAM_MEM_DDRT_LRDIMM_VREFDQ_VALUE_NAME + + + + MEM_DDRT_TWLS_PS + PARAM_MEM_DDRT_TWLS_PS_NAME + 0.0 + + + MEM_DDRT_TWLH_PS + PARAM_MEM_DDRT_TWLH_PS_NAME + 0.0 + + + BOARD_DDR3_USE_DEFAULT_SLEW_RATES + Use default slew rates + true + + + BOARD_DDR3_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_DDR3_USER_CK_SLEW_RATE + CK/CK# slew rate (Differential) + 4.0 + + + BOARD_DDR3_USER_AC_SLEW_RATE + Address and command slew rate + 2.0 + + + BOARD_DDR3_USER_RCLK_SLEW_RATE + Read DQS/DQS# slew rate (Differential) + 5.0 + + + BOARD_DDR3_USER_WCLK_SLEW_RATE + Write DQS/DQS# slew rate (Differential) + 4.0 + + + BOARD_DDR3_USER_RDATA_SLEW_RATE + Read DQ slew rate + 2.5 + + + BOARD_DDR3_USER_WDATA_SLEW_RATE + Write DQ slew rate + 2.0 + + + BOARD_DDR3_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_DDR3_USER_RCLK_ISI_NS + Read DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_DDR3_USER_WCLK_ISI_NS + Write DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_DDR3_USER_RDATA_ISI_NS + Read DQ ISI/crosstalk + 0.0 + + + BOARD_DDR3_USER_WDATA_ISI_NS + Write DQ ISI/crosstalk + 0.0 + + + BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED + Package deskewed with board layout (DQS group) + false + + + BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS + Maximum board skew within DQS group + 0.02 + + + BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS + Maximum system skew within DQS group + 0.02 + + + BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + true + + + BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.02 + + + BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.02 + + + BOARD_DDR3_DQS_TO_CK_SKEW_NS + Average delay difference between DQS and CK + 0.02 + + + BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS + Maximum delay difference between DIMMs/devices + 0.05 + + + BOARD_DDR3_SKEW_BETWEEN_DQS_NS + Maximum skew between DQS groups + 0.02 + + + BOARD_DDR3_AC_TO_CK_SKEW_NS + Average delay difference between address/command and CK + 0.0 + + + BOARD_DDR3_MAX_CK_DELAY_NS + Maximum CK delay to DIMM/device + 0.6 + + + BOARD_DDR3_MAX_DQS_DELAY_NS + Maximum DQS delay to DIMM/device + 0.6 + + + BOARD_DDR4_USE_DEFAULT_SLEW_RATES + Use default slew rates + true + + + BOARD_DDR4_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_DDR4_USER_CK_SLEW_RATE + CK/CK# slew rate (Differential) + 4.0 + + + BOARD_DDR4_USER_AC_SLEW_RATE + Address and command slew rate + 2.0 + + + BOARD_DDR4_USER_RCLK_SLEW_RATE + Read DQS/DQS# slew rate (Differential) + 8.0 + + + BOARD_DDR4_USER_WCLK_SLEW_RATE + Write DQS/DQS# slew rate (Differential) + 4.0 + + + BOARD_DDR4_USER_RDATA_SLEW_RATE + Read DQ slew rate + 4.0 + + + BOARD_DDR4_USER_WDATA_SLEW_RATE + Write DQ slew rate + 2.0 + + + BOARD_DDR4_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_DDR4_USER_RCLK_ISI_NS + Read DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_DDR4_USER_WCLK_ISI_NS + Write DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_DDR4_USER_RDATA_ISI_NS + Read DQ ISI/crosstalk + 0.0 + + + BOARD_DDR4_USER_WDATA_ISI_NS + Write DQ ISI/crosstalk + 0.0 + + + BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED + Package deskewed with board layout (DQS group) + true + + + BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS + Maximum board skew within DQS group + 0.02 + + + BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS + Maximum system skew within DQS group + 0.001350118 + + + BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + true + + + BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.002179616 + + + BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.002645604 + + + BOARD_DDR4_DQS_TO_CK_SKEW_NS + Average delay difference between DQS and CK + -0.042680619 + + + BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS + Maximum delay difference between DIMMs/devices + 0.05 + + + BOARD_DDR4_SKEW_BETWEEN_DQS_NS + Maximum skew between DQS groups + 0.116352997 + + + BOARD_DDR4_AC_TO_CK_SKEW_NS + Average delay difference between address/command and CK + 3.02328E-5 + + + BOARD_DDR4_MAX_CK_DELAY_NS + Maximum CK delay to DIMM/device + 0.601619768 + + + BOARD_DDR4_MAX_DQS_DELAY_NS + Maximum DQS delay to DIMM/device + 0.617112409 + + + BOARD_QDR2_USE_DEFAULT_SLEW_RATES + Use default slew rates + true + + + BOARD_QDR2_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_QDR2_USER_K_SLEW_RATE + K/K# slew rate (Differential) + 4.0 + + + BOARD_QDR2_USER_AC_SLEW_RATE + Address and command slew rate + 2.0 + + + BOARD_QDR2_USER_RCLK_SLEW_RATE + CQ/CQ# slew rate (Complementary) + 4.0 + + + BOARD_QDR2_USER_RDATA_SLEW_RATE + Read Q slew rate + 2.0 + + + BOARD_QDR2_USER_WDATA_SLEW_RATE + Write D slew rate + 2.0 + + + BOARD_QDR2_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_QDR2_USER_RCLK_ISI_NS + CQ/CQ# ISI/crosstalk + 0.0 + + + BOARD_QDR2_USER_WCLK_ISI_NS + K/K# ISI/crosstalk + 0.0 + + + BOARD_QDR2_USER_RDATA_ISI_NS + Read Q ISI/crosstalk + 0.0 + + + BOARD_QDR2_USER_WDATA_ISI_NS + Write D ISI/crosstalk + 0.0 + + + BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED + Package deskewed with board layout (Q group) + false + + + BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED + Package deskewed with board layout (D group) + false + + + BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + true + + + BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS + Maximum board skew within Q group + 0.02 + + + BOARD_QDR2_BRD_SKEW_WITHIN_D_NS + Maximum board skew within D group + 0.02 + + + BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.02 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS + Maximum system skew within Q group + 0.02 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS + Maximum system skew within D group + 0.02 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.02 + + + BOARD_QDR2_AC_TO_K_SKEW_NS + Average delay difference between address/command and K + 0.0 + + + BOARD_QDR2_MAX_K_DELAY_NS + Maximum K delay to device + 0.6 + + + BOARD_QDR4_USE_DEFAULT_SLEW_RATES + Use default slew rates + true + + + BOARD_QDR4_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_QDR4_USER_CK_SLEW_RATE + CK/CK# slew rate (Differential) + 4.0 + + + BOARD_QDR4_USER_AC_SLEW_RATE + Address and command slew rate + 2.0 + + + BOARD_QDR4_USER_RCLK_SLEW_RATE + QK/QK# slew rate (Differential) + 5.0 + + + BOARD_QDR4_USER_WCLK_SLEW_RATE + DK/DK# slew rate (Differential) + 4.0 + + + BOARD_QDR4_USER_RDATA_SLEW_RATE + Read DQ slew rate + 2.5 + + + BOARD_QDR4_USER_WDATA_SLEW_RATE + Write DQ slew rate + 2.0 + + + BOARD_QDR4_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_QDR4_USER_RCLK_ISI_NS + QK/QK# ISI/crosstalk + 0.0 + + + BOARD_QDR4_USER_WCLK_ISI_NS + DK/DK# ISI/crosstalk + 0.0 + + + BOARD_QDR4_USER_RDATA_ISI_NS + Read DQ ISI/crosstalk + 0.0 + + + BOARD_QDR4_USER_WDATA_ISI_NS + Write DQ ISI/crosstalk + 0.0 + + + BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED + Package deskewed with board layout (QK group) + true + + + BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS + Maximum board skew within QK group + 0.02 + + + BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS + Maximum system skew within QK group + 0.02 + + + BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + true + + + BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.02 + + + BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.02 + + + BOARD_QDR4_DK_TO_CK_SKEW_NS + Average delay difference between DK and CK + -0.02 + + + BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS + Maximum delay difference between devices + 0.05 + + + BOARD_QDR4_SKEW_BETWEEN_DK_NS + Maximum skew between DK groups + 0.02 + + + BOARD_QDR4_AC_TO_CK_SKEW_NS + Average delay difference between address/command and CK + 0.0 + + + BOARD_QDR4_MAX_CK_DELAY_NS + Maximum CK delay to device + 0.6 + + + BOARD_QDR4_MAX_DK_DELAY_NS + Maximum DK delay to device + 0.6 + + + BOARD_RLD3_USE_DEFAULT_SLEW_RATES + Use default slew rates + true + + + BOARD_RLD3_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_RLD3_USER_CK_SLEW_RATE + CK/CK# slew rate (Differential) + 4.0 + + + BOARD_RLD3_USER_AC_SLEW_RATE + Address and command slew rate + 2.0 + + + BOARD_RLD3_USER_RCLK_SLEW_RATE + QK/QK# slew rate (Differential) + 7.0 + + + BOARD_RLD3_USER_WCLK_SLEW_RATE + DK/DK# slew rate (Differential) + 4.0 + + + BOARD_RLD3_USER_RDATA_SLEW_RATE + Read DQ slew rate + 3.5 + + + BOARD_RLD3_USER_WDATA_SLEW_RATE + Write DQ slew rate + 2.0 + + + BOARD_RLD3_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_RLD3_USER_RCLK_ISI_NS + QK/QK# ISI/crosstalk + 0.0 + + + BOARD_RLD3_USER_WCLK_ISI_NS + DK/DK# ISI/crosstalk + 0.0 + + + BOARD_RLD3_USER_RDATA_ISI_NS + Read DQ ISI/crosstalk + 0.0 + + + BOARD_RLD3_USER_WDATA_ISI_NS + Write DQ ISI/crosstalk + 0.0 + + + BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED + Package deskewed with board layout (QK group) + false + + + BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS + Maximum board skew within QK group + 0.02 + + + BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS + Maximum system skew within QK group + 0.02 + + + BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + true + + + BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.02 + + + BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.02 + + + BOARD_RLD3_DK_TO_CK_SKEW_NS + Average delay difference between DK and CK + -0.02 + + + BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS + Maximum delay difference between devices + 0.05 + + + BOARD_RLD3_SKEW_BETWEEN_DK_NS + Maximum skew between DK groups + 0.02 + + + BOARD_RLD3_AC_TO_CK_SKEW_NS + Average delay difference between address/command and CK + 0.0 + + + BOARD_RLD3_MAX_CK_DELAY_NS + Maximum CK delay to device + 0.6 + + + BOARD_RLD3_MAX_DK_DELAY_NS + Maximum DK delay to device + 0.6 + + + BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES + PARAM_BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES_NAME + true + + + BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_LPDDR3_USER_CK_SLEW_RATE + PARAM_BOARD_LPDDR3_USER_CK_SLEW_RATE_NAME + 4.0 + + + BOARD_LPDDR3_USER_AC_SLEW_RATE + PARAM_BOARD_LPDDR3_USER_AC_SLEW_RATE_NAME + 2.0 + + + BOARD_LPDDR3_USER_RCLK_SLEW_RATE + PARAM_BOARD_LPDDR3_USER_RCLK_SLEW_RATE_NAME + 4.0 + + + BOARD_LPDDR3_USER_WCLK_SLEW_RATE + PARAM_BOARD_LPDDR3_USER_WCLK_SLEW_RATE_NAME + 4.0 + + + BOARD_LPDDR3_USER_RDATA_SLEW_RATE + PARAM_BOARD_LPDDR3_USER_RDATA_SLEW_RATE_NAME + 2.0 + + + BOARD_LPDDR3_USER_WDATA_SLEW_RATE + PARAM_BOARD_LPDDR3_USER_WDATA_SLEW_RATE_NAME + 2.0 + + + BOARD_LPDDR3_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_LPDDR3_USER_RCLK_ISI_NS + Read DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_LPDDR3_USER_WCLK_ISI_NS + Write DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_LPDDR3_USER_RDATA_ISI_NS + Read DQ ISI/crosstalk + 0.0 + + + BOARD_LPDDR3_USER_WDATA_ISI_NS + Write DQ ISI/crosstalk + 0.0 + + + BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED + Package deskewed with board layout (DQS group) + false + + + BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS + Maximum board skew within DQS group + 0.02 + + + BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS + Maximum system skew within DQS group + 0.02 + + + BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + true + + + BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.02 + + + BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.02 + + + BOARD_LPDDR3_DQS_TO_CK_SKEW_NS + Average delay difference between DQS and CK + 0.02 + + + BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS + Maximum delay difference between devices + 0.05 + + + BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS + Maximum skew between DQS groups + 0.02 + + + BOARD_LPDDR3_AC_TO_CK_SKEW_NS + Average delay difference between address/command and CK + 0.0 + + + BOARD_LPDDR3_MAX_CK_DELAY_NS + Maximum CK delay to device + 0.6 + + + BOARD_LPDDR3_MAX_DQS_DELAY_NS + Maximum DQS delay to device + 0.6 + + + BOARD_DDRT_USE_DEFAULT_SLEW_RATES + Use default slew rates + true + + + BOARD_DDRT_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_DDRT_USER_CK_SLEW_RATE + CK/CK# slew rate (Differential) + 4.0 + + + BOARD_DDRT_USER_AC_SLEW_RATE + Address and command slew rate + 2.0 + + + BOARD_DDRT_USER_RCLK_SLEW_RATE + Read DQS/DQS# slew rate (Differential) + 8.0 + + + BOARD_DDRT_USER_WCLK_SLEW_RATE + Write DQS/DQS# slew rate (Differential) + 4.0 + + + BOARD_DDRT_USER_RDATA_SLEW_RATE + Read DQ slew rate + 4.0 + + + BOARD_DDRT_USER_WDATA_SLEW_RATE + Write DQ slew rate + 2.0 + + + BOARD_DDRT_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_DDRT_USER_RCLK_ISI_NS + Read DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_DDRT_USER_WCLK_ISI_NS + Write DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_DDRT_USER_RDATA_ISI_NS + Read DQ ISI/crosstalk + 0.0 + + + BOARD_DDRT_USER_WDATA_ISI_NS + Write DQ ISI/crosstalk + 0.0 + + + BOARD_DDRT_IS_SKEW_WITHIN_DQS_DESKEWED + Package deskewed with board layout (DQS group) + true + + + BOARD_DDRT_BRD_SKEW_WITHIN_DQS_NS + Maximum board skew within DQS group + 0.02 + + + BOARD_DDRT_PKG_BRD_SKEW_WITHIN_DQS_NS + Maximum system skew within DQS group + 0.02 + + + BOARD_DDRT_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + false + + + BOARD_DDRT_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.02 + + + BOARD_DDRT_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.02 + + + BOARD_DDRT_DQS_TO_CK_SKEW_NS + Average delay difference between DQS and CK + 0.02 + + + BOARD_DDRT_SKEW_BETWEEN_DIMMS_NS + Maximum delay difference between DIMMs/devices + 0.05 + + + BOARD_DDRT_SKEW_BETWEEN_DQS_NS + Maximum skew between DQS groups + 0.02 + + + BOARD_DDRT_AC_TO_CK_SKEW_NS + Average delay difference between address/command and CK + 0.0 + + + BOARD_DDRT_MAX_CK_DELAY_NS + Maximum CK delay to DIMM/device + 0.6 + + + BOARD_DDRT_MAX_DQS_DELAY_NS + Maximum DQS delay to DIMM/device + 0.6 + + + CTRL_DDR3_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDR3_SELF_REFRESH_EN + Enable Self-Refresh Control + false + + + CTRL_DDR3_AUTO_POWER_DOWN_EN + Enable Auto Power-Down + false + + + CTRL_DDR3_AUTO_POWER_DOWN_CYCS + Auto Power-Down Cycles + 32 + + + CTRL_DDR3_USER_REFRESH_EN + Enable User Refresh Control + false + + + CTRL_DDR3_USER_PRIORITY_EN + Enable Command Priority Control + false + + + CTRL_DDR3_AUTO_PRECHARGE_EN + Enable Auto-Precharge Control + false + + + CTRL_DDR3_ADDR_ORDER_ENUM + Address Ordering + DDR3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_DDR3_ECC_EN + Enable Error Detection and Correction Logic with ECC + false + + + CTRL_DDR3_ECC_AUTO_CORRECTION_EN + Enable Auto Error Correction to External Memory + false + + + CTRL_DDR3_ECC_READDATAERROR_EN + Enable ctrl_ecc_readdataerror signal to indicate uncorrectable data errors + false + + + CTRL_DDR3_ECC_STATUS_EN + Export error-correction code (ECC) status ports + false + + + CTRL_DDR3_REORDER_EN + Enable Reordering + true + + + CTRL_DDR3_STARVE_LIMIT + Starvation limit for each command + 10 + + + CTRL_DDR3_MMR_EN + Enable Memory-Mapped Configuration and Status Register (MMR) Interface + false + + + CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (same rank) + 0 + + + CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (same rank) + 0 + + + CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional read-to-read turnaround time (different ranks) + 0 + + + CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (different ranks) + 0 + + + CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional write-to-write turnaround time (different ranks) + 0 + + + CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (different ranks) + 0 + + + CTRL_DDR4_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDR4_SELF_REFRESH_EN + Enable Self-Refresh Control + false + + + CTRL_DDR4_AUTO_POWER_DOWN_EN + Enable Auto Power-Down + false + + + CTRL_DDR4_AUTO_POWER_DOWN_CYCS + Auto Power-Down Cycles + 32 + + + CTRL_DDR4_USER_REFRESH_EN + Enable User Refresh Control + false + + + CTRL_DDR4_USER_PRIORITY_EN + Enable Command Priority Control + false + + + CTRL_DDR4_AUTO_PRECHARGE_EN + Enable Auto-Precharge Control + false + + + CTRL_DDR4_ADDR_ORDER_ENUM + Address Ordering + DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG + + + CTRL_DDR4_ECC_EN + Enable Error Detection and Correction Logic with ECC + true + + + CTRL_DDR4_ECC_AUTO_CORRECTION_EN + Enable Auto Error Correction to External Memory + true + + + CTRL_DDR4_ECC_READDATAERROR_EN + Enable ctrl_ecc_readdataerror signal to indicate uncorrectable data errors + false + + + CTRL_DDR4_ECC_STATUS_EN + Export error-correction code (ECC) status ports + false + + + CTRL_DDR4_REORDER_EN + Enable Reordering + true + + + CTRL_DDR4_STARVE_LIMIT + Starvation limit for each command + 10 + + + CTRL_DDR4_MMR_EN + Enable Memory-Mapped Configuration and Status Register (MMR) Interface + false + + + CTRL_DDR4_MAJOR_MODE_EN + Enable controller major mode + false + + + CTRL_DDR4_POST_REFRESH_EN + Enable controller post-pay refresh + false + + + CTRL_DDR4_POST_REFRESH_LOWER_LIMIT + Post-pay refresh lower limit + 0 + + + CTRL_DDR4_POST_REFRESH_UPPER_LIMIT + Post-pay refresh upper limit + 2 + + + CTRL_DDR4_PRE_REFRESH_EN + Enable controller pre-pay refresh + false + + + CTRL_DDR4_PRE_REFRESH_UPPER_LIMIT + Refresh pre-pay upper limit + 1 + + + CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (same rank) + 0 + + + CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (same rank) + 0 + + + CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional read-to-read turnaround time (different ranks) + 0 + + + CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (different ranks) + 0 + + + CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional write-to-write turnaround time (different ranks) + 0 + + + CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (different ranks) + 0 + + + CTRL_QDR2_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_QDR2_AVL_MAX_BURST_COUNT + Maximum Avalon-MM burst length + 4 + + + CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS + Generate power-of-2 data bus widths for Qsys + false + + + CTRL_QDR4_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_QDR4_AVL_MAX_BURST_COUNT + Maximum Avalon-MM burst length + 4 + + + CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS + Generate power-of-2 data bus widths for Qsys + false + + + CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC + Additional read-after-write turnaround time + 0 + + + CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC + Additional write-after-read turnaround time + 0 + + + CTRL_QDR4_DEF_RAW_TURNAROUND_DELAY_CYC + PARAM_CTRL_QDR4_DEF_RAW_TURNAROUND_DELAY_CYC_NAME + 7 + + + CTRL_RLD2_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_RLD3_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_RLD3_ADDR_ORDER_ENUM + Address Ordering + RLD3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_LPDDR3_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_LPDDR3_SELF_REFRESH_EN + Enable Self-Refresh Control + false + + + CTRL_LPDDR3_AUTO_POWER_DOWN_EN + Enable Auto Power-Down + false + + + CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS + Auto Power-Down Cycles + 32 + + + CTRL_LPDDR3_USER_REFRESH_EN + Enable User Refresh Control + false + + + CTRL_LPDDR3_USER_PRIORITY_EN + Enable Command Priority Control + false + + + CTRL_LPDDR3_AUTO_PRECHARGE_EN + Enable Auto-Precharge Control + false + + + CTRL_LPDDR3_ADDR_ORDER_ENUM + Address Ordering + LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_LPDDR3_REORDER_EN + Enable Reordering + true + + + CTRL_LPDDR3_STARVE_LIMIT + Starvation limit for each command + 10 + + + CTRL_LPDDR3_MMR_EN + Enable Memory-Mapped Configuration and Status Register (MMR) Interface + false + + + CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (same rank) + 0 + + + CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (same rank) + 0 + + + CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional read-to-read turnaround time (different ranks) + 0 + + + CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (different ranks) + 0 + + + CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional write-to-write turnaround time (different ranks) + 0 + + + CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (different ranks) + 0 + + + CTRL_DDRT_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDRT_SELF_REFRESH_EN + Enable Self-Refresh Control + false + + + CTRL_DDRT_AUTO_POWER_DOWN_EN + Enable Auto Power-Down + false + + + CTRL_DDRT_AUTO_POWER_DOWN_CYCS + Auto Power-Down Cycles + 32 + + + CTRL_DDRT_USER_REFRESH_EN + Enable User Refresh Control + false + + + CTRL_DDRT_USER_PRIORITY_EN + Enable Command Priority Control + false + + + CTRL_DDRT_AUTO_PRECHARGE_EN + Enable Auto-Precharge Control + false + + + CTRL_DDRT_ADDR_ORDER_ENUM + PARAM_CTRL_DDRT_ADDR_ORDER_ENUM_NAME + DDRT_CTRL_ADDR_ORDER_CS_R_B_C_BG + + + CTRL_DDRT_ECC_EN + Enable Error Detection and Correction Logic with ECC + false + + + CTRL_DDRT_ECC_AUTO_CORRECTION_EN + Enable Auto Error Correction to External Memory + false + + + CTRL_DDRT_ECC_READDATAERROR_EN + Enable ctrl_ecc_readdataerror signal to indicate uncorrectable data errors + true + + + CTRL_DDRT_ECC_STATUS_EN + Export error-correction code (ECC) status ports + true + + + CTRL_DDRT_REORDER_EN + Enable Reordering + true + + + CTRL_DDRT_STARVE_LIMIT + Starvation limit for each command + 10 + + + CTRL_DDRT_MMR_EN + Enable Memory-Mapped Configuration and Status Register (MMR) Interface + false + + + CTRL_DDRT_RD_TO_WR_SAME_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (same rank) + 0 + + + CTRL_DDRT_WR_TO_RD_SAME_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (same rank) + 0 + + + CTRL_DDRT_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional read-to-read turnaround time (different ranks) + 0 + + + CTRL_DDRT_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (different ranks) + 0 + + + CTRL_DDRT_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (different ranks) + 0 + + + CTRL_DDRT_DIMM_DENSITY + Capacity of Optane DIMM + 128 + + + CTRL_DDRT_NUM_OF_AXIS_ID + Number of AXI masters + 1 + + + CTRL_DDRT_WR_ACK_POLICY + Write Acknowldgement Policy + POSTED + + + CTRL_DDRT_ERR_REPLAY_EN + Replay on Error + false + + + CTRL_DDRT_HOST_VIRAL_FLOW_EN + Host Error Viral + false + + + CTRL_DDRT_DIMM_VIRAL_FLOW_EN + DIMM Error Viral + false + + + CTRL_DDRT_POISON_DETECTION_EN + Error Poison + false + + + CTRL_DDRT_PMM_ADR_FLOW_EN + PMM ADR Flow + false + + + CTRL_DDRT_PMM_WPQ_FLUSH_EN + PMM WPQ Flush + false + + + CTRL_DDRT_UPI_EN + UPI EN + false + + + CTRL_DDRT_UPI_ID_WIDTH + PARAM_CTRL_DDRT_UPI_ID_WIDTH_NAME + 8 + + + CTRL_DDRT_PARITY_CMD_EN + CMD Parity EN + false + + + CTRL_DDRT_ADDR_INTERLEAVING + Address Interleaving + COARSE + + + CTRL_DDRT_PORT_AFI_C_WIDTH + PARAM_CTRL_DDRT_PORT_AFI_C_WIDTH_NAME + 2 + + + CTRL_DDRT_ZQ_INTERVAL_MS + ZQCS command interval + 3 + + + CTRL_DDRT_ERR_INJECT_EN + Error Inject EN + false + + + CTRL_DDRT_GNT_TO_WR_SAME_CHIP_DELTA_CYCS + Additional grant to write turnaround time (same DIMM) + 1 + + + CTRL_DDRT_WR_TO_GNT_SAME_CHIP_DELTA_CYCS + Additional write to grant turnaround time (same DIMM) + 0 + + + CTRL_DDRT_GNT_TO_GNT_DIFF_CHIP_DELTA_CYCS + Additional grant to grant turnaround time (different DIMM) + 0 + + + CTRL_DDRT_GNT_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional grant to write turnaround time (different DIMM) + 1 + + + CTRL_DDRT_WR_TO_GNT_DIFF_CHIP_DELTA_CYCS + Additional write to grant turnaround time (different DIMM) + 0 + + + CTRL_DDRT_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional write to write turnaround time (different DIMM) + 0 + + + DIAG_SIM_REGTEST_MODE + Simulation regtest mode + false + + + DIAG_TIMING_REGTEST_MODE + Timing regtest mode + false + + + DIAG_SYNTH_FOR_SIM + Synthesize for simulation + false + + + DIAG_FAST_SIM_OVERRIDE + Fast simulation override + FAST_SIM_OVERRIDE_DEFAULT + + + DIAG_SEQ_RESET_AUTO_RELEASE + PARAM_DIAG_SEQ_RESET_AUTO_RELEASE_NAME + avl + + + DIAG_DB_RESET_AUTO_RELEASE + PARAM_DIAG_DB_RESET_AUTO_RELEASE_NAME + avl_release + + + DIAG_ADD_READY_PIPELINE + Add additional pipeline on the ready/WaitRequest path. + true + + + DIAG_EXPOSE_EARLY_READY + Expose Early Ready + false + + + DIAG_EXPOSE_RD_TYPE + Expose Read Type + false + + + DIAG_VERBOSE_IOAUX + Show verbose IOAUX debug messages + false + + + DIAG_ECLIPSE_DEBUG + Enable Eclipse debugging + false + + + DIAG_EXPORT_VJI + Export Virtual JTAG Interface (VJI) + false + + + DIAG_ENABLE_JTAG_UART + Enable JTAG UART + false + + + DIAG_ENABLE_JTAG_UART_HEX + Enable JTAG UART hexfiles + false + + + DIAG_ENABLE_HPS_EMIF_DEBUG + Enable UART for HPS EMIF Debug + false + + + DIAG_SOFT_NIOS_MODE + Use Soft NIOS Processor for On-Chip Debug + SOFT_NIOS_MODE_DISABLED + + + DIAG_SOFT_NIOS_CLOCK_FREQUENCY + Calibration Processor External Clock Frequency + 100 + + + DIAG_USE_RS232_UART + Use an RS232 UART for Soft NIOS Calibration Processor debug output (requires code change) + false + + + DIAG_RS232_UART_BAUDRATE + RS232 UART Speed + 57600 + + + DIAG_EX_DESIGN_ADD_TEST_EMIFS + Add extra EMIFs to example design + + + + DIAG_EX_DESIGN_SEPARATE_RESETS + Use a separate global reset signal for every interface + false + + + DIAG_EXPOSE_DFT_SIGNALS + Expose test and debug signals + false + + + DIAG_EXTRA_CONFIGS + Extra configuration + + + + DIAG_USE_BOARD_DELAY_MODEL + Use board delay model during simulation + false + + + DIAG_BOARD_DELAY_CONFIG_STR + Board delay model configuration + + + + DIAG_TG_AVL_2_NUM_CFG_INTERFACES + Number of Traffic Generator 2.0 configuration interfaces + 0 + + + DIAG_EXPORT_PLL_REF_CLK_OUT + PARAM_DIAG_EXPORT_PLL_REF_CLK_OUT_NAME + false + + + DIAG_EXPORT_PLL_LOCKED + Export PLL lock signal + false + + + DIAG_HMC_HRC + PARAM_DIAG_HMC_HRC_NAME + auto + + + SHORT_QSYS_INTERFACE_NAMES + Use short Qsys interface names + true + + + DIAG_EXT_DOCS + PARAM_DIAG_EXT_DOCS_NAME + false + + + DIAG_DDR3_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_DDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_DDR3_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + false + + + DIAG_DDR3_INTERFACE_ID + Interface ID + 0 + + + DIAG_DDR3_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_DDR3_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_DDR3_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_DDR3_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_DDR3_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_DDR3_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_DDR3_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_DDR3_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_DDR3_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_DDR3_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_DDR3_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_DDR3_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_DDR3_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_DDR3_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_DDR3_CA_LEVEL_EN + Enable address/command leveling calibration + true + + + DIAG_DDR3_CA_DESKEW_EN + Enable address/command deskew calibration + true + + + DIAG_DDR3_CAL_ADDR0 + Calibration address 0 + 0 + + + DIAG_DDR3_CAL_ADDR1 + Calibration address 1 + 8 + + + DIAG_DDR3_CAL_ENABLE_NON_DES + Enable refreshes during calibration + false + + + DIAG_DDR3_CAL_FULL_CAL_ON_RESET + Enable automatic calibration after reset + true + + + DIAG_DDR3_CAL_ENABLE_MICRON_AP + Enable Micron Automata Calibration + false + + + DIAG_DDR4_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_DDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_DDR4_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + false + + + DIAG_DDR4_INTERFACE_ID + Interface ID + 0 + + + DIAG_DDR4_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_DDR4_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_DDR4_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_DDR4_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_DDR4_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_DDR4_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_DDR4_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_DDR4_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_DDR4_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_DDR4_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_DDR4_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_DDR4_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_DDR4_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_DDR4_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_DDR4_SKIP_CA_LEVEL + Skip address/command leveling calibration + false + + + DIAG_DDR4_SKIP_CA_DESKEW + Skip address/command deskew calibration + false + + + DIAG_DDR4_SKIP_VREF_CAL + Skip VREF calibration + false + + + DIAG_DDR4_SKIP_AC_PARITY_CHECK + Skip address/command parity check during calibration + false + + + DIAG_DDR4_CAL_ADDR0 + Calibration address 0 + 0 + + + DIAG_DDR4_CAL_ADDR1 + Calibration address 1 + 8 + + + DIAG_DDR4_CAL_ENABLE_NON_DES + Enable refreshes during calibration + false + + + DIAG_DDR4_CAL_FULL_CAL_ON_RESET + Enable automatic calibration after reset + true + + + DIAG_QDR2_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_QDR2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_QDR2_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + false + + + DIAG_QDR2_INTERFACE_ID + Interface ID + 0 + + + DIAG_QDR2_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_QDR2_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_QDR2_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_QDR2_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_QDR2_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_QDR2_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_QDR2_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_QDR2_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_QDR2_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_QDR2_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_QDR2_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_QDR2_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_QDR2_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_QDR2_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_QDR4_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_QDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_QDR4_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + false + + + DIAG_QDR4_INTERFACE_ID + Interface ID + 0 + + + DIAG_QDR4_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_QDR4_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_QDR4_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_QDR4_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_QDR4_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_QDR4_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_QDR4_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_QDR4_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_QDR4_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_QDR4_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_QDR4_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_QDR4_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_QDR4_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_QDR4_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_QDR4_SKIP_VREF_CAL + Skip VREF_in calibration + false + + + DIAG_RLD2_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_RLD2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_RLD2_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + false + + + DIAG_RLD2_INTERFACE_ID + Interface ID + 0 + + + DIAG_RLD2_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_RLD2_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_RLD2_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_RLD2_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_RLD2_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_RLD2_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_RLD2_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_RLD2_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_RLD2_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_RLD2_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_RLD2_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_RLD2_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_RLD2_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_RLD2_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_RLD3_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_RLD3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_RLD3_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + false + + + DIAG_RLD3_INTERFACE_ID + Interface ID + 0 + + + DIAG_RLD3_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_RLD3_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_RLD3_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_RLD3_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_RLD3_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_RLD3_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_RLD3_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_RLD3_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_RLD3_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_RLD3_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_RLD3_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_RLD3_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + true + + + DIAG_RLD3_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_RLD3_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_RLD3_CA_LEVEL_EN + Enable address/command leveling calibration + true + + + DIAG_RLD3_CA_DESKEW_EN + Enable address/command deskew calibration + true + + + DIAG_LPDDR3_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_LPDDR3_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + false + + + DIAG_LPDDR3_INTERFACE_ID + Interface ID + 0 + + + DIAG_LPDDR3_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_LPDDR3_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_LPDDR3_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_LPDDR3_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_LPDDR3_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_LPDDR3_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_LPDDR3_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_LPDDR3_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_LPDDR3_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_LPDDR3_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_LPDDR3_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_LPDDR3_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_LPDDR3_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_LPDDR3_SKIP_CA_LEVEL + Skip address/command leveling calibration + false + + + DIAG_LPDDR3_SKIP_CA_DESKEW + Skip address/command deskew calibration + false + + + DIAG_DDRT_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_DDRT_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_DDRT_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_DDRT_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_DDRT_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_DDRT_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + false + + + DIAG_DDRT_INTERFACE_ID + Interface ID + 0 + + + DIAG_DDRT_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_DDRT_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_DDRT_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_DDRT_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + true + + + DIAG_DDRT_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_DDRT_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_DDRT_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + true + + + DIAG_DDRT_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + false + + + DIAG_DDRT_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_DDRT_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_DDRT_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_DDRT_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_DDRT_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_DDRT_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_DDRT_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_DDRT_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_DDRT_SKIP_CA_LEVEL + Skip address/command leveling calibration + false + + + DIAG_DDRT_SKIP_CA_DESKEW + Skip address/command deskew calibration + false + + + DIAG_DDRT_SKIP_VREF_CAL + Skip VREF calibration + false + + + DIAG_DDRT_CAL_ADDR0 + PARAM_DIAG_DDRT_CAL_ADDR0_NAME + 0 + + + DIAG_DDRT_CAL_ADDR1 + PARAM_DIAG_DDRT_CAL_ADDR1_NAME + 8 + + + DIAG_DDRT_CAL_ENABLE_NON_DES + PARAM_DIAG_DDRT_CAL_ENABLE_NON_DES_NAME + false + + + DIAG_DDRT_CAL_FULL_CAL_ON_RESET + PARAM_DIAG_DDRT_CAL_FULL_CAL_ON_RESET_NAME + true + + + DIAG_DDRT_ENABLE_ENHANCED_TESTING + Enable enhanced testing + false + + + DIAG_DDRT_ENABLE_DRIVER_MARGINING + Enable driver margining for DDR-T + false + + + NUM_IPS + Number of IPs + 1 + + + EMIF_0_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_0_STORED_PARAM + PARAM_EMIF_0_STORED_PARAM_NAME + + + + EMIF_0_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_1_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_1_STORED_PARAM + PARAM_EMIF_1_STORED_PARAM_NAME + + + + EMIF_1_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_2_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_2_STORED_PARAM + PARAM_EMIF_2_STORED_PARAM_NAME + + + + EMIF_2_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_3_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_3_STORED_PARAM + PARAM_EMIF_3_STORED_PARAM_NAME + + + + EMIF_3_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_4_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_4_STORED_PARAM + PARAM_EMIF_4_STORED_PARAM_NAME + + + + EMIF_4_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_5_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_5_STORED_PARAM + PARAM_EMIF_5_STORED_PARAM_NAME + + + + EMIF_5_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_6_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_6_STORED_PARAM + PARAM_EMIF_6_STORED_PARAM_NAME + + + + EMIF_6_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_7_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_7_STORED_PARAM + PARAM_EMIF_7_STORED_PARAM_NAME + + + + EMIF_7_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_8_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_8_STORED_PARAM + PARAM_EMIF_8_STORED_PARAM_NAME + + + + EMIF_8_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_9_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_9_STORED_PARAM + PARAM_EMIF_9_STORED_PARAM_NAME + + + + EMIF_9_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_10_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_10_STORED_PARAM + PARAM_EMIF_10_STORED_PARAM_NAME + + + + EMIF_10_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_11_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_11_STORED_PARAM + PARAM_EMIF_11_STORED_PARAM_NAME + + + + EMIF_11_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_12_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_12_STORED_PARAM + PARAM_EMIF_12_STORED_PARAM_NAME + + + + EMIF_12_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_13_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_13_STORED_PARAM + PARAM_EMIF_13_STORED_PARAM_NAME + + + + EMIF_13_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_14_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_14_STORED_PARAM + PARAM_EMIF_14_STORED_PARAM_NAME + + + + EMIF_14_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_15_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_15_STORED_PARAM + PARAM_EMIF_15_STORED_PARAM_NAME + + + + EMIF_15_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EX_DESIGN_GUI_DDR3_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDR3_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_DDR3_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_DDR3_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_DDR3_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_DDR3_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR3_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR4_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDR4_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_DDR4_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_DDR4_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_DDR4_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_DDR4_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR4_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR2_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_QDR2_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_QDR2_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_QDR2_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_QDR2_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_QDR2_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR2_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR4_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_QDR4_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_QDR4_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_QDR4_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_QDR4_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_QDR4_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR4_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD2_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_RLD2_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_RLD2_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_RLD2_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_RLD2_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_RLD2_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD2_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD3_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_RLD3_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_RLD3_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_RLD3_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_RLD3_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_RLD3_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD3_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_LPDDR3_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_LPDDR3_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_LPDDR3_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_LPDDR3_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_LPDDR3_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_LPDDR3_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_LPDDR3_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDRT_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDRT_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_DDRT_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_DDRT_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_DDRT_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_DDRT_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDRT_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDRT_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + + + + + device + Device + 1SX280HU2F50E1VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element $system + { + datum _originalDeviceFamily + { + value = "Stratix 10"; + type = "String"; + } + } + element DE10_Pro_QSYS_emif_s10_ddr4_b + { + datum _originalVersion + { + value = "19.1.0"; + type = "String"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + true + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>local_reset_req</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>local_reset_req</name> + <role>local_reset_req</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>local_reset_status</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>local_reset_done</name> + <role>local_reset_done</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>pll_ref_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>pll_ref_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>oct</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>oct_rzqin</name> + <role>oct_rzqin</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>mem_ck</name> + <role>mem_ck</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_ck_n</name> + <role>mem_ck_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_a</name> + <role>mem_a</role> + <direction>Output</direction> + <width>17</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_act_n</name> + <role>mem_act_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_ba</name> + <role>mem_ba</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_bg</name> + <role>mem_bg</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_cke</name> + <role>mem_cke</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_cs_n</name> + <role>mem_cs_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_odt</name> + <role>mem_odt</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_reset_n</name> + <role>mem_reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_par</name> + <role>mem_par</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_alert_n</name> + <role>mem_alert_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_dqs</name> + <role>mem_dqs</role> + <direction>Bidir</direction> + <width>9</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_dqs_n</name> + <role>mem_dqs_n</role> + <direction>Bidir</direction> + <width>9</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_dq</name> + <role>mem_dq</role> + <direction>Bidir</direction> + <width>72</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_dbi_n</name> + <role>mem_dbi_n</role> + <direction>Bidir</direction> + <width>9</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>status</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>local_cal_success</name> + <role>local_cal_success</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>local_cal_fail</name> + <role>local_cal_fail</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>emif_usr_reset_n</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>emif_usr_reset_n</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>none</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>emif_usr_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>emif_usr_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + </entry> + <entry> + <key>clockRate</key> + <value>333333333</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ctrl_ecc_user_interrupt_0</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>ctrl_ecc_user_interrupt_0</name> + <role>ctrl_ecc_user_interrupt</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ctrl_amm_0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>amm_ready_0</name> + <role>waitrequest_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_read_0</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_write_0</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_address_0</name> + <role>address</role> + <direction>Input</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_readdata_0</name> + <role>readdata</role> + <direction>Output</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_writedata_0</name> + <role>writedata</role> + <direction>Input</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_burstcount_0</name> + <role>burstcount</role> + <direction>Input</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_byteenable_0</name> + <role>byteenable</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_readdatavalid_0</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8589934592</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>emif_usr_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>emif_usr_reset_n</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>true</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>64</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>ctrl_amm_0</key> + <value> + <connectionPointName>ctrl_amm_0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='ctrl_amm_0' start='0x0' end='0x200000000' datawidth='512' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>33</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>512</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>emif_usr_clk</key> + <value> + <connectionPointName>emif_usr_clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>333333333</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Intel Corporation + addressAndMemoryMap + addressAndMemoryMap + 1.0 + + + ecc_core.ctrl_amm_0 + + + + + + + + + false + false + + \ No newline at end of file diff --git a/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_iopll_0.ip b/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_iopll_0.ip new file mode 100644 index 0000000..8a04991 --- /dev/null +++ b/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_iopll_0.ip @@ -0,0 +1,2091 @@ + + + + Intel Corporation + DE10_Pro_QSYS_iopll_0 + iopll_0 + 19.3.1 + + + reset + + + + + + + + reset + + + rst + + + + + + + + + associatedClock + Associated clock + + + + synchronousEdges + Synchronous edges + NONE + + + + + + + ui.blockdiagram.direction + input + + + + + + + refclk + + + + + + + + clk + + + refclk + + + + + + + + + clockRate + Clock rate + 50000000 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + input + + + + + + + locked + + + + + + + + export + + + locked + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + outclk0 + + + + + + + + clk + + + outclk_0 + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 50000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + output + + + + + + + outclk1 + + + + + + + + clk + + + outclk_1 + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 200000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + output + + + + + + + outclk2 + + + + + + + + clk + + + outclk_2 + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 200000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + output + + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_iopll + + QUARTUS_SYNTH + + + + + + + rst + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + refclk + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + locked + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + outclk_0 + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + outclk_1 + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + outclk_2 + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + DE10_Pro_QSYS_iopll_0 + altera_iopll + 19.3.1 + + + + + gui_debug_mode + + false + + + gui_skip_sdc_generation + + false + + + gui_include_iossm + + false + + + gui_cal_code_hex_file + + iossm.hex + + + gui_parameter_table_hex_file + + seq_params_sim.hex + + + gui_pll_tclk_mux_en + + false + + + gui_pll_tclk_sel + + pll_tclk_m_src + + + gui_pll_vco_freq_band_0 + + pll_freq_clk0_disabled + + + gui_pll_vco_freq_band_1 + + pll_freq_clk1_disabled + + + gui_pll_freqcal_en + + true + + + gui_pll_freqcal_req_flag + + true + + + gui_cal_converge + + false + + + gui_cal_error + + cal_clean + + + gui_pll_cal_done + + false + + + gui_pll_type + + S10_Simple + + + gui_pll_m_cnt_in_src + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src0 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src1 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src2 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src3 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src4 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src5 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src6 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src7 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src8 + + c_m_cnt_in_src_ph_mux_clk + + + system_info_device_family + Device Family + Stratix 10 + + + system_info_device_component + Component + 1SX280HU2F50E1VG + + + system_info_device_speed_grade + Speed Grade + 1 + + + system_info_device_iobank_rev + IO Bank Revision + + + + system_part_trait_speed_grade + Speed Grade Trait + 1 + + + system_part_trait_iobank_rev + IO Bank Revision Trait + + + + gui_usr_device_speed_grade + Speed Grade + 1 + + + gui_en_reconf + Enable dynamic reconfiguration of PLL + false + + + gui_en_dps_ports + Enable access to dynamic phase shift ports + false + + + gui_pll_mode + PLL Mode + Integer-N PLL + + + gui_location_type + IOPLL Type + I/O Bank + + + gui_use_logical + Use logical PLL + false + + + gui_reference_clock_frequency + Reference Clock Frequency + 50.0 + + + gui_reference_clock_frequency_ps + Reference Clock Frequency + 10000.0 + + + gui_use_coreclk + Refclk source is global clock + false + + + gui_refclk_might_change + My reference clock frequency might change + false + + + gui_fractional_cout + Fractional carry out + 32 + + + gui_prot_mode + prot_mode + UNUSED + + + gui_dsm_out_sel + DSM Order + 1st_order + + + gui_use_locked + Enable locked output port + true + + + gui_en_adv_params + Enable physical output clock parameters + false + + + gui_pll_bandwidth_preset + PLL Bandwidth Preset + Low + + + gui_lock_setting + Lock Threshold Setting + Low Lock Time + + + gui_pll_auto_reset + PLL Auto Reset + false + + + gui_en_lvds_ports + Access to PLL LVDS_CLK/LOADEN output port + Disabled + + + gui_operation_mode + Compensation Mode + normal + + + gui_feedback_clock + Feedback Clock + Global Clock + + + gui_clock_to_compensate + Compensated Outclk + 0 + + + gui_use_NDFB_modes + Use Nondedicated Feedback Path + false + + + gui_refclk_switch + Create a second input clock signal 'refclk1' + false + + + gui_refclk1_frequency + Second Reference Clock Frequency + 100.0 + + + gui_en_phout_ports + Enable access to PLL DPA output port + false + + + gui_phout_division + PLL DPA output division + 1 + + + gui_en_extclkout_ports + Enable access to PLL external clock output port + false + + + gui_number_of_clocks + Number Of Clocks + 3 + + + gui_multiply_factor + Multiply Factor (M-Counter) + 6 + + + gui_divide_factor_n + Divide Factor (N-Counter) + 1 + + + gui_frac_multiply_factor + Fractional Multiply Factor (K) + 1 + + + gui_fix_vco_frequency + Specify VCO frequency + false + + + gui_fixed_vco_frequency + Desired VCO Frequency + 600.0 + + + gui_fixed_vco_frequency_ps + Desired VCO Frequency + 1667.0 + + + gui_vco_frequency + Actual VCO Frequency + 600.0 + + + gui_enable_output_counter_cascading + Enable output counter cascading + false + + + gui_mif_gen_options + MIF Generation Options + Generate New MIF File + + + gui_new_mif_file_path + Path to New MIF file + ~/pll.mif + + + gui_existing_mif_file_path + Path to Existing MIF file + ~/pll.mif + + + gui_mif_config_name + Name of Current Configuration + unnamed + + + gui_active_clk + Create an 'active_clk' signal to indicate the input clock in use + false + + + gui_clk_bad + Create a 'clkbad' signal for each of the input clocks + false + + + gui_switchover_mode + Switchover Mode + Automatic Switchover + + + gui_switchover_delay + Switchover Delay + 0 + + + gui_enable_cascade_out + Create a 'cascade_out' signal to connect to a downstream PLL + false + + + gui_cascade_outclk_index + cascade_out source + 0 + + + gui_enable_cascade_in + Create an 'adjpllin' (cascade in) signal to connect to an upstream PLL through IO Column Cascading + false + + + gui_enable_permit_cal + Connect to an upstream PLL through Core Clock Network Cascading (create a permit_cal input signal) + false + + + gui_pll_cascading_mode + Connection Signal Type to Upstream PLL + adjpllin + + + gui_enable_mif_dps + Enable Dynamic Phase Shift for MIF streaming + false + + + gui_dps_cntr + DPS Counter Selection + C0 + + + gui_dps_num + Number of Dynamic Phase Shifts + 1 + + + gui_dps_dir + Dynamic Phase Shift Direction + Positive + + + gui_extclkout_0_source + extclk_out[0] source + C0 + + + gui_extclkout_1_source + extclk_out[1] source + C0 + + + gui_clock_name_global + Give clocks global names + false + + + gui_clock_name_string0 + Clock Name + outclk0 + + + gui_clock_name_string1 + Clock Name + outclk1 + + + gui_clock_name_string2 + Clock Name + outclk2 + + + gui_clock_name_string3 + Clock Name + outclk3 + + + gui_clock_name_string4 + Clock Name + outclk4 + + + gui_clock_name_string5 + Clock Name + outclk5 + + + gui_clock_name_string6 + Clock Name + outclk6 + + + gui_clock_name_string7 + Clock Name + outclk7 + + + gui_clock_name_string8 + Clock Name + outclk8 + + + gui_clock_name_string9 + Clock Name + outclk9 + + + gui_clock_name_string10 + Clock Name + outclk10 + + + gui_clock_name_string11 + Clock Name + outclk11 + + + gui_clock_name_string12 + Clock Name + outclk12 + + + gui_clock_name_string13 + Clock Name + outclk13 + + + gui_clock_name_string14 + Clock Name + outclk14 + + + gui_clock_name_string15 + Clock Name + outclk15 + + + gui_clock_name_string16 + Clock Name + outclk16 + + + gui_clock_name_string17 + Clock Name + outclk17 + + + gui_divide_factor_c0 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c1 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c2 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c3 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c4 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c5 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c6 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c7 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c8 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c9 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c10 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c11 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c12 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c13 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c14 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c15 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c16 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c17 + Divide Factor (C-Counter) + 6 + + + gui_cascade_counter0 + Make this a cascade counter + false + + + gui_cascade_counter1 + Make this a cascade counter + false + + + gui_cascade_counter2 + Make this a cascade counter + false + + + gui_cascade_counter3 + Make this a cascade counter + false + + + gui_cascade_counter4 + Make this a cascade counter + false + + + gui_cascade_counter5 + Make this a cascade counter + false + + + gui_cascade_counter6 + Make this a cascade counter + false + + + gui_cascade_counter7 + Make this a cascade counter + false + + + gui_cascade_counter8 + Make this a cascade counter + false + + + gui_cascade_counter9 + Make this a cascade counter + false + + + gui_cascade_counter10 + Make this a cascade counter + false + + + gui_cascade_counter11 + Make this a cascade counter + false + + + gui_cascade_counter12 + Make this a cascade counter + false + + + gui_cascade_counter13 + Make this a cascade counter + false + + + gui_cascade_counter14 + Make this a cascade counter + false + + + gui_cascade_counter15 + Make this a cascade counter + false + + + gui_cascade_counter16 + Make this a cascade counter + false + + + gui_cascade_counter17 + Make this a cascade counter + false + + + gui_output_clock_frequency0 + Desired Frequency + 50.0 + + + gui_output_clock_frequency1 + Desired Frequency + 200.0 + + + gui_output_clock_frequency2 + Desired Frequency + 200.0 + + + gui_output_clock_frequency3 + Desired Frequency + 100.0 + + + gui_output_clock_frequency4 + Desired Frequency + 100.0 + + + gui_output_clock_frequency5 + Desired Frequency + 100.0 + + + gui_output_clock_frequency6 + Desired Frequency + 100.0 + + + gui_output_clock_frequency7 + Desired Frequency + 100.0 + + + gui_output_clock_frequency8 + Desired Frequency + 100.0 + + + gui_output_clock_frequency9 + Desired Frequency + 100.0 + + + gui_output_clock_frequency10 + Desired Frequency + 100.0 + + + gui_output_clock_frequency11 + Desired Frequency + 100.0 + + + gui_output_clock_frequency12 + Desired Frequency + 100.0 + + + gui_output_clock_frequency13 + Desired Frequency + 100.0 + + + gui_output_clock_frequency14 + Desired Frequency + 100.0 + + + gui_output_clock_frequency15 + Desired Frequency + 100.0 + + + gui_output_clock_frequency16 + Desired Frequency + 100.0 + + + gui_output_clock_frequency17 + Desired Frequency + 100.0 + + + gui_output_clock_frequency_ps0 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps1 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps2 + Desired Frequency + 5000.0 + + + gui_output_clock_frequency_ps3 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps4 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps5 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps6 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps7 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps8 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps9 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps10 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps11 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps12 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps13 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps14 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps15 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps16 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps17 + Desired Frequency + 10000.0 + + + gui_ps_units0 + Phase Shift Units + ps + + + gui_ps_units1 + Phase Shift Units + ps + + + gui_ps_units2 + Phase Shift Units + ps + + + gui_ps_units3 + Phase Shift Units + ps + + + gui_ps_units4 + Phase Shift Units + ps + + + gui_ps_units5 + Phase Shift Units + ps + + + gui_ps_units6 + Phase Shift Units + ps + + + gui_ps_units7 + Phase Shift Units + ps + + + gui_ps_units8 + Phase Shift Units + ps + + + gui_ps_units9 + Phase Shift Units + ps + + + gui_ps_units10 + Phase Shift Units + ps + + + gui_ps_units11 + Phase Shift Units + ps + + + gui_ps_units12 + Phase Shift Units + ps + + + gui_ps_units13 + Phase Shift Units + ps + + + gui_ps_units14 + Phase Shift Units + ps + + + gui_ps_units15 + Phase Shift Units + ps + + + gui_ps_units16 + Phase Shift Units + ps + + + gui_ps_units17 + Phase Shift Units + ps + + + gui_phase_shift0 + Desired Phase Shift + 0.0 + + + gui_phase_shift1 + Desired Phase Shift + 0.0 + + + gui_phase_shift2 + Desired Phase Shift + 0.0 + + + gui_phase_shift3 + Desired Phase Shift + 0.0 + + + gui_phase_shift4 + Desired Phase Shift + 0.0 + + + gui_phase_shift5 + Desired Phase Shift + 0.0 + + + gui_phase_shift6 + Desired Phase Shift + 0.0 + + + gui_phase_shift7 + Desired Phase Shift + 0.0 + + + gui_phase_shift8 + Desired Phase Shift + 0.0 + + + gui_phase_shift9 + Desired Phase Shift + 0.0 + + + gui_phase_shift10 + Desired Phase Shift + 0.0 + + + gui_phase_shift11 + Desired Phase Shift + 0.0 + + + gui_phase_shift12 + Desired Phase Shift + 0.0 + + + gui_phase_shift13 + Desired Phase Shift + 0.0 + + + gui_phase_shift14 + Desired Phase Shift + 0.0 + + + gui_phase_shift15 + Desired Phase Shift + 0.0 + + + gui_phase_shift16 + Desired Phase Shift + 0.0 + + + gui_phase_shift17 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg0 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg1 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg2 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg3 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg4 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg5 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg6 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg7 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg8 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg9 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg10 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg11 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg12 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg13 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg14 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg15 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg16 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg17 + Desired Phase Shift + 0.0 + + + gui_duty_cycle0 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle1 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle2 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle3 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle4 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle5 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle6 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle7 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle8 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle9 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle10 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle11 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle12 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle13 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle14 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle15 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle16 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle17 + Desired Duty Cycle + 50.0 + + + hp_qsys_scripting_mode + hp_qsys_scripting_mode + false + + + + + + + embeddedsw.dts.compatible + altr,pll + + + embeddedsw.dts.group + clock + + + embeddedsw.dts.vendor + altr + + + + + + + device + Device + 1SX280HU2F50E1VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 1 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element $system + { + datum _originalDeviceFamily + { + value = "Stratix 10"; + type = "String"; + } + } + element iopll_0 + { + datum _originalVersion + { + value = "19.1"; + type = "String"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>ui.blockdiagram.direction</key> + <value>input</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>refclk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>refclk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>ui.blockdiagram.direction</key> + <value>input</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>50000000</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>locked</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>locked</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>ui.blockdiagram.direction</key> + <value>output</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>outclk0</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>outclk_0</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>ui.blockdiagram.direction</key> + <value>output</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + </entry> + <entry> + <key>clockRate</key> + <value>50000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>outclk1</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>outclk_1</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>ui.blockdiagram.direction</key> + <value>output</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + </entry> + <entry> + <key>clockRate</key> + <value>200000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>outclk2</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>outclk_2</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>ui.blockdiagram.direction</key> + <value>output</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + </entry> + <entry> + <key>clockRate</key> + <value>200000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>outclk0</key> + <value> + <connectionPointName>outclk0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>50000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>outclk1</key> + <value> + <connectionPointName>outclk1</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>200000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>outclk2</key> + <value> + <connectionPointName>outclk2</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>200000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_jtag_uart_0.ip b/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_jtag_uart_0.ip new file mode 100644 index 0000000..32aa1b3 --- /dev/null +++ b/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_jtag_uart_0.ip @@ -0,0 +1,1299 @@ + + + + Intel Corporation + DE10_Pro_QSYS_jtag_uart_0 + jtag_uart_0 + 19.1.0 + + + clk + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clk + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + avalon_jtag_slave + + + + + + + + chipselect + + + av_chipselect + + + + + address + + + av_address + + + + + read_n + + + av_read_n + + + + + readdata + + + av_readdata + + + + + write_n + + + av_write_n + + + + + writedata + + + av_writedata + + + + + waitrequest + + + av_waitrequest + + + + + + + + + addressAlignment + Agent addressing + NATIVE + + + addressGroup + Address group + 0 + + + addressSpan + Address span + 2 + + + addressUnits + Address units + WORDS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + clk + + + associatedReset + Associated reset + reset + + + bitsPerSymbol + Bits per symbol + 8 + + + bridgedAddressOffset + Bridged Address Offset + 0 + + + bridgesToMaster + Bridges to host + + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + explicitAddressSpan + Explicit address span + 0 + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isBigEndian + Big endian + false + + + isFlash + Flash memory + false + + + isMemoryDevice + Memory device + false + + + isNonVolatileStorage + Non-volatile storage + false + + + linewrapBursts + Linewrap bursts + false + + + maximumPendingReadTransactions + Maximum pending read transactions + 0 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + minimumUninterruptedRunLength + Minimum uninterrupted run length + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + printableDevice + Can receive stdout/stderr + true + + + readLatency + Read latency + 0 + + + readWaitStates + Read wait states + 1 + + + readWaitTime + Read wait + 1 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + transparentBridge + Transparent bridge + false + + + waitrequestAllowance + Waitrequest allowance + 0 + + + wellBehavedWaitrequest + Well-behaved waitrequest + false + + + writeLatency + Write latency + 0 + + + writeWaitStates + Write wait states + 0 + + + writeWaitTime + Write wait + 0 + + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 1 + + + + + + + irq + + + + + + + + irq + + + av_irq + + + + + + + + + associatedAddressablePoint + Associated addressable interface + DE10_Pro_QSYS_jtag_uart_0.avalon_jtag_slave + + + associatedClock + Associated clock + clk + + + associatedReset + Associated reset + reset + + + bridgedReceiverOffset + Bridged receiver offset + 0 + + + bridgesToReceiver + Bridges to receiver + + + + irqScheme + Interrupt scheme + NONE + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_avalon_jtag_uart + + QUARTUS_SYNTH + + + + + + + clk + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_chipselect + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_address + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_read_n + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_readdata + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + av_write_n + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_writedata + + in + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + av_waitrequest + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_irq + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + DE10_Pro_QSYS_jtag_uart_0 + altera_avalon_jtag_uart + 19.1.0 + + + + + allowMultipleConnections + Allow multiple connections to Avalon JTAG slave + false + + + hubInstanceID + hubInstanceID + 0 + + + readBufferDepth + Buffer depth (bytes) + 64 + + + readIRQThreshold + IRQ threshold + 8 + + + simInputCharacterStream + Contents + + + + simInteractiveOptions + Options + NO_INTERACTIVE_WINDOWS + + + useRegistersForReadBuffer + Construct using registers instead of memory blocks + false + + + useRegistersForWriteBuffer + Construct using registers instead of memory blocks + false + + + useRelativePathForSimFile + useRelativePathForSimFile + false + + + writeBufferDepth + Buffer depth (bytes) + 64 + + + writeIRQThreshold + IRQ threshold + 8 + + + clkFreq + clkFreq + 50000000 + + + avalonSpec + avalonSpec + 2.0 + + + + + + + embeddedsw.CMacro.READ_DEPTH + 64 + + + embeddedsw.CMacro.READ_THRESHOLD + 8 + + + embeddedsw.CMacro.WRITE_DEPTH + 64 + + + embeddedsw.CMacro.WRITE_THRESHOLD + 8 + + + embeddedsw.dts.compatible + altr,juart-1.0 + + + embeddedsw.dts.group + serial + + + embeddedsw.dts.name + juart + + + embeddedsw.dts.vendor + altr + + + + + + + device + Device + 1SX280HU2F50E1VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 1 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element $system + { + datum _originalDeviceFamily + { + value = "Stratix 10"; + type = "String"; + } + } + element jtag_uart_0 + { + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>avalon_jtag_slave</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>av_chipselect</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_read_n</name> + <role>read_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_write_n</name> + <role>write_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>1</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>2</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>true</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt; +&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt; + &lt;peripherals&gt; + &lt;peripheral&gt; + &lt;name&gt;altera_avalon_jtag_uart&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt; + &lt;addressBlock&gt; + &lt;offset&gt;0x0&lt;/offset&gt; + &lt;size&gt;8&lt;/size&gt; + &lt;usage&gt;registers&lt;/usage&gt; + &lt;/addressBlock&gt; + &lt;registers&gt; + &lt;register&gt; + &lt;name&gt;DATA&lt;/name&gt; + &lt;displayName&gt;Data&lt;/displayName&gt; + &lt;description&gt;Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost.&lt;/description&gt; + &lt;addressOffset&gt;0x0&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;data&lt;/name&gt; + &lt;description&gt;The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;8&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;rvalid&lt;/name&gt; + &lt;description&gt;Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined.&lt;/description&gt; + &lt;bitOffset&gt;0xf&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;ravail&lt;/name&gt; + &lt;description&gt;The number of characters remaining in the read FIFO (after the current read).&lt;/description&gt; + &lt;bitOffset&gt;0x10&lt;/bitOffset&gt; + &lt;bitWidth&gt;16&lt;/bitWidth&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;CONTROL&lt;/name&gt; + &lt;displayName&gt;Control&lt;/displayName&gt; + &lt;description&gt;Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit.&lt;/description&gt; + &lt;addressOffset&gt;0x4&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;re&lt;/name&gt; + &lt;description&gt;Interrupt-enable bit for read interrupts.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;we&lt;/name&gt; + &lt;description&gt;Interrupt-enable bit for write interrupts&lt;/description&gt; + &lt;bitOffset&gt;0x1&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;ri&lt;/name&gt; + &lt;description&gt;Indicates that the read interrupt is pending.&lt;/description&gt; + &lt;bitOffset&gt;0x8&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;wi&lt;/name&gt; + &lt;description&gt;Indicates that the write interrupt is pending.&lt;/description&gt; + &lt;bitOffset&gt;0x9&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;ac&lt;/name&gt; + &lt;description&gt;Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0.&lt;/description&gt; + &lt;bitOffset&gt;0xa&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;wspace&lt;/name&gt; + &lt;description&gt;The number of spaces available in the write FIFO&lt;/description&gt; + &lt;bitOffset&gt;0x10&lt;/bitOffset&gt; + &lt;bitWidth&gt;16&lt;/bitWidth&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;/registers&gt; + &lt;/peripheral&gt; + &lt;/peripherals&gt; +&lt;/device&gt; </cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars/> + </cmsisInfo> + </interface> + <interface> + <name>irq</name> + <type>interrupt</type> + <isStart>false</isStart> + <ports> + <port> + <name>av_irq</name> + <role>irq</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + <value>DE10_Pro_QSYS_jtag_uart_0.avalon_jtag_slave</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bridgedReceiverOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToReceiver</key> + </entry> + <entry> + <key>irqScheme</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>avalon_jtag_slave</key> + <value> + <connectionPointName>avalon_jtag_slave</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='avalon_jtag_slave' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>50000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_mm_clock_crossing_bridge_50m.ip b/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_mm_clock_crossing_bridge_50m.ip new file mode 100644 index 0000000..ce6651e --- /dev/null +++ b/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_mm_clock_crossing_bridge_50m.ip @@ -0,0 +1,1984 @@ + + + + Intel Corporation + DE10_Pro_QSYS_mm_clock_crossing_bridge_50m + DE10_Pro_QSYS_mm_clock_crossing_bridge_50m + 19.2.0 + + + m0_clk + + + + + + + + clk + + + m0_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + m0_reset + + + + + + + + reset + + + m0_reset + + + + + + + + + associatedClock + Associated clock + m0_clk + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + s0_clk + + + + + + + + clk + + + s0_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + s0_reset + + + + + + + + reset + + + s0_reset + + + + + + + + + associatedClock + Associated clock + s0_clk + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + s0 + + + + + + + + waitrequest + + + s0_waitrequest + + + + + readdata + + + s0_readdata + + + + + readdatavalid + + + s0_readdatavalid + + + + + burstcount + + + s0_burstcount + + + + + writedata + + + s0_writedata + + + + + address + + + s0_address + + + + + write + + + s0_write + + + + + read + + + s0_read + + + + + byteenable + + + s0_byteenable + + + + + debugaccess + + + s0_debugaccess + + + + + + + + + addressAlignment + Agent addressing + DYNAMIC + + + addressGroup + Address group + 0 + + + addressSpan + Address span + 8 + + + addressUnits + Address units + SYMBOLS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + s0_clk + + + associatedReset + Associated reset + s0_reset + + + bitsPerSymbol + Bits per symbol + 8 + + + bridgedAddressOffset + Bridged Address Offset + 0 + + + bridgesToMaster + Bridges to host + DE10_Pro_QSYS_mm_clock_crossing_bridge_50m.m0 + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + explicitAddressSpan + Explicit address span + 0 + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isBigEndian + Big endian + false + + + isFlash + Flash memory + false + + + isMemoryDevice + Memory device + false + + + isNonVolatileStorage + Non-volatile storage + false + + + linewrapBursts + Linewrap bursts + false + + + maximumPendingReadTransactions + Maximum pending read transactions + 8 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + minimumUninterruptedRunLength + Minimum uninterrupted run length + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + printableDevice + Can receive stdout/stderr + false + + + readLatency + Read latency + 0 + + + readWaitStates + Read wait states + 0 + + + readWaitTime + Read wait + 0 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + transparentBridge + Transparent bridge + false + + + waitrequestAllowance + Waitrequest allowance + 0 + + + wellBehavedWaitrequest + Well-behaved waitrequest + false + + + writeLatency + Write latency + 0 + + + writeWaitStates + Write wait states + 0 + + + writeWaitTime + Write wait + 0 + + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + + + + + m0 + + + + + + + + waitrequest + + + m0_waitrequest + + + + + readdata + + + m0_readdata + + + + + readdatavalid + + + m0_readdatavalid + + + + + burstcount + + + m0_burstcount + + + + + writedata + + + m0_writedata + + + + + address + + + m0_address + + + + + write + + + m0_write + + + + + read + + + m0_read + + + + + byteenable + + + m0_byteenable + + + + + debugaccess + + + m0_debugaccess + + + + + + + + + adaptsTo + Adapts to + + + + addressGroup + Address group + 0 + + + addressUnits + Address units + SYMBOLS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + m0_clk + + + associatedReset + Associated reset + m0_reset + + + bitsPerSymbol + Bits per symbol + 8 + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + dBSBigEndian + dBS big endian + false + + + doStreamReads + Use flow control for read transfers + false + + + doStreamWrites + Use flow control for write transfers + false + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isAsynchronous + Is asynchronous + false + + + isBigEndian + Is big endian + false + + + isReadable + Is readable + false + + + isWriteable + Is writeable + false + + + linewrapBursts + Linewrap bursts + false + + + maxAddressWidth + Maximum address width + 32 + + + maximumPendingReadTransactions + Maximum pending read transactions + 0 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + readLatency + Read latency + 0 + + + readWaitTime + Read wait + 1 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + waitrequestAllowance + Waitrequest allowance + 0 + + + writeWaitTime + Write wait + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + mm_ccb + + QUARTUS_SYNTH + + + + + + + m0_clk + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_reset + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_clk + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_reset + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_waitrequest + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_readdata + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_readdatavalid + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_burstcount + + in + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_writedata + + in + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_address + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_write + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_read + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_byteenable + + in + + + 0 + 3 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_debugaccess + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_waitrequest + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_readdata + + in + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_readdatavalid + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_burstcount + + out + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_writedata + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_address + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_write + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_read + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_byteenable + + out + + + 0 + 3 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_debugaccess + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + DE10_Pro_QSYS_mm_clock_crossing_bridge_50m + mm_ccb + 19.2.0 + + + + + DATA_WIDTH + Data width + 32 + + + SYMBOL_WIDTH + Symbol width + 8 + + + ADDRESS_WIDTH + Address width + 10 + + + SYSINFO_ADDR_WIDTH + SYSINFO_ADDR_WIDTH + 3 + + + USE_AUTO_ADDRESS_WIDTH + Use automatically-determined address width + 1 + + + ADDRESS_UNITS + Address units + SYMBOLS + + + MAX_BURST_SIZE + Maximum burst size (words) + 1 + + + COMMAND_FIFO_DEPTH + Command FIFO depth + 4 + + + RESPONSE_FIFO_DEPTH + Response FIFO depth + 4 + + + MASTER_SYNC_DEPTH + Master clock domain synchronizer depth + 2 + + + SLAVE_SYNC_DEPTH + Slave clock domain synchronizer depth + 2 + + + SYNC_RESET + Use synchronous resets + 0 + + + + + + + device + Device + 1SX280HU2F50E1VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 1 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element $system + { + datum _originalDeviceFamily + { + value = "Stratix 10"; + type = "String"; + } + } + element DE10_Pro_QSYS_mm_clock_crossing_bridge_50m + { + datum _originalVersion + { + value = "19.1"; + type = "String"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>m0_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>m0_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>m0_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>m0_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>m0_clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>s0_clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_burstcount</name> + <role>burstcount</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_address</name> + <role>address</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_debugaccess</name> + <role>debugaccess</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>s0_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>s0_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + <value>DE10_Pro_QSYS_mm_clock_crossing_bridge_50m.m0</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>8</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>m0</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>m0_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_burstcount</name> + <role>burstcount</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_address</name> + <role>address</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_debugaccess</name> + <role>debugaccess</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>m0_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>m0_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>m0</key> + <value> + <connectionPointName>m0</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>s0</key> + <value> + <connectionPointName>s0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_mm_clockcross_DDR4.ip b/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_mm_clockcross_DDR4.ip new file mode 100644 index 0000000..2bf2916 --- /dev/null +++ b/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_mm_clockcross_DDR4.ip @@ -0,0 +1,1994 @@ + + + + Intel Corporation + DE10_Pro_QSYS_mm_clockcross_DDR4 + DE10_Pro_QSYS_mm_clockcross_DDR4 + 19.2.0 + + + m0_clk + + + + + + + + clk + + + m0_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + m0_reset + + + + + + + + reset + + + m0_reset + + + + + + + + + associatedClock + Associated clock + m0_clk + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + s0_clk + + + + + + + + clk + + + s0_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + s0_reset + + + + + + + + reset + + + s0_reset + + + + + + + + + associatedClock + Associated clock + s0_clk + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + s0 + + + + + + + + waitrequest + + + s0_waitrequest + + + + + readdata + + + s0_readdata + + + + + readdatavalid + + + s0_readdatavalid + + + + + burstcount + + + s0_burstcount + + + + + writedata + + + s0_writedata + + + + + address + + + s0_address + + + + + write + + + s0_write + + + + + read + + + s0_read + + + + + byteenable + + + s0_byteenable + + + + + debugaccess + + + s0_debugaccess + + + + + + + + + addressAlignment + Agent addressing + DYNAMIC + + + addressGroup + Address group + 0 + + + addressSpan + Address span + 8589934592 + + + addressUnits + Address units + WORDS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + s0_clk + + + associatedReset + Associated reset + s0_reset + + + bitsPerSymbol + Bits per symbol + 8 + + + bridgedAddressOffset + Bridged Address Offset + 0 + + + bridgesToMaster + Bridges to host + DE10_Pro_QSYS_mm_clockcross_DDR4.m0 + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + explicitAddressSpan + Explicit address span + 0 + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isBigEndian + Big endian + false + + + isFlash + Flash memory + false + + + isMemoryDevice + Memory device + false + + + isNonVolatileStorage + Non-volatile storage + false + + + linewrapBursts + Linewrap bursts + false + + + maximumPendingReadTransactions + Maximum pending read transactions + 64 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + minimumUninterruptedRunLength + Minimum uninterrupted run length + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + printableDevice + Can receive stdout/stderr + false + + + readLatency + Read latency + 0 + + + readWaitStates + Read wait states + 0 + + + readWaitTime + Read wait + 0 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + transparentBridge + Transparent bridge + false + + + waitrequestAllowance + Waitrequest allowance + 0 + + + wellBehavedWaitrequest + Well-behaved waitrequest + false + + + writeLatency + Write latency + 0 + + + writeWaitStates + Write wait states + 0 + + + writeWaitTime + Write wait + 0 + + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + + + + + m0 + + + + + + + + waitrequest + + + m0_waitrequest + + + + + readdata + + + m0_readdata + + + + + readdatavalid + + + m0_readdatavalid + + + + + burstcount + + + m0_burstcount + + + + + writedata + + + m0_writedata + + + + + address + + + m0_address + + + + + write + + + m0_write + + + + + read + + + m0_read + + + + + byteenable + + + m0_byteenable + + + + + debugaccess + + + m0_debugaccess + + + + + + + + + adaptsTo + Adapts to + + + + addressGroup + Address group + 0 + + + addressUnits + Address units + WORDS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + m0_clk + + + associatedReset + Associated reset + m0_reset + + + bitsPerSymbol + Bits per symbol + 8 + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + dBSBigEndian + dBS big endian + false + + + doStreamReads + Use flow control for read transfers + false + + + doStreamWrites + Use flow control for write transfers + false + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isAsynchronous + Is asynchronous + false + + + isBigEndian + Is big endian + false + + + isReadable + Is readable + false + + + isWriteable + Is writeable + false + + + linewrapBursts + Linewrap bursts + false + + + maxAddressWidth + Maximum address width + 32 + + + maximumPendingReadTransactions + Maximum pending read transactions + 0 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + readLatency + Read latency + 0 + + + readWaitTime + Read wait + 1 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + waitrequestAllowance + Waitrequest allowance + 0 + + + writeWaitTime + Write wait + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + mm_ccb + + QUARTUS_SYNTH + + + + + + + m0_clk + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_reset + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_clk + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_reset + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_waitrequest + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_readdata + + out + + + 0 + 511 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_readdatavalid + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_burstcount + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_writedata + + in + + + 0 + 511 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_address + + in + + + 0 + 26 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_write + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_read + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_byteenable + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_debugaccess + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_waitrequest + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_readdata + + in + + + 0 + 511 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_readdatavalid + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_burstcount + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_writedata + + out + + + 0 + 511 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_address + + out + + + 0 + 26 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_write + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_read + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_byteenable + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_debugaccess + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + DE10_Pro_QSYS_mm_clockcross_DDR4 + mm_ccb + 19.2.0 + + + + + DATA_WIDTH + Data width + 512 + + + SYMBOL_WIDTH + Symbol width + 8 + + + ADDRESS_WIDTH + Address width + 26 + + + SYSINFO_ADDR_WIDTH + SYSINFO_ADDR_WIDTH + 33 + + + USE_AUTO_ADDRESS_WIDTH + Use automatically-determined address width + 1 + + + ADDRESS_UNITS + Address units + WORDS + + + MAX_BURST_SIZE + Maximum burst size (words) + 4 + + + COMMAND_FIFO_DEPTH + Command FIFO depth + 32 + + + RESPONSE_FIFO_DEPTH + Response FIFO depth + 32 + + + MASTER_SYNC_DEPTH + Master clock domain synchronizer depth + 2 + + + SLAVE_SYNC_DEPTH + Slave clock domain synchronizer depth + 2 + + + SYNC_RESET + Use synchronous resets + 0 + + + + + + + device + Device + 1SX280HU2F50E1VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 1 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element $system + { + datum _originalDeviceFamily + { + value = "Stratix 10"; + type = "String"; + } + } + element DE10_Pro_QSYS_mm_clockcross_DDR4 + { + datum _originalVersion + { + value = "19.1"; + type = "String"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>m0_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>m0_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>m0_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>m0_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>m0_clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>s0_clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_burstcount</name> + <role>burstcount</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_address</name> + <role>address</role> + <direction>Input</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_debugaccess</name> + <role>debugaccess</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8589934592</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>s0_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>s0_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + <value>DE10_Pro_QSYS_mm_clockcross_DDR4.m0</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>64</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>m0</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>m0_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_burstcount</name> + <role>burstcount</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_address</name> + <role>address</role> + <direction>Output</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_debugaccess</name> + <role>debugaccess</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>m0_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>m0_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>m0</key> + <value> + <connectionPointName>m0</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_WIDTH</key> + <value>33</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>s0</key> + <value> + <connectionPointName>s0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_pio_0.ip b/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_pio_0.ip new file mode 100644 index 0000000..d1eb102 --- /dev/null +++ b/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_pio_0.ip @@ -0,0 +1,726 @@ + + + Intel Corporation + DE10_Pro_QSYS_pio_0 + pio_0 + 19.1 + + + clk + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + reset_n + + + + + + + + + associatedClock + Associated clock + clk + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + s1 + + + + + + + + address + + + address + + + + + readdata + + + readdata + + + + + + + + + addressAlignment + Slave addressing + NATIVE + + + addressGroup + Address group + 0 + + + addressSpan + Address span + 4 + + + addressUnits + Address units + WORDS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + clk + + + associatedReset + Associated reset + reset + + + bitsPerSymbol + Bits per symbol + 8 + + + bridgedAddressOffset + Bridged Address Offset + 0 + + + bridgesToMaster + Bridges to master + + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + explicitAddressSpan + Explicit address span + 0 + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isBigEndian + Big endian + false + + + isFlash + Flash memory + false + + + isMemoryDevice + Memory device + false + + + isNonVolatileStorage + Non-volatile storage + false + + + linewrapBursts + Linewrap bursts + false + + + maximumPendingReadTransactions + Maximum pending read transactions + 0 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + minimumUninterruptedRunLength + Minimum uninterrupted run length + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + printableDevice + Can receive stdout/stderr + false + + + readLatency + Read latency + 0 + + + readWaitStates + Read wait states + 1 + + + readWaitTime + Read wait + 1 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + transparentBridge + Transparent bridge + false + + + waitrequestAllowance + Waitrequest allowance + 0 + + + wellBehavedWaitrequest + Well-behaved waitrequest + false + + + writeLatency + Write latency + 0 + + + writeWaitStates + Write wait states + 0 + + + writeWaitTime + Write wait + 0 + + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + + + + + external_connection + + + + + + + + export + + + in_port + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_avalon_pio + + QUARTUS_SYNTH + + + + + + + clk + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + reset_n + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + address + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + readdata + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + in_port + + in + + + 0 + 11 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + DE10_Pro_QSYS_pio_0 + altera_avalon_pio + 19.1 + + + + + bitClearingEdgeCapReg + Enable bit-clearing for edge capture register + false + + + bitModifyingOutReg + Enable individual bit setting/clearing + false + + + captureEdge + Synchronously capture + false + + + direction + Direction + Input + + + edgeType + Edge Type + RISING + + + generateIRQ + Generate IRQ + false + + + irqType + IRQ Type + LEVEL + + + resetValue + Output Port Reset Value + 0 + + + simDoTestBenchWiring + Hardwire PIO inputs in test bench + false + + + simDrivenValue + Drive inputs to field. + 0 + + + width + Width (1-32 bits) + 12 + + + clockRate + clockRate + 50000000 + + + derived_has_tri + derived_has_tri + false + + + derived_has_out + derived_has_out + false + + + derived_has_in + derived_has_in + true + + + derived_do_test_bench_wiring + derived_do_test_bench_wiring + false + + + derived_capture + derived_capture + false + + + derived_edge_type + derived_edge_type + NONE + + + derived_irq_type + derived_irq_type + NONE + + + derived_has_irq + derived_has_irq + false + + + + + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 12 + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0 + + + embeddedsw.CMacro.EDGE_TYPE + NONE + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.HAS_IN + 1 + + + embeddedsw.CMacro.HAS_OUT + 0 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.IRQ_TYPE + NONE + + + embeddedsw.CMacro.RESET_VALUE + 0 + + + embeddedsw.dts.compatible + altr,pio-1.0 + + + embeddedsw.dts.group + gpio + + + embeddedsw.dts.name + pio + + + embeddedsw.dts.params.altr,gpio-bank-width + 12 + + + embeddedsw.dts.params.resetvalue + 0 + + + embeddedsw.dts.vendor + altr + + + + + + + device + Device + 1SX280HU2F50E1VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 1 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData { element $system { datum _originalDeviceFamily { value = "Stratix 10"; type = "String"; } } element pio_0 { } } + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> <interfaces> <interface> <name>clk</name> <type>clock</type> <isStart>false</isStart> <ports> <port> <name>clk</name> <role>clk</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>clockRate</key> <value>0</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>reset</name> <type>reset</type> <isStart>false</isStart> <ports> <port> <name>reset_n</name> <role>reset_n</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> <value>clk</value> </entry> <entry> <key>synchronousEdges</key> <value>DEASSERT</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>s1</name> <type>avalon</type> <isStart>false</isStart> <ports> <port> <name>address</name> <role>address</role> <direction>Input</direction> <width>2</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> <port> <name>readdata</name> <role>readdata</role> <direction>Output</direction> <width>32</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> </ports> <assignments> <assignmentValueMap> <entry> <key>embeddedsw.configuration.isFlash</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isMemoryDevice</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isNonVolatileStorage</key> <value>0</value> </entry> <entry> <key>embeddedsw.configuration.isPrintableDevice</key> <value>0</value> </entry> </assignmentValueMap> </assignments> <parameters> <parameterValueMap> <entry> <key>addressAlignment</key> <value>NATIVE</value> </entry> <entry> <key>addressGroup</key> <value>0</value> </entry> <entry> <key>addressSpan</key> <value>4</value> </entry> <entry> <key>addressUnits</key> <value>WORDS</value> </entry> <entry> <key>alwaysBurstMaxBurst</key> <value>false</value> </entry> <entry> <key>associatedClock</key> <value>clk</value> </entry> <entry> <key>associatedReset</key> <value>reset</value> </entry> <entry> <key>bitsPerSymbol</key> <value>8</value> </entry> <entry> <key>bridgedAddressOffset</key> <value>0</value> </entry> <entry> <key>bridgesToMaster</key> </entry> <entry> <key>burstOnBurstBoundariesOnly</key> <value>false</value> </entry> <entry> <key>burstcountUnits</key> <value>WORDS</value> </entry> <entry> <key>constantBurstBehavior</key> <value>false</value> </entry> <entry> <key>explicitAddressSpan</key> <value>0</value> </entry> <entry> <key>holdTime</key> <value>0</value> </entry> <entry> <key>interleaveBursts</key> <value>false</value> </entry> <entry> <key>isBigEndian</key> <value>false</value> </entry> <entry> <key>isFlash</key> <value>false</value> </entry> <entry> <key>isMemoryDevice</key> <value>false</value> </entry> <entry> <key>isNonVolatileStorage</key> <value>false</value> </entry> <entry> <key>linewrapBursts</key> <value>false</value> </entry> <entry> <key>maximumPendingReadTransactions</key> <value>0</value> </entry> <entry> <key>maximumPendingWriteTransactions</key> <value>0</value> </entry> <entry> <key>minimumReadLatency</key> <value>1</value> </entry> <entry> <key>minimumResponseLatency</key> <value>1</value> </entry> <entry> <key>minimumUninterruptedRunLength</key> <value>1</value> </entry> <entry> <key>prSafe</key> <value>false</value> </entry> <entry> <key>printableDevice</key> <value>false</value> </entry> <entry> <key>readLatency</key> <value>0</value> </entry> <entry> <key>readWaitStates</key> <value>1</value> </entry> <entry> <key>readWaitTime</key> <value>1</value> </entry> <entry> <key>registerIncomingSignals</key> <value>false</value> </entry> <entry> <key>registerOutgoingSignals</key> <value>false</value> </entry> <entry> <key>setupTime</key> <value>0</value> </entry> <entry> <key>timingUnits</key> <value>Cycles</value> </entry> <entry> <key>transparentBridge</key> <value>false</value> </entry> <entry> <key>waitrequestAllowance</key> <value>0</value> </entry> <entry> <key>wellBehavedWaitrequest</key> <value>false</value> </entry> <entry> <key>writeLatency</key> <value>0</value> </entry> <entry> <key>writeWaitStates</key> <value>0</value> </entry> <entry> <key>writeWaitTime</key> <value>0</value> </entry> </parameterValueMap> </parameters> <cmsisInfo> <cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt; &lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt; &lt;peripherals&gt; &lt;peripheral&gt; &lt;name&gt;altera_avalon_pio&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt; &lt;addressBlock&gt; &lt;offset&gt;0x0&lt;/offset&gt; &lt;size&gt;32&lt;/size&gt; &lt;usage&gt;registers&lt;/usage&gt; &lt;/addressBlock&gt; &lt;registers&gt; &lt;register&gt; &lt;name&gt;DATA&lt;/name&gt; &lt;displayName&gt;Data&lt;/displayName&gt; &lt;description&gt;Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).&lt;/description&gt; &lt;addressOffset&gt;0x0&lt;/addressOffset&gt; &lt;size&gt;32&lt;/size&gt; &lt;access&gt;read-write&lt;/access&gt; &lt;resetValue&gt;0x0&lt;/resetValue&gt; &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; &lt;fields&gt; &lt;field&gt;&lt;name&gt;data&lt;/name&gt; &lt;description&gt;Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.&lt;/description&gt; &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; &lt;bitWidth&gt;32&lt;/bitWidth&gt; &lt;access&gt;read-write&lt;/access&gt; &lt;/field&gt; &lt;/fields&gt; &lt;/register&gt; &lt;register&gt; &lt;name&gt;DIRECTION&lt;/name&gt; &lt;displayName&gt;Direction&lt;/displayName&gt; &lt;description&gt;The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.&lt;/description&gt; &lt;addressOffset&gt;0x4&lt;/addressOffset&gt; &lt;size&gt;32&lt;/size&gt; &lt;access&gt;read-write&lt;/access&gt; &lt;resetValue&gt;0x0&lt;/resetValue&gt; &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; &lt;fields&gt; &lt;field&gt;&lt;name&gt;direction&lt;/name&gt; &lt;description&gt;Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.&lt;/description&gt; &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; &lt;bitWidth&gt;32&lt;/bitWidth&gt; &lt;access&gt;read-write&lt;/access&gt; &lt;/field&gt; &lt;/fields&gt; &lt;/register&gt; &lt;register&gt; &lt;name&gt;IRQ_MASK&lt;/name&gt; &lt;displayName&gt;Interrupt mask&lt;/displayName&gt; &lt;description&gt;Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.&lt;/description&gt; &lt;addressOffset&gt;0x8&lt;/addressOffset&gt; &lt;size&gt;32&lt;/size&gt; &lt;access&gt;read-write&lt;/access&gt; &lt;resetValue&gt;0x0&lt;/resetValue&gt; &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; &lt;fields&gt; &lt;field&gt;&lt;name&gt;interruptmask&lt;/name&gt; &lt;description&gt;IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.&lt;/description&gt; &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; &lt;bitWidth&gt;32&lt;/bitWidth&gt; &lt;access&gt;read-write&lt;/access&gt; &lt;/field&gt; &lt;/fields&gt; &lt;/register&gt; &lt;register&gt; &lt;name&gt;EDGE_CAP&lt;/name&gt; &lt;displayName&gt;Edge capture&lt;/displayName&gt; &lt;description&gt;Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.&lt;/description&gt; &lt;addressOffset&gt;0xc&lt;/addressOffset&gt; &lt;size&gt;32&lt;/size&gt; &lt;access&gt;read-write&lt;/access&gt; &lt;resetValue&gt;0x0&lt;/resetValue&gt; &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; &lt;fields&gt; &lt;field&gt;&lt;name&gt;edgecapture&lt;/name&gt; &lt;description&gt;Edge detection for each input port.&lt;/description&gt; &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; &lt;bitWidth&gt;32&lt;/bitWidth&gt; &lt;access&gt;read-write&lt;/access&gt; &lt;/field&gt; &lt;/fields&gt; &lt;/register&gt; &lt;register&gt; &lt;name&gt;SET_BIT&lt;/name&gt; &lt;displayName&gt;Outset&lt;/displayName&gt; &lt;description&gt;You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt; &lt;addressOffset&gt;0x10&lt;/addressOffset&gt; &lt;size&gt;32&lt;/size&gt; &lt;access&gt;write-only&lt;/access&gt; &lt;resetValue&gt;0x0&lt;/resetValue&gt; &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; &lt;fields&gt; &lt;field&gt;&lt;name&gt;outset&lt;/name&gt; &lt;description&gt;Specifies which bit of the output port to set.&lt;/description&gt; &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; &lt;bitWidth&gt;32&lt;/bitWidth&gt; &lt;access&gt;write-only&lt;/access&gt; &lt;/field&gt; &lt;/fields&gt; &lt;/register&gt; &lt;register&gt; &lt;name&gt;CLEAR_BITS&lt;/name&gt; &lt;displayName&gt;Outclear&lt;/displayName&gt; &lt;description&gt;You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt; &lt;addressOffset&gt;0x14&lt;/addressOffset&gt; &lt;size&gt;32&lt;/size&gt; &lt;access&gt;write-only&lt;/access&gt; &lt;resetValue&gt;0x0&lt;/resetValue&gt; &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; &lt;fields&gt; &lt;field&gt;&lt;name&gt;outclear&lt;/name&gt; &lt;description&gt;Specifies which output bit to clear.&lt;/description&gt; &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; &lt;bitWidth&gt;32&lt;/bitWidth&gt; &lt;access&gt;write-only&lt;/access&gt; &lt;/field&gt; &lt;/fields&gt; &lt;/register&gt; &lt;/registers&gt; &lt;/peripheral&gt; &lt;/peripherals&gt; &lt;/device&gt; </cmsisSrcFileContents> <addressGroup></addressGroup> <cmsisVars/> </cmsisInfo> </interface> <interface> <name>external_connection</name> <type>conduit</type> <isStart>false</isStart> <ports> <port> <name>in_port</name> <role>export</role> <direction>Input</direction> <width>12</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC_VECTOR</vhdlType> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>associatedReset</key> </entry> <entry> <key>prSafe</key> <value>false</value> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> <connPtSystemInfos> <entry> <key>clk</key> <value> <connectionPointName>clk</connectionPointName> <suppliedSystemInfos> <entry> <key>CLOCK_RATE</key> <value>50000000</value> </entry> </suppliedSystemInfos> <consumedSystemInfos/> </value> </entry> <entry> <key>s1</key> <value> <connectionPointName>s1</connectionPointName> <suppliedSystemInfos/> <consumedSystemInfos> <entry> <key>ADDRESS_MAP</key> <value>&lt;address-map&gt;&lt;slave name='s1' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value> </entry> <entry> <key>ADDRESS_WIDTH</key> <value>4</value> </entry> <entry> <key>MAX_SLAVE_DATA_WIDTH</key> <value>32</value> </entry> </consumedSystemInfos> </value> </entry> </connPtSystemInfos> </systemInfosDefinition> + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_reset_in.ip b/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_reset_in.ip new file mode 100644 index 0000000..a3950af --- /dev/null +++ b/de10-pro-e/ip/DE10_Pro_QSYS/DE10_Pro_QSYS_reset_in.ip @@ -0,0 +1,434 @@ + + + + Intel Corporation + DE10_Pro_QSYS_reset_in + reset_in + 19.2.0 + + + clk + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + in_reset + + + + + + + + reset + + + in_reset + + + + + + + + + associatedClock + Associated clock + clk + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + out_reset + + + + + + + + reset + + + out_reset + + + + + + + + + associatedClock + Associated clock + clk + + + associatedDirectReset + Associated direct reset + in_reset + + + associatedResetSinks + Associated reset sinks + in_reset + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_reset_bridge + + QUARTUS_SYNTH + + + + + + + clk + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + in_reset + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + out_reset + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + DE10_Pro_QSYS_reset_in + altera_reset_bridge + 19.2.0 + + + + + ACTIVE_LOW_RESET + Active low reset + 0 + + + SYNCHRONOUS_EDGES + Synchronous edges + deassert + + + NUM_RESET_OUTPUTS + Number of reset outputs + 1 + + + USE_RESET_REQUEST + Use reset request signal + 0 + + + SYNC_RESET + Use synchronous resets + 0 + + + AUTO_CLK_CLOCK_RATE + Auto CLOCK_RATE + 50000000 + + + + + + + device + Device + 1SX280HU2F50E1VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 1 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element $system + { + datum _originalDeviceFamily + { + value = "Stratix 10"; + type = "String"; + } + } + element reset_in + { + datum _originalVersion + { + value = "19.1"; + type = "String"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_reset</name> + <role>reset</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>50000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/de10-pro-e/prepare_dse.sh b/de10-pro-e/prepare_dse.sh new file mode 100755 index 0000000..df4247d --- /dev/null +++ b/de10-pro-e/prepare_dse.sh @@ -0,0 +1,10 @@ +#!/bin/bash + +# DSE seems to require every verilog file to be explicitly mentioned +for VFILE in ./*.v \ + ../src/*.v \ + ../pebbles/blarney/Verilog/Altera/*.v \ + ../pebbles/src/CHERI/Verilog/*.v +do + echo set_global_assignment -name VERILOG_FILE $VFILE >> DE10_Pro.qsf +done diff --git a/de10-pro-e/reset_release.ip b/de10-pro-e/reset_release.ip new file mode 100644 index 0000000..01a22b8 --- /dev/null +++ b/de10-pro-e/reset_release.ip @@ -0,0 +1,140 @@ + + + Intel Corporation + reset_release + s10_user_rst_clkgate_0 + 19.1 + + + ninit_done + + + + + + + + ninit_done + + + ninit_done + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_s10_user_rst_clkgate + + QUARTUS_SYNTH + + + + + + ninit_done + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + reset_release + altera_s10_user_rst_clkgate + 19.1 + + + + + + + + device + Device + 1SX280HU2F50E1VGAS + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 1 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData { element s10_user_rst_clkgate_0 { datum _sortIndex { value = "0"; type = "int"; } } } + + + hideFromIPCatalog + Hide from IP Catalog + true + + + lockedInterfaceDefinition + lockedInterfaceDefinition + + + + systemInfos + systemInfos + <systemInfosDefinition> <connPtSystemInfos/> </systemInfosDefinition> + + + + + + + + + false + false + + \ No newline at end of file diff --git a/scripts/sweep.py b/scripts/sweep.py index 8ea0954..891ffaa 100755 --- a/scripts/sweep.py +++ b/scripts/sweep.py @@ -33,6 +33,10 @@ def printUsage(): config["StoreBuffer"] = config["RegFileScalarisation"] + [ ("SIMTEnableSVStoreBuffer", "1") ] +config["DynRegSpill"] = config["RegFileScalarisation"] + [ + ("SIMTRegFileSize", "256") + , ("SIMTCapRegFileSize", "256") + ] # Combinations of configs that are of interest configCombos = [ @@ -45,6 +49,7 @@ def printUsage(): , ["CHERI"] , ["CHERI", "RegFileScalarisation"] , ["CHERI", "StoreBuffer"] + ["CHERI", "DynRegSpill"] ] # Get directory containing script diff --git a/src/Makefile b/src/Makefile index 75debc9..2d14d9b 100644 --- a/src/Makefile +++ b/src/Makefile @@ -13,6 +13,7 @@ all: -hidir $(BUILD_DIR) -odir $(BUILD_DIR) Main.hs -o Main ./Main --enable-dont-care-de-inline @cp *.mif $(SIMTIGHT_ROOT)/de10-pro 2> /dev/null || true + @cp *.mif $(SIMTIGHT_ROOT)/de10-pro-e 2> /dev/null || true @cp *.hex $(SIMTIGHT_ROOT)/sim 2> /dev/null || true clean: diff --git a/test/test.sh b/test/test.sh index 770ade1..1e533bd 100755 --- a/test/test.sh +++ b/test/test.sh @@ -38,7 +38,8 @@ do -h|--help) echo "Run test-suite and example apps" echo " --sim run in simulation (verilator)" - echo " --fpga run on FPGA (de10-pro)" + echo " --fpga-d run on FPGA (de10-pro revD)" + echo " --fpga-e run on FPGA (de10-pro revE)" echo " --no-pgm don't reprogram FPGA" echo " --apps-only run apps only (not test-suite)" echo " --log-sim log simulator output to sim-log.txt" @@ -50,8 +51,11 @@ do --sim) TestSim=yup ;; - --fpga) - TestFPGA=yup + --fpga-d) + TestFPGA=yup-d + ;; + --fpga-e) + TestFPGA=yup-e ;; --no-pgm) NoPgm=yup @@ -152,15 +156,19 @@ if [ "$TestSim" != "" ]; then fi # Prepare FPGA -if [ "$TestFPGA" != "" ] ; then +if [ "$TestFPGA" != "" ]; then # Check that quartus is in scope echo -n "Quartus available: " JTAG_CABLE=$(type -P quartus) assert $? # Look for FPGA image + QPROG="de10-pro" + if [ "$TestFPGA" == "yup-e" ]; then + QPROG="de10-pro-e" + fi echo -n "FPGA image available: " - test -f "../de10-pro/output_files/DE10_Pro.sof" - assert $? "" "" " (run 'make' in 'de10-pro' dir)" + test -f "../$QPROG/output_files/DE10_Pro.sof" + assert $? "" "" " (run 'make' in $QPROG dir)" # Check that FPGA is visisble echo -n "FPGA available: " JTAG_CABLE=$(jtagconfig 2> /dev/null | grep DE10-Pro) @@ -169,7 +177,7 @@ if [ "$TestFPGA" != "" ] ; then # Program FPGA if [ "$NoPgm" == "" ]; then echo -n "Programming FPGA: " - make -s -C ../de10-pro download-sof > /dev/null + make -s -C ../$QPROG download-sof > /dev/null assert $? fi echo