diff --git a/de10-pro-e/DE10_Pro.qsf b/de10-pro-e/DE10_Pro.qsf
index c8a4132..e80b47b 100644
--- a/de10-pro-e/DE10_Pro.qsf
+++ b/de10-pro-e/DE10_Pro.qsf
@@ -1735,3 +1735,5 @@ set_global_assignment -name SEARCH_PATH ../pebbles/src/CHERI/Verilog/
 set_global_assignment -name SEED 2
 set_global_assignment -name IP_FILE ../pebbles/blarney/blarney-vendor-ip/IntelFPGA/AvalonStreamClockCrosser/AvalonStreamClockCrosser.ip
 set_global_assignment -name VERILOG_FILE ../pebbles/blarney/blarney-vendor-ip/IntelFPGA/PipelinedDivider/PipelinedDivider.v
+set_global_assignment -name OPTIMIZATION_MODE "SUPERIOR PERFORMANCE WITH MAXIMUM PLACEMENT EFFORT"
+set_global_assignment -name FAST_PRESERVE OFF -entity DE10_Pro
diff --git a/de10-pro/DE10_Pro.qsf b/de10-pro/DE10_Pro.qsf
index d787d9c..f7c7f77 100644
--- a/de10-pro/DE10_Pro.qsf
+++ b/de10-pro/DE10_Pro.qsf
@@ -1738,3 +1738,5 @@ set_global_assignment -name SEARCH_PATH ../pebbles/src/CHERI/Verilog/
 set_global_assignment -name SEED 2
 set_global_assignment -name IP_FILE ../pebbles/blarney/blarney-vendor-ip/IntelFPGA/AvalonStreamClockCrosser/AvalonStreamClockCrosser.ip
 set_global_assignment -name VERILOG_FILE ../pebbles/blarney/blarney-vendor-ip/IntelFPGA/PipelinedDivider/PipelinedDivider.v
+set_global_assignment -name OPTIMIZATION_MODE "SUPERIOR PERFORMANCE WITH MAXIMUM PLACEMENT EFFORT"
+set_global_assignment -name FAST_PRESERVE OFF -entity DE10_Pro
diff --git a/pebbles b/pebbles
index 1188a3a..7e89894 160000
--- a/pebbles
+++ b/pebbles
@@ -1 +1 @@
-Subproject commit 1188a3ad191830b5f24a0b11d0e434acafe7db9e
+Subproject commit 7e8989424a12f42629289668bcf28596d168c7af
diff --git a/scripts/sweep.py b/scripts/sweep.py
index 8fb0fce..ec63bca 100755
--- a/scripts/sweep.py
+++ b/scripts/sweep.py
@@ -35,8 +35,8 @@ def printUsage():
     ("SIMTEnableSVStoreBuffer", "1")
   ]
 config["DynRegSpill"] = config["RegFileScalarisation"] + [
-    ("SIMTRegFileSize", "256")
-  , ("SIMTCapRegFileSize", "256")
+    ("SIMTRegFileSize", "512")
+  , ("SIMTCapRegFileSize", "192")
   ]
 config["DynHalfRF"] = [
     ("SIMTEnableRegFileScalarisation", "1")
@@ -53,14 +53,18 @@ def printUsage():
     ["Clang"]
   , ["CHERI", "RegFileScalarisation"]
   , ["CHERI", "DynRegSpill"]
-  , ["GCC", "DynHalfRF"]
-  , ["GCC", "StaticHalfRF"]
   , ["CHERI", "StoreBuffer"]
   , ["CHERI", "ScalarUnit"]
   , ["Clang", "DynRegSpill", "StoreBuffer", "ScalarUnit"]
   , ["CHERI", "DynRegSpill", "StoreBuffer", "ScalarUnit"]
   ]
 
+# Config combos of interest when benchmarking only
+benchCombos = [
+    ["GCC", "DynHalfRF"]
+  , ["GCC", "StaticHalfRF"]
+  ]
+
 # Get directory containing script
 scriptDir = os.path.dirname(os.path.realpath(__file__))
 
@@ -99,6 +103,7 @@ def applySettings(combo):
   # Remove old log file
   os.chdir(repoDir + "/de10-pro")
   os.system("rm -f synth.log")
+  os.system("rm -rf Synth-*")
   # Synthesise each combination using quartus DSE
   for combo in configCombos:
     name = "Baseline" if combo == [] else "+".join(combo)
@@ -110,19 +115,24 @@ def applySettings(combo):
     os.system("make > /dev/null")
     os.chdir(repoDir + "/de10-pro")
     os.system("./prepare_dse.sh")
-    os.system("make many > /dev/null")
+    os.system('BLC_FLAGS="enable-namer-plugin" make many > /dev/null')
     # Save report
     os.system("echo >> synth.log")
     os.system("echo ====== " + name + " ====== >> synth.log")
     os.system("echo >> synth.log")
     os.system("make report | grep -v 'Info:' >> synth.log")
+    os.system("mkdir -p Synth-" + name)
+    os.system("find dse/*" +
+              " | grep DE10_Pro.fit.place.rpt" +
+              " | tr '/' '_'" +
+              " | xargs -i cp {} Synth-" + name)
   clean()
 elif sys.argv[1] == "bench":
   # Remove old log file
   os.chdir(repoDir + "/test")
   os.system("rm -f bench.log")
-  # Test each combination in simulation
-  for combo in configCombos:
+  # Benchmark each combination in simulation
+  for combo in (configCombos + benchCombos):
     name = "Baseline" if combo == [] else "+".join(combo)
     print("Config: " + name)
     clean()