From 1ee4683efb6313eb8636a135bd7930471d2f88bf Mon Sep 17 00:00:00 2001 From: John Baldwin Date: Thu, 13 Jul 2023 10:54:23 -0700 Subject: [PATCH] Add an additional paragraph to the 64-bit CHERI format description. Also add a note in the 9.0 change list. While here, mention the flag bit in the 128-bit CHERI format description. --- app-versions-9-0.tex | 3 +++ chap-architecture.tex | 8 +++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/app-versions-9-0.tex b/app-versions-9-0.tex index 4681f3e8..429b3d67 100644 --- a/app-versions-9-0.tex +++ b/app-versions-9-0.tex @@ -61,4 +61,7 @@ existing instructions to support operations on capabilities as well as details for new instructions in a new ISA reference in Chapter~\ref{chap:isaref-x86-64}. + +\item Added a description of the 64-bit CHERI Concentrate capability + format. \end{itemize} diff --git a/chap-architecture.tex b/chap-architecture.tex index f2bfd71b..024e50a0 100644 --- a/chap-architecture.tex +++ b/chap-architecture.tex @@ -1186,7 +1186,7 @@ \subsection{CHERI Concentrate Compression} For a more detailed rational behind some of the encoding decisions see \cref{sec:rational:comressed}. \Cref{fig:cheric128} shows the capability format and decoding method for 128-bit CHERI concentrate. -The format contains a 64-bit address, $a$, 16 permission bits (4 user defined and 12 hardware defined), an 18-bit object type and 27 bits that encode the bounds relative to the address. +The format contains a 64-bit address, $a$, 16 permission bits (4 user defined and 12 hardware defined), a flag bit, an 18-bit object type and 27 bits that encode the bounds relative to the address. The following definitions are used in the description of the bounds encoding:\note{Would be useful if this list could be opposite \cref{fig:cheric128}}{rmn30} \begin{description} @@ -1381,6 +1381,7 @@ \subsubsection{CHERI Concentrate Fast Representable Limit Checking} This fast representability check allows us to perform pointer arithmetic on compressed capabilities directly, avoiding decompressing capabilities in the register file that introduces both a dramatically enlarged register file and substantial load-to-use delay. \subsubsection{CHERI Concentrate 64-bit format for 32-bit address spaces} + In this section, we describe how CHERI Concentrate compresses the bounds used in 64-bit capabilities with 32-bit architectural addresses. @@ -1475,6 +1476,11 @@ \subsubsection{CHERI Concentrate 64-bit format for 32-bit address spaces} \vspace{-1.5em} \end{figure} +\Cref{fig:cheric64} shows the capability format and decoding method +for 64-bit CHERI concentrate. The format contains a 32-bit address, +$a$, 12 hardware defined permission bits, a flag bit, a 4-bit object +type and 15 bits that encode the bounds relative to the address. + \subsection{Capability Address and Length Rounding Instructions} \label{sec:capability-address-and-length-rounding}