diff --git a/chap-cheri-riscv.tex b/chap-cheri-riscv.tex
index 7432becd..d5cc0f26 100644
--- a/chap-cheri-riscv.tex
+++ b/chap-cheri-riscv.tex
@@ -456,6 +456,10 @@ \subsubsection{Capability Control and Status Registers (CCSRs)}
   \riscvcheriexception{} exception (0).
 \end{description}
 
+An implementation compliant with the current version of this
+specification sets the \texttt{nr} and \texttt{tc} bits to 1 and all
+other bits to 0 at reset.
+
 \subsection{Special Capability Registers (SCRs)}
 \label{subsection:cheri-riscv-scrs}