From 37d717889a6dc0a3449f7b6cc58b1c140edadbdc Mon Sep 17 00:00:00 2001
From: John Baldwin <jhb@FreeBSD.org>
Date: Thu, 3 Aug 2023 16:15:55 -0700
Subject: [PATCH] RISC-V: Add a note for the reset value of xCCSR.

---
 chap-cheri-riscv.tex | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/chap-cheri-riscv.tex b/chap-cheri-riscv.tex
index 7432becd..d5cc0f26 100644
--- a/chap-cheri-riscv.tex
+++ b/chap-cheri-riscv.tex
@@ -456,6 +456,10 @@ \subsubsection{Capability Control and Status Registers (CCSRs)}
   \riscvcheriexception{} exception (0).
 \end{description}
 
+An implementation compliant with the current version of this
+specification sets the \texttt{nr} and \texttt{tc} bits to 1 and all
+other bits to 0 at reset.
+
 \subsection{Special Capability Registers (SCRs)}
 \label{subsection:cheri-riscv-scrs}