From 599a187f6b8427ddf0f1c42ae599c0a109f173d2 Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Wed, 21 Dec 2022 11:27:59 +0000 Subject: [PATCH] Fix references to exception-throwing RISC-V in x86 chapter --- chap-cheri-x86-64.tex | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/chap-cheri-x86-64.tex b/chap-cheri-x86-64.tex index 504eee11..197dacbf 100644 --- a/chap-cheri-x86-64.tex +++ b/chap-cheri-x86-64.tex @@ -769,8 +769,8 @@ \subsubsection{Capability-Inspection Instructions} \subsubsection{Capability-Modification Instructions} If these instructions fail, they should clear the tag in the resulting -capability similar to Morello rather than raising an exception as is -done for CHERI-RISC-V. +capability similar to Morello and CHERI-RISC-V rather than raising an +exception. \begin{itemize} \item \insnref{CSeal} r/mc, rc @@ -1088,7 +1088,7 @@ \subsection{Capability Violation Faults} implement. \end{enumerate} -Unlike CHERI-RISC-V, we recommend that CHERI-x86-64 +Like Morello and CHERI-RISC-V, we recommend that CHERI-x86-64 only raise capability violation faults when a invalid memory access is performed such as an out-of-bounds access or access via an untagged capability. Specifically, we recommend that instructions which modify