From a3340dc654d68c4bb85e2a3119802049300a0deb Mon Sep 17 00:00:00 2001
From: John Baldwin <jhb@FreeBSD.org>
Date: Tue, 18 Jul 2023 14:53:09 -0700
Subject: [PATCH] RISC-V: Remove an OBE note about RV128.

The chapter discusses RV128 in several other places.
---
 chap-cheri-riscv.tex | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/chap-cheri-riscv.tex b/chap-cheri-riscv.tex
index 45083e83..dc1adbe2 100644
--- a/chap-cheri-riscv.tex
+++ b/chap-cheri-riscv.tex
@@ -83,8 +83,7 @@ \subsection{Target RISC-V ISA Variants}
 
 The RISC-V ISA defines both 32-bit (\texttt{XLEN}=32) and 64-bit
 (\texttt{XLEN}=64) base integer instruction
-sets (RV32I, RV64I). \mmnote{Maybe mention that we don't support RV128I,
-because it has not been ratified yet.}
+sets (RV32I, RV64I).
 Our current proposal supports either mode with few differences beyond
 capability width, although safe support for both modes in a single processor
 is not specified at this time.