From b95fe956e4435ea54088a16bbd4f8072870d9521 Mon Sep 17 00:00:00 2001 From: John Baldwin Date: Fri, 4 Aug 2023 15:57:19 -0700 Subject: [PATCH] Regenerate sail_latex_riscv Corresponds to commit 77e647e6319d142e0bf101f908b4ba0b954fada9 in sail-cheri-riscv. --- sail_latex_riscv/commands.tex | 541 +++++++++++++++--- ...xecute33a689e3a631b9b905b85461d3814943.tex | 8 +- ...xecute33a689e3a631b9b905b85461d3814943.tex | 8 +- ...xecute33a689e3a631b9b905b85461d3814943.tex | 4 +- ...xecute33a689e3a631b9b905b85461d3814943.tex | 3 +- ...xecute33a689e3a631b9b905b85461d3814943.tex | 3 +- ...xecute33a689e3a631b9b905b85461d3814943.tex | 3 +- ...xecute33a689e3a631b9b905b85461d3814943.tex | 3 +- ...xecute33a689e3a631b9b905b85461d3814943.tex | 3 +- ...xecute33a689e3a631b9b905b85461d3814943.tex | 3 +- ...xecute33a689e3a631b9b905b85461d3814943.tex | 3 +- ...xecute33a689e3a631b9b905b85461d3814943.tex | 3 +- ...ger_pcfb8f9e29d6bb00469db30a7b19649da3.tex | 3 + ...string7067e2f1e90748309c77a5de3d661e3d.tex | 4 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sail_latex_riscv/{overloadKz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex => overloadAz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex} (100%) create mode 100644 sail_latex_riscv/overloadAzabs_intef5fbb521189282054dc80dc7173013d.tex rename sail_latex_riscv/{overloadYzappend88575169e0ec1639b6ae3851df999710.tex => overloadAzappend88575169e0ec1639b6ae3851df999710.tex} (100%) rename sail_latex_riscv/{overloadOOzbitstr0d04da018975c4776e05a9c59c2e380e.tex => overloadAzbitstr0d04da018975c4776e05a9c59c2e380e.tex} (100%) rename sail_latex_riscv/{overloadKKKzc15f67105dab436b80b9241d87d1f8e9d.tex => overloadAzc15f67105dab436b80b9241d87d1f8e9d.tex} (100%) rename sail_latex_riscv/{overloadOOOzf71805d10b9ea2a56437652aba0daf9bf.tex => overloadAzf71805d10b9ea2a56437652aba0daf9bf.tex} (100%) create mode 100644 sail_latex_riscv/overloadAzf_dce13a0941da7b7642c47c02aaaf22707.tex create mode 100644 sail_latex_riscv/overloadAzf_h8b5b89a166af005200eddfdb4c753f54.tex rename sail_latex_riscv/{overloadRRRzf_or_x_d024412251a76ad9b93d0cea341dd37e8.tex => overloadAzf_or_x_d024412251a76ad9b93d0cea341dd37e8.tex} (100%) rename sail_latex_riscv/{overloadPPPzf_or_x_h3ebc47a16976857a8cd1e19cfb51cb3e.tex => overloadAzf_or_x_h3ebc47a16976857a8cd1e19cfb51cb3e.tex} (100%) rename sail_latex_riscv/{overloadQQQzf_or_x_s13ae8815ba72277dad5d10001aed7f61.tex => overloadAzf_or_x_s13ae8815ba72277dad5d10001aed7f61.tex} (100%) create mode 100644 sail_latex_riscv/overloadAzf_s921e5f10c465aae8686d3336bac4e432.tex rename sail_latex_riscv/{overloadWzlength469e3f917f7b24f4691faf3caf842eba.tex => overloadAzlength469e3f917f7b24f4691faf3caf842eba.tex} (100%) rename sail_latex_riscv/{overloadTTzmax91b641c464c0dc87660499321a356d93.tex => overloadAzmax91b641c464c0dc87660499321a356d93.tex} (100%) rename sail_latex_riscv/{overloadSSzmin95ae3c0ebde1421750e6db87bdf74801.tex => overloadAzmin95ae3c0ebde1421750e6db87bdf74801.tex} (100%) rename sail_latex_riscv/{overloadMMMznan_boxf593e1648915be3a65ed1e1cf0dc7712.tex => overloadAznan_boxf593e1648915be3a65ed1e1cf0dc7712.tex} (100%) rename sail_latex_riscv/{overloadNNNznan_unbox6971c840905d637f635a4793907fe38e.tex => overloadAznan_unbox6971c840905d637f635a4793907fe38e.tex} (100%) rename sail_latex_riscv/{overloadNznegatef5714e2e9cd970a9cb8b7c6fdf3732b8.tex => overloadAznegatef5714e2e9cd970a9cb8b7c6fdf3732b8.tex} (100%) rename sail_latex_riscv/{overloadZZzreversed9f0df85c2b57ca70b0103d18920d22f.tex => overloadAzreversed9f0df85c2b57ca70b0103d18920d22f.tex} (100%) rename sail_latex_riscv/{overloadPzshl_int4772030e3fc0913189e795ec25e86dc5.tex => overloadAzshl_int4772030e3fc0913189e795ec25e86dc5.tex} (100%) rename sail_latex_riscv/{overloadQzshr_int5f4032eb21b9c850a9e2a8de5872a2a2.tex => overloadAzshr_int5f4032eb21b9c850a9e2a8de5872a2a2.tex} (100%) rename sail_latex_riscv/{overloadRztmod_int76b131b53b88df8b201279295eacebbe.tex => overloadAztmod_int76b131b53b88df8b201279295eacebbe.tex} (100%) rename sail_latex_riscv/{overloadDDDzto_str8b7a6895ae35945bd4740e9f790c43ee.tex => overloadAzto_str8b7a6895ae35945bd4740e9f790c43ee.tex} (100%) rename sail_latex_riscv/{overloadZzvector_accessbe81ec250d2df2ebadde393ea37a85a4.tex => overloadAzvector_accessbe81ec250d2df2ebadde393ea37a85a4.tex} (100%) rename sail_latex_riscv/{overloadEEzvector_subrange270c799ffa6c20b5244f22c64fba0367.tex => overloadAzvector_subrange270c799ffa6c20b5244f22c64fba0367.tex} (100%) rename sail_latex_riscv/{overloadFFzvector_update_subrangeb77be803268d55f5f112399f9d0dfbc2.tex => overloadAzvector_update_subrangeb77be803268d55f5f112399f9d0dfbc2.tex} (100%) rename sail_latex_riscv/{overloadAAzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex => overloadAzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex} (100%) rename sail_latex_riscv/{overloadIIIzx1f3c57dd04ac52fd92f3346ca51f00ec.tex => overloadAzx1f3c57dd04ac52fd92f3346ca51f00ec.tex} (100%) rename sail_latex_riscv/{overloadDzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex => overloadAzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex} (100%) rename sail_latex_riscv/{overloadRRzz8operatorz0z5z9194a289f0ceb02e29c9b6febc5146071.tex => overloadAzz8operatorz0z5z9194a289f0ceb02e29c9b6febc5146071.tex} (100%) rename sail_latex_riscv/{overloadFzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex => overloadAzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex} (100%) rename sail_latex_riscv/{overloadOzz8operatorz0zaz94d99df7698c53c990108e8f028c06211.tex => overloadAzz8operatorz0zaz94d99df7698c53c990108e8f028c06211.tex} (100%) rename sail_latex_riscv/{overloadLzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex => overloadAzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex} (100%) rename sail_latex_riscv/{overloadMzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex => overloadAzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex} (100%) rename sail_latex_riscv/{overloadHzz8operatorz0ziz9714b8c400aed24ebd80eac39b4f9d751.tex => overloadAzz8operatorz0ziz9714b8c400aed24ebd80eac39b4f9d751.tex} (100%) rename sail_latex_riscv/{overloadWWzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex => overloadAzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex} (100%) rename sail_latex_riscv/{overloadYYzz8operatorz0ziziziz9daf9b9d2ffdbec7af40418527044fa38.tex => overloadAzz8operatorz0ziziziz9daf9b9d2ffdbec7af40418527044fa38.tex} (100%) rename sail_latex_riscv/{overloadGzz8operatorz0zizjz95c366628fed7d8b7c251f1acd527ee3b.tex => overloadAzz8operatorz0zizjz95c366628fed7d8b7c251f1acd527ee3b.tex} (100%) create mode 100644 sail_latex_riscv/overloadAzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex rename sail_latex_riscv/{overloadJzz8operatorz0zkz93747e4d4a6f99eb3fca0b477d2437ed5.tex => overloadAzz8operatorz0zkz93747e4d4a6f99eb3fca0b477d2437ed5.tex} (100%) rename sail_latex_riscv/{overloadIzz8operatorz0zkzjz94161e4bfad2d20e5d25bc774612b6588.tex => overloadAzz8operatorz0zkzjz94161e4bfad2d20e5d25bc774612b6588.tex} (100%) rename sail_latex_riscv/{overloadCCCzz8operatorz0zkzk_sz9fd336467c8d7c9163cb44b900cb10522.tex => overloadAzz8operatorz0zkzk_sz9fd336467c8d7c9163cb44b900cb10522.tex} (100%) rename sail_latex_riscv/{overloadVVzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex => overloadAzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex} (100%) rename sail_latex_riscv/{overloadXXzz8operatorz0zkzkzkz957fa2f300078df169cd8f1b6939b710d.tex => overloadAzz8operatorz0zkzkzkz957fa2f300078df169cd8f1b6939b710d.tex} (100%) rename sail_latex_riscv/{overloadXzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex => overloadAzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex} (100%) rename sail_latex_riscv/{overloadEzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex => overloadAzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex} (100%) rename sail_latex_riscv/{overloadKKzzw805a9067649c7cfeedcb41b57a7e2c86.tex => overloadAzzw805a9067649c7cfeedcb41b57a7e2c86.tex} (100%) rename sail_latex_riscv/{overloadUUzzzerosc530711942e216cef3921733c1c5d101.tex => overloadAzzzerosc530711942e216cef3921733c1c5d101.tex} (100%) rename sail_latex_riscv/{overloadGGz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex => overloadBz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex} (100%) rename sail_latex_riscv/{overloadJJzappend88575169e0ec1639b6ae3851df999710.tex => overloadBzappend88575169e0ec1639b6ae3851df999710.tex} (100%) rename sail_latex_riscv/{overloadEEEzto_str8b7a6895ae35945bd4740e9f790c43ee.tex => overloadBzto_str8b7a6895ae35945bd4740e9f790c43ee.tex} (100%) rename sail_latex_riscv/{overloadIIzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex => overloadBzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex} (100%) rename sail_latex_riscv/{overloadVzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex => overloadBzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex} (100%) rename sail_latex_riscv/{overloadCCzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex => overloadBzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex} (100%) rename sail_latex_riscv/{overloadBBzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex => overloadBzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex} (100%) rename sail_latex_riscv/{overloadQQzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex => overloadBzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex} (100%) rename sail_latex_riscv/{overloadBBBzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex => overloadBzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex} (100%) rename sail_latex_riscv/{overloadTzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex => overloadBzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex} (100%) rename sail_latex_riscv/{overloadAAAzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex => overloadBzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex} (100%) rename sail_latex_riscv/{overloadPPzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex => overloadBzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex} (100%) rename sail_latex_riscv/{overloadDDzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex => overloadBzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex} (100%) rename sail_latex_riscv/{overloadFFFzto_str8b7a6895ae35945bd4740e9f790c43ee.tex => overloadCzto_str8b7a6895ae35945bd4740e9f790c43ee.tex} (100%) rename sail_latex_riscv/{overloadLLzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex => overloadCzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex} (100%) rename sail_latex_riscv/{overloadMMzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex => overloadCzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex} (100%) rename sail_latex_riscv/{overloadNNzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex => overloadCzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex} (100%) rename sail_latex_riscv/{overloadGGGzto_str8b7a6895ae35945bd4740e9f790c43ee.tex => overloadDzto_str8b7a6895ae35945bd4740e9f790c43ee.tex} (100%) rename sail_latex_riscv/{overloadHHzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex => overloadDzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex} (100%) rename sail_latex_riscv/{overloadHHHzto_str8b7a6895ae35945bd4740e9f790c43ee.tex => overloadEzto_str8b7a6895ae35945bd4740e9f790c43ee.tex} (100%) rename sail_latex_riscv/{overloadJJJzto_str8b7a6895ae35945bd4740e9f790c43ee.tex => overloadFzto_str8b7a6895ae35945bd4740e9f790c43ee.tex} (100%) rename sail_latex_riscv/{overloadLLLzto_str8b7a6895ae35945bd4740e9f790c43ee.tex => overloadGzto_str8b7a6895ae35945bd4740e9f790c43ee.tex} (100%) rename sail_latex_riscv/{overloadSSSzto_str8b7a6895ae35945bd4740e9f790c43ee.tex => overloadHzto_str8b7a6895ae35945bd4740e9f790c43ee.tex} (100%) rename sail_latex_riscv/{overloadTTTzto_str8b7a6895ae35945bd4740e9f790c43ee.tex => overloadIzto_str8b7a6895ae35945bd4740e9f790c43ee.tex} (100%) rename sail_latex_riscv/{overloadUUUzto_str8b7a6895ae35945bd4740e9f790c43ee.tex => overloadJzto_str8b7a6895ae35945bd4740e9f790c43ee.tex} (100%) delete mode 100644 sail_latex_riscv/overloadSzabs_intef5fbb521189282054dc80dc7173013d.tex delete mode 100644 sail_latex_riscv/overloadUzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex create mode 100644 sail_latex_riscv/registerzminstret_increment4bf06d6ee65982630fdaccfdc2b150e1.tex delete mode 100644 sail_latex_riscv/registerzminstret_writtenaed0046aa7ec44bb59b2c8c7710e05d2.tex create mode 100644 sail_latex_riscv/typezzzicondopa7aca235781cdb8d229dc510abbddd29.tex create mode 100644 sail_latex_riscv/valzcap_to_integer_pcfb8f9e29d6bb00469db30a7b19649da3.tex create mode 100644 sail_latex_riscv/valzddc_and_resulting_addr0f0e2d5c6123a71667b35ed17c44868e.tex create mode 100644 sail_latex_riscv/valzextern_f16le_quietba87aa826fe2ea7c4186b6a7d2619883.tex create mode 100644 sail_latex_riscv/valzextern_f16lt_quiet47c4bf08ad78e10df5bd97faf51ba75b.tex create mode 100644 sail_latex_riscv/valzextern_f16roundtointf6702102443ea92a9f058ba571bbd8d7.tex create mode 100644 sail_latex_riscv/valzextern_f32le_quiet8f7c77183e32b1b4c551a8457476d996.tex create mode 100644 sail_latex_riscv/valzextern_f32lt_quiet70f5a9ae1a77127a5cebd114c342108f.tex create mode 100644 sail_latex_riscv/valzextern_f32roundtointfd564f319eaa6e135f5b6a5d1d839221.tex create mode 100644 sail_latex_riscv/valzextern_f64le_quiet62f25ed39def4a3e2df9a7320243076b.tex create mode 100644 sail_latex_riscv/valzextern_f64lt_quietb909aef2c69da0356d6e4e66ceaba06b.tex create mode 100644 sail_latex_riscv/valzextern_f64roundtointa3a7bcf2dfbdc3862b468cb032011274.tex create mode 100644 sail_latex_riscv/valzhave_cheri_relocationbbe9a9f5c01227424d0cc8330de5d0b3.tex create mode 100644 sail_latex_riscv/valzhave_ddc_relocationcdaa2a12594a6d0db423bcedfc636210.tex create mode 100644 sail_latex_riscv/valzhave_pcc_relocation8ef276f0f56e5c3343729212dcd97cb5.tex create mode 100644 sail_latex_riscv/valzhavezfa170943288777f725fbf88904d27d506e.tex create mode 100644 sail_latex_riscv/valzhavezicond942507aaca8f56a8d3fc5cd08536c028.tex create mode 100644 sail_latex_riscv/valznum_of_zzicondop3e6d4701d8934768c6aaf82a93f9c62d.tex create mode 100644 sail_latex_riscv/valzrf_d29c6729673402bec577925987b943174.tex create mode 100644 sail_latex_riscv/valzrf_hf87446c77cdaf455431ea51fc65d658a.tex create mode 100644 sail_latex_riscv/valzrf_sae821dae13888ed4dd6a166d80f9c14c.tex create mode 100644 sail_latex_riscv/valzriscv_f16le_quiet8f63ce7ff3e42871a470478ce69c31a9.tex create mode 100644 sail_latex_riscv/valzriscv_f16lt_quiet244f6ba5b2310a0cac1e04951f6afb9c.tex create mode 100644 sail_latex_riscv/valzriscv_f16roundtoint52329eb13a3e4a06c8e70e0c4ef36e80.tex create mode 100644 sail_latex_riscv/valzriscv_f32le_quiet7e5f820135a916f973026964c0ce90bf.tex create mode 100644 sail_latex_riscv/valzriscv_f32lt_quiet6805f79a39a589997e0e972ca2f211be.tex create mode 100644 sail_latex_riscv/valzriscv_f32roundtoint33ebf4ca80343b549f0b5a1c93805348.tex create mode 100644 sail_latex_riscv/valzriscv_f64le_quietdbcd45688456ae3af8949c7df7db62f7.tex create mode 100644 sail_latex_riscv/valzriscv_f64lt_quiet14ab1c593c5d6a2b683a6949da76b09d.tex create mode 100644 sail_latex_riscv/valzriscv_f64roundtointc621d19070f8cdbcc8f4378ba7716a84.tex create mode 100644 sail_latex_riscv/valzsetcapaddrchecked02f3e6fc454faf7b488ed3661fb1a85e.tex create mode 100644 sail_latex_riscv/valzupdate_cap_with_integer_pc9c66feb4cf9d3f64ba301705bf4cece5.tex create mode 100644 sail_latex_riscv/valzwf_d94c91aff56d9566b109d96edd2d1663f.tex create mode 100644 sail_latex_riscv/valzwf_hb915a10402ec9321c4ad1188ae0afc9f.tex create mode 100644 sail_latex_riscv/valzwf_s8b4c2b923b5bc2d4c6f88cff982b6695.tex create mode 100644 sail_latex_riscv/valzzzicondop_of_num6c236bc72d5e4b8fcf599f8f5df132a1.tex diff --git a/sail_latex_riscv/commands.tex b/sail_latex_riscv/commands.tex index 02d7bc78..294999db 100644 --- a/sail_latex_riscv/commands.tex +++ b/sail_latex_riscv/commands.tex @@ -17,7 +17,7 @@ \newcommand{\sailRISCVvalabsIntAtom}{\saildoclabelled{sailRISCVzabszyintzyatom}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzabs_int_atom414063313cc5ac5d9a742f9c8a111704.tex}}}} -\newcommand{\sailRISCVoverloadBabsInt}{\saildoclabelled{sailRISCVoverloadBzabszyint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBzabs_intef5fbb521189282054dc80dc7173013d.tex}}}} +\newcommand{\sailRISCVoverloadAabsInt}{\saildoclabelled{sailRISCVoverloadAzabszyint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzabs_intef5fbb521189282054dc80dc7173013d.tex}}}} \newcommand{\sailRISCVtypeoption}{\saildoclabelled{sailRISCVtypezoption}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezoptiona3271ef8b6a63c78e6db36dac0ee6547.tex}}}} @@ -63,27 +63,27 @@ \newcommand{\sailRISCVvalgtInt}{\saildoclabelled{sailRISCVzgtzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzgt_intef94a8c66f39b1f715cb72941ed95921.tex}}}} -\newcommand{\sailRISCVoverloadCzEightoperatorzZerozJzJzNine}{\saildoclabelled{sailRISCVoverloadCzz8operatorz0zJzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex}}}} +\newcommand{\sailRISCVoverloadAzEightoperatorzZerozJzJzNine}{\saildoclabelled{sailRISCVoverloadAzz8operatorz0zJzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex}}}} -\newcommand{\sailRISCVoverloadDzEightoperatorzZerozOnezJzNine}{\saildoclabelled{sailRISCVoverloadDzz8operatorz0z1zJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex}}}} +\newcommand{\sailRISCVoverloadAzEightoperatorzZerozOnezJzNine}{\saildoclabelled{sailRISCVoverloadAzz8operatorz0z1zJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex}}}} -\newcommand{\sailRISCVoverloadEzEightoperatorzZerozUzNine}{\saildoclabelled{sailRISCVoverloadEzz8operatorz0zUz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex}}}} +\newcommand{\sailRISCVoverloadAzEightoperatorzZerozUzNine}{\saildoclabelled{sailRISCVoverloadAzz8operatorz0zUz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex}}}} -\newcommand{\sailRISCVoverloadFzEightoperatorzZerozSixzNine}{\saildoclabelled{sailRISCVoverloadFzz8operatorz0z6z9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex}}}} +\newcommand{\sailRISCVoverloadAzEightoperatorzZerozSixzNine}{\saildoclabelled{sailRISCVoverloadAzz8operatorz0z6z9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex}}}} -\newcommand{\sailRISCVoverloadGzEightoperatorzZerozIzJzNine}{\saildoclabelled{sailRISCVoverloadGzz8operatorz0zIzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGzz8operatorz0zizjz95c366628fed7d8b7c251f1acd527ee3b.tex}}}} +\newcommand{\sailRISCVoverloadAzEightoperatorzZerozIzJzNine}{\saildoclabelled{sailRISCVoverloadAzz8operatorz0zIzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzz8operatorz0zizjz95c366628fed7d8b7c251f1acd527ee3b.tex}}}} -\newcommand{\sailRISCVoverloadHzEightoperatorzZerozIzNine}{\saildoclabelled{sailRISCVoverloadHzz8operatorz0zIz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHzz8operatorz0ziz9714b8c400aed24ebd80eac39b4f9d751.tex}}}} +\newcommand{\sailRISCVoverloadAzEightoperatorzZerozIzNine}{\saildoclabelled{sailRISCVoverloadAzz8operatorz0zIz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzz8operatorz0ziz9714b8c400aed24ebd80eac39b4f9d751.tex}}}} -\newcommand{\sailRISCVoverloadIzEightoperatorzZerozKzJzNine}{\saildoclabelled{sailRISCVoverloadIzz8operatorz0zKzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIzz8operatorz0zkzjz94161e4bfad2d20e5d25bc774612b6588.tex}}}} +\newcommand{\sailRISCVoverloadAzEightoperatorzZerozKzJzNine}{\saildoclabelled{sailRISCVoverloadAzz8operatorz0zKzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzz8operatorz0zkzjz94161e4bfad2d20e5d25bc774612b6588.tex}}}} -\newcommand{\sailRISCVoverloadJzEightoperatorzZerozKzNine}{\saildoclabelled{sailRISCVoverloadJzz8operatorz0zKz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJzz8operatorz0zkz93747e4d4a6f99eb3fca0b477d2437ed5.tex}}}} +\newcommand{\sailRISCVoverloadAzEightoperatorzZerozKzNine}{\saildoclabelled{sailRISCVoverloadAzz8operatorz0zKz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzz8operatorz0zkz93747e4d4a6f99eb3fca0b477d2437ed5.tex}}}} \newcommand{\sailRISCVvalId}{\saildoclabelled{sailRISCVzzyzyid}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz__ided888b8991a27578d5dd72f84db80bce.tex}}}} \newcommand{\sailRISCVfnId}{\saildoclabelled{sailRISCVfnzzyzyid}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz__ided888b8991a27578d5dd72f84db80bce.tex}}}} -\newcommand{\sailRISCVoverloadKSizze}{\saildoclabelled{sailRISCVoverloadKzzyzysizze}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadKz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex}}}} +\newcommand{\sailRISCVoverloadASizze}{\saildoclabelled{sailRISCVoverloadAzzyzysizze}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex}}}} \newcommand{\sailRISCVvalDeref}{\saildoclabelled{sailRISCVzzyzyderef}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz__deref1dbc379e24bd1b182e1db755dea8c453.tex}}}} @@ -91,13 +91,13 @@ \newcommand{\sailRISCVvaladdInt}{\saildoclabelled{sailRISCVzaddzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzadd_intb17710be4fd02ace68d83b9dba907034.tex}}}} -\newcommand{\sailRISCVoverloadLzEightoperatorzZerozBzNine}{\saildoclabelled{sailRISCVoverloadLzz8operatorz0zBz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadLzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex}}}} +\newcommand{\sailRISCVoverloadAzEightoperatorzZerozBzNine}{\saildoclabelled{sailRISCVoverloadAzz8operatorz0zBz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex}}}} \newcommand{\sailRISCVvalsubAtom}{\saildoclabelled{sailRISCVzsubzyatom}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsub_atom328a68dfbab1a07c42d4e7b98eac766f.tex}}}} \newcommand{\sailRISCVvalsubInt}{\saildoclabelled{sailRISCVzsubzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsub_intf17f348f33594e77fdc3ef8b6a46b569.tex}}}} -\newcommand{\sailRISCVoverloadMzEightoperatorzZerozDzNine}{\saildoclabelled{sailRISCVoverloadMzz8operatorz0zDz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadMzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex}}}} +\newcommand{\sailRISCVoverloadAzEightoperatorzZerozDzNine}{\saildoclabelled{sailRISCVoverloadAzz8operatorz0zDz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex}}}} \newcommand{\sailRISCVvalsubNat}{\saildoclabelled{sailRISCVzsubzynat}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsub_nat1e51a6ef44b288dd12f7f69af44dfd3e.tex}}}} @@ -105,13 +105,13 @@ \newcommand{\sailRISCVvalnegateInt}{\saildoclabelled{sailRISCVznegatezyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznegate_int42f776f84c124d77c3e367500082e43f.tex}}}} -\newcommand{\sailRISCVoverloadNnegate}{\saildoclabelled{sailRISCVoverloadNznegate}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadNznegatef5714e2e9cd970a9cb8b7c6fdf3732b8.tex}}}} +\newcommand{\sailRISCVoverloadAnegate}{\saildoclabelled{sailRISCVoverloadAznegate}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAznegatef5714e2e9cd970a9cb8b7c6fdf3732b8.tex}}}} \newcommand{\sailRISCVvalmultAtom}{\saildoclabelled{sailRISCVzmultzyatom}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmult_atomdbad478b99777b7676dde1f5a7900711.tex}}}} \newcommand{\sailRISCVvalmultInt}{\saildoclabelled{sailRISCVzmultzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmult_inte25d1b032a27b461f0eaf0c84be37a2b.tex}}}} -\newcommand{\sailRISCVoverloadOzEightoperatorzZerozAzNine}{\saildoclabelled{sailRISCVoverloadOzz8operatorz0zAz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadOzz8operatorz0zaz94d99df7698c53c990108e8f028c06211.tex}}}} +\newcommand{\sailRISCVoverloadAzEightoperatorzZerozAzNine}{\saildoclabelled{sailRISCVoverloadAzz8operatorz0zAz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzz8operatorz0zaz94d99df7698c53c990108e8f028c06211.tex}}}} \newcommand{\sailRISCVvalprintInt}{\saildoclabelled{sailRISCVzprintzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprint_intfb625bfb7a4021903513aeb4396bd878.tex}}}} @@ -145,9 +145,9 @@ \newcommand{\sailRISCVfnShrIntGeneral}{\saildoclabelled{sailRISCVfnzzyshrzyintzygeneral}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_shr_int_generalf06a573ed81aec273a6397188519fd34.tex}}}} -\newcommand{\sailRISCVoverloadPshlInt}{\saildoclabelled{sailRISCVoverloadPzshlzyint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadPzshl_int4772030e3fc0913189e795ec25e86dc5.tex}}}} +\newcommand{\sailRISCVoverloadAshlInt}{\saildoclabelled{sailRISCVoverloadAzshlzyint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzshl_int4772030e3fc0913189e795ec25e86dc5.tex}}}} -\newcommand{\sailRISCVoverloadQshrInt}{\saildoclabelled{sailRISCVoverloadQzshrzyint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadQzshr_int5f4032eb21b9c850a9e2a8de5872a2a2.tex}}}} +\newcommand{\sailRISCVoverloadAshrInt}{\saildoclabelled{sailRISCVoverloadAzshrzyint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzshr_int5f4032eb21b9c850a9e2a8de5872a2a2.tex}}}} \newcommand{\sailRISCVvaltdivInt}{\saildoclabelled{sailRISCVztdivzyint}{\saildocval{Truncating division (rounds towards zero) @@ -161,7 +161,7 @@ }{\lstinputlisting[language=sail]{sail_latex_riscv/valz_tmod_int_positive6f0621d972182279e90a43c082e50c10.tex}}}} -\newcommand{\sailRISCVoverloadRtmodInt}{\saildoclabelled{sailRISCVoverloadRztmodzyint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadRztmod_int76b131b53b88df8b201279295eacebbe.tex}}}} +\newcommand{\sailRISCVoverloadAtmodInt}{\saildoclabelled{sailRISCVoverloadAztmodzyint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAztmod_int76b131b53b88df8b201279295eacebbe.tex}}}} \newcommand{\sailRISCVvalfdivInt}{\saildoclabelled{sailRISCVzfdivzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfdiv_intd3535e930b3252acc5f18a9e4b34e63a.tex}}}} @@ -173,11 +173,11 @@ \newcommand{\sailRISCVvalabsIntPlain}{\saildoclabelled{sailRISCVzabszyintzyplain}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzabs_int_plainb54aa4afeed2c86b519a464eb2e4c77c.tex}}}} -\newcommand{\sailRISCVoverloadSabsInt}{\saildoclabelled{sailRISCVoverloadSzabszyint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadSzabs_intef5fbb521189282054dc80dc7173013d.tex}}}} +\newcommand{\sailRISCVoverloadBabsInt}{\saildoclabelled{sailRISCVoverloadBzabszyint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBzabs_intef5fbb521189282054dc80dc7173013d.tex}}}} \newcommand{\sailRISCVvaleqString}{\saildoclabelled{sailRISCVzeqzystring}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzeq_string75dfa57c0476ae3f43f8e55ffe51a116.tex}}}} -\newcommand{\sailRISCVoverloadTzEightoperatorzZerozJzJzNine}{\saildoclabelled{sailRISCVoverloadTzz8operatorz0zJzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadTzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex}}}} +\newcommand{\sailRISCVoverloadBzEightoperatorzZerozJzJzNine}{\saildoclabelled{sailRISCVoverloadBzz8operatorz0zJzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex}}}} \newcommand{\sailRISCVvalconcatStr}{\saildoclabelled{sailRISCVzconcatzystr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzconcat_str366019c233188ef65ab3d1f977f04112.tex}}}} @@ -203,19 +203,19 @@ \newcommand{\sailRISCVvaleqBits}{\saildoclabelled{sailRISCVzeqzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzeq_bits886ce7cf3ec93a28308e8d4e9d63f4be.tex}}}} -\newcommand{\sailRISCVoverloadUzEightoperatorzZerozJzJzNine}{\saildoclabelled{sailRISCVoverloadUzz8operatorz0zJzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadUzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex}}}} +\newcommand{\sailRISCVoverloadCzEightoperatorzZerozJzJzNine}{\saildoclabelled{sailRISCVoverloadCzz8operatorz0zJzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex}}}} \newcommand{\sailRISCVvalneqBits}{\saildoclabelled{sailRISCVzneqzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzneq_bits167748c906c068e62596c88540a84f42.tex}}}} \newcommand{\sailRISCVfnneqBits}{\saildoclabelled{sailRISCVfnzneqzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzneq_bits167748c906c068e62596c88540a84f42.tex}}}} -\newcommand{\sailRISCVoverloadVzEightoperatorzZerozOnezJzNine}{\saildoclabelled{sailRISCVoverloadVzz8operatorz0z1zJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadVzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex}}}} +\newcommand{\sailRISCVoverloadBzEightoperatorzZerozOnezJzNine}{\saildoclabelled{sailRISCVoverloadBzz8operatorz0z1zJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex}}}} \newcommand{\sailRISCVvalbitvectorLength}{\saildoclabelled{sailRISCVzbitvectorzylength}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzbitvector_lengthcd74a5cced7567d19500671e4b6e1031.tex}}}} \newcommand{\sailRISCVvalvectorLength}{\saildoclabelled{sailRISCVzvectorzylength}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzvector_length9ee541b308cdfd9738d44bfb3dff4b46.tex}}}} -\newcommand{\sailRISCVoverloadWlength}{\saildoclabelled{sailRISCVoverloadWzlength}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadWzlength469e3f917f7b24f4691faf3caf842eba.tex}}}} +\newcommand{\sailRISCVoverloadAlength}{\saildoclabelled{sailRISCVoverloadAzlength}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzlength469e3f917f7b24f4691faf3caf842eba.tex}}}} \newcommand{\sailRISCVvalcountLeadingZeros}{\saildoclabelled{sailRISCVzcountzyleadingzyzzeros}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcount_leading_zzeros315ae28f559df1d42a7d2ca4cfff2905.tex}}}} @@ -239,11 +239,11 @@ \newcommand{\sailRISCVfnsailMask}{\saildoclabelled{sailRISCVfnzsailzymask}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzsail_maske146b73afc824e90813dd8234bfa3053.tex}}}} -\newcommand{\sailRISCVoverloadXzEightoperatorzZerozQzNine}{\saildoclabelled{sailRISCVoverloadXzz8operatorz0zQz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadXzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex}}}} +\newcommand{\sailRISCVoverloadAzEightoperatorzZerozQzNine}{\saildoclabelled{sailRISCVoverloadAzz8operatorz0zQz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex}}}} \newcommand{\sailRISCVvalbitvectorConcat}{\saildoclabelled{sailRISCVzbitvectorzyconcat}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzbitvector_concat6176f8be1468d8779ee8370fd3b4a6e0.tex}}}} -\newcommand{\sailRISCVoverloadYappend}{\saildoclabelled{sailRISCVoverloadYzappend}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadYzappend88575169e0ec1639b6ae3851df999710.tex}}}} +\newcommand{\sailRISCVoverloadAappend}{\saildoclabelled{sailRISCVoverloadAzappend}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzappend88575169e0ec1639b6ae3851df999710.tex}}}} \newcommand{\sailRISCVvalappendSixFour}{\saildoclabelled{sailRISCVzappendzy64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzappend_6433ef192058d4bf5f092d6f8b6d97f4c4.tex}}}} @@ -251,19 +251,19 @@ \newcommand{\sailRISCVvalplainVectorAccess}{\saildoclabelled{sailRISCVzplainzyvectorzyaccess}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzplain_vector_access792547dd734d4ff2e6078cbb88967469.tex}}}} -\newcommand{\sailRISCVoverloadZvectorAccess}{\saildoclabelled{sailRISCVoverloadZzvectorzyaccess}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadZzvector_accessbe81ec250d2df2ebadde393ea37a85a4.tex}}}} +\newcommand{\sailRISCVoverloadAvectorAccess}{\saildoclabelled{sailRISCVoverloadAzvectorzyaccess}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzvector_accessbe81ec250d2df2ebadde393ea37a85a4.tex}}}} \newcommand{\sailRISCVvalbitvectorUpdate}{\saildoclabelled{sailRISCVzbitvectorzyupdate}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzbitvector_update20826799a1ff3ff40895206db0df14bb.tex}}}} \newcommand{\sailRISCVvalplainVectorUpdate}{\saildoclabelled{sailRISCVzplainzyvectorzyupdate}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzplain_vector_updateb31d67bfe51b1a6f79983347dfc57da0.tex}}}} -\newcommand{\sailRISCVoverloadAAvectorUpdate}{\saildoclabelled{sailRISCVoverloadAAzvectorzyupdate}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAAzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex}}}} +\newcommand{\sailRISCVoverloadAvectorUpdate}{\saildoclabelled{sailRISCVoverloadAzvectorzyupdate}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex}}}} \newcommand{\sailRISCVvaladdBits}{\saildoclabelled{sailRISCVzaddzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzadd_bits24373ffc11f289d5bb648df2f4f41b25.tex}}}} \newcommand{\sailRISCVvaladdBitsInt}{\saildoclabelled{sailRISCVzaddzybitszyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzadd_bits_inta5424052402522ff4653275c899f7543.tex}}}} -\newcommand{\sailRISCVoverloadBBzEightoperatorzZerozBzNine}{\saildoclabelled{sailRISCVoverloadBBzz8operatorz0zBz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBBzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex}}}} +\newcommand{\sailRISCVoverloadBzEightoperatorzZerozBzNine}{\saildoclabelled{sailRISCVoverloadBzz8operatorz0zBz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex}}}} \newcommand{\sailRISCVvalsubBits}{\saildoclabelled{sailRISCVzsubzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsub_bitsf0dc4fc3429d45517c523db21af72127.tex}}}} @@ -271,21 +271,21 @@ \newcommand{\sailRISCVvalandVec}{\saildoclabelled{sailRISCVzandzyvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzand_vec99be3fe45d23194b597520c9e407ad35.tex}}}} -\newcommand{\sailRISCVoverloadCCzEightoperatorzZerozSixzNine}{\saildoclabelled{sailRISCVoverloadCCzz8operatorz0z6z9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCCzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex}}}} +\newcommand{\sailRISCVoverloadBzEightoperatorzZerozSixzNine}{\saildoclabelled{sailRISCVoverloadBzz8operatorz0z6z9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex}}}} \newcommand{\sailRISCVvalorVec}{\saildoclabelled{sailRISCVzorzyvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzor_vec467c7a3f74be27085fe1b2aa3651ffe7.tex}}}} -\newcommand{\sailRISCVoverloadDDzEightoperatorzZerozUzNine}{\saildoclabelled{sailRISCVoverloadDDzz8operatorz0zUz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDDzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex}}}} +\newcommand{\sailRISCVoverloadBzEightoperatorzZerozUzNine}{\saildoclabelled{sailRISCVoverloadBzz8operatorz0zUz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex}}}} \newcommand{\sailRISCVvalxorVec}{\saildoclabelled{sailRISCVzxorzyvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzxor_vecdacd54acc32f073fb01d1c188177bc8c.tex}}}} \newcommand{\sailRISCVvalsubrangeBits}{\saildoclabelled{sailRISCVzsubrangezybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsubrange_bits6c497c14df4f4754bd345a6c56ca2aad.tex}}}} -\newcommand{\sailRISCVoverloadEEvectorSubrange}{\saildoclabelled{sailRISCVoverloadEEzvectorzysubrange}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEEzvector_subrange270c799ffa6c20b5244f22c64fba0367.tex}}}} +\newcommand{\sailRISCVoverloadAvectorSubrange}{\saildoclabelled{sailRISCVoverloadAzvectorzysubrange}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzvector_subrange270c799ffa6c20b5244f22c64fba0367.tex}}}} \newcommand{\sailRISCVvalupdateSubrangeBits}{\saildoclabelled{sailRISCVzupdatezysubrangezybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzupdate_subrange_bitsb5ffe862b26310b45a779cd45bbf041e.tex}}}} -\newcommand{\sailRISCVoverloadFFvectorUpdateSubrange}{\saildoclabelled{sailRISCVoverloadFFzvectorzyupdatezysubrange}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFFzvector_update_subrangeb77be803268d55f5f112399f9d0dfbc2.tex}}}} +\newcommand{\sailRISCVoverloadAvectorUpdateSubrange}{\saildoclabelled{sailRISCVoverloadAzvectorzyupdatezysubrange}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzvector_update_subrangeb77be803268d55f5f112399f9d0dfbc2.tex}}}} \newcommand{\sailRISCVvalsailShiftleft}{\saildoclabelled{sailRISCVzsailzyshiftleft}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsail_shiftlefta7bc10407d10355c4e981688c9926084.tex}}}} @@ -321,7 +321,7 @@ }{\lstinputlisting[language=sail]{sail_latex_riscv/valzsigned36d2317f34f1dacb4e465e6e56b185e6.tex}}}} -\newcommand{\sailRISCVoverloadGGSizze}{\saildoclabelled{sailRISCVoverloadGGzzyzysizze}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGGz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex}}}} +\newcommand{\sailRISCVoverloadBSizze}{\saildoclabelled{sailRISCVoverloadBzzyzysizze}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex}}}} \newcommand{\sailRISCVtyperegfp}{\saildoclabelled{sailRISCVtypezregfp}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezregfpedcf3a6440b11288a4e07504f1ebdfae.tex}}}} @@ -431,7 +431,7 @@ \newcommand{\sailRISCVvaleqAnything}{\saildoclabelled{sailRISCVzeqzyanything}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzeq_anything99dff1d931070d33dac5c755eae24439.tex}}}} -\newcommand{\sailRISCVoverloadHHzEightoperatorzZerozJzJzNine}{\saildoclabelled{sailRISCVoverloadHHzz8operatorz0zJzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHHzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex}}}} +\newcommand{\sailRISCVoverloadDzEightoperatorzZerozJzJzNine}{\saildoclabelled{sailRISCVoverloadDzz8operatorz0zJzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex}}}} \newcommand{\sailRISCVvalregDeref}{\saildoclabelled{sailRISCVzregzyderef}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzreg_deref8bd1d78c61978d7074c7e0e5195e4bf7.tex}}}} @@ -439,19 +439,19 @@ \newcommand{\sailRISCVvalanyVectorUpdate}{\saildoclabelled{sailRISCVzanyzyvectorzyupdate}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzany_vector_updatef0077a3dd1846db0e7c8f84fa1a2eed5.tex}}}} -\newcommand{\sailRISCVoverloadIIvectorUpdate}{\saildoclabelled{sailRISCVoverloadIIzvectorzyupdate}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIIzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex}}}} +\newcommand{\sailRISCVoverloadBvectorUpdate}{\saildoclabelled{sailRISCVoverloadBzvectorzyupdate}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex}}}} \newcommand{\sailRISCVvalupdateSubrange}{\saildoclabelled{sailRISCVzupdatezysubrange}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzupdate_subrangea3cf2a13bfd32a2a89bc44a498800493.tex}}}} \newcommand{\sailRISCVvalvectorConcat}{\saildoclabelled{sailRISCVzvectorzyconcat}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzvector_concate0e61f7c9864d8d335d1f5c434546f7c.tex}}}} -\newcommand{\sailRISCVoverloadJJappend}{\saildoclabelled{sailRISCVoverloadJJzappend}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJJzappend88575169e0ec1639b6ae3851df999710.tex}}}} +\newcommand{\sailRISCVoverloadBappend}{\saildoclabelled{sailRISCVoverloadBzappend}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBzappend88575169e0ec1639b6ae3851df999710.tex}}}} \newcommand{\sailRISCVvalnotBit}{\saildoclabelled{sailRISCVznotzybit}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznot_bit3b618f3ab6887bbe967eaa12bf52b297.tex}}}} \newcommand{\sailRISCVfnnotBit}{\saildoclabelled{sailRISCVfnznotzybit}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznot_bit3b618f3ab6887bbe967eaa12bf52b297.tex}}}} -\newcommand{\sailRISCVoverloadKKzW}{\saildoclabelled{sailRISCVoverloadKKzzW}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadKKzzw805a9067649c7cfeedcb41b57a7e2c86.tex}}}} +\newcommand{\sailRISCVoverloadAzW}{\saildoclabelled{sailRISCVoverloadAzzW}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzzw805a9067649c7cfeedcb41b57a7e2c86.tex}}}} \newcommand{\sailRISCVvalnot}{\saildoclabelled{sailRISCVznot}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznotcbe861867f25b28c34f5ae99957794ed.tex}}}} @@ -463,11 +463,11 @@ \newcommand{\sailRISCVfnneqAnything}{\saildoclabelled{sailRISCVfnzneqzyanything}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzneq_anythingf220233154ca93d75c0323f604bb8d16.tex}}}} -\newcommand{\sailRISCVoverloadLLzEightoperatorzZerozOnezJzNine}{\saildoclabelled{sailRISCVoverloadLLzz8operatorz0z1zJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadLLzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex}}}} +\newcommand{\sailRISCVoverloadCzEightoperatorzZerozOnezJzNine}{\saildoclabelled{sailRISCVoverloadCzz8operatorz0z1zJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex}}}} -\newcommand{\sailRISCVoverloadMMzEightoperatorzZerozSixzNine}{\saildoclabelled{sailRISCVoverloadMMzz8operatorz0z6z9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadMMzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex}}}} +\newcommand{\sailRISCVoverloadCzEightoperatorzZerozSixzNine}{\saildoclabelled{sailRISCVoverloadCzz8operatorz0z6z9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex}}}} -\newcommand{\sailRISCVoverloadNNzEightoperatorzZerozUzNine}{\saildoclabelled{sailRISCVoverloadNNzz8operatorz0zUz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadNNzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex}}}} +\newcommand{\sailRISCVoverloadCzEightoperatorzZerozUzNine}{\saildoclabelled{sailRISCVoverloadCzz8operatorz0zUz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex}}}} \newcommand{\sailRISCVvalstringOfInt}{\saildoclabelled{sailRISCVzstringzyofzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzstring_of_int03988e4e2d2976513793427ac823afbe.tex}}}} @@ -477,33 +477,33 @@ \newcommand{\sailRISCVfnstringOfBit}{\saildoclabelled{sailRISCVfnzstringzyofzybit}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzstring_of_bit7313cdbf7b05129d4977581f9bb14794.tex}}}} -\newcommand{\sailRISCVoverloadOOBitStr}{\saildoclabelled{sailRISCVoverloadOOzBitStr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadOOzbitstr0d04da018975c4776e05a9c59c2e380e.tex}}}} +\newcommand{\sailRISCVoverloadABitStr}{\saildoclabelled{sailRISCVoverloadAzBitStr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzbitstr0d04da018975c4776e05a9c59c2e380e.tex}}}} \newcommand{\sailRISCVvalintPower}{\saildoclabelled{sailRISCVzintzypower}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzint_powerb0c5fc1a9fb0852260414607a93aeae6.tex}}}} -\newcommand{\sailRISCVoverloadPPzEightoperatorzZerozQzNine}{\saildoclabelled{sailRISCVoverloadPPzz8operatorz0zQz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadPPzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex}}}} +\newcommand{\sailRISCVoverloadBzEightoperatorzZerozQzNine}{\saildoclabelled{sailRISCVoverloadBzz8operatorz0zQz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex}}}} \newcommand{\sailRISCVvalsubVec}{\saildoclabelled{sailRISCVzsubzyvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsub_vec326e0ba0bb00229be26645e2d44dbd83.tex}}}} \newcommand{\sailRISCVvalsubVecInt}{\saildoclabelled{sailRISCVzsubzyveczyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsub_vec_int5e6c04459782b1b8cc706ba2e4c8a435.tex}}}} -\newcommand{\sailRISCVoverloadQQzEightoperatorzZerozDzNine}{\saildoclabelled{sailRISCVoverloadQQzz8operatorz0zDz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadQQzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex}}}} +\newcommand{\sailRISCVoverloadBzEightoperatorzZerozDzNine}{\saildoclabelled{sailRISCVoverloadBzz8operatorz0zDz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex}}}} \newcommand{\sailRISCVvalquotRoundZero}{\saildoclabelled{sailRISCVzquotzyroundzyzzero}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzquot_round_zzeroa8d9d278dc91a14956dfe19d01766403.tex}}}} \newcommand{\sailRISCVvalremRoundZero}{\saildoclabelled{sailRISCVzremzyroundzyzzero}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzrem_round_zzero90d115d6c3e756b94f7766d1b76fbb83.tex}}}} -\newcommand{\sailRISCVoverloadRRzEightoperatorzZerozFivezNine}{\saildoclabelled{sailRISCVoverloadRRzz8operatorz0z5z9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadRRzz8operatorz0z5z9194a289f0ceb02e29c9b6febc5146071.tex}}}} +\newcommand{\sailRISCVoverloadAzEightoperatorzZerozFivezNine}{\saildoclabelled{sailRISCVoverloadAzz8operatorz0z5z9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzz8operatorz0z5z9194a289f0ceb02e29c9b6febc5146071.tex}}}} \newcommand{\sailRISCVvalminInt}{\saildoclabelled{sailRISCVzminzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmin_intaf4626ab3b9c2d0b9494d7e8d265dd26.tex}}}} \newcommand{\sailRISCVvalmaxInt}{\saildoclabelled{sailRISCVzmaxzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmax_inta8f95a0baf723be8373221a893afa8f3.tex}}}} -\newcommand{\sailRISCVoverloadSSmin}{\saildoclabelled{sailRISCVoverloadSSzmin}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadSSzmin95ae3c0ebde1421750e6db87bdf74801.tex}}}} +\newcommand{\sailRISCVoverloadAmin}{\saildoclabelled{sailRISCVoverloadAzmin}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzmin95ae3c0ebde1421750e6db87bdf74801.tex}}}} -\newcommand{\sailRISCVoverloadTTmax}{\saildoclabelled{sailRISCVoverloadTTzmax}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadTTzmax91b641c464c0dc87660499321a356d93.tex}}}} +\newcommand{\sailRISCVoverloadAmax}{\saildoclabelled{sailRISCVoverloadAzmax}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzmax91b641c464c0dc87660499321a356d93.tex}}}} \newcommand{\sailRISCVvalpowTwo}{\saildoclabelled{sailRISCVzpow2}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpow2e971ce2f9ebb899590551317286dfd1b.tex}}}} @@ -547,7 +547,7 @@ \newcommand{\sailRISCVfnzzerosImplicit}{\saildoclabelled{sailRISCVfnzzzeroszyimplicit}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzzzeros_implicitce1dd4153c9a1823a9697c4472c43ebf.tex}}}} -\newcommand{\sailRISCVoverloadUUzzeros}{\saildoclabelled{sailRISCVoverloadUUzzzeros}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadUUzzzerosc530711942e216cef3921733c1c5d101.tex}}}} +\newcommand{\sailRISCVoverloadAzzeros}{\saildoclabelled{sailRISCVoverloadAzzzeros}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzzzerosc530711942e216cef3921733c1c5d101.tex}}}} \newcommand{\sailRISCVvalones}{\saildoclabelled{sailRISCVzones}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzones26f94136f5db8afd4e9df1e512f7fdc5.tex}}}} @@ -593,9 +593,9 @@ \newcommand{\sailRISCVvalshiftr}{\saildoclabelled{sailRISCVzshiftr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzshiftr173b7dba7206ed1b61a12344bdf9182a.tex}}}} -\newcommand{\sailRISCVoverloadVVzEightoperatorzZerozKzKzNine}{\saildoclabelled{sailRISCVoverloadVVzz8operatorz0zKzKz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadVVzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex}}}} +\newcommand{\sailRISCVoverloadAzEightoperatorzZerozKzKzNine}{\saildoclabelled{sailRISCVoverloadAzz8operatorz0zKzKz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex}}}} -\newcommand{\sailRISCVoverloadWWzEightoperatorzZerozIzIzNine}{\saildoclabelled{sailRISCVoverloadWWzz8operatorz0zIzIz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadWWzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex}}}} +\newcommand{\sailRISCVoverloadAzEightoperatorzZerozIzIzNine}{\saildoclabelled{sailRISCVoverloadAzz8operatorz0zIzIz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex}}}} \newcommand{\sailRISCVvalshiftRightArithSixFour}{\saildoclabelled{sailRISCVzshiftzyrightzyarith64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzshift_right_arith642d6a56971daae2b1fdb862ebbbaf6a46.tex}}}} @@ -621,15 +621,15 @@ \newcommand{\sailRISCVfnrotatel}{\saildoclabelled{sailRISCVfnzrotatel}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzrotatelf071331b6fd023da4d264842a39a016a.tex}}}} -\newcommand{\sailRISCVoverloadXXzEightoperatorzZerozKzKzKzNine}{\saildoclabelled{sailRISCVoverloadXXzz8operatorz0zKzKzKz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadXXzz8operatorz0zkzkzkz957fa2f300078df169cd8f1b6939b710d.tex}}}} +\newcommand{\sailRISCVoverloadAzEightoperatorzZerozKzKzKzNine}{\saildoclabelled{sailRISCVoverloadAzz8operatorz0zKzKzKz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzz8operatorz0zkzkzkz957fa2f300078df169cd8f1b6939b710d.tex}}}} -\newcommand{\sailRISCVoverloadYYzEightoperatorzZerozIzIzIzNine}{\saildoclabelled{sailRISCVoverloadYYzz8operatorz0zIzIzIz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadYYzz8operatorz0ziziziz9daf9b9d2ffdbec7af40418527044fa38.tex}}}} +\newcommand{\sailRISCVoverloadAzEightoperatorzZerozIzIzIzNine}{\saildoclabelled{sailRISCVoverloadAzz8operatorz0zIzIzIz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzz8operatorz0ziziziz9daf9b9d2ffdbec7af40418527044fa38.tex}}}} \newcommand{\sailRISCVvalreverseBitsInByte}{\saildoclabelled{sailRISCVzreversezybitszyinzybyte}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzreverse_bits_in_byte37f50ef4b8566a812c20f22ef8bba201.tex}}}} \newcommand{\sailRISCVfnreverseBitsInByte}{\saildoclabelled{sailRISCVfnzreversezybitszyinzybyte}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzreverse_bits_in_byte37f50ef4b8566a812c20f22ef8bba201.tex}}}} -\newcommand{\sailRISCVoverloadZZreverse}{\saildoclabelled{sailRISCVoverloadZZzreverse}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadZZzreversed9f0df85c2b57ca70b0103d18920d22f.tex}}}} +\newcommand{\sailRISCVoverloadAreverse}{\saildoclabelled{sailRISCVoverloadAzreverse}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzreversed9f0df85c2b57ca70b0103d18920d22f.tex}}}} \newcommand{\sailRISCVvalspc}{\saildoclabelled{sailRISCVzspc}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzspca574d99b4c3d28e08386a1f673633994.tex}}}} @@ -1337,6 +1337,18 @@ \newcommand{\sailRISCVfnboolToBit}{\saildoclabelled{sailRISCVfnzboolzytozybit}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzbool_to_bit5cc99dc0718457cc8a182fa8507f045a.tex}}}} +\newcommand{\sailRISCVvalhaveCheriRelocation}{\saildoclabelled{sailRISCVzhavezycherizyrelocation}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhave_cheri_relocationbbe9a9f5c01227424d0cc8330de5d0b3.tex}}}} + +\newcommand{\sailRISCVfnhaveCheriRelocation}{\saildoclabelled{sailRISCVfnzhavezycherizyrelocation}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhave_cheri_relocationbbe9a9f5c01227424d0cc8330de5d0b3.tex}}}} + +\newcommand{\sailRISCVvalhaveDdcRelocation}{\saildoclabelled{sailRISCVzhavezyddczyrelocation}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhave_ddc_relocationcdaa2a12594a6d0db423bcedfc636210.tex}}}} + +\newcommand{\sailRISCVfnhaveDdcRelocation}{\saildoclabelled{sailRISCVfnzhavezyddczyrelocation}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhave_ddc_relocationcdaa2a12594a6d0db423bcedfc636210.tex}}}} + +\newcommand{\sailRISCVvalhavePccRelocation}{\saildoclabelled{sailRISCVzhavezypcczyrelocation}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhave_pcc_relocation8ef276f0f56e5c3343729212dcd97cb5.tex}}}} + +\newcommand{\sailRISCVfnhavePccRelocation}{\saildoclabelled{sailRISCVfnzhavezypcczyrelocation}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhave_pcc_relocation8ef276f0f56e5c3343729212dcd97cb5.tex}}}} + \newcommand{\sailRISCVletreservedOtypes}{\saildoclabelled{sailRISCVletzreservedzyotypes}{\saildoclet{}{\lstinputlisting[language=sail]{sail_latex_riscv/letzreserved_otypesfc67c8a176aa3efad89f5a340aec39ac.tex}}}} \newcommand{\sailRISCVletotypeUnsealed}{\saildoclabelled{sailRISCVletzotypezyunsealed}{\saildoclet{}{\lstinputlisting[language=sail]{sail_latex_riscv/letzotype_unsealed27aafb55f546c5283a4542e7c4697e4f.tex}}}} @@ -1676,11 +1688,15 @@ \newcommand{\sailRISCVfnsetCapAddr}{\saildoclabelled{sailRISCVfnzsetCapAddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzsetcapaddr35ad6dc7effb74b141243b59c9daceff.tex}}}} -\newcommand{\sailRISCVoverloadAAAzEightoperatorzZerozKzKzNine}{\saildoclabelled{sailRISCVoverloadAAAzz8operatorz0zKzKz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAAAzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex}}}} +\newcommand{\sailRISCVvalsetCapAddrChecked}{\saildoclabelled{sailRISCVzsetCapAddrChecked}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsetcapaddrchecked02f3e6fc454faf7b488ed3661fb1a85e.tex}}}} -\newcommand{\sailRISCVoverloadBBBzEightoperatorzZerozIzIzNine}{\saildoclabelled{sailRISCVoverloadBBBzz8operatorz0zIzIz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBBBzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex}}}} +\newcommand{\sailRISCVfnsetCapAddrChecked}{\saildoclabelled{sailRISCVfnzsetCapAddrChecked}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzsetcapaddrchecked02f3e6fc454faf7b488ed3661fb1a85e.tex}}}} -\newcommand{\sailRISCVoverloadCCCzEightoperatorzZerozKzKSzNine}{\saildoclabelled{sailRISCVoverloadCCCzz8operatorz0zKzKzysz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCCCzz8operatorz0zkzk_sz9fd336467c8d7c9163cb44b900cb10522.tex}}}} +\newcommand{\sailRISCVoverloadBzEightoperatorzZerozKzKzNine}{\saildoclabelled{sailRISCVoverloadBzz8operatorz0zKzKz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex}}}} + +\newcommand{\sailRISCVoverloadBzEightoperatorzZerozIzIzNine}{\saildoclabelled{sailRISCVoverloadBzz8operatorz0zIzIz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex}}}} + +\newcommand{\sailRISCVoverloadAzEightoperatorzZerozKzKSzNine}{\saildoclabelled{sailRISCVoverloadAzz8operatorz0zKzKzysz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzz8operatorz0zkzk_sz9fd336467c8d7c9163cb44b900cb10522.tex}}}} \newcommand{\sailRISCVvalfastRepCheck}{\saildoclabelled{sailRISCVzfastRepCheck}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfastrepcheck592cc92c49a4599da60647f87c331420.tex}}}} @@ -1710,6 +1726,14 @@ \newcommand{\sailRISCVfngetRepresentableLength}{\saildoclabelled{sailRISCVfnzgetRepresentableLength}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzgetrepresentablelengthad3bb54ef850e37183b86b40599239a6.tex}}}} +\newcommand{\sailRISCVvalcapToIntegerPc}{\saildoclabelled{sailRISCVzcapzytozyintegerzypc}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcap_to_integer_pcfb8f9e29d6bb00469db30a7b19649da3.tex}}}} + +\newcommand{\sailRISCVfncapToIntegerPc}{\saildoclabelled{sailRISCVfnzcapzytozyintegerzypc}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcap_to_integer_pcfb8f9e29d6bb00469db30a7b19649da3.tex}}}} + +\newcommand{\sailRISCVvalupdateCapWithIntegerPc}{\saildoclabelled{sailRISCVzupdatezycapzywithzyintegerzypc}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzupdate_cap_with_integer_pc9c66feb4cf9d3f64ba301705bf4cece5.tex}}}} + +\newcommand{\sailRISCVfnupdateCapWithIntegerPc}{\saildoclabelled{sailRISCVfnzupdatezycapzywithzyintegerzypc}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzupdate_cap_with_integer_pc9c66feb4cf9d3f64ba301705bf4cece5.tex}}}} + \newcommand{\sailRISCVtypeexcCode}{\saildoclabelled{sailRISCVtypezexczycode}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezexc_code41fa41b8abb196633a02f07b51e90738.tex}}}} \newcommand{\sailRISCVtypeextPtwLc}{\saildoclabelled{sailRISCVtypezextzyptwzylc}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezext_ptw_lcbba545a858359524aa6ef05819a4c22a.tex}}}} @@ -1881,7 +1905,7 @@ \newcommand{\sailRISCVfnprivLevelToStr}{\saildoclabelled{sailRISCVfnzprivLevelzytozystr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzprivlevel_to_str130b731da9dd60ea89c77efcbbe0d598.tex}}}} -\newcommand{\sailRISCVoverloadDDDtoStr}{\saildoclabelled{sailRISCVoverloadDDDztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDDDzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} +\newcommand{\sailRISCVoverloadAtoStr}{\saildoclabelled{sailRISCVoverloadAztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} \newcommand{\sailRISCVtypeRetired}{\saildoclabelled{sailRISCVtypezRetired}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezretired3cb36a9311620933468743a8b2d2f6f4.tex}}}} @@ -1933,7 +1957,7 @@ \newcommand{\sailRISCVfnexceptionTypeToStr}{\saildoclabelled{sailRISCVfnzexceptionTypezytozystr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzexceptiontype_to_str566b70f16fdf6ed4d1850ec75465ec4b.tex}}}} -\newcommand{\sailRISCVoverloadEEEtoStr}{\saildoclabelled{sailRISCVoverloadEEEztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEEEzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} +\newcommand{\sailRISCVoverloadBtoStr}{\saildoclabelled{sailRISCVoverloadBztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} \newcommand{\sailRISCVtypetvMode}{\saildoclabelled{sailRISCVtypeztvzymode}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typeztv_modea724d5138c36f1ab6005c9051bd94ea0.tex}}}} @@ -2159,6 +2183,16 @@ \newcommand{\sailRISCVfnnumOfExtopZbb}{\saildoclabelled{sailRISCVfnznumzyofzyextopzyzzbb}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_extop_zzbbccc649422c5281a2100c3e881e0f493a.tex}}}} +\newcommand{\sailRISCVtypezzicondop}{\saildoclabelled{sailRISCVtypezzzicondop}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezzzicondopa7aca235781cdb8d229dc510abbddd29.tex}}}} + +\newcommand{\sailRISCVvalzzicondopOfNum}{\saildoclabelled{sailRISCVzzzicondopzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzzzicondop_of_num6c236bc72d5e4b8fcf599f8f5df132a1.tex}}}} + +\newcommand{\sailRISCVfnzzicondopOfNum}{\saildoclabelled{sailRISCVfnzzzicondopzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzzzicondop_of_num6c236bc72d5e4b8fcf599f8f5df132a1.tex}}}} + +\newcommand{\sailRISCVvalnumOfZicondop}{\saildoclabelled{sailRISCVznumzyofzyzzicondop}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_zzicondop3e6d4701d8934768c6aaf82a93f9c62d.tex}}}} + +\newcommand{\sailRISCVfnnumOfZicondop}{\saildoclabelled{sailRISCVfnznumzyofzyzzicondop}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_zzicondop3e6d4701d8934768c6aaf82a93f9c62d.tex}}}} + \newcommand{\sailRISCVvalsep}{\saildoclabelled{sailRISCVzsep}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsep43dac566d26bd3f7fb9088b8d09ca246.tex}}}} \newcommand{\sailRISCVvalboolBits}{\saildoclabelled{sailRISCVzboolzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzbool_bitsc0498d89cd314b64ec44bc657a0630ec.tex}}}} @@ -2380,7 +2414,7 @@ \newcommand{\sailRISCVvalcsrName}{\saildoclabelled{sailRISCVzcsrzyname}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcsr_name355619c0d72f0a56dfaf2d45f4b72967.tex}}}} -\newcommand{\sailRISCVoverloadFFFtoStr}{\saildoclabelled{sailRISCVoverloadFFFztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFFFzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} +\newcommand{\sailRISCVoverloadCtoStr}{\saildoclabelled{sailRISCVoverloadCztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} \newcommand{\sailRISCVvalextIsCSRDefined}{\saildoclabelled{sailRISCVzextzyiszyCSRzydefined}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex}}}} @@ -2392,7 +2426,7 @@ \newcommand{\sailRISCVvalscrName}{\saildoclabelled{sailRISCVzscrzyname}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzscr_name18d33d5c24513d7598c403423ce2f8e6.tex}}}} -\newcommand{\sailRISCVoverloadGGGtoStr}{\saildoclabelled{sailRISCVoverloadGGGztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGGGzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} +\newcommand{\sailRISCVoverloadDtoStr}{\saildoclabelled{sailRISCVoverloadDztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} \newcommand{\sailRISCVtypeextAccessType}{\saildoclabelled{sailRISCVtypezextzyaccesszytype}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezext_access_type8c60f923ce211fcdc0c77548b866673e.tex}}}} @@ -2410,7 +2444,7 @@ \newcommand{\sailRISCVfnaccessTypeToStr}{\saildoclabelled{sailRISCVfnzaccessTypezytozystr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzaccesstype_to_str58f7a46d6b3e326411426e3cf0fe52cf.tex}}}} -\newcommand{\sailRISCVoverloadHHHtoStr}{\saildoclabelled{sailRISCVoverloadHHHztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHHHzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} +\newcommand{\sailRISCVoverloadEtoStr}{\saildoclabelled{sailRISCVoverloadEztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} \newcommand{\sailRISCVregisterPC}{\saildoclabelled{sailRISCVregisterzPC}{\saildocregister{}{\lstinputlisting[language=sail]{sail_latex_riscv/registerzpcedbec7ccca699bef927f7d0d14fdf9d7.tex}}}} @@ -2500,13 +2534,13 @@ \newcommand{\sailRISCVfnwXBits}{\saildoclabelled{sailRISCVfnzwXzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwx_bitseb6ef5be72b31b8cb0f1595602665261.tex}}}} -\newcommand{\sailRISCVoverloadIIIX}{\saildoclabelled{sailRISCVoverloadIIIzX}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIIIzx1f3c57dd04ac52fd92f3346ca51f00ec.tex}}}} +\newcommand{\sailRISCVoverloadAX}{\saildoclabelled{sailRISCVoverloadAzX}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzx1f3c57dd04ac52fd92f3346ca51f00ec.tex}}}} \newcommand{\sailRISCVvalregNameAbi}{\saildoclabelled{sailRISCVzregzynamezyabi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzreg_name_abi8c36e923dc671675cb54fb0175878a3f.tex}}}} \newcommand{\sailRISCVfnregNameAbi}{\saildoclabelled{sailRISCVfnzregzynamezyabi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzreg_name_abi8c36e923dc671675cb54fb0175878a3f.tex}}}} -\newcommand{\sailRISCVoverloadJJJtoStr}{\saildoclabelled{sailRISCVoverloadJJJztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJJJzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} +\newcommand{\sailRISCVoverloadFtoStr}{\saildoclabelled{sailRISCVoverloadFztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} \newcommand{\sailRISCVvalregName}{\saildoclabelled{sailRISCVzregzyname}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzreg_namea3a934e14215c11bd841e5d2fb4f53e0.tex}}}} @@ -2580,9 +2614,9 @@ \newcommand{\sailRISCVfnhaveZbs}{\saildoclabelled{sailRISCVfnzhaveZbs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhavezbsb73d7808e3c6776f16235f4053e14f92.tex}}}} -\newcommand{\sailRISCVvalhaveZfh}{\saildoclabelled{sailRISCVzhaveZfh}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhavezfhe5dbd348c0b6c69910aec2c1edb56adf.tex}}}} +\newcommand{\sailRISCVvalhaveZfa}{\saildoclabelled{sailRISCVzhaveZfa}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhavezfa170943288777f725fbf88904d27d506e.tex}}}} -\newcommand{\sailRISCVfnhaveZfh}{\saildoclabelled{sailRISCVfnzhaveZfh}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhavezfhe5dbd348c0b6c69910aec2c1edb56adf.tex}}}} +\newcommand{\sailRISCVfnhaveZfa}{\saildoclabelled{sailRISCVfnzhaveZfa}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhavezfa170943288777f725fbf88904d27d506e.tex}}}} \newcommand{\sailRISCVvalhaveZbkb}{\saildoclabelled{sailRISCVzhaveZbkb}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhavezbkbb2448f035d58b7d5497beaa1d54a8db4.tex}}}} @@ -2624,6 +2658,10 @@ \newcommand{\sailRISCVfnhaveZmmul}{\saildoclabelled{sailRISCVfnzhaveZmmul}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhavezmmul9f897872e00093149d077731f7a24ffb.tex}}}} +\newcommand{\sailRISCVvalhaveZicond}{\saildoclabelled{sailRISCVzhaveZicond}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhavezicond942507aaca8f56a8d3fc5cd08536c028.tex}}}} + +\newcommand{\sailRISCVfnhaveZicond}{\saildoclabelled{sailRISCVfnzhaveZicond}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhavezicond942507aaca8f56a8d3fc5cd08536c028.tex}}}} + \newcommand{\sailRISCVtypeMstatush}{\saildoclabelled{sailRISCVtypezMstatush}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezmstatushbe19a0fd111f7cf462e74397c744ddef.tex}}}} \newcommand{\sailRISCVregistermstatush}{\saildoclabelled{sailRISCVregisterzmstatush}{\saildocregister{}{\lstinputlisting[language=sail]{sail_latex_riscv/registerzmstatush99e415e2be0d9f55ef4d84aa3694681f.tex}}}} @@ -2672,6 +2710,10 @@ \newcommand{\sailRISCVfnhaveDExt}{\saildoclabelled{sailRISCVfnzhaveDExt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhavedextbb6a692871d46f160484ca963a3fffd0.tex}}}} +\newcommand{\sailRISCVvalhaveZfh}{\saildoclabelled{sailRISCVzhaveZfh}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhavezfhe5dbd348c0b6c69910aec2c1edb56adf.tex}}}} + +\newcommand{\sailRISCVfnhaveZfh}{\saildoclabelled{sailRISCVfnzhaveZfh}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhavezfhe5dbd348c0b6c69910aec2c1edb56adf.tex}}}} + \newcommand{\sailRISCVvalhaveZhinx}{\saildoclabelled{sailRISCVzhaveZhinx}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhavezhinxd3b2b0b131eb0dedee007e834f875556.tex}}}} \newcommand{\sailRISCVfnhaveZhinx}{\saildoclabelled{sailRISCVfnzhaveZhinx}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhavezhinxd3b2b0b131eb0dedee007e834f875556.tex}}}} @@ -2770,7 +2812,7 @@ \newcommand{\sailRISCVregisterminstret}{\saildoclabelled{sailRISCVregisterzminstret}{\saildocregister{}{\lstinputlisting[language=sail]{sail_latex_riscv/registerzminstret542e7e5da16279d2bd90859b1533a6ee.tex}}}} -\newcommand{\sailRISCVregisterminstretWritten}{\saildoclabelled{sailRISCVregisterzminstretzywritten}{\saildocregister{}{\lstinputlisting[language=sail]{sail_latex_riscv/registerzminstret_writtenaed0046aa7ec44bb59b2c8c7710e05d2.tex}}}} +\newcommand{\sailRISCVregisterminstretIncrement}{\saildoclabelled{sailRISCVregisterzminstretzyincrement}{\saildocregister{}{\lstinputlisting[language=sail]{sail_latex_riscv/registerzminstret_increment4bf06d6ee65982630fdaccfdc2b150e1.tex}}}} \newcommand{\sailRISCVvalretireInstruction}{\saildoclabelled{sailRISCVzretirezyinstruction}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzretire_instructionc9e2e6b25fd8f4e5a96cd82a0dd2a675.tex}}}} @@ -3120,7 +3162,7 @@ \newcommand{\sailRISCVfnwCBits}{\saildoclabelled{sailRISCVfnzwCzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwc_bitsb8b2d4f53308d4bb8d154a1f6664d336.tex}}}} -\newcommand{\sailRISCVoverloadKKKC}{\saildoclabelled{sailRISCVoverloadKKKzC}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadKKKzc15f67105dab436b80b9241d87d1f8e9d.tex}}}} +\newcommand{\sailRISCVoverloadAC}{\saildoclabelled{sailRISCVoverloadAzC}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzc15f67105dab436b80b9241d87d1f8e9d.tex}}}} \newcommand{\sailRISCVvalextInitRegs}{\saildoclabelled{sailRISCVzextzyinitzyregs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_init_regs1d9ff00ce58fd5712eb26190e338015a.tex}}}} @@ -3138,7 +3180,7 @@ \newcommand{\sailRISCVfncapRegNameAbi}{\saildoclabelled{sailRISCVfnzcapzyregzynamezyabi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcap_reg_name_abi719d69842e8a63e886ffe0791675d4e0.tex}}}} -\newcommand{\sailRISCVoverloadLLLtoStr}{\saildoclabelled{sailRISCVoverloadLLLztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadLLLzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} +\newcommand{\sailRISCVoverloadGtoStr}{\saildoclabelled{sailRISCVoverloadGztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} \newcommand{\sailRISCVvalcapRegName}{\saildoclabelled{sailRISCVzcapzyregzyname}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcap_reg_name2541adc6dad121efe53209371c0fbc68.tex}}}} @@ -3578,12 +3620,24 @@ \newcommand{\sailRISCVfnriscvFOneSixLt}{\saildoclabelled{sailRISCVfnzriscvzyf16Lt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f16lta3ed2ba63f2bca9026b606ccfeb6ab64.tex}}}} +\newcommand{\sailRISCVvalexternFOneSixLtQuiet}{\saildoclabelled{sailRISCVzexternzyf16Ltzyquiet}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f16lt_quiet47c4bf08ad78e10df5bd97faf51ba75b.tex}}}} + +\newcommand{\sailRISCVvalriscvFOneSixLtQuiet}{\saildoclabelled{sailRISCVzriscvzyf16Ltzyquiet}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f16lt_quiet244f6ba5b2310a0cac1e04951f6afb9c.tex}}}} + +\newcommand{\sailRISCVfnriscvFOneSixLtQuiet}{\saildoclabelled{sailRISCVfnzriscvzyf16Ltzyquiet}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f16lt_quiet244f6ba5b2310a0cac1e04951f6afb9c.tex}}}} + \newcommand{\sailRISCVvalexternFOneSixLe}{\saildoclabelled{sailRISCVzexternzyf16Le}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f16le82541f452cc5ef9cea2bf63910c7157d.tex}}}} \newcommand{\sailRISCVvalriscvFOneSixLe}{\saildoclabelled{sailRISCVzriscvzyf16Le}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f16le898d0c1fa658c59f86be7840a63f5e17.tex}}}} \newcommand{\sailRISCVfnriscvFOneSixLe}{\saildoclabelled{sailRISCVfnzriscvzyf16Le}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f16le898d0c1fa658c59f86be7840a63f5e17.tex}}}} +\newcommand{\sailRISCVvalexternFOneSixLeQuiet}{\saildoclabelled{sailRISCVzexternzyf16Lezyquiet}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f16le_quietba87aa826fe2ea7c4186b6a7d2619883.tex}}}} + +\newcommand{\sailRISCVvalriscvFOneSixLeQuiet}{\saildoclabelled{sailRISCVzriscvzyf16Lezyquiet}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f16le_quiet8f63ce7ff3e42871a470478ce69c31a9.tex}}}} + +\newcommand{\sailRISCVfnriscvFOneSixLeQuiet}{\saildoclabelled{sailRISCVfnzriscvzyf16Lezyquiet}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f16le_quiet8f63ce7ff3e42871a470478ce69c31a9.tex}}}} + \newcommand{\sailRISCVvalexternFOneSixEq}{\saildoclabelled{sailRISCVzexternzyf16Eq}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f16eq051178e19b597007271114f150c7bf25.tex}}}} \newcommand{\sailRISCVvalriscvFOneSixEq}{\saildoclabelled{sailRISCVzriscvzyf16Eq}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f16eq3d04f3f3d3180635ecf8ff46df64bb5d.tex}}}} @@ -3596,12 +3650,24 @@ \newcommand{\sailRISCVfnriscvFThreeTwoLt}{\saildoclabelled{sailRISCVfnzriscvzyf32Lt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f32lt4e30f0abd945d0950f5c75c3397e58b8.tex}}}} +\newcommand{\sailRISCVvalexternFThreeTwoLtQuiet}{\saildoclabelled{sailRISCVzexternzyf32Ltzyquiet}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f32lt_quiet70f5a9ae1a77127a5cebd114c342108f.tex}}}} + +\newcommand{\sailRISCVvalriscvFThreeTwoLtQuiet}{\saildoclabelled{sailRISCVzriscvzyf32Ltzyquiet}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f32lt_quiet6805f79a39a589997e0e972ca2f211be.tex}}}} + +\newcommand{\sailRISCVfnriscvFThreeTwoLtQuiet}{\saildoclabelled{sailRISCVfnzriscvzyf32Ltzyquiet}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f32lt_quiet6805f79a39a589997e0e972ca2f211be.tex}}}} + \newcommand{\sailRISCVvalexternFThreeTwoLe}{\saildoclabelled{sailRISCVzexternzyf32Le}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f32le97e1d493296eff955b8dd2b74525e2ad.tex}}}} \newcommand{\sailRISCVvalriscvFThreeTwoLe}{\saildoclabelled{sailRISCVzriscvzyf32Le}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f32le5580a4448a4b6b5ef89a7a80b6f5e23a.tex}}}} \newcommand{\sailRISCVfnriscvFThreeTwoLe}{\saildoclabelled{sailRISCVfnzriscvzyf32Le}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f32le5580a4448a4b6b5ef89a7a80b6f5e23a.tex}}}} +\newcommand{\sailRISCVvalexternFThreeTwoLeQuiet}{\saildoclabelled{sailRISCVzexternzyf32Lezyquiet}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f32le_quiet8f7c77183e32b1b4c551a8457476d996.tex}}}} + +\newcommand{\sailRISCVvalriscvFThreeTwoLeQuiet}{\saildoclabelled{sailRISCVzriscvzyf32Lezyquiet}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f32le_quiet7e5f820135a916f973026964c0ce90bf.tex}}}} + +\newcommand{\sailRISCVfnriscvFThreeTwoLeQuiet}{\saildoclabelled{sailRISCVfnzriscvzyf32Lezyquiet}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f32le_quiet7e5f820135a916f973026964c0ce90bf.tex}}}} + \newcommand{\sailRISCVvalexternFThreeTwoEq}{\saildoclabelled{sailRISCVzexternzyf32Eq}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f32eq1152b8b8a8d02d885ad3651e36443f8b.tex}}}} \newcommand{\sailRISCVvalriscvFThreeTwoEq}{\saildoclabelled{sailRISCVzriscvzyf32Eq}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f32eqbb5f45f4706cd2893dcaf9d3d15d7b11.tex}}}} @@ -3614,18 +3680,48 @@ \newcommand{\sailRISCVfnriscvFSixFourLt}{\saildoclabelled{sailRISCVfnzriscvzyf64Lt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f64lt7fe1cae2d039f2771557eafe4cff0d62.tex}}}} +\newcommand{\sailRISCVvalexternFSixFourLtQuiet}{\saildoclabelled{sailRISCVzexternzyf64Ltzyquiet}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f64lt_quietb909aef2c69da0356d6e4e66ceaba06b.tex}}}} + +\newcommand{\sailRISCVvalriscvFSixFourLtQuiet}{\saildoclabelled{sailRISCVzriscvzyf64Ltzyquiet}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f64lt_quiet14ab1c593c5d6a2b683a6949da76b09d.tex}}}} + +\newcommand{\sailRISCVfnriscvFSixFourLtQuiet}{\saildoclabelled{sailRISCVfnzriscvzyf64Ltzyquiet}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f64lt_quiet14ab1c593c5d6a2b683a6949da76b09d.tex}}}} + \newcommand{\sailRISCVvalexternFSixFourLe}{\saildoclabelled{sailRISCVzexternzyf64Le}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f64le607de75fdc830000d71db4eee82f8025.tex}}}} \newcommand{\sailRISCVvalriscvFSixFourLe}{\saildoclabelled{sailRISCVzriscvzyf64Le}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f64leedff2d39af8855d31503064db9e49593.tex}}}} \newcommand{\sailRISCVfnriscvFSixFourLe}{\saildoclabelled{sailRISCVfnzriscvzyf64Le}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f64leedff2d39af8855d31503064db9e49593.tex}}}} +\newcommand{\sailRISCVvalexternFSixFourLeQuiet}{\saildoclabelled{sailRISCVzexternzyf64Lezyquiet}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f64le_quiet62f25ed39def4a3e2df9a7320243076b.tex}}}} + +\newcommand{\sailRISCVvalriscvFSixFourLeQuiet}{\saildoclabelled{sailRISCVzriscvzyf64Lezyquiet}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f64le_quietdbcd45688456ae3af8949c7df7db62f7.tex}}}} + +\newcommand{\sailRISCVfnriscvFSixFourLeQuiet}{\saildoclabelled{sailRISCVfnzriscvzyf64Lezyquiet}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f64le_quietdbcd45688456ae3af8949c7df7db62f7.tex}}}} + \newcommand{\sailRISCVvalexternFSixFourEq}{\saildoclabelled{sailRISCVzexternzyf64Eq}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f64eqb2180e00de7f0745336b1c04e9ead3f3.tex}}}} \newcommand{\sailRISCVvalriscvFSixFourEq}{\saildoclabelled{sailRISCVzriscvzyf64Eq}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f64eq911a3686fab30a7dbcecd0d21d7bc788.tex}}}} \newcommand{\sailRISCVfnriscvFSixFourEq}{\saildoclabelled{sailRISCVfnzriscvzyf64Eq}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f64eq911a3686fab30a7dbcecd0d21d7bc788.tex}}}} +\newcommand{\sailRISCVvalexternFOneSixroundToInt}{\saildoclabelled{sailRISCVzexternzyf16roundToInt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f16roundtointf6702102443ea92a9f058ba571bbd8d7.tex}}}} + +\newcommand{\sailRISCVvalriscvFOneSixroundToInt}{\saildoclabelled{sailRISCVzriscvzyf16roundToInt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f16roundtoint52329eb13a3e4a06c8e70e0c4ef36e80.tex}}}} + +\newcommand{\sailRISCVfnriscvFOneSixroundToInt}{\saildoclabelled{sailRISCVfnzriscvzyf16roundToInt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f16roundtoint52329eb13a3e4a06c8e70e0c4ef36e80.tex}}}} + +\newcommand{\sailRISCVvalexternFThreeTworoundToInt}{\saildoclabelled{sailRISCVzexternzyf32roundToInt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f32roundtointfd564f319eaa6e135f5b6a5d1d839221.tex}}}} + +\newcommand{\sailRISCVvalriscvFThreeTworoundToInt}{\saildoclabelled{sailRISCVzriscvzyf32roundToInt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f32roundtoint33ebf4ca80343b549f0b5a1c93805348.tex}}}} + +\newcommand{\sailRISCVfnriscvFThreeTworoundToInt}{\saildoclabelled{sailRISCVfnzriscvzyf32roundToInt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f32roundtoint33ebf4ca80343b549f0b5a1c93805348.tex}}}} + +\newcommand{\sailRISCVvalexternFSixFourroundToInt}{\saildoclabelled{sailRISCVzexternzyf64roundToInt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f64roundtointa3a7bcf2dfbdc3862b468cb032011274.tex}}}} + +\newcommand{\sailRISCVvalriscvFSixFourroundToInt}{\saildoclabelled{sailRISCVzriscvzyf64roundToInt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f64roundtointc621d19070f8cdbcc8f4378ba7716a84.tex}}}} + +\newcommand{\sailRISCVfnriscvFSixFourroundToInt}{\saildoclabelled{sailRISCVfnzriscvzyf64roundToInt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f64roundtointc621d19070f8cdbcc8f4378ba7716a84.tex}}}} + \newcommand{\sailRISCVvalcanonicalNaNH}{\saildoclabelled{sailRISCVzcanonicalzyNaNzyH}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcanonical_nan_h080e1071b7703771f0be5ac164e23688.tex}}}} \newcommand{\sailRISCVfncanonicalNaNH}{\saildoclabelled{sailRISCVfnzcanonicalzyNaNzyH}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcanonical_nan_h080e1071b7703771f0be5ac164e23688.tex}}}} @@ -3654,9 +3750,9 @@ \newcommand{\sailRISCVfnnanUnboxS}{\saildoclabelled{sailRISCVfnznanzyunboxzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznan_unbox_s2dd91248bdb4ecea3585b7e5b65dec23.tex}}}} -\newcommand{\sailRISCVoverloadMMMnanBox}{\saildoclabelled{sailRISCVoverloadMMMznanzybox}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadMMMznan_boxf593e1648915be3a65ed1e1cf0dc7712.tex}}}} +\newcommand{\sailRISCVoverloadAnanBox}{\saildoclabelled{sailRISCVoverloadAznanzybox}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAznan_boxf593e1648915be3a65ed1e1cf0dc7712.tex}}}} -\newcommand{\sailRISCVoverloadNNNnanUnbox}{\saildoclabelled{sailRISCVoverloadNNNznanzyunbox}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadNNNznan_unbox6971c840905d637f635a4793907fe38e.tex}}}} +\newcommand{\sailRISCVoverloadAnanUnbox}{\saildoclabelled{sailRISCVoverloadAznanzyunbox}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAznan_unbox6971c840905d637f635a4793907fe38e.tex}}}} \newcommand{\sailRISCVregisterfZero}{\saildoclabelled{sailRISCVregisterzf0}{\saildocregister{}{\lstinputlisting[language=sail]{sail_latex_riscv/registerzf093fe33c56e357cae27506236b348348d.tex}}}} @@ -3746,7 +3842,37 @@ \newcommand{\sailRISCVfnwFBits}{\saildoclabelled{sailRISCVfnzwFzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwf_bits141c8aafc4ef81f118d39a00d8a5249d.tex}}}} -\newcommand{\sailRISCVoverloadOOOF}{\saildoclabelled{sailRISCVoverloadOOOzF}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadOOOzf71805d10b9ea2a56437652aba0daf9bf.tex}}}} +\newcommand{\sailRISCVoverloadAF}{\saildoclabelled{sailRISCVoverloadAzF}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzf71805d10b9ea2a56437652aba0daf9bf.tex}}}} + +\newcommand{\sailRISCVvalrFH}{\saildoclabelled{sailRISCVzrFzyH}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzrf_hf87446c77cdaf455431ea51fc65d658a.tex}}}} + +\newcommand{\sailRISCVfnrFH}{\saildoclabelled{sailRISCVfnzrFzyH}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzrf_hf87446c77cdaf455431ea51fc65d658a.tex}}}} + +\newcommand{\sailRISCVvalwFH}{\saildoclabelled{sailRISCVzwFzyH}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwf_hb915a10402ec9321c4ad1188ae0afc9f.tex}}}} + +\newcommand{\sailRISCVfnwFH}{\saildoclabelled{sailRISCVfnzwFzyH}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwf_hb915a10402ec9321c4ad1188ae0afc9f.tex}}}} + +\newcommand{\sailRISCVvalrFS}{\saildoclabelled{sailRISCVzrFzyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzrf_sae821dae13888ed4dd6a166d80f9c14c.tex}}}} + +\newcommand{\sailRISCVfnrFS}{\saildoclabelled{sailRISCVfnzrFzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzrf_sae821dae13888ed4dd6a166d80f9c14c.tex}}}} + +\newcommand{\sailRISCVvalwFS}{\saildoclabelled{sailRISCVzwFzyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwf_s8b4c2b923b5bc2d4c6f88cff982b6695.tex}}}} + +\newcommand{\sailRISCVfnwFS}{\saildoclabelled{sailRISCVfnzwFzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwf_s8b4c2b923b5bc2d4c6f88cff982b6695.tex}}}} + +\newcommand{\sailRISCVvalrFD}{\saildoclabelled{sailRISCVzrFzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzrf_d29c6729673402bec577925987b943174.tex}}}} + +\newcommand{\sailRISCVfnrFD}{\saildoclabelled{sailRISCVfnzrFzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzrf_d29c6729673402bec577925987b943174.tex}}}} + +\newcommand{\sailRISCVvalwFD}{\saildoclabelled{sailRISCVzwFzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwf_d94c91aff56d9566b109d96edd2d1663f.tex}}}} + +\newcommand{\sailRISCVfnwFD}{\saildoclabelled{sailRISCVfnzwFzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwf_d94c91aff56d9566b109d96edd2d1663f.tex}}}} + +\newcommand{\sailRISCVoverloadAFH}{\saildoclabelled{sailRISCVoverloadAzFzyH}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzf_h8b5b89a166af005200eddfdb4c753f54.tex}}}} + +\newcommand{\sailRISCVoverloadAFS}{\saildoclabelled{sailRISCVoverloadAzFzyS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzf_s921e5f10c465aae8686d3336bac4e432.tex}}}} + +\newcommand{\sailRISCVoverloadAFD}{\saildoclabelled{sailRISCVoverloadAzFzyD}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzf_dce13a0941da7b7642c47c02aaaf22707.tex}}}} \newcommand{\sailRISCVvalrFOrXH}{\saildoclabelled{sailRISCVzrFzyorzyXzyH}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzrf_or_x_hd96ee68afa00d1a1a16a94c3a6ff0e02.tex}}}} @@ -3772,15 +3898,15 @@ \newcommand{\sailRISCVfnwFOrXD}{\saildoclabelled{sailRISCVfnzwFzyorzyXzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwf_or_x_d99d1bec09a43ea1c3cba945cc2ebd80e.tex}}}} -\newcommand{\sailRISCVoverloadPPPFOrXH}{\saildoclabelled{sailRISCVoverloadPPPzFzyorzyXzyH}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadPPPzf_or_x_h3ebc47a16976857a8cd1e19cfb51cb3e.tex}}}} +\newcommand{\sailRISCVoverloadAFOrXH}{\saildoclabelled{sailRISCVoverloadAzFzyorzyXzyH}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzf_or_x_h3ebc47a16976857a8cd1e19cfb51cb3e.tex}}}} -\newcommand{\sailRISCVoverloadQQQFOrXS}{\saildoclabelled{sailRISCVoverloadQQQzFzyorzyXzyS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadQQQzf_or_x_s13ae8815ba72277dad5d10001aed7f61.tex}}}} +\newcommand{\sailRISCVoverloadAFOrXS}{\saildoclabelled{sailRISCVoverloadAzFzyorzyXzyS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzf_or_x_s13ae8815ba72277dad5d10001aed7f61.tex}}}} -\newcommand{\sailRISCVoverloadRRRFOrXD}{\saildoclabelled{sailRISCVoverloadRRRzFzyorzyXzyD}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadRRRzf_or_x_d024412251a76ad9b93d0cea341dd37e8.tex}}}} +\newcommand{\sailRISCVoverloadAFOrXD}{\saildoclabelled{sailRISCVoverloadAzFzyorzyXzyD}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAzf_or_x_d024412251a76ad9b93d0cea341dd37e8.tex}}}} \newcommand{\sailRISCVvalfregNameAbi}{\saildoclabelled{sailRISCVzfregzynamezyabi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfreg_name_abi149ff973f4a58e634d652021d3e44de0.tex}}}} -\newcommand{\sailRISCVoverloadSSStoStr}{\saildoclabelled{sailRISCVoverloadSSSztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadSSSzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} +\newcommand{\sailRISCVoverloadHtoStr}{\saildoclabelled{sailRISCVoverloadHztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} \newcommand{\sailRISCVvalfregName}{\saildoclabelled{sailRISCVzfregzyname}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfreg_name4ac4601cc383d5edd878a00fc0bde952.tex}}}} @@ -4027,7 +4153,7 @@ \newcommand{\sailRISCVvalextCheckPhysMemWrite}{\saildoclabelled{sailRISCVzextzycheckzyphyszymemzywrite}{\saildocval{Validate a write to physical memory. \lstinline{ext_check_phys_mem_write}(write\_kind, paddr, size, data, metadata) should return Some(exception) -to abort the write or None to allow it to proceed. The check is performed +to abort the write or None to allow it to proceed. The check is performed after PMP checks and does not apply to MMIO memory. }{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_check_phys_mem_writeeec4b73c21b79225d7ccf5fb8b67ba61.tex}}}} @@ -4081,6 +4207,13 @@ \newcommand{\sailRISCVtypeextDataAddrError}{\saildoclabelled{sailRISCVtypezextzydatazyaddrzyerror}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezext_data_addr_errora4f74a5b44e1f0d7e46bc0f33c466dea.tex}}}} +\newcommand{\sailRISCVvalddcAndResultingAddr}{\saildoclabelled{sailRISCVzddczyandzyresultingzyaddr}{\saildocval{Returns the current value of DDC (for subsequent access checks) as well as +the resulting address for a non-CHERI integer-based memory access. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/valzddc_and_resulting_addr0f0e2d5c6123a71667b35ed17c44868e.tex}}}} + +\newcommand{\sailRISCVfnddcAndResultingAddr}{\saildoclabelled{sailRISCVfnzddczyandzyresultingzyaddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzddc_and_resulting_addr0f0e2d5c6123a71667b35ed17c44868e.tex}}}} + \newcommand{\sailRISCVvalgetCheriModeCapAddr}{\saildoclabelled{sailRISCVzgetzycherizymodezycapzyaddr}{\saildocval{For given base register and offset returns, depending on current capability mode flag, a bounding capability, effective address, and capreg\_idx (for use in cap cause). @@ -4383,7 +4516,7 @@ \newcommand{\sailRISCVfnptwErrorToStr}{\saildoclabelled{sailRISCVfnzptwzyerrorzytozystr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzptw_error_to_stra1d14633b5815718af0734f3fe6896fb.tex}}}} -\newcommand{\sailRISCVoverloadTTTtoStr}{\saildoclabelled{sailRISCVoverloadTTTztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadTTTzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} +\newcommand{\sailRISCVoverloadItoStr}{\saildoclabelled{sailRISCVoverloadIztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} \newcommand{\sailRISCVvalextGetPtwError}{\saildoclabelled{sailRISCVzextzygetzyptwzyerror}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_get_ptw_errorb38503fe4519ddae4ed13f9933d3c0a5.tex}}}} @@ -5258,7 +5391,7 @@ \subsection*{Exceptions} \item \emph{cs1}.\textbf{perms} does not grant \textbf{Permit\_Execute}. \item \emph{cs1}.\textbf{address} $+$ \emph{imm} $\lt$ \emph{cs1}.\textbf{base}. \item \emph{cs1}.\textbf{address} $+$ \emph{imm} $+$ min\_instruction\_bytes $\gt$ \emph{cs1}.\textbf{top}. -\item \emph{cs1}.\textbf{base} is unaligned. +\item \emph{cs1}.\textbf{base} is unaligned (only possible if PCC relocation is enabled). \item \emph{cs1}.\textbf{address} $+$ \emph{imm} is unaligned, ignoring bit 0. \end{itemize} }{\lstinputlisting[language=sail]{sail_latex_riscv/fclCJALRzexecute33a689e3a631b9b905b85461d3814943.tex}}}} @@ -5583,13 +5716,13 @@ \subsection*{Notes} \newcommand{\sailRISCVfclCRRLexecute}{\saildoclabelled{sailRISCVfclCRRLzexecute}{\saildocfcl{Integer register \emph{rd} is set to the smallest value greater or equal to \emph{rs1} that can be used as a length to set exact bounds on a capability that has a -suitably aligned base (as obtained with the help of \hyperref[sailRISCVzCRAM]{\lstinline{CRepresentableAlignmentMask}}). +suitably aligned base (as obtained with the help of \hyperref[sailRISCVzCRAM]{\lstinline{CRAM}}). }{\lstinputlisting[language=sail]{sail_latex_riscv/fclCRRLzexecute33a689e3a631b9b905b85461d3814943.tex}}}} \newcommand{\sailRISCVfclCRAMexecute}{\saildoclabelled{sailRISCVfclCRAMzexecute}{\saildocfcl{Integer register \emph{rd} is set to a mask that can be used to round addresses down to to a value that is sufficiently aligned to set exact bounds for the -nearest representable length of \emph{rs1} (as obtained by \hyperref[sailRISCVzCRRL]{\lstinline{CRoundRepresentableLength}}). +nearest representable length of \emph{rs1} (as obtained by \hyperref[sailRISCVzCRRL]{\lstinline{CRRL}}). }{\lstinputlisting[language=sail]{sail_latex_riscv/fclCRAMzexecute33a689e3a631b9b905b85461d3814943.tex}}}} @@ -5706,7 +5839,7 @@ \subsection*{Exceptions} \item \emph{cs2}.\textbf{perms} grants \textbf{Permit\_Execute}. \item \emph{cs1}.\textbf{address} $\lt$ \emph{cs1}.\textbf{base}. \item \emph{cs1}.\textbf{address} $+$ min\_instruction\_bytes $\gt$ \emph{cs1}.\textbf{top}. -\item \emph{cs1}.\textbf{base} is unaligned. +\item \emph{cs1}.\textbf{base} is unaligned (only possible if PCC relocation is enabled). \item \emph{cs1}.\textbf{address} is unaligned, ignoring bit 0. \end{itemize} @@ -5741,7 +5874,7 @@ \subsection*{Exceptions} \item \emph{cs1}.\textbf{perms} does not grant \textbf{Permit\_Execute}. \item \emph{cs1}.\textbf{address} $\lt$ \emph{cs1}.\textbf{base}. \item \emph{cs1}.\textbf{address} $+$ min\_instruction\_bytes $\gt$ \emph{cs1}.\textbf{top}. -\item \emph{cs1}.\textbf{base} is unaligned. +\item \emph{cs1}.\textbf{base} is unaligned (only possible if PCC relocation is enabled). \item \emph{cs1}.\textbf{address} is unaligned, ignoring bit 0. \end{itemize} }{\lstinputlisting[language=sail]{sail_latex_riscv/fclJALRUnderscoreCAPzexecute33a689e3a631b9b905b85461d3814943.tex}}}} @@ -6192,7 +6325,7 @@ \subsection*{Notes} \newcommand{\sailRISCVfnprintInsn}{\saildoclabelled{sailRISCVfnzprintzyinsn}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzprint_insn34adb9871c343ddeeb08d9e768ad4c92.tex}}}} -\newcommand{\sailRISCVoverloadUUUtoStr}{\saildoclabelled{sailRISCVoverloadUUUztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadUUUzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} +\newcommand{\sailRISCVoverloadJtoStr}{\saildoclabelled{sailRISCVoverloadJztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} \newcommand{\sailRISCVtypeFetchResult}{\saildoclabelled{sailRISCVtypezFetchResult}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezfetchresult170a566bc6b6cd6bbb373e14725091ab.tex}}}} @@ -6465,6 +6598,8 @@ \subsection*{Notes} \ifstrequal{#1}{cap\_reg\_name}{\sailRISCVvalcapRegName}{}% \ifstrequal{#1}{cap_reg_name_abi}{\sailRISCVvalcapRegNameAbi}{}% \ifstrequal{#1}{cap\_reg\_name\_abi}{\sailRISCVvalcapRegNameAbi}{}% + \ifstrequal{#1}{cap_to_integer_pc}{\sailRISCVvalcapToIntegerPc}{}% + \ifstrequal{#1}{cap\_to\_integer\_pc}{\sailRISCVvalcapToIntegerPc}{}% \ifstrequal{#1}{checkPTEPermission}{\sailRISCVvalcheckPTEPermission}{}% \ifstrequal{#1}{check_CSR}{\sailRISCVvalcheckCSR}{}% \ifstrequal{#1}{check\_CSR}{\sailRISCVvalcheckCSR}{}% @@ -6521,6 +6656,8 @@ \subsection*{Notes} \ifstrequal{#1}{curPTB64}{\sailRISCVvalcurPTBSixFour}{}% \ifstrequal{#1}{cur_Architecture}{\sailRISCVvalcurArchitecture}{}% \ifstrequal{#1}{cur\_Architecture}{\sailRISCVvalcurArchitecture}{}% + \ifstrequal{#1}{ddc_and_resulting_addr}{\sailRISCVvalddcAndResultingAddr}{}% + \ifstrequal{#1}{ddc\_and\_resulting\_addr}{\sailRISCVvalddcAndResultingAddr}{}% \ifstrequal{#1}{dec_str}{\sailRISCVvaldecStr}{}% \ifstrequal{#1}{dec\_str}{\sailRISCVvaldecStr}{}% \ifstrequal{#1}{decimal_string_of_bits}{\sailRISCVvaldecimalStringOfBits}{}% @@ -6684,8 +6821,12 @@ \subsection*{Notes} \ifstrequal{#1}{extern\_f16Eq}{\sailRISCVvalexternFOneSixEq}{}% \ifstrequal{#1}{extern_f16Le}{\sailRISCVvalexternFOneSixLe}{}% \ifstrequal{#1}{extern\_f16Le}{\sailRISCVvalexternFOneSixLe}{}% + \ifstrequal{#1}{extern_f16Le_quiet}{\sailRISCVvalexternFOneSixLeQuiet}{}% + \ifstrequal{#1}{extern\_f16Le\_quiet}{\sailRISCVvalexternFOneSixLeQuiet}{}% \ifstrequal{#1}{extern_f16Lt}{\sailRISCVvalexternFOneSixLt}{}% \ifstrequal{#1}{extern\_f16Lt}{\sailRISCVvalexternFOneSixLt}{}% + \ifstrequal{#1}{extern_f16Lt_quiet}{\sailRISCVvalexternFOneSixLtQuiet}{}% + \ifstrequal{#1}{extern\_f16Lt\_quiet}{\sailRISCVvalexternFOneSixLtQuiet}{}% \ifstrequal{#1}{extern_f16Mul}{\sailRISCVvalexternFOneSixMul}{}% \ifstrequal{#1}{extern\_f16Mul}{\sailRISCVvalexternFOneSixMul}{}% \ifstrequal{#1}{extern_f16MulAdd}{\sailRISCVvalexternFOneSixMulAdd}{}% @@ -6706,6 +6847,8 @@ \subsection*{Notes} \ifstrequal{#1}{extern\_f16ToUi32}{\sailRISCVvalexternFOneSixToUiThreeTwo}{}% \ifstrequal{#1}{extern_f16ToUi64}{\sailRISCVvalexternFOneSixToUiSixFour}{}% \ifstrequal{#1}{extern\_f16ToUi64}{\sailRISCVvalexternFOneSixToUiSixFour}{}% + \ifstrequal{#1}{extern_f16roundToInt}{\sailRISCVvalexternFOneSixroundToInt}{}% + \ifstrequal{#1}{extern\_f16roundToInt}{\sailRISCVvalexternFOneSixroundToInt}{}% \ifstrequal{#1}{extern_f32Add}{\sailRISCVvalexternFThreeTwoAdd}{}% \ifstrequal{#1}{extern\_f32Add}{\sailRISCVvalexternFThreeTwoAdd}{}% \ifstrequal{#1}{extern_f32Div}{\sailRISCVvalexternFThreeTwoDiv}{}% @@ -6714,8 +6857,12 @@ \subsection*{Notes} \ifstrequal{#1}{extern\_f32Eq}{\sailRISCVvalexternFThreeTwoEq}{}% \ifstrequal{#1}{extern_f32Le}{\sailRISCVvalexternFThreeTwoLe}{}% \ifstrequal{#1}{extern\_f32Le}{\sailRISCVvalexternFThreeTwoLe}{}% + \ifstrequal{#1}{extern_f32Le_quiet}{\sailRISCVvalexternFThreeTwoLeQuiet}{}% + \ifstrequal{#1}{extern\_f32Le\_quiet}{\sailRISCVvalexternFThreeTwoLeQuiet}{}% \ifstrequal{#1}{extern_f32Lt}{\sailRISCVvalexternFThreeTwoLt}{}% \ifstrequal{#1}{extern\_f32Lt}{\sailRISCVvalexternFThreeTwoLt}{}% + \ifstrequal{#1}{extern_f32Lt_quiet}{\sailRISCVvalexternFThreeTwoLtQuiet}{}% + \ifstrequal{#1}{extern\_f32Lt\_quiet}{\sailRISCVvalexternFThreeTwoLtQuiet}{}% \ifstrequal{#1}{extern_f32Mul}{\sailRISCVvalexternFThreeTwoMul}{}% \ifstrequal{#1}{extern\_f32Mul}{\sailRISCVvalexternFThreeTwoMul}{}% \ifstrequal{#1}{extern_f32MulAdd}{\sailRISCVvalexternFThreeTwoMulAdd}{}% @@ -6736,6 +6883,8 @@ \subsection*{Notes} \ifstrequal{#1}{extern\_f32ToUi32}{\sailRISCVvalexternFThreeTwoToUiThreeTwo}{}% \ifstrequal{#1}{extern_f32ToUi64}{\sailRISCVvalexternFThreeTwoToUiSixFour}{}% \ifstrequal{#1}{extern\_f32ToUi64}{\sailRISCVvalexternFThreeTwoToUiSixFour}{}% + \ifstrequal{#1}{extern_f32roundToInt}{\sailRISCVvalexternFThreeTworoundToInt}{}% + \ifstrequal{#1}{extern\_f32roundToInt}{\sailRISCVvalexternFThreeTworoundToInt}{}% \ifstrequal{#1}{extern_f64Add}{\sailRISCVvalexternFSixFourAdd}{}% \ifstrequal{#1}{extern\_f64Add}{\sailRISCVvalexternFSixFourAdd}{}% \ifstrequal{#1}{extern_f64Div}{\sailRISCVvalexternFSixFourDiv}{}% @@ -6744,8 +6893,12 @@ \subsection*{Notes} \ifstrequal{#1}{extern\_f64Eq}{\sailRISCVvalexternFSixFourEq}{}% \ifstrequal{#1}{extern_f64Le}{\sailRISCVvalexternFSixFourLe}{}% \ifstrequal{#1}{extern\_f64Le}{\sailRISCVvalexternFSixFourLe}{}% + \ifstrequal{#1}{extern_f64Le_quiet}{\sailRISCVvalexternFSixFourLeQuiet}{}% + \ifstrequal{#1}{extern\_f64Le\_quiet}{\sailRISCVvalexternFSixFourLeQuiet}{}% \ifstrequal{#1}{extern_f64Lt}{\sailRISCVvalexternFSixFourLt}{}% \ifstrequal{#1}{extern\_f64Lt}{\sailRISCVvalexternFSixFourLt}{}% + \ifstrequal{#1}{extern_f64Lt_quiet}{\sailRISCVvalexternFSixFourLtQuiet}{}% + \ifstrequal{#1}{extern\_f64Lt\_quiet}{\sailRISCVvalexternFSixFourLtQuiet}{}% \ifstrequal{#1}{extern_f64Mul}{\sailRISCVvalexternFSixFourMul}{}% \ifstrequal{#1}{extern\_f64Mul}{\sailRISCVvalexternFSixFourMul}{}% \ifstrequal{#1}{extern_f64MulAdd}{\sailRISCVvalexternFSixFourMulAdd}{}% @@ -6766,6 +6919,8 @@ \subsection*{Notes} \ifstrequal{#1}{extern\_f64ToUi32}{\sailRISCVvalexternFSixFourToUiThreeTwo}{}% \ifstrequal{#1}{extern_f64ToUi64}{\sailRISCVvalexternFSixFourToUiSixFour}{}% \ifstrequal{#1}{extern\_f64ToUi64}{\sailRISCVvalexternFSixFourToUiSixFour}{}% + \ifstrequal{#1}{extern_f64roundToInt}{\sailRISCVvalexternFSixFourroundToInt}{}% + \ifstrequal{#1}{extern\_f64roundToInt}{\sailRISCVvalexternFSixFourroundToInt}{}% \ifstrequal{#1}{extern_i32ToF16}{\sailRISCVvalexternIThreeTwoToFOneSix}{}% \ifstrequal{#1}{extern\_i32ToF16}{\sailRISCVvalexternIThreeTwoToFOneSix}{}% \ifstrequal{#1}{extern_i32ToF32}{\sailRISCVvalexternIThreeTwoToFThreeTwo}{}% @@ -7039,9 +7194,11 @@ \subsection*{Notes} \ifstrequal{#1}{haveZbkx}{\sailRISCVvalhaveZbkx}{}% \ifstrequal{#1}{haveZbs}{\sailRISCVvalhaveZbs}{}% \ifstrequal{#1}{haveZdinx}{\sailRISCVvalhaveZdinx}{}% + \ifstrequal{#1}{haveZfa}{\sailRISCVvalhaveZfa}{}% \ifstrequal{#1}{haveZfh}{\sailRISCVvalhaveZfh}{}% \ifstrequal{#1}{haveZfinx}{\sailRISCVvalhaveZfinx}{}% \ifstrequal{#1}{haveZhinx}{\sailRISCVvalhaveZhinx}{}% + \ifstrequal{#1}{haveZicond}{\sailRISCVvalhaveZicond}{}% \ifstrequal{#1}{haveZknd}{\sailRISCVvalhaveZknd}{}% \ifstrequal{#1}{haveZkne}{\sailRISCVvalhaveZkne}{}% \ifstrequal{#1}{haveZknh}{\sailRISCVvalhaveZknh}{}% @@ -7049,6 +7206,12 @@ \subsection*{Notes} \ifstrequal{#1}{haveZksed}{\sailRISCVvalhaveZksed}{}% \ifstrequal{#1}{haveZksh}{\sailRISCVvalhaveZksh}{}% \ifstrequal{#1}{haveZmmul}{\sailRISCVvalhaveZmmul}{}% + \ifstrequal{#1}{have_cheri_relocation}{\sailRISCVvalhaveCheriRelocation}{}% + \ifstrequal{#1}{have\_cheri\_relocation}{\sailRISCVvalhaveCheriRelocation}{}% + \ifstrequal{#1}{have_ddc_relocation}{\sailRISCVvalhaveDdcRelocation}{}% + \ifstrequal{#1}{have\_ddc\_relocation}{\sailRISCVvalhaveDdcRelocation}{}% + \ifstrequal{#1}{have_pcc_relocation}{\sailRISCVvalhavePccRelocation}{}% + \ifstrequal{#1}{have\_pcc\_relocation}{\sailRISCVvalhavePccRelocation}{}% \ifstrequal{#1}{hex_bits}{\sailRISCVvalhexBits}{}% \ifstrequal{#1}{hex\_bits}{\sailRISCVvalhexBits}{}% \ifstrequal{#1}{hex_bits_1}{\sailRISCVvalhexBitsOne}{}% @@ -7827,6 +7990,8 @@ \subsection*{Notes} \ifstrequal{#1}{num\_of\_word\_width}{\sailRISCVvalnumOfWordWidth}{}% \ifstrequal{#1}{num_of_write_kind}{\sailRISCVvalnumOfWriteKind}{}% \ifstrequal{#1}{num\_of\_write\_kind}{\sailRISCVvalnumOfWriteKind}{}% + \ifstrequal{#1}{num_of_zicondop}{\sailRISCVvalnumOfZicondop}{}% + \ifstrequal{#1}{num\_of\_zicondop}{\sailRISCVvalnumOfZicondop}{}% \ifstrequal{#1}{nvFlag}{\sailRISCVvalnvFlag}{}% \ifstrequal{#1}{nxFlag}{\sailRISCVvalnxFlag}{}% \ifstrequal{#1}{ofFlag}{\sailRISCVvalofFlag}{}% @@ -7970,6 +8135,12 @@ \subsection*{Notes} \ifstrequal{#1}{rC_bits}{\sailRISCVvalrCBits}{}% \ifstrequal{#1}{rC\_bits}{\sailRISCVvalrCBits}{}% \ifstrequal{#1}{rF}{\sailRISCVvalrF}{}% + \ifstrequal{#1}{rF_D}{\sailRISCVvalrFD}{}% + \ifstrequal{#1}{rF\_D}{\sailRISCVvalrFD}{}% + \ifstrequal{#1}{rF_H}{\sailRISCVvalrFH}{}% + \ifstrequal{#1}{rF\_H}{\sailRISCVvalrFH}{}% + \ifstrequal{#1}{rF_S}{\sailRISCVvalrFS}{}% + \ifstrequal{#1}{rF\_S}{\sailRISCVvalrFS}{}% \ifstrequal{#1}{rF_bits}{\sailRISCVvalrFBits}{}% \ifstrequal{#1}{rF\_bits}{\sailRISCVvalrFBits}{}% \ifstrequal{#1}{rF_or_X_D}{\sailRISCVvalrFOrXD}{}% @@ -8022,8 +8193,12 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f16Eq}{\sailRISCVvalriscvFOneSixEq}{}% \ifstrequal{#1}{riscv_f16Le}{\sailRISCVvalriscvFOneSixLe}{}% \ifstrequal{#1}{riscv\_f16Le}{\sailRISCVvalriscvFOneSixLe}{}% + \ifstrequal{#1}{riscv_f16Le_quiet}{\sailRISCVvalriscvFOneSixLeQuiet}{}% + \ifstrequal{#1}{riscv\_f16Le\_quiet}{\sailRISCVvalriscvFOneSixLeQuiet}{}% \ifstrequal{#1}{riscv_f16Lt}{\sailRISCVvalriscvFOneSixLt}{}% \ifstrequal{#1}{riscv\_f16Lt}{\sailRISCVvalriscvFOneSixLt}{}% + \ifstrequal{#1}{riscv_f16Lt_quiet}{\sailRISCVvalriscvFOneSixLtQuiet}{}% + \ifstrequal{#1}{riscv\_f16Lt\_quiet}{\sailRISCVvalriscvFOneSixLtQuiet}{}% \ifstrequal{#1}{riscv_f16Mul}{\sailRISCVvalriscvFOneSixMul}{}% \ifstrequal{#1}{riscv\_f16Mul}{\sailRISCVvalriscvFOneSixMul}{}% \ifstrequal{#1}{riscv_f16MulAdd}{\sailRISCVvalriscvFOneSixMulAdd}{}% @@ -8044,6 +8219,8 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f16ToUi32}{\sailRISCVvalriscvFOneSixToUiThreeTwo}{}% \ifstrequal{#1}{riscv_f16ToUi64}{\sailRISCVvalriscvFOneSixToUiSixFour}{}% \ifstrequal{#1}{riscv\_f16ToUi64}{\sailRISCVvalriscvFOneSixToUiSixFour}{}% + \ifstrequal{#1}{riscv_f16roundToInt}{\sailRISCVvalriscvFOneSixroundToInt}{}% + \ifstrequal{#1}{riscv\_f16roundToInt}{\sailRISCVvalriscvFOneSixroundToInt}{}% \ifstrequal{#1}{riscv_f32Add}{\sailRISCVvalriscvFThreeTwoAdd}{}% \ifstrequal{#1}{riscv\_f32Add}{\sailRISCVvalriscvFThreeTwoAdd}{}% \ifstrequal{#1}{riscv_f32Div}{\sailRISCVvalriscvFThreeTwoDiv}{}% @@ -8052,8 +8229,12 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f32Eq}{\sailRISCVvalriscvFThreeTwoEq}{}% \ifstrequal{#1}{riscv_f32Le}{\sailRISCVvalriscvFThreeTwoLe}{}% \ifstrequal{#1}{riscv\_f32Le}{\sailRISCVvalriscvFThreeTwoLe}{}% + \ifstrequal{#1}{riscv_f32Le_quiet}{\sailRISCVvalriscvFThreeTwoLeQuiet}{}% + \ifstrequal{#1}{riscv\_f32Le\_quiet}{\sailRISCVvalriscvFThreeTwoLeQuiet}{}% \ifstrequal{#1}{riscv_f32Lt}{\sailRISCVvalriscvFThreeTwoLt}{}% \ifstrequal{#1}{riscv\_f32Lt}{\sailRISCVvalriscvFThreeTwoLt}{}% + \ifstrequal{#1}{riscv_f32Lt_quiet}{\sailRISCVvalriscvFThreeTwoLtQuiet}{}% + \ifstrequal{#1}{riscv\_f32Lt\_quiet}{\sailRISCVvalriscvFThreeTwoLtQuiet}{}% \ifstrequal{#1}{riscv_f32Mul}{\sailRISCVvalriscvFThreeTwoMul}{}% \ifstrequal{#1}{riscv\_f32Mul}{\sailRISCVvalriscvFThreeTwoMul}{}% \ifstrequal{#1}{riscv_f32MulAdd}{\sailRISCVvalriscvFThreeTwoMulAdd}{}% @@ -8074,6 +8255,8 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f32ToUi32}{\sailRISCVvalriscvFThreeTwoToUiThreeTwo}{}% \ifstrequal{#1}{riscv_f32ToUi64}{\sailRISCVvalriscvFThreeTwoToUiSixFour}{}% \ifstrequal{#1}{riscv\_f32ToUi64}{\sailRISCVvalriscvFThreeTwoToUiSixFour}{}% + \ifstrequal{#1}{riscv_f32roundToInt}{\sailRISCVvalriscvFThreeTworoundToInt}{}% + \ifstrequal{#1}{riscv\_f32roundToInt}{\sailRISCVvalriscvFThreeTworoundToInt}{}% \ifstrequal{#1}{riscv_f64Add}{\sailRISCVvalriscvFSixFourAdd}{}% \ifstrequal{#1}{riscv\_f64Add}{\sailRISCVvalriscvFSixFourAdd}{}% \ifstrequal{#1}{riscv_f64Div}{\sailRISCVvalriscvFSixFourDiv}{}% @@ -8082,8 +8265,12 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f64Eq}{\sailRISCVvalriscvFSixFourEq}{}% \ifstrequal{#1}{riscv_f64Le}{\sailRISCVvalriscvFSixFourLe}{}% \ifstrequal{#1}{riscv\_f64Le}{\sailRISCVvalriscvFSixFourLe}{}% + \ifstrequal{#1}{riscv_f64Le_quiet}{\sailRISCVvalriscvFSixFourLeQuiet}{}% + \ifstrequal{#1}{riscv\_f64Le\_quiet}{\sailRISCVvalriscvFSixFourLeQuiet}{}% \ifstrequal{#1}{riscv_f64Lt}{\sailRISCVvalriscvFSixFourLt}{}% \ifstrequal{#1}{riscv\_f64Lt}{\sailRISCVvalriscvFSixFourLt}{}% + \ifstrequal{#1}{riscv_f64Lt_quiet}{\sailRISCVvalriscvFSixFourLtQuiet}{}% + \ifstrequal{#1}{riscv\_f64Lt\_quiet}{\sailRISCVvalriscvFSixFourLtQuiet}{}% \ifstrequal{#1}{riscv_f64Mul}{\sailRISCVvalriscvFSixFourMul}{}% \ifstrequal{#1}{riscv\_f64Mul}{\sailRISCVvalriscvFSixFourMul}{}% \ifstrequal{#1}{riscv_f64MulAdd}{\sailRISCVvalriscvFSixFourMulAdd}{}% @@ -8104,6 +8291,8 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f64ToUi32}{\sailRISCVvalriscvFSixFourToUiThreeTwo}{}% \ifstrequal{#1}{riscv_f64ToUi64}{\sailRISCVvalriscvFSixFourToUiSixFour}{}% \ifstrequal{#1}{riscv\_f64ToUi64}{\sailRISCVvalriscvFSixFourToUiSixFour}{}% + \ifstrequal{#1}{riscv_f64roundToInt}{\sailRISCVvalriscvFSixFourroundToInt}{}% + \ifstrequal{#1}{riscv\_f64roundToInt}{\sailRISCVvalriscvFSixFourroundToInt}{}% \ifstrequal{#1}{riscv_i32ToF16}{\sailRISCVvalriscvIThreeTwoToFOneSix}{}% \ifstrequal{#1}{riscv\_i32ToF16}{\sailRISCVvalriscvIThreeTwoToFOneSix}{}% \ifstrequal{#1}{riscv_i32ToF32}{\sailRISCVvalriscvIThreeTwoToFThreeTwo}{}% @@ -8181,6 +8370,7 @@ \subsection*{Notes} \ifstrequal{#1}{select\_instr\_or\_fcsr\_rm}{\sailRISCVvalselectInstrOrFcsrRm}{}% \ifstrequal{#1}{sep}{\sailRISCVvalsep}{}% \ifstrequal{#1}{setCapAddr}{\sailRISCVvalsetCapAddr}{}% + \ifstrequal{#1}{setCapAddrChecked}{\sailRISCVvalsetCapAddrChecked}{}% \ifstrequal{#1}{setCapBounds}{\sailRISCVvalsetCapBounds}{}% \ifstrequal{#1}{setCapFlags}{\sailRISCVvalsetCapFlags}{}% \ifstrequal{#1}{setCapOffset}{\sailRISCVvalsetCapOffset}{}% @@ -8323,6 +8513,8 @@ \subsection*{Notes} \ifstrequal{#1}{uop\_of\_num}{\sailRISCVvaluopOfNum}{}% \ifstrequal{#1}{update_PTE_Bits}{\sailRISCVvalupdatePTEBits}{}% \ifstrequal{#1}{update\_PTE\_Bits}{\sailRISCVvalupdatePTEBits}{}% + \ifstrequal{#1}{update_cap_with_integer_pc}{\sailRISCVvalupdateCapWithIntegerPc}{}% + \ifstrequal{#1}{update\_cap\_with\_integer\_pc}{\sailRISCVvalupdateCapWithIntegerPc}{}% \ifstrequal{#1}{update_softfloat_fflags}{\sailRISCVvalupdateSoftfloatFflags}{}% \ifstrequal{#1}{update\_softfloat\_fflags}{\sailRISCVvalupdateSoftfloatFflags}{}% \ifstrequal{#1}{update_subrange}{\sailRISCVvalupdateSubrange}{}% @@ -8342,6 +8534,12 @@ \subsection*{Notes} \ifstrequal{#1}{wC_bits}{\sailRISCVvalwCBits}{}% \ifstrequal{#1}{wC\_bits}{\sailRISCVvalwCBits}{}% \ifstrequal{#1}{wF}{\sailRISCVvalwF}{}% + \ifstrequal{#1}{wF_D}{\sailRISCVvalwFD}{}% + \ifstrequal{#1}{wF\_D}{\sailRISCVvalwFD}{}% + \ifstrequal{#1}{wF_H}{\sailRISCVvalwFH}{}% + \ifstrequal{#1}{wF\_H}{\sailRISCVvalwFH}{}% + \ifstrequal{#1}{wF_S}{\sailRISCVvalwFS}{}% + \ifstrequal{#1}{wF\_S}{\sailRISCVvalwFS}{}% \ifstrequal{#1}{wF_bits}{\sailRISCVvalwFBits}{}% \ifstrequal{#1}{wF\_bits}{\sailRISCVvalwFBits}{}% \ifstrequal{#1}{wF_or_X_D}{\sailRISCVvalwFOrXD}{}% @@ -8392,6 +8590,8 @@ \subsection*{Notes} \ifstrequal{#1}{xor\_vec}{\sailRISCVvalxorVec}{}% \ifstrequal{#1}{zeros_implicit}{\sailRISCVvalzzerosImplicit}{}% \ifstrequal{#1}{zeros\_implicit}{\sailRISCVvalzzerosImplicit}{}% + \ifstrequal{#1}{zicondop_of_num}{\sailRISCVvalzzicondopOfNum}{}% + \ifstrequal{#1}{zicondop\_of\_num}{\sailRISCVvalzzicondopOfNum}{}% \ifstrequal{#1}{(operator <=_u)}{\sailRISCVvalzEightoperatorzZerozIzJUzNine}{}% \ifstrequal{#1}{(operator $>$=\_u)}{\sailRISCVvalzEightoperatorzZerozIzJUzNine}{}% \ifstrequal{#1}{(operator <_s)}{\sailRISCVvalzEightoperatorzZerozISzNine}{}% @@ -8614,6 +8814,8 @@ \subsection*{Notes} \ifstrequal{#1}{cap\_reg\_name}{\hyperref[sailRISCVzcapzyregzyname]{#2}}{}% \ifstrequal{#1}{cap_reg_name_abi}{\hyperref[sailRISCVzcapzyregzynamezyabi]{#2}}{}% \ifstrequal{#1}{cap\_reg\_name\_abi}{\hyperref[sailRISCVzcapzyregzynamezyabi]{#2}}{}% + \ifstrequal{#1}{cap_to_integer_pc}{\hyperref[sailRISCVzcapzytozyintegerzypc]{#2}}{}% + \ifstrequal{#1}{cap\_to\_integer\_pc}{\hyperref[sailRISCVzcapzytozyintegerzypc]{#2}}{}% \ifstrequal{#1}{checkPTEPermission}{\hyperref[sailRISCVzcheckPTEPermission]{#2}}{}% \ifstrequal{#1}{check_CSR}{\hyperref[sailRISCVzcheckzyCSR]{#2}}{}% \ifstrequal{#1}{check\_CSR}{\hyperref[sailRISCVzcheckzyCSR]{#2}}{}% @@ -8670,6 +8872,8 @@ \subsection*{Notes} \ifstrequal{#1}{curPTB64}{\hyperref[sailRISCVzcurPTB64]{#2}}{}% \ifstrequal{#1}{cur_Architecture}{\hyperref[sailRISCVzcurzyArchitecture]{#2}}{}% \ifstrequal{#1}{cur\_Architecture}{\hyperref[sailRISCVzcurzyArchitecture]{#2}}{}% + \ifstrequal{#1}{ddc_and_resulting_addr}{\hyperref[sailRISCVzddczyandzyresultingzyaddr]{#2}}{}% + \ifstrequal{#1}{ddc\_and\_resulting\_addr}{\hyperref[sailRISCVzddczyandzyresultingzyaddr]{#2}}{}% \ifstrequal{#1}{dec_str}{\hyperref[sailRISCVzdeczystr]{#2}}{}% \ifstrequal{#1}{dec\_str}{\hyperref[sailRISCVzdeczystr]{#2}}{}% \ifstrequal{#1}{decimal_string_of_bits}{\hyperref[sailRISCVzdecimalzystringzyofzybits]{#2}}{}% @@ -8833,8 +9037,12 @@ \subsection*{Notes} \ifstrequal{#1}{extern\_f16Eq}{\hyperref[sailRISCVzexternzyf16Eq]{#2}}{}% \ifstrequal{#1}{extern_f16Le}{\hyperref[sailRISCVzexternzyf16Le]{#2}}{}% \ifstrequal{#1}{extern\_f16Le}{\hyperref[sailRISCVzexternzyf16Le]{#2}}{}% + \ifstrequal{#1}{extern_f16Le_quiet}{\hyperref[sailRISCVzexternzyf16Lezyquiet]{#2}}{}% + \ifstrequal{#1}{extern\_f16Le\_quiet}{\hyperref[sailRISCVzexternzyf16Lezyquiet]{#2}}{}% \ifstrequal{#1}{extern_f16Lt}{\hyperref[sailRISCVzexternzyf16Lt]{#2}}{}% \ifstrequal{#1}{extern\_f16Lt}{\hyperref[sailRISCVzexternzyf16Lt]{#2}}{}% + \ifstrequal{#1}{extern_f16Lt_quiet}{\hyperref[sailRISCVzexternzyf16Ltzyquiet]{#2}}{}% + \ifstrequal{#1}{extern\_f16Lt\_quiet}{\hyperref[sailRISCVzexternzyf16Ltzyquiet]{#2}}{}% \ifstrequal{#1}{extern_f16Mul}{\hyperref[sailRISCVzexternzyf16Mul]{#2}}{}% \ifstrequal{#1}{extern\_f16Mul}{\hyperref[sailRISCVzexternzyf16Mul]{#2}}{}% \ifstrequal{#1}{extern_f16MulAdd}{\hyperref[sailRISCVzexternzyf16MulAdd]{#2}}{}% @@ -8855,6 +9063,8 @@ \subsection*{Notes} \ifstrequal{#1}{extern\_f16ToUi32}{\hyperref[sailRISCVzexternzyf16ToUi32]{#2}}{}% \ifstrequal{#1}{extern_f16ToUi64}{\hyperref[sailRISCVzexternzyf16ToUi64]{#2}}{}% \ifstrequal{#1}{extern\_f16ToUi64}{\hyperref[sailRISCVzexternzyf16ToUi64]{#2}}{}% + \ifstrequal{#1}{extern_f16roundToInt}{\hyperref[sailRISCVzexternzyf16roundToInt]{#2}}{}% + \ifstrequal{#1}{extern\_f16roundToInt}{\hyperref[sailRISCVzexternzyf16roundToInt]{#2}}{}% \ifstrequal{#1}{extern_f32Add}{\hyperref[sailRISCVzexternzyf32Add]{#2}}{}% \ifstrequal{#1}{extern\_f32Add}{\hyperref[sailRISCVzexternzyf32Add]{#2}}{}% \ifstrequal{#1}{extern_f32Div}{\hyperref[sailRISCVzexternzyf32Div]{#2}}{}% @@ -8863,8 +9073,12 @@ \subsection*{Notes} \ifstrequal{#1}{extern\_f32Eq}{\hyperref[sailRISCVzexternzyf32Eq]{#2}}{}% \ifstrequal{#1}{extern_f32Le}{\hyperref[sailRISCVzexternzyf32Le]{#2}}{}% \ifstrequal{#1}{extern\_f32Le}{\hyperref[sailRISCVzexternzyf32Le]{#2}}{}% + \ifstrequal{#1}{extern_f32Le_quiet}{\hyperref[sailRISCVzexternzyf32Lezyquiet]{#2}}{}% + \ifstrequal{#1}{extern\_f32Le\_quiet}{\hyperref[sailRISCVzexternzyf32Lezyquiet]{#2}}{}% \ifstrequal{#1}{extern_f32Lt}{\hyperref[sailRISCVzexternzyf32Lt]{#2}}{}% \ifstrequal{#1}{extern\_f32Lt}{\hyperref[sailRISCVzexternzyf32Lt]{#2}}{}% + \ifstrequal{#1}{extern_f32Lt_quiet}{\hyperref[sailRISCVzexternzyf32Ltzyquiet]{#2}}{}% + \ifstrequal{#1}{extern\_f32Lt\_quiet}{\hyperref[sailRISCVzexternzyf32Ltzyquiet]{#2}}{}% \ifstrequal{#1}{extern_f32Mul}{\hyperref[sailRISCVzexternzyf32Mul]{#2}}{}% \ifstrequal{#1}{extern\_f32Mul}{\hyperref[sailRISCVzexternzyf32Mul]{#2}}{}% \ifstrequal{#1}{extern_f32MulAdd}{\hyperref[sailRISCVzexternzyf32MulAdd]{#2}}{}% @@ -8885,6 +9099,8 @@ \subsection*{Notes} \ifstrequal{#1}{extern\_f32ToUi32}{\hyperref[sailRISCVzexternzyf32ToUi32]{#2}}{}% \ifstrequal{#1}{extern_f32ToUi64}{\hyperref[sailRISCVzexternzyf32ToUi64]{#2}}{}% \ifstrequal{#1}{extern\_f32ToUi64}{\hyperref[sailRISCVzexternzyf32ToUi64]{#2}}{}% + \ifstrequal{#1}{extern_f32roundToInt}{\hyperref[sailRISCVzexternzyf32roundToInt]{#2}}{}% + \ifstrequal{#1}{extern\_f32roundToInt}{\hyperref[sailRISCVzexternzyf32roundToInt]{#2}}{}% \ifstrequal{#1}{extern_f64Add}{\hyperref[sailRISCVzexternzyf64Add]{#2}}{}% \ifstrequal{#1}{extern\_f64Add}{\hyperref[sailRISCVzexternzyf64Add]{#2}}{}% \ifstrequal{#1}{extern_f64Div}{\hyperref[sailRISCVzexternzyf64Div]{#2}}{}% @@ -8893,8 +9109,12 @@ \subsection*{Notes} \ifstrequal{#1}{extern\_f64Eq}{\hyperref[sailRISCVzexternzyf64Eq]{#2}}{}% \ifstrequal{#1}{extern_f64Le}{\hyperref[sailRISCVzexternzyf64Le]{#2}}{}% \ifstrequal{#1}{extern\_f64Le}{\hyperref[sailRISCVzexternzyf64Le]{#2}}{}% + \ifstrequal{#1}{extern_f64Le_quiet}{\hyperref[sailRISCVzexternzyf64Lezyquiet]{#2}}{}% + \ifstrequal{#1}{extern\_f64Le\_quiet}{\hyperref[sailRISCVzexternzyf64Lezyquiet]{#2}}{}% \ifstrequal{#1}{extern_f64Lt}{\hyperref[sailRISCVzexternzyf64Lt]{#2}}{}% \ifstrequal{#1}{extern\_f64Lt}{\hyperref[sailRISCVzexternzyf64Lt]{#2}}{}% + \ifstrequal{#1}{extern_f64Lt_quiet}{\hyperref[sailRISCVzexternzyf64Ltzyquiet]{#2}}{}% + \ifstrequal{#1}{extern\_f64Lt\_quiet}{\hyperref[sailRISCVzexternzyf64Ltzyquiet]{#2}}{}% \ifstrequal{#1}{extern_f64Mul}{\hyperref[sailRISCVzexternzyf64Mul]{#2}}{}% \ifstrequal{#1}{extern\_f64Mul}{\hyperref[sailRISCVzexternzyf64Mul]{#2}}{}% \ifstrequal{#1}{extern_f64MulAdd}{\hyperref[sailRISCVzexternzyf64MulAdd]{#2}}{}% @@ -8915,6 +9135,8 @@ \subsection*{Notes} \ifstrequal{#1}{extern\_f64ToUi32}{\hyperref[sailRISCVzexternzyf64ToUi32]{#2}}{}% \ifstrequal{#1}{extern_f64ToUi64}{\hyperref[sailRISCVzexternzyf64ToUi64]{#2}}{}% \ifstrequal{#1}{extern\_f64ToUi64}{\hyperref[sailRISCVzexternzyf64ToUi64]{#2}}{}% + \ifstrequal{#1}{extern_f64roundToInt}{\hyperref[sailRISCVzexternzyf64roundToInt]{#2}}{}% + \ifstrequal{#1}{extern\_f64roundToInt}{\hyperref[sailRISCVzexternzyf64roundToInt]{#2}}{}% \ifstrequal{#1}{extern_i32ToF16}{\hyperref[sailRISCVzexternzyi32ToF16]{#2}}{}% \ifstrequal{#1}{extern\_i32ToF16}{\hyperref[sailRISCVzexternzyi32ToF16]{#2}}{}% \ifstrequal{#1}{extern_i32ToF32}{\hyperref[sailRISCVzexternzyi32ToF32]{#2}}{}% @@ -9188,9 +9410,11 @@ \subsection*{Notes} \ifstrequal{#1}{haveZbkx}{\hyperref[sailRISCVzhaveZbkx]{#2}}{}% \ifstrequal{#1}{haveZbs}{\hyperref[sailRISCVzhaveZbs]{#2}}{}% \ifstrequal{#1}{haveZdinx}{\hyperref[sailRISCVzhaveZdinx]{#2}}{}% + \ifstrequal{#1}{haveZfa}{\hyperref[sailRISCVzhaveZfa]{#2}}{}% \ifstrequal{#1}{haveZfh}{\hyperref[sailRISCVzhaveZfh]{#2}}{}% \ifstrequal{#1}{haveZfinx}{\hyperref[sailRISCVzhaveZfinx]{#2}}{}% \ifstrequal{#1}{haveZhinx}{\hyperref[sailRISCVzhaveZhinx]{#2}}{}% + \ifstrequal{#1}{haveZicond}{\hyperref[sailRISCVzhaveZicond]{#2}}{}% \ifstrequal{#1}{haveZknd}{\hyperref[sailRISCVzhaveZknd]{#2}}{}% \ifstrequal{#1}{haveZkne}{\hyperref[sailRISCVzhaveZkne]{#2}}{}% \ifstrequal{#1}{haveZknh}{\hyperref[sailRISCVzhaveZknh]{#2}}{}% @@ -9198,6 +9422,12 @@ \subsection*{Notes} \ifstrequal{#1}{haveZksed}{\hyperref[sailRISCVzhaveZksed]{#2}}{}% \ifstrequal{#1}{haveZksh}{\hyperref[sailRISCVzhaveZksh]{#2}}{}% \ifstrequal{#1}{haveZmmul}{\hyperref[sailRISCVzhaveZmmul]{#2}}{}% + \ifstrequal{#1}{have_cheri_relocation}{\hyperref[sailRISCVzhavezycherizyrelocation]{#2}}{}% + \ifstrequal{#1}{have\_cheri\_relocation}{\hyperref[sailRISCVzhavezycherizyrelocation]{#2}}{}% + \ifstrequal{#1}{have_ddc_relocation}{\hyperref[sailRISCVzhavezyddczyrelocation]{#2}}{}% + \ifstrequal{#1}{have\_ddc\_relocation}{\hyperref[sailRISCVzhavezyddczyrelocation]{#2}}{}% + \ifstrequal{#1}{have_pcc_relocation}{\hyperref[sailRISCVzhavezypcczyrelocation]{#2}}{}% + \ifstrequal{#1}{have\_pcc\_relocation}{\hyperref[sailRISCVzhavezypcczyrelocation]{#2}}{}% \ifstrequal{#1}{hex_bits}{\hyperref[sailRISCVzhexzybits]{#2}}{}% \ifstrequal{#1}{hex\_bits}{\hyperref[sailRISCVzhexzybits]{#2}}{}% \ifstrequal{#1}{hex_bits_1}{\hyperref[sailRISCVzhexzybitszy1]{#2}}{}% @@ -9976,6 +10206,8 @@ \subsection*{Notes} \ifstrequal{#1}{num\_of\_word\_width}{\hyperref[sailRISCVznumzyofzywordzywidth]{#2}}{}% \ifstrequal{#1}{num_of_write_kind}{\hyperref[sailRISCVznumzyofzywritezykind]{#2}}{}% \ifstrequal{#1}{num\_of\_write\_kind}{\hyperref[sailRISCVznumzyofzywritezykind]{#2}}{}% + \ifstrequal{#1}{num_of_zicondop}{\hyperref[sailRISCVznumzyofzyzzicondop]{#2}}{}% + \ifstrequal{#1}{num\_of\_zicondop}{\hyperref[sailRISCVznumzyofzyzzicondop]{#2}}{}% \ifstrequal{#1}{nvFlag}{\hyperref[sailRISCVznvFlag]{#2}}{}% \ifstrequal{#1}{nxFlag}{\hyperref[sailRISCVznxFlag]{#2}}{}% \ifstrequal{#1}{ofFlag}{\hyperref[sailRISCVzofFlag]{#2}}{}% @@ -10119,6 +10351,12 @@ \subsection*{Notes} \ifstrequal{#1}{rC_bits}{\hyperref[sailRISCVzrCzybits]{#2}}{}% \ifstrequal{#1}{rC\_bits}{\hyperref[sailRISCVzrCzybits]{#2}}{}% \ifstrequal{#1}{rF}{\hyperref[sailRISCVzrF]{#2}}{}% + \ifstrequal{#1}{rF_D}{\hyperref[sailRISCVzrFzyD]{#2}}{}% + \ifstrequal{#1}{rF\_D}{\hyperref[sailRISCVzrFzyD]{#2}}{}% + \ifstrequal{#1}{rF_H}{\hyperref[sailRISCVzrFzyH]{#2}}{}% + \ifstrequal{#1}{rF\_H}{\hyperref[sailRISCVzrFzyH]{#2}}{}% + \ifstrequal{#1}{rF_S}{\hyperref[sailRISCVzrFzyS]{#2}}{}% + \ifstrequal{#1}{rF\_S}{\hyperref[sailRISCVzrFzyS]{#2}}{}% \ifstrequal{#1}{rF_bits}{\hyperref[sailRISCVzrFzybits]{#2}}{}% \ifstrequal{#1}{rF\_bits}{\hyperref[sailRISCVzrFzybits]{#2}}{}% \ifstrequal{#1}{rF_or_X_D}{\hyperref[sailRISCVzrFzyorzyXzyD]{#2}}{}% @@ -10171,8 +10409,12 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f16Eq}{\hyperref[sailRISCVzriscvzyf16Eq]{#2}}{}% \ifstrequal{#1}{riscv_f16Le}{\hyperref[sailRISCVzriscvzyf16Le]{#2}}{}% \ifstrequal{#1}{riscv\_f16Le}{\hyperref[sailRISCVzriscvzyf16Le]{#2}}{}% + \ifstrequal{#1}{riscv_f16Le_quiet}{\hyperref[sailRISCVzriscvzyf16Lezyquiet]{#2}}{}% + \ifstrequal{#1}{riscv\_f16Le\_quiet}{\hyperref[sailRISCVzriscvzyf16Lezyquiet]{#2}}{}% \ifstrequal{#1}{riscv_f16Lt}{\hyperref[sailRISCVzriscvzyf16Lt]{#2}}{}% \ifstrequal{#1}{riscv\_f16Lt}{\hyperref[sailRISCVzriscvzyf16Lt]{#2}}{}% + \ifstrequal{#1}{riscv_f16Lt_quiet}{\hyperref[sailRISCVzriscvzyf16Ltzyquiet]{#2}}{}% + \ifstrequal{#1}{riscv\_f16Lt\_quiet}{\hyperref[sailRISCVzriscvzyf16Ltzyquiet]{#2}}{}% \ifstrequal{#1}{riscv_f16Mul}{\hyperref[sailRISCVzriscvzyf16Mul]{#2}}{}% \ifstrequal{#1}{riscv\_f16Mul}{\hyperref[sailRISCVzriscvzyf16Mul]{#2}}{}% \ifstrequal{#1}{riscv_f16MulAdd}{\hyperref[sailRISCVzriscvzyf16MulAdd]{#2}}{}% @@ -10193,6 +10435,8 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f16ToUi32}{\hyperref[sailRISCVzriscvzyf16ToUi32]{#2}}{}% \ifstrequal{#1}{riscv_f16ToUi64}{\hyperref[sailRISCVzriscvzyf16ToUi64]{#2}}{}% \ifstrequal{#1}{riscv\_f16ToUi64}{\hyperref[sailRISCVzriscvzyf16ToUi64]{#2}}{}% + \ifstrequal{#1}{riscv_f16roundToInt}{\hyperref[sailRISCVzriscvzyf16roundToInt]{#2}}{}% + \ifstrequal{#1}{riscv\_f16roundToInt}{\hyperref[sailRISCVzriscvzyf16roundToInt]{#2}}{}% \ifstrequal{#1}{riscv_f32Add}{\hyperref[sailRISCVzriscvzyf32Add]{#2}}{}% \ifstrequal{#1}{riscv\_f32Add}{\hyperref[sailRISCVzriscvzyf32Add]{#2}}{}% \ifstrequal{#1}{riscv_f32Div}{\hyperref[sailRISCVzriscvzyf32Div]{#2}}{}% @@ -10201,8 +10445,12 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f32Eq}{\hyperref[sailRISCVzriscvzyf32Eq]{#2}}{}% \ifstrequal{#1}{riscv_f32Le}{\hyperref[sailRISCVzriscvzyf32Le]{#2}}{}% \ifstrequal{#1}{riscv\_f32Le}{\hyperref[sailRISCVzriscvzyf32Le]{#2}}{}% + \ifstrequal{#1}{riscv_f32Le_quiet}{\hyperref[sailRISCVzriscvzyf32Lezyquiet]{#2}}{}% + \ifstrequal{#1}{riscv\_f32Le\_quiet}{\hyperref[sailRISCVzriscvzyf32Lezyquiet]{#2}}{}% \ifstrequal{#1}{riscv_f32Lt}{\hyperref[sailRISCVzriscvzyf32Lt]{#2}}{}% \ifstrequal{#1}{riscv\_f32Lt}{\hyperref[sailRISCVzriscvzyf32Lt]{#2}}{}% + \ifstrequal{#1}{riscv_f32Lt_quiet}{\hyperref[sailRISCVzriscvzyf32Ltzyquiet]{#2}}{}% + \ifstrequal{#1}{riscv\_f32Lt\_quiet}{\hyperref[sailRISCVzriscvzyf32Ltzyquiet]{#2}}{}% \ifstrequal{#1}{riscv_f32Mul}{\hyperref[sailRISCVzriscvzyf32Mul]{#2}}{}% \ifstrequal{#1}{riscv\_f32Mul}{\hyperref[sailRISCVzriscvzyf32Mul]{#2}}{}% \ifstrequal{#1}{riscv_f32MulAdd}{\hyperref[sailRISCVzriscvzyf32MulAdd]{#2}}{}% @@ -10223,6 +10471,8 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f32ToUi32}{\hyperref[sailRISCVzriscvzyf32ToUi32]{#2}}{}% \ifstrequal{#1}{riscv_f32ToUi64}{\hyperref[sailRISCVzriscvzyf32ToUi64]{#2}}{}% \ifstrequal{#1}{riscv\_f32ToUi64}{\hyperref[sailRISCVzriscvzyf32ToUi64]{#2}}{}% + \ifstrequal{#1}{riscv_f32roundToInt}{\hyperref[sailRISCVzriscvzyf32roundToInt]{#2}}{}% + \ifstrequal{#1}{riscv\_f32roundToInt}{\hyperref[sailRISCVzriscvzyf32roundToInt]{#2}}{}% \ifstrequal{#1}{riscv_f64Add}{\hyperref[sailRISCVzriscvzyf64Add]{#2}}{}% \ifstrequal{#1}{riscv\_f64Add}{\hyperref[sailRISCVzriscvzyf64Add]{#2}}{}% \ifstrequal{#1}{riscv_f64Div}{\hyperref[sailRISCVzriscvzyf64Div]{#2}}{}% @@ -10231,8 +10481,12 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f64Eq}{\hyperref[sailRISCVzriscvzyf64Eq]{#2}}{}% \ifstrequal{#1}{riscv_f64Le}{\hyperref[sailRISCVzriscvzyf64Le]{#2}}{}% \ifstrequal{#1}{riscv\_f64Le}{\hyperref[sailRISCVzriscvzyf64Le]{#2}}{}% + \ifstrequal{#1}{riscv_f64Le_quiet}{\hyperref[sailRISCVzriscvzyf64Lezyquiet]{#2}}{}% + \ifstrequal{#1}{riscv\_f64Le\_quiet}{\hyperref[sailRISCVzriscvzyf64Lezyquiet]{#2}}{}% \ifstrequal{#1}{riscv_f64Lt}{\hyperref[sailRISCVzriscvzyf64Lt]{#2}}{}% \ifstrequal{#1}{riscv\_f64Lt}{\hyperref[sailRISCVzriscvzyf64Lt]{#2}}{}% + \ifstrequal{#1}{riscv_f64Lt_quiet}{\hyperref[sailRISCVzriscvzyf64Ltzyquiet]{#2}}{}% + \ifstrequal{#1}{riscv\_f64Lt\_quiet}{\hyperref[sailRISCVzriscvzyf64Ltzyquiet]{#2}}{}% \ifstrequal{#1}{riscv_f64Mul}{\hyperref[sailRISCVzriscvzyf64Mul]{#2}}{}% \ifstrequal{#1}{riscv\_f64Mul}{\hyperref[sailRISCVzriscvzyf64Mul]{#2}}{}% \ifstrequal{#1}{riscv_f64MulAdd}{\hyperref[sailRISCVzriscvzyf64MulAdd]{#2}}{}% @@ -10253,6 +10507,8 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f64ToUi32}{\hyperref[sailRISCVzriscvzyf64ToUi32]{#2}}{}% \ifstrequal{#1}{riscv_f64ToUi64}{\hyperref[sailRISCVzriscvzyf64ToUi64]{#2}}{}% \ifstrequal{#1}{riscv\_f64ToUi64}{\hyperref[sailRISCVzriscvzyf64ToUi64]{#2}}{}% + \ifstrequal{#1}{riscv_f64roundToInt}{\hyperref[sailRISCVzriscvzyf64roundToInt]{#2}}{}% + \ifstrequal{#1}{riscv\_f64roundToInt}{\hyperref[sailRISCVzriscvzyf64roundToInt]{#2}}{}% \ifstrequal{#1}{riscv_i32ToF16}{\hyperref[sailRISCVzriscvzyi32ToF16]{#2}}{}% \ifstrequal{#1}{riscv\_i32ToF16}{\hyperref[sailRISCVzriscvzyi32ToF16]{#2}}{}% \ifstrequal{#1}{riscv_i32ToF32}{\hyperref[sailRISCVzriscvzyi32ToF32]{#2}}{}% @@ -10330,6 +10586,7 @@ \subsection*{Notes} \ifstrequal{#1}{select\_instr\_or\_fcsr\_rm}{\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{#2}}{}% \ifstrequal{#1}{sep}{\hyperref[sailRISCVzsep]{#2}}{}% \ifstrequal{#1}{setCapAddr}{\hyperref[sailRISCVzsetCapAddr]{#2}}{}% + \ifstrequal{#1}{setCapAddrChecked}{\hyperref[sailRISCVzsetCapAddrChecked]{#2}}{}% \ifstrequal{#1}{setCapBounds}{\hyperref[sailRISCVzsetCapBounds]{#2}}{}% \ifstrequal{#1}{setCapFlags}{\hyperref[sailRISCVzsetCapFlags]{#2}}{}% \ifstrequal{#1}{setCapOffset}{\hyperref[sailRISCVzsetCapOffset]{#2}}{}% @@ -10472,6 +10729,8 @@ \subsection*{Notes} \ifstrequal{#1}{uop\_of\_num}{\hyperref[sailRISCVzuopzyofzynum]{#2}}{}% \ifstrequal{#1}{update_PTE_Bits}{\hyperref[sailRISCVzupdatezyPTEzyBits]{#2}}{}% \ifstrequal{#1}{update\_PTE\_Bits}{\hyperref[sailRISCVzupdatezyPTEzyBits]{#2}}{}% + \ifstrequal{#1}{update_cap_with_integer_pc}{\hyperref[sailRISCVzupdatezycapzywithzyintegerzypc]{#2}}{}% + \ifstrequal{#1}{update\_cap\_with\_integer\_pc}{\hyperref[sailRISCVzupdatezycapzywithzyintegerzypc]{#2}}{}% \ifstrequal{#1}{update_softfloat_fflags}{\hyperref[sailRISCVzupdatezysoftfloatzyfflags]{#2}}{}% \ifstrequal{#1}{update\_softfloat\_fflags}{\hyperref[sailRISCVzupdatezysoftfloatzyfflags]{#2}}{}% \ifstrequal{#1}{update_subrange}{\hyperref[sailRISCVzupdatezysubrange]{#2}}{}% @@ -10491,6 +10750,12 @@ \subsection*{Notes} \ifstrequal{#1}{wC_bits}{\hyperref[sailRISCVzwCzybits]{#2}}{}% \ifstrequal{#1}{wC\_bits}{\hyperref[sailRISCVzwCzybits]{#2}}{}% \ifstrequal{#1}{wF}{\hyperref[sailRISCVzwF]{#2}}{}% + \ifstrequal{#1}{wF_D}{\hyperref[sailRISCVzwFzyD]{#2}}{}% + \ifstrequal{#1}{wF\_D}{\hyperref[sailRISCVzwFzyD]{#2}}{}% + \ifstrequal{#1}{wF_H}{\hyperref[sailRISCVzwFzyH]{#2}}{}% + \ifstrequal{#1}{wF\_H}{\hyperref[sailRISCVzwFzyH]{#2}}{}% + \ifstrequal{#1}{wF_S}{\hyperref[sailRISCVzwFzyS]{#2}}{}% + \ifstrequal{#1}{wF\_S}{\hyperref[sailRISCVzwFzyS]{#2}}{}% \ifstrequal{#1}{wF_bits}{\hyperref[sailRISCVzwFzybits]{#2}}{}% \ifstrequal{#1}{wF\_bits}{\hyperref[sailRISCVzwFzybits]{#2}}{}% \ifstrequal{#1}{wF_or_X_D}{\hyperref[sailRISCVzwFzyorzyXzyD]{#2}}{}% @@ -10541,6 +10806,8 @@ \subsection*{Notes} \ifstrequal{#1}{xor\_vec}{\hyperref[sailRISCVzxorzyvec]{#2}}{}% \ifstrequal{#1}{zeros_implicit}{\hyperref[sailRISCVzzzeroszyimplicit]{#2}}{}% \ifstrequal{#1}{zeros\_implicit}{\hyperref[sailRISCVzzzeroszyimplicit]{#2}}{}% + \ifstrequal{#1}{zicondop_of_num}{\hyperref[sailRISCVzzzicondopzyofzynum]{#2}}{}% + \ifstrequal{#1}{zicondop\_of\_num}{\hyperref[sailRISCVzzzicondopzyofzynum]{#2}}{}% \ifstrequal{#1}{(operator <=_u)}{\hyperref[sailRISCVzz8operatorz0zIzJzyuz9]{#2}}{}% \ifstrequal{#1}{(operator $>$=\_u)}{\hyperref[sailRISCVzz8operatorz0zIzJzyuz9]{#2}}{}% \ifstrequal{#1}{(operator <_s)}{\hyperref[sailRISCVzz8operatorz0zIzysz9]{#2}}{}% @@ -10658,6 +10925,8 @@ \subsection*{Notes} \ifstrequal{#1}{capToString}{\sailRISCVfncapToString}{}% \ifstrequal{#1}{cap_reg_name_abi}{\sailRISCVfncapRegNameAbi}{}% \ifstrequal{#1}{cap\_reg\_name\_abi}{\sailRISCVfncapRegNameAbi}{}% + \ifstrequal{#1}{cap_to_integer_pc}{\sailRISCVfncapToIntegerPc}{}% + \ifstrequal{#1}{cap\_to\_integer\_pc}{\sailRISCVfncapToIntegerPc}{}% \ifstrequal{#1}{checkPTEPermission}{\sailRISCVfncheckPTEPermission}{}% \ifstrequal{#1}{check_CSR}{\sailRISCVfncheckCSR}{}% \ifstrequal{#1}{check\_CSR}{\sailRISCVfncheckCSR}{}% @@ -10704,6 +10973,8 @@ \subsection*{Notes} \ifstrequal{#1}{curPTB64}{\sailRISCVfncurPTBSixFour}{}% \ifstrequal{#1}{cur_Architecture}{\sailRISCVfncurArchitecture}{}% \ifstrequal{#1}{cur\_Architecture}{\sailRISCVfncurArchitecture}{}% + \ifstrequal{#1}{ddc_and_resulting_addr}{\sailRISCVfnddcAndResultingAddr}{}% + \ifstrequal{#1}{ddc\_and\_resulting\_addr}{\sailRISCVfnddcAndResultingAddr}{}% \ifstrequal{#1}{def_spc_backwards}{\sailRISCVfndefSpcBackwards}{}% \ifstrequal{#1}{def\_spc\_backwards}{\sailRISCVfndefSpcBackwards}{}% \ifstrequal{#1}{def_spc_forwards}{\sailRISCVfndefSpcForwards}{}% @@ -11014,9 +11285,11 @@ \subsection*{Notes} \ifstrequal{#1}{haveZbkx}{\sailRISCVfnhaveZbkx}{}% \ifstrequal{#1}{haveZbs}{\sailRISCVfnhaveZbs}{}% \ifstrequal{#1}{haveZdinx}{\sailRISCVfnhaveZdinx}{}% + \ifstrequal{#1}{haveZfa}{\sailRISCVfnhaveZfa}{}% \ifstrequal{#1}{haveZfh}{\sailRISCVfnhaveZfh}{}% \ifstrequal{#1}{haveZfinx}{\sailRISCVfnhaveZfinx}{}% \ifstrequal{#1}{haveZhinx}{\sailRISCVfnhaveZhinx}{}% + \ifstrequal{#1}{haveZicond}{\sailRISCVfnhaveZicond}{}% \ifstrequal{#1}{haveZknd}{\sailRISCVfnhaveZknd}{}% \ifstrequal{#1}{haveZkne}{\sailRISCVfnhaveZkne}{}% \ifstrequal{#1}{haveZknh}{\sailRISCVfnhaveZknh}{}% @@ -11024,6 +11297,12 @@ \subsection*{Notes} \ifstrequal{#1}{haveZksed}{\sailRISCVfnhaveZksed}{}% \ifstrequal{#1}{haveZksh}{\sailRISCVfnhaveZksh}{}% \ifstrequal{#1}{haveZmmul}{\sailRISCVfnhaveZmmul}{}% + \ifstrequal{#1}{have_cheri_relocation}{\sailRISCVfnhaveCheriRelocation}{}% + \ifstrequal{#1}{have\_cheri\_relocation}{\sailRISCVfnhaveCheriRelocation}{}% + \ifstrequal{#1}{have_ddc_relocation}{\sailRISCVfnhaveDdcRelocation}{}% + \ifstrequal{#1}{have\_ddc\_relocation}{\sailRISCVfnhaveDdcRelocation}{}% + \ifstrequal{#1}{have_pcc_relocation}{\sailRISCVfnhavePccRelocation}{}% + \ifstrequal{#1}{have\_pcc\_relocation}{\sailRISCVfnhavePccRelocation}{}% \ifstrequal{#1}{hex_bits_10_backwards}{\sailRISCVfnhexBitsOneZeroBackwards}{}% \ifstrequal{#1}{hex\_bits\_10\_backwards}{\sailRISCVfnhexBitsOneZeroBackwards}{}% \ifstrequal{#1}{hex_bits_10_backwards_matches}{\sailRISCVfnhexBitsOneZeroBackwardsMatches}{}% @@ -11551,6 +11830,8 @@ \subsection*{Notes} \ifstrequal{#1}{num\_of\_word\_width}{\sailRISCVfnnumOfWordWidth}{}% \ifstrequal{#1}{num_of_write_kind}{\sailRISCVfnnumOfWriteKind}{}% \ifstrequal{#1}{num\_of\_write\_kind}{\sailRISCVfnnumOfWriteKind}{}% + \ifstrequal{#1}{num_of_zicondop}{\sailRISCVfnnumOfZicondop}{}% + \ifstrequal{#1}{num\_of\_zicondop}{\sailRISCVfnnumOfZicondop}{}% \ifstrequal{#1}{nvFlag}{\sailRISCVfnnvFlag}{}% \ifstrequal{#1}{nxFlag}{\sailRISCVfnnxFlag}{}% \ifstrequal{#1}{ofFlag}{\sailRISCVfnofFlag}{}% @@ -11630,6 +11911,12 @@ \subsection*{Notes} \ifstrequal{#1}{rC_bits}{\sailRISCVfnrCBits}{}% \ifstrequal{#1}{rC\_bits}{\sailRISCVfnrCBits}{}% \ifstrequal{#1}{rF}{\sailRISCVfnrF}{}% + \ifstrequal{#1}{rF_D}{\sailRISCVfnrFD}{}% + \ifstrequal{#1}{rF\_D}{\sailRISCVfnrFD}{}% + \ifstrequal{#1}{rF_H}{\sailRISCVfnrFH}{}% + \ifstrequal{#1}{rF\_H}{\sailRISCVfnrFH}{}% + \ifstrequal{#1}{rF_S}{\sailRISCVfnrFS}{}% + \ifstrequal{#1}{rF\_S}{\sailRISCVfnrFS}{}% \ifstrequal{#1}{rF_bits}{\sailRISCVfnrFBits}{}% \ifstrequal{#1}{rF\_bits}{\sailRISCVfnrFBits}{}% \ifstrequal{#1}{rF_or_X_D}{\sailRISCVfnrFOrXD}{}% @@ -11674,8 +11961,12 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f16Eq}{\sailRISCVfnriscvFOneSixEq}{}% \ifstrequal{#1}{riscv_f16Le}{\sailRISCVfnriscvFOneSixLe}{}% \ifstrequal{#1}{riscv\_f16Le}{\sailRISCVfnriscvFOneSixLe}{}% + \ifstrequal{#1}{riscv_f16Le_quiet}{\sailRISCVfnriscvFOneSixLeQuiet}{}% + \ifstrequal{#1}{riscv\_f16Le\_quiet}{\sailRISCVfnriscvFOneSixLeQuiet}{}% \ifstrequal{#1}{riscv_f16Lt}{\sailRISCVfnriscvFOneSixLt}{}% \ifstrequal{#1}{riscv\_f16Lt}{\sailRISCVfnriscvFOneSixLt}{}% + \ifstrequal{#1}{riscv_f16Lt_quiet}{\sailRISCVfnriscvFOneSixLtQuiet}{}% + \ifstrequal{#1}{riscv\_f16Lt\_quiet}{\sailRISCVfnriscvFOneSixLtQuiet}{}% \ifstrequal{#1}{riscv_f16Mul}{\sailRISCVfnriscvFOneSixMul}{}% \ifstrequal{#1}{riscv\_f16Mul}{\sailRISCVfnriscvFOneSixMul}{}% \ifstrequal{#1}{riscv_f16MulAdd}{\sailRISCVfnriscvFOneSixMulAdd}{}% @@ -11696,6 +11987,8 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f16ToUi32}{\sailRISCVfnriscvFOneSixToUiThreeTwo}{}% \ifstrequal{#1}{riscv_f16ToUi64}{\sailRISCVfnriscvFOneSixToUiSixFour}{}% \ifstrequal{#1}{riscv\_f16ToUi64}{\sailRISCVfnriscvFOneSixToUiSixFour}{}% + \ifstrequal{#1}{riscv_f16roundToInt}{\sailRISCVfnriscvFOneSixroundToInt}{}% + \ifstrequal{#1}{riscv\_f16roundToInt}{\sailRISCVfnriscvFOneSixroundToInt}{}% \ifstrequal{#1}{riscv_f32Add}{\sailRISCVfnriscvFThreeTwoAdd}{}% \ifstrequal{#1}{riscv\_f32Add}{\sailRISCVfnriscvFThreeTwoAdd}{}% \ifstrequal{#1}{riscv_f32Div}{\sailRISCVfnriscvFThreeTwoDiv}{}% @@ -11704,8 +11997,12 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f32Eq}{\sailRISCVfnriscvFThreeTwoEq}{}% \ifstrequal{#1}{riscv_f32Le}{\sailRISCVfnriscvFThreeTwoLe}{}% \ifstrequal{#1}{riscv\_f32Le}{\sailRISCVfnriscvFThreeTwoLe}{}% + \ifstrequal{#1}{riscv_f32Le_quiet}{\sailRISCVfnriscvFThreeTwoLeQuiet}{}% + \ifstrequal{#1}{riscv\_f32Le\_quiet}{\sailRISCVfnriscvFThreeTwoLeQuiet}{}% \ifstrequal{#1}{riscv_f32Lt}{\sailRISCVfnriscvFThreeTwoLt}{}% \ifstrequal{#1}{riscv\_f32Lt}{\sailRISCVfnriscvFThreeTwoLt}{}% + \ifstrequal{#1}{riscv_f32Lt_quiet}{\sailRISCVfnriscvFThreeTwoLtQuiet}{}% + \ifstrequal{#1}{riscv\_f32Lt\_quiet}{\sailRISCVfnriscvFThreeTwoLtQuiet}{}% \ifstrequal{#1}{riscv_f32Mul}{\sailRISCVfnriscvFThreeTwoMul}{}% \ifstrequal{#1}{riscv\_f32Mul}{\sailRISCVfnriscvFThreeTwoMul}{}% \ifstrequal{#1}{riscv_f32MulAdd}{\sailRISCVfnriscvFThreeTwoMulAdd}{}% @@ -11726,6 +12023,8 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f32ToUi32}{\sailRISCVfnriscvFThreeTwoToUiThreeTwo}{}% \ifstrequal{#1}{riscv_f32ToUi64}{\sailRISCVfnriscvFThreeTwoToUiSixFour}{}% \ifstrequal{#1}{riscv\_f32ToUi64}{\sailRISCVfnriscvFThreeTwoToUiSixFour}{}% + \ifstrequal{#1}{riscv_f32roundToInt}{\sailRISCVfnriscvFThreeTworoundToInt}{}% + \ifstrequal{#1}{riscv\_f32roundToInt}{\sailRISCVfnriscvFThreeTworoundToInt}{}% \ifstrequal{#1}{riscv_f64Add}{\sailRISCVfnriscvFSixFourAdd}{}% \ifstrequal{#1}{riscv\_f64Add}{\sailRISCVfnriscvFSixFourAdd}{}% \ifstrequal{#1}{riscv_f64Div}{\sailRISCVfnriscvFSixFourDiv}{}% @@ -11734,8 +12033,12 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f64Eq}{\sailRISCVfnriscvFSixFourEq}{}% \ifstrequal{#1}{riscv_f64Le}{\sailRISCVfnriscvFSixFourLe}{}% \ifstrequal{#1}{riscv\_f64Le}{\sailRISCVfnriscvFSixFourLe}{}% + \ifstrequal{#1}{riscv_f64Le_quiet}{\sailRISCVfnriscvFSixFourLeQuiet}{}% + \ifstrequal{#1}{riscv\_f64Le\_quiet}{\sailRISCVfnriscvFSixFourLeQuiet}{}% \ifstrequal{#1}{riscv_f64Lt}{\sailRISCVfnriscvFSixFourLt}{}% \ifstrequal{#1}{riscv\_f64Lt}{\sailRISCVfnriscvFSixFourLt}{}% + \ifstrequal{#1}{riscv_f64Lt_quiet}{\sailRISCVfnriscvFSixFourLtQuiet}{}% + \ifstrequal{#1}{riscv\_f64Lt\_quiet}{\sailRISCVfnriscvFSixFourLtQuiet}{}% \ifstrequal{#1}{riscv_f64Mul}{\sailRISCVfnriscvFSixFourMul}{}% \ifstrequal{#1}{riscv\_f64Mul}{\sailRISCVfnriscvFSixFourMul}{}% \ifstrequal{#1}{riscv_f64MulAdd}{\sailRISCVfnriscvFSixFourMulAdd}{}% @@ -11756,6 +12059,8 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f64ToUi32}{\sailRISCVfnriscvFSixFourToUiThreeTwo}{}% \ifstrequal{#1}{riscv_f64ToUi64}{\sailRISCVfnriscvFSixFourToUiSixFour}{}% \ifstrequal{#1}{riscv\_f64ToUi64}{\sailRISCVfnriscvFSixFourToUiSixFour}{}% + \ifstrequal{#1}{riscv_f64roundToInt}{\sailRISCVfnriscvFSixFourroundToInt}{}% + \ifstrequal{#1}{riscv\_f64roundToInt}{\sailRISCVfnriscvFSixFourroundToInt}{}% \ifstrequal{#1}{riscv_i32ToF16}{\sailRISCVfnriscvIThreeTwoToFOneSix}{}% \ifstrequal{#1}{riscv\_i32ToF16}{\sailRISCVfnriscvIThreeTwoToFOneSix}{}% \ifstrequal{#1}{riscv_i32ToF32}{\sailRISCVfnriscvIThreeTwoToFThreeTwo}{}% @@ -11812,6 +12117,7 @@ \subsection*{Notes} \ifstrequal{#1}{select_instr_or_fcsr_rm}{\sailRISCVfnselectInstrOrFcsrRm}{}% \ifstrequal{#1}{select\_instr\_or\_fcsr\_rm}{\sailRISCVfnselectInstrOrFcsrRm}{}% \ifstrequal{#1}{setCapAddr}{\sailRISCVfnsetCapAddr}{}% + \ifstrequal{#1}{setCapAddrChecked}{\sailRISCVfnsetCapAddrChecked}{}% \ifstrequal{#1}{setCapBounds}{\sailRISCVfnsetCapBounds}{}% \ifstrequal{#1}{setCapFlags}{\sailRISCVfnsetCapFlags}{}% \ifstrequal{#1}{setCapOffset}{\sailRISCVfnsetCapOffset}{}% @@ -11886,6 +12192,8 @@ \subsection*{Notes} \ifstrequal{#1}{uop\_of\_num}{\sailRISCVfnuopOfNum}{}% \ifstrequal{#1}{update_PTE_Bits}{\sailRISCVfnupdatePTEBits}{}% \ifstrequal{#1}{update\_PTE\_Bits}{\sailRISCVfnupdatePTEBits}{}% + \ifstrequal{#1}{update_cap_with_integer_pc}{\sailRISCVfnupdateCapWithIntegerPc}{}% + \ifstrequal{#1}{update\_cap\_with\_integer\_pc}{\sailRISCVfnupdateCapWithIntegerPc}{}% \ifstrequal{#1}{update_softfloat_fflags}{\sailRISCVfnupdateSoftfloatFflags}{}% \ifstrequal{#1}{update\_softfloat\_fflags}{\sailRISCVfnupdateSoftfloatFflags}{}% \ifstrequal{#1}{validDoubleRegs}{\sailRISCVfnvalidDoubleRegs}{}% @@ -11895,6 +12203,12 @@ \subsection*{Notes} \ifstrequal{#1}{wC_bits}{\sailRISCVfnwCBits}{}% \ifstrequal{#1}{wC\_bits}{\sailRISCVfnwCBits}{}% \ifstrequal{#1}{wF}{\sailRISCVfnwF}{}% + \ifstrequal{#1}{wF_D}{\sailRISCVfnwFD}{}% + \ifstrequal{#1}{wF\_D}{\sailRISCVfnwFD}{}% + \ifstrequal{#1}{wF_H}{\sailRISCVfnwFH}{}% + \ifstrequal{#1}{wF\_H}{\sailRISCVfnwFH}{}% + \ifstrequal{#1}{wF_S}{\sailRISCVfnwFS}{}% + \ifstrequal{#1}{wF\_S}{\sailRISCVfnwFS}{}% \ifstrequal{#1}{wF_bits}{\sailRISCVfnwFBits}{}% \ifstrequal{#1}{wF\_bits}{\sailRISCVfnwFBits}{}% \ifstrequal{#1}{wF_or_X_D}{\sailRISCVfnwFOrXD}{}% @@ -11943,6 +12257,8 @@ \subsection*{Notes} \ifstrequal{#1}{write\_seed\_csr}{\sailRISCVfnwriteSeedCsr}{}% \ifstrequal{#1}{zeros_implicit}{\sailRISCVfnzzerosImplicit}{}% \ifstrequal{#1}{zeros\_implicit}{\sailRISCVfnzzerosImplicit}{}% + \ifstrequal{#1}{zicondop_of_num}{\sailRISCVfnzzicondopOfNum}{}% + \ifstrequal{#1}{zicondop\_of\_num}{\sailRISCVfnzzicondopOfNum}{}% \ifstrequal{#1}{(operator <=_u)}{\sailRISCVfnzEightoperatorzZerozIzJUzNine}{}% \ifstrequal{#1}{(operator $>$=\_u)}{\sailRISCVfnzEightoperatorzZerozIzJUzNine}{}% \ifstrequal{#1}{(operator <_s)}{\sailRISCVfnzEightoperatorzZerozISzNine}{}% @@ -12060,6 +12376,8 @@ \subsection*{Notes} \ifstrequal{#1}{capToString}{\hyperref[sailRISCVfnzcapToString]{#2}}{}% \ifstrequal{#1}{cap_reg_name_abi}{\hyperref[sailRISCVfnzcapzyregzynamezyabi]{#2}}{}% \ifstrequal{#1}{cap\_reg\_name\_abi}{\hyperref[sailRISCVfnzcapzyregzynamezyabi]{#2}}{}% + \ifstrequal{#1}{cap_to_integer_pc}{\hyperref[sailRISCVfnzcapzytozyintegerzypc]{#2}}{}% + \ifstrequal{#1}{cap\_to\_integer\_pc}{\hyperref[sailRISCVfnzcapzytozyintegerzypc]{#2}}{}% \ifstrequal{#1}{checkPTEPermission}{\hyperref[sailRISCVfnzcheckPTEPermission]{#2}}{}% \ifstrequal{#1}{check_CSR}{\hyperref[sailRISCVfnzcheckzyCSR]{#2}}{}% \ifstrequal{#1}{check\_CSR}{\hyperref[sailRISCVfnzcheckzyCSR]{#2}}{}% @@ -12106,6 +12424,8 @@ \subsection*{Notes} \ifstrequal{#1}{curPTB64}{\hyperref[sailRISCVfnzcurPTB64]{#2}}{}% \ifstrequal{#1}{cur_Architecture}{\hyperref[sailRISCVfnzcurzyArchitecture]{#2}}{}% \ifstrequal{#1}{cur\_Architecture}{\hyperref[sailRISCVfnzcurzyArchitecture]{#2}}{}% + \ifstrequal{#1}{ddc_and_resulting_addr}{\hyperref[sailRISCVfnzddczyandzyresultingzyaddr]{#2}}{}% + \ifstrequal{#1}{ddc\_and\_resulting\_addr}{\hyperref[sailRISCVfnzddczyandzyresultingzyaddr]{#2}}{}% \ifstrequal{#1}{def_spc_backwards}{\hyperref[sailRISCVfnzdefzyspczybackwards]{#2}}{}% \ifstrequal{#1}{def\_spc\_backwards}{\hyperref[sailRISCVfnzdefzyspczybackwards]{#2}}{}% \ifstrequal{#1}{def_spc_forwards}{\hyperref[sailRISCVfnzdefzyspczyforwards]{#2}}{}% @@ -12416,9 +12736,11 @@ \subsection*{Notes} \ifstrequal{#1}{haveZbkx}{\hyperref[sailRISCVfnzhaveZbkx]{#2}}{}% \ifstrequal{#1}{haveZbs}{\hyperref[sailRISCVfnzhaveZbs]{#2}}{}% \ifstrequal{#1}{haveZdinx}{\hyperref[sailRISCVfnzhaveZdinx]{#2}}{}% + \ifstrequal{#1}{haveZfa}{\hyperref[sailRISCVfnzhaveZfa]{#2}}{}% \ifstrequal{#1}{haveZfh}{\hyperref[sailRISCVfnzhaveZfh]{#2}}{}% \ifstrequal{#1}{haveZfinx}{\hyperref[sailRISCVfnzhaveZfinx]{#2}}{}% \ifstrequal{#1}{haveZhinx}{\hyperref[sailRISCVfnzhaveZhinx]{#2}}{}% + \ifstrequal{#1}{haveZicond}{\hyperref[sailRISCVfnzhaveZicond]{#2}}{}% \ifstrequal{#1}{haveZknd}{\hyperref[sailRISCVfnzhaveZknd]{#2}}{}% \ifstrequal{#1}{haveZkne}{\hyperref[sailRISCVfnzhaveZkne]{#2}}{}% \ifstrequal{#1}{haveZknh}{\hyperref[sailRISCVfnzhaveZknh]{#2}}{}% @@ -12426,6 +12748,12 @@ \subsection*{Notes} \ifstrequal{#1}{haveZksed}{\hyperref[sailRISCVfnzhaveZksed]{#2}}{}% \ifstrequal{#1}{haveZksh}{\hyperref[sailRISCVfnzhaveZksh]{#2}}{}% \ifstrequal{#1}{haveZmmul}{\hyperref[sailRISCVfnzhaveZmmul]{#2}}{}% + \ifstrequal{#1}{have_cheri_relocation}{\hyperref[sailRISCVfnzhavezycherizyrelocation]{#2}}{}% + \ifstrequal{#1}{have\_cheri\_relocation}{\hyperref[sailRISCVfnzhavezycherizyrelocation]{#2}}{}% + \ifstrequal{#1}{have_ddc_relocation}{\hyperref[sailRISCVfnzhavezyddczyrelocation]{#2}}{}% + \ifstrequal{#1}{have\_ddc\_relocation}{\hyperref[sailRISCVfnzhavezyddczyrelocation]{#2}}{}% + \ifstrequal{#1}{have_pcc_relocation}{\hyperref[sailRISCVfnzhavezypcczyrelocation]{#2}}{}% + \ifstrequal{#1}{have\_pcc\_relocation}{\hyperref[sailRISCVfnzhavezypcczyrelocation]{#2}}{}% \ifstrequal{#1}{hex_bits_10_backwards}{\hyperref[sailRISCVfnzhexzybitszy10zybackwards]{#2}}{}% \ifstrequal{#1}{hex\_bits\_10\_backwards}{\hyperref[sailRISCVfnzhexzybitszy10zybackwards]{#2}}{}% \ifstrequal{#1}{hex_bits_10_backwards_matches}{\hyperref[sailRISCVfnzhexzybitszy10zybackwardszymatches]{#2}}{}% @@ -12953,6 +13281,8 @@ \subsection*{Notes} \ifstrequal{#1}{num\_of\_word\_width}{\hyperref[sailRISCVfnznumzyofzywordzywidth]{#2}}{}% \ifstrequal{#1}{num_of_write_kind}{\hyperref[sailRISCVfnznumzyofzywritezykind]{#2}}{}% \ifstrequal{#1}{num\_of\_write\_kind}{\hyperref[sailRISCVfnznumzyofzywritezykind]{#2}}{}% + \ifstrequal{#1}{num_of_zicondop}{\hyperref[sailRISCVfnznumzyofzyzzicondop]{#2}}{}% + \ifstrequal{#1}{num\_of\_zicondop}{\hyperref[sailRISCVfnznumzyofzyzzicondop]{#2}}{}% \ifstrequal{#1}{nvFlag}{\hyperref[sailRISCVfnznvFlag]{#2}}{}% \ifstrequal{#1}{nxFlag}{\hyperref[sailRISCVfnznxFlag]{#2}}{}% \ifstrequal{#1}{ofFlag}{\hyperref[sailRISCVfnzofFlag]{#2}}{}% @@ -13032,6 +13362,12 @@ \subsection*{Notes} \ifstrequal{#1}{rC_bits}{\hyperref[sailRISCVfnzrCzybits]{#2}}{}% \ifstrequal{#1}{rC\_bits}{\hyperref[sailRISCVfnzrCzybits]{#2}}{}% \ifstrequal{#1}{rF}{\hyperref[sailRISCVfnzrF]{#2}}{}% + \ifstrequal{#1}{rF_D}{\hyperref[sailRISCVfnzrFzyD]{#2}}{}% + \ifstrequal{#1}{rF\_D}{\hyperref[sailRISCVfnzrFzyD]{#2}}{}% + \ifstrequal{#1}{rF_H}{\hyperref[sailRISCVfnzrFzyH]{#2}}{}% + \ifstrequal{#1}{rF\_H}{\hyperref[sailRISCVfnzrFzyH]{#2}}{}% + \ifstrequal{#1}{rF_S}{\hyperref[sailRISCVfnzrFzyS]{#2}}{}% + \ifstrequal{#1}{rF\_S}{\hyperref[sailRISCVfnzrFzyS]{#2}}{}% \ifstrequal{#1}{rF_bits}{\hyperref[sailRISCVfnzrFzybits]{#2}}{}% \ifstrequal{#1}{rF\_bits}{\hyperref[sailRISCVfnzrFzybits]{#2}}{}% \ifstrequal{#1}{rF_or_X_D}{\hyperref[sailRISCVfnzrFzyorzyXzyD]{#2}}{}% @@ -13076,8 +13412,12 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f16Eq}{\hyperref[sailRISCVfnzriscvzyf16Eq]{#2}}{}% \ifstrequal{#1}{riscv_f16Le}{\hyperref[sailRISCVfnzriscvzyf16Le]{#2}}{}% \ifstrequal{#1}{riscv\_f16Le}{\hyperref[sailRISCVfnzriscvzyf16Le]{#2}}{}% + \ifstrequal{#1}{riscv_f16Le_quiet}{\hyperref[sailRISCVfnzriscvzyf16Lezyquiet]{#2}}{}% + \ifstrequal{#1}{riscv\_f16Le\_quiet}{\hyperref[sailRISCVfnzriscvzyf16Lezyquiet]{#2}}{}% \ifstrequal{#1}{riscv_f16Lt}{\hyperref[sailRISCVfnzriscvzyf16Lt]{#2}}{}% \ifstrequal{#1}{riscv\_f16Lt}{\hyperref[sailRISCVfnzriscvzyf16Lt]{#2}}{}% + \ifstrequal{#1}{riscv_f16Lt_quiet}{\hyperref[sailRISCVfnzriscvzyf16Ltzyquiet]{#2}}{}% + \ifstrequal{#1}{riscv\_f16Lt\_quiet}{\hyperref[sailRISCVfnzriscvzyf16Ltzyquiet]{#2}}{}% \ifstrequal{#1}{riscv_f16Mul}{\hyperref[sailRISCVfnzriscvzyf16Mul]{#2}}{}% \ifstrequal{#1}{riscv\_f16Mul}{\hyperref[sailRISCVfnzriscvzyf16Mul]{#2}}{}% \ifstrequal{#1}{riscv_f16MulAdd}{\hyperref[sailRISCVfnzriscvzyf16MulAdd]{#2}}{}% @@ -13098,6 +13438,8 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f16ToUi32}{\hyperref[sailRISCVfnzriscvzyf16ToUi32]{#2}}{}% \ifstrequal{#1}{riscv_f16ToUi64}{\hyperref[sailRISCVfnzriscvzyf16ToUi64]{#2}}{}% \ifstrequal{#1}{riscv\_f16ToUi64}{\hyperref[sailRISCVfnzriscvzyf16ToUi64]{#2}}{}% + \ifstrequal{#1}{riscv_f16roundToInt}{\hyperref[sailRISCVfnzriscvzyf16roundToInt]{#2}}{}% + \ifstrequal{#1}{riscv\_f16roundToInt}{\hyperref[sailRISCVfnzriscvzyf16roundToInt]{#2}}{}% \ifstrequal{#1}{riscv_f32Add}{\hyperref[sailRISCVfnzriscvzyf32Add]{#2}}{}% \ifstrequal{#1}{riscv\_f32Add}{\hyperref[sailRISCVfnzriscvzyf32Add]{#2}}{}% \ifstrequal{#1}{riscv_f32Div}{\hyperref[sailRISCVfnzriscvzyf32Div]{#2}}{}% @@ -13106,8 +13448,12 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f32Eq}{\hyperref[sailRISCVfnzriscvzyf32Eq]{#2}}{}% \ifstrequal{#1}{riscv_f32Le}{\hyperref[sailRISCVfnzriscvzyf32Le]{#2}}{}% \ifstrequal{#1}{riscv\_f32Le}{\hyperref[sailRISCVfnzriscvzyf32Le]{#2}}{}% + \ifstrequal{#1}{riscv_f32Le_quiet}{\hyperref[sailRISCVfnzriscvzyf32Lezyquiet]{#2}}{}% + \ifstrequal{#1}{riscv\_f32Le\_quiet}{\hyperref[sailRISCVfnzriscvzyf32Lezyquiet]{#2}}{}% \ifstrequal{#1}{riscv_f32Lt}{\hyperref[sailRISCVfnzriscvzyf32Lt]{#2}}{}% \ifstrequal{#1}{riscv\_f32Lt}{\hyperref[sailRISCVfnzriscvzyf32Lt]{#2}}{}% + \ifstrequal{#1}{riscv_f32Lt_quiet}{\hyperref[sailRISCVfnzriscvzyf32Ltzyquiet]{#2}}{}% + \ifstrequal{#1}{riscv\_f32Lt\_quiet}{\hyperref[sailRISCVfnzriscvzyf32Ltzyquiet]{#2}}{}% \ifstrequal{#1}{riscv_f32Mul}{\hyperref[sailRISCVfnzriscvzyf32Mul]{#2}}{}% \ifstrequal{#1}{riscv\_f32Mul}{\hyperref[sailRISCVfnzriscvzyf32Mul]{#2}}{}% \ifstrequal{#1}{riscv_f32MulAdd}{\hyperref[sailRISCVfnzriscvzyf32MulAdd]{#2}}{}% @@ -13128,6 +13474,8 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f32ToUi32}{\hyperref[sailRISCVfnzriscvzyf32ToUi32]{#2}}{}% \ifstrequal{#1}{riscv_f32ToUi64}{\hyperref[sailRISCVfnzriscvzyf32ToUi64]{#2}}{}% \ifstrequal{#1}{riscv\_f32ToUi64}{\hyperref[sailRISCVfnzriscvzyf32ToUi64]{#2}}{}% + \ifstrequal{#1}{riscv_f32roundToInt}{\hyperref[sailRISCVfnzriscvzyf32roundToInt]{#2}}{}% + \ifstrequal{#1}{riscv\_f32roundToInt}{\hyperref[sailRISCVfnzriscvzyf32roundToInt]{#2}}{}% \ifstrequal{#1}{riscv_f64Add}{\hyperref[sailRISCVfnzriscvzyf64Add]{#2}}{}% \ifstrequal{#1}{riscv\_f64Add}{\hyperref[sailRISCVfnzriscvzyf64Add]{#2}}{}% \ifstrequal{#1}{riscv_f64Div}{\hyperref[sailRISCVfnzriscvzyf64Div]{#2}}{}% @@ -13136,8 +13484,12 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f64Eq}{\hyperref[sailRISCVfnzriscvzyf64Eq]{#2}}{}% \ifstrequal{#1}{riscv_f64Le}{\hyperref[sailRISCVfnzriscvzyf64Le]{#2}}{}% \ifstrequal{#1}{riscv\_f64Le}{\hyperref[sailRISCVfnzriscvzyf64Le]{#2}}{}% + \ifstrequal{#1}{riscv_f64Le_quiet}{\hyperref[sailRISCVfnzriscvzyf64Lezyquiet]{#2}}{}% + \ifstrequal{#1}{riscv\_f64Le\_quiet}{\hyperref[sailRISCVfnzriscvzyf64Lezyquiet]{#2}}{}% \ifstrequal{#1}{riscv_f64Lt}{\hyperref[sailRISCVfnzriscvzyf64Lt]{#2}}{}% \ifstrequal{#1}{riscv\_f64Lt}{\hyperref[sailRISCVfnzriscvzyf64Lt]{#2}}{}% + \ifstrequal{#1}{riscv_f64Lt_quiet}{\hyperref[sailRISCVfnzriscvzyf64Ltzyquiet]{#2}}{}% + \ifstrequal{#1}{riscv\_f64Lt\_quiet}{\hyperref[sailRISCVfnzriscvzyf64Ltzyquiet]{#2}}{}% \ifstrequal{#1}{riscv_f64Mul}{\hyperref[sailRISCVfnzriscvzyf64Mul]{#2}}{}% \ifstrequal{#1}{riscv\_f64Mul}{\hyperref[sailRISCVfnzriscvzyf64Mul]{#2}}{}% \ifstrequal{#1}{riscv_f64MulAdd}{\hyperref[sailRISCVfnzriscvzyf64MulAdd]{#2}}{}% @@ -13158,6 +13510,8 @@ \subsection*{Notes} \ifstrequal{#1}{riscv\_f64ToUi32}{\hyperref[sailRISCVfnzriscvzyf64ToUi32]{#2}}{}% \ifstrequal{#1}{riscv_f64ToUi64}{\hyperref[sailRISCVfnzriscvzyf64ToUi64]{#2}}{}% \ifstrequal{#1}{riscv\_f64ToUi64}{\hyperref[sailRISCVfnzriscvzyf64ToUi64]{#2}}{}% + \ifstrequal{#1}{riscv_f64roundToInt}{\hyperref[sailRISCVfnzriscvzyf64roundToInt]{#2}}{}% + \ifstrequal{#1}{riscv\_f64roundToInt}{\hyperref[sailRISCVfnzriscvzyf64roundToInt]{#2}}{}% \ifstrequal{#1}{riscv_i32ToF16}{\hyperref[sailRISCVfnzriscvzyi32ToF16]{#2}}{}% \ifstrequal{#1}{riscv\_i32ToF16}{\hyperref[sailRISCVfnzriscvzyi32ToF16]{#2}}{}% \ifstrequal{#1}{riscv_i32ToF32}{\hyperref[sailRISCVfnzriscvzyi32ToF32]{#2}}{}% @@ -13214,6 +13568,7 @@ \subsection*{Notes} \ifstrequal{#1}{select_instr_or_fcsr_rm}{\hyperref[sailRISCVfnzselectzyinstrzyorzyfcsrzyrm]{#2}}{}% \ifstrequal{#1}{select\_instr\_or\_fcsr\_rm}{\hyperref[sailRISCVfnzselectzyinstrzyorzyfcsrzyrm]{#2}}{}% \ifstrequal{#1}{setCapAddr}{\hyperref[sailRISCVfnzsetCapAddr]{#2}}{}% + \ifstrequal{#1}{setCapAddrChecked}{\hyperref[sailRISCVfnzsetCapAddrChecked]{#2}}{}% \ifstrequal{#1}{setCapBounds}{\hyperref[sailRISCVfnzsetCapBounds]{#2}}{}% \ifstrequal{#1}{setCapFlags}{\hyperref[sailRISCVfnzsetCapFlags]{#2}}{}% \ifstrequal{#1}{setCapOffset}{\hyperref[sailRISCVfnzsetCapOffset]{#2}}{}% @@ -13288,6 +13643,8 @@ \subsection*{Notes} \ifstrequal{#1}{uop\_of\_num}{\hyperref[sailRISCVfnzuopzyofzynum]{#2}}{}% \ifstrequal{#1}{update_PTE_Bits}{\hyperref[sailRISCVfnzupdatezyPTEzyBits]{#2}}{}% \ifstrequal{#1}{update\_PTE\_Bits}{\hyperref[sailRISCVfnzupdatezyPTEzyBits]{#2}}{}% + \ifstrequal{#1}{update_cap_with_integer_pc}{\hyperref[sailRISCVfnzupdatezycapzywithzyintegerzypc]{#2}}{}% + \ifstrequal{#1}{update\_cap\_with\_integer\_pc}{\hyperref[sailRISCVfnzupdatezycapzywithzyintegerzypc]{#2}}{}% \ifstrequal{#1}{update_softfloat_fflags}{\hyperref[sailRISCVfnzupdatezysoftfloatzyfflags]{#2}}{}% \ifstrequal{#1}{update\_softfloat\_fflags}{\hyperref[sailRISCVfnzupdatezysoftfloatzyfflags]{#2}}{}% \ifstrequal{#1}{validDoubleRegs}{\hyperref[sailRISCVfnzvalidDoubleRegs]{#2}}{}% @@ -13297,6 +13654,12 @@ \subsection*{Notes} \ifstrequal{#1}{wC_bits}{\hyperref[sailRISCVfnzwCzybits]{#2}}{}% \ifstrequal{#1}{wC\_bits}{\hyperref[sailRISCVfnzwCzybits]{#2}}{}% \ifstrequal{#1}{wF}{\hyperref[sailRISCVfnzwF]{#2}}{}% + \ifstrequal{#1}{wF_D}{\hyperref[sailRISCVfnzwFzyD]{#2}}{}% + \ifstrequal{#1}{wF\_D}{\hyperref[sailRISCVfnzwFzyD]{#2}}{}% + \ifstrequal{#1}{wF_H}{\hyperref[sailRISCVfnzwFzyH]{#2}}{}% + \ifstrequal{#1}{wF\_H}{\hyperref[sailRISCVfnzwFzyH]{#2}}{}% + \ifstrequal{#1}{wF_S}{\hyperref[sailRISCVfnzwFzyS]{#2}}{}% + \ifstrequal{#1}{wF\_S}{\hyperref[sailRISCVfnzwFzyS]{#2}}{}% \ifstrequal{#1}{wF_bits}{\hyperref[sailRISCVfnzwFzybits]{#2}}{}% \ifstrequal{#1}{wF\_bits}{\hyperref[sailRISCVfnzwFzybits]{#2}}{}% \ifstrequal{#1}{wF_or_X_D}{\hyperref[sailRISCVfnzwFzyorzyXzyD]{#2}}{}% @@ -13345,6 +13708,8 @@ \subsection*{Notes} \ifstrequal{#1}{write\_seed\_csr}{\hyperref[sailRISCVfnzwritezyseedzycsr]{#2}}{}% \ifstrequal{#1}{zeros_implicit}{\hyperref[sailRISCVfnzzzeroszyimplicit]{#2}}{}% \ifstrequal{#1}{zeros\_implicit}{\hyperref[sailRISCVfnzzzeroszyimplicit]{#2}}{}% + \ifstrequal{#1}{zicondop_of_num}{\hyperref[sailRISCVfnzzzicondopzyofzynum]{#2}}{}% + \ifstrequal{#1}{zicondop\_of\_num}{\hyperref[sailRISCVfnzzzicondopzyofzynum]{#2}}{}% \ifstrequal{#1}{(operator <=_u)}{\hyperref[sailRISCVfnzz8operatorz0zIzJzyuz9]{#2}}{}% \ifstrequal{#1}{(operator $>$=\_u)}{\hyperref[sailRISCVfnzz8operatorz0zIzJzyuz9]{#2}}{}% \ifstrequal{#1}{(operator <_s)}{\hyperref[sailRISCVfnzz8operatorz0zIzysz9]{#2}}{}% @@ -13665,7 +14030,8 @@ \subsection*{Notes} \ifstrequal{#1}{xlen}{\sailRISCVtypexlen}{}% \ifstrequal{#1}{xlen_bytes}{\sailRISCVtypexlenBytes}{}% \ifstrequal{#1}{xlen\_bytes}{\sailRISCVtypexlenBytes}{}% - \ifstrequal{#1}{xlenbits}{\sailRISCVtypexlenbits}{}} + \ifstrequal{#1}{xlenbits}{\sailRISCVtypexlenbits}{}% + \ifstrequal{#1}{zicondop}{\sailRISCVtypezzicondop}{}} \newcommand{\sailRISCVreftype}[2]{ \ifstrequal{#1}{AccessType}{\hyperref[sailRISCVtypezAccessType]{#2}}{}% @@ -13976,7 +14342,8 @@ \subsection*{Notes} \ifstrequal{#1}{xlen}{\hyperref[sailRISCVtypezxlen]{#2}}{}% \ifstrequal{#1}{xlen_bytes}{\hyperref[sailRISCVtypezxlenzybytes]{#2}}{}% \ifstrequal{#1}{xlen\_bytes}{\hyperref[sailRISCVtypezxlenzybytes]{#2}}{}% - \ifstrequal{#1}{xlenbits}{\hyperref[sailRISCVtypezxlenbits]{#2}}{}} + \ifstrequal{#1}{xlenbits}{\hyperref[sailRISCVtypezxlenbits]{#2}}{}% + \ifstrequal{#1}{zicondop}{\hyperref[sailRISCVtypezzzicondop]{#2}}{}} \newcommand{\sailRISCVlet}[1]{ \ifstrequal{#1}{CIA_fp}{\sailRISCVletCIAFp}{}% @@ -14307,8 +14674,8 @@ \subsection*{Notes} \ifstrequal{#1}{mie}{\sailRISCVregistermie}{}% \ifstrequal{#1}{mimpid}{\sailRISCVregistermimpid}{}% \ifstrequal{#1}{minstret}{\sailRISCVregisterminstret}{}% - \ifstrequal{#1}{minstret_written}{\sailRISCVregisterminstretWritten}{}% - \ifstrequal{#1}{minstret\_written}{\sailRISCVregisterminstretWritten}{}% + \ifstrequal{#1}{minstret_increment}{\sailRISCVregisterminstretIncrement}{}% + \ifstrequal{#1}{minstret\_increment}{\sailRISCVregisterminstretIncrement}{}% \ifstrequal{#1}{mip}{\sailRISCVregistermip}{}% \ifstrequal{#1}{misa}{\sailRISCVregistermisa}{}% \ifstrequal{#1}{mscratch}{\sailRISCVregistermscratch}{}% @@ -14485,8 +14852,8 @@ \subsection*{Notes} \ifstrequal{#1}{mie}{\hyperref[sailRISCVregisterzmie]{#2}}{}% \ifstrequal{#1}{mimpid}{\hyperref[sailRISCVregisterzmimpid]{#2}}{}% \ifstrequal{#1}{minstret}{\hyperref[sailRISCVregisterzminstret]{#2}}{}% - \ifstrequal{#1}{minstret_written}{\hyperref[sailRISCVregisterzminstretzywritten]{#2}}{}% - \ifstrequal{#1}{minstret\_written}{\hyperref[sailRISCVregisterzminstretzywritten]{#2}}{}% + \ifstrequal{#1}{minstret_increment}{\hyperref[sailRISCVregisterzminstretzyincrement]{#2}}{}% + \ifstrequal{#1}{minstret\_increment}{\hyperref[sailRISCVregisterzminstretzyincrement]{#2}}{}% \ifstrequal{#1}{mip}{\hyperref[sailRISCVregisterzmip]{#2}}{}% \ifstrequal{#1}{misa}{\hyperref[sailRISCVregisterzmisa]{#2}}{}% \ifstrequal{#1}{mscratch}{\hyperref[sailRISCVregisterzmscratch]{#2}}{}% diff --git a/sail_latex_riscv/fclCInvokezexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCInvokezexecute33a689e3a631b9b905b85461d3814943.tex index 11b77356..c434d770 100644 --- a/sail_latex_riscv/fclCInvokezexecute33a689e3a631b9b905b85461d3814943.tex +++ b/sail_latex_riscv/fclCInvokezexecute33a689e3a631b9b905b85461d3814943.tex @@ -29,15 +29,15 @@ } else if cs2_val.permit_execute then { #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_PermitExecuteViolation, cs2); RETIRE_FAIL -} else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(cs1_val, newPC, #\hyperref[sailRISCVzminzyinstructionzybytes]{min\_instruction\_bytes}#())) then { - #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs1); - RETIRE_FAIL -} else if newPCCBase[0] == bitone | (newPCCBase[1] == bitone & ~(#\hyperref[sailRISCVzhaveRVC]{haveRVC}#())) then { +} else if #\hyperref[sailRISCVzhavezypcczyrelocation]{have\_pcc\_relocation}#() & (newPCCBase[0] == bitone | (newPCCBase[1] == bitone & ~(#\hyperref[sailRISCVzhaveRVC]{haveRVC}#()))) then { #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_UnalignedBase, cs1); RETIRE_FAIL } else if newPC[1] == bitone & ~(#\hyperref[sailRISCVzhaveRVC]{haveRVC}#()) then { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(newPC, #\hyperref[sailRISCVzEzyFetchzyAddrzyAlign]{E\_Fetch\_Addr\_Align}#()); RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(cs1_val, newPC, #\hyperref[sailRISCVzminzyinstructionzybytes]{min\_instruction\_bytes}#())) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs1); + RETIRE_FAIL } else { #\hyperref[sailRISCVzC]{C}#(31) = #\hyperref[sailRISCVzunsealCap]{unsealCap}#(cs2_val); nextPC = newPC; diff --git a/sail_latex_riscv/fclCJALRzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCJALRzexecute33a689e3a631b9b905b85461d3814943.tex index e211d9b2..d9e3a56a 100644 --- a/sail_latex_riscv/fclCJALRzexecute33a689e3a631b9b905b85461d3814943.tex +++ b/sail_latex_riscv/fclCJALRzexecute33a689e3a631b9b905b85461d3814943.tex @@ -12,15 +12,15 @@ } else if #\hyperref[sailRISCVznot]{not}#(cs1_val.permit_execute) then { #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_PermitExecuteViolation, cs1); RETIRE_FAIL -} else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(cs1_val, newPC, #\hyperref[sailRISCVzminzyinstructionzybytes]{min\_instruction\_bytes}#())) then { - #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs1); - RETIRE_FAIL -} else if newPCCBase[0] == bitone | (newPCCBase[1] == bitone & ~(#\hyperref[sailRISCVzhaveRVC]{haveRVC}#())) then { +} else if #\hyperref[sailRISCVzhavezypcczyrelocation]{have\_pcc\_relocation}#() & (newPCCBase[0] == bitone | (newPCCBase[1] == bitone & ~(#\hyperref[sailRISCVzhaveRVC]{haveRVC}#()))) then { #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_UnalignedBase, cs1); RETIRE_FAIL } else if newPC[1] == bitone & ~(#\hyperref[sailRISCVzhaveRVC]{haveRVC}#()) then { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(newPC, #\hyperref[sailRISCVzEzyFetchzyAddrzyAlign]{E\_Fetch\_Addr\_Align}#()); RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(cs1_val, newPC, #\hyperref[sailRISCVzminzyinstructionzybytes]{min\_instruction\_bytes}#())) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs1); + RETIRE_FAIL } else { let (success, linkCap) = #\hyperref[sailRISCVzsetCapAddr]{setCapAddr}#(PCC, nextPC); /* Note that nextPC accounts for compressed instructions */ assert(success, "Link cap should always be representable."); diff --git a/sail_latex_riscv/fclCSpecialRWzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCSpecialRWzexecute33a689e3a631b9b905b85461d3814943.tex index d4cd5630..d93056b7 100644 --- a/sail_latex_riscv/fclCSpecialRWzexecute33a689e3a631b9b905b85461d3814943.tex +++ b/sail_latex_riscv/fclCSpecialRWzexecute33a689e3a631b9b905b85461d3814943.tex @@ -62,7 +62,9 @@ 30 => MScratchC = cs1_val, 31 => MEPCC = cs1_val, _ => assert(false, "unreachable") - } + }; + if #\hyperref[sailRISCVzgetzyconfigzyprintzyreg]{get\_config\_print\_reg}#() then + #\hyperref[sailRISCVzprintzyreg]{print\_reg}#(#\hyperref[sailRISCVzscrzynamezymap]{scr\_name\_map}#(scr) ^ " <- " ^ #\hyperref[sailRISCVzRegStr]{RegStr}#(cs1_val)); }; RETIRE_SUCCESS } diff --git a/sail_latex_riscv/fclLoadCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclLoadCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex index 2b986eae..63326dbd 100644 --- a/sail_latex_riscv/fclLoadCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex +++ b/sail_latex_riscv/fclLoadCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -1,3 +1,2 @@ -let ddc_val = DDC; -let vaddr = ddc_val.address + #\hyperref[sailRISCVzX]{X}#(rs1); +let (ddc_val, vaddr) = #\hyperref[sailRISCVzddczyandzyresultingzyaddr]{ddc\_and\_resulting\_addr}#(#\hyperref[sailRISCVzX]{X}#(rs1)); #\hyperref[sailRISCVzhandlezyloadzycapzyviazycap]{handle\_load\_cap\_via\_cap}#(cd, DDC_IDX, ddc_val, vaddr) diff --git a/sail_latex_riscv/fclLoadDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclLoadDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex index b9832bd7..1f11f3cb 100644 --- a/sail_latex_riscv/fclLoadDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex +++ b/sail_latex_riscv/fclLoadDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -1,3 +1,2 @@ -let ddc_val = DDC; -let vaddr = ddc_val.address + #\hyperref[sailRISCVzX]{X}#(rs1); +let (ddc_val, vaddr) = #\hyperref[sailRISCVzddczyandzyresultingzyaddr]{ddc\_and\_resulting\_addr}#(#\hyperref[sailRISCVzX]{X}#(rs1)); #\hyperref[sailRISCVzhandlezyloadzydatazyviazycap]{handle\_load\_data\_via\_cap}#(rd, DDC_IDX, ddc_val, vaddr, is_unsigned, width) diff --git a/sail_latex_riscv/fclLoadResCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclLoadResCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex index 927e95f9..18ca03ee 100644 --- a/sail_latex_riscv/fclLoadResCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex +++ b/sail_latex_riscv/fclLoadResCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -1,6 +1,5 @@ if #\hyperref[sailRISCVzhaveAtomics]{haveAtomics}#() then { - let ddc_val = DDC; - let vaddr = ddc_val.address + #\hyperref[sailRISCVzX]{X}#(rs1); + let (ddc_val, vaddr) = #\hyperref[sailRISCVzddczyandzyresultingzyaddr]{ddc\_and\_resulting\_addr}#(#\hyperref[sailRISCVzX]{X}#(rs1)); #\hyperref[sailRISCVzhandlezyloadreszycapzyviazycap]{handle\_loadres\_cap\_via\_cap}#(cd, DDC_IDX, ddc_val, vaddr, false, false) } else { #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); diff --git a/sail_latex_riscv/fclLoadResDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclLoadResDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex index 1c7a5edb..5d178f77 100644 --- a/sail_latex_riscv/fclLoadResDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex +++ b/sail_latex_riscv/fclLoadResDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -1,6 +1,5 @@ if #\hyperref[sailRISCVzhaveAtomics]{haveAtomics}#() then { - let ddc_val = DDC; - let vaddr = ddc_val.address + #\hyperref[sailRISCVzX]{X}#(rs1); + let (ddc_val, vaddr) = #\hyperref[sailRISCVzddczyandzyresultingzyaddr]{ddc\_and\_resulting\_addr}#(#\hyperref[sailRISCVzX]{X}#(rs1)); #\hyperref[sailRISCVzhandlezyloadreszydatazyviazycap]{handle\_loadres\_data\_via\_cap}#(rd, DDC_IDX, ddc_val, vaddr, width) } else { #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); diff --git a/sail_latex_riscv/fclStoreCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclStoreCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex index 872c7e3e..077fc697 100644 --- a/sail_latex_riscv/fclStoreCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex +++ b/sail_latex_riscv/fclStoreCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -1,3 +1,2 @@ -let ddc_val = DDC; -let vaddr = ddc_val.address + #\hyperref[sailRISCVzX]{X}#(rs1); +let (ddc_val, vaddr) = #\hyperref[sailRISCVzddczyandzyresultingzyaddr]{ddc\_and\_resulting\_addr}#(#\hyperref[sailRISCVzX]{X}#(rs1)); #\hyperref[sailRISCVzhandlezystorezycapzyviazycap]{handle\_store\_cap\_via\_cap}#(cs2, DDC_IDX, ddc_val, vaddr) diff --git a/sail_latex_riscv/fclStoreCondCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclStoreCondCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex index ae816a23..e86f52f4 100644 --- a/sail_latex_riscv/fclStoreCondCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex +++ b/sail_latex_riscv/fclStoreCondCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -5,8 +5,7 @@ #\hyperref[sailRISCVzC]{C}#(cs2) = #\hyperref[sailRISCVzintzytozycap]{int\_to\_cap}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b1)); RETIRE_SUCCESS } else if #\hyperref[sailRISCVzhaveAtomics]{haveAtomics}#() then { - let ddc_val = DDC; - let vaddr = ddc_val.address + #\hyperref[sailRISCVzX]{X}#(rs1); + let (ddc_val, vaddr) = #\hyperref[sailRISCVzddczyandzyresultingzyaddr]{ddc\_and\_resulting\_addr}#(#\hyperref[sailRISCVzX]{X}#(rs1)); #\hyperref[sailRISCVzhandlezystorezycondzycapzyviazycap]{handle\_store\_cond\_cap\_via\_cap}#(cs2, cs2, DDC_IDX, ddc_val, vaddr, false, false, true) } else { #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); diff --git a/sail_latex_riscv/fclStoreCondDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclStoreCondDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex index 4d341708..75689a1a 100644 --- a/sail_latex_riscv/fclStoreCondDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex +++ b/sail_latex_riscv/fclStoreCondDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -5,8 +5,7 @@ #\hyperref[sailRISCVzX]{X}#(rs2) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b1); RETIRE_SUCCESS } else if #\hyperref[sailRISCVzhaveAtomics]{haveAtomics}#() then { - let ddc_val = DDC; - let vaddr = ddc_val.address + #\hyperref[sailRISCVzX]{X}#(rs1); + let (ddc_val, vaddr) = #\hyperref[sailRISCVzddczyandzyresultingzyaddr]{ddc\_and\_resulting\_addr}#(#\hyperref[sailRISCVzX]{X}#(rs1)); #\hyperref[sailRISCVzhandlezystorezycondzydatazyviazycap]{handle\_store\_cond\_data\_via\_cap}#(rs2, DDC_IDX, ddc_val, vaddr, width) } else { #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); diff --git a/sail_latex_riscv/fclStoreDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclStoreDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex index 6f69313b..90b6f086 100644 --- a/sail_latex_riscv/fclStoreDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex +++ b/sail_latex_riscv/fclStoreDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -1,3 +1,2 @@ -let ddc_val = DDC; -let vaddr = ddc_val.address + #\hyperref[sailRISCVzX]{X}#(rs1); +let (ddc_val, vaddr) = #\hyperref[sailRISCVzddczyandzyresultingzyaddr]{ddc\_and\_resulting\_addr}#(#\hyperref[sailRISCVzX]{X}#(rs1)); #\hyperref[sailRISCVzhandlezystorezydatazyviazycap]{handle\_store\_data\_via\_cap}#(rs2, DDC_IDX, ddc_val, vaddr, width) diff --git a/sail_latex_riscv/fnzcap_to_integer_pcfb8f9e29d6bb00469db30a7b19649da3.tex b/sail_latex_riscv/fnzcap_to_integer_pcfb8f9e29d6bb00469db30a7b19649da3.tex new file mode 100644 index 00000000..a3fc82ec --- /dev/null +++ b/sail_latex_riscv/fnzcap_to_integer_pcfb8f9e29d6bb00469db30a7b19649da3.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzcapzytozyintegerzypc]{cap\_to\_integer\_pc}# (cap: Capability) -> xlenbits = { + if (#\hyperref[sailRISCVzhavezypcczyrelocation]{have\_pcc\_relocation}#()) then #\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(cap) else cap.address +} diff --git a/sail_latex_riscv/fnzcaptostring7067e2f1e90748309c77a5de3d661e3d.tex b/sail_latex_riscv/fnzcaptostring7067e2f1e90748309c77a5de3d661e3d.tex index 027c3c1e..7dc42b90 100644 --- a/sail_latex_riscv/fnzcaptostring7067e2f1e90748309c77a5de3d661e3d.tex +++ b/sail_latex_riscv/fnzcaptostring7067e2f1e90748309c77a5de3d661e3d.tex @@ -11,8 +11,8 @@ #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(#\hyperref[sailRISCVzBitStr]{BitStr}#(0b0 @ #\hyperref[sailRISCVzgetCapPerms]{getCapPerms}#(cap)), #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(" type:", #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(#\hyperref[sailRISCVzBitStr]{BitStr}#(otype64), - #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(" offset:", - #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(#\hyperref[sailRISCVzBitStr]{BitStr}#(#\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(cap)), + #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(" address:", + #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(#\hyperref[sailRISCVzBitStr]{BitStr}#(cap.address), #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(" base:", #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(#\hyperref[sailRISCVzBitStr]{BitStr}#(#\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(cap)), #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(" length:", len_str))))))))))))) diff --git a/sail_latex_riscv/fnzchecked_mem_write765e0693788c9f4b01c2243ece39909e.tex b/sail_latex_riscv/fnzchecked_mem_write765e0693788c9f4b01c2243ece39909e.tex index 33e547be..b86abb28 100644 --- a/sail_latex_riscv/fnzchecked_mem_write765e0693788c9f4b01c2243ece39909e.tex +++ b/sail_latex_riscv/fnzchecked_mem_write765e0693788c9f4b01c2243ece39909e.tex @@ -5,5 +5,5 @@ then match #\hyperref[sailRISCVzextzycheckzyphyszymemzywrite]{ext\_check\_phys\_mem\_write}# (wk, paddr, width, data, meta) { #\hyperref[sailRISCVzExtzyPhysAddrzyOK]{Ext\_PhysAddr\_OK}#() => #\hyperref[sailRISCVzphyszymemzywrite]{phys\_mem\_write}#(wk, paddr, width, data, meta), #\hyperref[sailRISCVzExtzyPhysAddrzyError]{Ext\_PhysAddr\_Error}#(e) => #\hyperref[sailRISCVzMemException]{MemException}#(e) - } + } else #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzySAMOzyAccesszyFault]{E\_SAMO\_Access\_Fault}#()) diff --git a/sail_latex_riscv/fnzddc_and_resulting_addr0f0e2d5c6123a71667b35ed17c44868e.tex b/sail_latex_riscv/fnzddc_and_resulting_addr0f0e2d5c6123a71667b35ed17c44868e.tex new file mode 100644 index 00000000..88e30b5d --- /dev/null +++ b/sail_latex_riscv/fnzddc_and_resulting_addr0f0e2d5c6123a71667b35ed17c44868e.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzddczyandzyresultingzyaddr]{ddc\_and\_resulting\_addr}# (addr) = { + let ddc_val = DDC in + (ddc_val, if (#\hyperref[sailRISCVzhavezyddczyrelocation]{have\_ddc\_relocation}#()) then ddc_val.address + addr else addr) +} diff --git a/sail_latex_riscv/fnzext_control_check_addr2d404fc3390578d569e3f547f0d18fce.tex b/sail_latex_riscv/fnzext_control_check_addr2d404fc3390578d569e3f547f0d18fce.tex index 7a0f0c65..622d5858 100644 --- a/sail_latex_riscv/fnzext_control_check_addr2d404fc3390578d569e3f547f0d18fce.tex +++ b/sail_latex_riscv/fnzext_control_check_addr2d404fc3390578d569e3f547f0d18fce.tex @@ -1,10 +1,10 @@ function #\hyperref[sailRISCVzextzycontrolzycheckzyaddr]{ext\_control\_check\_addr}#(pc : xlenbits) -> #\hyperref[sailRISCVzExtzyControlAddrzyCheck]{Ext\_ControlAddr\_Check}#(ext_control_addr_error) = { - let pcc_base = #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(PCC); /* We are given the addr without any bit[0] clearing, so the addition * below may include a set addr[0], and so the bounds checks should * be accurate. */ - let target : xlenbits = [pcc_base + pc with 0=bitzero]; + let pc = if #\hyperref[sailRISCVzhavezypcczyrelocation]{have\_pcc\_relocation}#() then #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(PCC) + pc else pc; + let target : xlenbits = [pc with 0=bitzero]; if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(PCC, target, #\hyperref[sailRISCVzminzyinstructionzybytes]{min\_instruction\_bytes}# ())) then #\hyperref[sailRISCVzExtzyControlAddrzyError]{Ext\_ControlAddr\_Error}#(CapEx_LengthViolation, PCC_IDX) else #\hyperref[sailRISCVzExtzyControlAddrzyOK]{Ext\_ControlAddr\_OK}#(target) diff --git a/sail_latex_riscv/fnzext_fail_xret_priva071b88d32f48ad8e720a4cae916da8b.tex b/sail_latex_riscv/fnzext_fail_xret_priva071b88d32f48ad8e720a4cae916da8b.tex index 1f69eb45..288256dd 100644 --- a/sail_latex_riscv/fnzext_fail_xret_priva071b88d32f48ad8e720a4cae916da8b.tex +++ b/sail_latex_riscv/fnzext_fail_xret_priva071b88d32f48ad8e720a4cae916da8b.tex @@ -1,2 +1,2 @@ -function #\hyperref[sailRISCVzextzyfailzyxretzypriv]{ext\_fail\_xret\_priv}# () : unit -> unit = +function #\hyperref[sailRISCVzextzyfailzyxretzypriv]{ext\_fail\_xret\_priv}# () : unit -> unit = #\hyperref[sailRISCVzhandlezycherizypcczyexception]{handle\_cheri\_pcc\_exception}#(CapEx_AccessSystemRegsViolation) diff --git a/sail_latex_riscv/fnzext_fetch_check_pc2e82f09c4f4da5465b70e5f9e6f48b77.tex b/sail_latex_riscv/fnzext_fetch_check_pc2e82f09c4f4da5465b70e5f9e6f48b77.tex index 66f9eb15..70c02ac9 100644 --- a/sail_latex_riscv/fnzext_fetch_check_pc2e82f09c4f4da5465b70e5f9e6f48b77.tex +++ b/sail_latex_riscv/fnzext_fetch_check_pc2e82f09c4f4da5465b70e5f9e6f48b77.tex @@ -1,7 +1,7 @@ function #\hyperref[sailRISCVzextzyfetchzycheckzypc]{ext\_fetch\_check\_pc}#(start_pc, pc) = { if start_pc == pc then { - pcc_base = #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(PCC); + let pcc_base = #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(PCC); /* We need to perform the permission checks only for the first granule. */ if #\hyperref[sailRISCVznot]{not}#(PCC.tag) then #\hyperref[sailRISCVzExtzyFetchAddrzyError]{Ext\_FetchAddr\_Error}#(CapEx_TagViolation) @@ -9,12 +9,12 @@ then #\hyperref[sailRISCVzExtzyFetchAddrzyError]{Ext\_FetchAddr\_Error}#(CapEx_SealViolation) else if #\hyperref[sailRISCVznot]{not}#(PCC.permit_execute) then #\hyperref[sailRISCVzExtzyFetchAddrzyError]{Ext\_FetchAddr\_Error}#(CapEx_PermitExecuteViolation) + /* If PCC relocation is enabled, require that PCC.base be as aligned as PC. + This is also enforced when setting PCC in most places. */ + else if #\hyperref[sailRISCVzhavezypcczyrelocation]{have\_pcc\_relocation}#() & (pcc_base[0] != bitzero | (pcc_base[1] != bitzero & ~(#\hyperref[sailRISCVzhaveRVC]{haveRVC}#()))) + then #\hyperref[sailRISCVzExtzyFetchAddrzyError]{Ext\_FetchAddr\_Error}#(CapEx_UnalignedBase) else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(PCC, pc, 2)) then #\hyperref[sailRISCVzExtzyFetchAddrzyError]{Ext\_FetchAddr\_Error}#(CapEx_LengthViolation) - /* Require that PCC.base be as aligned as PC. This - is also enforced when setting PCC in most places. */ - else if pcc_base[0] != bitzero | (pcc_base[1] != bitzero & ~(#\hyperref[sailRISCVzhaveRVC]{haveRVC}#())) - then #\hyperref[sailRISCVzExtzyFetchAddrzyError]{Ext\_FetchAddr\_Error}#(CapEx_UnalignedBase) else #\hyperref[sailRISCVzExtzyFetchAddrzyOK]{Ext\_FetchAddr\_OK}#(pc) } else { /* Perform only the bounds checks on the current granule, i.e. pc. */ diff --git a/sail_latex_riscv/fnzext_init_regs1d9ff00ce58fd5712eb26190e338015a.tex b/sail_latex_riscv/fnzext_init_regs1d9ff00ce58fd5712eb26190e338015a.tex index b7a535b4..f2e096de 100644 --- a/sail_latex_riscv/fnzext_init_regs1d9ff00ce58fd5712eb26190e338015a.tex +++ b/sail_latex_riscv/fnzext_init_regs1d9ff00ce58fd5712eb26190e338015a.tex @@ -51,10 +51,7 @@ x31 = null_cap; misa->#\hyperref[sailRISCVzX]{X}#() = 0b1; - mccsr->#\hyperref[sailRISCVzd]{d}#() = 0b1; - mccsr->#\hyperref[sailRISCVze]{e}#() = 0b1; - sccsr->#\hyperref[sailRISCVzd]{d}#() = 0b1; - sccsr->#\hyperref[sailRISCVze]{e}#() = 0b1; - uccsr->#\hyperref[sailRISCVzd]{d}#() = 0b1; - uccsr->#\hyperref[sailRISCVze]{e}#() = 0b1; + mccsr = #\hyperref[sailRISCVzlegalizzezyccsr]{legalize\_ccsr}#(mccsr, #\hyperref[sailRISCVzzzeros]{zeros}#()); + sccsr = #\hyperref[sailRISCVzlegalizzezyccsr]{legalize\_ccsr}#(sccsr, #\hyperref[sailRISCVzzzeros]{zeros}#()); + uccsr = #\hyperref[sailRISCVzlegalizzezyccsr]{legalize\_ccsr}#(uccsr, #\hyperref[sailRISCVzzzeros]{zeros}#()); } diff --git a/sail_latex_riscv/fnzext_initaf8e3807fa5c1bbef01331f40e0f99a4.tex b/sail_latex_riscv/fnzext_initaf8e3807fa5c1bbef01331f40e0f99a4.tex index 81b18d44..23cebfb6 100644 --- a/sail_latex_riscv/fnzext_initaf8e3807fa5c1bbef01331f40e0f99a4.tex +++ b/sail_latex_riscv/fnzext_initaf8e3807fa5c1bbef01331f40e0f99a4.tex @@ -1,9 +1,6 @@ function #\hyperref[sailRISCVzextzyinit]{ext\_init}# () = { misa->#\hyperref[sailRISCVzX]{X}#() = 0b1; - mccsr->#\hyperref[sailRISCVzd]{d}#() = 0b1; - mccsr->#\hyperref[sailRISCVze]{e}#() = 0b1; - sccsr->#\hyperref[sailRISCVzd]{d}#() = 0b1; - sccsr->#\hyperref[sailRISCVze]{e}#() = 0b1; - uccsr->#\hyperref[sailRISCVzd]{d}#() = 0b1; - uccsr->#\hyperref[sailRISCVze]{e}#() = 0b1; + mccsr = #\hyperref[sailRISCVzlegalizzezyccsr]{legalize\_ccsr}#(mccsr, #\hyperref[sailRISCVzzzeros]{zeros}#()); + sccsr = #\hyperref[sailRISCVzlegalizzezyccsr]{legalize\_ccsr}#(sccsr, #\hyperref[sailRISCVzzzeros]{zeros}#()); + uccsr = #\hyperref[sailRISCVzlegalizzezyccsr]{legalize\_ccsr}#(uccsr, #\hyperref[sailRISCVzzzeros]{zeros}#()); } diff --git a/sail_latex_riscv/fnzext_veto_disable_cd10c2d1c5077060fa007c1628d7aaa8c.tex b/sail_latex_riscv/fnzext_veto_disable_cd10c2d1c5077060fa007c1628d7aaa8c.tex index f0ef29ea..a8057b63 100644 --- a/sail_latex_riscv/fnzext_veto_disable_cd10c2d1c5077060fa007c1628d7aaa8c.tex +++ b/sail_latex_riscv/fnzext_veto_disable_cd10c2d1c5077060fa007c1628d7aaa8c.tex @@ -1 +1,5 @@ -function #\hyperref[sailRISCVzextzyvetozydisablezyC]{ext\_veto\_disable\_C}# () = #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(PCC)[1] == bitone +function #\hyperref[sailRISCVzextzyvetozydisablezyC]{ext\_veto\_disable\_C}# () = { + if #\hyperref[sailRISCVzhavezypcczyrelocation]{have\_pcc\_relocation}#() + then #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(PCC)[1] == bitone + else false +} diff --git a/sail_latex_riscv/fnzget_arch_pc874e1e50a5765cd3e317d37fa710a52d.tex b/sail_latex_riscv/fnzget_arch_pc874e1e50a5765cd3e317d37fa710a52d.tex index f906bff1..11760b78 100644 --- a/sail_latex_riscv/fnzget_arch_pc874e1e50a5765cd3e317d37fa710a52d.tex +++ b/sail_latex_riscv/fnzget_arch_pc874e1e50a5765cd3e317d37fa710a52d.tex @@ -1,2 +1,2 @@ function #\hyperref[sailRISCVzgetzyarchzypc]{get\_arch\_pc}# () = - PC - #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(PCC) + if #\hyperref[sailRISCVzhavezypcczyrelocation]{have\_pcc\_relocation}#() then PC - #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(PCC) else PC diff --git a/sail_latex_riscv/fnzget_cheri_mode_cap_addr267a231c94a9ae3cf08d67cb43590a2e.tex b/sail_latex_riscv/fnzget_cheri_mode_cap_addr267a231c94a9ae3cf08d67cb43590a2e.tex index 7a51dbf3..21087add 100644 --- a/sail_latex_riscv/fnzget_cheri_mode_cap_addr267a231c94a9ae3cf08d67cb43590a2e.tex +++ b/sail_latex_riscv/fnzget_cheri_mode_cap_addr267a231c94a9ae3cf08d67cb43590a2e.tex @@ -3,6 +3,6 @@ let base_cap = #\hyperref[sailRISCVzC]{C}#(base_reg) in (base_cap, base_cap.address + offset, 0b0 @ base_reg) else - let ddc = DDC in - (ddc, ddc.address + #\hyperref[sailRISCVzX]{X}#(base_reg) + offset, DDC_IDX); + let (ddc_val, addr) = #\hyperref[sailRISCVzddczyandzyresultingzyaddr]{ddc\_and\_resulting\_addr}#(#\hyperref[sailRISCVzX]{X}#(base_reg) + offset) in + (ddc_val, addr, DDC_IDX); } diff --git a/sail_latex_riscv/fnzget_mtvec134cdc828faab7bf9f19733fba43da2f.tex b/sail_latex_riscv/fnzget_mtvec134cdc828faab7bf9f19733fba43da2f.tex index b0b9f9c8..32198a24 100644 --- a/sail_latex_riscv/fnzget_mtvec134cdc828faab7bf9f19733fba43da2f.tex +++ b/sail_latex_riscv/fnzget_mtvec134cdc828faab7bf9f19733fba43da2f.tex @@ -1,2 +1,2 @@ function #\hyperref[sailRISCVzgetzymtvec]{get\_mtvec}#() -> xlenbits = - #\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(MTCC) + #\hyperref[sailRISCVzcapzytozyintegerzypc]{cap\_to\_integer\_pc}#(MTCC) diff --git a/sail_latex_riscv/fnzget_next_pc52098782da35f914abcd4b708363813b.tex b/sail_latex_riscv/fnzget_next_pc52098782da35f914abcd4b708363813b.tex index 3bdaf282..be272766 100644 --- a/sail_latex_riscv/fnzget_next_pc52098782da35f914abcd4b708363813b.tex +++ b/sail_latex_riscv/fnzget_next_pc52098782da35f914abcd4b708363813b.tex @@ -1,2 +1,2 @@ function #\hyperref[sailRISCVzgetzynextzypc]{get\_next\_pc}#() = - nextPC - #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(PCC) + if #\hyperref[sailRISCVzhavezypcczyrelocation]{have\_pcc\_relocation}#() then nextPC - #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(PCC) else nextPC diff --git a/sail_latex_riscv/fnzget_stvec8e871a236060976d6c548af2b67478db.tex b/sail_latex_riscv/fnzget_stvec8e871a236060976d6c548af2b67478db.tex index 7a46b46e..89d768fb 100644 --- a/sail_latex_riscv/fnzget_stvec8e871a236060976d6c548af2b67478db.tex +++ b/sail_latex_riscv/fnzget_stvec8e871a236060976d6c548af2b67478db.tex @@ -1,2 +1,2 @@ function #\hyperref[sailRISCVzgetzystvec]{get\_stvec}#() -> xlenbits = - #\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(STCC) + #\hyperref[sailRISCVzcapzytozyintegerzypc]{cap\_to\_integer\_pc}#(STCC) diff --git a/sail_latex_riscv/fnzget_utvec375b7b6fc923ff7174c10f9b93b1b2cf.tex b/sail_latex_riscv/fnzget_utvec375b7b6fc923ff7174c10f9b93b1b2cf.tex index 17ac50c4..34bb0abd 100644 --- a/sail_latex_riscv/fnzget_utvec375b7b6fc923ff7174c10f9b93b1b2cf.tex +++ b/sail_latex_riscv/fnzget_utvec375b7b6fc923ff7174c10f9b93b1b2cf.tex @@ -1,2 +1,2 @@ function #\hyperref[sailRISCVzgetzyutvec]{get\_utvec}#() -> xlenbits = - #\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(UTCC) + #\hyperref[sailRISCVzcapzytozyintegerzypc]{cap\_to\_integer\_pc}#(UTCC) diff --git a/sail_latex_riscv/fnzget_xret_target26ce66652c1cd67f2e91b685c1d44e62.tex b/sail_latex_riscv/fnzget_xret_target26ce66652c1cd67f2e91b685c1d44e62.tex index c1719457..7392abe1 100644 --- a/sail_latex_riscv/fnzget_xret_target26ce66652c1cd67f2e91b685c1d44e62.tex +++ b/sail_latex_riscv/fnzget_xret_target26ce66652c1cd67f2e91b685c1d44e62.tex @@ -4,5 +4,5 @@ Supervisor => SEPCC, User => UEPCC }; - #\hyperref[sailRISCVzlegalizzezyxepc]{legalize\_xepc}#(#\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(cap)) + #\hyperref[sailRISCVzlegalizzezyxepc]{legalize\_xepc}#(#\hyperref[sailRISCVzcapzytozyintegerzypc]{cap\_to\_integer\_pc}#(cap)) } diff --git a/sail_latex_riscv/fnzhandle_cheri_cap_exceptionc1ff083ca6d0a739fb48243e22ff4898.tex b/sail_latex_riscv/fnzhandle_cheri_cap_exceptionc1ff083ca6d0a739fb48243e22ff4898.tex index da1db904..cf29a328 100644 --- a/sail_latex_riscv/fnzhandle_cheri_cap_exceptionc1ff083ca6d0a739fb48243e22ff4898.tex +++ b/sail_latex_riscv/fnzhandle_cheri_cap_exceptionc1ff083ca6d0a739fb48243e22ff4898.tex @@ -1,6 +1,7 @@ function #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(capEx, regnum) = { - #\hyperref[sailRISCVzprint]{print}#("CHERI " ^ #\hyperref[sailRISCVzstringzyofzycapex]{string\_of\_capex}#(capEx) ^ " Reg=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(regnum)); + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("CHERI " ^ #\hyperref[sailRISCVzstringzyofzycapex]{string\_of\_capex}#(capEx) ^ " Reg=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(regnum)); let t : sync_exception = struct { trap = #\hyperref[sailRISCVzEzyExtension]{E\_Extension}#(EXC_CHERI), excinfo = #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(regnum @ #\hyperref[sailRISCVzCapExCode]{CapExCode}#(capEx)) : xlenbits), diff --git a/sail_latex_riscv/fnzhave_cheri_relocationbbe9a9f5c01227424d0cc8330de5d0b3.tex b/sail_latex_riscv/fnzhave_cheri_relocationbbe9a9f5c01227424d0cc8330de5d0b3.tex new file mode 100644 index 00000000..cdf581da --- /dev/null +++ b/sail_latex_riscv/fnzhave_cheri_relocationbbe9a9f5c01227424d0cc8330de5d0b3.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzhavezycherizyrelocation]{have\_cheri\_relocation}#() = false diff --git a/sail_latex_riscv/fnzhave_ddc_relocationcdaa2a12594a6d0db423bcedfc636210.tex b/sail_latex_riscv/fnzhave_ddc_relocationcdaa2a12594a6d0db423bcedfc636210.tex new file mode 100644 index 00000000..ec7ed276 --- /dev/null +++ b/sail_latex_riscv/fnzhave_ddc_relocationcdaa2a12594a6d0db423bcedfc636210.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzhavezyddczyrelocation]{have\_ddc\_relocation}#() = #\hyperref[sailRISCVzhavezycherizyrelocation]{have\_cheri\_relocation}#() diff --git a/sail_latex_riscv/fnzhave_pcc_relocation8ef276f0f56e5c3343729212dcd97cb5.tex b/sail_latex_riscv/fnzhave_pcc_relocation8ef276f0f56e5c3343729212dcd97cb5.tex new file mode 100644 index 00000000..ce99be35 --- /dev/null +++ b/sail_latex_riscv/fnzhave_pcc_relocation8ef276f0f56e5c3343729212dcd97cb5.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzhavezypcczyrelocation]{have\_pcc\_relocation}#() = #\hyperref[sailRISCVzhavezycherizyrelocation]{have\_cheri\_relocation}#() diff --git a/sail_latex_riscv/fnzhavezfa170943288777f725fbf88904d27d506e.tex b/sail_latex_riscv/fnzhavezfa170943288777f725fbf88904d27d506e.tex new file mode 100644 index 00000000..c2ac37bc --- /dev/null +++ b/sail_latex_riscv/fnzhavezfa170943288777f725fbf88904d27d506e.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzhaveZfa]{haveZfa}#() -> bool = true diff --git a/sail_latex_riscv/fnzhavezfhe5dbd348c0b6c69910aec2c1edb56adf.tex b/sail_latex_riscv/fnzhavezfhe5dbd348c0b6c69910aec2c1edb56adf.tex index 7922bc7a..7fd9dec2 100644 --- a/sail_latex_riscv/fnzhavezfhe5dbd348c0b6c69910aec2c1edb56adf.tex +++ b/sail_latex_riscv/fnzhavezfhe5dbd348c0b6c69910aec2c1edb56adf.tex @@ -1 +1 @@ -function #\hyperref[sailRISCVzhaveZfh]{haveZfh}#() -> bool = true +function #\hyperref[sailRISCVzhaveZfh]{haveZfh}#() -> bool = (misa.#\hyperref[sailRISCVzF]{F}#() == 0b1) & (mstatus.#\hyperref[sailRISCVzFS]{FS}#() != 0b00) diff --git a/sail_latex_riscv/fnzhavezicond942507aaca8f56a8d3fc5cd08536c028.tex b/sail_latex_riscv/fnzhavezicond942507aaca8f56a8d3fc5cd08536c028.tex new file mode 100644 index 00000000..d468518f --- /dev/null +++ b/sail_latex_riscv/fnzhavezicond942507aaca8f56a8d3fc5cd08536c028.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzhaveZicond]{haveZicond}#() -> bool = true diff --git a/sail_latex_riscv/fnzinit_sysc92898d1b2b72595dd36bce10e6a67fb.tex b/sail_latex_riscv/fnzinit_sysc92898d1b2b72595dd36bce10e6a67fb.tex index 02ec8362..4b9f298d 100644 --- a/sail_latex_riscv/fnzinit_sysc92898d1b2b72595dd36bce10e6a67fb.tex +++ b/sail_latex_riscv/fnzinit_sysc92898d1b2b72595dd36bce10e6a67fb.tex @@ -46,7 +46,7 @@ mcounteren->#\hyperref[sailRISCVzbits]{bits}#() = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0); minstret = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0); - minstret_written = false; + minstret_increment = true; #\hyperref[sailRISCVzinitzypmp]{init\_pmp}#(); diff --git a/sail_latex_riscv/fnzlegalizze_ccsr8248d36ab83d1808c1e3e0b64d88c1cf.tex b/sail_latex_riscv/fnzlegalizze_ccsr8248d36ab83d1808c1e3e0b64d88c1cf.tex index bf528757..ac3a8e7c 100644 --- a/sail_latex_riscv/fnzlegalizze_ccsr8248d36ab83d1808c1e3e0b64d88c1cf.tex +++ b/sail_latex_riscv/fnzlegalizze_ccsr8248d36ab83d1808c1e3e0b64d88c1cf.tex @@ -3,8 +3,10 @@ // Technically, WPRI does not need a legalizer, since software is // assumed to legalize; so we could remove this function. let v = #\hyperref[sailRISCVzMkzyccsr]{Mk\_ccsr}#(v); - /* For now these bits are not really supported so hardwired to true */ - let c = #\hyperref[sailRISCVzupdatezyd]{update\_d}#(c, 0b1); + /* For now the e bit is not really supported so hardwired to true */ let c = #\hyperref[sailRISCVzupdatezye]{update\_e}#(c, 0b1); + /* Read-only feature bits to allow for software to detect CHERI semantics. */ + let c = #\hyperref[sailRISCVzupdatezynr]{update\_nr}#(c, #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(#\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzhavezycherizyrelocation]{have\_cheri\_relocation}#()))); + let c = #\hyperref[sailRISCVzupdatezytc]{update\_tc}#(c, 0b1); c } diff --git a/sail_latex_riscv/fnzlegalizze_epccfd09ccf016c22f97fa9a6b5dfba65e84.tex b/sail_latex_riscv/fnzlegalizze_epccfd09ccf016c22f97fa9a6b5dfba65e84.tex index 6752cc9b..e1bdf7c8 100644 --- a/sail_latex_riscv/fnzlegalizze_epccfd09ccf016c22f97fa9a6b5dfba65e84.tex +++ b/sail_latex_riscv/fnzlegalizze_epccfd09ccf016c22f97fa9a6b5dfba65e84.tex @@ -1,8 +1,8 @@ function #\hyperref[sailRISCVzlegalizzezyepcc]{legalize\_epcc}# (v : Capability) -> Capability = { - let voffset = #\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(v); - let legalized = #\hyperref[sailRISCVzlegalizzezyxepc]{legalize\_xepc}#(voffset); + let int_val = #\hyperref[sailRISCVzcapzytozyintegerzypc]{cap\_to\_integer\_pc}#(v); + let legalized = #\hyperref[sailRISCVzlegalizzezyxepc]{legalize\_xepc}#(int_val); - if legalized == voffset + if legalized == int_val then v /* avoid possibly attempting to set the offset of a sentry */ - else #\hyperref[sailRISCVzsetCapOffsetChecked]{setCapOffsetChecked}#(v, legalized) + else #\hyperref[sailRISCVzupdatezycapzywithzyintegerzypc]{update\_cap\_with\_integer\_pc}#(v, legalized) } diff --git a/sail_latex_riscv/fnzlegalizze_tccfd2d2ccb3d791b05f6d62114b5036cb9.tex b/sail_latex_riscv/fnzlegalizze_tccfd2d2ccb3d791b05f6d62114b5036cb9.tex index 18deaa3a..46008be1 100644 --- a/sail_latex_riscv/fnzlegalizze_tccfd2d2ccb3d791b05f6d62114b5036cb9.tex +++ b/sail_latex_riscv/fnzlegalizze_tccfd2d2ccb3d791b05f6d62114b5036cb9.tex @@ -1,12 +1,12 @@ function #\hyperref[sailRISCVzlegalizzezytcc]{legalize\_tcc}#(o : Capability, v : Capability) -> Capability = { - new_base = #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(v); + let new_base = #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(v); /* Ignore writes that attempt to set unaligned TCC base */ - if new_base[0] != bitzero | new_base[1] != bitzero then + if #\hyperref[sailRISCVzhavezypcczyrelocation]{have\_pcc\_relocation}#() & (new_base[0] != bitzero | new_base[1] != bitzero) then o /* keep original TCC value */ else { - /* legalize new TCC #\hyperref[sailRISCVzoffset]{offset}# (RISC-V tvec) */ - new_tvec = v.address - new_base; - legalized_tvec = #\hyperref[sailRISCVzlegalizzezytvec]{legalize\_tvec}#(#\hyperref[sailRISCVzMkzyMtvec]{Mk\_Mtvec}#(#\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(o)), new_tvec); - #\hyperref[sailRISCVzsetCapOffsetChecked]{setCapOffsetChecked}#(v, legalized_tvec.#\hyperref[sailRISCVzbits]{bits}#()) + /* legalize new #\hyperref[sailRISCVzTCC]{TCC}# (RISC-V tvec) */ + let new_tvec = #\hyperref[sailRISCVzcapzytozyintegerzypc]{cap\_to\_integer\_pc}#(v); + let legalized_tvec = #\hyperref[sailRISCVzlegalizzezytvec]{legalize\_tvec}#(#\hyperref[sailRISCVzMkzyMtvec]{Mk\_Mtvec}#(#\hyperref[sailRISCVzcapzytozyintegerzypc]{cap\_to\_integer\_pc}#(o)), new_tvec); + #\hyperref[sailRISCVzupdatezycapzywithzyintegerzypc]{update\_cap\_with\_integer\_pc}#(v, legalized_tvec.#\hyperref[sailRISCVzbits]{bits}#()) } } diff --git a/sail_latex_riscv/fnzlegalizze_xepc8416dd9133f6232df0898ca0ae2784c2.tex b/sail_latex_riscv/fnzlegalizze_xepc8416dd9133f6232df0898ca0ae2784c2.tex index 8404292d..e09b62bf 100644 --- a/sail_latex_riscv/fnzlegalizze_xepc8416dd9133f6232df0898ca0ae2784c2.tex +++ b/sail_latex_riscv/fnzlegalizze_xepc8416dd9133f6232df0898ca0ae2784c2.tex @@ -1,5 +1,5 @@ function #\hyperref[sailRISCVzlegalizzezyxepc]{legalize\_xepc}#(v : xlenbits) -> xlenbits = - /* allow writing xepc[1] only if misa.C is enabled or could be enabled + /* allow writing xepc[1] only if misa.C is enabled or could be enabled XXX specification says this legalization should be done on read */ if (#\hyperref[sailRISCVzsyszyenablezywritablezymisa]{sys\_enable\_writable\_misa}#() & #\hyperref[sailRISCVzsyszyenablezyrvc]{sys\_enable\_rvc}#()) | misa.#\hyperref[sailRISCVzC]{C}#() == 0b1 then [v with 0 = bitzero] diff --git a/sail_latex_riscv/fnzmem_write_value_priv_meta8704060509807d04b1fcb48d80cdcd15.tex b/sail_latex_riscv/fnzmem_write_value_priv_meta8704060509807d04b1fcb48d80cdcd15.tex index a21bd042..e839165d 100644 --- a/sail_latex_riscv/fnzmem_write_value_priv_meta8704060509807d04b1fcb48d80cdcd15.tex +++ b/sail_latex_riscv/fnzmem_write_value_priv_meta8704060509807d04b1fcb48d80cdcd15.tex @@ -1,5 +1,4 @@ function #\hyperref[sailRISCVzmemzywritezyvaluezyprivzymeta]{mem\_write\_value\_priv\_meta}# (paddr, width, value, typ, priv, meta, aq, rl, con) = { - #\hyperref[sailRISCVzrvfizywrite]{rvfi\_write}#(paddr, width, value, meta); if (rl | con) & #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVziszyalignedzyaddr]{is\_aligned\_addr}#(paddr, width)) then #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzySAMOzyAddrzyAlign]{E\_SAMO\_Addr\_Align}#()) else { @@ -14,6 +13,8 @@ (true, false, false) => throw(#\hyperref[sailRISCVzErrorzynotzyimplemented]{Error\_not\_implemented}#("store.aq")), (true, false, true) => throw(#\hyperref[sailRISCVzErrorzynotzyimplemented]{Error\_not\_implemented}#("sc.aq")) }; - #\hyperref[sailRISCVzpmpzymemzywrite]{pmp\_mem\_write}#(wk, paddr, width, value, typ, priv, meta); + let result = #\hyperref[sailRISCVzpmpzymemzywrite]{pmp\_mem\_write}#(wk, paddr, width, value, typ, priv, meta); + #\hyperref[sailRISCVzrvfizywrite]{rvfi\_write}#(paddr, width, value, meta, result); + result } } diff --git a/sail_latex_riscv/fnznum_of_zzicondop3e6d4701d8934768c6aaf82a93f9c62d.tex b/sail_latex_riscv/fnznum_of_zzicondop3e6d4701d8934768c6aaf82a93f9c62d.tex new file mode 100644 index 00000000..d51ee6c4 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_zzicondop3e6d4701d8934768c6aaf82a93f9c62d.tex @@ -0,0 +1,4 @@ +function num_of_zicondop arg# = match arg# { + RISCV_CZERO_EQZ => 0, + RISCV_CZERO_NEZ => 1 +} diff --git a/sail_latex_riscv/fnzphys_mem_writefae7815adda192bed56129eba4b7bb01.tex b/sail_latex_riscv/fnzphys_mem_writefae7815adda192bed56129eba4b7bb01.tex index 568a611b..938852bb 100644 --- a/sail_latex_riscv/fnzphys_mem_writefae7815adda192bed56129eba4b7bb01.tex +++ b/sail_latex_riscv/fnzphys_mem_writefae7815adda192bed56129eba4b7bb01.tex @@ -1,5 +1,4 @@ function phys_mem_write forall 'n, 0 < 'n <= max_mem_access . (wk : write_kind, paddr : xlenbits, width : atom('n), data : #\hyperref[sailRISCVzbits]{bits}#(8 * 'n), meta : mem_meta) -> #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(bool) = { - #\hyperref[sailRISCVzrvfizywrite]{rvfi\_write}#(paddr, width, data, meta); let result = #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzwritezyram]{write\_ram}#(wk, paddr, width, data, meta)); if #\hyperref[sailRISCVzgetzyconfigzyprintzymem]{get\_config\_print\_mem}#() then #\hyperref[sailRISCVzprintzymem]{print\_mem}#("mem[" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(paddr) ^ "] <- " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(data)); diff --git a/sail_latex_riscv/fnzpmpmatchaddr4db797384cb60b665d5b05ce2f54ea2f.tex b/sail_latex_riscv/fnzpmpmatchaddr4db797384cb60b665d5b05ce2f54ea2f.tex index cb197d11..06a1623c 100644 --- a/sail_latex_riscv/fnzpmpmatchaddr4db797384cb60b665d5b05ce2f54ea2f.tex +++ b/sail_latex_riscv/fnzpmpmatchaddr4db797384cb60b665d5b05ce2f54ea2f.tex @@ -1,7 +1,7 @@ function #\hyperref[sailRISCVzpmpMatchAddr]{pmpMatchAddr}#(addr: xlenbits, width: xlenbits, rng: pmp_addr_range) -> pmpAddrMatch = { match rng { #\hyperref[sailRISCVzNone]{None}#() => PMP_NoMatch, - #\hyperref[sailRISCVzSome]{Some}#((lo, hi)) => if hi <_u lo /* to handle mis-configuration */ + #\hyperref[sailRISCVzSome]{Some}#((lo, hi)) => if hi <=_u lo /* to handle mis-configuration */ then PMP_NoMatch else { if (addr + width <=_u lo) | (hi <=_u addr) diff --git a/sail_latex_riscv/fnzprepare_trap_vector90a104f40adfa987d74a613f4061790f.tex b/sail_latex_riscv/fnzprepare_trap_vector90a104f40adfa987d74a613f4061790f.tex index 80254c4d..85eab7ea 100644 --- a/sail_latex_riscv/fnzprepare_trap_vector90a104f40adfa987d74a613f4061790f.tex +++ b/sail_latex_riscv/fnzprepare_trap_vector90a104f40adfa987d74a613f4061790f.tex @@ -6,9 +6,9 @@ }; /* NB we use address, not offset here because even though tvec is the offset - we want the absolute address to insert in PC. The bottom two #\hyperref[sailRISCVzbits]{bits}# (mode) should + we want the absolute address to insert in PC. The bottom two #\hyperref[sailRISCVzbits]{bits}# (mode) should be the same because we enforce aligned tcc base. */ - match #\hyperref[sailRISCVztveczyaddr]{tvec\_addr}#(#\hyperref[sailRISCVzMkzyMtvec]{Mk\_Mtvec}#(tcc.address), c) { + match #\hyperref[sailRISCVztveczyaddr]{tvec\_addr}#(#\hyperref[sailRISCVzMkzyMtvec]{Mk\_Mtvec}#(tcc.address), c) { #\hyperref[sailRISCVzSome]{Some}#(addr) => { nextPCC = tcc; addr }, #\hyperref[sailRISCVzNone]{None}#() => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#(__FILE__, __LINE__, "Invalid tvec mode") } diff --git a/sail_latex_riscv/fnzretire_instructionc9e2e6b25fd8f4e5a96cd82a0dd2a675.tex b/sail_latex_riscv/fnzretire_instructionc9e2e6b25fd8f4e5a96cd82a0dd2a675.tex index 13164a02..03834453 100644 --- a/sail_latex_riscv/fnzretire_instructionc9e2e6b25fd8f4e5a96cd82a0dd2a675.tex +++ b/sail_latex_riscv/fnzretire_instructionc9e2e6b25fd8f4e5a96cd82a0dd2a675.tex @@ -1,6 +1,3 @@ function #\hyperref[sailRISCVzretirezyinstruction]{retire\_instruction}#() -> unit = { - if minstret_written == true - then minstret_written = false - else if mcountinhibit.#\hyperref[sailRISCVzIR]{IR}#() == 0b0 - then minstret = minstret + 1 + if minstret_increment then minstret = minstret + 1; } diff --git a/sail_latex_riscv/fnzrf_d29c6729673402bec577925987b943174.tex b/sail_latex_riscv/fnzrf_d29c6729673402bec577925987b943174.tex new file mode 100644 index 00000000..fb0355ae --- /dev/null +++ b/sail_latex_riscv/fnzrf_d29c6729673402bec577925987b943174.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzrFzyD]{rF\_D}#(i) = { + assert(sizeof(flen) >= 64); + assert(#\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#() & #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzsyszyenablezyzzfinx]{sys\_enable\_zfinx}#())); + #\hyperref[sailRISCVzF]{F}#(i) +} diff --git a/sail_latex_riscv/fnzrf_hf87446c77cdaf455431ea51fc65d658a.tex b/sail_latex_riscv/fnzrf_hf87446c77cdaf455431ea51fc65d658a.tex new file mode 100644 index 00000000..c749c2f5 --- /dev/null +++ b/sail_latex_riscv/fnzrf_hf87446c77cdaf455431ea51fc65d658a.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzrFzyH]{rF\_H}#(i) = { + assert(sizeof(flen) >= 16); + assert(#\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#() & #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzsyszyenablezyzzfinx]{sys\_enable\_zfinx}#())); + #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}#(#\hyperref[sailRISCVzF]{F}#(i)) +} diff --git a/sail_latex_riscv/fnzrf_or_x_dd8e1de53f90a8fbd075b7f3c46756ac0.tex b/sail_latex_riscv/fnzrf_or_x_dd8e1de53f90a8fbd075b7f3c46756ac0.tex index a5db87c3..dfef091b 100644 --- a/sail_latex_riscv/fnzrf_or_x_dd8e1de53f90a8fbd075b7f3c46756ac0.tex +++ b/sail_latex_riscv/fnzrf_or_x_dd8e1de53f90a8fbd075b7f3c46756ac0.tex @@ -2,7 +2,7 @@ assert(sizeof(flen) >= 64); assert(#\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#() != #\hyperref[sailRISCVzsyszyenablezyzzfinx]{sys\_enable\_zfinx}#()); if #\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#() - then #\hyperref[sailRISCVzF]{F}#(#\hyperref[sailRISCVzunsigned]{unsigned}#(i)) + then #\hyperref[sailRISCVzFzyD]{F\_D}#(i) else if sizeof(xlen) >= 64 then #\hyperref[sailRISCVzX]{X}#(i)[63..0] else { diff --git a/sail_latex_riscv/fnzrf_or_x_hd96ee68afa00d1a1a16a94c3a6ff0e02.tex b/sail_latex_riscv/fnzrf_or_x_hd96ee68afa00d1a1a16a94c3a6ff0e02.tex index a73e4fa8..7f27b63a 100644 --- a/sail_latex_riscv/fnzrf_or_x_hd96ee68afa00d1a1a16a94c3a6ff0e02.tex +++ b/sail_latex_riscv/fnzrf_or_x_hd96ee68afa00d1a1a16a94c3a6ff0e02.tex @@ -2,6 +2,6 @@ assert(sizeof(flen) >= 16); assert(#\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#() != #\hyperref[sailRISCVzsyszyenablezyzzfinx]{sys\_enable\_zfinx}#()); if #\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#() - then #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}#(#\hyperref[sailRISCVzF]{F}#(i)) + then #\hyperref[sailRISCVzFzyH]{F\_H}#(i) else #\hyperref[sailRISCVzX]{X}#(i)[15..0] } diff --git a/sail_latex_riscv/fnzrf_or_x_s3a35ce7506a4fa509fd34496e2dbefd3.tex b/sail_latex_riscv/fnzrf_or_x_s3a35ce7506a4fa509fd34496e2dbefd3.tex index 747a34b3..58b43088 100644 --- a/sail_latex_riscv/fnzrf_or_x_s3a35ce7506a4fa509fd34496e2dbefd3.tex +++ b/sail_latex_riscv/fnzrf_or_x_s3a35ce7506a4fa509fd34496e2dbefd3.tex @@ -2,6 +2,6 @@ assert(sizeof(flen) >= 32); assert(#\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#() != #\hyperref[sailRISCVzsyszyenablezyzzfinx]{sys\_enable\_zfinx}#()); if #\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#() - then #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}#(#\hyperref[sailRISCVzF]{F}#(i)) + then #\hyperref[sailRISCVzFzyS]{F\_S}#(i) else #\hyperref[sailRISCVzX]{X}#(i)[31..0] } diff --git a/sail_latex_riscv/fnzrf_sae821dae13888ed4dd6a166d80f9c14c.tex b/sail_latex_riscv/fnzrf_sae821dae13888ed4dd6a166d80f9c14c.tex new file mode 100644 index 00000000..00e3615c --- /dev/null +++ b/sail_latex_riscv/fnzrf_sae821dae13888ed4dd6a166d80f9c14c.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzrFzyS]{rF\_S}#(i) = { + assert(sizeof(flen) >= 32); + assert(#\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#() & #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzsyszyenablezyzzfinx]{sys\_enable\_zfinx}#())); + #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}#(#\hyperref[sailRISCVzF]{F}#(i)) +} diff --git a/sail_latex_riscv/fnzriscv_f16le_quiet8f63ce7ff3e42871a470478ce69c31a9.tex b/sail_latex_riscv/fnzriscv_f16le_quiet8f63ce7ff3e42871a470478ce69c31a9.tex new file mode 100644 index 00000000..d3b167b5 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f16le_quiet8f63ce7ff3e42871a470478ce69c31a9.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf16Lezyquiet]{riscv\_f16Le\_quiet}# (v1, v2) = { + #\hyperref[sailRISCVzexternzyf16Lezyquiet]{extern\_f16Le\_quiet}#(v1, v2); + (float_fflags[4 .. 0], #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(float_result[0])) +} diff --git a/sail_latex_riscv/fnzriscv_f16lt_quiet244f6ba5b2310a0cac1e04951f6afb9c.tex b/sail_latex_riscv/fnzriscv_f16lt_quiet244f6ba5b2310a0cac1e04951f6afb9c.tex new file mode 100644 index 00000000..401bb859 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f16lt_quiet244f6ba5b2310a0cac1e04951f6afb9c.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf16Ltzyquiet]{riscv\_f16Lt\_quiet}# (v1, v2) = { + #\hyperref[sailRISCVzexternzyf16Ltzyquiet]{extern\_f16Lt\_quiet}#(v1, v2); + (float_fflags[4 .. 0], #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(float_result[0])) +} diff --git a/sail_latex_riscv/fnzriscv_f16roundtoint52329eb13a3e4a06c8e70e0c4ef36e80.tex b/sail_latex_riscv/fnzriscv_f16roundtoint52329eb13a3e4a06c8e70e0c4ef36e80.tex new file mode 100644 index 00000000..8061eb04 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f16roundtoint52329eb13a3e4a06c8e70e0c4ef36e80.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf16roundToInt]{riscv\_f16roundToInt}# (rm, v, exact) = { + #\hyperref[sailRISCVzexternzyf16roundToInt]{extern\_f16roundToInt}#(rm, v, exact); + (float_fflags[4 .. 0], float_result[15 .. 0]) +} diff --git a/sail_latex_riscv/fnzriscv_f32le_quiet7e5f820135a916f973026964c0ce90bf.tex b/sail_latex_riscv/fnzriscv_f32le_quiet7e5f820135a916f973026964c0ce90bf.tex new file mode 100644 index 00000000..bc6504cc --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f32le_quiet7e5f820135a916f973026964c0ce90bf.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf32Lezyquiet]{riscv\_f32Le\_quiet}# (v1, v2) = { + #\hyperref[sailRISCVzexternzyf32Lezyquiet]{extern\_f32Le\_quiet}#(v1, v2); + (float_fflags[4 .. 0], #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(float_result[0])) +} diff --git a/sail_latex_riscv/fnzriscv_f32lt_quiet6805f79a39a589997e0e972ca2f211be.tex b/sail_latex_riscv/fnzriscv_f32lt_quiet6805f79a39a589997e0e972ca2f211be.tex new file mode 100644 index 00000000..10ba71af --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f32lt_quiet6805f79a39a589997e0e972ca2f211be.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf32Ltzyquiet]{riscv\_f32Lt\_quiet}# (v1, v2) = { + #\hyperref[sailRISCVzexternzyf32Ltzyquiet]{extern\_f32Lt\_quiet}#(v1, v2); + (float_fflags[4 .. 0], #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(float_result[0])) +} diff --git a/sail_latex_riscv/fnzriscv_f32roundtoint33ebf4ca80343b549f0b5a1c93805348.tex b/sail_latex_riscv/fnzriscv_f32roundtoint33ebf4ca80343b549f0b5a1c93805348.tex new file mode 100644 index 00000000..bf5bfccb --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f32roundtoint33ebf4ca80343b549f0b5a1c93805348.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf32roundToInt]{riscv\_f32roundToInt}# (rm, v, exact) = { + #\hyperref[sailRISCVzexternzyf32roundToInt]{extern\_f32roundToInt}#(rm, v, exact); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} diff --git a/sail_latex_riscv/fnzriscv_f64le_quietdbcd45688456ae3af8949c7df7db62f7.tex b/sail_latex_riscv/fnzriscv_f64le_quietdbcd45688456ae3af8949c7df7db62f7.tex new file mode 100644 index 00000000..10c278f3 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f64le_quietdbcd45688456ae3af8949c7df7db62f7.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf64Lezyquiet]{riscv\_f64Le\_quiet}# (v1, v2) = { + #\hyperref[sailRISCVzexternzyf64Lezyquiet]{extern\_f64Le\_quiet}#(v1, v2); + (float_fflags[4 .. 0], #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(float_result[0])) +} diff --git a/sail_latex_riscv/fnzriscv_f64lt_quiet14ab1c593c5d6a2b683a6949da76b09d.tex b/sail_latex_riscv/fnzriscv_f64lt_quiet14ab1c593c5d6a2b683a6949da76b09d.tex new file mode 100644 index 00000000..9a51c5fa --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f64lt_quiet14ab1c593c5d6a2b683a6949da76b09d.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf64Ltzyquiet]{riscv\_f64Lt\_quiet}# (v1, v2) = { + #\hyperref[sailRISCVzexternzyf64Ltzyquiet]{extern\_f64Lt\_quiet}#(v1, v2); + (float_fflags[4 .. 0], #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(float_result[0])) +} diff --git a/sail_latex_riscv/fnzriscv_f64roundtointc621d19070f8cdbcc8f4378ba7716a84.tex b/sail_latex_riscv/fnzriscv_f64roundtointc621d19070f8cdbcc8f4378ba7716a84.tex new file mode 100644 index 00000000..57152eee --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f64roundtointc621d19070f8cdbcc8f4378ba7716a84.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf64roundToInt]{riscv\_f64roundToInt}# (rm, v, exact) = { + #\hyperref[sailRISCVzexternzyf64roundToInt]{extern\_f64roundToInt}#(rm, v, exact); + (float_fflags[4 .. 0], float_result) +} diff --git a/sail_latex_riscv/fnzrvfi_write8e76a07b5a6f2a7b76947099108996b1.tex b/sail_latex_riscv/fnzrvfi_write8e76a07b5a6f2a7b76947099108996b1.tex index 22c4515d..d860d40a 100644 --- a/sail_latex_riscv/fnzrvfi_write8e76a07b5a6f2a7b76947099108996b1.tex +++ b/sail_latex_riscv/fnzrvfi_write8e76a07b5a6f2a7b76947099108996b1.tex @@ -1 +1 @@ -function #\hyperref[sailRISCVzrvfizywrite]{rvfi\_write}# (addr, width, value, meta) = () +function #\hyperref[sailRISCVzrvfizywrite]{rvfi\_write}# (addr, width, value, meta, result) = () diff --git a/sail_latex_riscv/fnzset_mtvec628ceb1975fa7b69631fcc224f1bbbc0.tex b/sail_latex_riscv/fnzset_mtvec628ceb1975fa7b69631fcc224f1bbbc0.tex index 67d2649c..363ad790 100644 --- a/sail_latex_riscv/fnzset_mtvec628ceb1975fa7b69631fcc224f1bbbc0.tex +++ b/sail_latex_riscv/fnzset_mtvec628ceb1975fa7b69631fcc224f1bbbc0.tex @@ -1,5 +1,5 @@ function #\hyperref[sailRISCVzsetzymtvec]{set\_mtvec}#(value : xlenbits) -> xlenbits = { - let mtv = #\hyperref[sailRISCVzlegalizzezytvec]{legalize\_tvec}#(#\hyperref[sailRISCVzMkzyMtvec]{Mk\_Mtvec}#(#\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(MTCC)), value); - MTCC = #\hyperref[sailRISCVzsetCapOffsetChecked]{setCapOffsetChecked}#(MTCC, mtv.#\hyperref[sailRISCVzbits]{bits}#()); + let mtv = #\hyperref[sailRISCVzlegalizzezytvec]{legalize\_tvec}#(#\hyperref[sailRISCVzMkzyMtvec]{Mk\_Mtvec}#(#\hyperref[sailRISCVzcapzytozyintegerzypc]{cap\_to\_integer\_pc}#(MTCC)), value); + MTCC = #\hyperref[sailRISCVzupdatezycapzywithzyintegerzypc]{update\_cap\_with\_integer\_pc}#(MTCC, mtv.#\hyperref[sailRISCVzbits]{bits}#()); mtv.#\hyperref[sailRISCVzbits]{bits}#() } diff --git a/sail_latex_riscv/fnzset_stvec0d8dcc20a4d9dd912d52b9252d2370a7.tex b/sail_latex_riscv/fnzset_stvec0d8dcc20a4d9dd912d52b9252d2370a7.tex index b5e5cbd2..31ed7b23 100644 --- a/sail_latex_riscv/fnzset_stvec0d8dcc20a4d9dd912d52b9252d2370a7.tex +++ b/sail_latex_riscv/fnzset_stvec0d8dcc20a4d9dd912d52b9252d2370a7.tex @@ -1,5 +1,5 @@ function #\hyperref[sailRISCVzsetzystvec]{set\_stvec}#(value : xlenbits) -> xlenbits = { - let stv = #\hyperref[sailRISCVzlegalizzezytvec]{legalize\_tvec}#(#\hyperref[sailRISCVzMkzyMtvec]{Mk\_Mtvec}#(#\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(STCC)), value); - STCC = #\hyperref[sailRISCVzsetCapOffsetChecked]{setCapOffsetChecked}#(STCC, stv.#\hyperref[sailRISCVzbits]{bits}#()); + let stv = #\hyperref[sailRISCVzlegalizzezytvec]{legalize\_tvec}#(#\hyperref[sailRISCVzMkzyMtvec]{Mk\_Mtvec}#(#\hyperref[sailRISCVzcapzytozyintegerzypc]{cap\_to\_integer\_pc}#(STCC)), value); + STCC = #\hyperref[sailRISCVzupdatezycapzywithzyintegerzypc]{update\_cap\_with\_integer\_pc}#(STCC, stv.#\hyperref[sailRISCVzbits]{bits}#()); stv.#\hyperref[sailRISCVzbits]{bits}#() } diff --git a/sail_latex_riscv/fnzset_utvec4e028b19c2b4db0c1c1a0a48f1c4a330.tex b/sail_latex_riscv/fnzset_utvec4e028b19c2b4db0c1c1a0a48f1c4a330.tex index fe1c907a..b2598e57 100644 --- a/sail_latex_riscv/fnzset_utvec4e028b19c2b4db0c1c1a0a48f1c4a330.tex +++ b/sail_latex_riscv/fnzset_utvec4e028b19c2b4db0c1c1a0a48f1c4a330.tex @@ -1,5 +1,5 @@ function #\hyperref[sailRISCVzsetzyutvec]{set\_utvec}#(value : xlenbits) -> xlenbits = { - let utv = #\hyperref[sailRISCVzlegalizzezytvec]{legalize\_tvec}#(#\hyperref[sailRISCVzMkzyMtvec]{Mk\_Mtvec}#(#\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(UTCC)), value); - UTCC = #\hyperref[sailRISCVzsetCapOffsetChecked]{setCapOffsetChecked}#(UTCC, utv.#\hyperref[sailRISCVzbits]{bits}#()); + let utv = #\hyperref[sailRISCVzlegalizzezytvec]{legalize\_tvec}#(#\hyperref[sailRISCVzMkzyMtvec]{Mk\_Mtvec}#(#\hyperref[sailRISCVzcapzytozyintegerzypc]{cap\_to\_integer\_pc}#(UTCC)), value); + UTCC = #\hyperref[sailRISCVzupdatezycapzywithzyintegerzypc]{update\_cap\_with\_integer\_pc}#(UTCC, utv.#\hyperref[sailRISCVzbits]{bits}#()); utv.#\hyperref[sailRISCVzbits]{bits}#() } diff --git a/sail_latex_riscv/fnzset_xret_target81095db6e6bb6da6b746ed406dccd45e.tex b/sail_latex_riscv/fnzset_xret_target81095db6e6bb6da6b746ed406dccd45e.tex index c7703927..93537c03 100644 --- a/sail_latex_riscv/fnzset_xret_target81095db6e6bb6da6b746ed406dccd45e.tex +++ b/sail_latex_riscv/fnzset_xret_target81095db6e6bb6da6b746ed406dccd45e.tex @@ -1,8 +1,8 @@ function #\hyperref[sailRISCVzsetzyxretzytarget]{set\_xret\_target}#(p, value) = { match p { - Machine => MEPCC = #\hyperref[sailRISCVzsetCapOffsetChecked]{setCapOffsetChecked}#(MEPCC, value), - Supervisor => SEPCC = #\hyperref[sailRISCVzsetCapOffsetChecked]{setCapOffsetChecked}#(SEPCC, value), - User => UEPCC = #\hyperref[sailRISCVzsetCapOffsetChecked]{setCapOffsetChecked}#(UEPCC, value) + Machine => MEPCC = #\hyperref[sailRISCVzupdatezycapzywithzyintegerzypc]{update\_cap\_with\_integer\_pc}#(MEPCC, value), + Supervisor => SEPCC = #\hyperref[sailRISCVzupdatezycapzywithzyintegerzypc]{update\_cap\_with\_integer\_pc}#(SEPCC, value), + User => UEPCC = #\hyperref[sailRISCVzupdatezycapzywithzyintegerzypc]{update\_cap\_with\_integer\_pc}#(UEPCC, value) }; value } diff --git a/sail_latex_riscv/fnzsetcapaddrchecked02f3e6fc454faf7b488ed3661fb1a85e.tex b/sail_latex_riscv/fnzsetcapaddrchecked02f3e6fc454faf7b488ed3661fb1a85e.tex new file mode 100644 index 00000000..54446f64 --- /dev/null +++ b/sail_latex_riscv/fnzsetcapaddrchecked02f3e6fc454faf7b488ed3661fb1a85e.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzsetCapAddrChecked]{setCapAddrChecked}#(c, addr) : (Capability, CapAddrBits) -> Capability = + let (representable, newCap) = #\hyperref[sailRISCVzsetCapAddr]{setCapAddr}#(c, addr) in + #\hyperref[sailRISCVzclearTagIf]{clearTagIf}#(newCap, #\hyperref[sailRISCVznot]{not}#(representable) | #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(c)) diff --git a/sail_latex_riscv/fnzstepb001f84c8bf78b78b44b98d2b7f1f7d7.tex b/sail_latex_riscv/fnzstepb001f84c8bf78b78b44b98d2b7f1f7d7.tex index 980eeb8d..4b103602 100644 --- a/sail_latex_riscv/fnzstepb001f84c8bf78b78b44b98d2b7f1f7d7.tex +++ b/sail_latex_riscv/fnzstepb001f84c8bf78b78b44b98d2b7f1f7d7.tex @@ -2,7 +2,16 @@ /* for step extensions */ #\hyperref[sailRISCVzextzyprezystepzyhook]{ext\_pre\_step\_hook}#(); - minstret_written = false; /* see note for minstret */ + /* + * This records whether or not minstret should be incremented when + * the instruction is retired. Since retirement occurs before CSR + * writes we initialise it based on mcountinhibit here, before it is + * potentially changed. This is also set to false if minstret is + * written. See the note near the minstret declaration for more + * information. + */ + minstret_increment = mcountinhibit.#\hyperref[sailRISCVzIR]{IR}#() == 0b0; + let (retired, stepped) : (Retired, bool) = match #\hyperref[sailRISCVzdispatchInterrupt]{dispatchInterrupt}#(cur_privilege) { #\hyperref[sailRISCVzSome]{Some}#(intr, priv) => { diff --git a/sail_latex_riscv/fnzupdate_cap_with_integer_pc9c66feb4cf9d3f64ba301705bf4cece5.tex b/sail_latex_riscv/fnzupdate_cap_with_integer_pc9c66feb4cf9d3f64ba301705bf4cece5.tex new file mode 100644 index 00000000..b75da80e --- /dev/null +++ b/sail_latex_riscv/fnzupdate_cap_with_integer_pc9c66feb4cf9d3f64ba301705bf4cece5.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzupdatezycapzywithzyintegerzypc]{update\_cap\_with\_integer\_pc}# (cap: Capability, pc: xlenbits) -> Capability = { + if (#\hyperref[sailRISCVzhavezypcczyrelocation]{have\_pcc\_relocation}#()) then #\hyperref[sailRISCVzsetCapOffsetChecked]{setCapOffsetChecked}#(cap, pc) else #\hyperref[sailRISCVzsetCapAddrChecked]{setCapAddrChecked}#(cap, pc) +} diff --git a/sail_latex_riscv/fnzwf_d94c91aff56d9566b109d96edd2d1663f.tex b/sail_latex_riscv/fnzwf_d94c91aff56d9566b109d96edd2d1663f.tex new file mode 100644 index 00000000..60eacbfc --- /dev/null +++ b/sail_latex_riscv/fnzwf_d94c91aff56d9566b109d96edd2d1663f.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzwFzyD]{wF\_D}#(i, data) = { + assert(sizeof(flen) >= 64); + assert(#\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#() & #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzsyszyenablezyzzfinx]{sys\_enable\_zfinx}#())); + #\hyperref[sailRISCVzF]{F}#(i) = data +} diff --git a/sail_latex_riscv/fnzwf_hb915a10402ec9321c4ad1188ae0afc9f.tex b/sail_latex_riscv/fnzwf_hb915a10402ec9321c4ad1188ae0afc9f.tex new file mode 100644 index 00000000..a2db8ffd --- /dev/null +++ b/sail_latex_riscv/fnzwf_hb915a10402ec9321c4ad1188ae0afc9f.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzwFzyH]{wF\_H}#(i, data) = { + assert(sizeof(flen) >= 16); + assert(#\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#() & #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzsyszyenablezyzzfinx]{sys\_enable\_zfinx}#())); + #\hyperref[sailRISCVzF]{F}#(i) = #\hyperref[sailRISCVznanzybox]{nan\_box}#(data) +} diff --git a/sail_latex_riscv/fnzwf_or_x_d99d1bec09a43ea1c3cba945cc2ebd80e.tex b/sail_latex_riscv/fnzwf_or_x_d99d1bec09a43ea1c3cba945cc2ebd80e.tex index 3ffc3a5f..5e77603b 100644 --- a/sail_latex_riscv/fnzwf_or_x_d99d1bec09a43ea1c3cba945cc2ebd80e.tex +++ b/sail_latex_riscv/fnzwf_or_x_d99d1bec09a43ea1c3cba945cc2ebd80e.tex @@ -2,7 +2,7 @@ assert (sizeof(flen) >= 64); assert(#\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#() != #\hyperref[sailRISCVzsyszyenablezyzzfinx]{sys\_enable\_zfinx}#()); if #\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#() - then #\hyperref[sailRISCVzF]{F}#(i) = data + then #\hyperref[sailRISCVzFzyD]{F\_D}#(i) = data else if sizeof(xlen) >= 64 then #\hyperref[sailRISCVzX]{X}#(i) = #\hyperref[sailRISCVzEXTS]{EXTS}#(data) else { diff --git a/sail_latex_riscv/fnzwf_or_x_hc2f88749fb30cde823632a5f1fd09b02.tex b/sail_latex_riscv/fnzwf_or_x_hc2f88749fb30cde823632a5f1fd09b02.tex index 398980cc..6fc8f8f1 100644 --- a/sail_latex_riscv/fnzwf_or_x_hc2f88749fb30cde823632a5f1fd09b02.tex +++ b/sail_latex_riscv/fnzwf_or_x_hc2f88749fb30cde823632a5f1fd09b02.tex @@ -2,6 +2,6 @@ assert(sizeof(flen) >= 16); assert(#\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#() != #\hyperref[sailRISCVzsyszyenablezyzzfinx]{sys\_enable\_zfinx}#()); if #\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#() - then #\hyperref[sailRISCVzF]{F}#(i) = #\hyperref[sailRISCVznanzybox]{nan\_box}#(data) + then #\hyperref[sailRISCVzFzyH]{F\_H}#(i) = data else #\hyperref[sailRISCVzX]{X}#(i) = #\hyperref[sailRISCVzEXTS]{EXTS}#(data) } diff --git a/sail_latex_riscv/fnzwf_or_x_s315d4d6563a562bd03df2f3d680343b5.tex b/sail_latex_riscv/fnzwf_or_x_s315d4d6563a562bd03df2f3d680343b5.tex index 44033df4..d181619d 100644 --- a/sail_latex_riscv/fnzwf_or_x_s315d4d6563a562bd03df2f3d680343b5.tex +++ b/sail_latex_riscv/fnzwf_or_x_s315d4d6563a562bd03df2f3d680343b5.tex @@ -2,6 +2,6 @@ assert(sizeof(flen) >= 32); assert(#\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#() != #\hyperref[sailRISCVzsyszyenablezyzzfinx]{sys\_enable\_zfinx}#()); if #\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#() - then #\hyperref[sailRISCVzF]{F}#(i) = #\hyperref[sailRISCVznanzybox]{nan\_box}#(data) + then #\hyperref[sailRISCVzFzyS]{F\_S}#(i) = data else #\hyperref[sailRISCVzX]{X}#(i) = #\hyperref[sailRISCVzEXTS]{EXTS}#(data) } diff --git a/sail_latex_riscv/fnzwf_s8b4c2b923b5bc2d4c6f88cff982b6695.tex b/sail_latex_riscv/fnzwf_s8b4c2b923b5bc2d4c6f88cff982b6695.tex new file mode 100644 index 00000000..6ee765f0 --- /dev/null +++ b/sail_latex_riscv/fnzwf_s8b4c2b923b5bc2d4c6f88cff982b6695.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzwFzyS]{wF\_S}#(i, data) = { + assert(sizeof(flen) >= 32); + assert(#\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#() & #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzsyszyenablezyzzfinx]{sys\_enable\_zfinx}#())); + #\hyperref[sailRISCVzF]{F}#(i) = #\hyperref[sailRISCVznanzybox]{nan\_box}#(data) +} diff --git a/sail_latex_riscv/fnzwritecsr7af48520171f4dd0cd06c1b6876196a7.tex b/sail_latex_riscv/fnzwritecsr7af48520171f4dd0cd06c1b6876196a7.tex index 4b15e0db..6c5f119c 100644 --- a/sail_latex_riscv/fnzwritecsr7af48520171f4dd0cd06c1b6876196a7.tex +++ b/sail_latex_riscv/fnzwritecsr7af48520171f4dd0cd06c1b6876196a7.tex @@ -42,9 +42,9 @@ /* machine mode counters */ (0xB00, _) => { mcycle[(sizeof(xlen) - 1) .. 0] = value; #\hyperref[sailRISCVzSome]{Some}#(value) }, - (0xB02, _) => { minstret[(sizeof(xlen) - 1) .. 0] = value; minstret_written = true; #\hyperref[sailRISCVzSome]{Some}#(value) }, + (0xB02, _) => { minstret[(sizeof(xlen) - 1) .. 0] = value; minstret_increment = false; #\hyperref[sailRISCVzSome]{Some}#(value) }, (0xB80, 32) => { mcycle[63 .. 32] = value; #\hyperref[sailRISCVzSome]{Some}#(value) }, - (0xB82, 32) => { minstret[63 .. 32] = value; minstret_written = true; #\hyperref[sailRISCVzSome]{Some}#(value) }, + (0xB82, 32) => { minstret[63 .. 32] = value; minstret_increment = false; #\hyperref[sailRISCVzSome]{Some}#(value) }, /* trigger/debug */ (0x7a0, _) => { tselect = value; #\hyperref[sailRISCVzSome]{Some}#(tselect) }, diff --git a/sail_latex_riscv/fnzzzicondop_of_num6c236bc72d5e4b8fcf599f8f5df132a1.tex b/sail_latex_riscv/fnzzzicondop_of_num6c236bc72d5e4b8fcf599f8f5df132a1.tex new file mode 100644 index 00000000..5c1f8481 --- /dev/null +++ b/sail_latex_riscv/fnzzzicondop_of_num6c236bc72d5e4b8fcf599f8f5df132a1.tex @@ -0,0 +1,4 @@ +function zicondop_of_num arg# = match arg# { + 0 => RISCV_CZERO_EQZ, + _ => RISCV_CZERO_NEZ +} diff --git a/sail_latex_riscv/overloadKz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex b/sail_latex_riscv/overloadAz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex similarity index 100% rename from sail_latex_riscv/overloadKz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex rename to sail_latex_riscv/overloadAz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex diff --git a/sail_latex_riscv/overloadAzabs_intef5fbb521189282054dc80dc7173013d.tex b/sail_latex_riscv/overloadAzabs_intef5fbb521189282054dc80dc7173013d.tex new file mode 100644 index 00000000..047f6d0c --- /dev/null +++ b/sail_latex_riscv/overloadAzabs_intef5fbb521189282054dc80dc7173013d.tex @@ -0,0 +1 @@ +overload abs_int = {abs_int_atom} diff --git a/sail_latex_riscv/overloadYzappend88575169e0ec1639b6ae3851df999710.tex b/sail_latex_riscv/overloadAzappend88575169e0ec1639b6ae3851df999710.tex similarity index 100% rename from sail_latex_riscv/overloadYzappend88575169e0ec1639b6ae3851df999710.tex rename to sail_latex_riscv/overloadAzappend88575169e0ec1639b6ae3851df999710.tex diff --git a/sail_latex_riscv/overloadOOzbitstr0d04da018975c4776e05a9c59c2e380e.tex b/sail_latex_riscv/overloadAzbitstr0d04da018975c4776e05a9c59c2e380e.tex similarity index 100% rename from sail_latex_riscv/overloadOOzbitstr0d04da018975c4776e05a9c59c2e380e.tex rename to sail_latex_riscv/overloadAzbitstr0d04da018975c4776e05a9c59c2e380e.tex diff --git a/sail_latex_riscv/overloadKKKzc15f67105dab436b80b9241d87d1f8e9d.tex b/sail_latex_riscv/overloadAzc15f67105dab436b80b9241d87d1f8e9d.tex similarity index 100% rename from sail_latex_riscv/overloadKKKzc15f67105dab436b80b9241d87d1f8e9d.tex rename to sail_latex_riscv/overloadAzc15f67105dab436b80b9241d87d1f8e9d.tex diff --git a/sail_latex_riscv/overloadOOOzf71805d10b9ea2a56437652aba0daf9bf.tex b/sail_latex_riscv/overloadAzf71805d10b9ea2a56437652aba0daf9bf.tex similarity index 100% rename from sail_latex_riscv/overloadOOOzf71805d10b9ea2a56437652aba0daf9bf.tex rename to sail_latex_riscv/overloadAzf71805d10b9ea2a56437652aba0daf9bf.tex diff --git a/sail_latex_riscv/overloadAzf_dce13a0941da7b7642c47c02aaaf22707.tex b/sail_latex_riscv/overloadAzf_dce13a0941da7b7642c47c02aaaf22707.tex new file mode 100644 index 00000000..38e44c54 --- /dev/null +++ b/sail_latex_riscv/overloadAzf_dce13a0941da7b7642c47c02aaaf22707.tex @@ -0,0 +1 @@ +overload F_D = { rF_D, wF_D } diff --git a/sail_latex_riscv/overloadAzf_h8b5b89a166af005200eddfdb4c753f54.tex b/sail_latex_riscv/overloadAzf_h8b5b89a166af005200eddfdb4c753f54.tex new file mode 100644 index 00000000..3ad70d1e --- /dev/null +++ b/sail_latex_riscv/overloadAzf_h8b5b89a166af005200eddfdb4c753f54.tex @@ -0,0 +1 @@ +overload F_H = { rF_H, wF_H } diff --git a/sail_latex_riscv/overloadRRRzf_or_x_d024412251a76ad9b93d0cea341dd37e8.tex b/sail_latex_riscv/overloadAzf_or_x_d024412251a76ad9b93d0cea341dd37e8.tex similarity index 100% rename from sail_latex_riscv/overloadRRRzf_or_x_d024412251a76ad9b93d0cea341dd37e8.tex rename to sail_latex_riscv/overloadAzf_or_x_d024412251a76ad9b93d0cea341dd37e8.tex diff --git a/sail_latex_riscv/overloadPPPzf_or_x_h3ebc47a16976857a8cd1e19cfb51cb3e.tex b/sail_latex_riscv/overloadAzf_or_x_h3ebc47a16976857a8cd1e19cfb51cb3e.tex similarity index 100% rename from sail_latex_riscv/overloadPPPzf_or_x_h3ebc47a16976857a8cd1e19cfb51cb3e.tex rename to sail_latex_riscv/overloadAzf_or_x_h3ebc47a16976857a8cd1e19cfb51cb3e.tex diff --git a/sail_latex_riscv/overloadQQQzf_or_x_s13ae8815ba72277dad5d10001aed7f61.tex b/sail_latex_riscv/overloadAzf_or_x_s13ae8815ba72277dad5d10001aed7f61.tex similarity index 100% rename from sail_latex_riscv/overloadQQQzf_or_x_s13ae8815ba72277dad5d10001aed7f61.tex rename to sail_latex_riscv/overloadAzf_or_x_s13ae8815ba72277dad5d10001aed7f61.tex diff --git a/sail_latex_riscv/overloadAzf_s921e5f10c465aae8686d3336bac4e432.tex b/sail_latex_riscv/overloadAzf_s921e5f10c465aae8686d3336bac4e432.tex new file mode 100644 index 00000000..041ed0ad --- /dev/null +++ b/sail_latex_riscv/overloadAzf_s921e5f10c465aae8686d3336bac4e432.tex @@ -0,0 +1 @@ +overload F_S = { rF_S, wF_S } diff --git a/sail_latex_riscv/overloadWzlength469e3f917f7b24f4691faf3caf842eba.tex b/sail_latex_riscv/overloadAzlength469e3f917f7b24f4691faf3caf842eba.tex similarity index 100% rename from sail_latex_riscv/overloadWzlength469e3f917f7b24f4691faf3caf842eba.tex rename to sail_latex_riscv/overloadAzlength469e3f917f7b24f4691faf3caf842eba.tex diff --git a/sail_latex_riscv/overloadTTzmax91b641c464c0dc87660499321a356d93.tex b/sail_latex_riscv/overloadAzmax91b641c464c0dc87660499321a356d93.tex similarity index 100% rename from sail_latex_riscv/overloadTTzmax91b641c464c0dc87660499321a356d93.tex rename to sail_latex_riscv/overloadAzmax91b641c464c0dc87660499321a356d93.tex diff --git a/sail_latex_riscv/overloadSSzmin95ae3c0ebde1421750e6db87bdf74801.tex b/sail_latex_riscv/overloadAzmin95ae3c0ebde1421750e6db87bdf74801.tex similarity index 100% rename from sail_latex_riscv/overloadSSzmin95ae3c0ebde1421750e6db87bdf74801.tex rename to sail_latex_riscv/overloadAzmin95ae3c0ebde1421750e6db87bdf74801.tex diff --git a/sail_latex_riscv/overloadMMMznan_boxf593e1648915be3a65ed1e1cf0dc7712.tex b/sail_latex_riscv/overloadAznan_boxf593e1648915be3a65ed1e1cf0dc7712.tex similarity index 100% rename from sail_latex_riscv/overloadMMMznan_boxf593e1648915be3a65ed1e1cf0dc7712.tex rename to sail_latex_riscv/overloadAznan_boxf593e1648915be3a65ed1e1cf0dc7712.tex diff --git a/sail_latex_riscv/overloadNNNznan_unbox6971c840905d637f635a4793907fe38e.tex b/sail_latex_riscv/overloadAznan_unbox6971c840905d637f635a4793907fe38e.tex similarity index 100% rename from sail_latex_riscv/overloadNNNznan_unbox6971c840905d637f635a4793907fe38e.tex rename to sail_latex_riscv/overloadAznan_unbox6971c840905d637f635a4793907fe38e.tex diff --git a/sail_latex_riscv/overloadNznegatef5714e2e9cd970a9cb8b7c6fdf3732b8.tex b/sail_latex_riscv/overloadAznegatef5714e2e9cd970a9cb8b7c6fdf3732b8.tex similarity index 100% rename from sail_latex_riscv/overloadNznegatef5714e2e9cd970a9cb8b7c6fdf3732b8.tex rename to sail_latex_riscv/overloadAznegatef5714e2e9cd970a9cb8b7c6fdf3732b8.tex diff --git a/sail_latex_riscv/overloadZZzreversed9f0df85c2b57ca70b0103d18920d22f.tex b/sail_latex_riscv/overloadAzreversed9f0df85c2b57ca70b0103d18920d22f.tex similarity index 100% rename from sail_latex_riscv/overloadZZzreversed9f0df85c2b57ca70b0103d18920d22f.tex rename to sail_latex_riscv/overloadAzreversed9f0df85c2b57ca70b0103d18920d22f.tex diff --git a/sail_latex_riscv/overloadPzshl_int4772030e3fc0913189e795ec25e86dc5.tex b/sail_latex_riscv/overloadAzshl_int4772030e3fc0913189e795ec25e86dc5.tex similarity index 100% rename from sail_latex_riscv/overloadPzshl_int4772030e3fc0913189e795ec25e86dc5.tex rename to sail_latex_riscv/overloadAzshl_int4772030e3fc0913189e795ec25e86dc5.tex diff --git a/sail_latex_riscv/overloadQzshr_int5f4032eb21b9c850a9e2a8de5872a2a2.tex b/sail_latex_riscv/overloadAzshr_int5f4032eb21b9c850a9e2a8de5872a2a2.tex similarity index 100% rename from sail_latex_riscv/overloadQzshr_int5f4032eb21b9c850a9e2a8de5872a2a2.tex rename to sail_latex_riscv/overloadAzshr_int5f4032eb21b9c850a9e2a8de5872a2a2.tex diff --git a/sail_latex_riscv/overloadRztmod_int76b131b53b88df8b201279295eacebbe.tex b/sail_latex_riscv/overloadAztmod_int76b131b53b88df8b201279295eacebbe.tex similarity index 100% rename from sail_latex_riscv/overloadRztmod_int76b131b53b88df8b201279295eacebbe.tex rename to sail_latex_riscv/overloadAztmod_int76b131b53b88df8b201279295eacebbe.tex diff --git a/sail_latex_riscv/overloadDDDzto_str8b7a6895ae35945bd4740e9f790c43ee.tex b/sail_latex_riscv/overloadAzto_str8b7a6895ae35945bd4740e9f790c43ee.tex similarity index 100% rename from sail_latex_riscv/overloadDDDzto_str8b7a6895ae35945bd4740e9f790c43ee.tex rename to sail_latex_riscv/overloadAzto_str8b7a6895ae35945bd4740e9f790c43ee.tex diff --git a/sail_latex_riscv/overloadZzvector_accessbe81ec250d2df2ebadde393ea37a85a4.tex b/sail_latex_riscv/overloadAzvector_accessbe81ec250d2df2ebadde393ea37a85a4.tex similarity index 100% rename from sail_latex_riscv/overloadZzvector_accessbe81ec250d2df2ebadde393ea37a85a4.tex rename to sail_latex_riscv/overloadAzvector_accessbe81ec250d2df2ebadde393ea37a85a4.tex diff --git a/sail_latex_riscv/overloadEEzvector_subrange270c799ffa6c20b5244f22c64fba0367.tex b/sail_latex_riscv/overloadAzvector_subrange270c799ffa6c20b5244f22c64fba0367.tex similarity index 100% rename from sail_latex_riscv/overloadEEzvector_subrange270c799ffa6c20b5244f22c64fba0367.tex rename to sail_latex_riscv/overloadAzvector_subrange270c799ffa6c20b5244f22c64fba0367.tex diff --git a/sail_latex_riscv/overloadFFzvector_update_subrangeb77be803268d55f5f112399f9d0dfbc2.tex b/sail_latex_riscv/overloadAzvector_update_subrangeb77be803268d55f5f112399f9d0dfbc2.tex similarity index 100% rename from sail_latex_riscv/overloadFFzvector_update_subrangeb77be803268d55f5f112399f9d0dfbc2.tex rename to sail_latex_riscv/overloadAzvector_update_subrangeb77be803268d55f5f112399f9d0dfbc2.tex diff --git a/sail_latex_riscv/overloadAAzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex b/sail_latex_riscv/overloadAzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex similarity index 100% rename from sail_latex_riscv/overloadAAzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex rename to sail_latex_riscv/overloadAzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex diff --git a/sail_latex_riscv/overloadIIIzx1f3c57dd04ac52fd92f3346ca51f00ec.tex b/sail_latex_riscv/overloadAzx1f3c57dd04ac52fd92f3346ca51f00ec.tex similarity index 100% rename from sail_latex_riscv/overloadIIIzx1f3c57dd04ac52fd92f3346ca51f00ec.tex rename to sail_latex_riscv/overloadAzx1f3c57dd04ac52fd92f3346ca51f00ec.tex diff --git a/sail_latex_riscv/overloadDzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex b/sail_latex_riscv/overloadAzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex similarity index 100% rename from sail_latex_riscv/overloadDzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex rename to sail_latex_riscv/overloadAzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex diff --git a/sail_latex_riscv/overloadRRzz8operatorz0z5z9194a289f0ceb02e29c9b6febc5146071.tex b/sail_latex_riscv/overloadAzz8operatorz0z5z9194a289f0ceb02e29c9b6febc5146071.tex similarity index 100% rename from sail_latex_riscv/overloadRRzz8operatorz0z5z9194a289f0ceb02e29c9b6febc5146071.tex rename to sail_latex_riscv/overloadAzz8operatorz0z5z9194a289f0ceb02e29c9b6febc5146071.tex diff --git a/sail_latex_riscv/overloadFzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex b/sail_latex_riscv/overloadAzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex similarity index 100% rename from sail_latex_riscv/overloadFzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex rename to sail_latex_riscv/overloadAzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex diff --git a/sail_latex_riscv/overloadOzz8operatorz0zaz94d99df7698c53c990108e8f028c06211.tex b/sail_latex_riscv/overloadAzz8operatorz0zaz94d99df7698c53c990108e8f028c06211.tex similarity index 100% rename from sail_latex_riscv/overloadOzz8operatorz0zaz94d99df7698c53c990108e8f028c06211.tex rename to sail_latex_riscv/overloadAzz8operatorz0zaz94d99df7698c53c990108e8f028c06211.tex diff --git a/sail_latex_riscv/overloadLzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex b/sail_latex_riscv/overloadAzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex similarity index 100% rename from sail_latex_riscv/overloadLzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex rename to sail_latex_riscv/overloadAzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex diff --git a/sail_latex_riscv/overloadMzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex b/sail_latex_riscv/overloadAzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex similarity index 100% rename from sail_latex_riscv/overloadMzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex rename to sail_latex_riscv/overloadAzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex diff --git a/sail_latex_riscv/overloadHzz8operatorz0ziz9714b8c400aed24ebd80eac39b4f9d751.tex b/sail_latex_riscv/overloadAzz8operatorz0ziz9714b8c400aed24ebd80eac39b4f9d751.tex similarity index 100% rename from sail_latex_riscv/overloadHzz8operatorz0ziz9714b8c400aed24ebd80eac39b4f9d751.tex rename to sail_latex_riscv/overloadAzz8operatorz0ziz9714b8c400aed24ebd80eac39b4f9d751.tex diff --git a/sail_latex_riscv/overloadWWzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex b/sail_latex_riscv/overloadAzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex similarity index 100% rename from sail_latex_riscv/overloadWWzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex rename to sail_latex_riscv/overloadAzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex diff --git a/sail_latex_riscv/overloadYYzz8operatorz0ziziziz9daf9b9d2ffdbec7af40418527044fa38.tex b/sail_latex_riscv/overloadAzz8operatorz0ziziziz9daf9b9d2ffdbec7af40418527044fa38.tex similarity index 100% rename from sail_latex_riscv/overloadYYzz8operatorz0ziziziz9daf9b9d2ffdbec7af40418527044fa38.tex rename to sail_latex_riscv/overloadAzz8operatorz0ziziziz9daf9b9d2ffdbec7af40418527044fa38.tex diff --git a/sail_latex_riscv/overloadGzz8operatorz0zizjz95c366628fed7d8b7c251f1acd527ee3b.tex b/sail_latex_riscv/overloadAzz8operatorz0zizjz95c366628fed7d8b7c251f1acd527ee3b.tex similarity index 100% rename from sail_latex_riscv/overloadGzz8operatorz0zizjz95c366628fed7d8b7c251f1acd527ee3b.tex rename to sail_latex_riscv/overloadAzz8operatorz0zizjz95c366628fed7d8b7c251f1acd527ee3b.tex diff --git a/sail_latex_riscv/overloadAzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex b/sail_latex_riscv/overloadAzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex new file mode 100644 index 00000000..751094be --- /dev/null +++ b/sail_latex_riscv/overloadAzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex @@ -0,0 +1 @@ +overload operator == = {eq_int, eq_bit, eq_bool, eq_unit} diff --git a/sail_latex_riscv/overloadJzz8operatorz0zkz93747e4d4a6f99eb3fca0b477d2437ed5.tex b/sail_latex_riscv/overloadAzz8operatorz0zkz93747e4d4a6f99eb3fca0b477d2437ed5.tex similarity index 100% rename from sail_latex_riscv/overloadJzz8operatorz0zkz93747e4d4a6f99eb3fca0b477d2437ed5.tex rename to sail_latex_riscv/overloadAzz8operatorz0zkz93747e4d4a6f99eb3fca0b477d2437ed5.tex diff --git a/sail_latex_riscv/overloadIzz8operatorz0zkzjz94161e4bfad2d20e5d25bc774612b6588.tex b/sail_latex_riscv/overloadAzz8operatorz0zkzjz94161e4bfad2d20e5d25bc774612b6588.tex similarity index 100% rename from sail_latex_riscv/overloadIzz8operatorz0zkzjz94161e4bfad2d20e5d25bc774612b6588.tex rename to sail_latex_riscv/overloadAzz8operatorz0zkzjz94161e4bfad2d20e5d25bc774612b6588.tex diff --git a/sail_latex_riscv/overloadCCCzz8operatorz0zkzk_sz9fd336467c8d7c9163cb44b900cb10522.tex b/sail_latex_riscv/overloadAzz8operatorz0zkzk_sz9fd336467c8d7c9163cb44b900cb10522.tex similarity index 100% rename from sail_latex_riscv/overloadCCCzz8operatorz0zkzk_sz9fd336467c8d7c9163cb44b900cb10522.tex rename to sail_latex_riscv/overloadAzz8operatorz0zkzk_sz9fd336467c8d7c9163cb44b900cb10522.tex diff --git a/sail_latex_riscv/overloadVVzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex b/sail_latex_riscv/overloadAzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex similarity index 100% rename from sail_latex_riscv/overloadVVzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex rename to sail_latex_riscv/overloadAzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex diff --git a/sail_latex_riscv/overloadXXzz8operatorz0zkzkzkz957fa2f300078df169cd8f1b6939b710d.tex b/sail_latex_riscv/overloadAzz8operatorz0zkzkzkz957fa2f300078df169cd8f1b6939b710d.tex similarity index 100% rename from sail_latex_riscv/overloadXXzz8operatorz0zkzkzkz957fa2f300078df169cd8f1b6939b710d.tex rename to sail_latex_riscv/overloadAzz8operatorz0zkzkzkz957fa2f300078df169cd8f1b6939b710d.tex diff --git a/sail_latex_riscv/overloadXzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex b/sail_latex_riscv/overloadAzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex similarity index 100% rename from sail_latex_riscv/overloadXzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex rename to sail_latex_riscv/overloadAzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex diff --git a/sail_latex_riscv/overloadEzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex b/sail_latex_riscv/overloadAzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex similarity index 100% rename from sail_latex_riscv/overloadEzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex rename to sail_latex_riscv/overloadAzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex diff --git a/sail_latex_riscv/overloadKKzzw805a9067649c7cfeedcb41b57a7e2c86.tex b/sail_latex_riscv/overloadAzzw805a9067649c7cfeedcb41b57a7e2c86.tex similarity index 100% rename from sail_latex_riscv/overloadKKzzw805a9067649c7cfeedcb41b57a7e2c86.tex rename to sail_latex_riscv/overloadAzzw805a9067649c7cfeedcb41b57a7e2c86.tex diff --git a/sail_latex_riscv/overloadUUzzzerosc530711942e216cef3921733c1c5d101.tex b/sail_latex_riscv/overloadAzzzerosc530711942e216cef3921733c1c5d101.tex similarity index 100% rename from sail_latex_riscv/overloadUUzzzerosc530711942e216cef3921733c1c5d101.tex rename to sail_latex_riscv/overloadAzzzerosc530711942e216cef3921733c1c5d101.tex diff --git a/sail_latex_riscv/overloadGGz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex b/sail_latex_riscv/overloadBz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex similarity index 100% rename from sail_latex_riscv/overloadGGz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex rename to sail_latex_riscv/overloadBz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex diff --git a/sail_latex_riscv/overloadBzabs_intef5fbb521189282054dc80dc7173013d.tex b/sail_latex_riscv/overloadBzabs_intef5fbb521189282054dc80dc7173013d.tex index 047f6d0c..6598a227 100644 --- a/sail_latex_riscv/overloadBzabs_intef5fbb521189282054dc80dc7173013d.tex +++ b/sail_latex_riscv/overloadBzabs_intef5fbb521189282054dc80dc7173013d.tex @@ -1 +1 @@ -overload abs_int = {abs_int_atom} +overload abs_int = {abs_int_plain} diff --git a/sail_latex_riscv/overloadJJzappend88575169e0ec1639b6ae3851df999710.tex b/sail_latex_riscv/overloadBzappend88575169e0ec1639b6ae3851df999710.tex similarity index 100% rename from sail_latex_riscv/overloadJJzappend88575169e0ec1639b6ae3851df999710.tex rename to sail_latex_riscv/overloadBzappend88575169e0ec1639b6ae3851df999710.tex diff --git a/sail_latex_riscv/overloadEEEzto_str8b7a6895ae35945bd4740e9f790c43ee.tex b/sail_latex_riscv/overloadBzto_str8b7a6895ae35945bd4740e9f790c43ee.tex similarity index 100% rename from sail_latex_riscv/overloadEEEzto_str8b7a6895ae35945bd4740e9f790c43ee.tex rename to sail_latex_riscv/overloadBzto_str8b7a6895ae35945bd4740e9f790c43ee.tex diff --git a/sail_latex_riscv/overloadIIzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex b/sail_latex_riscv/overloadBzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex similarity index 100% rename from sail_latex_riscv/overloadIIzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex rename to sail_latex_riscv/overloadBzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex diff --git a/sail_latex_riscv/overloadVzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex b/sail_latex_riscv/overloadBzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex similarity index 100% rename from sail_latex_riscv/overloadVzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex rename to sail_latex_riscv/overloadBzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex diff --git a/sail_latex_riscv/overloadCCzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex b/sail_latex_riscv/overloadBzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex similarity index 100% rename from sail_latex_riscv/overloadCCzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex rename to sail_latex_riscv/overloadBzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex diff --git a/sail_latex_riscv/overloadBBzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex b/sail_latex_riscv/overloadBzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex similarity index 100% rename from sail_latex_riscv/overloadBBzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex rename to sail_latex_riscv/overloadBzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex diff --git a/sail_latex_riscv/overloadQQzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex b/sail_latex_riscv/overloadBzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex similarity index 100% rename from sail_latex_riscv/overloadQQzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex rename to sail_latex_riscv/overloadBzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex diff --git a/sail_latex_riscv/overloadBBBzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex b/sail_latex_riscv/overloadBzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex similarity index 100% rename from sail_latex_riscv/overloadBBBzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex rename to sail_latex_riscv/overloadBzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex diff --git a/sail_latex_riscv/overloadTzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex b/sail_latex_riscv/overloadBzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex similarity index 100% rename from sail_latex_riscv/overloadTzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex rename to sail_latex_riscv/overloadBzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex diff --git a/sail_latex_riscv/overloadAAAzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex b/sail_latex_riscv/overloadBzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex similarity index 100% rename from sail_latex_riscv/overloadAAAzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex rename to sail_latex_riscv/overloadBzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex diff --git a/sail_latex_riscv/overloadPPzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex b/sail_latex_riscv/overloadBzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex similarity index 100% rename from sail_latex_riscv/overloadPPzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex rename to sail_latex_riscv/overloadBzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex diff --git a/sail_latex_riscv/overloadDDzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex b/sail_latex_riscv/overloadBzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex similarity index 100% rename from sail_latex_riscv/overloadDDzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex rename to sail_latex_riscv/overloadBzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex diff --git a/sail_latex_riscv/overloadFFFzto_str8b7a6895ae35945bd4740e9f790c43ee.tex b/sail_latex_riscv/overloadCzto_str8b7a6895ae35945bd4740e9f790c43ee.tex similarity index 100% rename from sail_latex_riscv/overloadFFFzto_str8b7a6895ae35945bd4740e9f790c43ee.tex rename to sail_latex_riscv/overloadCzto_str8b7a6895ae35945bd4740e9f790c43ee.tex diff --git a/sail_latex_riscv/overloadLLzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex b/sail_latex_riscv/overloadCzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex similarity index 100% rename from sail_latex_riscv/overloadLLzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex rename to sail_latex_riscv/overloadCzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex diff --git a/sail_latex_riscv/overloadMMzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex b/sail_latex_riscv/overloadCzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex similarity index 100% rename from sail_latex_riscv/overloadMMzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex rename to sail_latex_riscv/overloadCzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex diff --git a/sail_latex_riscv/overloadCzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex b/sail_latex_riscv/overloadCzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex index 751094be..49daed5c 100644 --- a/sail_latex_riscv/overloadCzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex +++ b/sail_latex_riscv/overloadCzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex @@ -1 +1 @@ -overload operator == = {eq_int, eq_bit, eq_bool, eq_unit} +overload operator == = {eq_bit, eq_bits} diff --git a/sail_latex_riscv/overloadNNzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex b/sail_latex_riscv/overloadCzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex similarity index 100% rename from sail_latex_riscv/overloadNNzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex rename to sail_latex_riscv/overloadCzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex diff --git a/sail_latex_riscv/overloadGGGzto_str8b7a6895ae35945bd4740e9f790c43ee.tex b/sail_latex_riscv/overloadDzto_str8b7a6895ae35945bd4740e9f790c43ee.tex similarity index 100% rename from sail_latex_riscv/overloadGGGzto_str8b7a6895ae35945bd4740e9f790c43ee.tex rename to sail_latex_riscv/overloadDzto_str8b7a6895ae35945bd4740e9f790c43ee.tex diff --git a/sail_latex_riscv/overloadHHzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex b/sail_latex_riscv/overloadDzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex similarity index 100% rename from sail_latex_riscv/overloadHHzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex rename to sail_latex_riscv/overloadDzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex diff --git a/sail_latex_riscv/overloadHHHzto_str8b7a6895ae35945bd4740e9f790c43ee.tex b/sail_latex_riscv/overloadEzto_str8b7a6895ae35945bd4740e9f790c43ee.tex similarity index 100% rename from sail_latex_riscv/overloadHHHzto_str8b7a6895ae35945bd4740e9f790c43ee.tex rename to sail_latex_riscv/overloadEzto_str8b7a6895ae35945bd4740e9f790c43ee.tex diff --git a/sail_latex_riscv/overloadJJJzto_str8b7a6895ae35945bd4740e9f790c43ee.tex b/sail_latex_riscv/overloadFzto_str8b7a6895ae35945bd4740e9f790c43ee.tex similarity index 100% rename from sail_latex_riscv/overloadJJJzto_str8b7a6895ae35945bd4740e9f790c43ee.tex rename to sail_latex_riscv/overloadFzto_str8b7a6895ae35945bd4740e9f790c43ee.tex diff --git a/sail_latex_riscv/overloadLLLzto_str8b7a6895ae35945bd4740e9f790c43ee.tex b/sail_latex_riscv/overloadGzto_str8b7a6895ae35945bd4740e9f790c43ee.tex similarity index 100% rename from sail_latex_riscv/overloadLLLzto_str8b7a6895ae35945bd4740e9f790c43ee.tex rename to sail_latex_riscv/overloadGzto_str8b7a6895ae35945bd4740e9f790c43ee.tex diff --git a/sail_latex_riscv/overloadSSSzto_str8b7a6895ae35945bd4740e9f790c43ee.tex b/sail_latex_riscv/overloadHzto_str8b7a6895ae35945bd4740e9f790c43ee.tex similarity index 100% rename from sail_latex_riscv/overloadSSSzto_str8b7a6895ae35945bd4740e9f790c43ee.tex rename to sail_latex_riscv/overloadHzto_str8b7a6895ae35945bd4740e9f790c43ee.tex diff --git a/sail_latex_riscv/overloadTTTzto_str8b7a6895ae35945bd4740e9f790c43ee.tex b/sail_latex_riscv/overloadIzto_str8b7a6895ae35945bd4740e9f790c43ee.tex similarity index 100% rename from sail_latex_riscv/overloadTTTzto_str8b7a6895ae35945bd4740e9f790c43ee.tex rename to sail_latex_riscv/overloadIzto_str8b7a6895ae35945bd4740e9f790c43ee.tex diff --git a/sail_latex_riscv/overloadUUUzto_str8b7a6895ae35945bd4740e9f790c43ee.tex b/sail_latex_riscv/overloadJzto_str8b7a6895ae35945bd4740e9f790c43ee.tex similarity index 100% rename from sail_latex_riscv/overloadUUUzto_str8b7a6895ae35945bd4740e9f790c43ee.tex rename to sail_latex_riscv/overloadJzto_str8b7a6895ae35945bd4740e9f790c43ee.tex diff --git a/sail_latex_riscv/overloadSzabs_intef5fbb521189282054dc80dc7173013d.tex b/sail_latex_riscv/overloadSzabs_intef5fbb521189282054dc80dc7173013d.tex deleted file mode 100644 index 6598a227..00000000 --- a/sail_latex_riscv/overloadSzabs_intef5fbb521189282054dc80dc7173013d.tex +++ /dev/null @@ -1 +0,0 @@ -overload abs_int = {abs_int_plain} diff --git a/sail_latex_riscv/overloadUzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex b/sail_latex_riscv/overloadUzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex deleted file mode 100644 index 49daed5c..00000000 --- a/sail_latex_riscv/overloadUzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex +++ /dev/null @@ -1 +0,0 @@ -overload operator == = {eq_bit, eq_bits} diff --git a/sail_latex_riscv/registerzminstret_increment4bf06d6ee65982630fdaccfdc2b150e1.tex b/sail_latex_riscv/registerzminstret_increment4bf06d6ee65982630fdaccfdc2b150e1.tex new file mode 100644 index 00000000..c67fd514 --- /dev/null +++ b/sail_latex_riscv/registerzminstret_increment4bf06d6ee65982630fdaccfdc2b150e1.tex @@ -0,0 +1 @@ +register minstret_increment : bool diff --git a/sail_latex_riscv/registerzminstret_writtenaed0046aa7ec44bb59b2c8c7710e05d2.tex b/sail_latex_riscv/registerzminstret_writtenaed0046aa7ec44bb59b2c8c7710e05d2.tex deleted file mode 100644 index 48a73935..00000000 --- a/sail_latex_riscv/registerzminstret_writtenaed0046aa7ec44bb59b2c8c7710e05d2.tex +++ /dev/null @@ -1 +0,0 @@ -register minstret_written : bool diff --git a/sail_latex_riscv/typezbits_h76e870fea4865b90f006ce427cb2a6df.tex b/sail_latex_riscv/typezbits_h76e870fea4865b90f006ce427cb2a6df.tex index eb3948e0..57a2dc9d 100644 --- a/sail_latex_riscv/typezbits_h76e870fea4865b90f006ce427cb2a6df.tex +++ b/sail_latex_riscv/typezbits_h76e870fea4865b90f006ce427cb2a6df.tex @@ -1 +1 @@ -type bits_H = #\hyperref[sailRISCVzbits]{bits}#(16) /* Half-precision float value */ +type bits_H = #\hyperref[sailRISCVzbits]{bits}#(16) /* Half-precision float value */ diff --git a/sail_latex_riscv/typezccsrebba1b25012128c604b97c41d5de5508.tex b/sail_latex_riscv/typezccsrebba1b25012128c604b97c41d5de5508.tex index 5272ab5a..0d34f621 100644 --- a/sail_latex_riscv/typezccsrebba1b25012128c604b97c41d5de5508.tex +++ b/sail_latex_riscv/typezccsrebba1b25012128c604b97c41d5de5508.tex @@ -1,4 +1,6 @@ bitfield ccsr : xlenbits = { - d : 1, /* dirty */ + /* Bits allocated from 31 downwards are used for feature flags. */ + tc : 31, /* tag-clearing error semantics */ + nr : 30, /* no DDC/PCC relocation */ e : 0 /* enable */ } diff --git a/sail_latex_riscv/typezzzicondopa7aca235781cdb8d229dc510abbddd29.tex b/sail_latex_riscv/typezzzicondopa7aca235781cdb8d229dc510abbddd29.tex new file mode 100644 index 00000000..d88260ee --- /dev/null +++ b/sail_latex_riscv/typezzzicondopa7aca235781cdb8d229dc510abbddd29.tex @@ -0,0 +1 @@ +enum zicondop = {RISCV_CZERO_EQZ, RISCV_CZERO_NEZ} diff --git a/sail_latex_riscv/valzcap_to_integer_pcfb8f9e29d6bb00469db30a7b19649da3.tex b/sail_latex_riscv/valzcap_to_integer_pcfb8f9e29d6bb00469db30a7b19649da3.tex new file mode 100644 index 00000000..1f11be80 --- /dev/null +++ b/sail_latex_riscv/valzcap_to_integer_pcfb8f9e29d6bb00469db30a7b19649da3.tex @@ -0,0 +1 @@ +cap_to_integer_pc : Capability -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzddc_and_resulting_addr0f0e2d5c6123a71667b35ed17c44868e.tex b/sail_latex_riscv/valzddc_and_resulting_addr0f0e2d5c6123a71667b35ed17c44868e.tex new file mode 100644 index 00000000..28e40212 --- /dev/null +++ b/sail_latex_riscv/valzddc_and_resulting_addr0f0e2d5c6123a71667b35ed17c44868e.tex @@ -0,0 +1 @@ +ddc_and_resulting_addr : xlenbits -> (Capability, xlenbits) \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f16le_quietba87aa826fe2ea7c4186b6a7d2619883.tex b/sail_latex_riscv/valzextern_f16le_quietba87aa826fe2ea7c4186b6a7d2619883.tex new file mode 100644 index 00000000..20bf1bd4 --- /dev/null +++ b/sail_latex_riscv/valzextern_f16le_quietba87aa826fe2ea7c4186b6a7d2619883.tex @@ -0,0 +1 @@ +extern_f16Le_quiet : (bits_H, bits_H) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f16lt_quiet47c4bf08ad78e10df5bd97faf51ba75b.tex b/sail_latex_riscv/valzextern_f16lt_quiet47c4bf08ad78e10df5bd97faf51ba75b.tex new file mode 100644 index 00000000..b1b0273f --- /dev/null +++ b/sail_latex_riscv/valzextern_f16lt_quiet47c4bf08ad78e10df5bd97faf51ba75b.tex @@ -0,0 +1 @@ +extern_f16Lt_quiet : (bits_H, bits_H) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f16roundtointf6702102443ea92a9f058ba571bbd8d7.tex b/sail_latex_riscv/valzextern_f16roundtointf6702102443ea92a9f058ba571bbd8d7.tex new file mode 100644 index 00000000..34683b1b --- /dev/null +++ b/sail_latex_riscv/valzextern_f16roundtointf6702102443ea92a9f058ba571bbd8d7.tex @@ -0,0 +1 @@ +extern_f16roundToInt : (bits_rm, bits_H, bool) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f32le_quiet8f7c77183e32b1b4c551a8457476d996.tex b/sail_latex_riscv/valzextern_f32le_quiet8f7c77183e32b1b4c551a8457476d996.tex new file mode 100644 index 00000000..02729bd2 --- /dev/null +++ b/sail_latex_riscv/valzextern_f32le_quiet8f7c77183e32b1b4c551a8457476d996.tex @@ -0,0 +1 @@ +extern_f32Le_quiet : (bits_S, bits_S) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f32lt_quiet70f5a9ae1a77127a5cebd114c342108f.tex b/sail_latex_riscv/valzextern_f32lt_quiet70f5a9ae1a77127a5cebd114c342108f.tex new file mode 100644 index 00000000..ccdcdbba --- /dev/null +++ b/sail_latex_riscv/valzextern_f32lt_quiet70f5a9ae1a77127a5cebd114c342108f.tex @@ -0,0 +1 @@ +extern_f32Lt_quiet : (bits_S, bits_S) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f32roundtointfd564f319eaa6e135f5b6a5d1d839221.tex b/sail_latex_riscv/valzextern_f32roundtointfd564f319eaa6e135f5b6a5d1d839221.tex new file mode 100644 index 00000000..676a5d10 --- /dev/null +++ b/sail_latex_riscv/valzextern_f32roundtointfd564f319eaa6e135f5b6a5d1d839221.tex @@ -0,0 +1 @@ +extern_f32roundToInt : (bits_rm, bits_S, bool) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f64le_quiet62f25ed39def4a3e2df9a7320243076b.tex b/sail_latex_riscv/valzextern_f64le_quiet62f25ed39def4a3e2df9a7320243076b.tex new file mode 100644 index 00000000..b393bd23 --- /dev/null +++ b/sail_latex_riscv/valzextern_f64le_quiet62f25ed39def4a3e2df9a7320243076b.tex @@ -0,0 +1 @@ +extern_f64Le_quiet : (bits_D, bits_D) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f64lt_quietb909aef2c69da0356d6e4e66ceaba06b.tex b/sail_latex_riscv/valzextern_f64lt_quietb909aef2c69da0356d6e4e66ceaba06b.tex new file mode 100644 index 00000000..dd8877ea --- /dev/null +++ b/sail_latex_riscv/valzextern_f64lt_quietb909aef2c69da0356d6e4e66ceaba06b.tex @@ -0,0 +1 @@ +extern_f64Lt_quiet : (bits_D, bits_D) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f64roundtointa3a7bcf2dfbdc3862b468cb032011274.tex b/sail_latex_riscv/valzextern_f64roundtointa3a7bcf2dfbdc3862b468cb032011274.tex new file mode 100644 index 00000000..af3460f7 --- /dev/null +++ b/sail_latex_riscv/valzextern_f64roundtointa3a7bcf2dfbdc3862b468cb032011274.tex @@ -0,0 +1 @@ +extern_f64roundToInt : (bits_rm, bits_D, bool) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzhave_cheri_relocationbbe9a9f5c01227424d0cc8330de5d0b3.tex b/sail_latex_riscv/valzhave_cheri_relocationbbe9a9f5c01227424d0cc8330de5d0b3.tex new file mode 100644 index 00000000..2be2af63 --- /dev/null +++ b/sail_latex_riscv/valzhave_cheri_relocationbbe9a9f5c01227424d0cc8330de5d0b3.tex @@ -0,0 +1 @@ +have_cheri_relocation : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhave_ddc_relocationcdaa2a12594a6d0db423bcedfc636210.tex b/sail_latex_riscv/valzhave_ddc_relocationcdaa2a12594a6d0db423bcedfc636210.tex new file mode 100644 index 00000000..107c6f0a --- /dev/null +++ b/sail_latex_riscv/valzhave_ddc_relocationcdaa2a12594a6d0db423bcedfc636210.tex @@ -0,0 +1 @@ +have_ddc_relocation : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhave_pcc_relocation8ef276f0f56e5c3343729212dcd97cb5.tex b/sail_latex_riscv/valzhave_pcc_relocation8ef276f0f56e5c3343729212dcd97cb5.tex new file mode 100644 index 00000000..6e962fe5 --- /dev/null +++ b/sail_latex_riscv/valzhave_pcc_relocation8ef276f0f56e5c3343729212dcd97cb5.tex @@ -0,0 +1 @@ +have_pcc_relocation : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhavezfa170943288777f725fbf88904d27d506e.tex b/sail_latex_riscv/valzhavezfa170943288777f725fbf88904d27d506e.tex new file mode 100644 index 00000000..90e8d6e8 --- /dev/null +++ b/sail_latex_riscv/valzhavezfa170943288777f725fbf88904d27d506e.tex @@ -0,0 +1 @@ +haveZfa : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhavezicond942507aaca8f56a8d3fc5cd08536c028.tex b/sail_latex_riscv/valzhavezicond942507aaca8f56a8d3fc5cd08536c028.tex new file mode 100644 index 00000000..a45bc49d --- /dev/null +++ b/sail_latex_riscv/valzhavezicond942507aaca8f56a8d3fc5cd08536c028.tex @@ -0,0 +1 @@ +haveZicond : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_zzicondop3e6d4701d8934768c6aaf82a93f9c62d.tex b/sail_latex_riscv/valznum_of_zzicondop3e6d4701d8934768c6aaf82a93f9c62d.tex new file mode 100644 index 00000000..94eec92e --- /dev/null +++ b/sail_latex_riscv/valznum_of_zzicondop3e6d4701d8934768c6aaf82a93f9c62d.tex @@ -0,0 +1 @@ +num_of_zicondop : zicondop -> {'e, (0 <= 'e & 'e <= 1). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valzrf_d29c6729673402bec577925987b943174.tex b/sail_latex_riscv/valzrf_d29c6729673402bec577925987b943174.tex new file mode 100644 index 00000000..2501627c --- /dev/null +++ b/sail_latex_riscv/valzrf_d29c6729673402bec577925987b943174.tex @@ -0,0 +1 @@ +rF_D : bits(5) -> bits(64) \ No newline at end of file diff --git a/sail_latex_riscv/valzrf_hf87446c77cdaf455431ea51fc65d658a.tex b/sail_latex_riscv/valzrf_hf87446c77cdaf455431ea51fc65d658a.tex new file mode 100644 index 00000000..b2cdf0b4 --- /dev/null +++ b/sail_latex_riscv/valzrf_hf87446c77cdaf455431ea51fc65d658a.tex @@ -0,0 +1 @@ +rF_H : bits(5) -> bits(16) \ No newline at end of file diff --git a/sail_latex_riscv/valzrf_sae821dae13888ed4dd6a166d80f9c14c.tex b/sail_latex_riscv/valzrf_sae821dae13888ed4dd6a166d80f9c14c.tex new file mode 100644 index 00000000..81ec4a92 --- /dev/null +++ b/sail_latex_riscv/valzrf_sae821dae13888ed4dd6a166d80f9c14c.tex @@ -0,0 +1 @@ +rF_S : bits(5) -> bits(32) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f16le_quiet8f63ce7ff3e42871a470478ce69c31a9.tex b/sail_latex_riscv/valzriscv_f16le_quiet8f63ce7ff3e42871a470478ce69c31a9.tex new file mode 100644 index 00000000..8f59190d --- /dev/null +++ b/sail_latex_riscv/valzriscv_f16le_quiet8f63ce7ff3e42871a470478ce69c31a9.tex @@ -0,0 +1 @@ +riscv_f16Le_quiet : (bits_H, bits_H) -> (bits_fflags, bool) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f16lt_quiet244f6ba5b2310a0cac1e04951f6afb9c.tex b/sail_latex_riscv/valzriscv_f16lt_quiet244f6ba5b2310a0cac1e04951f6afb9c.tex new file mode 100644 index 00000000..5172e9f7 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f16lt_quiet244f6ba5b2310a0cac1e04951f6afb9c.tex @@ -0,0 +1 @@ +riscv_f16Lt_quiet : (bits_H, bits_H) -> (bits_fflags, bool) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f16roundtoint52329eb13a3e4a06c8e70e0c4ef36e80.tex b/sail_latex_riscv/valzriscv_f16roundtoint52329eb13a3e4a06c8e70e0c4ef36e80.tex new file mode 100644 index 00000000..08f74a62 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f16roundtoint52329eb13a3e4a06c8e70e0c4ef36e80.tex @@ -0,0 +1 @@ +riscv_f16roundToInt : (bits_rm, bits_H, bool) -> (bits_fflags, bits_H) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f32le_quiet7e5f820135a916f973026964c0ce90bf.tex b/sail_latex_riscv/valzriscv_f32le_quiet7e5f820135a916f973026964c0ce90bf.tex new file mode 100644 index 00000000..4ab6fb94 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f32le_quiet7e5f820135a916f973026964c0ce90bf.tex @@ -0,0 +1 @@ +riscv_f32Le_quiet : (bits_S, bits_S) -> (bits_fflags, bool) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f32lt_quiet6805f79a39a589997e0e972ca2f211be.tex b/sail_latex_riscv/valzriscv_f32lt_quiet6805f79a39a589997e0e972ca2f211be.tex new file mode 100644 index 00000000..fcae0de4 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f32lt_quiet6805f79a39a589997e0e972ca2f211be.tex @@ -0,0 +1 @@ +riscv_f32Lt_quiet : (bits_S, bits_S) -> (bits_fflags, bool) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f32roundtoint33ebf4ca80343b549f0b5a1c93805348.tex b/sail_latex_riscv/valzriscv_f32roundtoint33ebf4ca80343b549f0b5a1c93805348.tex new file mode 100644 index 00000000..074bb8f8 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f32roundtoint33ebf4ca80343b549f0b5a1c93805348.tex @@ -0,0 +1 @@ +riscv_f32roundToInt : (bits_rm, bits_S, bool) -> (bits_fflags, bits_S) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f64le_quietdbcd45688456ae3af8949c7df7db62f7.tex b/sail_latex_riscv/valzriscv_f64le_quietdbcd45688456ae3af8949c7df7db62f7.tex new file mode 100644 index 00000000..bbdc71ad --- /dev/null +++ b/sail_latex_riscv/valzriscv_f64le_quietdbcd45688456ae3af8949c7df7db62f7.tex @@ -0,0 +1 @@ +riscv_f64Le_quiet : (bits_D, bits_D) -> (bits_fflags, bool) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f64lt_quiet14ab1c593c5d6a2b683a6949da76b09d.tex b/sail_latex_riscv/valzriscv_f64lt_quiet14ab1c593c5d6a2b683a6949da76b09d.tex new file mode 100644 index 00000000..dc10e745 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f64lt_quiet14ab1c593c5d6a2b683a6949da76b09d.tex @@ -0,0 +1 @@ +riscv_f64Lt_quiet : (bits_D, bits_D) -> (bits_fflags, bool) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f64roundtointc621d19070f8cdbcc8f4378ba7716a84.tex b/sail_latex_riscv/valzriscv_f64roundtointc621d19070f8cdbcc8f4378ba7716a84.tex new file mode 100644 index 00000000..cb6ba41f --- /dev/null +++ b/sail_latex_riscv/valzriscv_f64roundtointc621d19070f8cdbcc8f4378ba7716a84.tex @@ -0,0 +1 @@ +riscv_f64roundToInt : (bits_rm, bits_D, bool) -> (bits_fflags, bits_D) \ No newline at end of file diff --git a/sail_latex_riscv/valzrvfi_write8e76a07b5a6f2a7b76947099108996b1.tex b/sail_latex_riscv/valzrvfi_write8e76a07b5a6f2a7b76947099108996b1.tex index ac9561c9..aba29ce8 100644 --- a/sail_latex_riscv/valzrvfi_write8e76a07b5a6f2a7b76947099108996b1.tex +++ b/sail_latex_riscv/valzrvfi_write8e76a07b5a6f2a7b76947099108996b1.tex @@ -1 +1 @@ -rvfi_write : forall 'n, 'n > 0. (xlenbits, int('n), bits(8 * 'n), mem_meta) -> unit \ No newline at end of file +rvfi_write : forall 'n, 'n > 0. (xlenbits, int('n), bits(8 * 'n), mem_meta, MemoryOpResult(bool)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzsetcapaddrchecked02f3e6fc454faf7b488ed3661fb1a85e.tex b/sail_latex_riscv/valzsetcapaddrchecked02f3e6fc454faf7b488ed3661fb1a85e.tex new file mode 100644 index 00000000..fdd03287 --- /dev/null +++ b/sail_latex_riscv/valzsetcapaddrchecked02f3e6fc454faf7b488ed3661fb1a85e.tex @@ -0,0 +1 @@ +setCapAddrChecked : (Capability, CapAddrBits) -> Capability \ No newline at end of file diff --git a/sail_latex_riscv/valzupdate_cap_with_integer_pc9c66feb4cf9d3f64ba301705bf4cece5.tex b/sail_latex_riscv/valzupdate_cap_with_integer_pc9c66feb4cf9d3f64ba301705bf4cece5.tex new file mode 100644 index 00000000..fe0718c9 --- /dev/null +++ b/sail_latex_riscv/valzupdate_cap_with_integer_pc9c66feb4cf9d3f64ba301705bf4cece5.tex @@ -0,0 +1 @@ +update_cap_with_integer_pc : (Capability, xlenbits) -> Capability \ No newline at end of file diff --git a/sail_latex_riscv/valzwf_d94c91aff56d9566b109d96edd2d1663f.tex b/sail_latex_riscv/valzwf_d94c91aff56d9566b109d96edd2d1663f.tex new file mode 100644 index 00000000..0770cdcb --- /dev/null +++ b/sail_latex_riscv/valzwf_d94c91aff56d9566b109d96edd2d1663f.tex @@ -0,0 +1 @@ +wF_D : (bits(5), bits(64)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzwf_hb915a10402ec9321c4ad1188ae0afc9f.tex b/sail_latex_riscv/valzwf_hb915a10402ec9321c4ad1188ae0afc9f.tex new file mode 100644 index 00000000..c2e16e4a --- /dev/null +++ b/sail_latex_riscv/valzwf_hb915a10402ec9321c4ad1188ae0afc9f.tex @@ -0,0 +1 @@ +wF_H : (bits(5), bits(16)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzwf_s8b4c2b923b5bc2d4c6f88cff982b6695.tex b/sail_latex_riscv/valzwf_s8b4c2b923b5bc2d4c6f88cff982b6695.tex new file mode 100644 index 00000000..caaaa7c3 --- /dev/null +++ b/sail_latex_riscv/valzwf_s8b4c2b923b5bc2d4c6f88cff982b6695.tex @@ -0,0 +1 @@ +wF_S : (bits(5), bits(32)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzzzicondop_of_num6c236bc72d5e4b8fcf599f8f5df132a1.tex b/sail_latex_riscv/valzzzicondop_of_num6c236bc72d5e4b8fcf599f8f5df132a1.tex new file mode 100644 index 00000000..e9a6f091 --- /dev/null +++ b/sail_latex_riscv/valzzzicondop_of_num6c236bc72d5e4b8fcf599f8f5df132a1.tex @@ -0,0 +1 @@ +zicondop_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> zicondop \ No newline at end of file