diff --git a/Makefile b/Makefile
index 38059b80..b290e40a 100644
--- a/Makefile
+++ b/Makefile
@@ -4,7 +4,7 @@ PREVEOUS=../branches/20150624-cheri-architecture-1-13
 
 SAIL_LATEX_RISCV_DIR=sail_latex_riscv
 
-SOURCES=$(wildcard *.tex insn-riscv/*.tex $(SAIL_LATEX_RISCV_DIR)/*.tex cheri_concentrate_listings/*.bsv cheri_concentrate_listings/*.tex) cheri.bib LICENSE LICENSE-sail-cheri-riscv LICENSE-sail-riscv
+SOURCES=$(wildcard *.tex insn-riscv/*.tex insn-x86-64/*.tex $(SAIL_LATEX_RISCV_DIR)/*.tex cheri_concentrate_listings/*.bsv cheri_concentrate_listings/*.tex) cheri.bib LICENSE LICENSE-sail-cheri-riscv LICENSE-sail-riscv
 DIFFDIR=diff
 DIFFTEX=$(SOURCES:%=${DIFFDIR}/%)
 DIFFPARAM=--type=UNDERLINE --packages=amsmath,hyperref --math-markup=1
@@ -67,6 +67,7 @@ diffdir:
 	@(test -d ${DIFFDIR} || mkdir ${DIFFDIR})
 	@(test -d ${DIFFDIR}/cheri_concentrate_listings || mkdir ${DIFFDIR}/cheri_concentrate_listings)
 	@(test -d ${DIFFDIR}/insn-riscv || mkdir ${DIFFDIR}/insn-riscv)
+	@(test -d ${DIFFDIR}/insn-x86-64 || mkdir ${DIFFDIR}/insn-x86-64)
 	@(test -d ${DIFFDIR}/sail_latex_riscv || mkdir ${DIFFDIR}/sail_latex_riscv)
 
 ${DIFFDIR}/$(TARGET): $(DIFFTEX)
diff --git a/chap-intro.tex b/chap-intro.tex
index 0c167b88..02bb9e4f 100644
--- a/chap-intro.tex
+++ b/chap-intro.tex
@@ -757,6 +757,11 @@ \section{Document Structure}
 Chapter~\ref{chap:isaref-riscv} provides a detailed description of each
 CHERI-RISC-V instruction.
 
+\medskip
+\noindent
+Chapter~\ref{chap:isaref-x86-64} provides a detailed description of each
+CHERI-x86-64 instruction.
+
 \medskip
 \noindent
 Chapter~\ref{chap:rationale} discusses the design rationale for many aspects
diff --git a/chap-isaref-x86-64.tex b/chap-isaref-x86-64.tex
new file mode 100644
index 00000000..abaf5eb9
--- /dev/null
+++ b/chap-isaref-x86-64.tex
@@ -0,0 +1,106 @@
+\chapter{The CHERI-x86-64 Instruction-Set Reference}
+\label{chap:isaref-x86-64}
+
+\newcolumntype{Y}{>{\centering\arraybackslash}X}
+\newcolumntype{Z}{>{\raggedright\arraybackslash}X}
+
+\newenvironment{x86opcodetable}{%
+  \tabularx{\textwidth}{| l | l | p{2.0em} | p{2.5em} | p{2.5em} | Z |} \hline
+    \textbf{Opcode} & \textbf{Instruction} & \textbf{Op/ En} &
+    \textbf{Cap Mode} & \textbf{64-bit Mode} & \textbf{Description}\\
+    \hline
+}{%
+  \endtabularx
+}
+
+\newcommand{\xopcode}[6]{%
+  #1 & #2 & #3 & #4 & #5 & #6\\
+  \hline
+}
+
+\newenvironment{x86opentable}{%
+  \bigskip
+  \noindent
+  \tabularx{\textwidth}{| c | Y | Y | Y | Y |}
+    \multicolumn{5}{c}{\bfseries Instruction Operand Encoding}\\
+    \hline
+    Op/En & Operand 1 & Operand 2 & Operand 3 & Operand 4\\
+    \hline
+}{%
+  \endtabularx
+}
+
+\newcommand{\xopen}[5]{%
+  #1 & #2 & #3 & #4 & #5\\
+  \hline
+}
+
+In this chapter, we specify new CHERI instructions as well as
+extensions to existing instructions to support capability-sized
+operands.  Instructions are described using similar syntax to Volume 2
+of Intel's Software Developer's Manual~\cite{intel-sdm-vol2} with a
+few extensions.
+
+An additional symbol is defined to represent object code in the
+``Opcode'' column:
+
+\begin{itemize}
+  \item \textbf{CAP} { }---{ } Indicates the use of the capability
+    operand prefix.
+\end{itemize}
+
+Additional symbols are defined to represent operands in the
+``Instruction'' column:
+
+\begin{itemize}
+  \item \textbf{rc} { }---{ } One of the general-purpose capability
+    registers: \CAX{}, \CBX{}, \CCX{}, \CDX{}, \CDI{}, \CSI{}, \CBP{},
+    \CSP{}, \creg{8}-\creg{15}.
+
+  \item \textbf{r/mc} { }---{ } A capability operand that is either
+    the contents of one of the capability registers for \textbf{rc} or
+    a capability in memory.
+\end{itemize}
+
+In addition, all of these instructions are either invalid or not
+encodable in Compatibility/Legacy mode, so that column is omitted from
+opcode tables.  However, a new column is added to describe capability
+mode support using one of the following annotations:
+
+\begin{itemize}
+  \item \textbf{V} { }---{ } Supported.
+  \item \textbf{I} { }---{ } Not supported.
+\end{itemize}
+
+\clearpage
+\section{Extensions to x86-64 Instructions}
+
+This section contains extensions to existing instructions to support
+capability operands.  For each of these instructions, the instruction
+description should be treated as an extension to the description of
+the existing instruction in Volume 2 of Intel's Software Developer's
+Manual.  Many of the instruction descriptions in this section reuse
+language from Intel's manual to highlight the similarity in semantics
+between the base instructions and their CHERI extensions.
+
+\clearpage
+\section{CHERI-x86-64 Instructions}
+
+This section contains new instructions added to support operations on
+capabilities.  The opcode assignments in this section are tentative
+and subject to change.  Single byte opcodes have been used for
+instructions which we believe may either be used frequently or in
+frequently-accessed code paths.
+
+\clearpage
+\section{Summary of New Opcodes}
+
+The following new opcodes are added in 64-bit mode and are also
+available in capability mode.
+
+\bigskip
+\noindent
+\begin{tabular}{| l | l |} \hline
+  \textbf{Opcode} & \textbf{Instruction}\\
+  \hline
+\end{tabular}
diff --git a/chap-research.tex b/chap-research.tex
index 805db493..f0243b96 100644
--- a/chap-research.tex
+++ b/chap-research.tex
@@ -908,7 +908,7 @@ \section{Protection Model and Architecture}
 specific mapping into the 32-bit and 64-bit RISC-V ISA for the purposes of experimentation
 and evaluation (Chapters~\ref{chap:architecture}, ~\ref{chap:cheri-riscv}
 and~\ref{chap:isaref-riscv}), and architectural sketches for potential integration
-into other ISAs (Chapter~\ref{chap:cheri-x86-64} on CHERI-x86-64 and Arm
+into other ISAs (Chapters~\ref{chap:cheri-x86-64} and~\ref{chap:isaref-x86-64} on CHERI-x86-64 and Arm
 Morello~\cite{arm-morello}).
 However, we have taken a ``ground-up'' approach utilizing hardware-software
 co-design to ensure that concrete mapping exist that
diff --git a/cheri-architecture.tex b/cheri-architecture.tex
index 5c1701c8..88e42e7b 100644
--- a/cheri-architecture.tex
+++ b/cheri-architecture.tex
@@ -137,6 +137,7 @@
 \input{chap-cheri-x86-64}
 \input{chap-sail}
 \input{chap-isaref-riscv}
+\input{chap-isaref-x86-64}
 \input{chap-rationale}
 \input{chap-assurance}
 \input{chap-microarchitecture}
diff --git a/preamble.tex b/preamble.tex
index 7b1c2e48..e3c1231b 100644
--- a/preamble.tex
+++ b/preamble.tex
@@ -10,6 +10,7 @@
 \usepackage{bitset}
 \usepackage{comment}
 \usepackage{graphicx}
+\usepackage{tabularx}
 \usepackage{marginnote}
 \usepackage{booktabs}
 \usepackage{ifthen}
@@ -436,6 +437,8 @@
 \newcommand{\@makeinsncmds}[1]{\@makeinsncmds@explicit{#1}{#1}}
 
 \@makeinsncmds{riscv}
+% Cannot use more intuitive x86 in command names
+\@makeinsncmds{xes}
 
 \newcommand{\definsnarch}[1]{\def\@definsnarch{#1}}
 \@makeinsncmds@explicit{}{\@definsnarch}